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path: root/opcodes/aarch64-dis-2.c
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* aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford2023-03-301-646/+1354
* aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford2023-03-301-521/+699
* aarch64: Add the SME2 maximum/minimum instructionsRichard Sandiford2023-03-301-439/+923
* aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford2023-03-301-445/+644
* aarch64: Add the SME2 ZT0 instructionsRichard Sandiford2023-03-301-386/+516
* aarch64: Add the SME2 predicate-related instructionsRichard Sandiford2023-03-301-789/+1042
* aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford2023-03-301-419/+1831
* aarch64: Add the SME2 MOVA instructionsRichard Sandiford2023-03-301-294/+408
* aarch64: Add support for predicate-as-counter registersRichard Sandiford2023-03-301-1474/+1487
* Update year range in copyright notice of binutils filesAlan Modra2023-01-011-1/+1
* aarch64: Add support for Common Short Sequence Compression extensionAndre Vieira2022-11-141-47/+130
* Arm64: support CLEARBHB aliasJan Beulich2022-10-051-1463/+1464
* aarch64: Add support for new SME instructionsRichard Sandiford2022-01-061-302/+335
* Update year range in copyright notice of binutils filesAlan Modra2022-01-021-1/+1
* aarch64: Add BC instructionRichard Sandiford2021-12-021-47/+58
* aarch64: Add support for +mopsRichard Sandiford2021-12-021-31/+1355
* aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus2021-11-171-189/+235
* aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus2021-11-171-1350/+1356
* aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus2021-11-171-185/+343
* aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus2021-11-171-139/+151
* aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus2021-11-171-171/+200
* aarch64: [SME] Add SME instructionsPrzemyslaw Wirkus2021-11-171-131/+442
* Use bool in opcodesAlan Modra2021-03-311-1/+1
* aarch64: Remove support for CSREKyrylo Tkachov2021-01-111-1290/+1289
* Update year range in copyright notice of binutils filesAlan Modra2021-01-011-1/+1
* aarch64: Limit Rt register number for LS64 load/store instructionsPrzemyslaw Wirkus2020-11-091-84/+85
* [PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7Przemyslaw Wirkus2020-11-031-1820/+1864
* [PATCH][GAS] aarch64: Add WFIT instruction for Armv8.7-aPrzemyslaw Wirkus2020-10-301-1250/+1252
* aarch64: Add CSR PDEC instructionPrzemyslaw Wirkus2020-10-281-1287/+1288
* aarch64: Add WFET instruction for Armv8.7-aPrzemyslaw Wirkus2020-10-281-1250/+1252
* aarch64: Add DSB instruction Armv8.7-a variantPrzemyslaw Wirkus2020-10-281-1305/+1309
* aarch64: Add support for Armv8-R DFB aliasAlex Coplan2020-09-081-1261/+1262
* AArch64: add GAS support for UDF instructionAlex Coplan2020-04-301-1900/+1912
* [AArch64, Binutils] Add missing TSB instructionSudakshina Das2020-04-201-1263/+1265
* [AArch64, Binutils] Make hint space instructions valid for Armv8-aSudakshina Das2020-04-201-1223/+1223
* AArch64: Fix cfinv disassembly issuesTamar Christina2020-01-271-1182/+1182
* Arm64: correct uzp{1,2} mnemonicsJan Beulich2020-01-031-2/+2
* Arm64: correct 64-bit element fmmla encodingJan Beulich2020-01-031-45/+45
* Update year range in copyright notice of binutils filesAlan Modra2020-01-011-1/+1
* [gas][aarch64] Add the v8.6 Data Gathering Hint mnemonic [10/X]Matthew Malcomson2019-11-071-49/+50
* [binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson2019-11-071-424/+733
* [binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson2019-11-071-68/+268
* [gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AESMatthew Malcomson2019-07-011-286/+308
* [binutils][aarch64] Add SVE2 instructions.Matthew Malcomson2019-05-091-941/+4120
* [binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.Matthew Malcomson2019-05-091-11/+12
* [binutils][aarch64] New SVE_Zm4_11_INDEX operand.Matthew Malcomson2019-05-091-7/+8
* [binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.Matthew Malcomson2019-05-091-10/+11
* [binutils][aarch64] New SVE_ADDR_ZX operand.Matthew Malcomson2019-05-091-33/+34
* [binutils][aarch64] New SVE_Zm3_11_INDEX operand.Matthew Malcomson2019-05-091-7/+8
* [binutils][aarch64] Introduce SVE_IMM_ROT3 operand.Matthew Malcomson2019-05-091-19/+20
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