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* [ARM][GAS] ARMv8.2 should enable ARMv8.1 NEON instructions.Matthew Wahab2016-06-302-1/+6
* sparc: make SPARC_OPCODE_ARCH_MAX part of its enumTrevor Saunders2016-06-292-2/+6
* [AArch64] Make register indices be full 64-bit valuesRichard Sandiford2016-06-282-3/+7
* MIPS16: Add R_MIPS16_PC16_S1 branch relocation supportMaciej W. Rozycki2016-06-282-1/+6
* xtensa: prototype xtensa_make_property_section in elf/xtensa.hTrevor Saunders2016-06-252-0/+6
* Add constants for FreeBSD-specific auxiliary vector entry types.John Baldwin2016-06-242-0/+17
* [ARC] Misc minor edits/fixesGraham Markall2016-06-232-3/+7
* addmore extern CTrevor Saunders2016-06-224-0/+30
* tilegx: move TILEGX_NUM_PIPELINE_ENCODINGS to tilegx_pipeline enumTrevor Saunders2016-06-222-3/+6
* Arc assembler: Convert nps400 from a machine type to an extension.Graham Markall2016-06-213-2/+9
* bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine nu...Jose E. Marchesi2016-06-172-0/+13
* Change the size field of MSP430_Opcode_Decoded to a plain integer.John Baldwin2016-06-142-8/+6
* [ARC] Add deep packet inspection instructions for npsGraham Markall2016-06-141-0/+1
* sparc-coff writing uninitialized memoryAlan Modra2016-06-112-0/+12
* sparc: add missing comment about hyperprivileged register operandsJose E. Marchesi2016-06-092-0/+7
* PowerPC VLEAlan Modra2016-06-072-0/+20
* [ARM] Add command line option for RAS extension.Matthew Wahab2016-06-072-3/+10
* Add support for 48 and 64 bit ARC instructions.Andrew Burgess2016-06-022-1/+32
* add more extern CTrevor Saunders2016-06-0111-0/+91
* Return void from linker callbacksAlan Modra2016-05-282-15/+19
* metag: add extern C to headerTrevor Saunders2016-05-262-0/+12
* [ARC] Update instruction type and delay slot info.Claudiu Zissulescu2016-05-232-1/+10
* [ARC] Rename "class" named attributes.Claudiu Zissulescu2016-05-232-2/+8
* tic54x: rename typedef of struct symbol_Trevor Saunders2016-05-232-4/+9
* Add DW_LANG_RustTom Tromey2016-05-172-1/+10
* Add MIPS32 DSPr3 support.Matthew Fortune2016-05-113-1/+9
* Use getters/setters to access ARM branch typeThomas Preud'homme2016-05-102-3/+34
* Add support for ARMv8-M Mainline with DSP extensionThomas Preud'homme2016-05-102-0/+5
* Allow extension availability to depend on several architecture bitsThomas Preud'homme2016-05-102-0/+10
* Add support for ARMv8-M security extensions instructionsThomas Preud'homme2016-05-102-1/+11
* [ARC] Add SYNTAX_NOP and SYNTAX_1OP for extension instructionsClaudiu Zissulescu2016-05-042-2/+18
* Add support to AArch64 disassembler for verifying instructions. Add verifier...Nick Clifton2016-04-282-0/+8
* Cache result of scan for __start_* and __stop_* sectionsAlan Modra2016-04-272-6/+20
* Add support for non-ELF targets to check their relocs.Nick Clifton2016-04-212-0/+9
* Check ELF relocs after opening all input filesH.J. Lu2016-04-202-0/+8
* arc: Fix relocation formula for ARC_NPS_CMEM16 relocationAndrew Burgess2016-04-202-1/+5
* opcodes/arc: Add yet more nps instructionsAndrew Burgess2016-04-192-1/+5
* opcodes/arc: Add more nps instructionsAndrew Burgess2016-04-192-0/+6
* arc/nps400 : New cmem instructions and associated relocationAndrew Burgess2016-04-143-0/+15
* Add support for .extCondCode, .extCoreRegister and .extAuxRegister.Claudiu Zissulescu2016-04-122-3/+32
* Add support for .extInstruction pseudo-op.Claudiu Zissulescu2016-04-122-24/+90
* [ARC] Fix support for double assist instructions.Claudiu Zissulescu2016-04-052-3/+16
* [ARC] 24 bit reloc and overflow detection fix.Claudiu Zissulescu2016-04-052-1/+21
* [ARC] Add support for Quarkse opcodes.Claudiu Zissulescu2016-03-292-0/+89
* make more variables constTrevor Saunders2016-03-223-2/+7
* arc/nps400: Add first nps400 instructionsAndrew Burgess2016-03-212-0/+5
* arc/opcodes: Use flag operand class to handle multiple flag matchesAndrew Burgess2016-03-212-9/+14
* arc: Add nps400 machine type, and assembler flag.Andrew Burgess2016-03-213-0/+7
* arc: Remove EF_ARC_CPU_GENERIC constant.Andrew Burgess2016-03-212-4/+6
* arc: Remove duplicated constant in include/elf/arc.hAndrew Burgess2016-03-212-5/+5
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