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* opcodes: constify aarch64_opcode_tablesMike Frysinger2021-07-011-1/+1
* arm: don't treat XScale features as part of the FPU [PR 28031]Richard Earnshaw2021-07-011-1/+1
* MIPS/opcodes: Properly handle ISA exclusionMaciej W. Rozycki2021-05-291-19/+18
* MIPS/opcodes: Factor out ISA matching against flagsMaciej W. Rozycki2021-05-291-4/+21
* MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki2021-05-291-2/+9
* MIPS/opcodes: Free up redundant `g' operand codeMaciej W. Rozycki2021-05-291-2/+1
* Remove strneq macro and use startswith.Martin Liska2021-04-011-1/+0
* Use bool in includeAlan Modra2021-03-315-46/+45
* Remove bfd_stdint.hAlan Modra2021-03-314-5/+4
* TRUE/FALSE simplificationAlan Modra2021-03-291-7/+5
* opcodes int vs bfd_boolean fixesAlan Modra2021-03-291-1/+1
* RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructionsKuan-Lin Chen2021-03-162-0/+107
* RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu2021-02-191-64/+71
* RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.Nelson Chu2021-02-181-69/+0
* IBM Z: Implement instruction set extensionsAndreas Krebbel2021-02-151-0/+1
* opcodes: tic54x: namespace exported variablesMike Frysinger2021-02-081-4/+4
* RISC-V: PR27348, Remove the obsolete OP_*CUSTOM_IMM.Nelson Chu2021-02-051-2/+0
* RISC-V: PR27348, Remove obsolete Xcustom support.Nelson Chu2021-02-051-72/+0
* RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.Nelson Chu2021-02-042-112/+0
* RISC-V: Indent and GNU coding standards tidy, also aligned the code.Nelson Chu2021-01-151-44/+51
* RISC-V: Comments tidy and improvement.Nelson Chu2021-01-152-31/+17
* aarch64: Remove support for CSREKyrylo Tkachov2021-01-111-2/+0
* RISC-V: Add pause hint instruction.Philipp Tomsich2021-01-072-0/+4
* RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).Claire Xenia Wolf2021-01-072-1/+114
* PR27116, Spelling errors found by Debian style checkerAlan Modra2021-01-011-1/+1
* Update year range in copyright notice of binutils filesAlan Modra2021-01-0169-69/+69
* Constify more arraysAlan Modra2020-12-181-1/+1
* RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.Nelson Chu2020-12-101-0/+4
* RISC-V: Control fence.i and csr instructions by zifencei and zicsr.Nelson Chu2020-12-101-2/+4
* RISC-V: Support to add implicit extensions for G.Nelson Chu2020-12-011-0/+2
* RISC-V: Improve the version parsing for arch string.Nelson Chu2020-12-011-2/+2
* aarch64: Extract Condition flag manipulation feature from Armv8.4-APrzemyslaw Wirkus2020-11-161-1/+3
* Add support for the LMBD (left-most bit detect) instruction to the PRU assemb...Spencer E. Olson2020-11-091-16/+18
* aarch64: Limit Rt register number for LS64 load/store instructionsPrzemyslaw Wirkus2020-11-091-0/+1
* aarch64: Extract Pointer Authentication feature from Armv8.3-APrzemyslaw Wirkus2020-11-061-0/+2
* aarch64: Update feature RAS system registersPrzemyslaw Wirkus2020-11-041-2/+2
* [PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7Przemyslaw Wirkus2020-11-031-1/+3
* aarch64: Add CSR PDEC instructionPrzemyslaw Wirkus2020-10-281-0/+2
* aarch64: Add DSB instruction Armv8.7-a variantPrzemyslaw Wirkus2020-10-281-0/+2
* aarch64: Add basic support for armv8.7-a architecturePrzemyslaw Wirkus2020-10-281-0/+3
* CSKY: Add version flag in eflag and fix bug in disassembling register.Cooper Qu2020-10-261-0/+5
* CSKY: Change ISA flag's type to bfd_uint64_t and fix build error.Cooper Qu2020-09-121-31/+36
* Fix compile time warnings when building for the CSKY target on a 32-bit host.Nick Clifton2020-09-101-1/+1
* CSKY: Change mvtc and mulsw's ISA flag.Cooper Qu2020-09-091-0/+1
* CSKY: Add FPUV3 instructions, which supported by ck860f.Cooper Qu2020-09-091-0/+2
* aarch64: Add support for Armv8-R system registersAlex Coplan2020-09-081-2/+4
* aarch64: Add base support for Armv8-RAlex Coplan2020-09-081-1/+7
* ubsan: v850-opc.c:412 left shift cannot be representedAlan Modra2020-09-021-1/+1
* CSKY: Add CPU CK803r3.Cooper Qu2020-09-021-0/+1
* PR26493 UBSAN: elfnn-riscv.c left shift of negative valueAlan Modra2020-08-311-4/+4
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