| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | PowerPC add initial -mfuture instruction support | Peter Bergner | 2019-05-24 | 1 | -0/+18 |
| * | [PATCH 1/57][Arm][GAS]: Add support for +mve and +mve.fp | Andre Vieira | 2019-05-16 | 1 | -0/+2 |
| * | [binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand. | Matthew Malcomson | 2019-05-09 | 1 | -0/+1 |
| * | [binutils][aarch64] New sve_size_tsz_bhs iclass. | Matthew Malcomson | 2019-05-09 | 1 | -0/+1 |
| * | [binutils][aarch64] New SVE_Zm4_11_INDEX operand. | Matthew Malcomson | 2019-05-09 | 1 | -0/+1 |
| * | [binutils][aarch64] New sve_shift_tsz_bhsd iclass. | Matthew Malcomson | 2019-05-09 | 1 | -0/+1 |
| * | [binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand. | Matthew Malcomson | 2019-05-09 | 1 | -0/+2 |
| * | [binutils][aarch64] New sve_size_013 iclass. | Matthew Malcomson | 2019-05-09 | 1 | -0/+1 |
| * | [binutils][aarch64] New sve_size_bh iclass. | Matthew Malcomson | 2019-05-09 | 1 | -0/+1 |
| * | [binutils][aarch64] New sve_size_sd2 iclass. | Matthew Malcomson | 2019-05-09 | 1 | -0/+1 |
| * | [binutils][aarch64] New SVE_ADDR_ZX operand. | Matthew Malcomson | 2019-05-09 | 1 | -0/+1 |
| * | [binutils][aarch64] New SVE_Zm3_11_INDEX operand. | Matthew Malcomson | 2019-05-09 | 1 | -0/+1 |
| * | [binutils][aarch64] New iclass sve_size_hsd2. | Matthew Malcomson | 2019-05-09 | 1 | -0/+1 |
| * | [binutils][aarch64] Introduce SVE_IMM_ROT3 operand. | Matthew Malcomson | 2019-05-09 | 1 | -0/+1 |
| * | [binutils][aarch64] SVE2 feature extension flags. | Matthew Malcomson | 2019-05-09 | 1 | -0/+7 |
| * | Add load-link, store-conditional paired EVA instructions | Faraz Shahbazker | 2019-05-06 | 1 | -0/+5 |
| * | [BINUTILS, AArch64] Enable Transactional Memory Extension | Sudakshina Das | 2019-05-01 | 1 | -1/+3 |
| * | [MIPS] Add load-link, store-conditional paired instructions | Andrew Bennett | 2019-04-26 | 1 | -0/+4 |
| * | MIPS/include: opcode/mips.h: Update stale comment for CODE20 operand | Maciej W. Rozycki | 2019-04-25 | 1 | -2/+2 |
| * | [binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLI | Andre Vieira | 2019-04-15 | 1 | -0/+6 |
| * | [BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions | Sudakshina Das | 2019-04-11 | 1 | -0/+1 |
| * | [GAS, Arm] CLI with architecture sensitive extensions | Andre Vieira | 2019-04-01 | 1 | -7/+24 |
| * | PR24390, Don't decode mtfsb field as a cr field | Alan Modra | 2019-03-28 | 1 | -1/+4 |
| * | S/390: Implement instruction set extensions | Andreas Krebbel | 2019-01-31 | 1 | -0/+1 |
| * | AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Exte... | Sudi Das | 2019-01-25 | 1 | -2/+0 |
| * | RX: include - Add RXv3 support. | Yoshinori Sato | 2019-01-05 | 1 | -0/+32 |
| * | Update year range in copyright notice of binutils files | Alan Modra | 2019-01-01 | 69 | -69/+69 |
| * | PR24028, PPC_INT_FMT | Alan Modra | 2018-12-28 | 1 | -8/+0 |
| * | PowerPC @l, @h and @ha warnings, plus VLE e_li | Alan Modra | 2018-12-06 | 1 | -0/+5 |
| * | opcodes/riscv: Hide '.L0 ' fake symbols | Andrew Burgess | 2018-12-06 | 1 | -0/+6 |
| * | RISC-V: Accept version, supervisor ext and more than one NSE for -march. | Jim Wilson | 2018-12-03 | 1 | -1/+1 |
| * | RISC-V: Add .insn CA support. | Jim Wilson | 2018-11-27 | 1 | -0/+4 |
| * | [ARM] Improve indentation of ARM architecture declarations | Thomas Preud'homme | 2018-11-13 | 1 | -254/+281 |
| * | [BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension | Sudakshina Das | 2018-11-12 | 1 | -0/+2 |
| * | [BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten... | Sudakshina Das | 2018-11-12 | 1 | -0/+8 |
| * | [BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex... | Sudakshina Das | 2018-11-12 | 1 | -0/+2 |
| * | [BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-A | Sudakshina Das | 2018-11-12 | 1 | -0/+2 |
| * | [BINUTILS, ARM] Add Armv8.5-A to select_arm_features and update macros. | Sudakshina Das | 2018-11-06 | 1 | -4/+3 |
| * | [PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRS | Sudakshina Das | 2018-10-09 | 1 | -1/+4 |
| * | [PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registers | Sudakshina Das | 2018-10-09 | 1 | -1/+8 |
| * | [PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction | Sudakshina Das | 2018-10-09 | 1 | -1/+12 |
| * | [PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructions | Sudakshina Das | 2018-10-09 | 1 | -0/+2 |
| * | [PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instruction | Sudakshina Das | 2018-10-09 | 1 | -1/+4 |
| * | [PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructions | Sudakshina Das | 2018-10-09 | 1 | -1/+6 |
| * | [PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-A | Sudakshina Das | 2018-10-09 | 1 | -1/+4 |
| * | [PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-A | Sudakshina Das | 2018-10-09 | 1 | -1/+8 |
| * | [PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal fea... | Sudakshina Das | 2018-10-09 | 1 | -0/+4 |
| * | [Arm, 3/3] Add Execution and Data Prediction instructions for AArch32 | Sudakshina Das | 2018-10-05 | 1 | -1/+3 |
| * | [Arm, 2/3] Add instruction SB for AArch32 | Sudakshina Das | 2018-10-05 | 1 | -1/+3 |
| * | [Arm, 1/3] Add -march=armv8.5-a and related internal feature macros to AArch32 | Sudakshina Das | 2018-10-05 | 1 | -0/+5 |
