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path: root/include/opcode/riscv-opc.h
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* RISC-V: Support XVentanaCondOps extensionPhilipp Tomsich2023-04-261-0/+8
* Update year range in copyright notice of binutils filesAlan Modra2023-01-011-1/+1
* RISC-V: Fix T-Head Fmv vendor extension encodingChristoph Müllner2022-12-271-2/+2
* riscv: Add AIA extension support (Smaia, Ssaia)Christoph Müllner2022-11-251-0/+68
* RISC-V: Add 'Ssstateen' extension and its CSRsTsukasa OI2022-11-191-13/+13
* RISC-V: Add T-Head Int vendor extensionChristoph Müllner2022-11-171-0/+8
* RISC-V: Add T-Head Fmv vendor extensionChristoph Müllner2022-11-171-0/+8
* RISC-V: Add Zawrs ISA extension supportChristoph Müllner2022-09-231-0/+8
* RISC-V: Add T-Head MemPair vendor extensionChristoph Müllner2022-09-221-0/+17
* RISC-V: Add T-Head MemIdx vendor extensionChristoph Müllner2022-09-221-0/+134
* RISC-V: Add T-Head FMemIdx vendor extensionChristoph Müllner2022-09-221-0/+26
* RISC-V: Add T-Head MAC vendor extensionChristoph Müllner2022-09-221-0/+20
* RISC-V: Add T-Head CondMov vendor extensionChristoph Müllner2022-09-221-0/+8
* RISC-V: Add T-Head Bitmanip vendor extensionChristoph Müllner2022-09-221-0/+39
* RISC-V: Add T-Head SYNC vendor extensionChristoph Müllner2022-09-221-0/+17
* RISC-V: Add T-Head CMO vendor extensionChristoph Müllner2022-09-221-0/+65
* RISC-V: Add 'Sstc' extension and its CSRsTsukasa OI2022-06-281-0/+10
* RISC-V: Add 'Sscofpmf' extension with its CSRsTsukasa OI2022-06-281-0/+62
* RISC-V: Add 'Smstateen' extension and its CSRsTsukasa OI2022-06-281-0/+42
* RISC-V: Use single h extension to control hypervisor CSRs and instructions.Nelson Chu2022-06-221-25/+25
* RISC-V: Remove RV128-only fmv instructionsTsukasa OI2022-05-201-6/+0
* RISC-V: Added half-precision floating-point v1.0 instructions.Nelson Chu2022-05-171-0/+72
* RISC-V: Add missing DECLARE_INSNs for Zicbo{m,p,z}Christoph Muellner2022-04-221-0/+9
* RISC-V: Cache management instructionsTsukasa OI2022-03-181-0/+9
* RISC-V: Prefetch hint instructions and operand setTsukasa OI2022-03-181-0/+7
* RISC-V: Updated CSRs to privileged spec v1.12 and debug spec v1.0.Nelson Chu2022-02-231-34/+49
* RISC-V: Add Privileged Architecture 1.12 CSRsTsukasa OI2022-02-231-0/+138
* Update year range in copyright notice of binutils filesAlan Modra2022-01-021-1/+1
* RISC-V: Hypervisor ext: support Privileged Spec 1.12Vineet Gupta2021-12-241-0/+100
* RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/testsVineet Gupta2021-12-241-20/+0
* RISC-V: Support svinval extension with frozen version 1.0.Nelson Chu2021-12-161-0/+16
* RISC-V: Support rvv extension with released version 1.0.Nelson Chu2021-11-171-0/+1296
* RISC-V: Scalar crypto instructions and operand set.jiawei2021-11-161-0/+75
* RISC-V: Add support for Zbs instructionsPhilipp Tomsich2021-10-071-0/+24
* RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructionsKuan-Lin Chen2021-03-161-0/+104
* RISC-V: PR27348, Remove obsolete Xcustom support.Nelson Chu2021-02-051-72/+0
* RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.Nelson Chu2021-02-041-108/+0
* RISC-V: Comments tidy and improvement.Nelson Chu2021-01-151-8/+8
* RISC-V: Add pause hint instruction.Philipp Tomsich2021-01-071-0/+3
* RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).Claire Xenia Wolf2021-01-071-0/+108
* Update year range in copyright notice of binutils filesAlan Modra2021-01-011-1/+1
* RISC-V: Support debug and float CSR as the unprivileged ones.Nelson Chu2020-06-301-24/+42
* RISC-V: Cleanup the include/opcode/riscv-opc.h.Nelson Chu2020-06-301-33/+26
* RISC-V: Drop the privileged spec v1.9 support.Nelson Chu2020-06-121-218/+217
* [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions...Nelson Chu2020-05-201-261/+248
* RISC-V: Update CSR to privileged spec 1.11.Nelson Chu2020-03-301-6/+19
* RISC-V: Support the ISA-dependent CSR checking.Nelson Chu2020-02-201-244/+244
* RISC-V: Add fence.tso instructionPalmer Dabbelt2018-10-021-0/+2
* RISC-V: Add missing hint instructions from RV128I.Jim Wilson2018-05-081-0/+6
* RISC-V: Add 2 missing privileged registers.Jim Wilson2018-01-041-4/+8
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