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* x86: adjust an ILP32 testcase using .insnJan Beulich2023-04-201-1/+1
* gas: sframe: fix commentIndu Bhagat2023-04-191-1/+1
* gas: sframe: use ATTRIBUTE_UNUSED consistentlyIndu Bhagat2023-04-191-3/+3
* gas: document that get_symbol_name() can clobber the input bufferJan Beulich2023-04-191-5/+10
* x86: parse_register() must not alter the parsed stringJan Beulich2023-04-191-13/+9
* x86: parse_real_register() does not alter the parsed stringJan Beulich2023-04-191-4/+4
* Symbols with GOT relocatios do not fix adjustbalemengqinggang2023-04-184-69/+91
* Assembler Internal Docs: Describe handling of opcodes for relaxation a bit be...Thomas Koenig2023-04-182-3/+10
* arc: Update ARC's CFI tests.Claudiu Zissulescu2023-04-133-11/+16
* arc: Update GAS testClaudiu Zissulescu2023-04-133-8/+5
* Fail of x86_64 AMX-COMPLEX insns (Intel disassembly)Alan Modra2023-04-121-0/+1
* Comment typo fixAlan Modra2023-04-121-1/+1
* x86: Add inval tests for AMX instructionsHaochen Jiang2023-04-107-8/+60
* Support Intel AMX-COMPLEXHaochen Jiang2023-04-0711-1/+104
* gas/write.c use better typesAlan Modra2023-04-061-3/+3
* opcodes/arm: adjust whitespace in cpsie instructionAndrew Burgess2023-04-032-4/+4
* ubsan: aarch64 parse_vector_reg_listAlan Modra2023-04-031-4/+4
* RISC-V: Allocate "various" operand typeTsukasa OI2023-03-311-17/+47
* x86: convert testcases to use .insnJan Beulich2023-03-3139-523/+346
* x86: document .insnJan Beulich2023-03-312-0/+133
* x86: handle immediate operands for .insnJan Beulich2023-03-316-4/+182
* x86: allow for multiple immediates in output_disp()Jan Beulich2023-03-311-5/+5
* x86: handle EVEX Disp8 for .insnJan Beulich2023-03-315-1/+149
* x86: process instruction operands for .insnJan Beulich2023-03-316-21/+432
* x86: parse special opcode modifiers for .insnJan Beulich2023-03-311-1/+38
* x86: parse VEX and alike specifiers for .insnJan Beulich2023-03-315-6/+250
* x86: introduce .insn directiveJan Beulich2023-03-316-10/+213
* aarch64: Add the RPRFM instructionRichard Sandiford2023-03-307-1/+186
* aarch64: Add the SVE FCLAMP instructionRichard Sandiford2023-03-308-1/+102
* aarch64: Add new SVE shift instructionsRichard Sandiford2023-03-307-0/+97
* aarch64: Add new SVE saturating conversion instructionsRichard Sandiford2023-03-307-0/+93
* aarch64: Add new SVE dot-product instructionsRichard Sandiford2023-03-309-12/+186
* aarch64: Add the SVE BFMLSL instructionsRichard Sandiford2023-03-307-0/+143
* aarch64: Add the SME2 UZP and ZIP instructionsRichard Sandiford2023-03-307-0/+352
* aarch64: Add the SME2 UNPK instructionsRichard Sandiford2023-03-307-0/+188
* aarch64: Add the SME2 shift instructionsRichard Sandiford2023-03-3015-3/+384
* aarch64: Add the SME2 saturating conversion instructionsRichard Sandiford2023-03-3014-0/+328
* aarch64: Add the SME2 FP<->FP conversion instructionsRichard Sandiford2023-03-307-0/+102
* aarch64: Add the SME2 FP<->int conversion instructionsRichard Sandiford2023-03-307-0/+245
* aarch64: Add the SME2 CLAMP instructionsRichard Sandiford2023-03-307-0/+407
* aarch64: Add the SME2 MOPA and MOPS instructionsRichard Sandiford2023-03-307-0/+177
* aarch64: Add the SME2 vertical dot-product instructionsRichard Sandiford2023-03-3028-0/+556
* aarch64: Add the SME2 dot-product instructionsRichard Sandiford2023-03-3028-0/+2355
* aarch64: Add the SME2 MLALL and MLSLL instructionsRichard Sandiford2023-03-3022-0/+2317
* aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford2023-03-308-0/+2084
* aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford2023-03-3015-0/+1129
* aarch64: Add the SME2 maximum/minimum instructionsRichard Sandiford2023-03-308-6/+2218
* aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford2023-03-3022-1/+1424
* aarch64: Add the SME2 ZT0 instructionsRichard Sandiford2023-03-3011-12/+746
* aarch64: Add the SME2 predicate-related instructionsRichard Sandiford2023-03-3026-24/+2680
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