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* Re: compress .gnu.debuglto_.debug_* sections if requestedAlan Modra2022-10-041-13/+7
* compress .gnu.debuglto_.debug_* sections if requestedMartin Liska2022-10-041-1/+3
* RISC-V/gas: allow generating up to 176-bit instructions with .insnJan Beulich2022-10-047-10/+82
* RISC-V/gas: don't open-code insn_length()Jan Beulich2022-10-041-1/+1
* RISC-V/gas: drop stray call to install_insn()Jan Beulich2022-10-041-1/+0
* RISC-V/gas: drop riscv_subsets static variableJan Beulich2022-10-041-18/+14
* RISC-V: don't cast expressions' X_add_number to long in diagnosticsJan Beulich2022-10-041-4/+4
* RISC-V: Assign DWARF numbers to vector registersTsukasa OI2022-10-033-2/+73
* RISC-V: Add testcase for DWARF register numbersTsukasa OI2022-10-032-0/+296
* RISC-V: Relax "fmv.[sdq]" requirementsTsukasa OI2022-09-306-0/+6
* RISC-V: Reorganize and enhance 'Zfinx' testsTsukasa OI2022-09-306-106/+207
* RISC-V: Eliminate long-casts of X_add_number in diagnosticsChristoph Müllner2022-09-301-8/+8
* RISC-V: fallout from "re-arrange opcode table for consistent alias handling"Jan Beulich2022-09-304-14/+14
* RISC-V: fix build after "Add support for arbitrary immediate encoding formats"Jan Beulich2022-09-301-4/+4
* RISC-V: drop stray INSN_ALIAS flagsJan Beulich2022-09-302-0/+35
* RISC-V: re-arrange opcode table for consistent alias handlingJan Beulich2022-09-3021-159/+375
* x86: improve match_template()'s diagnosticsJan Beulich2022-09-307-67/+86
* x86/Intel: restrict suffix derivationJan Beulich2022-09-306-61/+230
* LoongArch: Update ELF e_flags handling according to specification.liuzhensong2022-09-301-10/+10
* The help document of as misses some many optionsNick Clifton2022-09-284-34/+90
* binutils, gdb: support zstd compressed debug sectionsFangrui Song2022-09-2612-47/+380
* RISC-V: Add Zawrs ISA extension supportChristoph Müllner2022-09-233-0/+25
* RISC-V: Add T-Head MemPair vendor extensionChristoph Müllner2022-09-226-0/+88
* RISC-V: Add support for literal instruction argumentsChristoph Müllner2022-09-221-0/+10
* RISC-V: Add T-Head MemIdx vendor extensionChristoph Müllner2022-09-226-0/+137
* RISC-V: Add T-Head FMemIdx vendor extensionChristoph Müllner2022-09-226-0/+85
* RISC-V: Add T-Head MAC vendor extensionChristoph Müllner2022-09-223-0/+27
* RISC-V: Add T-Head CondMov vendor extensionChristoph Müllner2022-09-223-0/+19
* RISC-V: Add T-Head Bitmanip vendor extensionChristoph Müllner2022-09-2216-0/+141
* RISC-V: Add support for arbitrary immediate encoding formatsChristoph Müllner2022-09-221-0/+74
* RISC-V: Add T-Head SYNC vendor extensionChristoph Müllner2022-09-226-0/+40
* RISC-V: Add T-Head CMO vendor extensionChristoph Müllner2022-09-226-0/+103
* RISC-V: Add generic support for vendor extensionsChristoph Müllner2022-09-221-0/+14
* RISC-V: Add macro-only operands to validate_riscv_insnTsukasa OI2022-09-221-0/+3
* RISC-V: Fix riscv_set_tso declarationTsukasa OI2022-09-211-1/+1
* RISC-V: Set EF_RISCV_TSO also on .option archTsukasa OI2022-09-211-0/+3
* RISC-V: Implement Ztso extensionShihua2022-09-212-0/+19
* RISC-V: Always generate R_RISCV_CALL_PLT reloc for call in assembler.Nelson Chu2022-09-213-8/+4
* Re: PowerPC64 pcrel got relocs against local symbolsAlan Modra2022-09-211-6/+52
* ppc/svp64: test setvl ms operandDmitry Selyutin2022-09-212-0/+2
* LoongArch: Set macro SUB_SEGMENT_ALIGN to 0.liuzhensong2022-09-201-0/+2
* PowerPC64 pcrel got relocs against local symbolsAlan Modra2022-09-161-0/+6
* RISC-V: Make g imply zmmul extension.Nelson Chu2022-09-168-8/+8
* bfd, binutils, gas: Remove/mark unused variablesTsukasa OI2022-09-151-3/+0
* bfd: Stop using -Wstack-usage=262144 when built with ClangTsukasa OI2022-09-141-0/+18
* ppc: Document the -mfuture and -Mfuture options and make them usablePeter Bergner2022-09-122-0/+5
* Re: PR29466, APP/NO_APP with linefileAlan Modra2022-09-101-1/+1
* RISC-V: Fix vector CSR requirementsTsukasa OI2022-09-095-57/+57
* Gas generated incorrect debug info (top-level DW_TAG_unspecified_type DIE)Nick Clifton2022-09-086-30/+50
* LoongArch: fix gas BFD_RELOC_8/16/24 bugmengqinggang2022-09-073-18/+58
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