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* gas: merge doc subdir up a levelMike Frysinger2021-12-016-1163/+671
| | | | | This avoids a recursive make into the doc subdir and speeds up the build slightly. It also allows for more parallelism.
* aarch64: Add missing system registers [PR27145]Richard Sandiford2021-11-3010-6/+877
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for various system registers, up to Armv8.7-A. This includes all the registers that were mentioned in the PR and that hadn't become supported since. opcodes/ PR aarch64/27145 * aarch64-opc.c (SR_V8_4): Remove duplicate definition. (SR_V8_6, SR_V8_7, SR_GIC, SR_AMU): New macros. (aarch64_sys_regs): Add missing entries (up to Armv8.7-A). gas/ PR aarch64/27145 * testsuite/gas/aarch64/sysreg-8.s, * testsuite/gas/aarch64/sysreg-8.d, * testsuite/gas/aarch64/illegal-sysreg-8.s, * testsuite/gas/aarch64/illegal-sysreg-8.d, * testsuite/gas/aarch64/illegal-sysreg-8.l, * testsuite/gas/aarch64/illegal-sysreg-8b.s, * testsuite/gas/aarch64/illegal-sysreg-8b.d, * testsuite/gas/aarch64/illegal-sysreg-8b.l: New tests. * testsuite/gas/aarch64/sysreg.s: Change system register numbers to ones that are still unallocated. * testsuite/gas/aarch64/sysreg.d: Update accordingly.
* aarch64: Make LOR registers conditional on +lorRichard Sandiford2021-11-304-1/+13
| | | | | | | | | | | | | | | | | We have a +lor feature flag for the Limited Ordering Regions extension, but the associated registers didn't use it. opcodes/ * aarch64-opc.c (SR_LOR): New macro. (aarch64_sys_regs): Use it for lorc_el1, lorea_el1, lorn_el1 and lorsa_el1. gas/ * testsuite/gas/aarch64/sysreg-7.s: Enable +lor. * testsuite/gas/aarch64/illegal-sysreg-7.s: Test for LOR registers without +lor. * testsuite/gas/aarch64/illegal-sysreg-7.d: Update accordingly. * testsuite/gas/aarch64/illegal-sysreg-7.l: Likewise.
* aarch64: Remove ZIDR_EL1Richard Sandiford2021-11-303-7/+0
| | | | | | | | | | | | | ZIDR_EL1 was part of an early version of SVE, but didn't make it to the final release. opcodes/ * aarch64-opc.c (aarch64_sys_regs): Remove zidr_el1 entry. gas/ * testsuite/gas/aarch64/sve-sysreg.s: Remove zidr_el1. * testsuite/gas/aarch64/sve-sysreg.d: Update accordingly. * testsuite/gas/aarch64/sve-sysreg-invalid.l: Likewise.
* aarch64: Allow writes to MFAR_EL3Richard Sandiford2021-11-305-20/+13
| | | | | | | | | | | | | | | | MFAR_EL3 is a read/write register, but was incorrectly marked as read-only [https://developer.arm.com/documentation/ddi0601/2021-09/AArch64-Registers/MFAR-EL3--PA-Fault-Address-Register?lang=en] opcodes/ * aarch64-opc.c (aarch64_sys_regs): Mark mfar_el3 as read-write. gas/ * testsuite/gas/aarch64/rme.s: Test writing to mfar_el3. * testsuite/gas/aarch64/rme.d: Update accordingly. * testsuite/gas/aarch64/rme-invalid.s: Delete. * testsuite/gas/aarch64/rme-invalid.l: Likewise. * testsuite/gas/aarch64/rme-invalid.d: Likewise.
* aarch64: Mark PMSIDR_EL1 as read-onlyRichard Sandiford2021-11-305-3/+8
| | | | | | | | | | | | | | | | We were incorrectly allowing writes to PMSIDR_EL1, which is a read-only register. [https://developer.arm.com/documentation/ddi0595/2021-09/AArch64-Registers/PMSIDR-EL1--Sampling-Profiling-ID-Register?lang=en] opcodes/ * aarch64-opc.c (aarch64_sys_regs): Make pmsidr_el1 as F_REG_READ. gas/ * testsuite/gas/aarch64/msr.s: Remove write to pmsidr_el1. * testsuite/gas/aarch64/msr.d: Update accordingly. * testsuite/gas/aarch64/illegal-sysreg-2.s, * testsuite/gas/aarch64/illegal-sysreg-2.d, * testsuite/gas/aarch64/illegal-sysreg-2.l: New test.
* aarch64: Remove duplicate system register entriesRichard Sandiford2021-11-302-4/+0
| | | | | | | | | | | | | | | There is a lot of overlap between the ETM and ETE system registers, so some registers were listed twice. Already tested by etm.[sd] and ete.[sd]. opcodes/ * aarch64-opc.c (aarch64_sys_regs): Combine ETE and ETM blocks and remove redundant entries. gas/ * testsuite/gas/aarch64/etm.s: Remove duplicated test. * testsuite/gas/aarch64/etm.d: Update accordingly.
* aarch64: Check for register aliases before mnemonicsRichard Sandiford2021-11-306-34/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we would not accept: A .req B if A happened to be the name of an instruction. Adding new instructions could therefore invalidate existing register aliases. I noticed this with a test that used "zero" as a register alias for "xzr", where "zero" is now also the name of an SME instruction. I don't have any evidence that "real" code is doing this, but it seems at least plausible. This patch switches things so that we check for register aliases first. It might slow down parsing slightly, but the difference is unlikely to be noticeable. Things like: b .req + 0 still work, since create_register_alias checks for " .req ", and with the input scrubber, we'll only keep whitespace after .req if it's followed by another name. If there's some valid expression that I haven't thought about that is scrubbed to " .req ", users could avoid the ambiguity by wrapping .req in parentheses. The new test for invalid aliases already passed. I just wanted something to exercise the !dot condition. I can't find a way of exercising the (existing) p == base condition, but I'm not brave enough to say that it can never happen. If it does happen, get_mnemonic_name would return an empty string. gas/ * config/tc-aarch64.c (opcode_lookup): Move mnemonic extraction code to... (md_assemble): ...here. Check for register aliases first. * testsuite/gas/aarch64/register_aliases.d, testsuite/gas/aarch64/register_aliases.s: Test for a register alias called "zero". * testsuite/gas/aarch64/register_aliases_invalid.d, testsuite/gas/aarch64/register_aliases_invalid.l, testsuite/gas/aarch64/register_aliases_invalid.s: New test.
* RISC-V: The vtype immediate with more than the defined 8 bits are preserved.Nelson Chu2021-11-302-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According the rvv spec, https://github.com/riscv/riscv-v-spec/blob/master/vtype-format.adoc The bits of vtype immediate from 8 to (xlen - 1) should be reserved. Therefore, we should also dump the vtype immediate as numbers, when they are set over 8-bits. I think this is a bug that we used to support vediv extension and use the bit 8 and 9 of vtype, but forgot to update the behavior when removing the vediv. Consider the testcases, vsetvli a0, a1, 0x700 # the reserved bit 10, 9 and 8 are used. vsetvli a0, a1, 0x400 # the reserved bit 10 is used. vsetvli a0, a1, 0x300 # the reserved bit 9 and 8 are used. vsetvli a0, a1, 0x100 # the reserved bit 8 is used. vsetivli a0, 0xb, 0x300 # the reserved bit 9 and 8 are used. vsetivli a0, 0xb, 0x100 # the reserved bit 8 is used. The original objdump shows the following result, 0000000000000000 <.text>: 0: 7005f557 vsetvli a0,a1,1792 4: 4005f557 vsetvli a0,a1,1024 8: 3005f557 vsetvli a0,a1,e8,m1,tu,mu c: 1005f557 vsetvli a0,a1,e8,m1,tu,mu 10: f005f557 vsetivli a0,11,e8,m1,tu,mu 14: d005f557 vsetivli a0,11,e8,m1,tu,mu But in fact the correct result should be, 0000000000000000 <.text>: 0: 7005f557 vsetvli a0,a1,1792 4: 4005f557 vsetvli a0,a1,1024 8: 3005f557 vsetvli a0,a1,768 c: 1005f557 vsetvli a0,a1,256 10: f005f557 vsetivli a0,11,768 14: d005f557 vsetivli a0,11,256 gas/ * testsuite/gas/riscv/vector-insns.d: Added testcases to test the reserved bit 8 to (xlen-1) of vtype. * testsuite/gas/riscv/vector-insns.s: Likewise. include/ * opcode/riscv.h: Removed OP_MASK_VTYPE_RES and OP_SH_VTYPE_RES, since they are different for operand Vc and Vb. opcodes/ * riscv-dis.c (print_insn_args): Updated imm_vtype_res to extract the reserved immediate of vtype correctly.
* RISC-V: Dump vset[i]vli immediate as numbers once vsew or vlmul is reserved.Nelson Chu2021-11-302-68/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Consider the following case, vsetvli a0, a1, 0x4 # unrecognized vlmul vsetvli a0, a1, 0x20 # unrecognized vsew vsetivli a0, 0xb, 0x4 # unrecognized vlmul vsetivli a0, 0xb, 0x20 # unrecognized vsew For the current dis-assembler, we get the result, 0000000000000000 <.text>: 0: 0045f557 vsetvli a0,a1,e8,(null),tu,mu 4: 0205f557 vsetvli a0,a1,e128,m1,tu,mu 8: c045f557 vsetivli a0,11,e8,(null),tu,mu c: c205f557 vsetivli a0,11,e128,m1,tu,mu The vsew e128 and vlmul (null) are preserved according to the spec, so dump these fields looks wrong. Consider that we are used to dump the unrecognized csr as csr numbers directly, we should also dump the whole vset[i]vli immediates as numbers, once the vsew or vlmul is reserved. Therefore, following is what I expected, 0000000000000000 <.text>: 0: 0045f557 vsetvli a0,a1,4 4: 0205f557 vsetvli a0,a1,32 8: c045f557 vsetivli a0,11,4 c: c205f557 vsetivli a0,11,32 gas/ * testsuite/gas/riscv/vector-insns.d: Rewrite the vset[i]vli testcases since we should dump the immediate as numbers once the vsew or vlmul is reserved. * testsuite/gas/riscv/vector-insns.s: Likewise. opcodes/ * riscv-dis.c (print_insn_args): The reserved vsew and vlmul are NULL string in the riscv_vsew and riscv_vlmul, so dump the whole imm as numbers once one of them is NULL. * riscv-opc.c (riscv_vsew): Set the reserved vsew to NULL. (riscv_vlmul): Set the reserved vlmul to NULL.
* PR28629 NIOS2 falloutAlan Modra2021-11-291-1/+1
| | | | | | | The test exactly matched wrong output. PR 28629 * testsuite/gas/nios2/relax.d: Update expected output.
* gas: Update commit 4780e5e4933H.J. Lu2021-11-262-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update commit 4780e5e4933a2497a5aecc4ceabbbb8e82aaf822 Author: Tom de Vries <tdevries@suse.de> Date: Fri Nov 26 09:59:45 2021 +0100 [gas] Fix file 0 dir with -gdwarf-5 1. Replace i with j in for (j = 0; i < NUM_MD5_BYTES; ++j) 2. Pass -W to readelf to force CU: in output due to: if (do_wide || strlen (directory) < 76) printf (_("CU: %s/%s:\n"), directory, file_table[0].name); else printf ("%s:\n", file_table[0].name); PR gas/28629 * dwarf2dbg.c (out_dir_and_file_list): Fix a typo in commit 4780e5e4933. * testsuite/gas/elf/dwarf-5-nop-for-line-table.d: Pass -W to readelf.
* [gas] Fix file 0 dir with -gdwarf-5Tom de Vries2021-11-263-3/+16
| | | | | | | | | | | | | | | | In out_dir_and_file_list, if file 0 is copied from file 1, only the filename is copied, and the dir and md5 fields are left to their default values. Fix this by adding the copy of the dir and md5 fields. gas/ChangeLog: 2021-11-26 Tom de Vries <tdevries@suse.de> PR 28629 * dwarf2dbg.c (out_dir_and_file_list): When copying file 1 to file 0, also copy dir and md5 fields. * testsuite/gas/i386/dwarf5-line-4.d: Adjust expected output.
* gas: enable silent build rulesMike Frysinger2021-11-252-2/+42
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* Update bug reporting addressAlan Modra2021-11-232-6/+2
| | | | | | | | | | | | | | | | | | | | | | | https://sourceware.org/bugzilla/ everywhere bfd/ * configure.ac (ACX_BUGURL): Set to https://sourceware.org/bugzilla/ * po/Make-in (msgid-bugs-address): Likewise. * README: Report bugs to the above. * configure: Regenerate. binutils/ * po/Make-in (msgid-bugs-address): Update. gas/ * README: Update bug address. Delete mention of gcc. * po/Make-in: Update bug address. gold/ * po/Make-in: Update bug address. gprof/ * po/Make-in: Update bug address. ld/ * po/Make-in: Update bug address. opcodes/ * po/Make-in: Update bug address.
* RISC-V: Replace .option rvc/norvc with .option arch, +c/-c.Nelson Chu2021-11-2216-18/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | Since the .option rvc/norvc directives are obsolete, replace them with the new proposed diretives: .option arch, +c/-c. And also reset the riscv_opts.rvc flag for the .option arch directives. gas/ * config/tc-riscv.c (s_riscv_option): Reset the riscv_opts.rvc for the .option arch directives. * testsuite/gas/riscv/align-1.s: Replace the obsolete .option rvc/norvc with .option arch, +c/-c. * testsuite/gas/riscv/c-add-addi.s: Likewise. * testsuite/gas/riscv/c-nonzero-imm.s: Likewise. * testsuite/gas/riscv/c-nonzero-reg.s: Likewise. * testsuite/gas/riscv/c-zero-imm-64.s: Likewise. * testsuite/gas/riscv/c-zero-imm.s: Likewise. * testsuite/gas/riscv/c-zero-reg.s: Likewise. * testsuite/gas/riscv/ext.s: Likewise. * testsuite/gas/riscv/mapping-01.s: Likewise. * testsuite/gas/riscv/mapping-02.s: Likewise. * testsuite/gas/riscv/mapping-03.s: Likewise. * testsuite/gas/riscv/mapping-04.s: Likewise. * testsuite/gas/riscv/no-relax-align-2.s: Likewise. * testsuite/gas/riscv/shamt-32.s: Likewise. * testsuite/gas/riscv/shamt-64.s: Likewise.
* RISC-V: Support new .option arch directive.Nelson Chu2021-11-1912-18/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://github.com/riscv/riscv-asm-manual/pull/67 Format: .option arch, +<extension><version>, ... .option arch, -<extension> .option arch, =<ISA string> The new direcitve is used to enable/disable extensions for the specific code region. For example, .attribute arch, "rv64ic" # arch = rv64i2p0_c2p0 .option push .option arch, +d2p0, -c # arch = rv64i2p0_f2p0_d2p0, f is added implied .option arch, =rv32gc # arch = rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0 .option pop # arch = rv64i2p0_c2p0 Note that, 1. ".option rvc/norvc" have the same behavior as ".option arch +c/-c". 2. ".option arch -i" is illegal, since we cannot remove base i extension. 3. If arch=rv64i2p0, then ".option arch, +i3p0" will update the i's version from 2.0 to 3.0. 4. If arch=rv64i3p0, then ".option arch, +i" will update the i's version from 2.0 to the default one according to the chosen isa spec. bfd/ * elfxx-riscv.c (riscv_add_subset): If the subset is already added, and the new versions are not RISCV_UNKNOWN_VERSION, then update the versions to the subset list. (riscv_copy_subset): New function. Copy the subset from list. (riscv_copy_subset_list): New function. Return the new copyed list. (riscv_update_subset): Updated to make .option arch directives workable. * elfxx-riscv.h: Updated. gas/ * config/tc-riscv.c (riscv_subsets): Defined as a pointer. (riscv_rps_as): Init the subset_list to NULL, we will set it later once riscv_opts_stack is created or updated. (struct riscv_option_stack, riscv_opts_stack): Moved forward. (riscv_set_arch): Updated. (s_riscv_option): Support new .option arch directive, to add, remove or update subsets for the specific code region. (riscv_write_out_attrs): Updated. * doc/c-riscv.texi: Added document for new .option arch directive. * testsuite/gas/riscv/option-arch-01a.d: New testcase. * testsuite/gas/riscv/option-arch-01b.d: Likewise. * testsuite/gas/riscv/option-arch-01.s: Likewise.. * testsuite/gas/riscv/option-arch-02.d: Likewise. * testsuite/gas/riscv/option-arch-02.s: Likewise. * testsuite/gas/riscv/option-arch-fail.d: Likewise. * testsuite/gas/riscv/option-arch-fail.l: Likewise. * testsuite/gas/riscv/option-arch-fail.s: Likewise.
* Re: Add multibyte character warning option to the assembler.Alan Modra2021-11-191-10/+10
| | | | | | | | On hppa*-hp-hpux* run_dump_test edits the test file, adjusting .comm directives to suit those target's unusual syntax. Thus gas is passed a temporary file name. * testsuite/gas/all/multibyte1.l: Ignore file name.
* RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC.Nelson Chu2021-11-196-0/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the original discussion, https://github.com/riscv/riscv-elf-psabi-doc/pull/190 And here is the glibc part, https://sourceware.org/pipermail/libc-alpha/2021-August/129931.html For binutils part, we need to support a new direcitve: .variant_cc. The function symbol marked by .variant_cc means it need to be resolved directly without resolver for dynamic linker. We also add a new dynamic entry, STO_RISCV_VARIANT_CC, to indicate there are symbols with the special attribute in the dynamic symbol table of the object. I heard that llvm already have supported this in their mainline, so I think it's time to commit this. bfd/ * elfnn-riscv.c (riscv_elf_link_hash_table): Added variant_cc flag. It is used to check if relocations for variant CC symbols may be present. (allocate_dynrelocs): If the symbol has STO_RISCV_VARIANT_CC flag, then raise the variant_cc flag of riscv_elf_link_hash_table. (riscv_elf_size_dynamic_sections): Added dynamic entry for variant_cc. (riscv_elf_merge_symbol_attribute): New function, used to merge non-visibility st_other attributes, including STO_RISCV_VARIANT_CC. binutils/ * readelf.c (get_riscv_dynamic_type): New function. (get_dynamic_type): Called get_riscv_dynamic_type for riscv targets. (get_riscv_symbol_other): New function. (get_symbol_other): Called get_riscv_symbol_other for riscv targets. gas/ * config/tc-riscv.c (s_variant_cc): Marked symbol that it follows a variant CC convention. (riscv_elf_copy_symbol_attributes): Same as elf_copy_symbol_attributes, but without copying st_other. If a function symbol has special st_other value set via directives, then attaching an IFUNC resolver to that symbol should not override the st_other setting. (riscv_pseudo_table): Support variant_cc diretive. * config/tc-riscv.h (OBJ_COPY_SYMBOL_ATTRIBUTES): Defined. * testsuite/gas/riscv/variant_cc-set.d: New testcase. * testsuite/gas/riscv/variant_cc-set.s: Likewise. * testsuite/gas/riscv/variant_cc.d: Likewise. * testsuite/gas/riscv/variant_cc.s: Likewise. include/ * elf/riscv.h (DT_RISCV_VARIANT_CC): Defined to (DT_LOPROC + 1). (STO_RISCV_VARIANT_CC): Defined to 0x80. ld/ * testsuite/ld-riscv-elf/variant_cc-1.s: New testcase. * testsuite/ld-riscv-elf/variant_cc-2.s: Likewise. * testsuite/ld-riscv-elf/variant_cc-now.d: Likewise. * testsuite/ld-riscv-elf/variant_cc-r.d: Likewise. * testsuite/ld-riscv-elf/variant_cc-shared.d: Likewise. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
* Add multibyte character warning option to the assembler.Nick Clifton2021-11-1814-10/+205
| | | | | | | | | | | | | | | | | | | | | | * as.c (parse_args): Add support for --multibyte-handling. * as.h (multibyte_handling): Declare. * app.c (scan_for_multibyte_characters): New function. (do_scrub_chars): Call the new function if multibyte warning is enabled. * input-scrub,c (input_scrub_next_buffer): Call the multibyte scanning function if multibyte warnings are enabled. * symbols.c (struct symbol_flags): Add multibyte_warned bit. (symbol_init): Call the multibyte scanning function if multibyte symbol warnings are enabled. (S_SET_SEGMENT): Likewise. * NEWS: Mention the new feature. * doc/as.texi: Document the new feature. * testsuite/gas/all/multibyte.s: New test source file. * testsuite/gas/all/multibyte1.d: New test driver file. * testsuite/gas/all/multibyte1.l: New test expected output. * testsuite/gas/all/multibyte2.d: New test driver file. * testsuite/gas/all/multibyte2.l: New test expected output. * testsuite/gas/all/gas.exp: Run the new tests.
* RISC-V: Add testcases for z[fdq]inxjiawei2021-11-186-0/+222
| | | | | | | | | | | | | | | | Use gpr when the zfinx enable, the testcases contain float instructions that reuse by z[fdq]inx. gas/ChangeLog: * testsuite/gas/riscv/zdinx.d: New test. * testsuite/gas/riscv/zdinx.s: New test. * testsuite/gas/riscv/zfinx.d: New test. * testsuite/gas/riscv/zfinx.s: New test. * testsuite/gas/riscv/zqinx.d: New test. * testsuite/gas/riscv/zqinx.s: New test. Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
* RISC-V: Add instructions and operand set for z[fdq]inxjiawei2021-11-181-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Reuse float instructions in INSN_CLASS_F/D/Q, use riscv_subset_supports to verify if z*inx enabled and use gpr instead of fpr when z*inx is enable. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Added support for z*inx extension. gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Added register choice for z*inx. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Reused INSN_CLASS_* for z*inx. opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Added disassemble check for z*inx. * riscv-opc.c: Reused INSN_CLASS_* for z*inx. Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
* aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus2021-11-176-0/+348
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is adding new SVE2 instructions added to support SME extension. The following SVE2 instructions are added by the SME architecture: * PSEL, * REVD, SCLAMP and UCLAMP. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_pred_reg_with_index): New parser. (parse_operands): New parser. * testsuite/gas/aarch64/sme-9-illegal.d: New test. * testsuite/gas/aarch64/sme-9-illegal.l: New test. * testsuite/gas/aarch64/sme-9-illegal.s: New test. * testsuite/gas/aarch64/sme-9.d: New test. * testsuite/gas/aarch64/sme-9.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_SME_PnT_Wm_imm. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_sme_pred_reg_with_index): New inserter. * aarch64-dis.c (aarch64_ext_sme_pred_reg_with_index): New extractor. * aarch64-opc.c (aarch64_print_operand): Printout of OPND_SME_PnT_Wm_imm. * aarch64-opc.h (enum aarch64_field_kind): New bitfields FLD_SME_Rm, FLD_SME_i1, FLD_SME_tszh, FLD_SME_tszl. * aarch64-tbl.h (OP_SVE_NN_BHSD): New qualifier. (OP_SVE_QMQ): New qualifier. (struct aarch64_opcode): New instructions PSEL, REVD, SCLAMP and UCLAMP. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
* aarch64: [SME] Add new SME system registersPrzemyslaw Wirkus2021-11-175-0/+61
| | | | | | | | | | | | | | | | | | This patch is adding miscellaneous SME related system registers. gas/ChangeLog: * testsuite/gas/aarch64/sme-sysreg.d: New test. * testsuite/gas/aarch64/sme-sysreg.s: New test. * testsuite/gas/aarch64/sme-sysreg-illegal.d: New test. * testsuite/gas/aarch64/sme-sysreg-illegal.l: New test. * testsuite/gas/aarch64/sme-sysreg-illegal.s: New test. opcodes/ChangeLog: * aarch64-opc.c: New system registers id_aa64smfr0_el1, smcr_el1, smcr_el12, smcr_el2, smcr_el3, smpri_el1, smprimap_el2, smidr_el1, tpidr2_el0 and mpamsm_el1.
* aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus2021-11-176-8/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is adding new SME mode selection and state access instructions: * Add SMSTART and SMSTOP instructions. * Add SVCR system register. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_sm_za): New parser. (parse_operands): New parser. * testsuite/gas/aarch64/sme-8-illegal.d: New test. * testsuite/gas/aarch64/sme-8-illegal.l: New test. * testsuite/gas/aarch64/sme-8-illegal.s: New test. * testsuite/gas/aarch64/sme-8.d: New test. * testsuite/gas/aarch64/sme-8.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_SME_SM_ZA. (enum aarch64_insn_class): New instruction classes sme_start and sme_stop. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_pstatefield): New inserter. (aarch64_ins_sme_sm_za): New inserter. * aarch64-dis.c (aarch64_ext_imm): New extractor. (aarch64_ext_pstatefield): New extractor. (aarch64_ext_sme_sm_za): New extractor. * aarch64-opc.c (operand_general_constraint_met_p): New pstatefield value for SME instructions. (aarch64_print_operand): Printout for OPND_SME_SM_ZA. (SR_SME): New register SVCR. * aarch64-opc.h (F_REG_IN_CRM): New register endcoding. * aarch64-opc.h (F_IMM_IN_CRM): New immediate endcoding. (PSTATE_ENCODE_CRM): Encode CRm field. (PSTATE_DECODE_CRM): Decode CRm field. (PSTATE_ENCODE_CRM_IMM): Encode CRm immediate field. (PSTATE_DECODE_CRM_IMM): Decode CRm immediate field. (PSTATE_ENCODE_CRM_AND_IMM): Encode CRm and immediate field. * aarch64-tbl.h (struct aarch64_opcode): New SMSTART and SMSTOP instructions. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
* aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus2021-11-1716-8/+801
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is adding new loads and stores defined by SME instructions. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_address): New parser. (parse_sme_za_hv_tiles_operand_with_braces): New parser. (parse_sme_za_array): New parser. (output_operand_error_record): Print error details if present. (parse_operands): Support new operands. * testsuite/gas/aarch64/sme-5-illegal.d: New test. * testsuite/gas/aarch64/sme-5-illegal.l: New test. * testsuite/gas/aarch64/sme-5-illegal.s: New test. * testsuite/gas/aarch64/sme-5.d: New test. * testsuite/gas/aarch64/sme-5.s: New test. * testsuite/gas/aarch64/sme-6-illegal.d: New test. * testsuite/gas/aarch64/sme-6-illegal.l: New test. * testsuite/gas/aarch64/sme-6-illegal.s: New test. * testsuite/gas/aarch64/sme-6.d: New test. * testsuite/gas/aarch64/sme-6.s: New test. * testsuite/gas/aarch64/sme-7-illegal.d: New test. * testsuite/gas/aarch64/sme-7-illegal.l: New test. * testsuite/gas/aarch64/sme-7-illegal.s: New test. * testsuite/gas/aarch64/sme-7.d: New test. * testsuite/gas/aarch64/sme-7.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operands. (enum aarch64_insn_class): Added sme_ldr and sme_str. (AARCH64_OPDE_UNTIED_IMMS): New operand error kind. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_sme_za_hv_tiles): New inserter. (aarch64_ins_sme_za_list): New inserter. (aarch64_ins_sme_za_array): New inserter. (aarch64_ins_sme_addr_ri_u4xvl): New inserter. * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): Added ins_sme_za_list, ins_sme_za_array and ins_sme_addr_ri_u4xvl. * aarch64-dis.c (aarch64_ext_sme_za_hv_tiles): New extractor. (aarch64_ext_sme_za_list): New extractor. (aarch64_ext_sme_za_array): New extractor. (aarch64_ext_sme_addr_ri_u4xvl): New extractor. * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): Added ext_sme_za_list, ext_sme_za_array and ext_sme_addr_ri_u4xvl. * aarch64-opc.c (operand_general_constraint_met_p): (aarch64_match_operands_constraint): Handle sme_ldr, sme_str and sme_misc. (aarch64_print_operand): New operands supported. * aarch64-tbl.h (OP_SVE_QUU): New qualifier. (OP_SVE_QZU): New qualifier. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
* aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus2021-11-176-0/+334
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is adding ZERO (a list of 64-bit element ZA tiles) instruction. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_list_of_64bit_tiles): New parser. (parse_operands): Handle OPND_SME_list_of_64bit_tiles. * testsuite/gas/aarch64/sme-4-illegal.d: New test. * testsuite/gas/aarch64/sme-4-illegal.l: New test. * testsuite/gas/aarch64/sme-4-illegal.s: New test. * testsuite/gas/aarch64/sme-4.d: New test. * testsuite/gas/aarch64/sme-4.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_SME_list_of_64bit_tiles. opcodes/ChangeLog: * aarch64-opc.c (print_sme_za_list): New printing function. (aarch64_print_operand): Handle OPND_SME_list_of_64bit_tiles. * aarch64-opc.h (enum aarch64_field_kind): New bitfield FLD_SME_zero_mask. * aarch64-tbl.h (struct aarch64_opcode): New ZERO instruction. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
* aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus2021-11-1715-1/+575
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is adding new MOV (alias) and MOVA SME instruction. gas/ChangeLog: * config/tc-aarch64.c (enum sme_hv_slice): new enum. (struct reloc_entry): Added ZAH and ZAV registers. (parse_sme_immediate): Immediate parser. (parse_sme_za_hv_tiles_operand): ZA tile parser. (parse_sme_za_hv_tiles_operand_index): Index parser. (parse_operands): Added ZA tile parser calls. (REGNUMS): New macro. Regs with suffix. (REGSET16S): New macro. 16 regs with suffix. * testsuite/gas/aarch64/sme-2-illegal.d: New test. * testsuite/gas/aarch64/sme-2-illegal.l: New test. * testsuite/gas/aarch64/sme-2-illegal.s: New test. * testsuite/gas/aarch64/sme-2.d: New test. * testsuite/gas/aarch64/sme-2.s: New test. * testsuite/gas/aarch64/sme-2a.d: New test. * testsuite/gas/aarch64/sme-2a.s: New test. * testsuite/gas/aarch64/sme-3-illegal.d: New test. * testsuite/gas/aarch64/sme-3-illegal.l: New test. * testsuite/gas/aarch64/sme-3-illegal.s: New test. * testsuite/gas/aarch64/sme-3.d: New test. * testsuite/gas/aarch64/sme-3.s: New test. * testsuite/gas/aarch64/sme-3a.d: New test. * testsuite/gas/aarch64/sme-3a.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New enums AARCH64_OPND_SME_ZA_HV_idx_src and AARCH64_OPND_SME_ZA_HV_idx_dest. (struct aarch64_opnd_info): New ZA tile vector struct. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_sme_za_hv_tiles): New inserter. * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter ins_sme_za_hv_tiles. * aarch64-dis.c (aarch64_ext_sme_za_hv_tiles): New extractor. * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor ext_sme_za_hv_tiles. * aarch64-opc.c (aarch64_print_operand): Handle SME_ZA_HV_idx_src and SME_ZA_HV_idx_dest. * aarch64-opc.h (enum aarch64_field_kind): New enums FLD_SME_size_10, FLD_SME_Q, FLD_SME_V and FLD_SME_Rv. (struct aarch64_operand): Increase fields size to 5. * aarch64-tbl.h (OP_SME_BHSDQ_PM_BHSDQ): New qualifiers aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
* aarch64: [SME] Add SME instructionsPrzemyslaw Wirkus2021-11-1710-1/+872
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch is adding new SME matrix instructions. Please note additional instructions will be added in following patches. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_zada_operand): New parser. * config/tc-aarch64.c (parse_reg_with_qual): New reg parser. * config/tc-aarch64.c (R_ZA): New egister type. (parse_operands): New parser. * testsuite/gas/aarch64/sme-illegal.d: New test. * testsuite/gas/aarch64/sme-illegal.l: New test. * testsuite/gas/aarch64/sme-illegal.s: New test. * testsuite/gas/aarch64/sme.d: New test. * testsuite/gas/aarch64/sme.s: New test. * testsuite/gas/aarch64/sme-f64.d: New test. * testsuite/gas/aarch64/sme-f64.s: New test. * testsuite/gas/aarch64/sme-i64.d: New test. * testsuite/gas/aarch64/sme-i64.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operands AARCH64_OPND_SME_ZAda_2b, AARCH64_OPND_SME_ZAda_3b and AARCH64_OPND_SME_Pm. (enum aarch64_insn_class): New instruction class sme_misc. opcodes/ChangeLog: * aarch64-opc.c (aarch64_print_operand): Print OPND_SME_ZAda_2b and OPND_SME_ZAda_3b operands. (verify_constraints): Handle OPND_SME_Pm. * aarch64-opc.h (enum aarch64_field_kind): New bit fields FLD_SME_ZAda_2b, FLD_SME_ZAda_3b and FLD_SME_Pm. * aarch64-tbl.h (OP_SME_ZADA_PN_PM_ZN_S): New qualifier set. (OP_SME_ZADA_PN_PM_ZN_D): New qualifier. (OP_SME_ZADA_PN_PM_ZN_ZM): New qualifier. (OP_SME_ZADA_S_PM_PM_S_S): New qualifier. (OP_SME_ZADA_D_PM_PM_D_D): New qualifier. (OP_SME_ZADA_S_PM_PM_H_H): New qualifier. (OP_SME_ZADA_S_PM_PM_B_B): New qualifier. (OP_SME_ZADA_D_PM_PM_H_H): New qualifier. (SME_INSN): New instruction macro. (SME_F64_INSN): New instruction macro. (SME_I64_INSN): New instruction macro. (SME_INSNC): New instruction macro. (struct aarch64_opcode): New SME instructions. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
* aarch64: [SME] Add +sme option to -marchPrzemyslaw Wirkus2021-11-173-0/+19
| | | | | | | | | | | | | | | | | | | | | | This series of patches (tagged [SME]) add support for the Scalable Matrix Extension. Patch introduces new command line options: +sme, +sme-f64 and +sme-i64 to -march command line options. gas/ChangeLog: * NEWS: Updated docs. * config/tc-aarch64.c: New SME command line options. * doc/c-aarch64.texi: Update docs. include/ChangeLog: * opcode/aarch64.h (AARCH64_FEATURE_SME): New flag. (AARCH64_FEATURE_SME_F64): New flag. (AARCH64_FEATURE_SME_I64): New flag. opcodes/ChangeLog: * aarch64-tbl.h (SME): New feature object.
* RISC-V: Support rvv extension with released version 1.0.Nelson Chu2021-11-1719-14/+4293
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2021-11-17 Jim Wilson <jimw@sifive.com> Kito Cheng <kito.cheng@sifive.com> Nelson Chu <nelson.chu@sifive.com> This patch is porting from the following riscv github, https://github.com/riscv/riscv-binutils-gdb/tree/rvv-1.0.x And here is the vector spec, https://github.com/riscv/riscv-v-spec bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Added imply rules of v, zve and zvl extensions. (riscv_supported_std_ext): Updated verison of v to 1.0. (riscv_supported_std_z_ext): Added zve and zvl extensions. (riscv_parse_check_conflicts): The zvl extensions need to enable either v or zve extension. (riscv_multi_subset_supports): Check the subset list to know if the INSN_CLASS_V and INSN_CLASS_ZVEF instructions are supported. gas/ * config/tc-riscv.c (enum riscv_csr_class): Added CSR_CLASS_V. (enum reg_class): Added RCLASS_VECR and RCLASS_VECM. (validate_riscv_insn): Check whether the rvv operands are valid. (md_begin): Initialize register hash for rvv registers. (macro_build): Added rvv operands when expanding rvv pseudoes. (vector_macro): Expand rvv macros into one or more instructions. (macro): Likewise. (my_getVsetvliExpression): Similar to my_getVsetvliExpression, but used for parsing vsetvli operands. (riscv_ip): Parse and encode rvv operands. Besides, The rvv loads and stores with EEW 64 cannot be used when zve32x is enabled. * testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Updated -march to rv32ifv_zkr. * testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise. * testsuite/gas/riscv/priv-reg.s: Added rvv csr testcases. * testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise. * testsuite/gas/riscv/march-imply-v.d: New testcase. * testsuite/gas/riscv/vector-insns-fail-zve32xf.d: Likewise. * testsuite/gas/riscv/vector-insns-fail-zve32xf.l: Likewise. * testsuite/gas/riscv/vector-insns-fail-zvl.d: Likewise. * testsuite/gas/riscv/vector-insns-fail-zvl.l: Likewise. * testsuite/gas/riscv/vector-insns-vmsgtvx.d: Likewise. * testsuite/gas/riscv/vector-insns-vmsgtvx.s: Likewise. * testsuite/gas/riscv/vector-insns-zero-imm.d: Likewise. * testsuite/gas/riscv/vector-insns-zero-imm.s: Likewise. * testsuite/gas/riscv/vector-insns.d: Likewise. * testsuite/gas/riscv/vector-insns.s: Likewise. include/ * opcode/riscv-opc.h: Defined mask/match encodings and csrs for rvv. * opcode/riscv.h: Defined rvv immediate encodings and fields. (enum riscv_insn_class): Added INSN_CLASS_V and INSN_CLASS_ZVEF. (INSN_V_EEW64): Defined. (M_VMSGE, M_VMSGEU): Added for the rvv pseudoes. opcodes/ * riscv-dis.c (print_insn_args): Dump the rvv operands. * riscv-opc.c (riscv_vecr_names_numeric): Defined rvv registers. (riscv_vecm_names_numeric): Likewise. (riscv_vsew): Likewise. (riscv_vlmul): Likewise. (riscv_vta): Likewise. (riscv_vma): Likewise. (match_vs1_eq_vs2): Added for rvv Vu operand. (match_vd_eq_vs1_eq_vs2): Added for rvv Vv operand. (riscv_opcodes): Added rvv v1.0 instructions.
* x86: Don't allow KMOV in TLS code sequencesH.J. Lu2021-11-166-5/+35
| | | | | | | | | | | | | | | Don't allow KMOV in TLS code sequences which require integer MOV instructions. PR target/28595 * config/tc-i386.c (match_template): Don't allow KMOV in TLS code sequences. * testsuite/gas/i386/i386.exp: Run inval-tls and x86-64-inval-tls tests. * testsuite/gas/i386/inval-tls.l: New file. * testsuite/gas/i386/inval-tls.s: Likewise. * testsuite/gas/i386/x86-64-inval-tls.l: Likewise. * testsuite/gas/i386/x86-64-inval-tls.s: Likewise.
* RISC-V: Scalar crypto instruction and entropy source CSR testcases.jiawei2021-11-1641-3/+490
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add testcases for Scalar Crypto extension, with total testcase contain all instructions in k-ext/k-ext-64 and sub-extension testcase for zbk* zk*. Also add testcase for new CSR name 'seed' which is the Entropy Source in zkr. In fact these whole testcases can be combined into one file, after we have supported the .option arch +-= directives. gas/ * testsuite/gas/riscv/k-ext-64.d: New testcase for crypto instructions. * testsuite/gas/riscv/k-ext-64.s: Likewise. * testsuite/gas/riscv/k-ext.d: Likewise. * testsuite/gas/riscv/k-ext.s: Likewise. * testsuite/gas/riscv/zbkb-32.d: Likewise. * testsuite/gas/riscv/zbkb-32.s: Likewise. * testsuite/gas/riscv/zbkb-64.d: Likewise. * testsuite/gas/riscv/zbkb-64.s: Likewise. * testsuite/gas/riscv/zbkc-32.d: Likewise. * testsuite/gas/riscv/zbkc-64.d: Likewise. * testsuite/gas/riscv/zbkc.s: Likewise. * testsuite/gas/riscv/zbkx-32.d: Likewise. * testsuite/gas/riscv/zbkx-64.d: Likewise. * testsuite/gas/riscv/zbkx.s: Likewise. * testsuite/gas/riscv/zknd-32.d: Likewise. * testsuite/gas/riscv/zknd-32.s: Likewise. * testsuite/gas/riscv/zknd-64.d: Likewise. * testsuite/gas/riscv/zknd-64.s: Likewise. * testsuite/gas/riscv/zkne-32.d: Likewise. * testsuite/gas/riscv/zkne-32.s: Likewise. * testsuite/gas/riscv/zkne-64.d: Likewise. * testsuite/gas/riscv/zkne-64.s: Likewise. * testsuite/gas/riscv/zknh-32.d: Likewise. * testsuite/gas/riscv/zknh-32.s: Likewise. * testsuite/gas/riscv/zknh-64.d: Likewise. * testsuite/gas/riscv/zknh-64.s: Likewise. * testsuite/gas/riscv/zksed-32.d: Likewise. * testsuite/gas/riscv/zksed-64.d: Likewise. * testsuite/gas/riscv/zksed.s: Likewise. * testsuite/gas/riscv/zksh-32.d: Likewise. * testsuite/gas/riscv/zksh-64.d: Likewise. * testsuite/gas/riscv/zksh.s: Likewise. * testsuite/gas/riscv/priv-reg-fail-zkr.d: New testcase for zkr csr check. * testsuite/gas/riscv/priv-reg-fail-zkr.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Updated march to rv32if_zkr. * testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p10.d: Added Crypto seed csr. * testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise. * testsuite/gas/riscv/priv-reg.s: Likewise.
* RISC-V: Scalar crypto instructions and operand set.jiawei2021-11-161-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | Add instructions in k-ext, some instruction in zbkb, zbkc is reuse from zbb,zbc, we just change the class attribute to make them both support. The 'aes64ks1i' and 'aes64ks2' instructions are present in both the Zknd and Zkne extensions on rv64. Add new operand letter 'y' to present 'bs' symbol and 'Y' to present 'rnum' symbolc for zkn instructions. Also add a new Entropy Source CSR define 'seed' located at address 0x015. bfd/ * elfxx-riscv.c (riscv_multi_subset_supports): Added support for crypto extension. gas/ *config/tc-riscv.c (enum riscv_csr_class): Added CSR_CLASS_ZKR. (riscv_csr_address): Checked for CSR_CLASS_ZKR. (validate_riscv_insn): Added y and Y for bs and rnum operands. (riscv_ip): Handle y and Y operands. include/ * opcode/riscv-opc.h: Added encodings of crypto instructions. Also defined new csr seed, which address is 0x15. * opcode/riscv.h: Defined OP_* and INSN_CLASS_* for crypto. opcodes/ * riscv-dis.c (print_insn_args): Recognized new y and Y operands. * riscv-opc.c (riscv_opcodes): Added crypto instructions.
* Deal with full path in .file 0 directiveEric Botcazou2021-11-158-24/+184
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Gas uses the directory part, if present, of the .file 0 directive to set entry 0 of the directory table in DWARF 5, which represents the "current directory". Now Gas also uses the file part of the same directive to set entry 0 of the file table, which represents the "current compilation file". But the latter need not be located in the former so GCC will use a full path in the file part when it is passed a full path: gcc -c /full/path/test.c -save-temps yields: .file 0 "/current/directory" "/full/path/test.c" in the assembly file and: The Directory Table (offset 0x22, lines 2, columns 1): Entry Name 0 (indirect line string, offset: 0x25): /current/directory 1 (indirect line string, offset: 0x38): /full/path The File Name Table (offset 0x30, lines 2, columns 2): Entry Dir Name 0 0 (indirect line string, offset: 0x43): /full/path/test.c in the object file. Note the full path and the questionable Dir value in the 0 entry of the file table.
* PowerPC64 @notoc in non-power10 codeAlan Modra2021-11-151-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | R_PPC64_REL24_P9NOTOC is a variant of R_PPC64_REL24_NOTOC for use on @notoc cals from non-power10 code in the rare case that using such a construct is useful. R_PPC64_REL24_P9NOTOC will be emitted by gas rather than R_PPC64_REL24_NOTOC when @notoc is used in a branch instruction if power10 instructions are not enabled at that point. The new relocation tells the linker to not use power10 instructions on any stub emitted for that branch, unless overridden by --power10-stubs=yes. The current linker heuristic of only generating power10 instructions for stubs if power10-only relocations are detected, continues to be used. include/ * elf/ppc64.h (R_PPC64_REL24_P9NOTOC): Define. bfd/ * reloc.c (BFD_RELOC_PPC64_REL24_P9NOTOC): Define. * elf64-ppc.c (ppc64_elf_howto_raw): Add entry for new reloc. (ppc64_elf_reloc_type_lookup): Handle it. (enum ppc_stub_type): Delete. (enum ppc_stub_main_type, ppc_stub_sub_type): New. (struct ppc_stub_type): New. (struct ppc_stub_hash_entry): Use the above new type. (struct ppc_link_hash_table): Update stub_count. (is_branch_reloc, ppc64_elf_check_relocs), (toc_adjusting_stub_needed): Handle new reloc. (stub_hash_newfunc, select_alt_stub, ppc_merge_stub), (ppc_type_of_stub, plt_stub_size, build_plt_stub), (build_tls_get_addr_head, build_tls_get_addr_tail), (ppc_build_one_stub, ppc_size_one_stub, ppc64_elf_size_stubs), (ppc64_elf_build_stubs, ppc64_elf_relocate_section): Handle new reloc. Modify stub handling to suit new scheme. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-ppc.c (ppc_elf_suffix): When power10 is not enabled return BFD_RELOC_PPC64_REL24_P9NOTOC for @notoc. (fixup_size, ppc_force_relocation, ppc_fix_adjustable): Handle BFD_RELOC_PPC64_REL24_P9NOTOC. ld/ * testsuite/ld-powerpc/callstub-2.s: Add .machine power10.
* RISC-V: Dump objects according to the elf architecture attribute.Nelson Chu2021-11-114-92/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For now we should always generate the elf architecture attribute both for elf and linux toolchains, so that we could dump the objects correctly according to the generated architecture string. This patch resolves the problem that we probably dump an object with c.nop instructions, but in fact the c extension isn't allowed. Consider the following case, nelson@LAPTOP-QFSGI1F2:~/test$ cat temp.s .option norvc .option norelax .text add a0, a0, a0 .byte 0x1 .balign 16 nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-as temp.s -o temp.o nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-objdump -d temp.o temp.o: file format elf32-littleriscv Disassembly of section .text: 00000000 <.text>: 0: 00a50533 add a0,a0,a0 4: 01 .byte 0x01 5: 00 .byte 0x00 6: 0001 nop 8: 00000013 nop c: 00000013 nop nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-readelf -A temp.o Attribute Section: riscv File Attributes Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0" The c.nop at address 0x6 is generated for alignment, but since the rvc isn't allowed for this object, dump it as a c.nop instruction looks wrong. After applying this patch, I get the following result, nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-objdump -d temp.o temp.o: file format elf32-littleriscv Disassembly of section .text: 00000000 <.text>: 0: 00a50533 add a0,a0,a0 4: 01 .byte 0x01 5: 00 .byte 0x00 6: 0001 .2byte 0x1 8: 00000013 nop c: 00000013 nop For the current objdump, we dump data to .byte/.short/.word/.dword, and dump the unknown or unsupported instructions to .2byte/.4byte/.8byte, which respectively are 2, 4 and 8 bytes instructions. Therefore, we shouldn't dump the 0x0001 as a c.nop instruction in the above case, we should dump it to .2byte 0x1 as a unknown instruction, since the rvc is disabled. However, consider that some people may use the new objdump to dump the old objects, which don't have any elf attributes. We usually set the default architecture string to rv64g by bfd/elfxx-riscv.c:riscv_set_default_arch. But this will cause rvc instructions to be unrecognized. Therefore, we set the default architecture string to rv64gc for disassembler, to keep the previous behavior. This patch pass the riscv-gnu-toolchain gcc/binutils regressions for rv32emc-elf, rv32gc-linux, rv32i-elf, rv64gc-elf and rv64gc-linux toolchains. Also, tested by --enable-targets=all and can build riscv-gdb successfully. bfd/ * elfnn-riscv.c (riscv_merge_arch_attr_info): Tidy the codes for riscv_parse_subset_t setting. * elfxx-riscv.c (riscv_get_default_ext_version): Updated. (riscv_subset_supports): Moved from gas/config/tc-riscv.c. (riscv_multi_subset_supports): Likewise. * elfxx-riscv.h: Added extern for riscv_subset_supports and riscv_multi_subset_supports. gas/ * config/tc-riscv.c (riscv_subset_supports): Moved to bfd/elfxx-riscv.c. (riscv_multi_subset_supports): Likewise. (riscv_rps_as): Defined for architectrue parser. (riscv_set_arch): Updated. (riscv_set_abi_by_arch): Likewise. (riscv_csr_address): Likewise. (reg_lookup_internal): Likewise. (riscv_ip): Likewise. (s_riscv_option): Updated. * testsuite/gas/riscv/mapping-04b.d: Updated. * testsuite/gas/riscv/mapping-norelax-03b.d: Likewise. * testsuite/gas/riscv/mapping-norelax-04b.d: Likewise. opcodes/ * riscv-dis.c: Include elfxx-riscv.h since we need the architecture parser. Also removed the cpu-riscv.h, it is already included in elfxx-riscv.h. (default_isa_spec): Defined since the parser need this to set the default architecture string. (xlen): Moved out from riscv_disassemble_insn as a global variable, it is more convenient to initialize riscv_rps_dis. (riscv_subsets): Defined to recoed the supported extensions. (riscv_rps_dis): Defined for architectrue parser. (riscv_disassemble_insn): Call riscv_multi_subset_supports to make sure if the instructions are valid or not. (print_insn_riscv): Initialize the riscv_subsets by parsing the elf architectrue attribute. Otherwise, set the default architectrue string to rv64gc.
* arm: enable Cortex-A710 CPUPrzemyslaw Wirkus2021-11-104-0/+14
| | | | | | | | | | | | | | | This patch is adding support for Cortex-A710 CPU in Arm. bfd/ * cpu-arm.c (processors): Add cortex-a710. gas/ * NEWS: Update docs. * config/tc-arm.c (arm_cpus): Add cortex-a710 to -mcpu. * doc/c-arm.texi: Update docs. * testsuite/gas/arm/cpu-cortex-a710.d: New test.
* PR 28447: implement multiple parameters for .file on XCOFFClément Chigot2021-11-106-1/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On XCOFF, ".file" pseudo-op allows 3 extras parameters to provide additional information to AIX linker, or its debugger. These are stored in auxiliary entries of the C_FILE symbol. bfd/ PR 28447 * coffcode.h (combined_entry_type): Add extrap field. (coff_bigobj_swap_aux_in): Adjust names of x_file fields. (coff_bigobj_swap_aux_out): Likewise. * coffgen.c (coff_write_auxent_fname): New function. (coff_fix_symbol_name): Write x_file using coff_write_auxent_fname. (coff_write_symbol): Likewise. (coff_write_symbols): Add C_FILE auxiliary entries to string table if needed. (coff_get_normalized_symtab): Adjust names of x_file fields. Normalize C_FILE auxiliary entries. (coff_print_symbol): Print C_FILE auxiliary entries. * coff-rs6000.c (_bfd_xcoff_swap_aux_in): Adjust names of x_file fields. (_bfd_xcoff_swap_aux_out): Likewise. * coff64-rs6000.c (_bfd_xcoff64_swap_aux_in): Likewise. (_bfd_xcoff64_swap_aux_out): Likewise. * cofflink.c (_bfd_coff_final_link): Likewise. (_bfd_coff_link_input_bfd): Likewise. * coffswap.h (coff_swap_aux_in): Likewise. * peXXigen.c (_bfd_XXi_swap_aux_in): Likewise. (_bfd_XXi_swap_aux_out): Likewise. * xcofflink.c (xcoff_link_input_bfd): Likewise. * libcoff.h: Regenerate. gas/ * config/tc-ppc.c (ppc_file): New function. * config/tc-ppc.h (OBJ_COFF_MAX_AUXENTRIES): Change to 4. * testsuite/gas/ppc/aix.exp: Add tests. * testsuite/gas/ppc/xcoff-file-32.d: New test. * testsuite/gas/ppc/xcoff-file-64.d: New test. * testsuite/gas/ppc/xcoff-file.s: New test. include/ * coff/internal.h (union internal_auxent): Change x_file to be a struct instead of a union. Add x_ftype field. * coff/rs6000.h (union external_auxent): Add x_resv field. * coff/xcoff.h (XFT_FN): New define. (XFT_CT): Likewise. (XFT_CV): Likewise. (XFT_CD): Likewise.
* Modernise yyerrorAlan Modra2021-11-062-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | Newer versions of bison emit a prototype for yyerror void yyerror (const char *); This clashes with some of our old code that declares yyerror to return an int. Fix that in most cases by modernizing yyerror. bfin-parse.y uses the return value all over the place, so for there disable generation of the prototype as specified by posix. binutils/ * arparse.y (yyerror): Return void. * dlltool.c (yyerror): Likewise. * dlltool.h (yyerror): Likewise. * sysinfo.y (yyerror): Likewise. * windmc.h (yyerror): Likewise. * mclex.c (mc_error): Extract from .. (yyerror): ..here, both now returning void. gas/ * config/bfin-parse.y (yyerror): Define. (yyerror): Make static. * itbl-parse.y (yyerror): Return void. ld/ * deffilep.y (def_error): Return void.
* RISC-V: Clarify the behavior of .option rvc or norvc.Nelson Chu2021-11-041-21/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add/Remove the rvc extension to/from the riscv_subsets once the .option rvc/norvc is set. So that we don't need to always check the riscv_opts.rvc in the riscv_subset_supports, just call the riscv_lookup_subset to search the subset list is enough. Besides, we will need to dump the instructions according to the elf architecture attributes. That means the dis-assembler needs to parse the architecture string from the elf attribute before dumping any instructions, and also needs to recognized the INSN_CLASS* classes from riscv_opcodes. Therefore, I suppose some functions will need to be moved from gas/config/tc-riscv.c to bfd/elfxx-riscv.c, including riscv_multi_subset_supports and riscv_subset_supports. This is one of the reasons why we need this patch. This patch passes the gcc/binutils regressions of rv32emc-elf, rv32i-elf, rv64gc-elf and rv64gc-linux toolchains. bfd/ * elfxx-riscv.c (riscv_remove_subset): Remove the extension from the subset list. (riscv_update_subset): Add/Remove an extension to/from the subset list. This is used for the .option rvc or norvc. * elfxx-riscv.h: Added the extern bool riscv_update_subset. gas/ * config/tc-riscv.c (riscv_set_options): Removed the unused rve flag. (riscv_opts): Likewise. (riscv_set_rve): Removed. (riscv_subset_supports): Removed the riscv_opts.rvc check. (riscv_set_arch): Don't need to call riscv_set_rve. (reg_lookup_internal): Call riscv_subset_supports to check whether the rve is supported. (s_riscv_option): Add/Remove the rvc extension to/from the subset list once the .option rvc/norvc is set.
* asan: dlltool buffer overflow: embedded NUL in stringAlan Modra2021-11-031-3/+1
| | | | | | | | | | | | | | | | | yyleng gives the pattern length, xstrdup just copies up to the NUL. So it is quite possible writing at an index of yyleng-2 overflows the xstrdup allocated string buffer. xmemdup quite handily avoids this problem, even writing the terminating NUL over the trailing quote. Use it in ldlex.l too where we'd already had a report of this problem and fixed it by hand, and to implement xmemdup0 in gas. binutils/ * deflex.l (single and double quote strings): Use xmemdup. gas/ * as.h (xmemdup0): Use xmemdup. ld/ PR 20906 * ldlex.l (double quote string): Use xmemdup.
* ARM: match armeb output for unwind-pacbti-m testAlan Modra2021-11-021-3/+3
| | | | * testsuite/gas/arm/unwind-pacbti-m.d: Match armeb output.
* arm: add armv9-a architecture to -marchPrzemyslaw Wirkus2021-11-015-4/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update also include: + New value of Tag_CPU_arch EABI attribute (22) is added. + Updated missing Tag_CPU_arch EABI attributes. + Updated how we combine archs 'v4t_plus_v6_m' as this mechanism have to handle new Armv9 as well. Regression tested on `arm-none-eabi` cross Binutils and no issues. bfd/ * archures.c: Define bfd_mach_arm_9. * bfd-in2.h (bfd_mach_arm_9): Define bfd_mach_arm_9. * cpu-arm.c: Add 'armv9-a' option to -march. * elf32-arm.c (using_thumb2_bl): Update assert check. (arch_has_arm_nop): Add TAG_CPU_ARCH_V9. (bfd_arm_get_mach_from_attributes): Add case for TAG_CPU_ARCH_V9. Update assert. (tag_cpu_arch_combine): Updated table. (v9): New table.. binutils/ * readelf.c (arm_attr_tag_CPU_arch): Update with elfcpp/ * arm.h: Update TAG_CPU_ARCH_ enums with correct values. gas/ * NEWS: Update docs. * config/tc-arm.c (get_aeabi_cpu_arch_from_fset): Return Armv9-a for -amarch=all. (aeabi_set_public_attributes): Update assert. * doc/c-arm.texi: Update docs. * testsuite/gas/arm/armv9-a_arch.d: New test. * testsuite/gas/arm/attr-march-all.d: Update test with v9. include/ * elf/arm.h Update TAG_CPU_ARCH_ defines with correct values. * opcode/arm.h (ARM_EXT3_V9A): New macro. (ARM_ARCH_NONE): Updated with arm_feature_set.core size. (FPU_NONE): Updated. (ARM_ANY): Updated. (ARM_ARCH_UNKNOWN): New macro. (ARM_FEATURE_LOW): Updated. (ARM_FEATURE_CORE): Updated. (ARM_FEATURE_CORE_LOW): Updated. (ARM_FEATURE_CORE_HIGH): Updated. (ARM_FEATURE_COPROC): Updated. (ARM_FEATURE): Updated. (ARM_FEATURE_ALL): New macro. opcodes/ * arm-dis.c (select_arm_features): Support bfd_mach_arm_9. Also Update bfd_mach_arm_unknown to use new macro ARM_ARCH_UNKNOWN.
* Re: arm: add unwinder encoding support for PACBTIAlan Modra2021-10-293-0/+59
| | | | Move the gas testsuite files to where they belong.
* ARM assembler: Allow up to 32 single precision registers in the VPUSH and ↵Markus Klein2021-10-284-17/+41
| | | | | | | | | | | VPOP instructions. PR 28436 * config/tc-arm.c (do_vfp_nsyn_push_pop_check): New function. (do_vfp_nsyn_pop): Use the new function. (do_vfp_nsyn_push): Use the new function. * testsuite/gas/arm/v8_1m-mve.s: Add new instructions. * testsuite/gas/arm/v8_1m-mve.d: Updated expected disassembly.
* arm: add unwinder encoding support for PACBTITejas Belagod2021-10-281-5/+57
| | | | | | | | | | | | | | | | | | | | This patch adds support for encoding the Return Address Authentication pseudo register - '.save {ra_auth_code}' as defined by the DWARF ABI - in the exception tables where the opcode is defined by the EHABI gas/Changelog: * config/tc-arm.c (arm_reg_type): Add new type REG_TYPE_PSEUDO. (reg_expected_msgs): Add message for pseudo reg type. (reg_list_els): Add new reg list type REGLIST_PSEUDO. (parse_reg_list): Handle new REGLIST_PSEUDO type. (s_arm_unwind_save_pseudo): Encode pseudo reg list save in exception tables. (s_arm_unwind_save): Handle new REG_TYPE_PSEUDO. (reg_names): Add ra_auth_code pseudo register. * testsuite/gas/arm/unwind-pacbti-m.s: New test. * testsuite/gas/arm/unwind-pacbti-m.d: New test. * testsuite/gas/arm/unwind-pacbti-m-readelf.d: New test.
* RISC-V: Tidy riscv assembler and disassembler.Nelson Chu2021-10-271-288/+304
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tidy the gas/config/tc-riscv.c and opcodes/riscv-dis.c, to prepare for moving the released extensions (including released vendor extensions) from integration branch back to mainline. * Added parts of missing comments. * Updated md_show_usage. * For validate_riscv_insn, riscv_ip and print_insn_args, unify the following pointer names, - oparg: pointed to the parsed operand defined in the riscv_opcodes. - asarg: pointed to the parsed operand from assembly. - opargStart: recorded the parsed operand name from riscv_opcodes. - asargStart: recorded the parsed operand name from assembly. gas/ * config/tc-riscv.c: Added parts of missind comments and updated the md_show_usage. (riscv_multi_subset_supports): Tidy codes. (validate_riscv_insn): Unify the pointer names, oparg, asarg, opargStart and asargStart, to prepare for moving the released extensions from integration branch back to mainline. (riscv_ip): Likewise. (macro_build): Added fmtStart, also used to prepare for moving released extensions. (md_show_usage): Added missing descriptions for new options. opcodes/ * riscv-dis.c (print_insn_args): Unify the pointer names, oparg and opargStart, to prepare for moving the released extensions from integration branch back to mainline.
* x86: Also handle stores for -muse-unaligned-vector-moveH.J. Lu2021-10-254-15/+74
| | | | | | | | * config/tc-i386.c (encode_with_unaligned_vector_move): Also handle stores. * testsuite/gas/i386/unaligned-vector-move.s: Add stores. * testsuite/gas/i386/unaligned-vector-move.d: Updated. * testsuite/gas/i386/x86-64-unaligned-vector-move.d: Likewise.
* LoongArch gas supportliuzhensong2021-10-2439-5/+4152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2021-10-22 Chenghua Xu <xuchenghua@loongson.cn> Zhensong Liu <liuzhensong@loongson.cn> Weinan Liu <liuweinan@loongson.cn> Xiaolin Tang <tangxiaolin@loongson.cn> gas/ * Makefile.am: Add LoongArch. * NEWS: Mention LoongArch support. * config/loongarch-lex-wrapper.c: New. * config/loongarch-lex.h: New. * config/loongarch-lex.l: New. * config/loongarch-parse.y: New. * config/tc-loongarch.c: New. * config/tc-loongarch.h: New. * configure.ac: Add LoongArch. * configure.tgt: Likewise. * doc/as.texi: Likewise. * doc/c-loongarch.texi: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate. gas/testsuite/ * gas/all/gas.exp: Add LoongArch. * gas/elf/elf.exp: Likewise. * gas/loongarch/4opt_op.d: New. * gas/loongarch/4opt_op.s: Likewise. * gas/loongarch/fix_op.d: Likewise. * gas/loongarch/fix_op.s: Likewise. * gas/loongarch/float_op.d: Likewise. * gas/loongarch/float_op.s: Likewise. * gas/loongarch/imm_op.d: Likewise. * gas/loongarch/imm_op.s: Likewise. * gas/loongarch/jmp_op.d: Likewise. * gas/loongarch/jmp_op.s: Likewise. * gas/loongarch/load_store_op.d: Likewise. * gas/loongarch/load_store_op.s: Likewise. * gas/loongarch/loongarch.exp: Likewise. * gas/loongarch/macro_op.d: Likewise. * gas/loongarch/macro_op.s: Likewise. * gas/loongarch/nop.d: Likewise. * gas/loongarch/nop.s: Likewise. * gas/loongarch/privilege_op.d: Likewise. * gas/loongarch/privilege_op.s: Likewise. * gas/loongarch/syscall.d: Likewise. * gas/loongarch/syscall.s: Likewise. * lib/gas-defs.exp: Add LoongArch.
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