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* aarch64: Add the SME2 dot-product instructionsRichard Sandiford2023-03-3028-0/+2355
* aarch64: Add the SME2 MLALL and MLSLL instructionsRichard Sandiford2023-03-3022-0/+2317
* aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford2023-03-308-0/+2084
* aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford2023-03-3015-0/+1129
* aarch64: Add the SME2 maximum/minimum instructionsRichard Sandiford2023-03-308-6/+2218
* aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford2023-03-3022-1/+1424
* aarch64: Add the SME2 ZT0 instructionsRichard Sandiford2023-03-3011-12/+746
* aarch64: Add the SME2 predicate-related instructionsRichard Sandiford2023-03-3026-24/+2680
* aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford2023-03-3029-0/+6804
* aarch64: Add the SME2 MOVA instructionsRichard Sandiford2023-03-3010-2/+1598
* aarch64: Add support for predicate-as-counter registersRichard Sandiford2023-03-3015-3/+331
* aarch64; Add support for vector offset rangesRichard Sandiford2023-03-3011-0/+84
* aarch64: Add support for vgx2 and vgx4Richard Sandiford2023-03-3013-1/+119
* aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_arrayRichard Sandiford2023-03-301-1/+1
* aarch64: Add +sme2Richard Sandiford2023-03-303-0/+6
* aarch64: Prefer register ranges & support wrappingRichard Sandiford2023-03-3011-982/+1038
* aarch64: Add support for strided register listsRichard Sandiford2023-03-304-27/+53
* aarch64: Rename some of GAS's REG_TYPE_* macrosRichard Sandiford2023-03-301-71/+71
* aarch64: Add a aarch64_cpu_supports_inst_p helperRichard Sandiford2023-03-301-2/+1
* aarch64: Tweak priorities of parsing-related errorsRichard Sandiford2023-03-302-11/+51
* aarch64: Try to report invalid variants against the closest matchRichard Sandiford2023-03-304-93/+101
* aarch64: Tweak register list errorsRichard Sandiford2023-03-304-20/+18
* aarch64: Make AARCH64_OPDE_REG_LIST take a bitfieldRichard Sandiford2023-03-301-20/+34
* aarch64: Add an operand class for SVE register listsRichard Sandiford2023-03-301-13/+13
* aarch64: Add an error code for out-of-range registersRichard Sandiford2023-03-301-0/+8
* aarch64: Deprioritise AARCH64_OPDE_REG_LISTRichard Sandiford2023-03-301-3/+3
* aarch64: Update operand_mismatch_kind_namesRichard Sandiford2023-03-301-0/+2
* aarch64: Rework reporting of failed register checksRichard Sandiford2023-03-3023-972/+1202
* aarch64: Try to avoid inappropriate default errorsRichard Sandiford2023-03-306-5/+26
* aarch64: Improve errors for malformed register listsRichard Sandiford2023-03-306-21/+41
* aarch64: Tweak parsing of integer & FP registersRichard Sandiford2023-03-301-29/+42
* aarch64: Tweak errors for base & offset registersRichard Sandiford2023-03-309-293/+308
* aarch64: Tweak error for missing immediate offsetRichard Sandiford2023-03-305-18/+18
* aarch64: Move w12-w15 range check to libopcodesRichard Sandiford2023-03-307-26/+31
* aarch64: Commonise index parsingRichard Sandiford2023-03-301-21/+21
* aarch64: Consolidate ZA slice parsingRichard Sandiford2023-03-305-72/+55
* aarch64: Move ZA range checks to aarch64-opc.cRichard Sandiford2023-03-308-140/+77
* aarch64: Pass aarch64_indexed_za to parsersRichard Sandiford2023-03-301-152/+78
* aarch64: Rename za_tile_vector to za_indexRichard Sandiford2023-03-301-9/+9
* aarch64: Treat ZA as a registerRichard Sandiford2023-03-303-46/+89
* aarch64: Consolidate ZA tile range checksRichard Sandiford2023-03-306-163/+127
* aarch64: Reuse parse_typed_reg for ZA tilesRichard Sandiford2023-03-301-51/+47
* aarch64: Rework parse_typed_reg interfaceRichard Sandiford2023-03-301-71/+53
* aarch64: Move vectype_to_qualifier further upRichard Sandiford2023-03-301-75/+75
* aarch64: Add REG_TYPE_ZATHVRichard Sandiford2023-03-301-14/+9
* aarch64: Rename REG_TYPE_ZA* to REG_TYPE_ZAT*Richard Sandiford2023-03-301-10/+11
* aarch64: Use aarch64_operand_error more widelyRichard Sandiford2023-03-301-22/+8
* aarch64: Fix SVE2 register/immediate distinctionRichard Sandiford2023-03-303-1/+13
* aarch64: Restrict range of PRFM opcodesRichard Sandiford2023-03-304-17/+17
* aarch64: Fix PSEL opcode maskRichard Sandiford2023-03-302-0/+8
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