summaryrefslogtreecommitdiff
path: root/gas
Commit message (Expand)AuthorAgeFilesLines
* Support Intel AVX-VNNI-INT8Cui,Lili2022-11-0210-1/+547
* Support Intel AVX-IFMAHongyu Wang2022-11-0215-15/+252
* opcodes/arm: use '@' consistently for the comment characterAndrew Burgess2022-11-01121-2291/+2291
* x86: minor improvements to optimize_imm() (part III)Jan Beulich2022-10-311-9/+8
* x86: Silence GCC 12 warning on tc-i386.cH.J. Lu2022-10-312-5/+5
* Support Intel PREFETCHICui, Lili2022-10-3113-3/+103
* RX assembler: switch arguments of thw MVTACGU insn.Yoshinori Sato2022-10-312-4/+8
* RISC-V: Always generate mapping symbols at the start of the sections.Nelson Chu2022-10-293-41/+0
* gas: NEWS: Note support for RISC-V ZawrsPalmer Dabbelt2022-10-281-0/+2
* gas: NEWS: Add a missing newlinePalmer Dabbelt2022-10-281-0/+1
* RISC-V: Improve "bits undefined" diagnosticsTsukasa OI2022-10-281-2/+2
* RISC-V: Fallback for instructions longer than 64bTsukasa OI2022-10-281-5/+8
* RISC-V/gas: fix build with certain gcc versionsJan Beulich2022-10-281-7/+7
* RISC-V: Fix build failure for -Werror=maybe-uninitializedTsukasa OI2022-10-281-1/+1
* RISC-V: Output mapping symbols with ISA string.Nelson Chu2022-10-2824-328/+404
* PowerPC: Add support for RFC02658 - MMA+ Outer-Product InstructionsPeter Bergner2022-10-274-2/+81
* PowerPC: Add support for RFC02653 - Dense Math FacilityPeter Bergner2022-10-276-65/+270
* re: Support Intel AMX-FP16Alan Modra2022-10-272-0/+2
* x86: consolidate VPCLMUL testsJan Beulich2022-10-2415-268/+156
* x86: consolidate VAES testsJan Beulich2022-10-2415-352/+211
* x86: emit {evex} prefix when disassembling ambiguous AVX512VL insnsJan Beulich2022-10-2431-361/+361
* Support Intel AMX-FP16Cui,Lili2022-10-219-1/+97
* x86: Check VEX/EVEX encoding before checking vector operandsH.J. Lu2022-10-205-4/+8
* x86: re-work AVX-VNNI supportJan Beulich2022-10-207-12/+36
* aarch64-pe support for LD, GAS and BFDJedidiah Thompson2022-10-198-25/+108
* x86: generalize gas documentation for disabling of ISA extensionsJan Beulich2022-10-181-49/+5
* Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp}CaiJingtao2022-10-175-205/+566
* PowerPC se_rfmci and VLE, SPE2 and LSP insns with -manyAlan Modra2022-10-165-56/+55
* PowerPC SPE disassembly and testsAlan Modra2022-10-144-14/+11
* e200 LSP supportAlan Modra2022-10-145-12/+38
* RISC-V: Imply 'Zicsr' from privileged extensions with CSRsTsukasa OI2022-10-141-0/+6
* RISC-V: Test DWARF register number for "fp"Tsukasa OI2022-10-142-0/+4
* x86: drop "regmask" static variableJan Beulich2022-10-121-3/+2
* Re: Error: attempt to get value of unresolved symbol `L0'Nick Clifton2022-10-114-10/+26
* add --enable-default-compressed-debug-sections-algorithm configure optionMartin Liska2022-10-115-3/+40
* refactor usage of compressed_debug_section_typeMartin Liska2022-10-111-25/+9
* Error: attempt to get value of unresolved symbol `L0'Nick Clifton2022-10-112-2/+12
* x86/gas: support quoted address scale factor in AT&T syntaxJan Beulich2022-10-054-12/+35
* Arm64: support CLEARBHB aliasJan Beulich2022-10-052-1/+3
* gas: NEWS: Mention the T-Head extensions that were recently addedPalmer Dabbelt2022-10-041-0/+5
* Re: compress .gnu.debuglto_.debug_* sections if requestedAlan Modra2022-10-041-13/+7
* compress .gnu.debuglto_.debug_* sections if requestedMartin Liska2022-10-041-1/+3
* RISC-V/gas: allow generating up to 176-bit instructions with .insnJan Beulich2022-10-047-10/+82
* RISC-V/gas: don't open-code insn_length()Jan Beulich2022-10-041-1/+1
* RISC-V/gas: drop stray call to install_insn()Jan Beulich2022-10-041-1/+0
* RISC-V/gas: drop riscv_subsets static variableJan Beulich2022-10-041-18/+14
* RISC-V: don't cast expressions' X_add_number to long in diagnosticsJan Beulich2022-10-041-4/+4
* RISC-V: Assign DWARF numbers to vector registersTsukasa OI2022-10-033-2/+73
* RISC-V: Add testcase for DWARF register numbersTsukasa OI2022-10-032-0/+296
* RISC-V: Relax "fmv.[sdq]" requirementsTsukasa OI2022-09-306-0/+6
View Lorry Controller Status