summaryrefslogtreecommitdiff
path: root/gas/testsuite
Commit message (Collapse)AuthorAgeFilesLines
* x86-64: LAR and LSL don't need REX.WJan Beulich2023-02-222-24/+24
| | | | | | | | | | Just like we suppress emitting REX.W for e.g. MOV from/to segment register, there's also no need for it for LAR and LSL - these can only ever return 32-bit values and hence always zero-extend their results anyway. While there also drop the redundant Word from the first operand of the second template each - this is already implied by Reg16.
* x86: optimize BT{,C,R,S} $imm,%regJan Beulich2023-02-227-0/+79
| | | | | | In 64-bit mode BT can have REX.W or a data size prefix dropped in certain cases. Outside of 64-bit mode all 4 insns can have the data size prefix dropped in certain cases.
* gas/testsuite: adjust a test for case insensitive file systemsClément Chigot2023-02-212-7/+7
| | | | | | | | | | | | | | When dealing with case insensitive file systems, ".file line.s" and ".file Line.s" are identical and thus gas won't change the current input file. However, in line.l test, it's expecting to trigger an input file switch. As the second filename doesn't matter in it, change it to fit for those file systems. gas/ChangeLog: * testsuite/gas/elf/line.l: Change Line.s to Line2.s. * testsuite/gas/elf/line.s: Adjust output.
* gas: correct symbol name comparison in .startof./.sizeof. handlingJan Beulich2023-02-142-0/+5
| | | | | | In 162c6aef1f3a ("gas: fold symbol table entries generated for .startof.() / .sizeof.()") I screwed up quite badly, inverting the case sensitive and case insensitive comparison functions.
* PR30120: fix x87 fucomp misassembledMichael Matz2023-02-132-3/+20
| | | | | this fixes the entry for 'fucomp' to use the correct Reg value (otherwise it's assembled as 'fucom').
* objdump -D of bss sections and -s with -jAlan Modra2023-02-112-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is some inconsistency between the behaviour of objdump -D and objdump -s, both supposedly operating on all sections by default. objdump -s ignores bss sections, while objdump -D dissassembles the zeros. Fix this by making objdump -D ignore bss sections too. Furthermore, "objdump -s -j .bss" doesn't dump .bss as it should, since the user is specifically asking to look at all those zeros. This change does find some tests that used objdump -D with expected output in bss-style sections. I've updated all the msp430 tests that just wanted to find a non-empty section to look at section headers instead, making the tests slightly more stringent. The ppc xcoff and spu tests are fixed by adding -j options to objdump, which makes the tests somewhat more lenient. binutils/ * objdump.c (disassemble_section): Ignore sections without contents, unless overridden by -j. (dump_section): Allow -j to override the default of not displaying sections without contents. * doc/binutils.texi (objdump options): Update -D, -s and -j description. gas/ * testsuite/gas/ppc/xcoff-tls-32.d: Select wanted objdump sections with -j. * testsuite/gas/ppc/xcoff-tls-64.d: Likewise. ld/ * testsuite/ld-msp430-elf/main-bss-lower.d, * testsuite/ld-msp430-elf/main-bss-upper.d, * testsuite/ld-msp430-elf/main-const-lower.d, * testsuite/ld-msp430-elf/main-const-upper.d, * testsuite/ld-msp430-elf/main-text-lower.d, * testsuite/ld-msp430-elf/main-text-upper.d, * testsuite/ld-msp430-elf/main-var-lower.d, * testsuite/ld-msp430-elf/main-var-upper.d: Expect -wh output. * testsuite/ld-msp430-elf/msp430-elf.exp: Use objdump -wh rather than objdump -D or objdump -d with tests checking for non-empty given sections. * testsuite/ld-spu/ear.d, * testsuite/ld-spu/icache1.d, * testsuite/ld-spu/ovl.d, * testsuite/ld-spu/ovl2.d: Select wanted objdump sections.
* x86: drop LOCK from XCHG when optimizingJan Beulich2023-02-035-0/+12
| | | | | Like with segment overrides on LEA, optimize away such a redundant instruction prefix.
* x86-64: respect {nooptimize} when building VEX prefixJan Beulich2023-02-032-0/+5
| | | | | | Swapping operands for commutative insns occurs outside of optimize_encoding() and hence needs explicit checking for a request to avoid any optimizations.
* x86: respect {nooptimize} for LEAJan Beulich2023-02-037-1/+15
| | | | | | Dropping a meaningless segment prefix occurs outside of optimize_encoding() and hence needs explicit checking for a request to avoid any optimizations.
* RISC-V: don't disassemble unrecognized insns as .byteJan Beulich2023-02-032-16/+16
| | | | | | | Insn width granularity being 16 bits, producing byte granular output isn't very useful. With there being a way to specific otherwise unknown insns to the assembler, use that same representation (to be precise: its <length>,<encoding> flavor) for disassembly.
* gas: use "stack trace" instead of "unwind" for SFrameIndu Bhagat2023-02-024-7/+7
| | | | | | | | | | | | | | | | | SFrame format is meant for generating stack traces only. gas/ * as.c: Replace the use of "unwind" with "stack trace". * config/tc-aarch64.c: Likewise. * config/tc-aarch64.h: Likewise. * config/tc-i386.c: Likewise. * config/tc-i386.h: Likewise. * gen-sframe.c: Likewise. * gen-sframe.h: Likewise. * testsuite/gas/cfi-sframe/cfi-sframe-aarch64-2.s: Likewise. * testsuite/gas/cfi-sframe/cfi-sframe-common-8.s: Likewise. * testsuite/gas/cfi-sframe/common-empty-2.s: Likewise. * testsuite/gas/cfi-sframe/common-empty-3.s: Likewise.
* [gas] Emit v2 .debug_line for -gdwarf-2Tom de Vries2023-02-013-15/+6
| | | | | | | | | | | | | | | | | | | | Currently, when using -gdwarf-2, gas emits a v3 .debug_line contribution. Fix this by emitting a v2 .debug_line contribution instead. gas/ChangeLog: 2023-01-31 Tom de Vries <tdevries@suse.de> PR 23941 * dwarf2dbg.c (DWARF2_LINE_VERSION): Set to 2 for -gdwarf-2. (DWARF2_LINE_OPCODE_BASE): Handle DWARF2_LINE_VERSION == 2. (dwarf2_directive_loc): Bump dwarf_level when encountering v3 .loc options. (out_debug_line): Don't output v3 standard opcodes for v2. * testsuite/gas/i386/debug1.d: Update. * testsuite/gas/i386/dwarf2-line-1.d: Update. * testsuite/gas/i386/dwarf2-line-4.d: Update.
* gas/ppc: Additional tests for DFP instructionsAndrew Burgess2023-01-313-0/+186
| | | | | | | | | | | | | | | I noticed that some of the Power6 DFP instructions were not covered by the assembler tests. I've added a new test file which I believe covers all the DFP Power6 instructions. The existing gas/testsuite/gas/ppc/power6.d test is called: POWER6 tests (includes DFP and Altivec) And does cover some of the DFP instructions. But, given the number of additional instructions I'm adding I opted to add a whole new test file. I've left the original power6.d unchanged, so there is now some overlap, but I don't think that should hurt much.
* RISC-V: make C-extension JAL available again for (32-bit) assemblyJan Beulich2023-01-313-0/+50
| | | | | | | | | | Along with the normal JAL alias, the C-extension one should have been moved as well by 839189bc932e ("RISC-V: re-arrange opcode table for consistent alias handling"), for the assembler to actually be able to use it where/when possible. Since neither this nor any other compressed branch insn was being tested so far, take the opportunity and introduce a new testcase covering those.
* gas/testsuite: Add -gcodeview test for aarch64-w64-mingw32Mark Harmstone2023-01-274-0/+350
| | | | | This is a copy of the x86 gas -gcodeview test, with changes made for the differing instruction lengths between x86 and aarch64.
* gas: arm: Change warning message to not reference specific A-class ↵Stam Markianos-Wright2023-01-174-222/+222
| | | | | | | | | | | | | | | | | | | | | | | | | architecture revision We noticed that a warning message about the use of scalar fp16 instructions being UNPREDICTABLE when conditionalized in an IT block referenced the specific A-class architecture revision ARMv8.2-A. Many of these instructions are now also part of ARMv8.1-M, so the warning message had become misleading. Here we just change the message to not specify an architecture revision at all and update all testing accordingly. This was done with a simple find-n-replace within the binutils sources. No tests have regressed for the arm target. gas/ChangeLog: * config/tc-arm.c (do_scalar_fp16_v82_encode): Remove ARMv8.2-A from the warning message. (do_neon_movhf): Likewise * testsuite/gas/arm/armv8-2-fp16-scalar-bad.l: Likewise * testsuite/gas/arm/mve-vaddsub-it-bad.l: Likewise * testsuite/gas/arm/mve-vcvtne-it-bad.l: Likewise * testsuite/gas/arm/mve-vcvtne-it.d: Likewise
* gas: arm: Fix a further IT-predicated vcvt issue in the presense of MVE vcvtnStam Markianos-Wright2023-01-174-2/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we had experienced issues with assembling a "VCVTNE" instruction in the presence of the MVE architecture extension, because it could be interpreted both as: * The base instruction VCVT + NE for IT predication when inside an IT block. * The MVE instruction VCVTN + E in the Else of a VPT block. Given a C reproducer of: ``` int test_function(float value) { int ret_val = 10; if (value != 0.0) { ret_val = (int) value; } return ret_val; } ``` GCC generates a VCVTNE instruction based on the `truncsisf2_vfp` pattern, which will look like: `vcvtne.s32.f32 s-reg, s-reg` This still triggers an error due to being misidentified as "vcvtn+e" Similar errors were found with other type combinations and instruction patterns (these have all been added to the testing of this patch). This class of errors was previously worked around by: https://sourceware.org/pipermail/binutils/2020-August/112728.html which addressed this by looking at the operand types, however, that isn't adequate to cover all the extra cases that have been found. Instead, we add some special-casing logic earlier when the instructions are parsed that is conditional on whether we are in a VPT block or not, when the instruction is parsed. gas/ChangeLog: * config/tc-arm.c (opcode_lookup): Add special vcvtn handling. * testsuite/gas/arm/mve-vcvtne-it-bad.l: Add further testing. * testsuite/gas/arm/mve-vcvtne-it-bad.s: Likewise. * testsuite/gas/arm/mve-vcvtne-it.d: Likewise. * testsuite/gas/arm/mve-vcvtne-it.s: Likewise.
* PR29991, MicroMIPS flag erased after align directivesAlan Modra2023-01-164-0/+30
| | | | | | | | | | PR 29991 * config/tc-mips.c (s_align): Call file_mips_check_options and mips_mark_labels. * testsuite/gas/mips/align-after-label.s, * testsuite/gas/mips/mips-align-after-label.d, * testsuite/gas/mips/micromips-align-after-label.d: New test. * testsuite/gas/mips/mips.exp: Run it.
* Add aarch64-w64-mingw32 targetMark Harmstone2023-01-101-1/+1
| | | | | | | This adds a mingw target for aarch64, including windres and dlltool. Note that the old value of jmp_aarch64_bytes was wrong, and this does the same thing as MSVC does.
* Add pe-aarch64 relocationsMark Harmstone2023-01-102-14/+378
| | | | | | | This adds the remaining pe-aarch64 relocations, and gets them working. It also brings in the constant directives from ELF, as otherwise .word would be 2 rather than 4 bytes, and .xword and .dword wouldn't be defined.
* obsolete target tidyAlan Modra2023-01-026-11/+7
| | | | | | | Delete a few files only used for obsolete targets, and tidy config, xfails and other pieces of support specific to those targets. And since I was editing target triplets in test files, fix the nm alpha-linuxecoff fails.
* Update year range in copyright notice of binutils filesAlan Modra2023-01-01192-192/+192
| | | | | | The newer update-copyright.py fixes file encoding too, removing cr/lf on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
* PR29948, heap-buffer-overflow in display_debug_lines_decodedAlan Modra2022-12-301-2/+2
| | | | | | | | | | | | | | | | | | | This fixes a couple of places in display_debug_lines_decoded that were off by one in checking DWARF5 .debug_line directory indices. It also displays the DWARF5 entry 0 for the program current directory rather than "." as is done for pre-DWARF5. I decided against displaying DW_AT_comp_dir for pre-DWARF5 since I figure it is better for readelf to minimally interpret debug info. binutils/ PR 29948 * dwarf.c (display_debug_lines_decoded): Display the given directory entry 0 for DWARF5. Properly check directory index against number of entries in the table. Revert to using unsigned int for n_directories and associated variables. Correct warning messages. gas/ * testsuite/gas/elf/dwarf-5-loc0.d: Update.
* RISC-V: Fix T-Head Fmv vendor extension encodingChristoph Müllner2022-12-271-2/+2
| | | | | | | | | | A recent change in the XTheadFmv spec fixed an encoding bug in the document. This patch changes the code to follow this bugfix. Spec patch can be found here: https://github.com/T-head-Semi/thead-extension-spec/pull/11 Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* RISC-V: Relax the order checking for the architecture stringNelson Chu2022-12-237-14/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * riscv-toolchain-conventions, PR, https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/14 Issue, https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/11 * Refer to the commit afc41ffb, RISC-V: Reorder the prefixed extensions which are out of order. In the past we only allow to reorder the prefixed extensions. But according to the PR 14 in the riscv-toolchain-convention, we can also relax the order checking to allow the whole extensions be written out of orders, including the single standard extensions and the prefixed multi-letter extensions. Just that we still need to follow the following rules as usual, 1. prefixed extensions need to be seperated with `_'. 2. prefixed extensions need complete <major>.<minor> version if set. Please see the details in the march-ok-reorder gas testcase. Passed the riscv-gnu-toolchain regressions. bfd/ * elfxx-riscv.c (enum riscv_prefix_ext_class): Changed RV_ISA_CLASS_UNKNOWN to RV_ISA_CLASS_SINGLE, since everything that does not belong to the multi-keyword will possible be a single extension for the current parser. (parse_config): Likewise. (riscv_get_prefix_class): Likewise. (riscv_compare_subsets): Likewise. (riscv_parse_std_ext): Removed, and merged with riscv_parse_prefixed_ext into riscv_parse_extensions. (riscv_parse_prefixed_ext): Likewise. (riscv_parse_subset): Only need to call riscv_parse_extensions to parse both single standard and prefixed extensions. gas/ * testsuite/gas/riscv/march-fail-order-std.d: Removed since the relaxed order checking. * testsuite/gas/riscv/march-fail-order-std.l: Likewise. * testsuite/gas/riscv/march-fail-order-x-std.d: Likewise. * testsuite/gas/riscv/march-fail-order-z-std.d: Likewise. * testsuite/gas/riscv/march-fail-order-zx-std.l: Likewise. * testsuite/gas/riscv/march-fail-unknown-std.l: Updated. * testsuite/gas/riscv/march-ok-reorder.d: New testcase.
* gas: sframe: testsuite: add testcase for .cfi_b_key_frameIndu Bhagat2022-12-223-0/+64
| | | | | | | | | | | | | | This is actually a composite test that checks SFrame unwind information generation for both the .cfi_negate_ra_state and .cfi_b_key_frame directives on aarch64. ChangeLog: * testsuite/gas/cfi-sframe/cfi-sframe-aarch64-pac-ab-key-1.d: New test. * testsuite/gas/cfi-sframe/cfi-sframe-aarch64-pac-ab-key-1.s: Likewise. * testsuite/gas/cfi-sframe/cfi-sframe.exp: Run new test.
* gas: re-arrange listing output for .irp and alikeJan Beulich2022-12-221-2/+2
| | | | | | | | | | | It is kind of odd to have the expansions of such constructs ahead of their definition in listings with macro expansion enabled. Adjust this by pulling ahead the output of the definition lines, taking care to avoid producing a listing line for (non-existing) line 0 when the source is stdin. Note that with the code movement the conditional operator isn't necessary anymore - list->line now match up.
* x86: correct dependencies of a few AVX512 sub-featuresJan Beulich2022-12-221-6/+6
| | | | | | | Like AVX512-FP16, several other extensions require wider than 16-bit mask registers. As a result they take AVX512BW as a prereq, not (just) AVX512F. Which in turn points out wrong expectations in the noavx512-1 testcase.
* x86: rework noavx512-1 testcaseJan Beulich2022-12-223-587/+415
| | | | | | | | So far the set of ".noavx512*" has been accumulating, which isn't ideal. In particular this hides issues with dependencies between features. Switch back to the default ISA before disabling a particular subset. Furthermore limit redundancy by wrapping the repeated block of insns in an .irp.
* gas: sframe: testsuite: add testcase for .cfi_negate_ra_stateIndu Bhagat2022-12-163-0/+39
| | | | | | | | | | | | Add a new test to check that .cfi_negate_ra_state on aarch64 is handled well (a non-empty SFrame section with valid SFrame FREs is generated). ChangeLog: * testsuite/gas/cfi-sframe/cfi-sframe-aarch64-2.d: New test. * testsuite/gas/cfi-sframe/cfi-sframe-aarch64-2.s: Likewise. * testsuite/gas/cfi-sframe/cfi-sframe.exp: Adjust the list accordingly.
* gas: sframe: add support for .cfi_negate_ra_stateIndu Bhagat2022-12-163-32/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | DW_CFA_AARCH64_negate_ra_state in aarch64 is multiplexed with DW_CFA_GNU_window_save in the DWARF format. Remove the common-empty-4 testcase because the generated SFrame section will not be be empty anymore. A relevant test will be added in a later commit. ChangeLog: * gas/gen-sframe.c (sframe_v1_set_fre_info): Add new argument for mangled_ra_p. (sframe_set_fre_info): Likewise. (output_sframe_row_entry): Handle mangled_ra_p. (sframe_row_entry_new): Reset mangled_ra_p. (sframe_row_entry_initialize): Initialize mangled_ra_p. (sframe_xlate_do_gnu_window_save): New definition. (sframe_do_cfi_insn): Handle DW_CFA_GNU_window_save. * gas/gen-sframe.h (struct sframe_row_entry): New member. (struct sframe_version_ops): Add a new argument for mangled_ra_p. * gas/testsuite/gas/cfi-sframe/cfi-sframe.exp: Remove test. * gas/testsuite/gas/cfi-sframe/common-empty-4.d: Removed. * gas/testsuite/gas/cfi-sframe/common-empty-4.s: Removed.
* gas: restore Dwarf info generation after macro diagnostic adjustmentsJan Beulich2022-12-164-0/+26
| | | | | | | | | | | | While 6fdb723799e2 ("gas: re-work line number tracking for macros and their expansions") was meant to leave generated Dwarf as is, it really didn't (and the testcase intended to catch that wasn't covering the case which broke). Its adjustment to buffer_and_nest() didn't go far enough, leading to the "linefile" directive inserted at the top to also be processed later in the PR gas/16908 workaround (which clearly isn't intended - it's being put there for processing during macro expansion only). That unnoticed flaw in turn led me to work around it by a (suspicious to me already at the time) conditional in as_where().
* RISC-V: Add string length check for operands in ASLi Xu2022-12-143-0/+7
| | | | | | | | | | | | | | | | | | | The current AS accepts invalid operands due to miss of operands length check. For example, "e6" is an invalid operand in (vsetvli a0, a1, e6, mf8, tu, ma), but it's still accepted by assembler. In detail, the condition check "strncmp (array[i], *s, len) == 0" in arg_lookup function passes with "strncmp ("e64", "e6", 2)" in the case above. So the generated encoding is same as that of (vsetvli a0, a1, e64, mf8, tu, ma). This patch fixes issue above by prompting an error in such case and also adds a new testcase. gas/ChangeLog: * config/tc-riscv.c (arg_lookup): Add string length check for operands. * testsuite/gas/riscv/vector-insns-fail-vsew.d: New testcase for an illegal vsew. * testsuite/gas/riscv/vector-insns-fail-vsew.l: Likewise. * testsuite/gas/riscv/vector-insns-fail-vsew.s: Likewise.
* gas: re-work line number tracking for macros and their expansionsJan Beulich2022-12-1357-2537/+9605
| | | | | | | | | | | | | | | | | | The PR gas/16908 workaround aimed at uniformly reporting line numbers to reference macro invocation sites. As mentioned in a comment this may be desirable for small macros, but often isn't for larger ones. As a first step improve diagnostics to report both locations, while aiming at leaving generated debug info unaltered. Note that macro invocation context is lost for any diagnostics issued only after all input was processed (or more generally for any use of as_*_where(), as the functions can't know whether the passed in location is related to [part of] the present stack of locations). To maintain the intended workaround behavior for PR gas/16908, a new as_where() is introduced to "look through" macro invocations, while the existing as_where() is renamed (and used in only very few places for now). Down the road as_where() will likely want to return a list of (file,line) pairs.
* Arm: avoid unhelpful uses of .macro in testsuiteJan Beulich2022-12-13141-2306/+2237
| | | | | | | | | | Macros with just a single use site are a little pointless to have, and even in further cases .irp is more suitable for the purpose. Expand such inline, avoiding the need to touch the testcases when diagnostics are changed for code resulting from macro expansion. While there also make what was "iter_mla" in sp-usage-thumb2-relax cover smlatt as well, rather than testing smlabt twice.
* x86: further re-work insn/suffix recognition to also cover MOVSXJan Beulich2022-12-128-11/+184
| | | | | | | | | PR gas/29524 Having templates with a suffix explicitly present has always been quirky. After prior adjustment all that's left to also eliminate the anomaly from move-with-sign-extend is to consolidate the insn templates and to make may_need_pass2() cope (plus extend testsuite coverage).
* x86-64: allow HLE store of accumulator to absolute 32-bit addressJan Beulich2022-12-123-0/+24
| | | | | | | | | | | | | In commit 1212781b35c9 ("ix86: allow HLE store of accumulator to absolute address") I was wrong to exclude 64-bit code. Dropping the check also leads to better diagnostics in 64-bit code ("MOV", after all, isn't invalid with "XRELEASE"). While there also limit the amount of further checks done: The operand type checks that were there were effectively redundant with other ones anyway, plus it's quite fine to also have "xrelease mov <disp>, %eax" look for the next MOV template (in fact again also improving diagnostics).
* ix86: don't recognize/derive Q suffix in the common caseJan Beulich2022-12-1212-26/+59
| | | | | | | | | | | | | | | | | | Have its use, except where actually legitimate, result in the same "only supported in 64-bit mode" diagnostic as emitted for other 64-bit only insns. Also suppress deriving of the suffix in Intel mode except in the legitimate cases. This in exchange allows dropping the respective code from match_template(). To maintain reasonable diagnostics (in particular to avoid "`mov' is only supported in 64-bit mode" on the SIMD forms of MOVQ) we need to defer parse_insn()'s emitting of errors unrelated to prefix parsing. Utilize i.error just like match_template() does. Oddly enough despite gcc's preference towards FILDQ and FIST{,T}Q we had no testcase whatsoever for these. Therefore such tests are being added. Note that the removed line in the x86-64-lfence-load testcase was redundant with the exact same one a few lines up.
* x86: re-work insn/suffix recognitionJan Beulich2022-12-125-4/+26
| | | | | | | | | | | | | | | | | | | | | | | | | Having templates with a suffix explicitly present has always been quirky. Introduce a 2nd matching pass in case the 1st one couldn't find a suitable template _and_ didn't itself already need to trim off a suffix to find a match at all. This requires error reporting adjustments (albeit luckily fewer than I was afraid might be necessary), as errors previously reported during matching now need deferring until after the 2nd pass (because, obviously, we must not emit any error if the 2nd pass succeeds). While also related to PR gas/29524, it was requested that move-with-sign-extend be left as broken as it always was. PR gas/29525 Note that with the dropped CMPSD and MOVSD Intel Syntax string insn templates taking operands, mixed IsString/non-IsString template groups (with memory operands) cannot occur anymore. With that maybe_adjust_templates() becomes unnecessary (and is hence being removed). PR gas/29526 Note further that while the additions to the intel16 testcase aren't really proper Intel syntax, we've been permitting all of those except for the MOVD variant. The test therefore is to avoid re-introducing such an inconsistency.
* x86: revert disassembler parts of "x86: Allow 16-bit register source for LAR ↵Jan Beulich2022-12-126-52/+52
| | | | | | | | | | | | and LSL" This reverts the disassembler parts of 859aa2c86dc9 ("x86: Allow 16-bit register source for LAR and LSL"), adjusting testcases as necessary. That change was itself a partial revert of c9f5b96bdab0 ("x86: correct handling of LAR and LSL"), without actually saying so. While the earlier commit was properly agreed upon, the partial revert was not, and hence should not have been committed. This is even more so that the revert part of that change wasn't even necessary to address PR gas/29844.
* PowerPC: Add support for RFC02655 - Saturating Subtract InstructionPeter Bergner2022-12-075-0/+52
| | | | | | | | | | | | | | opcodes/ * ppc-opc.c (XOL): New define. (XOL_MASK): Likewise. (powerpc_opcodes): Add subfus, subfus., subwus, subwus., subdus, subdus. gas/ * testsuite/gas/ppc/rfc02655.s: New test. * testsuite/gas/ppc/rfc02655.d: Likewise * testsuite/gas/ppc/future-raw.s: Likewise. * testsuite/gas/ppc/future-raw.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run them.
* PowerPC: Add support for RFC02656 - Enhanced Load Store with Length InstructionsPeter Bergner2022-12-073-0/+30
| | | | | | | | | | | | opcodes/ * ppc-opc.c (PPCVSXF): New define. (powerpc_opcodes): Add lxvrl, lxvrll, lxvprl, lxvprll, stxvrl, stxvrll, stxvprl, stxvprl. gas/ * testsuite/gas/ppc/rfc02656.s: New test. * testsuite/gas/ppc/rfc02656.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run it.
* gas: add Dwarf line number test for .macro expansionsJan Beulich2022-12-053-0/+56
| | | | | Before fiddling with the code let's put in place a test covering what PR/gas 16908 aimed at.
* opcodes/mips: use .word/.short for undefined instructionsAndrew Burgess2022-12-0513-514/+514
| | | | | | | | | | | | | While working on disassembler styling for MIPS, I noticed that undefined instructions are printed by the disassembler as raw number with no assembler directive prefix (e.g. without .word or .short). I think adding something like .word, or .short, helps to make it clearer the size of the value that is being displayed, and is inline with what many of the other libopcode disassemblers do. In this commit I've added the .word and .short directives, and updated all the tests that I spotted that failed as a result.
* x86: Allow 16-bit register source for LAR and LSLH.J. Lu2022-12-0310-8/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since LAR and LSL only access 16 bits of the source operand, regardless of operand size, allow 16-bit register source for LAR and LSL, and always disassemble LAR and LSL with 16-bit source operand. gas/ PR gas/29844 * testsuite/gas/i386/i386.s: Add tests for LAR and LSL. * testsuite/gas/i386/x86_64.s: Likewise. * testsuite/gas/i386/intelbad.s: Remove "lar/lsl eax, ax". * testsuite/gas/i386/i386-intel.d: Updated. * testsuite/gas/i386/i386.d: Likewise. * testsuite/gas/i386/intel-intel.d: Likewise. * testsuite/gas/i386/intel.d: Likewise. * testsuite/gas/i386/intelbad.l: Likewise. * testsuite/gas/i386/x86_64-intel.d: Likewise. * testsuite/gas/i386/x86_64.d: Likewise. opcodes/ PR gas/29844 * i386-dis.c (MOD_0F02): Removed. (MOD_0F03): Likewise. (dis386_twobyte): Restore larS and lslS. (mod_table): Remove MOD_0F02 and MOD_0F03. * i386-opc.tbl: Allow 16-bit register source for LAR and LSL. * i386-tbl.h: Regenerated.
* x86: extend FPU test coverage for AT&T / Intel mnemonic differencesJan Beulich2022-11-305-0/+44
| | | | | | Before touching the templates, let's ensure we actually cover things: For one FSUB{,R} and FDIV{,R} would better be tested with operands in both possible orders. And then -mmnemonic=intel wasn't tested at all.
* RISC-V: Better support for long instructions (tests)Tsukasa OI2022-11-284-1/+48
| | | | | | | | | | | | | | This commit tests both (assembler and disassembler) fixes of "Better support for long instructions". gas/ChangeLog: * testsuite/gas/riscv/insn.s: Add testcases such that big number handling is required and should be disassembled as long ".byte" sequence with correct instruction bits. * testsuite/gas/riscv/insn.d: Likewise. * testsuite/gas/riscv/insn-na.d: Likewise. * testsuite/gas/riscv/insn-dwarf.d: Likewise.
* riscv: Add AIA extension support (Smaia, Ssaia)Christoph Müllner2022-11-2511-0/+860
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds the AIA extensions (Smaia and Ssaia) CSRs. bfd/ChangeLog: * elfxx-riscv.c: Add 'smaia' and 'ssaia' to the list of known standard extensions. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): (riscv_csr_address): Add CSR classes for Smaia/Ssaia. * testsuite/gas/riscv/csr-dw-regnums.d: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (CSR_MISELECT): New CSR macro. (CSR_MIREG): Likewise. (CSR_MTOPEI): Likewise. (CSR_MTOPI): Likewise. (CSR_MVIEN): Likewise. (CSR_MVIP): Likewise. (CSR_MIDELEGH): Likewise. (CSR_MIEH): Likewise. (CSR_MVIENH): Likewise. (CSR_MVIPH): Likewise. (CSR_MIPH): Likewise. (CSR_SISELECT): Likewise. (CSR_SIREG): Likewise. (CSR_STOPEI): Likewise. (CSR_STOPI): Likewise. (CSR_SIEH): Likewise. (CSR_SIPH): Likewise. (CSR_HVIEN): Likewise. (CSR_HVICTL): Likewise. (CSR_HVIPRIO1): Likewise. (CSR_HVIPRIO2): Likewise. (CSR_VSISELECT): Likewise. (CSR_VSIREG): Likewise. (CSR_VSTOPEI): Likewise. (CSR_VSTOPI): Likewise. (CSR_HIDELEGH): Likewise. (CSR_HVIENH): Likewise. (CSR_HVIPH): Likewise. (CSR_HVIPRIO1H): Likewise. (CSR_HVIPRIO2H): Likewise. (CSR_VSIEH): Likewise. (CSR_VSIPH): Likewise. (DECLARE_CSR): Add CSRs for Smaia and Ssaia. Changes for v3: - Imply ssaia for smaia - Imply zicsr for ssaia (and transitively smaia) - Move hypervisor CSRs to Ssaia+H - Rebase on upstream/master Changes for v2: - Add hypervisor and VS CSRs - Fix whitespace issue Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* x86: widen applicability and use of CheckRegSizeJan Beulich2022-11-242-0/+60
| | | | | | | | | | | | | | | | | | | | | | | First of all make operand_type_register_match() apply to all sized operands, i.e. in Intel Syntax also to respective memory ones. This addresses gas wrongly accepting certain SIMD insns where register and memory operand sizes should match but don't. This apparently has affected all templates with one memory-only operand and one or more register ones, both permitting at least two sizes, due to CheckRegSize not taking effect. Then also add CheckRegSize to a couple of non-SIMD templates matching that same pattern of memory-only vs register operands. This replaces bogus (for Intel Syntax) diagnostics referring to a wrong suffix (when none was used at all) by "type mismatch" ones, just like already emitted for insns where the template allows a register operand alongside a memory one at any particular position. This also is a prereq to limiting (ideally eliminating in the long run) suffix "derivation" in Intel Syntax mode. While making the code adjustment also flip order of checks to do the cheaper one first in both cases.
* x86: correct handling of LAR and LSLJan Beulich2022-11-245-19/+63
| | | | | | | | Both uniformly only ever take 16-bit memory operands while at the same time requiring matching (in size) register operands, which then also should disassemble that way. This in particular requires splitting each of the templates for the assembler and separating decode of the register and memory forms in the disassembler.
View Lorry Controller Status