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| author | Jan Beulich <jbeulich@suse.com> | 2023-01-31 09:47:22 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2023-01-31 09:47:22 +0100 |
| commit | a3c2d248683e13aafa7362e3da278080a5bb5954 (patch) | |
| tree | 1fa567e7ea7f7fbabb9d58d224edc05a86f607a8 /gas/testsuite | |
| parent | b3a3d7d90800b7c21ce8d82dbdbf17eeab163c7b (diff) | |
| download | binutils-gdb-a3c2d248683e13aafa7362e3da278080a5bb5954.tar.gz | |
RISC-V: make C-extension JAL available again for (32-bit) assembly
Along with the normal JAL alias, the C-extension one should have been
moved as well by 839189bc932e ("RISC-V: re-arrange opcode table for
consistent alias handling"), for the assembler to actually be able to
use it where/when possible.
Since neither this nor any other compressed branch insn was being tested
so far, take the opportunity and introduce a new testcase covering those.
Diffstat (limited to 'gas/testsuite')
| -rw-r--r-- | gas/testsuite/gas/riscv/c-branch-na.d | 20 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/c-branch.d | 19 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/c-branch.s | 11 |
3 files changed, 50 insertions, 0 deletions
diff --git a/gas/testsuite/gas/riscv/c-branch-na.d b/gas/testsuite/gas/riscv/c-branch-na.d new file mode 100644 index 00000000000..dcfcb293735 --- /dev/null +++ b/gas/testsuite/gas/riscv/c-branch-na.d @@ -0,0 +1,20 @@ +#as: -march=rv32ic +#source: c-branch.s +#objdump: -drw -Mno-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+ <target>: +[ ]+[0-9a-f]+:[ ]+c001[ ]+c\.beqz[ ]+s0,0 <target>[ ]+0: R_RISCV_RVC_BRANCH .* +[ ]+[0-9a-f]+:[ ]+dcfd[ ]+c\.beqz[ ]+s1,0 <target>[ ]+2: R_RISCV_RVC_BRANCH .* +[ ]+[0-9a-f]+:[ ]+fc75[ ]+c\.bnez[ ]+s0,0 <target>[ ]+4: R_RISCV_RVC_BRANCH .* +[ ]+[0-9a-f]+:[ ]+fced[ ]+c\.bnez[ ]+s1,0 <target>[ ]+6: R_RISCV_RVC_BRANCH .* +[ ]+[0-9a-f]+:[ ]+bfe5[ ]+c\.j[ ]+0 <target>[ ]+8: R_RISCV_RVC_JUMP .* +[ ]+[0-9a-f]+:[ ]+3fdd[ ]+c\.jal[ ]+0 <target>[ ]+a: R_RISCV_RVC_JUMP .* +[ ]+[0-9a-f]+:[ ]+9302[ ]+c\.jalr[ ]+t1 +[ ]+[0-9a-f]+:[ ]+8382[ ]+c\.jr[ ]+t2 +[ ]+[0-9a-f]+:[ ]+8082[ ]+c\.jr[ ]+ra +#... diff --git a/gas/testsuite/gas/riscv/c-branch.d b/gas/testsuite/gas/riscv/c-branch.d new file mode 100644 index 00000000000..253dcfb9b22 --- /dev/null +++ b/gas/testsuite/gas/riscv/c-branch.d @@ -0,0 +1,19 @@ +#as: -march=rv64ic +#objdump: -drw + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+ <target>: +[ ]+[0-9a-f]+:[ ]+c001[ ]+beqz[ ]+s0,0 <target>[ ]+0: R_RISCV_RVC_BRANCH .* +[ ]+[0-9a-f]+:[ ]+dcfd[ ]+beqz[ ]+s1,0 <target>[ ]+2: R_RISCV_RVC_BRANCH .* +[ ]+[0-9a-f]+:[ ]+fc75[ ]+bnez[ ]+s0,0 <target>[ ]+4: R_RISCV_RVC_BRANCH .* +[ ]+[0-9a-f]+:[ ]+fced[ ]+bnez[ ]+s1,0 <target>[ ]+6: R_RISCV_RVC_BRANCH .* +[ ]+[0-9a-f]+:[ ]+bfe5[ ]+j[ ]+0 <target>[ ]+8: R_RISCV_RVC_JUMP .* +[ ]+[0-9a-f]+:[ ]+ff7ff0ef[ ]+jal[ ]+0 <target>[ ]+a: R_RISCV_JAL .* +[ ]+[0-9a-f]+:[ ]+9302[ ]+jalr[ ]+t1 +[ ]+[0-9a-f]+:[ ]+8382[ ]+jr[ ]+t2 +[ ]+[0-9a-f]+:[ ]+8082[ ]+ret +#... diff --git a/gas/testsuite/gas/riscv/c-branch.s b/gas/testsuite/gas/riscv/c-branch.s new file mode 100644 index 00000000000..34cb3a4f38e --- /dev/null +++ b/gas/testsuite/gas/riscv/c-branch.s @@ -0,0 +1,11 @@ + .text +target: + beq x8, x0, target + beqz x9, target + bne x8, x0, target + bnez x9, target + j target + jal target + jalr x6 + jr x7 + ret |