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* gas: Add --gcodeview optionMark Harmstone2022-11-234-0/+342
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* Fix ARM and AArch64 assembler tests to work in a multi-arch environment.Nick Clifton2022-11-214-4/+4
| | | | | | | | | | | | | | | | PR 29764 gas * testsuite/gas/arm/cpu-cortex-a76ae.d: Add arm prefix to the -m option passed to objdump. * testsuite/gas/arm/cpu-cortex-a77.d: Likewise. * testsuite/gas/aarch64/cpu-cortex-a76ae.d: Add aarch64 prefix to the -m option passed to objdump. * testsuite/gas/aarch64/cpu-cortex-a77.d: Likewise. bfd * cpu-arm.c (scan): Accept machine names prefixed with "arm:". * cpu-aarch64.c (scan): Accept machine names prefixed with "aarch64:". bin * doc/binutils.texi (objdump): Note that the -m option supports the <architecture>:<machine> syntax.
* RISC-V: Add 'Ssstateen' extension and its CSRsTsukasa OI2022-11-198-97/+154
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds 'Ssstateen' extension, which is a supervisor-visible view of the 'Smstateen' extension. It means, this extension implements sstateen* and hstateen* CSRs of the 'Smstateen' extension. Note that 'Smstateen' extension itself is unchanged but due to implementation simplicity, it is implemented so that 'Smstateen' implies 'Ssstateen' (just like 'M' implies 'Zmmul'). This is based on the latest version of RISC-V Profiles (version 0.9-draft, Frozen): <https://github.com/riscv/riscv-profiles/commit/226b7f643067b29abc6723fac60d5f6d3f9eb901> bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Update implication rules. (riscv_supported_std_s_ext) Add 'Ssstateen' extension. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Rename CSR_CLASS_SMSTATEEN_AND_H{,_32} to CSR_CLASS_SSSTATEEN_... Add CSR_CLASS_SSSTATEEN. (riscv_csr_address): Support new/renamed CSR classes. * testsuite/gas/riscv/csr.s: Add 'Ssstateen' extension to comment. * testsuite/gas/riscv/csr-version-1p9p1.l: Reflect changes to error messages. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/ssstateen-csr.s: Test for 'Ssstateen' CSRs. * testsuite/gas/riscv/ssstateen-csr.d: Likewise. * testsuite/gas/riscv/smstateen-csr-s.d: Test to make sure that supervisor/hypervisor part of 'Smstateen' CSRs are accessible from 'RV32IH_Smstateen', not just from 'RV32IH_Ssstateen' that is tested in ssstateen-csr.d. include/ChangeLog: * opcode/riscv-opc.h: Update DECLARE_CSR declarations with new CSR classes.
* RISC-V: Add T-Head Int vendor extensionChristoph Müllner2022-11-172-0/+14
| | | | | | | | | | | | This patch adds the XTheadInt extension, which provides interrupt stack management instructions. The XTheadFmv extension is documented in the RISC-V toolchain contentions: https://github.com/riscv-non-isa/riscv-toolchain-conventions Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* RISC-V: Add T-Head Fmv vendor extensionChristoph Müllner2022-11-172-0/+14
| | | | | | | | | | | | This patch adds the XTheadFmv extension, which allows to access the upper 32 bits of a double-precision floating-point register in RV32. The XTheadFmv extension is documented in the RISC-V toolchain contentions: https://github.com/riscv-non-isa/riscv-toolchain-conventions Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* gas: testsuite: add new tests for SFrame unwind infoIndu Bhagat2022-11-1529-0/+533
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Earlier these tests were in the same commit as previous which adds the support in GNU assembler to generate .sframe section from CFI directives. Splitting this out here for ease of applying and testing. ChangeLog: * gas/testsuite/gas/cfi-sframe/cfi-sframe-aarch64-1.d: New file. * gas/testsuite/gas/cfi-sframe/cfi-sframe-aarch64-1.s: Likewise. * gas/testsuite/gas/cfi-sframe/cfi-sframe-common-1.d: Likewise. * gas/testsuite/gas/cfi-sframe/cfi-sframe-common-1.s: Likewise. * gas/testsuite/gas/cfi-sframe/cfi-sframe-common-2.d: Likewise. * gas/testsuite/gas/cfi-sframe/cfi-sframe-common-2.s: Likewise. * gas/testsuite/gas/cfi-sframe/cfi-sframe-common-3.d: Likewise. * gas/testsuite/gas/cfi-sframe/cfi-sframe-common-3.s: Likewise. * gas/testsuite/gas/cfi-sframe/cfi-sframe-common-4.d: Likewise. * gas/testsuite/gas/cfi-sframe/cfi-sframe-common-4.s: Likewise. * gas/testsuite/gas/cfi-sframe/cfi-sframe-common-5.d: Likewise. * gas/testsuite/gas/cfi-sframe/cfi-sframe-common-5.s: Likewise. * gas/testsuite/gas/cfi-sframe/cfi-sframe-common-6.d: Likewise. * gas/testsuite/gas/cfi-sframe/cfi-sframe-common-6.s: Likewise. * gas/testsuite/gas/cfi-sframe/cfi-sframe-common-7.d: Likewise. * gas/testsuite/gas/cfi-sframe/cfi-sframe-common-7.s: Likewise. * gas/testsuite/gas/cfi-sframe/cfi-sframe-common-8.d: Likewise. * gas/testsuite/gas/cfi-sframe/cfi-sframe-common-8.s: Likewise. * gas/testsuite/gas/cfi-sframe/cfi-sframe-x86_64-1.d: Likewise. * gas/testsuite/gas/cfi-sframe/cfi-sframe-x86_64-1.s: Likewise. * gas/testsuite/gas/cfi-sframe/cfi-sframe.exp: Likewise. * gas/testsuite/gas/cfi-sframe/common-empty-1.d: Likewise. * gas/testsuite/gas/cfi-sframe/common-empty-1.s: Likewise. * gas/testsuite/gas/cfi-sframe/common-empty-2.d: Likewise. * gas/testsuite/gas/cfi-sframe/common-empty-2.s: Likewise. * gas/testsuite/gas/cfi-sframe/common-empty-3.d: Likewise. * gas/testsuite/gas/cfi-sframe/common-empty-3.s: Likewise. * gas/testsuite/gas/cfi-sframe/common-empty-4.d: Likewise. * gas/testsuite/gas/cfi-sframe/common-empty-4.s: Likewise.
* Re: [gas] arm: Add support for new unwinder directive ".pacspval".Alan Modra2022-11-161-4/+5
| | | | * testsuite/gas/arm/ehabi-pacbti-m.d: Limit test to ELF.
* Add AMD znver4 processor supportTejas Joshi2022-11-159-0/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2022-09-28 Tejas Joshi <TejasSanjay.Joshi@amd.com> gas/ * config/tc-i386.c (cpu_arch): Add znver4 ARCH and rmpquery SUBARCH. (md_assemble): Expand comment before swap_operands() with rmpquery. * doc/c-i386.texi: Add znver4. * testsuite/gas/i386/arch-14-1.d: New. * testsuite/gas/i386/arch-14-1.s: New. * testsuite/gas/i386/arch-14-znver4.d: New. * testsuite/gas/i386/i386.exp: Add new znver4 test cases. * testsuite/gas/i386/rmpquery.d: New. * testsuite/gas/i386/rmpquery.s: New. * testsuite/gas/i386/x86-64-arch-4-1.d: New. * testsuite/gas/i386/x86-64-arch-4-1.s: New. * testsuite/gas/i386/x86-64-arch-4-znver4.d: New. opcodes/ * i386-dis.c (x86_64_table): Add rmpquery. * i386-gen.c (cpu_flag_init): Add CPU_ZNVER4_FLAGS and CPU_RMPQUERY_FLAGS. (cpu_flags): Add CpuRMPQUERY. * i386-opc.h (enum): Add CpuRMPQUERY. (i386_cpu_flags): Add cpurmpquery. * i386-opc.tbl: Add rmpquery insn. * i386-init.h: Re-generated. * i386-tbl.h: Re-generated.
* aarch64, testsuite: Fixed recently added cssc.dAndre Vieira2022-11-151-7/+0
| | | | | | | | Fixed wrong paste in cssc.d. gas/ChangeLog: * testsuite/gas/aarch64/cssc.d: Removed duplicate head.
* aarch64: Add support for Common Short Sequence Compression extensionAndre Vieira2022-11-142-0/+334
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the CSSC extension and its corresponding instructions: ABS, CNT, CTZ, SMAX, UMAX, SMIN, UMIN. gas/ChangeLog: * config/tc-aarch64.c (parse_operands): Handle new operand types. * doc/c-aarch64.texi: Document new extension. * testsuite/gas/aarch64/cssc.d: New test. * testsuite/gas/aarch64/cssc.s: New test. include/ChangeLog: * opcode/aarch64.h (AARCH64_FEATURE_CSSC): New feature Macro. (enum aarch64_opnd): New operand types. (enum aarch64_insn_class): New instruction class. opcodes/ChangeLog: * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-opc.c (operand_general_constraint_met_p): Update for new operand types. (aarch64_print_operand): Likewise. * aarch64-opc.h (enum aarch64_field_kind): Declare FLD_CSSC_imm8 field. * aarch64-tbl.h (aarch64_feature_cssc): Define new feature set. (CSSC): Define new feature set Macro. (CSSC_INSN): Define new instruction type. (aarch64_opcode_table): Add new instructions.
* [gas] arm: Add support for new unwinder directive ".pacspval".Srinath Parvathaneni2022-11-142-0/+53
| | | | | | | | | | | | | | | | | This patch adds the assembler support for the new unwinder directive ".pacspval" and encodes this directives with opcode "0xb5". This opcode indicates the unwinder to use effective vsp as modifier for PAC validation. gas/ChangeLog: 2022-11-07 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * doc/c-arm.texi: Document directive. * config/tc-arm.c (s_arm_unwind_pacspval): Define function. (md_pseudo_table): Add entry for pacspval directive. * testsuite/gas/arm/ehabi-pacbti-m.d: New test. * testsuite/gas/arm/ehabi-pacbti-m.s: Likewise.
* arm: Add support for Cortex-X1C CPU.Srinath Parvathaneni2022-11-141-0/+6
| | | | | | | | | | | | | | | | | | | This patch adds support for Cortex-X1C CPU in Arm. bfd/ChangeLog: 2022-11-09 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * cpu-arm.c (processors): Add Cortex-X1C CPU entry. gas/ChangeLog: 2022-11-09 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * NEWS: Update docs. * config/tc-arm.c (arm_cpus): Add cortex-x1c to -mcpu. * doc/c-arm.texi: Update docs. * testsuite/gas/arm/cpu-cortex-x1c.d: New test.
* PowerPC64 paddi -MrawAlan Modra2022-11-122-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On a testcase like pla 8,foo@pcrel disassembled with -Mpower10 results in 0: 00 00 10 06 pla r8,0 # 0 4: 00 00 00 39 0: R_PPC64_PCREL34 foo but with -Mpower10 -Mraw 0: 00 00 10 06 .long 0x6100000 0: R_PPC64_PCREL34 foo 4: 00 00 00 39 addi r8,0,0 The instruction is unrecognised due to the hack we have in extract_pcrel0 in order to disassemble paddi with RA0=0 and R=1 as pla. I could have just added "&& !(dialect & PPC_OPCODE_RAW)" to the condition in extract_pcrel0 under which *invalid is set, but went for this larger patch that reorders the extended insn pla to the more usual place before its underlying machine insn. (la is after addi because we never disassemble to la.) gas/ * testsuite/gas/ppc/raw.d, * testsuite/gas/ppc/raw.s: Add pla. opcodes/ * ppc-opc.c (extract_pcrel1): Rename from extract_pcrel0 and invert *invalid logic. (PCREL1): Rename from PCREL0. (prefix_opcodes): Sort pla before paddi, adjusting R operand for pla, paddi and psubi.
* i386: Check invalid (%dx) usageH.J. Lu2022-11-104-0/+28
| | | | | | | | | | | | | | | | | | | (%dx) isn't a valid memory address in any modes. It is used as a special memory operand for input/output port address in AT&T syntax and should only be used with input/output instructions. Update i386_att_operand to set i.input_output_operand to true for (%dx) and issue an error if (%dx) is used with non-input/output instructions. PR gas/29751 * config/tc-i386.c (_i386_insn): Add input_output_operand. (md_assemble): Issue an error if input/output memory operand is used with non-input/output instructions. (i386_att_operand): Set i.input_output_operand to true for (%dx). * testsuite/gas/i386/inval.l: Updated. * testsuite/gas/i386/x86-64-inval.l: Likewise. * testsuite/gas/i386/inval.s: Add tests for invalid (%dx) usage. * testsuite/gas/i386/x86-64-inval.s: Likewise.
* x86/Intel: don't accept malformed EXTRQ / INSERTQJan Beulich2022-11-093-15/+15
| | | | | | | | | | Operand swapping was mistakenly suppressed when the first two operands were immediate ones, not taking into account overall operand count. This way EXTRQ / INSERTQ would have been accepted also with kind-of-AT&T operand order. For the testcase being extended, in order to not move around "GAS LISTING" expectations, suppress pagination.
* RISC-V: xtheadfmemidx: Use fp register in mnemonicsChristoph Müllner2022-11-094-48/+50
| | | | | | | | | | | | | | | | | | | | | | Although the encoding for scalar and fp registers is identical, we should follow common pratice and use fp register names when referencing fp registers. The xtheadmemidx extension consists of indirect load/store instructions which all load to or store from fp registers. Let's use fp register names in this case and adjust the test cases accordingly. gas/ * testsuite/gas/riscv/x-thead-fmemidx-fail.l: Updated since rd need to be float register. * testsuite/gas/riscv/x-thead-fmemidx-fail.s: Likewise. * testsuite/gas/riscv/x-thead-fmemidx.d: Likewise. * testsuite/gas/riscv/x-thead-fmemidx.s: Likewise. opcodes/ * riscv-opc.c (riscv_opcodes): Updated since rd need to be float register. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* Support Intel RAO-INTKong Lingling2022-11-087-0/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ChangeLog: * NEWS: Support Intel RAO-INT. * config/tc-i386.c: Add raoint. * doc/c-i386.texi: Document .raoint. * testsuite/gas/i386/i386.exp: Run RAO_INT tests. * testsuite/gas/i386/raoint-intel.d: New test. * testsuite/gas/i386/raoint.d: Ditto. * testsuite/gas/i386/raoint.s: Ditto. * testsuite/gas/i386/x86-64-raoint-intel.d: Ditto. * testsuite/gas/i386/x86-64-raoint.d: Ditto. * testsuite/gas/i386/x86-64-raoint.s: Ditto. opcodes/ChangeLog: * i386-dis.c (PREFIX_0F38FC): New. (prefix_table): Add PREFIX_0F38FC. * i386-gen.c: (cpu_flag_init): Add CPU_RAO_INT_FLAGS and CPU_ANY_RAO_INT_FLAGS. * i386-init.h: Regenerated. * i386-opc.h: (CpuRAO_INT): New. (i386_cpu_flags): Add cpuraoint. * i386-opc.tbl: Add RAO_INT instructions. * i386-tbl.h: Regenerated.
* RISC-V: Remove RV32EF conflictTsukasa OI2022-11-072-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Despite that the RISC-V ISA Manual version 2.2 prohibited "RV32EF", later versions beginning with the version 20190608-Base-Ratified removed this restriction. Because the 'E' extension is still a draft, the author chose to *just* remove the conflict (not checking the ISA version). Note that, because RV32E is only used with a soft-float calling convention, there's no valid official ABI for RV32EF. It means, even if we can assemble a program with -march=rv32ef -mabi=ilp32e, floating-point registers are kept in an unmanaged state (outside ABI management). The purpose of this commit is to suppress unnecessary errors while parsing an ISA string and/or disassembling, not to allow hard-float with RVE. bfd/ChangeLog: * elfxx-riscv.c (riscv_parse_check_conflicts): Accept RV32EF because only older specifications disallowed it. gas/ChangeLog: * testsuite/gas/riscv/march-fail-rv32ef.d: Remove as not directly prohibited. * testsuite/gas/riscv/march-fail-rv32ef.l: Likewise.
* x86: adjust recently introduced testcasesJan Beulich2022-11-048-0/+8
| | | | | The issue addressed by 2c02c72c62d2 ("re: Support Intel AMX-FP16") has been introduced once again in a number of new tests.
* Support Intel AVX-NE-CONVERTkonglin12022-11-047-0/+1018
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ChangeLog: * NEWS: Support Intel AVX-NE-CONVERT. * config/tc-i386.c: Add avx_ne_convert. * doc/c-i386.texi: Document .avx_ne_convert. * testsuite/gas/i386/i386.exp: Run AVX NE CONVERT tests. * testsuite/gas/i386/avx-ne-convert-intel.d: New test. * testsuite/gas/i386/avx-ne-convert.d: Ditto. * testsuite/gas/i386/avx-ne-convert.s: Ditto. * testsuite/gas/i386/x86-64-avx-ne-convert-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx-ne-convert.d: Ditto. * testsuite/gas/i386/x86-64-avx-ne-convert.s: Ditto. opcodes/ChangeLog: * i386-dis.c (Mw): New. (PREFIX_VEX_0F3872): Ditto. (PREFIX_VEX_0F38B0_W_0): Ditto. (PREFIX_VEX_0F38B1_W_0): Ditto. (VEX_W_0F3872_P_1): Ditto. (VEX_W_0F38B0): Ditto. (VEX_W_0F38B1): Ditto. (prefix_table): Add PREFIX_VEX_0F3872, PREFIX_VEX_0F38B0_W_0, PREFIX_VEX_0F38B1_W_0. (vex_w_table): Add VEX_W_0F3872_P_1, VEX_W_0F38B0, VEX_W_0F38B1. * i386-gen.c (cpu_flag_init): Add CPU_AVX_NE_CONVERT_FLGAS and CPU_ANY_AVX_NE_CONVERT_FLAGS. (cpu_flags): Add CpuAVX_NE_CONVERT. * i386-init.h: Regenerated. * i386-opc.h (CpuAVX_NE CONVERT): New. (i386_cpu_flags): Add cpuavx_ne_convert. * i386-opc.tbl: Add Intel AVX-NE-CONVERT instructions. * i386-tbl.h: Regenerated.
* RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment.Nelson Chu2022-11-023-9/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Consider the case, .option arch, rv32i .option norelax .option arch, +c .byte 1 .align 2 addi a0, zero, 1 Assembler adds $d for the odd .byte, and then adds $x+arch for the alignment. Since norelax, riscv_add_odd_padding_symbol will add the $d and $x for the odd alignment, but accidently remove the $x+arch because it has the same address as $d. Therefore, we will get the unexpected result before applying this patch, .byte 1 # $d .align 2 # odd alignment, $xrv32ic replaced by $d + $x After this patch, the expected result should be, .byte 1 # $d .align 2 # odd alignment, $xrv32ic replaced by $d + $xrv32ic gas/ * config/tc-riscv.c (make_mapping_symbol): If we are adding mapping symbol for odd alignment, then we probably will remove the $x+arch by accidently when it has the same address of $d. Try to add the removed $x+arch back after the $d rather than just $x. (riscv_mapping_state): Updated since parameters of make_mapping_symbol are changed. (riscv_add_odd_padding_symbol): Likewise. (riscv_remove_mapping_symbol): Removed and moved the code into the riscv_check_mapping_symbols. (riscv_check_mapping_symbols): Updated. * testsuite/gas/riscv/mapping-dis.d: Updated and added new testcase. * testsuite/gas/riscv/mapping-symbols.d: Likewise. * testsuite/gas/riscv/mapping.s: Likewise.
* Support Intel MSRLISTHu, Lin12022-11-026-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ChangeLog: * NEWS: Support Intel MSRLIST. * config/tc-i386.c: Add msrlist. * doc/c-i386.texi: Document .msrlist. * testsuite/gas/i386/i386.exp: Add MSRLIST tests. * testsuite/gas/i386/msrlist-inval.l: New test. * testsuite/gas/i386/msrlist-inval.s: Ditto. * testsuite/gas/i386/x86-64-msrlist-intel.d: Ditto. * testsuite/gas/i386/x86-64-msrlist.d: Ditto. * testsuite/gas/i386/x86-64-msrlist.s: Ditto. opcodes/ChangeLog: * i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_6_P_1): New. (X86_64_0F01_REG_0_MOD_3_RM_6_P_3): Ditto. (prefix_table): New entry for msrlist. (x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_6_P_1 and X86_64_0F01_REG_0_MOD_3_RM_6_P_3. * i386-gen.c (cpu_flag_init): Add CPU_MSRLIST_FLAGS and CPU_ANY_MSRLIST_FLAGS. * i386-init.h: Regenerated. * i386-opc.h (CpuMSRLIST): New. (i386_cpu_flags): Add cpumsrlist. * i386-opc.tbl: Add MSRLIST instructions. * i386-tbl.h: Regenerated.
* Support Intel WRMSRNSHu, Lin12022-11-026-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ChangeLog: * NEWS: Support Intel WRMSRNS. * config/tc-i386.c: Add wrmsrns. * doc/c-i386.texi: Document .wrmsrns. * testsuite/gas/i386/i386.exp: Add WRMSRNS tests. * testsuite/gas/i386/wrmsrns-intel.d: New test. * testsuite/gas/i386/wrmsrns.d: Ditto. * testsuite/gas/i386/wrmsrns.s: Ditto. * testsuite/gas/i386/x86-64-wrmsrns-intel.d: Ditto. * testsuite/gas/i386/x86-64-wrmsrns.d: Ditto. opcodes/ChangeLog: * i386-dis.c (PREFIX_0F01_REG_0_MOD_3_RM_6): New. (prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_6. (rm_table): New entry for wrmsrns. * i386-gen.c (cpu_flag_init): Add CPU_WRMSRNS_FLAGS and CPU_ANY_WRMSRNS_FLAGS. (cpu_flags): Add CpuWRMSRNS. * i386-init.h: Regenerated. * i386-opc.h (CpuWRMSRNS): New. (i386_cpu_flags): Add cpuwrmsrns. * i386-opc.tbl: Add WRMSRNS instructions. * i386-tbl.h: Regenerated.
* Support Intel CMPccXADDHaochen Jiang2022-11-026-0/+812
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ChangeLog: * NEWS: Support Intel CMPccXADD. * config/tc-i386.c: Add cmpccxadd. (build_modrm_byte): Add operations for Vex.VVVV reg on operand 0 while have memory operand. * doc/c-i386.texi: Document .cmpccxadd. * testsuite/gas/i386/i386.exp: Run CMPccXADD tests. * testsuite/gas/i386/cmpccxadd-inval.s: New test. * testsuite/gas/i386/cmpccxadd-inval.l: Ditto. * testsuite/gas/i386/x86-64-cmpccxadd-intel.d: Ditto. * testsuite/gas/i386/x86-64-cmpccxadd.s: Ditto. * testsuite/gas/i386/x86-64-cmpccxadd.d: Ditto. opcodes/ChangeLog: * i386-dis.c (Mdq): New. (X86_64_VEX_0F38E0): Ditto. (X86_64_VEX_0F38E1): Ditto. (X86_64_VEX_0F38E2): Ditto. (X86_64_VEX_0F38E3): Ditto. (X86_64_VEX_0F38E4): Ditto. (X86_64_VEX_0F38E5): Ditto. (X86_64_VEX_0F38E6): Ditto. (X86_64_VEX_0F38E7): Ditto. (X86_64_VEX_0F38E8): Ditto. (X86_64_VEX_0F38E9): Ditto. (X86_64_VEX_0F38EA): Ditto. (X86_64_VEX_0F38EB): Ditto. (X86_64_VEX_0F38EC): Ditto. (X86_64_VEX_0F38ED): Ditto. (X86_64_VEX_0F38EE): Ditto. (X86_64_VEX_0F38EF): Ditto. (x86_64_table): Add X86_64_VEX_0F38E0, X86_64_VEX_0F38E1, X86_64_VEX_0F38E2, X86_64_VEX_0F38E3, X86_64_VEX_0F38E4, X86_64_VEX_0F38E5, X86_64_VEX_0F38E6, X86_64_VEX_0F38E7, X86_64_VEX_0F38E8, X86_64_VEX_0F38E9, X86_64_VEX_0F38EA, X86_64_VEX_0F38EB, X86_64_VEX_0F38EC, X86_64_VEX_0F38ED, X86_64_VEX_0F38EE, X86_64_VEX_0F38EF. * i386-gen.c (cpu_flag_init): Add CPU_CMPCCXADD_FLAGS and CPU_ANY_CMPCCXADD_FLAGS. (cpu_flags): Add CpuCMPCCXADD. * i386-init.h: Regenerated. * i386-opc.h (CpuCMPCCXADD): New. (i386_cpu_flags): Add cpucmpccxadd. Comment unused for it is actually 0. * i386-opc.tbl: Add Intel CMPccXADD instructions. * i386-tbl.h: Regenerated.
* Support Intel AVX-VNNI-INT8Cui,Lili2022-11-027-0/+542
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ * NEWS: Support Intel AVX-VNNI-INT8. * config/tc-i386.c: Add avx_vnni_int8. * doc/c-i386.texi: Document avx_vnni_int8. * testsuite/gas/i386/avx-vnni-int8-intel.d: New file. * testsuite/gas/i386/avx-vnni-int8.d: Likewise. * testsuite/gas/i386/avx-vnni-int8.s: Likewise. * testsuite/gas/i386/x86-64-avx-vnni-int8-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-vnni-int8.d: Likewise. * testsuite/gas/i386/x86-64-avx-vnni-int8.s: Likewise. * testsuite/gas/i386/i386.exp: Run AVX VNNI INT8 tests. opcodes/ * i386-dis.c: (PREFIX_VEX_0F3850) New. (PREFIX_VEX_0F3851): Likewise. (VEX_W_0F3850_P_0): Likewise. (VEX_W_0F3850_P_1): Likewise. (VEX_W_0F3850_P_2): Likewise. (VEX_W_0F3850_P_3): Likewise. (VEX_W_0F3851_P_0): Likewise. (VEX_W_0F3851_P_1): Likewise. (VEX_W_0F3851_P_2): Likewise. (VEX_W_0F3851_P_3): Likewise. (VEX_W_0F3850): Delete. (VEX_W_0F3851): Likewise. (prefix_table): Add PREFIX_VEX_0F3850 and PREFIX_VEX_0F3851. (vex_table): Add PREFIX_VEX_0F3850 and PREFIX_VEX_0F3851, delete VEX_W_0F3850 and VEX_W_0F3851. (vex_w_table): Add VEX_W_0F3850_P_0, VEX_W_0F3850_P_1, VEX_W_0F3850_P_2 VEX_W_0F3850_P_3, VEX_W_0F3851_P_0, VEX_W_0F3851_P_1, VEX_W_0F3851_P_2 and VEX_W_0F3851_P_3, delete VEX_W_0F3850 and VEX_W_0F3851. * i386-gen.c: (cpu_flag_init): Add CPU_AVX_VNNI_INT8_FLAGS and CPU_ANY_AVX_VNNI_INT8_FLAGS. (cpu_flags): Add CpuAVX_VNNI_INT8. * i386-opc.h (CpuAVX_VNNI_INT8): New. * i386-opc.tbl: Add Intel AVX_VNNI_INT8 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
* Support Intel AVX-IFMAHongyu Wang2022-11-0212-12/+245
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | x86: Support Intel AVX-IFMA Intel AVX IFMA instructions are marked with CpuVEX_PREFIX, which is cleared by default. Without {vex} pseudo prefix, Intel IFMA instructions are encoded with EVEX prefix. {vex} pseudo prefix will turn on VEX encoding for Intel IFMA instructions. gas/ * NEWS: Support Intel AVX-IFMA. * config/tc-i386.c (cpu_arch): Add avx_ifma. * doc/c-i386.texi: Document .avx_ifma. * testsuite/gas/i386/avx-ifma.d: New file. * testsuite/gas/i386/avx-ifma-intel.d: Likewise. * testsuite/gas/i386/avx-ifma.s: Likewise. * testsuite/gas/i386/x86-64-avx-ifma.d: Likewise. * testsuite/gas/i386/x86-64-avx-ifma-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-ifma.s: Likewise. * testsuite/gas/i386/i386.exp: Run AVX IFMA tests. opcodes/ * i386-dis.c (PREFIX_VEX_0F38B4): New. (PREFIX_VEX_0F38B5): Likewise. (VEX_W_0F38B4_P_2): Likewise. (VEX_W_0F38B5_P_2): Likewise. (prefix_table): Add PREFIX_VEX_0F38B4 and PREFIX_VEX_0F38B5. (vex_table): Add VEX_W_0F38B4_P_2 and VEX_W_0F38B5_P_2. * i386-dis-evex.h: Fold AVX512IFMA entries to AVX-IFMA. * i386-gen.c (cpu_flag_init): Clear the CpuAVX_IFMA bit in CPU_UNKNOWN_FLAGS. Add CPU_AVX_IFMA_FLGAS and CPU_ANY_AVX_IFMA_FLAGS. Add CpuAVX_IFMA to CPU_AVX2_FLAGS. (cpu_flags): Add CpuAVX_IFMA. * i386-opc.h (CpuAVX_IFMA): New. (i386_cpu_flags): Add cpuavx_ifma. * i386-opc.tbl: Add Intel AVX IFMA instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
* opcodes/arm: use '@' consistently for the comment characterAndrew Burgess2022-11-01121-2291/+2291
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Looking at the ARM disassembler output, every comment seems to start with a ';' character, so I assumed this was the correct character to start an assembler comment. I then spotted a couple of places where there was no ';', but instead, just a '@' character. I thought that this was a case of a missing ';', and proposed a patch to add the missing ';' characters. Turns out I was wrong, '@' is actually the ARM assembler comment character, while ';' is the statement separator. Thus this: nop ;@ comment is two statements, the first is the 'nop' instruction, while the second contains no instructions, just the '@ comment' comment text. This: nop @ comment is a single 'nop' instruction followed by a comment. And finally, this: nop ; comment is two statements, the first contains the 'nop' instruction, while the second contains the instruction 'comment', which obviously isn't actually an instruction at all. Why this matters is that, in the next commit, I would like to add libopcodes syntax styling support for ARM. The question then is how should the disassembler style the three cases above? As '@' is the actual comment start character then clearly the '@' and anything after it can be styled as a comment. But what about ';' in the second example? Style as text? Style as a comment? And the third example is even harder, what about the 'comment' text? Style as an instruction mnemonic? Style as text? Style as a comment? I think the only sensible answer is to move the disassembler to use '@' consistently as its comment character, and remove all the uses of ';'. Then, in the next commit, it's obvious what to do. There's obviously a *lot* of tests that get updated by this commit, the only actual code changes are in opcodes/arm-dis.c.
* x86: Silence GCC 12 warning on tc-i386.cH.J. Lu2022-10-311-4/+4
| | | | | | | | | | | | Silence GCC 12 warning on tc-i386.c: gas/config/tc-i386.c: In function ‘md_assemble’: gas/config/tc-i386.c:5039:16: error: too many arguments for format [-Werror=format-extra-args] 5039 | as_warn (_("only support RIP-relative address"), i.tm.name); * config/tc-i386.c (md_assemble): Print mnemonic in RIP-relative warning. * estsuite/gas/i386/x86-64-prefetchi-warn.l: Updated.
* Support Intel PREFETCHICui, Lili2022-10-3110-0/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ChangeLog: * NEWS: Add support for Intel PREFETCHI instruction. * config/tc-i386.c (load_insn_p): Use prefetch* to fold all prefetches. (md_assemble): Add warning for illegal input of PREFETCHI. * doc/c-i386.texi: Document .prefetchi. * testsuite/gas/i386/i386.exp: Run PREFETCHI tests. * testsuite/gas/i386/x86-64-lfence-load.d: Add PREFETCHI. * testsuite/gas/i386/x86-64-lfence-load.s: Likewise. * testsuite/gas/i386/x86-64-prefetch.d: New test. * testsuite/gas/i386/x86-64-prefetchi-intel.d: Likewise. * testsuite/gas/i386/x86-64-prefetchi-inval-register.d: Likewise.. * testsuite/gas/i386/x86-64-prefetchi-inval-register.s: Likewise. * testsuite/gas/i386/x86-64-prefetchi-warn.l: Likewise. * testsuite/gas/i386/x86-64-prefetchi-warn.s: Likewise. * testsuite/gas/i386/x86-64-prefetchi.d: Likewise. * testsuite/gas/i386/x86-64-prefetchi.s: Likewise. opcodes/ChangeLog: * i386-dis.c (reg_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7 (x86_64_table): Add X86_64_0F18_REG_6_MOD_0 and X86_64_0F18_REG_7_MOD_0. (mod_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7. (prefix_table): Add PREFIX_0F18_REG_6_MOD_0_X86_64 and PREFIX_0F18_REG_7_MOD_0_X86_64. (PREFETCHI_Fixup): New. * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHI_FLAGS. (cpu_flags): Add CpuPREFETCHI. * i386-opc.h (CpuPREFETCHI): New. (i386_cpu_flags): Add cpuprefetchi. * i386-opc.tbl: Add Intel PREFETCHI instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
* RX assembler: switch arguments of thw MVTACGU insn.Yoshinori Sato2022-10-311-4/+4
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* RISC-V: Always generate mapping symbols at the start of the sections.Nelson Chu2022-10-292-28/+0
| | | | | | | | | | | | Before figuring out the suppress rule of mapping symbol with architecture (changed back to $x), always generate them at the start of the sections. gas/ * config/tc-riscv.c (need_arch_map_symbol): Removed. (riscv_mapping_state): Updated. (riscv_check_mapping_symbols): Updated. * testsuite/gas/riscv/mapping-non-arch.d: Removed. * testsuite/gas/riscv/mapping-non-arch.s: Likewise.
* RISC-V: Output mapping symbols with ISA string.Nelson Chu2022-10-2822-291/+273
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RISC-V Psabi pr196, https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/196 bfd/ * elfxx-riscv.c (riscv_release_subset_list): Free arch_str if needed. (riscv_copy_subset_list): Copy arch_str as well. * elfxx-riscv.h (riscv_subset_list_t): Store arch_str for each subset list. gas/ * config/tc-riscv.c (riscv_reset_subsets_list_arch_str): Update the architecture string in the subset_list. (riscv_set_arch): Call riscv_reset_subsets_list_arch_str after parsing new architecture string. (s_riscv_option): Likewise. (need_arch_map_symbol): New boolean, used to indicate if .option directives do affect instructions. (make_mapping_symbol): New boolean parameter reset_seg_arch_str. Need to generate $x+arch for MAP_INSN, and then store it into tc_segment_info_data if reset_seg_arch_str is true. (riscv_mapping_state): Decide if we need to add $x+arch for MAP_INSN. For now, only add $x+arch if the architecture strings in subset list and segment are different. Besides, always add $x+arch at the start of section, and do not add $x+arch for code alignment, since rvc for alignment can be judged from addend of R_RISCV_ALIGN. (riscv_remove_mapping_symbol): If current and previous mapping symbol have same value, then remove the current $x only if the previous is $x+arch; Otherwise, always remove previous. (riscv_add_odd_padding_symbol): Updated. (riscv_check_mapping_symbols): Don't need to add any $x+arch if need_arch_map_symbol is false, so changed them to $x. (riscv_frag_align_code): Updated since riscv_mapping_state is changed. (riscv_init_frag): Likewise. (s_riscv_insn): Likewise. (riscv_elf_final_processing): Call riscv_release_subset_list to release subset_list of riscv_rps_as, rather than only release arch_str in the riscv_write_out_attrs. (riscv_write_out_attrs): No need to call riscv_arch_str, just get arch_str from subset_list of riscv_rps_as. * config/tc-riscv.h (riscv_segment_info_type): Record current $x+arch mapping symbol of each segment. * testsuite/gas/riscv/mapping-0*: Merged and replaced by mapping.s. * testsuite/gas/riscv/mapping.s: New testcase, to test most of the cases in one file. * testsuite/gas/riscv/mapping-symbols.d: Likewise. * testsuite/gas/riscv/mapping-dis.d: Likewise. * testsuite/gas/riscv/mapping-non-arch.s: New testcase for the case that does need any $x+arch. * testsuite/gas/riscv/mapping-non-arch.d: Likewise. * testsuite/gas/riscv/option-arch-01a.d: Updated. opcodes/ * riscv-dis.c (riscv_disassemble_insn): Set riscv_fpr_names back to riscv_fpr_names_abi or riscv_fpr_names_numeric when zfinx is disabled for some specfic code region. (riscv_get_map_state): Recognized mapping symbols $x+arch, and then reset the architecture string once the ISA is different.
* PowerPC: Add support for RFC02658 - MMA+ Outer-Product InstructionsPeter Bergner2022-10-273-0/+80
| | | | | | | | | | | | | | | | | | gas/ * config/tc-ppc.c (md_assemble): Only check for prefix opcodes. * testsuite/gas/ppc/rfc02658.s: New test. * testsuite/gas/ppc/rfc02658.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run it. opcodes/ * ppc-opc.c (XMSK8, P_GERX4_MASK, P_GERX2_MASK, XX3GERX_MASK): New. (powerpc_opcodes): Add dmxvi8gerx4pp, dmxvi8gerx4, dmxvf16gerx2pp, dmxvf16gerx2, dmxvbf16gerx2pp, dmxvf16gerx2np, dmxvbf16gerx2, dmxvi8gerx4spp, dmxvbf16gerx2np, dmxvf16gerx2pn, dmxvbf16gerx2pn, dmxvf16gerx2nn, dmxvbf16gerx2nn, pmdmxvi8gerx4pp, pmdmxvi8gerx4, pmdmxvf16gerx2pp, pmdmxvf16gerx2, pmdmxvbf16gerx2pp, pmdmxvf16gerx2np, pmdmxvbf16gerx2, pmdmxvi8gerx4spp, pmdmxvbf16gerx2np, pmdmxvf16gerx2pn, pmdmxvbf16gerx2pn, pmdmxvf16gerx2nn, pmdmxvbf16gerx2nn.
* PowerPC: Add support for RFC02653 - Dense Math FacilityPeter Bergner2022-10-275-64/+258
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ * config/tc-ppc.c (pre_defined_registers): Add dense math registers. (md_assemble): Check dmr specified in correct operand. * testsuite/gas/ppc/outerprod.s <dmsetaccz, dmxvbf16ger2, dmxvbf16ger2nn, dmxvbf16ger2np, dmxvbf16ger2pn, dmxvbf16ger2pp, dmxvf16ger2, dmxvf16ger2nn, dmxvf16ger2np, dmxvf16ger2pn, dmxvf16ger2pp, dmxvf32ger, dmxvf32gernn, dmxvf32gernp, dmxvf32gerpn, dmxvf32gerpp, dmxvf64ger, dmxvf64gernn, dmxvf64gernp, dmxvf64gerpn, dmxvf64gerpp, dmxvi16ger2, dmxvi16ger2pp, dmxvi16ger2s, dmxvi16ger2spp, dmxvi4ger8, dmxvi4ger8pp, dmxvi8ger4, dmxvi8ger4pp, dmxvi8ger4spp, dmxxmfacc, dmxxmtacc, pmdmxvbf16ger2, pmdmxvbf16ger2nn, pmdmxvbf16ger2np, pmdmxvbf16ger2pn, pmdmxvbf16ger2pp, pmdmxvf16ger2, pmdmxvf16ger2nn, pmdmxvf16ger2np, pmdmxvf16ger2pn, pmdmxvf16ger2pp, pmdmxvf32ger, pmdmxvf32gernn, pmdmxvf32gernp, pmdmxvf32gerpn, pmdmxvf32gerpp, pmdmxvf64ger, pmdmxvf64gernn, pmdmxvf64gernp, pmdmxvf64gerpn, pmdmxvf64gerpp, pmdmxvi16ger2, pmdmxvi16ger2pp, pmdmxvi16ger2s, pmdmxvi16ger2spp, pmdmxvi4ger8, pmdmxvi4ger8pp, pmdmxvi8ger4, pmdmxvi8ger4pp, pmdmxvi8ger4spp>: Add new tests. * testsuite/gas/ppc/outerprod.d: Likewise. * testsuite/gas/ppc/rfc02653.s: New test. * testsuite/gas/ppc/rfc02653.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run it. include/ * opcode/ppc.h (PPC_OPERAND_DMR): Define. Renumber following PPC_OPERAND defines. opcodes/ * ppc-dis.c (print_insn_powerpc): Prepend 'dm' when printing DMR regs. * ppc-opc.c (insert_p2, (extract_p2, (insert_xa5, (extract_xa5, insert_xb5, (extract_xb5): New functions. (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a): Disallow operand overlap only on Power10. (DMR, DMRAB, P1, P2, XA5p, XB5p, XDMR_MASK, XDMRDMR_MASK, XX2ACC_MASK, XX2DMR_MASK, XX3DMR_MASK): New defines. (powerpc_opcodes): Add dmmr, dmsetaccz, dmsetdmrz, dmxor, dmxvbf16ger2, dmxvbf16ger2nn, dmxvbf16ger2np, dmxvbf16ger2pn, dmxvbf16ger2pp, dmxvf16ger2, dmxvf16ger2nn, dmxvf16ger2np, dmxvf16ger2pn, dmxvf16ger2pp, dmxvf32ger, dmxvf32gernn, dmxvf32gernp, dmxvf32gerpn, dmxvf32gerpp, dmxvf64ger, dmxvf64gernn, dmxvf64gernp, dmxvf64gerpn, dmxvf64gerpp, dmxvi16ger2, dmxvi16ger2pp, dmxvi16ger2s, dmxvi16ger2spp, dmxvi4ger8, dmxvi4ger8pp, dmxvi8ger4, dmxvi8ger4pp, dmxvi8ger4spp, dmxxextfdmr256, dmxxextfdmr512, dmxxinstdmr256, dmxxinstdmr512, dmxxmfacc, dmxxmtacc, pmdmxvbf16ger2, pmdmxvbf16ger2nn, pmdmxvbf16ger2np, pmdmxvbf16ger2pn, pmdmxvbf16ger2pp, pmdmxvf16ger2, pmdmxvf16ger2nn, pmdmxvf16ger2np, pmdmxvf16ger2pn, pmdmxvf16ger2pp, pmdmxvf32ger, pmdmxvf32gernn, pmdmxvf32gernp, pmdmxvf32gerpn, pmdmxvf32gerpp, pmdmxvf64ger, pmdmxvf64gernn, pmdmxvf64gernp, pmdmxvf64gerpn, pmdmxvf64gerpp, pmdmxvi16ger2, pmdmxvi16ger2pp, pmdmxvi16ger2s, pmdmxvi16ger2spp, pmdmxvi4ger8, pmdmxvi4ger8pp, pmdmxvi8ger4, pmdmxvi8ger4pp, pmdmxvi8ger4spp.
* re: Support Intel AMX-FP16Alan Modra2022-10-272-0/+2
| | | | | | | | | Fix these fails due to the target padding out sections with nops. x86_64-w64-mingw32 +FAIL: x86_64 AMX-FP16 insns x86_64-w64-mingw32 +FAIL: x86_64 AMX-FP16 insns (Intel disassembly) * testsuite/gas/i386/x86-64-amx-fp16-intel.d: Accept trailing nops. * testsuite/gas/i386/x86-64-amx-fp16.d: Likewise.
* x86: consolidate VPCLMUL testsJan Beulich2022-10-2415-268/+156
| | | | | | | | | | There's little point in having Intel syntax disassembler tests when the purpose of a test is assembler functionality: Drop all *avx512*_vpclmulqdq-wig1-intel. For *avx512*_vpclmulqdq-wig1 share source with *avx512*_vpclmulqdq. Finally put in place similar tests for -mvexwig=1.
* x86: consolidate VAES testsJan Beulich2022-10-2415-352/+211
| | | | | | | | | | | | There's little point in having Intel syntax disassembler tests when the purpose of a test is assembler functionality: Drop all *avx512*_vaes-wig1-intel. For *avx512*_vaes-wig1 share source with *avx512*_vaes. This in particular makes sure that the 32-bit VL test actually tests any EVEX encodings in the first place. Finally put in place similar tests for -mvexwig=1.
* x86: emit {evex} prefix when disassembling ambiguous AVX512VL insnsJan Beulich2022-10-2431-361/+361
| | | | | | | | When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
* Support Intel AMX-FP16Cui,Lili2022-10-216-0/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ * NEWS: Add support for Intel AMX-FP16 instruction. * config/tc-i386.c: Add amx_fp16. * doc/c-i386.texi: Document .amx_fp16. * testsuite/gas/i386/i386.exp: Add AMX-FP16 tests. * testsuite/gas/i386/x86-64-amx-fp16-intel.d: New test. * testsuite/gas/i386/x86-64-amx-fp16.d: Likewise. * testsuite/gas/i386/x86-64-amx-fp16.s: Likewise. * testsuite/gas/i386/x86-64-amx-fp16-bad.d: Likewise. * testsuite/gas/i386/x86-64-amx-fp16-bad.s: Likewise. opcodes/ * i386-dis.c (MOD_VEX_0F385C_X86_64_P_3_W_0): New. (VEX_LEN_0F385C_X86_64_P_3_W_0_M_0): Likewise. (VEX_W_0F385C_X86_64_P_3): Likewise. (prefix_table): Add VEX_W_0F385C_X86_64_P_3. (vex_len_table): Add VEX_LEN_0F385C_X86_64_P_3_W_0_M_0. (vex_w_table): Add VEX_W_0F385C_X86_64_P_3. (mod_table): Add MOD_VEX_0F385C_X86_64_P_3_W_0. * i386-gen.c (cpu_flag_init): Add AMX-FP16_FLAGS. (CPU_ANY_AMX_TILE_FLAGS): Add CpuAMX_FP16. (cpu_flags): Add CpuAMX-FP16. * i386-opc.h (enum): Add CpuAMX-FP16. (i386_cpu_flags): Add cpuamx_fp16. * i386-opc.tbl: Add Intel AMX-FP16 instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
* x86: Check VEX/EVEX encoding before checking vector operandsH.J. Lu2022-10-204-0/+4
| | | | | | | | | | | | | | | | | | | | | | Since commit 837e225ba1992f9745e5bbbd5e8443243a7f475f Author: Jan Beulich <jbeulich@suse.com> Date: Thu Oct 20 10:01:12 2022 +0200 x86: re-work AVX-VNNI support moved AVX-VNNI after AVX512-VNNI, vector Disp8 is applied even when VEX encoding is selected. Check VEX/EVEX encoding before checking vector operands to avoid vector Disp8 with VEX encoding. PR gas/29708 * config/tc-i386.c (match_template): Check VEX/EVEX encoding before checking vector operands. * testsuite/gas/i386/avx-vnni.d: Updated. * testsuite/gas/i386/x86-64-avx-vnni.d: Likewise. * testsuite/gas/i386/avx-vnni.s: Add a Disp32 test. * testsuite/gas/i386/x86-64-avx-vnni.s: Likewise.
* x86: re-work AVX-VNNI supportJan Beulich2022-10-206-6/+36
| | | | | | | | By putting the templates after their AVX512 counterparts, the AVX512 flavors will be picked by default. That way the need to always use {vex} ceases to exist once respective CPU features (AVX512-VNNI or AVX512VL as a whole) have been disabled. This way the need for the PseudoVexPrefix attribute also disappears.
* aarch64-pe support for LD, GAS and BFDJedidiah Thompson2022-10-193-0/+31
| | | | | | | | Allows aarch64-pe to be targeted natively, not having to use objcopy to convert it from ELF to PE. Based on initial work by Jedidiah Thompson Co-authored-by: Jedidiah Thompson <wej22007@outlook.com> Co-authored-by: Zac Walker <zac.walker@linaro.org>
* Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp}CaiJingtao2022-10-175-205/+566
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Omitting predicate size specifier in vector form of {sq, uq, }{decp, incp} is deprecated and will be prohibited in a future release of the aarch64, see https://developer.arm.com/documentation/ddi0602/2021-09/SVE-Instructions/DECP--vector---Decrement-vector-by-count-of-true-predicate-elements-. This allows explicit size specifier, e.g. `decp z0.h, p0.h`, for predicate operand of these SVE instructions. The existing behaviour of not requiring the specifier is preserved. And the disasembly is with the specifier with this patch. The GAS tests passed under our local tests. opcodes/ * aarch64-asm.c: Modify `sve_size_hsd` encoding. * aarch64-tbl.h (aarch64_opcode_table): Add QUALS's type OP_SVE_Vv_HSD for decp, incp, sqdecp, sqincp, uqdecp and uqincp. gas/ * testsuite/gas/aarch64/sve-movprfx_23.s: Update movprfx_23 testcase's test_sametwo macro, where take the predicate size specifier. * testsuite/gas/aarch64/sve-movprfx_23.d: Update movprfx_23 testcase's expected disassembly. * testsuite/gas/aarch64/sve-movprfx_23.l: Update movprfx_23 testcase's expected assembler messages. * testsuite/gas/aarch64/sve.s: Add sve testcase's instructions for decp, incp, sqdecp, sqincp, uqdecp and uqincp, which take the predicate size specifier. * testsuite/gas/aarch64/sve.d: Update sve testcase's expected disassembly. Signed-off-by: CaiJingtao <caijingtao@huawei.com>
* PowerPC se_rfmci and VLE, SPE2 and LSP insns with -manyAlan Modra2022-10-164-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | I noticed recently that se_rfmci, a VLE mode instruction, was being accepted by non-VLE cpus, and also that se_rfmci by itself in a section did not cause SHF_PPC_VLE to be set. ie. both testcases added by this patch fail without the changes to tc-ppc.c here. Also, VLE, SPE2 and LSP insns were not accepted by the assembler with -many nor were SPE2 and LSP being disassembled with -Many. gas/ * config/tc-ppc.c (ppc_setup_opcodes): Wrap long lines. Add vle_opcodes when PPC_OPCODE_VLE or PPC_OPCODE_ANY. Simplify disassembler index segment checks. Add LSP and SPE2 opcodes when PPC_OPCODE_ANY too. (md_assemble): Correct logic adding PPC_APUINFO_VLE and SHF_PPC_VLE. * testsuite/gas/ppc/se_rfmci.s * testsuite/gas/ppc/se_rfmci.d, * testsuite/gas/ppc/se_rfmci_bad.d: New tests. * testsuite/gas/ppc/ppc.exp: Run them. opcodes/ * ppc-dis.c (print_insn_powerpc): Disassemble SPE2 and LSP insn when -Many. * ppc-opc.c (vle_opcodes <se_rfmci>): Comment.
* PowerPC SPE disassembly and testsAlan Modra2022-10-144-14/+11
| | | | | | | | | | | | | | | | | | | | | Where sub and subf forms of an instruction exist we generally disassemble to the extended insn sub form rather than the underlying machine subf instruction. Do so for SPE evsubw and evsubiw too. spe_ambiguous.d always was a bit too optimistic. There is no sensible way to disassemble identical bytes back to different and original source. Instead change the test to check -Mraw results. gas/ * testsuite/gas/ppc/ppc.exp: Run spe_ambiguous test. * testsuite/gas/ppc/spe.d: Expect evsubw and evsubiw rather than evsubfw and evsubifw. * testsuite/gas/ppc/spe_ambiguous.s: Test evnor form equivalent to evnot. * testsuite/gas/ppc/spe_ambiguous.d: Test Mraw. opcodes/ * ppc-opc.c (powerpc_opcodes): Move evsubw before evsubfw and evsubiw before evsubifw and mark EXT.
* e200 LSP supportAlan Modra2022-10-143-7/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It has bothered me for a long time that we have disabled LSP (and SPE) tests. Also the LSP test comment indicating there is something wrong with get_powerpc_dialect. I don't think there is. Decoding of a VLE instruction depends on whether the processor is in VLE mode (some processors support both VLE and standard PPC) which we flag per section with SHF_PPC_VLE for decoding when disassembling. Background: Some versions of powerpc e200 have "Lightweight Signal Processing" support, examples being e200z215 and e200z425. As far as I can tell, LSP and SPE are mutually exclusive. This seems to be borne out by insn encoding, for example LSP "zvaddih" and SPE "evaddw" have the same encoding. So none of the processor descriptions in ppc_opts ought to have both PPC_OPCODE_LSP and PPC_OPCODE_SPE/2, if we want disassembly to work. I also could not find anything to suggest that the LSP insns are enabled only in VLE mode, which means the LSP insns should not be in vle_opcodes. Fix all this by moving the LSP insns to their own table, and add a new e200z2 cpu entry with LSP support, removing LSP from -me200z4 and from -mvle. (Yes, I know, as I said above some of the e200z4 processors have LSP. Others have SPE. It's hard to choose good options. Think of z2 as meaning earlier, z4 as later.) Also add -mlsp to allow adding the LSP insn set. include/ * opcode/ppc.h (lsp_opcodes, lsp_num_opcodes): Declare. (LSP_OP_TO_SEG): Define. binutils/ * doc/binutils.texi: Update ppc docs. gas/ * config/tc-ppc.c (ppc_setup_opcodes): Add lsp opcodes to ppc_hash. * doc/c-ppc.texi: Document e200 and lsp. * testsuite/gas/ppc/lsp-checks.d: Assemble with -me200z2. * testsuite/gas/ppc/lsp.d: Likewise, disassembly too. * testsuite/gas/ppc/ppc.exp: Don't xfail lsp test. opcodes/ * ppc-dis.c (ppc_opts): Add e200z2 and lsp. Don't set PPC_OPCODE_LSP for e200z4 or vle. (ppc_parse_cpu): Mutually exclude LSP and SPE. (LSP_OPCD_SEGS): Define. (lsp_opcd_indices): New array. (disassemble_init_powerpc): Init lsp_opcd_indices. (lookup_lsp): New function. (print_insn_powerpc): Call it. * ppc-opc.c: Include libiberty.h for ARRAY_SIZE and use throughout. (vle_opcodes): Move LSP opcodes to.. (lsp_opcodes): ..here, and sort. (lsp_num_opcodes): New.
* RISC-V: Imply 'Zicsr' from privileged extensions with CSRsTsukasa OI2022-10-141-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | 'H', 'Smstateen', 'Sscofpmf' and 'Sstc' are four privileged extensions with their CSR definitions and 'Smepmp' is a privileged extension with additional CSR bits. Volume II: Privileged Architecture of the RISC-V ISA Manual states that the privileged architecture requires the 'Zicsr' extension. However, current GNU Binutils has no direct way whether the program has dependency to the privileged architecture itself. As a workaround, we should add implications from privileged extensions that either add new CSRs, extend existing CSRs or depends on using CSRs. This commit adds such implications for existing privileged extensions that satisfy this condition. gas/ChangeLog: * testsuite/gas/riscv/march-imply-h.d: New test, at least for 'H'. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Add 'Zicsr' implicications for privileged extensions 'H', 'Smstateen', 'Sscofpmf', 'Sstc' and 'Smepmp'.
* RISC-V: Test DWARF register number for "fp"Tsukasa OI2022-10-142-0/+4
| | | | | | | | | This commit adds "fp" (x8 or s0) to dw-regnums.{s,d}. gas/ChangeLog: * testsuite/gas/riscv/dw-regnums.s: Add "fp". * testsuite/gas/riscv/dw-regnums.d: Likewise.
* x86/gas: support quoted address scale factor in AT&T syntaxJan Beulich2022-10-053-0/+16
| | | | | | | | | | An earlier attempt (e68c3d59acd0 ["x86: better respect quotes in parse_operands()"]) needed undoing (cc0f96357e0b ["x86: permit parenthesized expressions again as addressing scale factor"]) as far its effect here went. As indicated back then, the issue is the backwards scanning of the operand string to find the matching opening parenthesis. Switch to forward scanning, finding the last outermost unquoted opening parenthesis (which is the one matching the trailing closing one).
* Arm64: support CLEARBHB aliasJan Beulich2022-10-052-1/+3
| | | | | While the Arm v8 ARM (rev I-a) still doesn't mention this alias, it is (typically via a macro) already in use in kernels and alike.
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