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* RISC-V: PR27764, Add tests for A extensionChristoph Muellner2021-05-034-0/+550
* x86: allow @secrel32 also in data definitionsJan Beulich2021-05-032-6/+12
* x86: use UNIX EOL in secrel testcaseJan Beulich2021-05-032-125/+125
* testsuite: Don't start directives in first columnAlan Modra2021-05-032-14/+14
* x86-64: adjust recently added testsJan Beulich2021-04-295-15/+18
* x86: relax when/how @size can be usedJan Beulich2021-04-294-0/+77
* x86: allow @size to also (sensibly) apply to sectionsJan Beulich2021-04-293-6/+23
* x86: honor signedness of PC-relative relocationsJan Beulich2021-04-289-0/+146
* x86: optimize LEAJan Beulich2021-04-2611-7/+415
* x86-64: have value properly checked when resolving fixupJan Beulich2021-04-263-0/+45
* Fix type of .persistent.bss sectionEric Botcazou2021-04-233-2/+11
* Adjust readelf's output so that section symbols without a name as shown with ...Nick Clifton2021-04-2133-133/+133
* Fix an assembler testuite failure when checking a toolchain configured with -...Nick Clifton2021-04-191-0/+2
* aarch64: New instructions for maintenance of GPT entries cached in a TLBPrzemyslaw Wirkus2021-04-192-0/+10
* aarch64: Add new data cache maintenance operationsPrzemyslaw Wirkus2021-04-192-0/+6
* aarch64: Define RME system registersPrzemyslaw Wirkus2021-04-165-0/+33
* RISC-V: PR27436, make operand C> work the same as >.Nelson Chu2021-04-166-0/+103
* RISC-V: compress "addi d,CV,z" to "c.mv d,CV"Lifang Xia2021-04-162-9/+9
* m68hc11 gas testsuite wartAlan Modra2021-04-131-13/+9
* Power10 bignum operandsAlan Modra2021-04-122-0/+29
* RISC-V: Support to parse the multi-letter prefix in the architecture string.Nelson Chu2021-04-1222-23/+31
* AArch64: Fix Diagnostic messaging for LD/ST Exclusive.Tejas Belagod2021-04-092-6/+7
* PowerPC disassembly of pcrel referencesAlan Modra2021-04-093-51/+51
* PR27676, PowerPC missing extended dcbt, dcbtst mnemonicsAlan Modra2021-04-085-4/+155
* Fix pr27217 testcase failureAlan Modra2021-04-071-3/+3
* Fix a problem assembling AArch64 sources when a relocation is generated again...Nick Clifton2021-04-062-0/+31
* x86: VPSADBW's source operands are also commutativeJan Beulich2021-03-293-2/+4
* x86-64: don't accept supposedly disabled MOVQ formsJan Beulich2021-03-263-0/+25
* [NIOS2] Fix disassembly of br.n instruction.Hafiz Abid Qadeer2021-03-252-0/+14
* x86: flag bad S/G insn operand combinationsJan Beulich2021-03-2511-176/+73
* x86: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clearJan Beulich2021-03-252-1/+5
* x86: fix AMD Zen3 insnsJan Beulich2021-03-256-23/+77
* x86-64: limit breakage from gcc movdir64b et al workaroundJan Beulich2021-03-2514-33/+149
* PR27647 PowerPC extended conditional branch mnemonicsAlan Modra2021-03-252-8/+8
* x86: unbreak certain MPX insn operand formsJan Beulich2021-03-232-18/+28
* RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructionsKuan-Lin Chen2021-03-164-0/+148
* aarch64: Add few missing system registersPrzemyslaw Wirkus2021-03-125-0/+51
* x86/Intel: correct AVX512 S/G disassemblyJan Beulich2021-03-106-930/+930
* x86: correct decoding of nop/reserved space (0f18 ... 0x1f)Jan Beulich2021-03-107-16/+2363
* x86-64: make SYSEXIT handling similar to SYSRET'sJan Beulich2021-03-0911-7/+21
* Correct an error message in the ARM assembler.Nick Clifton2021-02-263-0/+22
* RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu2021-02-192-19/+31
* h8300 complains about new section defined without attributesAlan Modra2021-02-171-0/+1
* gas: Allow SHF_GNU_RETAIN on all sectionsH.J. Lu2021-02-165-0/+43
* x86: CVTPI2PD has special behaviorJan Beulich2021-02-1614-93/+147
* x86: honor template rather than actual operands when updating i.xstateJan Beulich2021-02-163-3/+3
* x86: record register use for SIMD insns without respective explicit operandsJan Beulich2021-02-167-0/+36
* x86: make common property tests commonJan Beulich2021-02-1610-108/+10
* x86: make 16-bit ENQCMD test actually test ENQCMDJan Beulich2021-02-162-12/+17
* IBM Z: Implement instruction set extensionsAndreas Krebbel2021-02-153-0/+56
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