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* Update year range in copyright notice of binutils filesAlan Modra2020-01-01190-190/+190
* x86: adjust ignored prefix warning for branchesJan Beulich2019-12-273-8/+12
* x86-64: correct / adjust prefix emissionJan Beulich2019-12-278-51/+45
* x86-64: fix Intel64 handling of branch with data16 prefixJan Beulich2019-12-274-19/+19
* x86: consolidate Disp<NN> handling a littleJan Beulich2019-12-271-0/+1
* i386: Also check R12-R15 registers when optimizing testq to testbH.J. Lu2019-12-123-0/+12
* i386: Add tests for -malign-branch-boundary and -malign-branchH.J. Lu2019-12-1254-0/+2562
* [gas][arm] Add -mwarn-restrict-itAndre Vieira2019-12-118-8/+8
* x86: further refine SSE check (SSE4a, SHA, GFNI)Jan Beulich2019-12-115-25/+75
* [gas][arm] Set context table for '.arch_extension'Andre Vieira2019-12-102-0/+13
* x86/Intel: support "mmword ptr"Jan Beulich2019-12-095-3/+8
* x86/Intel: fix "near ptr" / "far ptr" handlingJan Beulich2019-12-092-0/+10
* aarch64*-*-*ilp32 gas testsAlan Modra2019-12-0813-36/+34
* [gas] Implement .cfi_negate_ra_state directiveKyrylo Tkachov2019-12-062-0/+46
* Arm64: correct "sha3" arch-extension directive handlingJan Beulich2019-12-055-42/+35
* x86-64: accept 64-bit LFS/LGS/LSS forms with suffix or operand size specifierJan Beulich2019-12-047-8/+67
* x86-64/Intel: fix CALL/JMP with dword operandJan Beulich2019-12-042-4/+20
* x86/Intel: extend MOVDIRI testingJan Beulich2019-12-046-0/+12
* x86: make sure all PUSH/POP honor DefaultSizeJan Beulich2019-12-042-0/+16
* x86: drop some stray/bogus DefaultSizeJan Beulich2019-12-042-8/+84
* gas/riscv: Produce version 3 DWARF CIE by defaultAndrew Burgess2019-11-282-0/+17
* gas: Check for overflow on return column in version 1 CIE DWARFAndrew Burgess2019-11-283-0/+23
* binutils/gas/riscv: Add DWARF register numbers for CSRsAndrew Burgess2019-11-282-0/+520
* Fix "psb CSYNC" and "bti C".Andrew Pinski2019-11-255-0/+12
* Arm: Change CRC from fpu feature to archititectural extensionMihail Ionescu2019-11-222-0/+33
* PR24944, gas doesn't read enough digits when parsing a floating point numberAlan Modra2019-11-202-3/+10
* gas: Add --gdwarf-cie-version command line flagAndrew Burgess2019-11-187-0/+71
* x86/Intel: correct CMPSD test cases' regexp closing paren placementJan Beulich2019-11-142-39/+39
* x86/Intel: extend MOVSD/CMPSD testsuite coverageJan Beulich2019-11-149-0/+374
* RISC-V: Support the INSN_CLASS.*F.* classes for .insn directive.Jim Wilson2019-11-121-1/+1
* [gas][arm] Enable VLDM, VSTM, VPUSH, VPOP for MVEMihail Ionescu2019-11-122-0/+51
* [binutils][arm] Update the decoding of MVE VMOV, VMVNMihail Ionescu2019-11-122-0/+88
* [gas][arm] Make .fpu reset the FPU/Coprocessor feature bitsMihail Ionescu2019-11-123-0/+23
* x86: eliminate ImmExt abuseJan Beulich2019-11-1210-304/+325
* Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same registerJan Beulich2019-11-112-0/+4
* i386: Only check suffix in instruction mnemonicH.J. Lu2019-11-084-2/+27
* [gas][aarch64] Add the v8.6 Data Gathering Hint mnemonic [10/X]Matthew Malcomson2019-11-072-0/+15
* [Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]Matthew Malcomson2019-11-073-1/+69
* [binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson2019-11-078-0/+304
* [Patch][binutils][aarch64] .bfloat16 directive for AArch64 [7/10]Matthew Malcomson2019-11-073-0/+41
* [Patch][binutils][arm] .bfloat16 directive for Arm [6/X]Matthew Malcomson2019-11-073-0/+41
* [binutils][arm] BFloat16 enablement [4/X]Matthew Malcomson2019-11-0715-0/+544
* [binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson2019-11-077-0/+350
* x86: support further AMD Zen2 instructionsJan Beulich2019-11-077-54/+22
* x86: adjust register names printed for MONITOR/MWAITJan Beulich2019-11-0711-201/+61
* i386; Add .code16gcc fldenv testsH.J. Lu2019-10-312-2/+15
* Add support for context sensitive '.arch_extension' to the ARM assembler.Mihail Ionescu2019-10-314-0/+25
* Modify the ARNM assembler to accept the omission of the immediate argument fo...Delia Burduv2019-10-304-29/+45
* x86: add tests to cover defaulting of operand sizes for ambiguous insnsJan Beulich2019-10-307-0/+385
* Fix the disassembly of the LDS and STS instructions of the AVR architecture.Nick Clifton2019-10-092-0/+13
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