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* gas: re-work line number tracking for macros and their expansionsJan Beulich2022-12-1357-2537/+9605
* Arm: avoid unhelpful uses of .macro in testsuiteJan Beulich2022-12-13141-2306/+2237
* x86: further re-work insn/suffix recognition to also cover MOVSXJan Beulich2022-12-128-11/+184
* x86-64: allow HLE store of accumulator to absolute 32-bit addressJan Beulich2022-12-123-0/+24
* ix86: don't recognize/derive Q suffix in the common caseJan Beulich2022-12-1212-26/+59
* x86: re-work insn/suffix recognitionJan Beulich2022-12-125-4/+26
* x86: revert disassembler parts of "x86: Allow 16-bit register source for LAR ...Jan Beulich2022-12-126-52/+52
* PowerPC: Add support for RFC02655 - Saturating Subtract InstructionPeter Bergner2022-12-075-0/+52
* PowerPC: Add support for RFC02656 - Enhanced Load Store with Length InstructionsPeter Bergner2022-12-073-0/+30
* gas: add Dwarf line number test for .macro expansionsJan Beulich2022-12-053-0/+56
* opcodes/mips: use .word/.short for undefined instructionsAndrew Burgess2022-12-0513-514/+514
* x86: Allow 16-bit register source for LAR and LSLH.J. Lu2022-12-0310-8/+170
* x86: extend FPU test coverage for AT&T / Intel mnemonic differencesJan Beulich2022-11-305-0/+44
* RISC-V: Better support for long instructions (tests)Tsukasa OI2022-11-284-1/+48
* riscv: Add AIA extension support (Smaia, Ssaia)Christoph Müllner2022-11-2511-0/+860
* x86: widen applicability and use of CheckRegSizeJan Beulich2022-11-242-0/+60
* x86: correct handling of LAR and LSLJan Beulich2022-11-245-19/+63
* gas: Add --gcodeview optionMark Harmstone2022-11-234-0/+342
* Fix ARM and AArch64 assembler tests to work in a multi-arch environment.Nick Clifton2022-11-214-4/+4
* RISC-V: Add 'Ssstateen' extension and its CSRsTsukasa OI2022-11-198-97/+154
* RISC-V: Add T-Head Int vendor extensionChristoph Müllner2022-11-172-0/+14
* RISC-V: Add T-Head Fmv vendor extensionChristoph Müllner2022-11-172-0/+14
* gas: testsuite: add new tests for SFrame unwind infoIndu Bhagat2022-11-1529-0/+533
* Re: [gas] arm: Add support for new unwinder directive ".pacspval".Alan Modra2022-11-161-4/+5
* Add AMD znver4 processor supportTejas Joshi2022-11-159-0/+127
* aarch64, testsuite: Fixed recently added cssc.dAndre Vieira2022-11-151-7/+0
* aarch64: Add support for Common Short Sequence Compression extensionAndre Vieira2022-11-142-0/+334
* [gas] arm: Add support for new unwinder directive ".pacspval".Srinath Parvathaneni2022-11-142-0/+53
* arm: Add support for Cortex-X1C CPU.Srinath Parvathaneni2022-11-141-0/+6
* PowerPC64 paddi -MrawAlan Modra2022-11-122-0/+3
* i386: Check invalid (%dx) usageH.J. Lu2022-11-104-0/+28
* x86/Intel: don't accept malformed EXTRQ / INSERTQJan Beulich2022-11-093-15/+15
* RISC-V: xtheadfmemidx: Use fp register in mnemonicsChristoph Müllner2022-11-094-48/+50
* Support Intel RAO-INTKong Lingling2022-11-087-0/+110
* RISC-V: Remove RV32EF conflictTsukasa OI2022-11-072-5/+0
* x86: adjust recently introduced testcasesJan Beulich2022-11-048-0/+8
* Support Intel AVX-NE-CONVERTkonglin12022-11-047-0/+1018
* RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment.Nelson Chu2022-11-023-9/+31
* Support Intel MSRLISTHu, Lin12022-11-026-0/+42
* Support Intel WRMSRNSHu, Lin12022-11-026-0/+39
* Support Intel CMPccXADDHaochen Jiang2022-11-026-0/+812
* Support Intel AVX-VNNI-INT8Cui,Lili2022-11-027-0/+542
* Support Intel AVX-IFMAHongyu Wang2022-11-0212-12/+245
* opcodes/arm: use '@' consistently for the comment characterAndrew Burgess2022-11-01121-2291/+2291
* x86: Silence GCC 12 warning on tc-i386.cH.J. Lu2022-10-311-4/+4
* Support Intel PREFETCHICui, Lili2022-10-3110-0/+91
* RX assembler: switch arguments of thw MVTACGU insn.Yoshinori Sato2022-10-311-4/+4
* RISC-V: Always generate mapping symbols at the start of the sections.Nelson Chu2022-10-292-28/+0
* RISC-V: Output mapping symbols with ISA string.Nelson Chu2022-10-2822-291/+273
* PowerPC: Add support for RFC02658 - MMA+ Outer-Product InstructionsPeter Bergner2022-10-273-0/+80
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