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* Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. A...Sergey Belyashov2020-01-022-455/+2046
* [ARM][gas] fix build breakage with gcc-10 by using correct enum typeSzabolcs Nagy2020-01-021-1/+1
* Update year range in copyright notice of binutils filesAlan Modra2020-01-01237-237/+237
* x86: adjust ignored prefix warning for branchesJan Beulich2019-12-271-6/+6
* x86-64: correct / adjust prefix emissionJan Beulich2019-12-271-12/+11
* x86-64: fix Intel64 handling of branch with data16 prefixJan Beulich2019-12-271-5/+39
* x86: consolidate Disp<NN> handling a littleJan Beulich2019-12-272-46/+51
* i386: Also check R12-R15 registers when optimizing testq to testbH.J. Lu2019-12-121-3/+2
* i386: Add -mbranches-within-32B-boundariesH.J. Lu2019-12-121-0/+13
* i386: Align branches within a fixed boundaryH.J. Lu2019-12-122-3/+1074
* gas signed overflow fixesAlan Modra2019-12-1210-52/+51
* obj-evax.c tidyAlan Modra2019-12-121-29/+22
* [gas][arm] Add -mwarn-restrict-itAndre Vieira2019-12-111-0/+7
* x86: further refine SSE check (SSE4a, SHA, GFNI)Jan Beulich2019-12-111-0/+3
* [gas][arm] Set context table for '.arch_extension'Andre Vieira2019-12-101-0/+1
* x86/Intel: fold "xmmword" with "oword"Jan Beulich2019-12-091-11/+9
* x86/Intel: support "mmword ptr"Jan Beulich2019-12-091-2/+5
* x86/Intel: fix "near ptr" / "far ptr" handlingJan Beulich2019-12-091-3/+6
* x86/Intel: drop pointless suffix setting for "tbyte ptr"Jan Beulich2019-12-091-10/+5
* x86/Intel: drop pointless suffix setting for "fword ptr"Jan Beulich2019-12-091-2/+0
* x86/Intel: drop pointless special casing of LxSJan Beulich2019-12-091-6/+1
* Arm64: simplify Crypto arch extension handlingJan Beulich2019-12-051-3/+1
* Arm64: correct "sha3" arch-extension directive handlingJan Beulich2019-12-051-3/+2
* x86-64: accept 64-bit LFS/LGS/LSS forms with suffix or operand size specifierJan Beulich2019-12-041-0/+9
* x86-64/Intel: fix CALL/JMP with dword operandJan Beulich2019-12-041-2/+3
* x86: consolidate tracking of MMX register useJan Beulich2019-12-041-9/+3
* x86: make sure all PUSH/POP honor DefaultSizeJan Beulich2019-12-041-8/+14
* x86: drop some stray/bogus DefaultSizeJan Beulich2019-12-041-1/+3
* gas/riscv: Produce version 3 DWARF CIE by defaultAndrew Burgess2019-11-281-0/+6
* binutils/gas/riscv: Add DWARF register numbers for CSRsAndrew Burgess2019-11-281-0/+4
* gas/riscv: Remove unneeded structureAndrew Burgess2019-11-281-7/+1
* Fix "psb CSYNC" and "bti C".Andrew Pinski2019-11-251-3/+6
* Arm: Change CRC from fpu feature to archititectural extensionMihail Ionescu2019-11-221-16/+17
* x86: fold individual Jump* attributes into a single Jump oneJan Beulich2019-11-142-34/+33
* x86: make JumpAbsolute an insn attributeJan Beulich2019-11-142-21/+35
* x86: make AnySize an insn attributeJan Beulich2019-11-141-1/+1
* [gas][arm] Enable VLDM, VSTM, VPUSH, VPOP for MVEMihail Ionescu2019-11-121-44/+65
* [binutils][arm] Update the decoding of MVE VMOV, VMVNMihail Ionescu2019-11-121-2/+0
* [gas][arm] Make .fpu reset the FPU/Coprocessor feature bitsMihail Ionescu2019-11-121-2/+1
* x86: fold EsSeg into IsStringJan Beulich2019-11-121-34/+23
* x86: eliminate ImmExt abuseJan Beulich2019-11-121-48/+2
* x86: introduce operand type "instance"Jan Beulich2019-11-121-29/+44
* i386: Only check suffix in instruction mnemonicH.J. Lu2019-11-081-42/+33
* x86: convert RegMask and RegBND from bitfield to enumeratorJan Beulich2019-11-081-6/+7
* x86: convert RegSIMD and RegMMX from bitfield to enumeratorJan Beulich2019-11-081-43/+45
* x86: convert Control/Debug/Test from bitfield to enumeratorJan Beulich2019-11-081-14/+14
* x86: convert SReg from bitfield to enumeratorJan Beulich2019-11-082-9/+10
* x86: introduce operand type "class"Jan Beulich2019-11-081-41/+59
* [Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]Matthew Malcomson2019-11-071-4/+83
* [binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson2019-11-071-0/+7