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path: root/bfd/elfnn-riscv.c
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* bfd/riscv: prepare to handle bare metal core dump creationAndrew Burgess2021-03-051-2/+82
* RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu2021-02-191-17/+17
* RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.Nelson Chu2021-02-181-2/+3
* RISC-V: PR27200, allow the first input non-ABI binary to be linked with any one.Nelson Chu2021-02-171-14/+16
* RISC-V: Fixed the indent that caused by the previous commits accidentally.Nelson Chu2021-01-151-1/+1
* RISC-V: Indent and GNU coding standards tidy, also aligned the code.Nelson Chu2021-01-151-109/+108
* RISC-V: Error and warning messages tidy.Nelson Chu2021-01-151-2/+2
* RISC-V: Comments tidy and improvement.Nelson Chu2021-01-151-49/+49
* RISC-V: Implement support for big endian targets.Marcus Comstedt2021-01-061-33/+74
* RISC-V: Ouput __global_pointer$ as dynamic symbol when generating dynamic PDE.Nelson Chu2021-01-051-0/+9
* RISC-V: Fix the merged orders of Z* extension for linker.Nelson Chu2021-01-041-34/+1
* Update year range in copyright notice of binutils filesAlan Modra2021-01-011-1/+1
* RISC-V: Support to add implicit extensions.Nelson Chu2020-12-011-9/+12
* RISC-V: Relax PCREL to GPREL while doing other relaxations is dangerous.Nelson Chu2020-11-211-13/+18
* RISC-V: Fix that IRELATIVE relocs may be inserted to the wrong place.Nelson Chu2020-10-161-7/+39
* RISC-V: Support GNU indirect functions.Nelson Chu2020-10-161-47/+678
* RISC-V: Minor cleanup and typos when merging elf attributes.Nelson Chu2020-09-031-12/+12
* RISC-V: Report warnings rather than errors for the mis-matched ISA versions.Nelson Chu2020-09-031-32/+39
* RISC-V: Improve the error message for the mis-matched ISA versions.Kito Cheng2020-09-031-1/+1
* PR26493 UBSAN: elfnn-riscv.c left shift of negative valueAlan Modra2020-08-311-3/+3
* RISC-V: Treat R_RISCV_CALL and R_RISCV_CALL_PLT as the same in check_relocs.Nelson Chu2020-08-281-9/+10
* elf_hash_table_id accessAlan Modra2020-08-251-2/+3
* elf: Add sym_cache to elf_link_hash_tableH.J. Lu2020-07-301-4/+1
* ELF: Add _bfd_elf_add_dynamic_tagsH.J. Lu2020-06-231-45/+1
* RISC-V: Report warning when linking the objects with different priv specs.Nelson Chu2020-06-221-11/+36
* RISC-V: Don't assume the priv attributes are in order when handling them.Nelson Chu2020-06-221-37/+36
* RISC-V: The object without priv spec attributes can be linked with any object.Nelson Chu2020-06-051-2/+38
* ELF: Consolidate maybe_set_textrelH.J. Lu2020-06-031-28/+2
* ELF: Copy dyn_relocs in _bfd_elf_link_hash_copy_indirectH.J. Lu2020-06-031-31/+0
* ELF: Consolidate readonly_dynrelocsH.J. Lu2020-06-031-19/+2
* ELF: Move dyn_relocs to struct elf_link_hash_entryH.J. Lu2020-06-011-21/+15
* Replace "if (x) free (x)" with "free (x)", bfdAlan Modra2020-05-211-3/+2
* [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions...Nelson Chu2020-05-201-1/+5
* RISC-V: Add elfNN_riscv_mkobject to initialize RISC-V tdata.Nelson Chu2020-05-141-0/+9
* PR25900, RISC-V: null pointer dereferenceAlan Modra2020-05-011-5/+6
* Indent labelsAlan Modra2020-02-261-3/+3
* bfd_size_type to size_tAlan Modra2020-02-191-2/+2
* RISC-V: Change -march parsing.Jim Wilson2020-01-221-63/+83
* RISC-V: Fix weak function call reloc overflow on llvm build.Jim Wilson2020-01-061-3/+6
* Update year range in copyright notice of binutils filesAlan Modra2020-01-011-1/+1
* RISC-V: Fix ld relax failure with calls and align directives.Jim Wilson2019-11-121-3/+10
* RISC-V: Report unresolved relocation error via linker's callback function.Jim Wilson2019-10-171-17/+46
* RISC-V: Optimize lui and auipc relaxations for undefweak symbol.Jim Wilson2019-09-201-27/+116
* bfd_section_* macrosAlan Modra2019-09-191-6/+5
* RISC-V: Fix linker problems with tls copy relocs.Jim Wilson2019-08-311-0/+14
* RISC-V: Force linker error exit after unresolvable reloc.Jim Wilson2019-08-301-1/+4
* RISC-V: Fix a gp relaxation reloc overflow error.Jim Wilson2019-08-281-7/+10
* RISC-V: Fix lui relaxation issue with code at address 0.Jim Wilson2019-08-151-2/+14
* RISC-V: Fix lui relax failure with relro.Jim Wilson2019-08-011-2/+7
* RISC-V: Enable lui relaxation for CODE and MERGE sections.Jim Wilson2019-06-241-10/+46
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