diff options
Diffstat (limited to 'sim/testsuite/sim/fr30/mulh.cgs')
| -rw-r--r-- | sim/testsuite/sim/fr30/mulh.cgs | 211 |
1 files changed, 211 insertions, 0 deletions
diff --git a/sim/testsuite/sim/fr30/mulh.cgs b/sim/testsuite/sim/fr30/mulh.cgs new file mode 100644 index 00000000000..1421f07b31a --- /dev/null +++ b/sim/testsuite/sim/fr30/mulh.cgs @@ -0,0 +1,211 @@ +# fr30 testcase for mulh $Rj,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global mulh +mulh: + ; Test mulh $Rj,$Ri + ; Positive operands + mvi_h_gr 0xdead0003,r7 ; multiply small numbers + mvi_h_gr 0xbeef0002,r8 + set_cc 0x09 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 1 + test_h_dr 6,mdl + + mvi_h_gr 0xdead0001,r7 ; multiply by 1 + mvi_h_gr 0xbeef0002,r8 + set_cc 0x08 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 0 + test_h_dr 2,mdl + + mvi_h_gr 0xdead0002,r7 ; multiply by 1 + mvi_h_gr 0xbeef0001,r8 + set_cc 0x09 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 1 + test_h_dr 2,mdl + + mvi_h_gr 0xdead0000,r7 ; multiply by 0 + mvi_h_gr 0xbeef0002,r8 + set_cc 0x09 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 1 + test_h_dr 0,mdl + + mvi_h_gr 0xdead0002,r7 ; multiply by 0 + mvi_h_gr 0xbeef0000,r8 + set_cc 0x08 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 0 + test_h_dr 0,mdl + + mvi_h_gr 0xdead3fff,r7 ; 15 bit result + mvi_h_gr 0xbeef0002,r8 + set_cc 0x09 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 1 + test_h_dr 0x00007ffe,mdl + + mvi_h_gr 0xdead4000,r7 ; 16 bit result + mvi_h_gr 0xbeef0002,r8 + set_cc 0x0a ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 1 0 + test_h_dr 0x00008000,mdl + + mvi_h_gr 0xdead4000,r7 ; 17 bit result + mvi_h_gr 0xbeef0004,r8 + set_cc 0x0b ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 1 1 + test_h_dr 0x00010000,mdl + + mvi_h_gr 0xdead7fff,r7 ; max positive result + mvi_h_gr 0xbeef7fff,r8 + set_cc 0x0b ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 1 1 + test_h_dr 0x3fff0001,mdl + + ; Mixed operands + mvi_h_gr -3,r7 ; multiply small numbers + mvi_h_gr 2,r8 + set_cc 0x05 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 0 1 + test_h_dr -6,mdl + + mvi_h_gr 3,r7 ; multiply small numbers + mvi_h_gr -2,r8 + set_cc 0x05 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 0 1 + test_h_dr -6,mdl + + mvi_h_gr 1,r7 ; multiply by 1 + mvi_h_gr -2,r8 + set_cc 0x04 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 0 0 + test_h_dr -2,mdl + + mvi_h_gr -2,r7 ; multiply by 1 + mvi_h_gr 1,r8 + set_cc 0x05 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 0 1 + test_h_dr -2,mdl + + mvi_h_gr 0,r7 ; multiply by 0 + mvi_h_gr -2,r8 + set_cc 0x09 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 1 + test_h_dr 0,mdl + + mvi_h_gr -2,r7 ; multiply by 0 + mvi_h_gr 0,r8 + set_cc 0x08 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 0 + test_h_dr 0,mdl + + mvi_h_gr 0xdead2001,r7 ; 15 bit result + mvi_h_gr -2,r8 + set_cc 0x05 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 0 1 + test_h_dr 0xffffbffe,mdl + + mvi_h_gr 0xdead4000,r7 ; 16 bit result + mvi_h_gr -2,r8 + set_cc 0x04 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 0 0 + test_h_dr 0xffff8000,mdl + + mvi_h_gr 0xdead4001,r7 ; 16 bit result + mvi_h_gr -2,r8 + set_cc 0x06 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 1 0 + test_h_dr 0xffff7ffe,mdl + + mvi_h_gr 0xdead4000,r7 ; 17 bit result + mvi_h_gr -4,r8 + set_cc 0x07 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 1 1 + test_h_dr 0xffff0000,mdl + + mvi_h_gr 0xdead7fff,r7 ; max negative result + mvi_h_gr 0xbeef8000,r8 + set_cc 0x07 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 1 1 + test_h_dr 0xc0008000,mdl + + ; Negative operands + mvi_h_gr -3,r7 ; multiply small numbers + mvi_h_gr -2,r8 + set_cc 0x09 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 1 + test_h_dr 6,mdl + + mvi_h_gr -1,r7 ; multiply by 1 + mvi_h_gr -2,r8 + set_cc 0x08 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 0 + test_h_dr 2,mdl + + mvi_h_gr -2,r7 ; multiply by 1 + mvi_h_gr -1,r8 + set_cc 0x09 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 1 + test_h_dr 2,mdl + + mvi_h_gr 0xdeadc001,r7 ; 15 bit result + mvi_h_gr -2,r8 + set_cc 0x09 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 1 + test_h_dr 0x00007ffe,mdl + + mvi_h_gr 0xdeadc000,r7 ; 16 bit result + mvi_h_gr -2,r8 + set_cc 0x0a ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 1 0 + test_h_dr 0x00008000,mdl + + mvi_h_gr 0xdeadc000,r7 ; 17 bit result + mvi_h_gr -4,r8 + set_cc 0x0b ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 1 1 + test_h_dr 0x00010000,mdl + + mvi_h_gr 0xdead8001,r7 ; almost max positive result + mvi_h_gr 0xbeef8001,r8 + set_cc 0x0b ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 1 1 + test_h_dr 0x3fff0001,mdl + + mvi_h_gr 0xdead8000,r7 ; max positive result + mvi_h_gr 0xbeef8000,r8 + set_cc 0x0b ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 1 1 + test_h_dr 0x40000000,mdl + + pass |