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-rw-r--r--sim/testsuite/sim/fr30/mov.cgs108
1 files changed, 108 insertions, 0 deletions
diff --git a/sim/testsuite/sim/fr30/mov.cgs b/sim/testsuite/sim/fr30/mov.cgs
new file mode 100644
index 00000000000..bf99252f061
--- /dev/null
+++ b/sim/testsuite/sim/fr30/mov.cgs
@@ -0,0 +1,108 @@
+# fr30 testcase for mov $Rj,$Ri
+# mach(): fr30
+
+ .include "testutils.inc"
+
+ START
+
+ .text
+ .global mov
+mov:
+ ; Test mov $Rj,$Ri
+ mvi_h_gr 1,r7
+ mvi_h_dr 0xa,tbr
+ mvi_h_dr 0xb,rp
+ mvi_h_dr 0xc,mdh
+ mvi_h_dr 0xd,mdl
+ mvr_h_gr sp,ssp
+ mvr_h_gr sp,usp
+
+ mov r7,r7
+ set_cc 0x0f ; Condition codes should not change
+ test_cc 1 1 1 1
+ test_h_gr 1,r7
+
+ mov r7,r8
+ set_cc 0x0e ; Condition codes should not change
+ test_cc 1 1 1 0
+ test_h_gr 1,r7
+ test_h_gr 1,r8
+
+ ; Test mov $Rs,$Ri
+ set_cc 0x0d ; Condition codes should not change
+ mov tbr,r7
+ test_cc 1 1 0 1
+ test_h_gr 0xa,r7
+
+ set_cc 0x0c ; Condition codes should not change
+ mov rp,r7
+ test_cc 1 1 0 0
+ test_h_gr 0xb,r7
+
+ set_cc 0x0b ; Condition codes should not change
+ mov mdh,r7
+ test_cc 1 0 1 1
+ test_h_gr 0xc,r7
+
+ set_cc 0x0a ; Condition codes should not change
+ mov mdl,r7
+ test_cc 1 0 1 0
+ test_h_gr 0xd,r7
+
+ set_cc 0x09 ; Condition codes should not change
+ mov usp,r7
+ test_cc 1 0 0 1
+ testr_h_gr sp,r7
+
+ set_cc 0x08 ; Condition codes should not change
+ mov ssp,r7
+ test_cc 1 0 0 0
+ testr_h_gr sp,r7
+
+ ; Test mov $Ri,$Rs
+ set_cc 0x07 ; Condition codes should not change
+ mov r8,tbr
+ test_cc 0 1 1 1
+ test_h_dr 0x1,tbr
+
+ set_cc 0x06 ; Condition codes should not change
+ mov r8,rp
+ test_cc 0 1 1 0
+ test_h_dr 0x1,rp
+
+ set_cc 0x05 ; Condition codes should not change
+ mov r8,mdh
+ test_cc 0 1 0 1
+ test_h_dr 0x1,mdh
+
+ set_cc 0x04 ; Condition codes should not change
+ mov r8,mdl
+ test_cc 0 1 0 0
+ test_h_dr 0x1,mdl
+
+ set_cc 0x03 ; Condition codes should not change
+ mov r8,ssp
+ test_cc 0 0 1 1
+ test_h_dr 0x1,ssp
+
+ set_cc 0x02 ; Condition codes should not change
+ mov r8,usp
+ test_cc 0 0 1 0
+ test_h_dr 0x1,usp
+
+ ; Test mov $PS,$Ri
+ set_cc 0x01 ; Condition codes affect result
+ set_dbits 0x3
+ mov ps,r7
+ test_cc 0 0 0 1
+ test_h_gr 0x00000601,r7
+
+ ; Test mov $Ri,PS
+ set_cc 0x01 ; Set opposite of expected
+ set_dbits 0x1 ; Set opposite of expected
+ mvi_h_gr 0x0000040e,r7
+ mov r7,PS
+ test_cc 1 1 1 0
+ test_dbits 0x2
+
+ pass