diff options
Diffstat (limited to 'sim/testsuite/sh')
80 files changed, 9669 insertions, 0 deletions
diff --git a/sim/testsuite/sh/ChangeLog b/sim/testsuite/sh/ChangeLog new file mode 100644 index 00000000000..e3852f9eb91 --- /dev/null +++ b/sim/testsuite/sh/ChangeLog @@ -0,0 +1,77 @@ +2004-09-13 DJ Delorie <dj@redhat.com> + + * sim/sh/allinsn.exp: Set global_as_options and + global_ld_options appropriately for little endian builds. + * sim/sh/movua.s: Support little endian. + +2004-09-08 Michael Snyder <msnyder@redhat.com> + + Commited by Corinna Vinschen <vinschen@redhat.com> + * allinsn.exp: Add new tests. + * bandor.s: New file. + * bandornot.s: New file. + * bclr.s: New file. + * bld.s: New file. + * bldnot.s: New file. + * bset.s: New file. + * bst.s: New file. + * bxor.s: New file. + * clip.s: New file. + * div.s: New file. + * fail.s: New file, make sure fail works. + * fsca.s: New file. + * fsrra.s: New file. + * mov.s: New file. + * mulr.s: New file. + * pass.s: New file, make sure pass works. + * pushpop.s: New file. + * resbank.s: New file. + * testutils.inc (bf8k, bt8k, assertmem): New macros. + +2004-02-12 Michael Snyder <msnyder@redhat.com> + + * and.s, movi.s, sett.s: New files. + * allinsn.exp: Add new tests. + * testutils.inc (set_sr_bit): Fix macro labels. + +2004-01-07 Michael Snyder <msnyder@redhat.com> + + * dmxy.s, fipr.s, fpchg.s, ldrc.s, loop.s, movli.s, movua.s, + movxy.s, pabs.s, pclr.s, prnd.s, psub.s, pswap.s: New files. + * allinsn.exp: Add new tests. + * testutils.inc (set_sr_bit): Add argument. + (set_greg): Add .align directives. + +2003-08-11 Michael Snyder <msnyder@redhat.com> + + * macl.s: New file. + * macw.s: New file. + * allinsn.exp: Add new tests for mac.w and mac.l. + +2003-07-25 Michael Snyder <msnyder@redhat.com> + + * pshai.s, pshar.s, pshli.s, pshlr.s: New files. + * allinsn.exp: Add psha, pshl tests. + * pdec.s, pinc.s, padd.s, paddc.s: New files. + * allinsn.exp: Add pdec, pinc, padd, paddc tests. + * pand.s, pdmsb.s: New files. + * allinsn.exp: Add pand, pdmsb tests. + +2003-07-23 Michael Snyder <msnyder@redhat.com> + + * pmuls.s: New file. + +2003-07-08 Michael Snyder <msnyder@redhat.com> + + * allinsn.exp, testutils.inc, add.s, fabs.s, fadd.s, fcmpeq.s, + fcmpgt.s, fcnvds.s, fcnvsd.s, fdiv.s, fldi0.s, fldi1.s, flds.s, + float.s, fmac.s, fmov.s, fmul.s, fneg.s, frchg.s, fschg.s, + fsqrt.s, fsub.s, ftrc.s, shll16.s, shll2.s, shll8.s, shll.s, + shlr16.s, shlr2.s, shlr8.s, shlr.s, swap.s: New files. + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/sim/testsuite/sh/add.s b/sim/testsuite/sh/add.s new file mode 100644 index 00000000000..95192518a84 --- /dev/null +++ b/sim/testsuite/sh/add.s @@ -0,0 +1,86 @@ +# sh testcase for add +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 1 +_y: .long 1 + + start + +add_reg_reg_direct: + set_grs_a5a5 + mov.l i, r1 + mov.l j, r2 + add r1, r2 + test_gr0_a5a5 + assertreg 2 r1 + assertreg 4 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +add_reg_reg_indirect: + set_grs_a5a5 + mov.l x, r1 + mov.l y, r2 + mov.l @r1, r1 + mov.l @r2, r2 + add r1, r2 + test_gr0_a5a5 + assertreg 1 r1 + assertreg 2 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +add_imm_reg: + set_grs_a5a5 + add #0x16, r1 + test_gr0_a5a5 + assertreg 0xa5a5a5bb r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + .align 2 +x: .long _x +y: .long _y +i: .long 2 +j: .long 2 + diff --git a/sim/testsuite/sh/allinsn.exp b/sim/testsuite/sh/allinsn.exp new file mode 100644 index 00000000000..40d13929942 --- /dev/null +++ b/sim/testsuite/sh/allinsn.exp @@ -0,0 +1,89 @@ +# sh tests + +set all "sh shdsp" + +set global_as_options "" +set global_ld_options "" + +foreach opt $board_variant_list { + switch "x$opt" { + x-ml { set global_as_options "-little --defsym LITTLE=1" + set global_ld_options "-EL" } + } +} + +if [istarget sh-*elf] { + run_sim_test add.s $all + run_sim_test and.s $all + run_sim_test bandor.s sh + run_sim_test bandornot.s sh + run_sim_test bclr.s sh + run_sim_test bld.s sh + run_sim_test bldnot.s sh + run_sim_test bset.s sh + run_sim_test bst.s sh + run_sim_test bxor.s sh + run_sim_test clip.s sh + run_sim_test div.s sh + run_sim_test dmxy.s shdsp + run_sim_test fabs.s sh + run_sim_test fadd.s sh + run_sim_test fcmpeq.s sh + run_sim_test fcmpgt.s sh + run_sim_test fcnvds.s sh + run_sim_test fcnvsd.s sh + run_sim_test fdiv.s sh + run_sim_test fipr.s sh + run_sim_test fldi0.s sh + run_sim_test fldi1.s sh + run_sim_test flds.s sh + run_sim_test float.s sh + run_sim_test fmac.s sh + run_sim_test fmov.s sh + run_sim_test fmul.s sh + run_sim_test fneg.s sh + run_sim_test fpchg.s sh + run_sim_test frchg.s sh + run_sim_test fschg.s sh + run_sim_test fsqrt.s sh + run_sim_test fsub.s sh + run_sim_test ftrc.s sh + run_sim_test ldrc.s shdsp + run_sim_test loop.s shdsp + run_sim_test macl.s sh + run_sim_test macw.s sh + run_sim_test mov.s $all + run_sim_test movi.s $all + run_sim_test movli.s $all + run_sim_test movua.s $all + run_sim_test movxy.s shdsp + run_sim_test mulr.s sh + run_sim_test pabs.s shdsp + run_sim_test paddc.s shdsp + run_sim_test padd.s shdsp + run_sim_test pand.s shdsp + run_sim_test pclr.s shdsp + run_sim_test pdec.s shdsp + run_sim_test pdmsb.s shdsp + run_sim_test pinc.s shdsp + run_sim_test pmuls.s shdsp + run_sim_test prnd.s shdsp + run_sim_test pshai.s shdsp + run_sim_test pshar.s shdsp + run_sim_test pshli.s shdsp + run_sim_test pshlr.s shdsp + run_sim_test psub.s shdsp + run_sim_test pswap.s shdsp + run_sim_test pushpop.s sh + run_sim_test resbank.s sh + run_sim_test sett.s sh + run_sim_test shll.s $all + run_sim_test shll2.s $all + run_sim_test shll8.s $all + run_sim_test shll16.s $all + run_sim_test shlr.s $all + run_sim_test shlr2.s $all + run_sim_test shlr8.s $all + run_sim_test shlr16.s $all + run_sim_test swap.s $all +} diff --git a/sim/testsuite/sh/and.s b/sim/testsuite/sh/and.s new file mode 100644 index 00000000000..00934473f97 --- /dev/null +++ b/sim/testsuite/sh/and.s @@ -0,0 +1,89 @@ +# sh testcase for and +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0xa5a5a5a5 +_y: .long 0x55555555 + + start + +and_reg_reg_direct: + set_grs_a5a5 + mov.l i, r1 + mov.l j, r2 + and r1, r2 + test_gr0_a5a5 + assertreg 0xa5a5a5a5 r1 + assertreg 0xa0a0a0a0 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + bra and_imm_reg + nop + + .align 2 +i: .long 0xa5a5a5a5 +j: .long 0xaaaaaaaa + +and_imm_reg: + set_grs_a5a5 + and #0xff, r0 + assertreg 0xa5, r0 + test_gr_a5a5 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +and_b_imm_ind: + set_grs_a5a5 + mov.l x, r0 + and.b #0x55, @(r0, GBR) + mov.l @r0, r0 + + assertreg 0xa5a5a505, r0 + test_gr_a5a5 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + .align 2 +x: .long _x +y: .long _y + diff --git a/sim/testsuite/sh/bandor.s b/sim/testsuite/sh/bandor.s new file mode 100644 index 00000000000..9ada4850696 --- /dev/null +++ b/sim/testsuite/sh/bandor.s @@ -0,0 +1,120 @@ +# sh testcase for band, bor +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0xa5a5a5a5 + + start + +bandor_b_imm_disp12_reg: + set_grs_a5a5 + # Make sure T is true to start. + sett + + mov.l x, r1 + + band.b #0, @(3, r1) + bf8k mfail + bor.b #1, @(3, r1) + bf8k mfail + band.b #2, @(3, r1) + bf8k mfail + bor.b #3, @(3, r1) + bf8k mfail + + bor.b #4, @(3, r1) + bf8k mfail + band.b #5, @(3, r1) + bf8k mfail + bor.b #6, @(3, r1) + bf8k mfail + band.b #7, @(3, r1) + bf8k mfail + + band.b #0, @(2, r1) + bf8k mfail + bor.b #1, @(2, r1) + bf8k mfail + band.b #2, @(2, r1) + bf8k mfail + bor.b #3, @(2, r1) + bf8k mfail + + bra .L2 + nop + + .align 2 +x: .long _x + +.L2: + bor.b #4, @(2, r1) + bf8k mfail + band.b #5, @(2, r1) + bf8k mfail + bor.b #6, @(2, r1) + bf8k mfail + band.b #7, @(2, r1) + bf8k mfail + + band.b #0, @(1, r1) + bf8k mfail + bor.b #1, @(1, r1) + bf8k mfail + band.b #2, @(1, r1) + bf8k mfail + bor.b #3, @(1, r1) + bf8k mfail + + bor.b #4, @(1, r1) + bf8k mfail + band.b #5, @(1, r1) + bf8k mfail + bor.b #6, @(1, r1) + bf8k mfail + band.b #7, @(1, r1) + bf8k mfail + + band.b #0, @(0, r1) + bf8k mfail + bor.b #1, @(0, r1) + bf8k mfail + band.b #2, @(0, r1) + bf8k mfail + bor.b #3, @(0, r1) + bf8k mfail + + bor.b #4, @(0, r1) + bf8k mfail + band.b #5, @(0, r1) + bf8k mfail + bor.b #6, @(0, r1) + bf8k mfail + band.b #7, @(0, r1) + bf8k mfail + + assertreg _x, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + diff --git a/sim/testsuite/sh/bandornot.s b/sim/testsuite/sh/bandornot.s new file mode 100644 index 00000000000..1787d0d92fb --- /dev/null +++ b/sim/testsuite/sh/bandornot.s @@ -0,0 +1,120 @@ +# sh testcase for bandnot, bornot +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0xa5a5a5a5 + + start + +bandor_b_imm_disp12_reg: + set_grs_a5a5 + # Make sure T is true to start. + sett + + mov.l x, r1 + + bandnot.b #0, @(3, r1) + bt8k mfail + bornot.b #1, @(3, r1) + bf8k mfail + bandnot.b #2, @(3, r1) + bt8k mfail + bornot.b #3, @(3, r1) + bf8k mfail + + bornot.b #4, @(3, r1) + bf8k mfail + bandnot.b #5, @(3, r1) + bt8k mfail + bornot.b #6, @(3, r1) + bf8k mfail + bandnot.b #7, @(3, r1) + bt8k mfail + + bandnot.b #0, @(2, r1) + bt8k mfail + bornot.b #1, @(2, r1) + bf8k mfail + bandnot.b #2, @(2, r1) + bt8k mfail + bornot.b #3, @(2, r1) + bf8k mfail + + bra .L2 + nop + + .align 2 +x: .long _x + +.L2: + bornot.b #4, @(2, r1) + bf8k mfail + bandnot.b #5, @(2, r1) + bt8k mfail + bornot.b #6, @(2, r1) + bf8k mfail + bandnot.b #7, @(2, r1) + bt8k mfail + + bandnot.b #0, @(1, r1) + bt8k mfail + bornot.b #1, @(1, r1) + bf8k mfail + bandnot.b #2, @(1, r1) + bt8k mfail + bornot.b #3, @(1, r1) + bf8k mfail + + bornot.b #4, @(1, r1) + bf8k mfail + bandnot.b #5, @(1, r1) + bt8k mfail + bornot.b #6, @(1, r1) + bf8k mfail + bandnot.b #7, @(1, r1) + bt8k mfail + + bandnot.b #0, @(0, r1) + bt8k mfail + bornot.b #1, @(0, r1) + bf8k mfail + bandnot.b #2, @(0, r1) + bt8k mfail + bornot.b #3, @(0, r1) + bf8k mfail + + bornot.b #4, @(0, r1) + bf8k mfail + bandnot.b #5, @(0, r1) + bt8k mfail + bornot.b #6, @(0, r1) + bf8k mfail + bandnot.b #7, @(0, r1) + bt8k mfail + + assertreg _x, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + diff --git a/sim/testsuite/sh/bclr.s b/sim/testsuite/sh/bclr.s new file mode 100644 index 00000000000..cbe1c7e618d --- /dev/null +++ b/sim/testsuite/sh/bclr.s @@ -0,0 +1,139 @@ +# sh testcase for bclr +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0xffffffff +_y: .long 0x55555555 + + start + +bclr_b_imm_disp12_reg: + set_grs_a5a5 + mov.l x, r1 + + bclr.b #0, @(3, r1) + assertmem _x, 0xfffffffe + bclr.b #1, @(3, r1) + assertmem _x, 0xfffffffc + bclr.b #2, @(3, r1) + assertmem _x, 0xfffffff8 + bclr.b #3, @(3, r1) + assertmem _x, 0xfffffff0 + + bclr.b #4, @(3, r1) + assertmem _x, 0xffffffe0 + bclr.b #5, @(3, r1) + assertmem _x, 0xffffffc0 + bclr.b #6, @(3, r1) + assertmem _x, 0xffffff80 + bclr.b #7, @(3, r1) + assertmem _x, 0xffffff00 + + bclr.b #0, @(2, r1) + assertmem _x, 0xfffffe00 + bclr.b #1, @(2, r1) + assertmem _x, 0xfffffc00 + bclr.b #2, @(2, r1) + assertmem _x, 0xfffff800 + bclr.b #3, @(2, r1) + assertmem _x, 0xfffff000 + + bra .L2 + nop + + .align 2 +x: .long _x +y: .long _y + +.L2: + bclr.b #4, @(2, r1) + assertmem _x, 0xffffe000 + bclr.b #5, @(2, r1) + assertmem _x, 0xffffc000 + bclr.b #6, @(2, r1) + assertmem _x, 0xffff8000 + bclr.b #7, @(2, r1) + assertmem _x, 0xffff0000 + + bclr.b #0, @(1, r1) + assertmem _x, 0xfffe0000 + bclr.b #1, @(1, r1) + assertmem _x, 0xfffc0000 + bclr.b #2, @(1, r1) + assertmem _x, 0xfff80000 + bclr.b #3, @(1, r1) + assertmem _x, 0xfff00000 + + bclr.b #4, @(1, r1) + assertmem _x, 0xffe00000 + bclr.b #5, @(1, r1) + assertmem _x, 0xffc00000 + bclr.b #6, @(1, r1) + assertmem _x, 0xff800000 + bclr.b #7, @(1, r1) + assertmem _x, 0xff000000 + + bclr.b #0, @(0, r1) + assertmem _x, 0xfe000000 + bclr.b #1, @(0, r1) + assertmem _x, 0xfc000000 + bclr.b #2, @(0, r1) + assertmem _x, 0xf8000000 + bclr.b #3, @(0, r1) + assertmem _x, 0xf0000000 + + bclr.b #4, @(0, r1) + assertmem _x, 0xe0000000 + bclr.b #5, @(0, r1) + assertmem _x, 0xc0000000 + bclr.b #6, @(0, r1) + assertmem _x, 0x80000000 + bclr.b #7, @(0, r1) + assertmem _x, 0x00000000 + + assertreg _x, r1 + +bclr_imm_reg: + set_greg 0xff, r1 + bclr #0, r1 + assertreg 0xfe, r1 + bclr #1, r1 + assertreg 0xfc, r1 + bclr #2, r1 + assertreg 0xf8, r1 + bclr #3, r1 + assertreg 0xf0, r1 + + bclr #4, r1 + assertreg 0xe0, r1 + bclr #5, r1 + assertreg 0xc0, r1 + bclr #6, r1 + assertreg 0x80, r1 + bclr #7, r1 + assertreg 0x00, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + diff --git a/sim/testsuite/sh/bld.s b/sim/testsuite/sh/bld.s new file mode 100644 index 00000000000..172718df676 --- /dev/null +++ b/sim/testsuite/sh/bld.s @@ -0,0 +1,121 @@ +# sh testcase for bld +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0xa5a5a5a5 +_y: .long 0x55555555 + + start + +bld_b_imm_disp12_reg: + set_grs_a5a5 + mov.l x, r1 + + bld.b #0, @(0, r1) + bf8k mfail + bld.b #1, @(0, r1) + bt8k mfail + bld.b #2, @(0, r1) + bf8k mfail + bld.b #3, @(0, r1) + bt8k mfail + + bld.b #4, @(0, r1) + bt8k mfail + bld.b #5, @(0, r1) + bf8k mfail + bld.b #6, @(0, r1) + bt8k mfail + bld.b #7, @(0, r1) + bf8k mfail + + bld.b #0, @(1, r1) + bf8k mfail + bld.b #1, @(1, r1) + bt8k mfail + bld.b #2, @(1, r1) + bf8k mfail + bld.b #3, @(1, r1) + bt8k mfail + + bld.b #4, @(1, r1) + bt8k mfail + bld.b #5, @(1, r1) + bf8k mfail + bld.b #6, @(1, r1) + bt8k mfail + bld.b #7, @(1, r1) + bf8k mfail + + bld.b #0, @(2, r1) + bf8k mfail + bld.b #1, @(2, r1) + bt8k mfail + bld.b #2, @(2, r1) + bf8k mfail + bld.b #3, @(2, r1) + bt8k mfail + + bld.b #4, @(2, r1) + bt8k mfail + bld.b #5, @(2, r1) + bf8k mfail + bld.b #6, @(2, r1) + bt8k mfail + bld.b #7, @(2, r1) + bf8k mfail + + bld.b #0, @(3, r1) + bf8k mfail + bld.b #1, @(3, r1) + bt8k mfail + bld.b #2, @(3, r1) + bf8k mfail + bld.b #3, @(3, r1) + bt8k mfail + + bld.b #4, @(3, r1) + bt8k mfail + bld.b #5, @(3, r1) + bf8k mfail + bld.b #6, @(3, r1) + bt8k mfail + bld.b #7, @(3, r1) + bf8k mfail + + assertreg _x, r1 + +bld_imm_reg: + set_greg 0xa5a5a5a5, r1 + bld #0, r1 + bf8k mfail + bld #1, r1 + bt8k mfail + bld #2, r1 + bf8k mfail + bld #3, r1 + bt8k mfail + + bld #4, r1 + bt8k mfail + bld #5, r1 + bf8k mfail + bld #6, r1 + bt8k mfail + bld #7, r1 + bf8k mfail + + test_grs_a5a5 + + pass + + exit 0 + + .align 2 +x: .long _x +y: .long _y + diff --git a/sim/testsuite/sh/bldnot.s b/sim/testsuite/sh/bldnot.s new file mode 100644 index 00000000000..eda87def9c2 --- /dev/null +++ b/sim/testsuite/sh/bldnot.s @@ -0,0 +1,102 @@ +# sh testcase for bldnot +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0xa5a5a5a5 +_y: .long 0x55555555 + + start + +bldnot_b_imm_disp12_reg: + set_grs_a5a5 + mov.l x, r1 + + bldnot.b #0, @(0, r1) + bt8k mfail + bldnot.b #1, @(0, r1) + bf8k mfail + bldnot.b #2, @(0, r1) + bt8k mfail + bldnot.b #3, @(0, r1) + bf8k mfail + + bldnot.b #4, @(0, r1) + bf8k mfail + bldnot.b #5, @(0, r1) + bt8k mfail + bldnot.b #6, @(0, r1) + bf8k mfail + bldnot.b #7, @(0, r1) + bt8k mfail + + bldnot.b #0, @(1, r1) + bt8k mfail + bldnot.b #1, @(1, r1) + bf8k mfail + bldnot.b #2, @(1, r1) + bt8k mfail + bldnot.b #3, @(1, r1) + bf8k mfail + + bldnot.b #4, @(1, r1) + bf8k mfail + bldnot.b #5, @(1, r1) + bt8k mfail + bldnot.b #6, @(1, r1) + bf8k mfail + bldnot.b #7, @(1, r1) + bt8k mfail + + bldnot.b #0, @(2, r1) + bt8k mfail + bldnot.b #1, @(2, r1) + bf8k mfail + bldnot.b #2, @(2, r1) + bt8k mfail + bldnot.b #3, @(2, r1) + bf8k mfail + + bldnot.b #4, @(2, r1) + bf8k mfail + bldnot.b #5, @(2, r1) + bt8k mfail + bldnot.b #6, @(2, r1) + bf8k mfail + bldnot.b #7, @(2, r1) + bt8k mfail + + bldnot.b #0, @(3, r1) + bt8k mfail + bldnot.b #1, @(3, r1) + bf8k mfail + bldnot.b #2, @(3, r1) + bt8k mfail + bldnot.b #3, @(3, r1) + bf8k mfail + + bldnot.b #4, @(3, r1) + bf8k mfail + bldnot.b #5, @(3, r1) + bt8k mfail + bldnot.b #6, @(3, r1) + bf8k mfail + bldnot.b #7, @(3, r1) + bt8k mfail + + assertreg _x, r1 + set_greg 0xa5a5a5a5, r1 + + test_grs_a5a5 + + pass + + exit 0 + + .align 2 +x: .long _x +y: .long _y + diff --git a/sim/testsuite/sh/bset.s b/sim/testsuite/sh/bset.s new file mode 100644 index 00000000000..13ae246e39c --- /dev/null +++ b/sim/testsuite/sh/bset.s @@ -0,0 +1,139 @@ +# sh testcase for bset +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0 +_y: .long 0x55555555 + + start + +bset_b_imm_disp12_reg: + set_grs_a5a5 + mov.l x, r1 + + bset.b #0, @(3, r1) + assertmem _x, 0x1 + bset.b #1, @(3, r1) + assertmem _x, 0x3 + bset.b #2, @(3, r1) + assertmem _x, 0x7 + bset.b #3, @(3, r1) + assertmem _x, 0xf + + bset.b #4, @(3, r1) + assertmem _x, 0x1f + bset.b #5, @(3, r1) + assertmem _x, 0x3f + bset.b #6, @(3, r1) + assertmem _x, 0x7f + bset.b #7, @(3, r1) + assertmem _x, 0xff + + bset.b #0, @(2, r1) + assertmem _x, 0x1ff + bset.b #1, @(2, r1) + assertmem _x, 0x3ff + bset.b #2, @(2, r1) + assertmem _x, 0x7ff + bset.b #3, @(2, r1) + assertmem _x, 0xfff + + bra .L2 + nop + + .align 2 +x: .long _x +y: .long _y + +.L2: + bset.b #4, @(2, r1) + assertmem _x, 0x1fff + bset.b #5, @(2, r1) + assertmem _x, 0x3fff + bset.b #6, @(2, r1) + assertmem _x, 0x7fff + bset.b #7, @(2, r1) + assertmem _x, 0xffff + + bset.b #0, @(1, r1) + assertmem _x, 0x1ffff + bset.b #1, @(1, r1) + assertmem _x, 0x3ffff + bset.b #2, @(1, r1) + assertmem _x, 0x7ffff + bset.b #3, @(1, r1) + assertmem _x, 0xfffff + + bset.b #4, @(1, r1) + assertmem _x, 0x1fffff + bset.b #5, @(1, r1) + assertmem _x, 0x3fffff + bset.b #6, @(1, r1) + assertmem _x, 0x7fffff + bset.b #7, @(1, r1) + assertmem _x, 0xffffff + + bset.b #0, @(0, r1) + assertmem _x, 0x1ffffff + bset.b #1, @(0, r1) + assertmem _x, 0x3ffffff + bset.b #2, @(0, r1) + assertmem _x, 0x7ffffff + bset.b #3, @(0, r1) + assertmem _x, 0xfffffff + + bset.b #4, @(0, r1) + assertmem _x, 0x1fffffff + bset.b #5, @(0, r1) + assertmem _x, 0x3fffffff + bset.b #6, @(0, r1) + assertmem _x, 0x7fffffff + bset.b #7, @(0, r1) + assertmem _x, 0xffffffff + + assertreg _x, r1 + +bset_imm_reg: + set_greg 0, r1 + bset #0, r1 + assertreg 0x1, r1 + bset #1, r1 + assertreg 0x3, r1 + bset #2, r1 + assertreg 0x7, r1 + bset #3, r1 + assertreg 0xf, r1 + + bset #4, r1 + assertreg 0x1f, r1 + bset #5, r1 + assertreg 0x3f, r1 + bset #6, r1 + assertreg 0x7f, r1 + bset #7, r1 + assertreg 0xff, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + diff --git a/sim/testsuite/sh/bst.s b/sim/testsuite/sh/bst.s new file mode 100644 index 00000000000..e8b6d656ec3 --- /dev/null +++ b/sim/testsuite/sh/bst.s @@ -0,0 +1,142 @@ +# sh testcase for bst +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0 +_y: .long 0x55555555 + + start + +bst_b_imm_disp12_reg: + set_grs_a5a5 + # Make sure T is true to start. + sett + + mov.l x, r1 + + bst.b #0, @(3, r1) + assertmem _x, 0x1 + bst.b #1, @(3, r1) + assertmem _x, 0x3 + bst.b #2, @(3, r1) + assertmem _x, 0x7 + bst.b #3, @(3, r1) + assertmem _x, 0xf + + bst.b #4, @(3, r1) + assertmem _x, 0x1f + bst.b #5, @(3, r1) + assertmem _x, 0x3f + bst.b #6, @(3, r1) + assertmem _x, 0x7f + bst.b #7, @(3, r1) + assertmem _x, 0xff + + bst.b #0, @(2, r1) + assertmem _x, 0x1ff + bst.b #1, @(2, r1) + assertmem _x, 0x3ff + bst.b #2, @(2, r1) + assertmem _x, 0x7ff + bst.b #3, @(2, r1) + assertmem _x, 0xfff + + bra .L2 + nop + + .align 2 +x: .long _x +y: .long _y + +.L2: + bst.b #4, @(2, r1) + assertmem _x, 0x1fff + bst.b #5, @(2, r1) + assertmem _x, 0x3fff + bst.b #6, @(2, r1) + assertmem _x, 0x7fff + bst.b #7, @(2, r1) + assertmem _x, 0xffff + + bst.b #0, @(1, r1) + assertmem _x, 0x1ffff + bst.b #1, @(1, r1) + assertmem _x, 0x3ffff + bst.b #2, @(1, r1) + assertmem _x, 0x7ffff + bst.b #3, @(1, r1) + assertmem _x, 0xfffff + + bst.b #4, @(1, r1) + assertmem _x, 0x1fffff + bst.b #5, @(1, r1) + assertmem _x, 0x3fffff + bst.b #6, @(1, r1) + assertmem _x, 0x7fffff + bst.b #7, @(1, r1) + assertmem _x, 0xffffff + + bst.b #0, @(0, r1) + assertmem _x, 0x1ffffff + bst.b #1, @(0, r1) + assertmem _x, 0x3ffffff + bst.b #2, @(0, r1) + assertmem _x, 0x7ffffff + bst.b #3, @(0, r1) + assertmem _x, 0xfffffff + + bst.b #4, @(0, r1) + assertmem _x, 0x1fffffff + bst.b #5, @(0, r1) + assertmem _x, 0x3fffffff + bst.b #6, @(0, r1) + assertmem _x, 0x7fffffff + bst.b #7, @(0, r1) + assertmem _x, 0xffffffff + + assertreg _x, r1 + +bst_imm_reg: + set_greg 0, r1 + bst #0, r1 + assertreg 0x1, r1 + bst #1, r1 + assertreg 0x3, r1 + bst #2, r1 + assertreg 0x7, r1 + bst #3, r1 + assertreg 0xf, r1 + + bst #4, r1 + assertreg 0x1f, r1 + bst #5, r1 + assertreg 0x3f, r1 + bst #6, r1 + assertreg 0x7f, r1 + bst #7, r1 + assertreg 0xff, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + diff --git a/sim/testsuite/sh/bxor.s b/sim/testsuite/sh/bxor.s new file mode 100644 index 00000000000..abedd38eb09 --- /dev/null +++ b/sim/testsuite/sh/bxor.s @@ -0,0 +1,120 @@ +# sh testcase for bxor +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0xa5a5a5a5 + + start + +bxor_b_imm_disp12_reg: + set_grs_a5a5 + # Make sure T is true to start. + sett + + mov.l x, r1 + + bxor.b #0, @(3, r1) + bt8k mfail + bxor.b #1, @(3, r1) + bt8k mfail + bxor.b #2, @(3, r1) + bf8k mfail + bxor.b #3, @(3, r1) + bf8k mfail + + bxor.b #4, @(3, r1) + bf8k mfail + bxor.b #5, @(3, r1) + bt8k mfail + bxor.b #6, @(3, r1) + bt8k mfail + bxor.b #7, @(3, r1) + bf8k mfail + + bxor.b #0, @(2, r1) + bt8k mfail + bxor.b #1, @(2, r1) + bt8k mfail + bxor.b #2, @(2, r1) + bf8k mfail + bxor.b #3, @(2, r1) + bf8k mfail + + bra .L2 + nop + + .align 2 +x: .long _x + +.L2: + bxor.b #4, @(2, r1) + bf8k mfail + bxor.b #5, @(2, r1) + bt8k mfail + bxor.b #6, @(2, r1) + bt8k mfail + bxor.b #7, @(2, r1) + bf8k mfail + + bxor.b #0, @(1, r1) + bt8k mfail + bxor.b #1, @(1, r1) + bt8k mfail + bxor.b #2, @(1, r1) + bf8k mfail + bxor.b #3, @(1, r1) + bf8k mfail + + bxor.b #4, @(1, r1) + bf8k mfail + bxor.b #5, @(1, r1) + bt8k mfail + bxor.b #6, @(1, r1) + bt8k mfail + bxor.b #7, @(1, r1) + bf8k mfail + + bxor.b #0, @(0, r1) + bt8k mfail + bxor.b #1, @(0, r1) + bt8k mfail + bxor.b #2, @(0, r1) + bf8k mfail + bxor.b #3, @(0, r1) + bf8k mfail + + bxor.b #4, @(0, r1) + bf8k mfail + bxor.b #5, @(0, r1) + bt8k mfail + bxor.b #6, @(0, r1) + bt8k mfail + bxor.b #7, @(0, r1) + bf8k mfail + + assertreg _x, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + diff --git a/sim/testsuite/sh/clip.s b/sim/testsuite/sh/clip.s new file mode 100644 index 00000000000..12770c381db --- /dev/null +++ b/sim/testsuite/sh/clip.s @@ -0,0 +1,89 @@ +# sh testcase for clips, clipu +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +clips_b: + set_grs_a5a5 + clips.b r1 + test_gr0_a5a5 + assertreg 0xffffff80 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +clipu_b: + set_grs_a5a5 + clipu.b r1 + test_gr0_a5a5 + assertreg 0xff r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +clips_w: + set_grs_a5a5 + clips.w r1 + test_gr0_a5a5 + assertreg 0xffff8000 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +clipu_w: + set_grs_a5a5 + clipu.w r1 + test_gr0_a5a5 + assertreg 0xffff r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + diff --git a/sim/testsuite/sh/div.s b/sim/testsuite/sh/div.s new file mode 100644 index 00000000000..8293c2117f1 --- /dev/null +++ b/sim/testsuite/sh/div.s @@ -0,0 +1,199 @@ +# sh testcase for divs and divu +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +divs_1: ! divide by one + set_grs_a5a5 + mov #1, r0 + divs r0, r1 + assertreg0 1 + test_gr_a5a5 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +divs_2: ! divide by two + set_grs_a5a5 + mov #2, r0 + divs r0, r1 + assertreg0 2 + assertreg 0xd2d2d2d3, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +divs_3: ! divide by three + set_grs_a5a5 + mov #3, r0 + divs r0, r1 + assertreg0 3 + assertreg 0xe1e1e1e2, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +divs_0: ! divide by zero + set_grs_a5a5 + mov #0, r0 + divs r0, r1 + assertreg0 0 + assertreg 0x7fffffff, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +divs_o: ! divide signed overflow + set_grs_a5a5 + mov #16, r0 + movi20 #0x8000, r1 + shad r0, r1 ! r1 == 0x80000000 + mov #-1, r0 + divs r0, r1 + assertreg0 -1 + assertreg 0x7fffffff, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + +divu_1: ! divide by one, unsigned + set_grs_a5a5 + mov #1, r0 + divu r0, r1 + assertreg0 1 + test_gr_a5a5 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +divu_2: ! divide by two, unsigned + set_grs_a5a5 + mov #2, r0 + divu r0, r1 + assertreg0 2 + assertreg 0x52d2d2d2, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +divu_3: ! divide by three, unsigned + set_grs_a5a5 + mov #3, r0 + divu r0, r1 + assertreg0 3 + assertreg 0x37373737, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +divu_0: ! divide by zero, unsigned + set_grs_a5a5 + mov #0, r0 + divu r0, r1 + assertreg0 0 + assertreg 0xffffffff, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + + pass + + exit 0 + +
\ No newline at end of file diff --git a/sim/testsuite/sh/dmxy.s b/sim/testsuite/sh/dmxy.s new file mode 100644 index 00000000000..0e96963aee9 --- /dev/null +++ b/sim/testsuite/sh/dmxy.s @@ -0,0 +1,21 @@ +# sh testcase for setdmx, setdmy, clrdmxy +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + setdmx + test_sr_bit_set 0x400 + test_sr_bit_clear 0x800 + setdmy + test_sr_bit_clear 0x400 + test_sr_bit_set 0x800 + clrdmxy + test_sr_bit_clear 0x400 + test_sr_bit_clear 0x800 + + test_grs_a5a5 + pass + exit 0 diff --git a/sim/testsuite/sh/fabs.s b/sim/testsuite/sh/fabs.s new file mode 100644 index 00000000000..1fb354e5922 --- /dev/null +++ b/sim/testsuite/sh/fabs.s @@ -0,0 +1,115 @@ +# sh testcase for fabs +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fabs_freg_b0: + single_prec + bank0 + set_grs_a5a5 + set_fprs_a5a5 + # fabs(0.0) = 0.0. + fldi0 fr0 + fabs fr0 + fldi0 fr1 + fcmp/eq fr0, fr1 + bt .L1 + fail +.L1: + # fabs(1.0) = 1.0. + fldi1 fr0 + fabs fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bt .L2 + fail +.L2: + # fabs(-1.0) = 1.0. + fldi1 fr0 + fneg fr0 + fabs fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bt .L3 + fail +.L3: + test_grs_a5a5 + test_fpr_a5a5 fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fabs_dreg_b0: + # double precision tests. + set_grs_a5a5 + set_fprs_a5a5 + double_prec + # fabs(0.0) = 0.0. + fldi0 fr0 + flds fr0, fpul + fcnvsd fpul, dr0 + fabs dr0 + assert_dpreg_i 0 dr0 + + # fabs(1.0) = 1.0. + fldi1 fr0 + flds fr0, fpul + fcnvsd fpul, dr0 + fabs dr0 + assert_dpreg_i 1 dr0 + + # check. + fldi1 fr2 + flds fr2, fpul + fcnvsd fpul, dr2 + fcmp/eq dr0, dr2 + bt .L4 + fail + +.L4: + # fabs(-1.0) = 1.0. + fldi1 fr0 + fneg fr0 + flds fr0, fpul + fcnvsd fpul, dr0 + fabs dr0 + assert_dpreg_i 1 dr0 + + # check. + fldi1 fr2 + flds fr2, fpul + fcnvsd fpul, dr2 + fcmp/eq dr0, dr2 + bt .L5 + fail +.L5: + test_grs_a5a5 + assert_dpreg_i 1 dr0 + assert_dpreg_i 1 dr2 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sh/fadd.s b/sim/testsuite/sh/fadd.s new file mode 100644 index 00000000000..72431f0f871 --- /dev/null +++ b/sim/testsuite/sh/fadd.s @@ -0,0 +1,75 @@ +# sh testcase for fadd +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fadd_freg_freg_b0: + set_grs_a5a5 + set_fprs_a5a5 + bank0 + + fldi1 fr0 + fldi1 fr1 + fadd fr0, fr1 + assert_fpreg_i 2 fr1 + + fldi0 fr0 + fldi1 fr1 + fadd fr0, fr1 + assert_fpreg_i 1 fr1 + + fldi1 fr0 + fldi0 fr1 + fadd fr0, fr1 + assert_fpreg_i 1 fr1 + test_grs_a5a5 + assert_fpreg_i 1 fr0 + test_fpr_a5a5 fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fadd_dreg_dreg_b0: + set_grs_a5a5 + set_fprs_a5a5 + double_prec + fldi1 fr0 + fldi1 fr2 + flds fr0, fpul + fcnvsd fpul, dr0 + flds fr2, fpul + fcnvsd fpul, dr2 + fadd dr0, dr2 + fcnvds dr2, fpul + fsts fpul, fr0 + + test_grs_a5a5 + assert_fpreg_i 2, fr0 + assert_dpreg_i 2, dr2 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sh/fail.s b/sim/testsuite/sh/fail.s new file mode 100644 index 00000000000..0ffb0b2a6ff --- /dev/null +++ b/sim/testsuite/sh/fail.s @@ -0,0 +1,13 @@ +# sh testcase, fail +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + + fail + + exit 0 + diff --git a/sim/testsuite/sh/fcmpeq.s b/sim/testsuite/sh/fcmpeq.s new file mode 100644 index 00000000000..9c0ef57298e --- /dev/null +++ b/sim/testsuite/sh/fcmpeq.s @@ -0,0 +1,119 @@ +# sh testcase for fcmpeq +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fcmpeq_single: + set_grs_a5a5 + set_fprs_a5a5 + # 1.0 == 1.0. + fldi1 fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bt .L0 + fail +.L0: + # 0.0 != 1.0. + fldi0 fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bf .L1 + fail +.L1: + # 1.0 != 0.0. + fldi1 fr0 + fldi0 fr1 + fcmp/eq fr0, fr1 + bf .L2 + fail +.L2: + # 2.0 != 1.0 + fldi1 fr0 + fadd fr0, fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bf .L3 + fail +.L3: + test_grs_a5a5 + assert_fpreg_i 2, fr0 + assert_fpreg_i 1, fr1 + test_fpr_a5a5 fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fcmpeq_double: + # 1.0 == 1.0 + set_grs_a5a5 + set_fprs_a5a5 + double_prec + fldi1 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fcmp/eq dr0, dr2 + bt .L10 + fail +.L10: + # 0.0 != 1.0 + fldi0 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fcmp/eq dr0, dr2 + bf .L11 + fail +.L11: + # 1.0 != 0.0 + fldi1 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fcmp/eq dr0, dr2 + bf .L12 + fail +.L12: + # 2.0 != 1.0 + fldi1 fr0 + single_prec + fadd fr0, fr0 + double_prec + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fcmp/eq dr0, dr2 + bf .L13 + fail +.L13: + test_grs_a5a5 + assert_dpreg_i 2, dr0 + assert_dpreg_i 1, dr2 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 + diff --git a/sim/testsuite/sh/fcmpgt.s b/sim/testsuite/sh/fcmpgt.s new file mode 100644 index 00000000000..c6945bae377 --- /dev/null +++ b/sim/testsuite/sh/fcmpgt.s @@ -0,0 +1,119 @@ +# sh testcase for fcmpgt +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fcmpgt_single: + set_grs_a5a5 + set_fprs_a5a5 + # 1.0 !> 1.0. + fldi1 fr0 + fldi1 fr1 + fcmp/gt fr0, fr1 + bf .L0 + fail +.L0: + # 0.0 !> 1.0. + fldi0 fr0 + fldi1 fr1 + fcmp/gt fr0, fr1 + bt .L1 + fail +.L1: + # 1.0 > 0.0. + fldi1 fr0 + fldi0 fr1 + fcmp/gt fr0, fr1 + bf .L2 + fail +.L2: + # 2.0 > 1.0 + fldi1 fr0 + fadd fr0, fr0 + fldi1 fr1 + fcmp/gt fr0, fr1 + bf .L3 + fail +.L3: + test_grs_a5a5 + assert_fpreg_i 2, fr0 + assert_fpreg_i 1, fr1 + test_fpr_a5a5 fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fcmpgt_double: + # double precision tests. + set_grs_a5a5 + set_fprs_a5a5 + double_prec + # 1.0 !> 1.0. + fldi1 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fcmp/gt dr0, dr2 + bf .L10 + fail +.L10: + # 0.0 !> 1.0. + fldi0 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fcmp/gt dr0, dr2 + bt .L11 + fail +.L11: + # 1.0 > 0.0. + fldi1 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fcmp/gt dr0, dr2 + bf .L12 + fail +.L12: + # 2.0 > 1.0. + fldi1 fr0 + single_prec + fadd fr0, fr0 + double_prec + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fcmp/gt dr0, dr2 + bf .L13 + fail +.L13: + test_grs_a5a5 + assert_dpreg_i 2, dr0 + assert_dpreg_i 1, dr2 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sh/fcnvds.s b/sim/testsuite/sh/fcnvds.s new file mode 100644 index 00000000000..cffcb4940b8 --- /dev/null +++ b/sim/testsuite/sh/fcnvds.s @@ -0,0 +1,56 @@ +# sh testcase for fcnvds +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start + double_prec + sz_64 + set_grs_a5a5 + set_fprs_a5a5 + mov.l ax, r0 + fmov @r0, dr0 + fcnvds dr0, fpul + fsts fpul, fr2 + + assert_dpreg_i 5, dr0 + single_prec + assert_fpreg_i 5, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + assertreg0 x + test_gr_a5a5 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + exit 0 + + .align 2 +x: .double 5.0 +ax: .long x + diff --git a/sim/testsuite/sh/fcnvsd.s b/sim/testsuite/sh/fcnvsd.s new file mode 100644 index 00000000000..6592540e4f1 --- /dev/null +++ b/sim/testsuite/sh/fcnvsd.s @@ -0,0 +1,40 @@ +# sh testcase for fcnvsd +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start + set_grs_a5a5 + set_fprs_a5a5 + double_prec + fldi1 fr0 + flds fr0, fpul + fcnvsd fpul, dr2 + assert_dpreg_i 1, dr2 + + # Convert back. + fcnvds dr2, fpul + fsts fpul, fr1 + single_prec + assert_fpreg_i 1, fr1 + fcmp/eq fr0, fr1 + bt .L0 + fail +.L0: + test_grs_a5a5 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + pass + exit 0 + diff --git a/sim/testsuite/sh/fdiv.s b/sim/testsuite/sh/fdiv.s new file mode 100644 index 00000000000..629e774bd67 --- /dev/null +++ b/sim/testsuite/sh/fdiv.s @@ -0,0 +1,91 @@ +# sh testcase for fdiv +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fdiv_single: + # Single test + set_grs_a5a5 + set_fprs_a5a5 + single_prec + # 1.0 / 0.0 should be INF + # (and not crash the sim). + fldi0 fr0 + fldi1 fr1 + fdiv fr0, fr1 + assert_fpreg_x 0x7f800000, fr1 + + # 0.0 / 1.0 == 0.0. + fldi0 fr0 + fldi1 fr1 + fdiv fr1, fr0 + assert_fpreg_x 0, fr0 + + # 2.0 / 1.0 == 2.0. + fldi1 fr1 + fldi1 fr2 + fadd fr2, fr2 + fdiv fr1, fr2 + assert_fpreg_i 2, fr2 + + # (1.0 / 2.0) + (1.0 / 2.0) == 1.0. + fldi1 fr1 + fldi1 fr2 + fadd fr2, fr2 + fdiv fr2, fr1 + # fr1 should contain 0.5. + fadd fr1, fr1 + assert_fpreg_i 1, fr1 + test_grs_a5a5 + assert_fpreg_i 2, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fdiv_double: + # Double test + set_grs_a5a5 + set_fprs_a5a5 + # (1.0 / 2.0) + (1.0 / 2.0) == 1.0. + fldi1 fr1 + fldi1 fr2 + # This add must be in single precision. The rest must be in double. + fadd fr2, fr2 + double_prec + _s2d fr1, dr0 + _s2d fr2, dr2 + fdiv dr2, dr0 + # dr0 should contain 0.5. + # double it, expect 1.0. + fadd dr0, dr0 + assert_dpreg_i 1, dr0 + assert_dpreg_i 2, dr2 + test_grs_a5a5 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 + diff --git a/sim/testsuite/sh/fipr.s b/sim/testsuite/sh/fipr.s new file mode 100644 index 00000000000..6a949aa6ec7 --- /dev/null +++ b/sim/testsuite/sh/fipr.s @@ -0,0 +1,137 @@ +# sh testcase for fipr $fvm, $fvn +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +initv0: + set_grs_a5a5 + set_fprs_a5a5 + # Load 1 into fr0. + fldi1 fr0 + # Load 2 into fr1. + fldi1 fr1 + fadd fr1, fr1 + # Load 4 into fr2. + fldi1 fr2 + fadd fr2, fr2 + fadd fr2, fr2 + # Load 8 into fr3. + fmov fr2, fr3 + fadd fr2, fr3 + +initv8: + fldi1 fr8 + fldi0 fr9 + fldi1 fr10 + fldi0 fr11 + + fipr fv0, fv8 +test1: + # Result will be in fr11. + assert_fpreg_i 1, fr0 + assert_fpreg_i 2, fr1 + assert_fpreg_i 4, fr2 + assert_fpreg_i 8, fr3 + assert_fpreg_x 0xa5a5a5a5, fr4 + assert_fpreg_x 0xa5a5a5a5, fr5 + assert_fpreg_x 0xa5a5a5a5, fr6 + assert_fpreg_x 0xa5a5a5a5, fr7 + assert_fpreg_i 1, fr8 + assert_fpreg_i 0, fr9 + assert_fpreg_i 1, fr10 + assert_fpreg_i 5, fr11 + assert_fpreg_x 0xa5a5a5a5, fr12 + assert_fpreg_x 0xa5a5a5a5, fr13 + assert_fpreg_x 0xa5a5a5a5, fr14 + assert_fpreg_x 0xa5a5a5a5, fr15 + + test_grs_a5a5 +test_infp: + # Test positive infinity + fldi0 fr11 + mov.l infp, r0 + lds r0, fpul + fsts fpul, fr0 + fipr fv0, fv8 + # fr11 should be plus infinity + assert_fpreg_x 0x7f800000, fr11 +test_infm: + # Test negitive infinity + fldi0 fr11 + mov.l infm, r0 + lds r0, fpul + fsts fpul, fr0 + fipr fv0, fv8 + # fr11 should be plus infinity + assert_fpreg_x 0xff800000, fr11 +test_qnanp: + # Test positive qnan + fldi0 fr11 + mov.l qnanp, r0 + lds r0, fpul + fsts fpul, fr0 + fipr fv0, fv8 + # fr11 should be plus qnan (or greater) + flds fr11, fpul + sts fpul, r1 + cmp/ge r0, r1 + bt .L0 + fail +.L0: +test_snanp: + # Test positive snan + fldi0 fr11 + mov.l snanp, r0 + lds r0, fpul + fsts fpul, fr0 + fipr fv0, fv8 + # fr11 should be plus snan (or greater) + flds fr11, fpul + sts fpul, r1 + cmp/ge r0, r1 + bt .L1 + fail +.L1: +.if 0 + # Handling of nan and inf not implemented yet. +test_qnanm: + # Test negantive qnan + fldi0 fr11 + mov.l qnanm, r0 + lds r0, fpul + fsts fpul, fr0 + fipr fv0, fv8 + # fr11 should be minus qnan (or less) + flds fr11, fpul + sts fpul, r1 + cmp/ge r1, r0 + bt .L2 + fail +.L2: +test_snanm: + # Test negative snan + fldi0 fr11 + mov.l snanm, r0 + lds r0, fpul + fsts fpul, fr0 + fipr fv0, fv8 + # fr11 should be minus snan (or less) + flds fr11, fpul + sts fpul, r1 + cmp/ge r1, r0 + bt .L3 + fail +.L3: +.endif + pass + exit 0 + + .align 2 +qnanp: .long 0x7f800001 +qnanm: .long 0xff800001 +snanp: .long 0x7fc00000 +snanm: .long 0xffc00000 +infp: .long 0x7f800000 +infm: .long 0xff800000 diff --git a/sim/testsuite/sh/fldi0.s b/sim/testsuite/sh/fldi0.s new file mode 100644 index 00000000000..1e2005832b0 --- /dev/null +++ b/sim/testsuite/sh/fldi0.s @@ -0,0 +1,37 @@ +# sh testcase for fldi0 $frn +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fldi0_single: + set_grs_a5a5 + set_fprs_a5a5 + fldi0 fr0 + fldi0 fr2 + fldi0 fr4 + fldi0 fr6 + fldi0 fr8 + fldi0 fr10 + fldi0 fr12 + fldi0 fr14 + test_grs_a5a5 + assert_fpreg_i 0 fr0 + assert_fpreg_i 0 fr2 + assert_fpreg_i 0 fr4 + assert_fpreg_i 0 fr6 + assert_fpreg_i 0 fr8 + assert_fpreg_i 0 fr10 + assert_fpreg_i 0 fr12 + assert_fpreg_i 0 fr14 + assert_fpreg_x 0xa5a5a5a5 fr1 + assert_fpreg_x 0xa5a5a5a5 fr3 + assert_fpreg_x 0xa5a5a5a5 fr5 + assert_fpreg_x 0xa5a5a5a5 fr7 + assert_fpreg_x 0xa5a5a5a5 fr9 + assert_fpreg_x 0xa5a5a5a5 fr11 + assert_fpreg_x 0xa5a5a5a5 fr13 + assert_fpreg_x 0xa5a5a5a5 fr15 + pass + exit 0 diff --git a/sim/testsuite/sh/fldi1.s b/sim/testsuite/sh/fldi1.s new file mode 100644 index 00000000000..1b7c1701c7d --- /dev/null +++ b/sim/testsuite/sh/fldi1.s @@ -0,0 +1,38 @@ +# sh testcase for fldi1 $frn +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fldi1_single: + set_grs_a5a5 + set_fprs_a5a5 + fldi1 fr1 + fldi1 fr3 + fldi1 fr5 + fldi1 fr7 + fldi1 fr9 + fldi1 fr11 + fldi1 fr13 + fldi1 fr15 + test_grs_a5a5 + assert_fpreg_x 0xa5a5a5a5 fr0 + assert_fpreg_x 0xa5a5a5a5 fr2 + assert_fpreg_x 0xa5a5a5a5 fr4 + assert_fpreg_x 0xa5a5a5a5 fr6 + assert_fpreg_x 0xa5a5a5a5 fr8 + assert_fpreg_x 0xa5a5a5a5 fr10 + assert_fpreg_x 0xa5a5a5a5 fr12 + assert_fpreg_x 0xa5a5a5a5 fr14 + assert_fpreg_i 1 fr1 + assert_fpreg_i 1 fr3 + assert_fpreg_i 1 fr5 + assert_fpreg_i 1 fr7 + assert_fpreg_i 1 fr9 + assert_fpreg_i 1 fr11 + assert_fpreg_i 1 fr13 + assert_fpreg_i 1 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sh/flds.s b/sim/testsuite/sh/flds.s new file mode 100644 index 00000000000..086b4edf057 --- /dev/null +++ b/sim/testsuite/sh/flds.s @@ -0,0 +1,43 @@ +# sh testcase for flds +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +flds_zero: + set_grs_a5a5 + set_fprs_a5a5 + fldi0 fr0 + flds fr0, fpul + fsts fpul, fr1 + fcmp/eq fr0, fr1 + bt flds_one + fail +flds_one: + fldi1 fr0 + flds fr0, fpul + fsts fpul, fr1 + fcmp/eq fr0, fr1 + bt .L0 + fail +.L0: + test_grs_a5a5 + assert_fpreg_i 1, fr0 + assert_fpreg_i 1, fr1 + test_fpr_a5a5 fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + pass + exit 0 diff --git a/sim/testsuite/sh/float.s b/sim/testsuite/sh/float.s new file mode 100644 index 00000000000..e5a3bc6dbfc --- /dev/null +++ b/sim/testsuite/sh/float.s @@ -0,0 +1,149 @@ +# sh testcase for float +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start + +float_pos: + set_grs_a5a5 + set_fprs_a5a5 + single_prec + mov #3, r0 + lds r0, fpul + float fpul, fr2 + + # Check the result. + fldi1 fr0 + fldi1 fr1 + fadd fr0, fr1 + fadd fr0, fr1 + fcmp/eq fr1, fr2 + bt float_neg + fail + +float_neg: + mov #3, r0 + neg r0, r0 + lds r0, fpul + float fpul, fr2 + + # Check the result. + fldi1 fr0 + fldi1 fr1 + fadd fr0, fr1 + fadd fr0, fr1 + fneg fr1 + fcmp/eq fr1, fr2 + bt .L0 + fail +.L0: + assertreg0 -3 + test_gr_a5a5 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + assert_fpreg_i 1, fr0 + assert_fpreg_i -3, fr1 + assert_fpreg_i -3, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +double_pos: + set_grs_a5a5 + set_fprs_a5a5 + double_prec + mov #3, r0 + lds r0, fpul + float fpul, dr4 + + # check the result. + fldi1 fr0 + fldi1 fr1 + single_prec + fadd fr0, fr1 + fadd fr0, fr1 + double_prec + _s2d fr1, dr2 + fcmp/eq dr2, dr4 + bt double_neg + fail + +double_neg: + double_prec + mov #3, r0 + neg r0, r0 + lds r0, fpul + float fpul, dr4 + + # check the result. + fldi1 fr0 + fldi1 fr1 + single_prec + fadd fr0, fr1 + fadd fr0, fr1 + fneg fr1 + double_prec + _s2d fr1, dr2 + fcmp/eq dr2, dr4 + bt .L2 + fail +.L2: + assertreg0 -3 + test_gr_a5a5 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + single_prec + assert_fpreg_i 1, fr0 + assert_fpreg_i -3, fr1 + double_prec + assert_dpreg_i -3, dr2 + assert_dpreg_i -3, dr4 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sh/fmac.s b/sim/testsuite/sh/fmac.s new file mode 100644 index 00000000000..eba1da5f4d8 --- /dev/null +++ b/sim/testsuite/sh/fmac.s @@ -0,0 +1,98 @@ +# sh testcase for fmac +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fmac_: + set_grs_a5a5 + set_fprs_a5a5 + # 0.0 * x + y = y. + + fldi0 fr0 + fldi1 fr1 + fldi1 fr2 + fmac fr0, fr1, fr2 + # check result. + fldi1 fr0 + fcmp/eq fr0, fr2 + bt .L0 + fail +.L0: + # x * y + 0.0 = x * y. + + fldi1 fr0 + fldi1 fr1 + fldi0 fr2 + # double it. + fadd fr1, fr2 + fmac fr0, fr1, fr2 + # check result. + fldi1 fr0 + fadd fr0, fr0 + fcmp/eq fr0, fr2 + bt .L1 + fail +.L1: + # x * 0.0 + y = y. + + fldi1 fr0 + fldi0 fr1 + fldi1 fr2 + fadd fr2, fr2 + fmac fr0, fr1, fr2 + # check result. + fldi1 fr0 + # double fr0. + fadd fr0, fr0 + fcmp/eq fr0, fr2 + bt .L2 + fail +.L2: + # x * 0.0 + 0.0 = 0.0 + + fldi1 fr0 + fadd fr0, fr0 + fldi0 fr1 + fldi0 fr2 + fmac fr0, fr1, fr2 + # check result. + fldi0 fr0 + fcmp/eq fr0, fr2 + bt .L3 + fail +.L3: + # 0.0 * x + 0.0 = 0.0. + + fldi0 fr0 + fldi1 fr1 + # double it. + fadd fr1, fr1 + fldi0 fr2 + fmac fr0, fr1, fr2 + # check result. + fldi0 fr0 + fcmp/eq fr0, fr2 + bt .L4 + fail +.L4: + test_grs_a5a5 + assert_fpreg_i 0, fr0 + assert_fpreg_i 2, fr1 + assert_fpreg_i 0, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + pass + exit 0 diff --git a/sim/testsuite/sh/fmov.s b/sim/testsuite/sh/fmov.s new file mode 100644 index 00000000000..29c51b5d1e5 --- /dev/null +++ b/sim/testsuite/sh/fmov.s @@ -0,0 +1,322 @@ +# sh testcase for all fmov instructions +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + .macro init + fldi0 fr0 + fldi1 fr1 + fldi1 fr2 + fldi1 fr3 + .endm + + start + +fmov1: # Test fr -> fr. + set_grs_a5a5 + set_fprs_a5a5 + init + single_prec + sz_32 + fmov fr0, fr1 + # Ensure fr0 and fr1 are now equal. + fcmp/eq fr0, fr1 + bt fmov2 + fail + +fmov2: # Test dr -> dr. + init + double_prec + sz_64 + fmov dr0, dr2 + # Ensure dr0 and dr2 are now equal. + fcmp/eq dr0, dr2 + bt fmov3 + fail + +fmov3: # Test dr -> xd and xd -> dr. + init + sz_64 + fmov dr0, xd0 + # Ensure dr0 and xd0 are now equal. + fmov xd0, dr2 + fcmp/eq dr0, dr2 + bt fmov4 + fail + +fmov4: # Test xd -> xd. + init + sz_64 + double_prec + fmov dr0, xd0 + fmov xd0, xd2 + fmov xd2, dr2 + # Ensure dr0 and dr2 are now equal. + fcmp/eq dr0, dr2 + bt .L0 + fail + + # FIXME: test fmov.s fr -> @gr, fmov dr -> @gr + # FIXME: test fmov.s @gr -> fr, fmov @gr -> dr + # FIXME: test fmov.s @gr+ -> fr, fmov @gr+ -> dr + # FIXME: test fmov.s fr -> @-gr, fmov dr -> @-gr + # FIXME: test fmov.s @(r0,gr) -> fr, fmov @(r0,gr) -> dr + # FIXME: test fmov.s fr -> @(r0,gr), fmov dr -> @(r0,gr) + +.L0: + test_grs_a5a5 + sz_32 + single_prec + assert_fpreg_i 0, fr0 + assert_fpreg_i 1, fr1 + assert_fpreg_i 0, fr2 + assert_fpreg_i 1, fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fmov5: # Test fr -> @rn and @rn -> fr. + init + sz_32 + single_prec + # FIXME! Use a reserved memory location! + mov #40, r0 + shll8 r0 + fmov fr0, @r0 + fmov @r0, fr1 + fcmp/eq fr0, fr1 + bt fmov6 + fail + +fmov6: # Test dr -> @rn and @rn -> dr. + init + sz_64 + double_prec + mov #40, r0 + shll8 r0 + fmov dr0, @r0 + fmov @r0, dr2 + fcmp/eq dr0, dr2 + bt fmov7 + fail + +fmov7: # Test xd -> @rn and @rn -> xd. + init + sz_64 + double_prec + mov #40, r0 + shll8 r0 + fmov dr0, xd0 + fmov xd0, @r0 + fmov @r0, xd2 + fmov xd2, dr2 + fcmp/eq dr0, dr2 + bt fmov8 + fail + +fmov8: # Test fr -> @-rn. + init + sz_32 + single_prec + mov #40, r0 + shll8 r0 + # Preserve. + mov r0, r1 + fmov fr0, @-r0 + fmov @r0, fr2 + fcmp/eq fr0, fr2 + bt f8b + fail +f8b: # check pre-dec. + add #4, r0 + cmp/eq r0, r1 + bt fmov9 + fail + +fmov9: # Test dr -> @-rn. + init + sz_64 + double_prec + mov #40, r0 + shll8 r0 + # Preserve r0. + mov r0, r1 + fmov dr0, @-r0 + fmov @r0, dr2 + fcmp/eq dr0, dr2 + bt f9b + fail +f9b: # check pre-dec. + add #8, r0 + cmp/eq r0, r1 + bt fmov10 + fail + +fmov10: # Test xd -> @-rn. + init + sz_64 + double_prec + mov #40, r0 + shll8 r0 + # Preserve r0. + mov r0, r1 + fmov dr0, xd0 + fmov xd0, @-r0 + fmov @r0, xd2 + fmov xd2, dr2 + fcmp/eq dr0, dr2 + bt f10b + fail +f10b: # check pre-dec. + add #8, r0 + cmp/eq r0, r1 + bt fmov11 + fail + +fmov11: # Test @rn+ -> fr. + init + sz_32 + single_prec + mov #40, r0 + shll8 r0 + # Preserve r0. + mov r0, r1 + fmov fr0, @r0 + fmov @r0+, fr2 + fcmp/eq fr0, fr2 + bt f11b + fail +f11b: # check post-inc. + add #4, r1 + cmp/eq r0, r1 + bt fmov12 + fail + +fmov12: # Test @rn+ -> dr. + init + sz_64 + double_prec + mov #40, r0 + shll8 r0 + # preserve r0. + mov r0, r1 + fmov dr0, @r0 + fmov @r0+, dr2 + fcmp/eq dr0, dr2 + bt f12b + fail +f12b: # check post-inc. + add #8, r1 + cmp/eq r0, r1 + bt fmov13 + fail + +fmov13: # Test @rn -> xd. + init + sz_64 + double_prec + mov #40, r0 + shll8 r0 + # Preserve r0. + mov r0, r1 + fmov dr0, xd0 + fmov xd0, @r0 + fmov @r0+, xd2 + fmov xd2, dr2 + fcmp/eq dr0, dr2 + bt f13b + fail +f13b: + add #8, r1 + cmp/eq r0, r1 + bt fmov14 + fail + +fmov14: # Test fr -> @(r0,rn), @(r0, rn) -> fr. + init + sz_32 + single_prec + mov #40, r0 + shll8 r0 + mov #0, r1 + fmov fr0, @(r0, r1) + fmov @(r0, r1), fr1 + fcmp/eq fr0, fr1 + bt fmov15 + fail + +fmov15: # Test dr -> @(r0, rn), @(r0, rn) -> dr. + init + sz_64 + double_prec + mov #40, r0 + shll8 r0 + mov #0, r1 + fmov dr0, @(r0, r1) + fmov @(r0, r1), dr2 + fcmp/eq dr0, dr2 + bt fmov16 + fail + +fmov16: # Test xd -> @(r0, rn), @(r0, rn) -> xd. + init + sz_64 + double_prec + mov #40, r0 + shll8 r0 + mov #0, r1 + fmov dr0, xd0 + fmov xd0, @(r0, r1) + fmov @(r0, r1), xd2 + fmov xd2, dr2 + fcmp/eq dr0, dr2 + bt .L1 + fail +.L1: + assertreg0 0x2800 + assertreg 0, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + sz_32 + single_prec + assert_fpreg_i 0, fr0 + assert_fpreg_i 1, fr1 + assert_fpreg_i 0, fr2 + assert_fpreg_i 1, fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sh/fmul.s b/sim/testsuite/sh/fmul.s new file mode 100644 index 00000000000..81a2545ccfa --- /dev/null +++ b/sim/testsuite/sh/fmul.s @@ -0,0 +1,116 @@ +# sh testcase for fmul +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + .macro init + fldi0 fr0 + fldi1 fr1 + fldi1 fr2 + fadd fr2, fr2 + .endm + + start +fmul_single: + set_grs_a5a5 + set_fprs_a5a5 + # 0.0 * 0.0 = 0.0. + init + fmul fr0, fr0 + assert_fpreg_i 0, fr0 + + # 0.0 * 1.0 = 0.0. + init + fmul fr1, fr0 + assert_fpreg_i 0, fr0 + + # 1.0 * 0.0 = 0.0. + init + fmul fr0, fr1 + assert_fpreg_i 0, fr1 + + # 1.0 * 1.0 = 1.0. + init + fmul fr1, fr1 + assert_fpreg_i 1, fr1 + + # 2.0 * 1.0 = 2.0. + init + fmul fr2, fr1 + assert_fpreg_i 2, fr1 + + test_grs_a5a5 + assert_fpreg_i 0, fr0 + assert_fpreg_i 2, fr1 + assert_fpreg_i 2, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + .macro dinit + fldi0 fr0 + fldi1 fr2 + fldi1 fr4 + single_prec + fadd fr4, fr4 + double_prec + _s2d fr0, dr0 + _s2d fr2, dr2 + _s2d fr4, dr4 + .endm + +fmul_double: + double_prec + # 0.0 * 0.0 = 0.0. + dinit + fmul dr0, dr0 + assert_dpreg_i 0, dr0 + + # 0.0 * 1.0 = 0.0. + dinit + fmul dr2, dr0 + assert_dpreg_i 0, dr0 + + # 1.0 * 0.0 = 0.0. + dinit + fmul dr0, dr2 + assert_dpreg_i 0, dr2 + + # 1.0 * 1.0 = 1.0. + dinit + fmul dr2, dr2 + assert_dpreg_i 1, dr2 + + # 2.0 * 1.0 = 2.0. + dinit + fmul dr4, dr2 + assert_dpreg_i 2, dr2 + + test_grs_a5a5 + assert_dpreg_i 0, dr0 + assert_dpreg_i 2, dr2 + assert_dpreg_i 2, dr4 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sh/fneg.s b/sim/testsuite/sh/fneg.s new file mode 100644 index 00000000000..dd5fe5d8bab --- /dev/null +++ b/sim/testsuite/sh/fneg.s @@ -0,0 +1,112 @@ +# sh testcase for fneg +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fneg_single: + set_grs_a5a5 + set_fprs_a5a5 + # neg(0.0) = 0.0. + fldi0 fr0 + fldi0 fr1 + fneg fr0 + fcmp/eq fr0, fr1 + bt .L0 + fail +.L0: + # neg(1.0) = fsub(0,1) + fldi1 fr0 + fneg fr0 + fldi0 fr1 + fldi1 fr2 + fsub fr2, fr1 + fcmp/eq fr0, fr1 + bt .L1 + fail +.L1: + # neg(neg(1.0)) = 1.0. + fldi1 fr0 + fldi1 fr1 + fneg fr0 + fneg fr0 + fcmp/eq fr0, fr1 + bt .L2 + fail +.L2: + test_grs_a5a5 + assert_fpreg_i 1, fr0 + assert_fpreg_i 1, fr1 + assert_fpreg_i 1, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fneg_double: + set_grs_a5a5 + set_fprs_a5a5 + double_prec + # neg(0.0) = 0.0. + fldi0 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fneg dr0 + fcmp/eq dr0, dr2 + bt .L10 + fail +.L10: + # neg(1.0) = fsub(0,1) + fldi1 fr0 + _s2d fr0, dr0 + fneg dr0 + fldi0 fr2 + fldi1 fr3 + single_prec + fsub fr3, fr2 + double_prec + _s2d fr2, dr2 + fcmp/eq dr0, dr2 + bt .L11 + fail +.L11: + # neg(neg(1.0)) = 1.0. + fldi1 fr0 + _s2d fr0, dr0 + fldi1 fr2 + _s2d fr2, dr2 + fneg dr2 + fneg dr2 + fcmp/eq dr0, dr2 + bt .L12 + fail +.L12: + test_grs_a5a5 + assert_dpreg_i 1, dr0 + assert_dpreg_i 1, dr2 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sh/fpchg.s b/sim/testsuite/sh/fpchg.s new file mode 100644 index 00000000000..47ba03b1c03 --- /dev/null +++ b/sim/testsuite/sh/fpchg.s @@ -0,0 +1,30 @@ +# sh testcase for fpchg +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start + set_grs_a5a5 + set_fprs_a5a5 + sts fpscr, r0 + assertreg0 0 + fpchg + sts fpscr, r0 + assertreg0 0x80000 + fpchg + sts fpscr, r0 + assertreg0 0 + fpchg + sts fpscr, r0 + assertreg0 0x80000 + fpchg + sts fpscr, r0 + assertreg0 0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + test_fprs_a5a5 + + pass + exit 0 diff --git a/sim/testsuite/sh/frchg.s b/sim/testsuite/sh/frchg.s new file mode 100644 index 00000000000..c5dc0992e5f --- /dev/null +++ b/sim/testsuite/sh/frchg.s @@ -0,0 +1,30 @@ +# sh testcase for frchg +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start + set_grs_a5a5 + set_fprs_a5a5 + sts fpscr, r0 + assertreg0 0 + frchg + sts fpscr, r0 + assertreg0 0x200000 + frchg + sts fpscr, r0 + assertreg0 0 + frchg + sts fpscr, r0 + assertreg0 0x200000 + frchg + sts fpscr, r0 + assertreg0 0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + test_fprs_a5a5 + + pass + exit 0 diff --git a/sim/testsuite/sh/fsca.s b/sim/testsuite/sh/fsca.s new file mode 100644 index 00000000000..90df6c97680 --- /dev/null +++ b/sim/testsuite/sh/fsca.s @@ -0,0 +1,97 @@ +# sh testcase for fsca +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fsca: + set_grs_a5a5 + set_fprs_a5a5 + # Start with angle zero + mov.l zero, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i 0, fr2 + assert_fpreg_i 1, fr3 + + mov.l plus_90, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i 1, fr2 + assert_fpreg_i 0, fr3 + + mov.l plus_180, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i 0, fr2 + assert_fpreg_i -1, fr3 + + mov.l plus_270, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i -1, fr2 + assert_fpreg_i 0, fr3 + + mov.l plus_360, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i 0, fr2 + assert_fpreg_i 1, fr3 + + mov.l minus_90, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i -1, fr2 + assert_fpreg_i 0, fr3 + + mov.l minus_180, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i 0, fr2 + assert_fpreg_i -1, fr3 + + mov.l minus_270, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i 1, fr2 + assert_fpreg_i 0, fr3 + + mov.l minus_360, r0 + lds r0, fpul + fsca fpul, dr2 + assert_fpreg_i 0, fr2 + assert_fpreg_i 1, fr3 + + assertreg0 0xffff0000 + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + test_fpr_a5a5 fr0 + test_fpr_a5a5 fr1 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + pass + exit 0 + + .align 2 +zero: .long 0 +one_bitty: .long 1 +plus_90: .long 0x04000 +plus_180: .long 0x08000 +plus_270: .long 0x0c000 +plus_360: .long 0x10000 +minus_90: .long 0xffffc000 +minus_180: .long 0xffff8000 +minus_270: .long 0xffff4000 +minus_360: .long 0xffff0000 +minus_1_bitty: .long 0xffffffff diff --git a/sim/testsuite/sh/fschg.s b/sim/testsuite/sh/fschg.s new file mode 100644 index 00000000000..7454787b1d6 --- /dev/null +++ b/sim/testsuite/sh/fschg.s @@ -0,0 +1,29 @@ +# sh testcase for fschg +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start + set_grs_a5a5 + set_fprs_a5a5 + sts fpscr, r0 + assertreg0 0 + fschg + sts fpscr, r0 + assertreg0 0x100000 + fschg + sts fpscr, r0 + assertreg0 0 + fschg + sts fpscr, r0 + assertreg0 0x100000 + fschg + sts fpscr, r0 + assertreg0 0 + + set_greg 0xa5a5a5a5 r0 + test_grs_a5a5 + test_fprs_a5a5 + pass + exit 0 diff --git a/sim/testsuite/sh/fsqrt.s b/sim/testsuite/sh/fsqrt.s new file mode 100644 index 00000000000..cb61bcf4085 --- /dev/null +++ b/sim/testsuite/sh/fsqrt.s @@ -0,0 +1,120 @@ +# sh testcase for fsqrt +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fsqrt_single: + set_grs_a5a5 + set_fprs_a5a5 + # sqrt(0.0) = 0.0. + fldi0 fr0 + fsqrt fr0 + fldi0 fr1 + fcmp/eq fr0, fr1 + bt .L0 + fail +.L0: + # sqrt(1.0) = 1.0. + fldi1 fr0 + fsqrt fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bt .L1 + fail +.L1: + # sqrt(4.0) = 2.0 + fldi1 fr0 + # Double it. + fadd fr0, fr0 + # Double it again. + fadd fr0, fr0 + fsqrt fr0 + fldi1 fr1 + # Double it. + fadd fr1, fr1 + fcmp/eq fr0, fr1 + bt .L2 + fail +.L2: + test_grs_a5a5 + assert_fpreg_i 2, fr0 + assert_fpreg_i 2, fr1 + test_fpr_a5a5 fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fsqrt_double: + double_prec + set_grs_a5a5 + set_fprs_a5a5 + # sqrt(0.0) = 0.0. + fldi0 fr0 + _s2d fr0, dr0 + fsqrt dr0 + fldi0 fr2 + _s2d fr2, dr2 + fcmp/eq dr0, dr2 + bt .L10 + fail +.L10: + # sqrt(1.0) = 1.0. + fldi1 fr0 + _s2d fr0, dr0 + fsqrt dr0 + fldi1 fr2 + _s2d fr2, dr2 + fcmp/eq dr0, dr2 + bt .L11 + fail +.L11: + # sqrt(4.0) = 2.0. + fldi1 fr0 + # Double it. + single_prec + fadd fr0, fr0 + # Double it again. + fadd fr0, fr0 + double_prec + _s2d fr0, dr0 + fsqrt dr0 + fldi1 fr2 + # Double it. + single_prec + fadd fr2, fr2 + double_prec + _s2d fr2, dr2 + fcmp/eq dr0, dr2 + bt .L12 + fail +.L12: + test_grs_a5a5 + assert_dpreg_i 2, dr0 + assert_dpreg_i 2, dr2 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + + pass + exit 0 diff --git a/sim/testsuite/sh/fsrra.s b/sim/testsuite/sh/fsrra.s new file mode 100644 index 00000000000..fdd22356d66 --- /dev/null +++ b/sim/testsuite/sh/fsrra.s @@ -0,0 +1,62 @@ +# sh testcase for fsrra +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fsrra_single: + set_grs_a5a5 + set_fprs_a5a5 + # 1/sqrt(0.0) = +infinity. + fldi0 fr0 + fsrra fr0 + assert_fpreg_x 0x7f800000, fr0 + + # 1/sqrt(1.0) = 1.0. + fldi1 fr0 + fsrra fr0 + assert_fpreg_i 1, fr0 + + # 1/sqrt(4.0) = 1/2.0 + fldi1 fr0 + # Double it. + fadd fr0, fr0 + # Double it again. + fadd fr0, fr0 + fsrra fr0 + fldi1 fr2 + # Double it. + fadd fr2, fr2 + fldi1 fr1 + # Divide + fdiv fr2, fr1 + fcmp/eq fr0, fr1 + bt .L2 + fail +.L2: + # Double-check (pun intended) + fadd fr0, fr0 + assert_fpreg_i 1, fr0 + fadd fr1, fr1 + assert_fpreg_i 1, fr1 + + # And make sure the rest of the regs are un-affected. + assert_fpreg_i 2, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + test_grs_a5a5 + + pass + exit 0 diff --git a/sim/testsuite/sh/fsub.s b/sim/testsuite/sh/fsub.s new file mode 100644 index 00000000000..dfe9172f57a --- /dev/null +++ b/sim/testsuite/sh/fsub.s @@ -0,0 +1,136 @@ +# sh testcase for fsub +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +fsub_single: + set_grs_a5a5 + set_fprs_a5a5 + # 0.0 - 0.0 = 0.0. + fldi0 fr0 + fldi0 fr1 + fsub fr0, fr1 + fldi0 fr2 + fcmp/eq fr1, fr2 + bt .L0 + fail +.L0: + # 1.0 - 0.0 = 1.0. + fldi0 fr0 + fldi1 fr1 + fsub fr0, fr1 + fldi1 fr2 + fcmp/eq fr1, fr2 + bt .L1 + fail +.L1: + # 1.0 - 1.0 = 0.0. + fldi1 fr0 + fldi1 fr1 + fsub fr0, fr1 + fldi0 fr2 + fcmp/eq fr1, fr2 + bt .L2 + fail +.L2: + # 0.0 - 1.0 = -1.0. + fldi1 fr0 + fldi0 fr1 + fsub fr0, fr1 + fldi1 fr2 + fneg fr2 + fcmp/eq fr1, fr2 + bt .L3 + fail +.L3: + test_grs_a5a5 + assert_fpreg_i 1, fr0 + assert_fpreg_i -1, fr1 + assert_fpreg_i -1, fr2 + test_fpr_a5a5 fr3 + test_fpr_a5a5 fr4 + test_fpr_a5a5 fr5 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + +fsub_double: + set_grs_a5a5 + set_fprs_a5a5 + double_prec + # 0.0 - 0.0 = 0.0. + fldi0 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fsub dr0, dr2 + fldi0 fr4 + _s2d fr4, dr4 + fcmp/eq dr2, dr4 + bt .L10 + fail +.L10: + # 1.0 - 0.0 = 1.0. + fldi0 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fsub dr0, dr2 + fldi1 fr4 + _s2d fr4, dr4 + fcmp/eq dr2, dr4 + bt .L11 + fail +.L11: + # 1.0 - 1.0 = 0.0. + fldi1 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fsub dr0, dr2 + fldi0 fr4 + _s2d fr4, dr4 + fcmp/eq dr2, dr4 + bt .L12 + fail +.L12: + # 0.0 - 1.0 = -1.0. + fldi1 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + fsub dr0, dr2 + fldi1 fr4 + single_prec + fneg fr4 + double_prec + _s2d fr4, dr4 + fcmp/eq dr2, dr4 + bt .L13 + fail +.L13: + test_grs_a5a5 + assert_dpreg_i 1, dr0 + assert_dpreg_i -1, dr2 + assert_dpreg_i -1, dr4 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + pass + exit 0 diff --git a/sim/testsuite/sh/ftrc.s b/sim/testsuite/sh/ftrc.s new file mode 100644 index 00000000000..25e33be33ad --- /dev/null +++ b/sim/testsuite/sh/ftrc.s @@ -0,0 +1,156 @@ +# sh testcase for ftrc +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start +ftrc_single: + set_grs_a5a5 + set_fprs_a5a5 + # ftrc(0.0) = 0. + fldi0 fr0 + ftrc fr0, fpul + # check results. + mov #0, r0 + sts fpul, r1 + cmp/eq r0, r1 + bt .L0 + fail +.L0: + # ftrc(1.5) = 1. + fldi1 fr0 + fldi1 fr1 + fldi1 fr2 + # double it. + fadd fr2, fr2 + # form the fraction. + fdiv fr2, fr1 + fadd fr1, fr0 + # now we've got 1.5 in fr0. + ftrc fr0, fpul + # check results. + mov #1, r0 + sts fpul, r1 + cmp/eq r0, r1 + bt .L1 + fail +.L1: + # ftrc(-1.5) = -1. + fldi1 fr0 + fneg fr0 + fldi1 fr1 + fldi1 fr2 + # double it. + fadd fr2, fr2 + # form the fraction. + fdiv fr2, fr1 + fneg fr1 + # -1 + -0.5 = -1.5. + fadd fr1, fr0 + # now we've got 1.5 in fr0. + ftrc fr0, fpul + # check results. + mov #1, r0 + neg r0, r0 + sts fpul, r1 + cmp/eq r0, r1 + bt ftrc_double + fail + +ftrc_double: + double_prec + # ftrc(0.0) = 0. + fldi0 fr0 + _s2d fr0, dr0 + ftrc dr0, fpul + # check results. + mov #0, r0 + sts fpul, r1 + cmp/eq r0, r1 + bt .L10 + fail +.L10: + # ftrc(1.5) = 1. + fldi1 fr0 + fldi1 fr2 + fldi1 fr4 + # double it. + single_prec + fadd fr4, fr4 + # form 0.5. + fdiv fr4, fr2 + fadd fr2, fr0 + double_prec + # now we've got 1.5 in fr0, so do some single->double + # conversions and perform the ftrc. + _s2d fr0, dr0 + _s2d fr2, dr2 + _s2d fr4, dr4 + ftrc dr0, fpul + + # check results. + mov #1, r0 + sts fpul, r1 + cmp/eq r0, r1 + bt .L11 + fail +.L11: + # ftrc(-1.5) = -1. + fldi1 fr0 + fneg fr0 + fldi1 fr2 + fldi1 fr4 + single_prec + # double it. + fadd fr4, fr4 + # form the fraction. + fdiv fr4, fr2 + fneg fr2 + # -1 + -0.5 = -1.5. + fadd fr2, fr0 + double_prec + # now we've got 1.5 in fr0, so do some single->double + # conversions and perform the ftrc. + _s2d fr0, dr0 + _s2d fr2, dr2 + _s2d fr4, dr4 + ftrc dr0, fpul + + # check results. + mov #1, r0 + neg r0, r0 + sts fpul, r1 + cmp/eq r0, r1 + bt .L12 + fail +.L12: + assertreg0 -1 + assertreg -1, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + assert_dpreg_i 2, dr4 + test_fpr_a5a5 fr6 + test_fpr_a5a5 fr7 + test_fpr_a5a5 fr8 + test_fpr_a5a5 fr9 + test_fpr_a5a5 fr10 + test_fpr_a5a5 fr11 + test_fpr_a5a5 fr12 + test_fpr_a5a5 fr13 + test_fpr_a5a5 fr14 + test_fpr_a5a5 fr15 + pass + exit 0 diff --git a/sim/testsuite/sh/ldrc.s b/sim/testsuite/sh/ldrc.s new file mode 100644 index 00000000000..444131302f4 --- /dev/null +++ b/sim/testsuite/sh/ldrc.s @@ -0,0 +1,118 @@ +# sh testcase for ldrc, strc +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +setrc_imm: + set_grs_a5a5 + # Test setrc + # + ldrs lstart + ldre lend + setrc #0xff + get_sr r1 + shlr16 r1 + set_greg 0xfff, r0 + and r0, r1 + assertreg 0xff, r1 + + stc rs, r0 ! rs unchanged + assertreg0 lstart + stc re, r0 ! re unchanged + assertreg0 lend + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + + test_grs_a5a5 + +setrc_reg: + set_grs_a5a5 + # Test setrc + # + ldrs lstart + ldre lend + set_greg 0xfff, r0 + setrc r0 + get_sr r1 + shlr16 r1 + set_greg 0xfff, r0 + and r0, r1 + assertreg 0xfff, r1 + + stc rs, r0 ! rs unchanged + assertreg0 lstart + stc re, r0 ! re unchanged + assertreg0 lend + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + + test_grs_a5a5 + + bra ldrc_imm + + .global lstart + .align 2 +lstart: nop + nop + nop + nop + .global lend + .align 2 +lend: nop + nop + nop + nop + +ldrc_imm: + set_grs_a5a5 + # Test ldrc + setrc #0x0 ! zero rc + ldrc #0xa5 + get_sr r1 + shlr16 r1 + set_greg 0xfff, r0 + and r0, r1 + assertreg 0xa5, r1 + stc rs, r0 ! rs unchanged + assertreg0 lstart + stc re, r0 + assertreg0 lend+1 ! bit 0 set in re + + # fix up re for next test + dt r0 ! Ugh! No DEC insn! + ldc r0, re + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + + test_grs_a5a5 + +ldrc_reg: + set_grs_a5a5 + # Test ldrc + setrc #0x0 ! zero rc + set_greg 0xa5a, r0 + ldrc r0 + get_sr r1 + shlr16 r1 + set_greg 0xfff, r0 + and r0, r1 + assertreg 0xa5a, r1 + stc rs, r0 ! rs unchanged + assertreg0 lstart + stc re, r0 + assertreg0 lend+1 ! bit 0 set in re + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + + test_grs_a5a5 + + pass + exit 0 + diff --git a/sim/testsuite/sh/loop.s b/sim/testsuite/sh/loop.s new file mode 100644 index 00000000000..604051938e7 --- /dev/null +++ b/sim/testsuite/sh/loop.s @@ -0,0 +1,311 @@ +# sh testcase for loop control +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start +loop1: + set_grs_a5a5 + + ldrs Loop1_start0+8 + ldre Loop1_start0+4 + setrc #5 +Loop1_start0: + add #1, r1 ! Before loop + # Loop should execute one instruction five times. +Loop1_begin: + add #1, r1 ! Within loop +Loop1_end: + add #2, r1 ! After loop + + # r1 = 0xa5a5a5a5 + 8 (five in loop, two after, one before) + assertreg 0xa5a5a5a5+8, r1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + +loop2: + set_grs_a5a5 + + ldrs Loop2_start0+6 + ldre Loop2_start0+4 + setrc #5 +Loop2_start0: + add #1, r1 ! Before loop + # Loop should execute two instructions five times. +Loop2_begin: + add #1, r1 ! Within loop + add #1, r1 ! Within loop +Loop2_end: + add #3, r1 ! After loop + + # r1 = 0xa5a5a5a5 + 14 (ten in loop, three after, one before) + assertreg 0xa5a5a5a5+14, r1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + +loop3: + set_grs_a5a5 + + ldrs Loop3_start0+4 + ldre Loop3_start0+4 + setrc #5 +Loop3_start0: + add #1, r1 ! Before loop + # Loop should execute three instructions five times. +Loop3_begin: + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop +Loop3_end: + add #2, r1 ! After loop + + # r1 = 0xa5a5a5a5 + 18 (fifteen in loop, two after, one before) + assertreg 0xa5a5a5a5+18, r1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + +loop4: + set_grs_a5a5 + + ldrs Loop4_begin + ldre Loop4_last3+4 + setrc #5 + add #1, r1 ! Before loop + # Loop should execute four instructions five times. +Loop4_begin: +Loop4_last3: + add #1, r1 ! Within loop +Loop4_last2: + add #1, r1 ! Within loop +Loop4_last1: + add #1, r1 ! Within loop +Loop4_last: + add #1, r1 ! Within loop +Loop4_end: + add #2, r1 ! After loop + + # r1 = 0xa5a5a5a5 + 23 (20 in loop, two after, one before) + assertreg 0xa5a5a5a5+23, r1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + +loop5: + set_grs_a5a5 + + ldrs Loop5_begin + ldre Loop5_last3+4 + setrc #5 + add #1, r1 ! Before loop + # Loop should execute five instructions five times. +Loop5_begin: + add #1, r1 ! Within loop +Loop5_last3: + add #1, r1 ! Within loop +Loop5_last2: + add #1, r1 ! Within loop +Loop5_last1: + add #1, r1 ! Within loop +Loop5_last: + add #1, r1 ! Within loop +Loop5_end: + add #2, r1 ! After loop + + # r1 = 0xa5a5a5a5 + 28 (25 in loop, two after, one before) + assertreg 0xa5a5a5a5+28, r1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + +loopn: + set_grs_a5a5 + + ldrs Loopn_begin + ldre Loopn_last3+4 + setrc #5 + add #1, r1 ! Before loop + # Loop should execute n instructions five times. +Loopn_begin: + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop +Loopn_last3: + add #1, r1 ! Within loop +Loopn_last2: + add #1, r1 ! Within loop +Loopn_last1: + add #1, r1 ! Within loop +Loopn_last: + add #1, r1 ! Within loop +Loopn_end: + add #3, r1 ! After loop + + # r1 = 0xa5a5a5a5 + 64 (60 in loop, three after, one before) + assertreg 0xa5a5a5a5+64, r1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + +loop1e: + set_grs_a5a5 + + ldrs Loop1e_begin + ldre Loop1e_last + ldrc #5 + add #1, r1 ! Before loop + # Loop should execute one instruction five times. +Loop1e_begin: +Loop1e_last: + add #1, r1 ! Within loop +Loop1e_end: + add #2, r1 ! After loop + + # r1 = 0xa5a5a5a5 + 8 (five in loop, two after, one before) + assertreg 0xa5a5a5a5+8, r1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + +loop2e: + set_grs_a5a5 + + ldrs Loop2e_begin + ldre Loop2e_last + ldrc #5 + add #1, r1 ! Before loop + # Loop should execute two instructions five times. +Loop2e_begin: + add #1, r1 ! Within loop +Loop2e_last: + add #1, r1 ! Within loop +Loop2e_end: + add #2, r1 ! After loop + + # r1 = 0xa5a5a5a5 + 13 (ten in loop, two after, one before) + assertreg 0xa5a5a5a5+13, r1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + +loop3e: + set_grs_a5a5 + + ldrs Loop3e_begin + ldre Loop3e_last + ldrc #5 + add #1, r1 ! Before loop + # Loop should execute three instructions five times. +Loop3e_begin: + add #1, r1 ! Within loop + add #1, r1 ! Within loop +Loop3e_last: + add #1, r1 ! Within loop +Loop3e_end: + add #2, r1 ! After loop + + # r1 = 0xa5a5a5a5 + 18 (fifteen in loop, two after, one before) + assertreg 0xa5a5a5a5+18, r1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + +loop4e: + set_grs_a5a5 + + ldrs Loop4e_begin + ldre Loop4e_last + ldrc #5 + add #1, r1 ! Before loop + # Loop should execute four instructions five times. +Loop4e_begin: + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop +Loop4e_last: + add #1, r1 ! Within loop +Loop4e_end: + add #2, r1 ! After loop + + # r1 = 0xa5a5a5a5 + 23 (twenty in loop, two after, one before) + assertreg 0xa5a5a5a5+23, r1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + +loop5e: + set_grs_a5a5 + + ldrs Loop5e_begin + ldre Loop5e_last + ldrc #5 + add #1, r1 ! Before loop + # Loop should execute five instructions five times. +Loop5e_begin: + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop +Loop5e_last: + add #1, r1 ! Within loop +Loop5e_end: + add #2, r1 ! After loop + + # r1 = 0xa5a5a5a5 + 28 (twenty five in loop, two after, one before) + assertreg 0xa5a5a5a5+28, r1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + +loop_n_e: + set_grs_a5a5 + + ldrs Loop_n_e_begin + ldre Loop_n_e_last + ldrc #5 + add #1, r1 ! Before loop + # Loop should execute n instructions five times. +Loop_n_e_begin: + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop + add #1, r1 ! Within loop +Loop_n_e_last: + add #1, r1 ! Within loop +Loop_n_e_end: + add #2, r1 ! After loop + + # r1 = 0xa5a5a5a5 + 48 (forty five in loop, two after, one before) + assertreg 0xa5a5a5a5+48, r1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + + pass + + exit 0 + diff --git a/sim/testsuite/sh/macl.s b/sim/testsuite/sh/macl.s new file mode 100644 index 00000000000..39b3b7d604b --- /dev/null +++ b/sim/testsuite/sh/macl.s @@ -0,0 +1,54 @@ +# sh testcase for mac.l +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + # force S-bit clear + clrs + +init: + # Prime {MACL, MACH} to #1. + mov #1, r0 + dmulu.l r0, r0 + + # Set up addresses. + mov.l pfour00, r0 ! 85 + mov.l pfour12, r1 ! 17 + +test: + mac.l @r0+, @r1+ + +check: + # Check result. + assert_sreg 0, mach + assert_sreg 85*17+1, macl + + # Ensure post-increment occurred. + assertreg0 four00+4 + assertreg four12+4, r1 + +doubleinc: + mov.l pfour00, r0 + mac.l @r0+, @r0+ + assertreg0 four00+8 + + + pass + exit 0 + + .align 1 +four00: + .long 85 + .long 2 +four12: + .long 17 + .long 3 + + .align 2 +pfour00: + .long four00 +pfour12: + .long four12 diff --git a/sim/testsuite/sh/macw.s b/sim/testsuite/sh/macw.s new file mode 100644 index 00000000000..7e3ebc07d7b --- /dev/null +++ b/sim/testsuite/sh/macw.s @@ -0,0 +1,56 @@ +# sh testcase for mac.w +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + + # Prime {MACL, MACH} to #1. + mov #1, r0 + dmulu.l r0, r0 + + # Set up addresses. + mov.l pfour00, r0 ! 85 + mov.l pfour12, r1 ! 17 + +test: + mac.w @r0+, @r1+ ! MAC = 85 * 17 + 1 + +check: + # Check result. + assert_sreg 0, mach + assert_sreg 85*17+1, macl + + # Ensure post-increment occurred. + assertreg0 four00+2 + assertreg four12+2, r1 + +doubleinc: + mov.l pfour00, r0 + mac.w @r0+, @r0+ + assertreg0 four00+4 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + + test_grs_a5a5 + + pass + exit 0 + + .align 2 +four00: + .word 85 + .word 2 +four12: + .word 17 + .word 3 + + +pfour00: + .long four00 +pfour12: + .long four12 diff --git a/sim/testsuite/sh/mov.s b/sim/testsuite/sh/mov.s new file mode 100644 index 00000000000..37fef514401 --- /dev/null +++ b/sim/testsuite/sh/mov.s @@ -0,0 +1,118 @@ +# sh testcase for all mov.[bwl] instructions +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + .align 2 +_lsrc: .long 0x55555555 +_wsrc: .long 0x55550000 +_bsrc: .long 0x55000000 + + .align 2 +_ldst: .long 0 +_wdst: .long 0 +_bdst: .long 0 + + + start + +movb_disp12_reg: # Test 8-bit @(disp12,gr) -> gr + set_grs_a5a5 + mov.l bsrc, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + mov.b @(444,r1), r2 + + assertreg _bsrc-444, r1 + assertreg 0x55, r2 + +movb_reg_disp12: # Test 8-bit gr -> @(disp12,gr) + set_grs_a5a5 + mov.l bdst, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + mov.b r2, @(444,r1) + + assertreg _bdst-444, r1 + assertmem _bdst, 0xa5000000 + +movw_disp12_reg: # Test 16-bit @(disp12,gr) -> gr + set_grs_a5a5 + mov.l wsrc, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + mov.w @(444,r1), r2 + + assertreg _wsrc-444, r1 + assertreg 0x5555, r2 + +movw_reg_disp12: # Test 16-bit gr -> @(disp12,gr) + set_grs_a5a5 + mov.l wdst, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + mov.w r2, @(444,r1) + + assertreg _wdst-444, r1 + assertmem _wdst, 0xa5a50000 + +movl_disp12_reg: # Test 32-bit @(disp12,gr) -> gr + set_grs_a5a5 + mov.l lsrc, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + mov.l @(444,r1), r2 + + assertreg _lsrc-444, r1 + assertreg 0x55555555, r2 + +movl_reg_disp12: # Test 32-bit gr -> @(disp12,gr) + set_grs_a5a5 + mov.l ldst, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + add #-111, r1 + mov.l r2, @(444,r1) + + assertreg _ldst-444, r1 + assertmem _ldst, 0xa5a5a5a5 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + +lsrc: .long _lsrc +wsrc: .long _wsrc +bsrc: .long _bsrc + +ldst: .long _ldst +wdst: .long _wdst +bdst: .long _bdst + diff --git a/sim/testsuite/sh/movi.s b/sim/testsuite/sh/movi.s new file mode 100644 index 00000000000..e54f4f6597a --- /dev/null +++ b/sim/testsuite/sh/movi.s @@ -0,0 +1,76 @@ +# sh testcase for all mov <#imm> instructions +# mach: sh +# as(sh): -defsym sim_cpu=0 + + .include "testutils.inc" + + start + +mov_i_reg: # Test <imm8> + set_grs_a5a5 + mov #-0x55, r1 + + assertreg 0xffffffab, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +movi20_reg: # Test <imm20> + set_grs_a5a5 + movi20 #-0x55555,r1 + + assertreg 0xfffaaaab, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +movi20s_reg: # Test <imm20> << 8 + set_grs_a5a5 + movi20s #-0x5555500,r1 + + assertreg 0xfaaaab00, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + diff --git a/sim/testsuite/sh/movli.s b/sim/testsuite/sh/movli.s new file mode 100644 index 00000000000..eacd10358ba --- /dev/null +++ b/sim/testsuite/sh/movli.s @@ -0,0 +1,55 @@ +# sh testcase for movli +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +x: .long 1 +y: .long 2 +z: .long 3 + + start + set_grs_a5a5 + mov.l xptr, r1 + mov.l yptr, r2 + # Move linked/conditional, x to y + movli.l @r1, r0 + movco.l r0, @r2 + + # Check result. + assertreg0 1 + mov.l yptr, r1 + mov.l @r1, r2 + assertreg 1, r2 + + # Now attempt an unlinked move of r0 to z + mov.l zptr, r1 + movco.l r0, @r1 + + # Check that z is unchanged. + mov.l zptr, r1 + mov.l @r1, r2 + assertreg 3, r2 + + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + exit 0 + + .align 2 +xptr: .long x +yptr: .long y +zptr: .long z diff --git a/sim/testsuite/sh/movua.s b/sim/testsuite/sh/movua.s new file mode 100644 index 00000000000..fa12fe53f8c --- /dev/null +++ b/sim/testsuite/sh/movua.s @@ -0,0 +1,197 @@ +# sh testcase for movua +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start +movua_1: + set_grs_a5a5 + mov.l srcp, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x03020100 +.else + assertreg0 0x00010203 +.endif + + add #1, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x04030201 +.else + assertreg0 0x01020304 +.endif + + add #1, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x05040302 +.else + assertreg0 0x02030405 +.endif + + add #1, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x06050403 +.else + assertreg0 0x03040506 +.endif + + add #1, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x07060504 +.else + assertreg0 0x04050607 +.endif + + add #1, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x08070605 +.else + assertreg0 0x05060708 +.endif + + add #1, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x09080706 +.else + assertreg0 0x06070809 +.endif + + add #1, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x0a090807 +.else + assertreg0 0x0708090a +.endif + + add #1, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x0b0a0908 +.else + assertreg0 0x08090a0b +.endif + + add #1, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x0c0b0a09 +.else + assertreg0 0x090a0b0c +.endif + + add #1, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x0d0c0b0a +.else + assertreg0 0x0a0b0c0d +.endif + + add #1, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x0e0d0c0b +.else + assertreg0 0x0b0c0d0e +.endif + + add #1, r1 + movua.l @r1, r0 +.ifdef LITTLE + assertreg0 0x0f0e0d0c +.else + assertreg0 0x0c0d0e0f +.endif + + assertreg src+12, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + bra movua_4: + nop + + .align 0 +src: .byte 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 + .align 2 +srcp: .long src + +movua_4: + set_grs_a5a5 + mov.l srcp2, r1 + movua.l @r1+, r0 +.ifdef LITTLE + assertreg0 0x03020100 +.else + assertreg0 0x00010203 +.endif + assertreg src+4, r1 + + mov.l srcp2, r1 + add #1, r1 + movua.l @r1+, r0 +.ifdef LITTLE + assertreg0 0x04030201 +.else + assertreg0 0x01020304 +.endif + assertreg src+5, r1 + + mov.l srcp2, r1 + add #2, r1 + movua.l @r1+, r0 +.ifdef LITTLE + assertreg0 0x05040302 +.else + assertreg0 0x02030405 +.endif + assertreg src+6, r1 + + mov.l srcp2, r1 + add #3, r1 + movua.l @r1+, r0 +.ifdef LITTLE + assertreg0 0x06050403 +.else + assertreg0 0x03040506 +.endif + assertreg src+7, r1 + + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + exit 0 + +srcp2: .long src + diff --git a/sim/testsuite/sh/movxy.s b/sim/testsuite/sh/movxy.s new file mode 100644 index 00000000000..7768ef96d50 --- /dev/null +++ b/sim/testsuite/sh/movxy.s @@ -0,0 +1,1186 @@ +# sh testcase for movxy +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +src1: .word 1 +src2: .word 2 +src3: .word 3 +src4: .word 4 +src5: .word 5 +src6: .word 6 +src7: .word 7 +src8: .word 8 +src9: .word 9 + .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + +dst1: .word 0 +dst2: .word 0 +dst3: .word 0 +dst4: .word 0 +dst5: .word 0 +dst6: .word 0 +dst7: .word 0 +dst8: .word 0 +dst9: .word 0 + .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + + start +movxw_nopy: + set_grs_a5a5 + # load up pointers + mov.l srcp1, r4 + mov.l dstp1, r5 + + # perform moves + movx.w @r4, x0 + pcopy x0, a0 + movx.w a0, @r5 + + # verify pointers unchanged + mov.l srcp1, r0 + cmp/eq r0, r4 + bt .L0 + fail +.L0: + mov.l dstp1, r1 + cmp/eq r1, r5 + bt .L1 + fail +.L1: + # verify copied values + mov.w @r0, r0 + mov.w @r1, r1 + cmp/eq r0, r1 + bt .L2 + fail +.L2: + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +movyw_nopx: + set_grs_a5a5 + # load up pointers + mov.l srcp2, r6 + mov.l dstp2, r7 + + # perform moves + movy.w @r6, y0 + pcopy y0, a0 + movy.w a0, @r7 + + # verify pointers unchanged + mov.l srcp2, r2 + cmp/eq r2, r6 + bt .L3 + fail +.L3: + mov.l dstp2, r3 + cmp/eq r3, r7 + bt .L4 + fail +.L4: + # verify copied values + mov.w @r2, r2 + mov.w @r3, r3 + cmp/eq r2, r3 + bt .L5 + fail +.L5: + test_gr_a5a5 r0 + test_gr_a5a5 r1 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +movxw_movyw: + set_grs_a5a5 + # load up pointers + mov.l srcp3, r4 + mov.l dstp3, r5 + mov.l srcp4, r6 + mov.l dstp4, r7 + + # perform moves + movx.w @r4, x1 movy.w @r6, y1 + pcopy x1, a0 + pcopy y1, a1 + movx.w a0, @r5 movy.w a1, @r7 + + # verify pointers unchanged + mov.l srcp3, r0 + cmp/eq r0, r4 + bt .L6 + fail +.L6: + mov.l dstp3, r1 + cmp/eq r1, r5 + bt .L7 + fail +.L7: + mov.l srcp4, r2 + cmp/eq r2, r6 + bt .L8 + fail +.L8: + mov.l dstp4, r3 + cmp/eq r3, r7 + bt .L9 + fail +.L9: + # verify copied values + mov.w @r0, r0 + mov.w @r1, r1 + cmp/eq r0, r1 + bt .L10 + fail +.L10: + mov.w @r2, r2 + mov.w @r3, r3 + cmp/eq r2, r3 + bt .L11 + fail +.L11: + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + bra movxw_movyw_new + nop + + .align 2 +srcp1: .long src1 +srcp2: .long src2 +srcp3: .long src3 +srcp4: .long src4 +srcp5: .long src5 +srcp6: .long src6 +srcp7: .long src7 +srcp8: .long src8 +srcp9: .long src9 + +dstp1: .long dst1 +dstp2: .long dst2 +dstp3: .long dst3 +dstp4: .long dst4 +dstp5: .long dst5 +dstp6: .long dst6 +dstp7: .long dst7 +dstp8: .long dst8 +dstp9: .long dst9 + +movxw_movyw_new: + set_grs_a5a5 + # load up pointers + mov.l srcp5b, r0 + mov.l dstp5b, r1 + mov.l srcp6b, r2 + mov.l dstp6b, r3 + + # perform moves + movx.w @r0, x1 + movy.w @r2, y1 + movx.w x1, @r1 + movy.w y1, @r3 + + # verify pointers unchanged + mov.l srcp5b, r4 + cmp/eq r0, r4 + bt .L12 + fail + +.L12: + mov.l dstp5b, r5 + cmp/eq r1, r5 + bt .L13 + fail +.L13: + mov.l srcp6b, r6 + cmp/eq r2, r6 + bt .L14 + fail +.L14: + mov.l dstp6b, r7 + cmp/eq r3, r7 + bt .L15 + fail +.L15: + # verify copied values + mov.w @r0, r0 + mov.w @r1, r1 + cmp/eq r0, r1 + bt .L16 + fail +.L16: + mov.w @r2, r2 + mov.w @r3, r3 + cmp/eq r2, r3 + bt .L17 + fail +.L17: + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + mov.l srcp1b, r0 + mov.l dstp1b, r1 + mov.l srcp2b, r2 + mov.l dstp2b, r3 + mov.l srcp1b, r4 + mov.l dstp1b, r5 + mov.l srcp2b, r6 + mov.l dstp2b, r7 + mov #4, r8 + mov #4, r9 + bra .L18 + nop + + .align 2 +srcp1b: .long src1 +srcp2b: .long src2 +srcp3b: .long src3 +srcp4b: .long src4 +srcp5b: .long src5 +srcp6b: .long src6 +srcp7b: .long src7 +srcp8b: .long src8 +srcp9b: .long src9 + +dstp1b: .long dst1 +dstp2b: .long dst2 +dstp3b: .long dst3 +dstp4b: .long dst4 +dstp5b: .long dst5 +dstp6b: .long dst6 +dstp7b: .long dst7 +dstp8b: .long dst8 +dstp9b: .long dst9 + +.L18: + + # movx.w @Ax{}, Dx | nopy +movxwaxdx_nopy: + movx.w @r4,x0 ! .word 0xf004 + movx.w @r4,x1 ! .word 0xf084 + movx.w @r5,x0 ! .word 0xf204 + movx.w @r5,x1 ! .word 0xf284 + movx.w @r4+,x0 ! .word 0xf008 + movx.w @r4+,x1 ! .word 0xf088 + movx.w @r5+,x0 ! .word 0xf208 + movx.w @r5+,x1 ! .word 0xf288 + movx.w @r4+r8,x0 ! .word 0xf00c + movx.w @r4+r8,x1 ! .word 0xf08c + movx.w @r5+r8,x0 ! .word 0xf20c + movx.w @r5+r8,x1 ! .word 0xf28c + # movx.w Da, @Ax{} | nopy +movxwdaax_nopy: + movx.w a0,@r4 ! .word 0xf024 + movx.w a1,@r4 ! .word 0xf0a4 + movx.w a0,@r5 ! .word 0xf224 + movx.w a1,@r5 ! .word 0xf2a4 + movx.w a0,@r4+ ! .word 0xf028 + movx.w a1,@r4+ ! .word 0xf0a8 + movx.w a0,@r5+ ! .word 0xf228 + movx.w a1,@r5+ ! .word 0xf2a8 + movx.w a0,@r4+r8 ! .word 0xf02c + movx.w a1,@r4+r8 ! .word 0xf0ac + movx.w a0,@r5+r8 ! .word 0xf22c + movx.w a1,@r5+r8 ! .word 0xf2ac + # movy.w @Ay{}, Dy | nopx +movywaydy_nopx: + movy.w @r6,y0 ! .word 0xf001 + movy.w @r6,y1 ! .word 0xf041 + movy.w @r7,y0 ! .word 0xf101 + movy.w @r7,y1 ! .word 0xf141 + movy.w @r6+,y0 ! .word 0xf002 + movy.w @r6+,y1 ! .word 0xf042 + movy.w @r7+,y0 ! .word 0xf102 + movy.w @r7+,y1 ! .word 0xf142 + movy.w @r6+r9,y0 ! .word 0xf003 + movy.w @r6+r9,y1 ! .word 0xf043 + movy.w @r7+r9,y0 ! .word 0xf103 + movy.w @r7+r9,y1 ! .word 0xf143 + # movy.w Da, @Ay{} | nopx +movywdaay_nopx: + movy.w a0,@r6 ! .word 0xf011 + movy.w a1,@r6 ! .word 0xf051 + movy.w a0,@r7 ! .word 0xf111 + movy.w a1,@r7 ! .word 0xf151 + movy.w a0,@r6+ ! .word 0xf012 + movy.w a1,@r6+ ! .word 0xf052 + movy.w a0,@r7+ ! .word 0xf112 + movy.w a1,@r7+ ! .word 0xf152 + movy.w a0,@r6+r9 ! .word 0xf013 + movy.w a1,@r6+r9 ! .word 0xf053 + movy.w a0,@r7+r9 ! .word 0xf113 + movy.w a1,@r7+r9 ! .word 0xf153 + # movx {} || movy {} +movx_movy: + movx.w @r4,x0 movy.w @r6,y0 ! .word 0xf005 + movx.w @r4,x0 movy.w @r6,y1 ! .word 0xf045 + movx.w @r4,x1 movy.w @r6,y0 ! .word 0xf085 + movx.w @r4,x1 movy.w @r6,y1 ! .word 0xf0c5 + movx.w @r4,x0 movy.w @r7,y0 ! .word 0xf105 + movx.w @r4,x0 movy.w @r7,y1 ! .word 0xf145 + movx.w @r4,x1 movy.w @r7,y0 ! .word 0xf185 + movx.w @r4,x1 movy.w @r7,y1 ! .word 0xf1c5 + movx.w @r5,x0 movy.w @r6,y0 ! .word 0xf205 + movx.w @r5,x0 movy.w @r6,y1 ! .word 0xf245 + movx.w @r5,x1 movy.w @r6,y0 ! .word 0xf285 + movx.w @r5,x1 movy.w @r6,y1 ! .word 0xf2c5 + movx.w @r5,x0 movy.w @r7,y0 ! .word 0xf305 + movx.w @r5,x0 movy.w @r7,y1 ! .word 0xf345 + movx.w @r5,x1 movy.w @r7,y0 ! .word 0xf385 + movx.w @r5,x1 movy.w @r7,y1 ! .word 0xf3c5 + movx.w @r4,x0 movy.w @r6+,y0 ! .word 0xf006 + movx.w @r4,x0 movy.w @r6+,y1 ! .word 0xf046 + movx.w @r4,x1 movy.w @r6+,y0 ! .word 0xf086 + movx.w @r4,x1 movy.w @r6+,y1 ! .word 0xf0c6 + movx.w @r4,x0 movy.w @r7+,y0 ! .word 0xf106 + movx.w @r4,x0 movy.w @r7+,y1 ! .word 0xf146 + movx.w @r4,x1 movy.w @r7+,y0 ! .word 0xf186 + movx.w @r4,x1 movy.w @r7+,y1 ! .word 0xf1c6 + movx.w @r5,x0 movy.w @r6+,y0 ! .word 0xf206 + movx.w @r5,x0 movy.w @r6+,y1 ! .word 0xf246 + movx.w @r5,x1 movy.w @r6+,y0 ! .word 0xf286 + movx.w @r5,x1 movy.w @r6+,y1 ! .word 0xf2c6 + movx.w @r5,x0 movy.w @r7+,y0 ! .word 0xf306 + movx.w @r5,x0 movy.w @r7+,y1 ! .word 0xf346 + movx.w @r5,x1 movy.w @r7+,y0 ! .word 0xf386 + movx.w @r5,x1 movy.w @r7+,y1 ! .word 0xf3c6 + movx.w @r4,x0 movy.w @r6+r9,y0 ! .word 0xf007 + movx.w @r4,x0 movy.w @r6+r9,y1 ! .word 0xf047 + movx.w @r4,x1 movy.w @r6+r9,y0 ! .word 0xf087 + movx.w @r4,x1 movy.w @r6+r9,y1 ! .word 0xf0c7 + movx.w @r4,x0 movy.w @r7+r9,y0 ! .word 0xf107 + movx.w @r4,x0 movy.w @r7+r9,y1 ! .word 0xf147 + movx.w @r4,x1 movy.w @r7+r9,y0 ! .word 0xf187 + movx.w @r4,x1 movy.w @r7+r9,y1 ! .word 0xf1c7 + movx.w @r5,x0 movy.w @r6+r9,y0 ! .word 0xf207 + movx.w @r5,x0 movy.w @r6+r9,y1 ! .word 0xf247 + movx.w @r5,x1 movy.w @r6+r9,y0 ! .word 0xf287 + movx.w @r5,x1 movy.w @r6+r9,y1 ! .word 0xf2c7 + movx.w @r5,x0 movy.w @r7+r9,y0 ! .word 0xf307 + movx.w @r5,x0 movy.w @r7+r9,y1 ! .word 0xf347 + movx.w @r5,x1 movy.w @r7+r9,y0 ! .word 0xf387 + movx.w @r5,x1 movy.w @r7+r9,y1 ! .word 0xf3c7 + movx.w @r4+,x0 movy.w @r6,y0 ! .word 0xf009 + movx.w @r4+,x0 movy.w @r6,y1 ! .word 0xf049 + movx.w @r4+,x1 movy.w @r6,y0 ! .word 0xf089 + movx.w @r4+,x1 movy.w @r6,y1 ! .word 0xf0c9 + movx.w @r4+,x0 movy.w @r7,y0 ! .word 0xf109 + movx.w @r4+,x0 movy.w @r7,y1 ! .word 0xf149 + movx.w @r4+,x1 movy.w @r7,y0 ! .word 0xf189 + movx.w @r4+,x1 movy.w @r7,y1 ! .word 0xf1c9 + movx.w @r5+,x0 movy.w @r6,y0 ! .word 0xf209 + movx.w @r5+,x0 movy.w @r6,y1 ! .word 0xf249 + movx.w @r5+,x1 movy.w @r6,y0 ! .word 0xf289 + movx.w @r5+,x1 movy.w @r6,y1 ! .word 0xf2c9 + movx.w @r5+,x0 movy.w @r7,y0 ! .word 0xf309 + movx.w @r5+,x0 movy.w @r7,y1 ! .word 0xf349 + movx.w @r5+,x1 movy.w @r7,y0 ! .word 0xf389 + movx.w @r5+,x1 movy.w @r7,y1 ! .word 0xf3c9 + movx.w @r4+,x0 movy.w @r6+,y0 ! .word 0xf00a + movx.w @r4+,x0 movy.w @r6+,y1 ! .word 0xf04a + movx.w @r4+,x1 movy.w @r6+,y0 ! .word 0xf08a + movx.w @r4+,x1 movy.w @r6+,y1 ! .word 0xf0ca + movx.w @r4+,x0 movy.w @r7+,y0 ! .word 0xf10a + movx.w @r4+,x0 movy.w @r7+,y1 ! .word 0xf14a + movx.w @r4+,x1 movy.w @r7+,y0 ! .word 0xf18a + movx.w @r4+,x1 movy.w @r7+,y1 ! .word 0xf1ca + movx.w @r5+,x0 movy.w @r6+,y0 ! .word 0xf20a + movx.w @r5+,x0 movy.w @r6+,y1 ! .word 0xf24a + movx.w @r5+,x1 movy.w @r6+,y0 ! .word 0xf28a + movx.w @r5+,x1 movy.w @r6+,y1 ! .word 0xf2ca + movx.w @r5+,x0 movy.w @r7+,y0 ! .word 0xf30a + movx.w @r5+,x0 movy.w @r7+,y1 ! .word 0xf34a + movx.w @r5+,x1 movy.w @r7+,y0 ! .word 0xf38a + movx.w @r5+,x1 movy.w @r7+,y1 ! .word 0xf3ca + movx.w @r4+,x0 movy.w @r6+r9,y0 ! .word 0xf00b + movx.w @r4+,x0 movy.w @r6+r9,y1 ! .word 0xf04b + movx.w @r4+,x1 movy.w @r6+r9,y0 ! .word 0xf08b + movx.w @r4+,x1 movy.w @r6+r9,y1 ! .word 0xf0cb + movx.w @r4+,x0 movy.w @r7+r9,y0 ! .word 0xf10b + movx.w @r4+,x0 movy.w @r7+r9,y1 ! .word 0xf14b + movx.w @r4+,x1 movy.w @r7+r9,y0 ! .word 0xf18b + movx.w @r4+,x1 movy.w @r7+r9,y1 ! .word 0xf1cb + movx.w @r5+,x0 movy.w @r6+r9,y0 ! .word 0xf20b + movx.w @r5+,x0 movy.w @r6+r9,y1 ! .word 0xf24b + movx.w @r5+,x1 movy.w @r6+r9,y0 ! .word 0xf28b + movx.w @r5+,x1 movy.w @r6+r9,y1 ! .word 0xf2cb + movx.w @r5+,x0 movy.w @r7+r9,y0 ! .word 0xf30b + movx.w @r5+,x0 movy.w @r7+r9,y1 ! .word 0xf34b + movx.w @r5+,x1 movy.w @r7+r9,y0 ! .word 0xf38b + movx.w @r5+,x1 movy.w @r7+r9,y1 ! .word 0xf3cb + movx.w @r4+r8,x0 movy.w @r6,y0 ! .word 0xf00d + movx.w @r4+r8,x0 movy.w @r6,y1 ! .word 0xf04d + movx.w @r4+r8,x1 movy.w @r6,y0 ! .word 0xf08d + movx.w @r4+r8,x1 movy.w @r6,y1 ! .word 0xf0cd + movx.w @r4+r8,x0 movy.w @r7,y0 ! .word 0xf10d + movx.w @r4+r8,x0 movy.w @r7,y1 ! .word 0xf14d + movx.w @r4+r8,x1 movy.w @r7,y0 ! .word 0xf18d + movx.w @r4+r8,x1 movy.w @r7,y1 ! .word 0xf1cd + movx.w @r5+r8,x0 movy.w @r6,y0 ! .word 0xf20d + movx.w @r5+r8,x0 movy.w @r6,y1 ! .word 0xf24d + movx.w @r5+r8,x1 movy.w @r6,y0 ! .word 0xf28d + movx.w @r5+r8,x1 movy.w @r6,y1 ! .word 0xf2cd + movx.w @r5+r8,x0 movy.w @r7,y0 ! .word 0xf30d + movx.w @r5+r8,x0 movy.w @r7,y1 ! .word 0xf34d + movx.w @r5+r8,x1 movy.w @r7,y0 ! .word 0xf38d + movx.w @r5+r8,x1 movy.w @r7,y1 ! .word 0xf3cd + movx.w @r4+r8,x0 movy.w @r6+,y0 ! .word 0xf00e + movx.w @r4+r8,x0 movy.w @r6+,y1 ! .word 0xf04e + movx.w @r4+r8,x1 movy.w @r6+,y0 ! .word 0xf08e + movx.w @r4+r8,x1 movy.w @r6+,y1 ! .word 0xf0ce + movx.w @r4+r8,x0 movy.w @r7+,y0 ! .word 0xf10e + movx.w @r4+r8,x0 movy.w @r7+,y1 ! .word 0xf14e + movx.w @r4+r8,x1 movy.w @r7+,y0 ! .word 0xf18e + movx.w @r4+r8,x1 movy.w @r7+,y1 ! .word 0xf1ce + movx.w @r5+r8,x0 movy.w @r6+,y0 ! .word 0xf20e + movx.w @r5+r8,x0 movy.w @r6+,y1 ! .word 0xf24e + movx.w @r5+r8,x1 movy.w @r6+,y0 ! .word 0xf28e + movx.w @r5+r8,x1 movy.w @r6+,y1 ! .word 0xf2ce + movx.w @r5+r8,x0 movy.w @r7+,y0 ! .word 0xf30e + movx.w @r5+r8,x0 movy.w @r7+,y1 ! .word 0xf34e + movx.w @r5+r8,x1 movy.w @r7+,y0 ! .word 0xf38e + movx.w @r5+r8,x1 movy.w @r7+,y1 ! .word 0xf3ce + movx.w @r4+r8,x0 movy.w @r6+r9,y0 ! .word 0xf00f + movx.w @r4+r8,x0 movy.w @r6+r9,y1 ! .word 0xf04f + movx.w @r4+r8,x1 movy.w @r6+r9,y0 ! .word 0xf08f + movx.w @r4+r8,x1 movy.w @r6+r9,y1 ! .word 0xf0cf + movx.w @r4+r8,x0 movy.w @r7+r9,y0 ! .word 0xf10f + movx.w @r4+r8,x0 movy.w @r7+r9,y1 ! .word 0xf14f + movx.w @r4+r8,x1 movy.w @r7+r9,y0 ! .word 0xf18f + movx.w @r4+r8,x1 movy.w @r7+r9,y1 ! .word 0xf1cf + movx.w @r5+r8,x0 movy.w @r6+r9,y0 ! .word 0xf20f + movx.w @r5+r8,x0 movy.w @r6+r9,y1 ! .word 0xf24f + movx.w @r5+r8,x1 movy.w @r6+r9,y0 ! .word 0xf28f + movx.w @r5+r8,x1 movy.w @r6+r9,y1 ! .word 0xf2cf + movx.w @r5+r8,x0 movy.w @r7+r9,y0 ! .word 0xf30f + movx.w @r5+r8,x0 movy.w @r7+r9,y1 ! .word 0xf34f + movx.w @r5+r8,x1 movy.w @r7+r9,y0 ! .word 0xf38f + movx.w @r5+r8,x1 movy.w @r7+r9,y1 ! .word 0xf3cf + movx.w @r4,x0 movy.w a0,@r6 ! .word 0xf015 + movx.w @r4,x0 movy.w a1,@r6 ! .word 0xf055 + movx.w @r4,x1 movy.w a0,@r6 ! .word 0xf095 + movx.w @r4,x1 movy.w a1,@r6 ! .word 0xf0d5 + movx.w @r4,x0 movy.w a0,@r7 ! .word 0xf115 + movx.w @r4,x0 movy.w a1,@r7 ! .word 0xf155 + movx.w @r4,x1 movy.w a0,@r7 ! .word 0xf195 + movx.w @r4,x1 movy.w a1,@r7 ! .word 0xf1d5 + movx.w @r5,x0 movy.w a0,@r6 ! .word 0xf215 + movx.w @r5,x0 movy.w a1,@r6 ! .word 0xf255 + movx.w @r5,x1 movy.w a0,@r6 ! .word 0xf295 + movx.w @r5,x1 movy.w a1,@r6 ! .word 0xf2d5 + movx.w @r5,x0 movy.w a0,@r7 ! .word 0xf315 + movx.w @r5,x0 movy.w a1,@r7 ! .word 0xf355 + movx.w @r5,x1 movy.w a0,@r7 ! .word 0xf395 + movx.w @r5,x1 movy.w a1,@r7 ! .word 0xf3d5 + movx.w @r4,x0 movy.w a0,@r6+ ! .word 0xf016 + movx.w @r4,x0 movy.w a1,@r6+ ! .word 0xf056 + movx.w @r4,x1 movy.w a0,@r6+ ! .word 0xf096 + movx.w @r4,x1 movy.w a1,@r6+ ! .word 0xf0d6 + movx.w @r4,x0 movy.w a0,@r7+ ! .word 0xf116 + movx.w @r4,x0 movy.w a1,@r7+ ! .word 0xf156 + movx.w @r4,x1 movy.w a0,@r7+ ! .word 0xf196 + movx.w @r4,x1 movy.w a1,@r7+ ! .word 0xf1d6 + movx.w @r5,x0 movy.w a0,@r6+ ! .word 0xf216 + movx.w @r5,x0 movy.w a1,@r6+ ! .word 0xf256 + movx.w @r5,x1 movy.w a0,@r6+ ! .word 0xf296 + movx.w @r5,x1 movy.w a1,@r6+ ! .word 0xf2d6 + movx.w @r5,x0 movy.w a0,@r7+ ! .word 0xf316 + movx.w @r5,x0 movy.w a1,@r7+ ! .word 0xf356 + movx.w @r5,x1 movy.w a0,@r7+ ! .word 0xf396 + movx.w @r5,x1 movy.w a1,@r7+ ! .word 0xf3d6 + movx.w @r4,x0 movy.w a0,@r6+r9 ! .word 0xf017 + movx.w @r4,x0 movy.w a1,@r6+r9 ! .word 0xf057 + movx.w @r4,x1 movy.w a0,@r6+r9 ! .word 0xf097 + movx.w @r4,x1 movy.w a1,@r6+r9 ! .word 0xf0d7 + movx.w @r4,x0 movy.w a0,@r7+r9 ! .word 0xf117 + movx.w @r4,x0 movy.w a1,@r7+r9 ! .word 0xf157 + movx.w @r4,x1 movy.w a0,@r7+r9 ! .word 0xf197 + movx.w @r4,x1 movy.w a1,@r7+r9 ! .word 0xf1d7 + movx.w @r5,x0 movy.w a0,@r6+r9 ! .word 0xf217 + movx.w @r5,x0 movy.w a1,@r6+r9 ! .word 0xf257 + movx.w @r5,x1 movy.w a0,@r6+r9 ! .word 0xf297 + movx.w @r5,x1 movy.w a1,@r6+r9 ! .word 0xf2d7 + movx.w @r5,x0 movy.w a0,@r7+r9 ! .word 0xf317 + movx.w @r5,x0 movy.w a1,@r7+r9 ! .word 0xf357 + movx.w @r5,x1 movy.w a0,@r7+r9 ! .word 0xf397 + movx.w @r5,x1 movy.w a1,@r7+r9 ! .word 0xf3d7 + movx.w @r4+,x0 movy.w a0,@r6 ! .word 0xf019 + movx.w @r4+,x0 movy.w a1,@r6 ! .word 0xf059 + movx.w @r4+,x1 movy.w a0,@r6 ! .word 0xf099 + movx.w @r4+,x1 movy.w a1,@r6 ! .word 0xf0d9 + movx.w @r4+,x0 movy.w a0,@r7 ! .word 0xf119 + movx.w @r4+,x0 movy.w a1,@r7 ! .word 0xf159 + movx.w @r4+,x1 movy.w a0,@r7 ! .word 0xf199 + movx.w @r4+,x1 movy.w a1,@r7 ! .word 0xf1d9 + movx.w @r5+,x0 movy.w a0,@r6 ! .word 0xf219 + movx.w @r5+,x0 movy.w a1,@r6 ! .word 0xf259 + movx.w @r5+,x1 movy.w a0,@r6 ! .word 0xf299 + movx.w @r5+,x1 movy.w a1,@r6 ! .word 0xf2d9 + movx.w @r5+,x0 movy.w a0,@r7 ! .word 0xf319 + movx.w @r5+,x0 movy.w a1,@r7 ! .word 0xf359 + movx.w @r5+,x1 movy.w a0,@r7 ! .word 0xf399 + movx.w @r5+,x1 movy.w a1,@r7 ! .word 0xf3d9 + movx.w @r4+,x0 movy.w a0,@r6+ ! .word 0xf01a + movx.w @r4+,x0 movy.w a1,@r6+ ! .word 0xf05a + movx.w @r4+,x1 movy.w a0,@r6+ ! .word 0xf09a + movx.w @r4+,x1 movy.w a1,@r6+ ! .word 0xf0da + movx.w @r4+,x0 movy.w a0,@r7+ ! .word 0xf11a + movx.w @r4+,x0 movy.w a1,@r7+ ! .word 0xf15a + movx.w @r4+,x1 movy.w a0,@r7+ ! .word 0xf19a + movx.w @r4+,x1 movy.w a1,@r7+ ! .word 0xf1da + movx.w @r5+,x0 movy.w a0,@r6+ ! .word 0xf21a + movx.w @r5+,x0 movy.w a1,@r6+ ! .word 0xf25a + movx.w @r5+,x1 movy.w a0,@r6+ ! .word 0xf29a + movx.w @r5+,x1 movy.w a1,@r6+ ! .word 0xf2da + movx.w @r5+,x0 movy.w a0,@r7+ ! .word 0xf31a + movx.w @r5+,x0 movy.w a1,@r7+ ! .word 0xf35a + movx.w @r5+,x1 movy.w a0,@r7+ ! .word 0xf39a + movx.w @r5+,x1 movy.w a1,@r7+ ! .word 0xf3da + movx.w @r4+,x0 movy.w a0,@r6+r9 ! .word 0xf01b + movx.w @r4+,x0 movy.w a1,@r6+r9 ! .word 0xf05b + movx.w @r4+,x1 movy.w a0,@r6+r9 ! .word 0xf09b + movx.w @r4+,x1 movy.w a1,@r6+r9 ! .word 0xf0db + movx.w @r4+,x0 movy.w a0,@r7+r9 ! .word 0xf11b + movx.w @r4+,x0 movy.w a1,@r7+r9 ! .word 0xf15b + movx.w @r4+,x1 movy.w a0,@r7+r9 ! .word 0xf19b + movx.w @r4+,x1 movy.w a1,@r7+r9 ! .word 0xf1db + movx.w @r5+,x0 movy.w a0,@r6+r9 ! .word 0xf21b + movx.w @r5+,x0 movy.w a1,@r6+r9 ! .word 0xf25b + movx.w @r5+,x1 movy.w a0,@r6+r9 ! .word 0xf29b + movx.w @r5+,x1 movy.w a1,@r6+r9 ! .word 0xf2db + movx.w @r5+,x0 movy.w a0,@r7+r9 ! .word 0xf31b + movx.w @r5+,x0 movy.w a1,@r7+r9 ! .word 0xf35b + movx.w @r5+,x1 movy.w a0,@r7+r9 ! .word 0xf39b + movx.w @r5+,x1 movy.w a1,@r7+r9 ! .word 0xf3db + movx.w @r4+r8,x0 movy.w a0,@r6 ! .word 0xf01d + movx.w @r4+r8,x0 movy.w a1,@r6 ! .word 0xf05d + movx.w @r4+r8,x1 movy.w a0,@r6 ! .word 0xf09d + movx.w @r4+r8,x1 movy.w a1,@r6 ! .word 0xf0dd + movx.w @r4+r8,x0 movy.w a0,@r7 ! .word 0xf11d + movx.w @r4+r8,x0 movy.w a1,@r7 ! .word 0xf15d + movx.w @r4+r8,x1 movy.w a0,@r7 ! .word 0xf19d + movx.w @r4+r8,x1 movy.w a1,@r7 ! .word 0xf1dd + movx.w @r5+r8,x0 movy.w a0,@r6 ! .word 0xf21d + movx.w @r5+r8,x0 movy.w a1,@r6 ! .word 0xf25d + movx.w @r5+r8,x1 movy.w a0,@r6 ! .word 0xf29d + movx.w @r5+r8,x1 movy.w a1,@r6 ! .word 0xf2dd + movx.w @r5+r8,x0 movy.w a0,@r7 ! .word 0xf31d + movx.w @r5+r8,x0 movy.w a1,@r7 ! .word 0xf35d + movx.w @r5+r8,x1 movy.w a0,@r7 ! .word 0xf39d + movx.w @r5+r8,x1 movy.w a1,@r7 ! .word 0xf3dd + movx.w @r4+r8,x0 movy.w a0,@r6+ ! .word 0xf01e + movx.w @r4+r8,x0 movy.w a1,@r6+ ! .word 0xf05e + movx.w @r4+r8,x1 movy.w a0,@r6+ ! .word 0xf09e + movx.w @r4+r8,x1 movy.w a1,@r6+ ! .word 0xf0de + movx.w @r4+r8,x0 movy.w a0,@r7+ ! .word 0xf11e + movx.w @r4+r8,x0 movy.w a1,@r7+ ! .word 0xf15e + movx.w @r4+r8,x1 movy.w a0,@r7+ ! .word 0xf19e + movx.w @r4+r8,x1 movy.w a1,@r7+ ! .word 0xf1de + movx.w @r5+r8,x0 movy.w a0,@r6+ ! .word 0xf21e + movx.w @r5+r8,x0 movy.w a1,@r6+ ! .word 0xf25e + movx.w @r5+r8,x1 movy.w a0,@r6+ ! .word 0xf29e + movx.w @r5+r8,x1 movy.w a1,@r6+ ! .word 0xf2de + movx.w @r5+r8,x0 movy.w a0,@r7+ ! .word 0xf31e + movx.w @r5+r8,x0 movy.w a1,@r7+ ! .word 0xf35e + movx.w @r5+r8,x1 movy.w a0,@r7+ ! .word 0xf39e + movx.w @r5+r8,x1 movy.w a1,@r7+ ! .word 0xf3de + movx.w @r4+r8,x0 movy.w a0,@r6+r9 ! .word 0xf01f + movx.w @r4+r8,x0 movy.w a1,@r6+r9 ! .word 0xf05f + movx.w @r4+r8,x1 movy.w a0,@r6+r9 ! .word 0xf09f + movx.w @r4+r8,x1 movy.w a1,@r6+r9 ! .word 0xf0df + movx.w @r4+r8,x0 movy.w a0,@r7+r9 ! .word 0xf11f + movx.w @r4+r8,x0 movy.w a1,@r7+r9 ! .word 0xf15f + movx.w @r4+r8,x1 movy.w a0,@r7+r9 ! .word 0xf19f + movx.w @r4+r8,x1 movy.w a1,@r7+r9 ! .word 0xf1df + movx.w @r5+r8,x0 movy.w a0,@r6+r9 ! .word 0xf21f + movx.w @r5+r8,x0 movy.w a1,@r6+r9 ! .word 0xf25f + movx.w @r5+r8,x1 movy.w a0,@r6+r9 ! .word 0xf29f + movx.w @r5+r8,x1 movy.w a1,@r6+r9 ! .word 0xf2df + movx.w @r5+r8,x0 movy.w a0,@r7+r9 ! .word 0xf31f + movx.w @r5+r8,x0 movy.w a1,@r7+r9 ! .word 0xf35f + movx.w @r5+r8,x1 movy.w a0,@r7+r9 ! .word 0xf39f + movx.w @r5+r8,x1 movy.w a1,@r7+r9 ! .word 0xf3df + movx.w a0,@r4 movy.w @r6,y0 ! .word 0xf025 + movx.w a0,@r4 movy.w @r6,y1 ! .word 0xf065 + movx.w a1,@r4 movy.w @r6,y0 ! .word 0xf0a5 + movx.w a1,@r4 movy.w @r6,y1 ! .word 0xf0e5 + movx.w a0,@r4 movy.w @r7,y0 ! .word 0xf125 + movx.w a0,@r4 movy.w @r7,y1 ! .word 0xf165 + movx.w a1,@r4 movy.w @r7,y0 ! .word 0xf1a5 + movx.w a1,@r4 movy.w @r7,y1 ! .word 0xf1e5 + movx.w a0,@r5 movy.w @r6,y0 ! .word 0xf225 + movx.w a0,@r5 movy.w @r6,y1 ! .word 0xf265 + movx.w a1,@r5 movy.w @r6,y0 ! .word 0xf2a5 + movx.w a1,@r5 movy.w @r6,y1 ! .word 0xf2e5 + movx.w a0,@r5 movy.w @r7,y0 ! .word 0xf325 + movx.w a0,@r5 movy.w @r7,y1 ! .word 0xf365 + movx.w a0,@r5 movy.w @r7,y1 ! .word 0xf3a5 + movx.w a1,@r5 movy.w @r7,y1 ! .word 0xf3e5 + movx.w a0,@r4 movy.w @r6+,y0 ! .word 0xf026 + movx.w a0,@r4 movy.w @r6+,y1 ! .word 0xf066 + movx.w a1,@r4 movy.w @r6+,y0 ! .word 0xf0a6 + movx.w a1,@r4 movy.w @r6+,y1 ! .word 0xf0e6 + movx.w a0,@r4 movy.w @r7+,y0 ! .word 0xf126 + movx.w a0,@r4 movy.w @r7+,y1 ! .word 0xf166 + movx.w a1,@r4 movy.w @r7+,y0 ! .word 0xf1a6 + movx.w a1,@r4 movy.w @r7+,y1 ! .word 0xf1e6 + movx.w a0,@r5 movy.w @r6+,y0 ! .word 0xf226 + movx.w a0,@r5 movy.w @r6+,y1 ! .word 0xf266 + movx.w a1,@r5 movy.w @r6+,y0 ! .word 0xf2a6 + movx.w a1,@r5 movy.w @r6+,y1 ! .word 0xf2e6 + movx.w a0,@r5 movy.w @r7+,y0 ! .word 0xf326 + movx.w a0,@r5 movy.w @r7+,y1 ! .word 0xf366 + movx.w a1,@r5 movy.w @r7+,y0 ! .word 0xf3a6 + movx.w a1,@r5 movy.w @r7+,y1 ! .word 0xf3e6 + movx.w a0,@r4 movy.w @r6+r9,y0 ! .word 0xf027 + movx.w a0,@r4 movy.w @r6+r9,y1 ! .word 0xf067 + movx.w a1,@r4 movy.w @r6+r9,y0 ! .word 0xf0a7 + movx.w a1,@r4 movy.w @r6+r9,y1 ! .word 0xf0e7 + movx.w a0,@r4 movy.w @r7+r9,y0 ! .word 0xf127 + movx.w a0,@r4 movy.w @r7+r9,y1 ! .word 0xf167 + movx.w a1,@r4 movy.w @r7+r9,y0 ! .word 0xf1a7 + movx.w a1,@r4 movy.w @r7+r9,y1 ! .word 0xf1e7 + movx.w a0,@r5 movy.w @r6+r9,y0 ! .word 0xf227 + movx.w a0,@r5 movy.w @r6+r9,y1 ! .word 0xf267 + movx.w a1,@r5 movy.w @r6+r9,y0 ! .word 0xf2a7 + movx.w a1,@r5 movy.w @r6+r9,y1 ! .word 0xf2e7 + movx.w a0,@r5 movy.w @r7+r9,y0 ! .word 0xf327 + movx.w a0,@r5 movy.w @r7+r9,y1 ! .word 0xf367 + movx.w a1,@r5 movy.w @r7+r9,y0 ! .word 0xf3a7 + movx.w a1,@r5 movy.w @r7+r9,y1 ! .word 0xf3e7 + movx.w a0,@r4+ movy.w @r6,y0 ! .word 0xf029 + movx.w a0,@r4+ movy.w @r6,y1 ! .word 0xf069 + movx.w a1,@r4+ movy.w @r6,y0 ! .word 0xf0a9 + movx.w a1,@r4+ movy.w @r6,y1 ! .word 0xf0e9 + movx.w a0,@r4+ movy.w @r7,y0 ! .word 0xf129 + movx.w a0,@r4+ movy.w @r7,y1 ! .word 0xf169 + movx.w a1,@r4+ movy.w @r7,y0 ! .word 0xf1a9 + movx.w a1,@r4+ movy.w @r7,y1 ! .word 0xf1e9 + movx.w a0,@r5+ movy.w @r6,y0 ! .word 0xf229 + movx.w a0,@r5+ movy.w @r6,y1 ! .word 0xf269 + movx.w a1,@r5+ movy.w @r6,y0 ! .word 0xf2a9 + movx.w a1,@r5+ movy.w @r6,y1 ! .word 0xf2e9 + movx.w a0,@r5+ movy.w @r7,y0 ! .word 0xf329 + movx.w a0,@r5+ movy.w @r7,y1 ! .word 0xf369 + movx.w a1,@r5+ movy.w @r7,y0 ! .word 0xf3a9 + movx.w a1,@r5+ movy.w @r7,y1 ! .word 0xf3e9 + movx.w a0,@r4+ movy.w @r6+,y0 ! .word 0xf02a + movx.w a0,@r4+ movy.w @r6+,y1 ! .word 0xf06a + movx.w a1,@r4+ movy.w @r6+,y0 ! .word 0xf0aa + movx.w a1,@r4+ movy.w @r6+,y1 ! .word 0xf0ea + movx.w a0,@r4+ movy.w @r7+,y0 ! .word 0xf12a + movx.w a0,@r4+ movy.w @r7+,y1 ! .word 0xf16a + movx.w a1,@r4+ movy.w @r7+,y0 ! .word 0xf1aa + movx.w a1,@r4+ movy.w @r7+,y1 ! .word 0xf1ea + movx.w a0,@r5+ movy.w @r6+,y0 ! .word 0xf22a + movx.w a0,@r5+ movy.w @r6+,y1 ! .word 0xf26a + movx.w a1,@r5+ movy.w @r6+,y0 ! .word 0xf2aa + movx.w a1,@r5+ movy.w @r6+,y1 ! .word 0xf2ea + movx.w a0,@r5+ movy.w @r7+,y0 ! .word 0xf32a + movx.w a0,@r5+ movy.w @r7+,y1 ! .word 0xf36a + movx.w a1,@r5+ movy.w @r7+,y0 ! .word 0xf3aa + movx.w a1,@r5+ movy.w @r7+,y1 ! .word 0xf3ea + movx.w a0,@r4+ movy.w @r6+r9,y0 ! .word 0xf02b + movx.w a0,@r4+ movy.w @r6+r9,y1 ! .word 0xf06b + movx.w a1,@r4+ movy.w @r6+r9,y0 ! .word 0xf0ab + movx.w a1,@r4+ movy.w @r6+r9,y1 ! .word 0xf0eb + movx.w a0,@r4+ movy.w @r7+r9,y0 ! .word 0xf12b + movx.w a0,@r4+ movy.w @r7+r9,y1 ! .word 0xf16b + movx.w a1,@r4+ movy.w @r7+r9,y0 ! .word 0xf1ab + movx.w a1,@r4+ movy.w @r7+r9,y1 ! .word 0xf1eb + movx.w a0,@r5+ movy.w @r6+r9,y0 ! .word 0xf22b + movx.w a0,@r5+ movy.w @r6+r9,y1 ! .word 0xf26b + movx.w a1,@r5+ movy.w @r6+r9,y0 ! .word 0xf2ab + movx.w a1,@r5+ movy.w @r6+r9,y1 ! .word 0xf2eb + movx.w a0,@r5+ movy.w @r7+r9,y0 ! .word 0xf32b + movx.w a0,@r5+ movy.w @r7+r9,y1 ! .word 0xf36b + movx.w a1,@r5+ movy.w @r7+r9,y0 ! .word 0xf3ab + movx.w a1,@r5+ movy.w @r7+r9,y1 ! .word 0xf3eb + movx.w a0,@r4+r8 movy.w @r6,y0 ! .word 0xf02d + movx.w a0,@r4+r8 movy.w @r6,y1 ! .word 0xf06d + movx.w a1,@r4+r8 movy.w @r6,y0 ! .word 0xf0ad + movx.w a1,@r4+r8 movy.w @r6,y1 ! .word 0xf0ed + movx.w a0,@r4+r8 movy.w @r7,y0 ! .word 0xf12d + movx.w a0,@r4+r8 movy.w @r7,y1 ! .word 0xf16d + movx.w a1,@r4+r8 movy.w @r7,y0 ! .word 0xf1ad + movx.w a1,@r4+r8 movy.w @r7,y1 ! .word 0xf1ed + movx.w a0,@r5+r8 movy.w @r6,y0 ! .word 0xf22d + movx.w a0,@r5+r8 movy.w @r6,y1 ! .word 0xf26d + movx.w a1,@r5+r8 movy.w @r6,y0 ! .word 0xf2ad + movx.w a1,@r5+r8 movy.w @r6,y1 ! .word 0xf2ed + movx.w a0,@r5+r8 movy.w @r7,y0 ! .word 0xf32d + movx.w a0,@r5+r8 movy.w @r7,y1 ! .word 0xf36d + movx.w a1,@r5+r8 movy.w @r7,y0 ! .word 0xf3ad + movx.w a1,@r5+r8 movy.w @r7,y1 ! .word 0xf3ed + movx.w a0,@r4+r8 movy.w @r6+,y0 ! .word 0xf02e + movx.w a0,@r4+r8 movy.w @r6+,y1 ! .word 0xf06e + movx.w a1,@r4+r8 movy.w @r6+,y0 ! .word 0xf0ae + movx.w a1,@r4+r8 movy.w @r6+,y1 ! .word 0xf0ee + movx.w a0,@r4+r8 movy.w @r7+,y0 ! .word 0xf12e + movx.w a0,@r4+r8 movy.w @r7+,y1 ! .word 0xf16e + movx.w a1,@r4+r8 movy.w @r7+,y0 ! .word 0xf1ae + movx.w a1,@r4+r8 movy.w @r7+,y1 ! .word 0xf1ee + movx.w a0,@r5+r8 movy.w @r6+,y0 ! .word 0xf22e + movx.w a0,@r5+r8 movy.w @r6+,y1 ! .word 0xf26e + movx.w a1,@r5+r8 movy.w @r6+,y0 ! .word 0xf2ae + movx.w a1,@r5+r8 movy.w @r6+,y1 ! .word 0xf2ee + movx.w a0,@r5+r8 movy.w @r7+,y0 ! .word 0xf32e + movx.w a0,@r5+r8 movy.w @r7+,y1 ! .word 0xf36e + movx.w a1,@r5+r8 movy.w @r7+,y0 ! .word 0xf3ae + movx.w a1,@r5+r8 movy.w @r7+,y1 ! .word 0xf3ee + movx.w a0,@r4+r8 movy.w @r6+r9,y0 ! .word 0xf02f + movx.w a0,@r4+r8 movy.w @r6+r9,y1 ! .word 0xf06f + movx.w a1,@r4+r8 movy.w @r6+r9,y0 ! .word 0xf0af + movx.w a1,@r4+r8 movy.w @r6+r9,y1 ! .word 0xf0ef + movx.w a0,@r4+r8 movy.w @r7+r9,y0 ! .word 0xf12f + movx.w a0,@r4+r8 movy.w @r7+r9,y1 ! .word 0xf16f + movx.w a1,@r4+r8 movy.w @r7+r9,y0 ! .word 0xf1af + movx.w a1,@r4+r8 movy.w @r7+r9,y1 ! .word 0xf1ef + movx.w a0,@r5+r8 movy.w @r6+r9,y0 ! .word 0xf22f + movx.w a0,@r5+r8 movy.w @r6+r9,y1 ! .word 0xf26f + movx.w a1,@r5+r8 movy.w @r6+r9,y0 ! .word 0xf2af + movx.w a1,@r5+r8 movy.w @r6+r9,y1 ! .word 0xf2ef + movx.w a0,@r5+r8 movy.w @r7+r9,y0 ! .word 0xf32f + movx.w a0,@r5+r8 movy.w @r7+r9,y1 ! .word 0xf36f + movx.w a1,@r5+r8 movy.w @r7+r9,y0 ! .word 0xf3af + movx.w a1,@r5+r8 movy.w @r7+r9,y1 ! .word 0xf3ef + +movxwaxydxy: + movx.w @r4,x0 ! + movx.w @r4,y0 ! + movx.w @r4,x1 ! + movx.w @r4,y1 ! + movx.w @r0,x0 ! + movx.w @r0,y0 ! + movx.w @r0,x1 ! + movx.w @r0,y1 ! + movx.w @r5,x0 ! + movx.w @r5,y0 ! + movx.w @r5,x1 ! + movx.w @r5,y1 ! + movx.w @r1,x0 ! + movx.w @r1,y0 ! + movx.w @r1,x1 ! + movx.w @r1,y1 ! + movx.w @r4+,x0 ! + movx.w @r4+,y0 ! + movx.w @r4+,x1 ! + movx.w @r4+,y1 ! + movx.w @r0+,x0 ! + movx.w @r0+,y0 ! + movx.w @r0+,x1 ! + movx.w @r0+,y1 ! + movx.w @r5+,x0 ! + movx.w @r5+,y0 ! + movx.w @r5+,x1 ! + movx.w @r5+,y1 ! + movx.w @r1+,x0 ! + movx.w @r1+,y0 ! + movx.w @r1+,x1 ! + movx.w @r1+,y1 ! + movx.w @r4+r8,x0 ! + movx.w @r4+r8,y0 ! + movx.w @r4+r8,x1 ! + movx.w @r4+r8,y1 ! + movx.w @r0+r8,x0 ! + movx.w @r0+r8,y0 ! + movx.w @r0+r8,x1 ! + movx.w @r0+r8,y1 ! + movx.w @r5+r8,x0 ! + movx.w @r5+r8,y0 ! + movx.w @r5+r8,x1 ! + movx.w @r5+r8,y1 ! + movx.w @r1+r8,x0 ! + movx.w @r1+r8,y0 ! + movx.w @r1+r8,x1 ! + movx.w @r1+r8,y1 ! + +movxwdaxaxy: ! + movx.w a0,@r4 ! + movx.w x0,@r4 ! + movx.w a1,@r4 ! + movx.w x1,@r4 ! + movx.w a0,@r0 ! + movx.w x0,@r0 ! + movx.w a1,@r0 ! + movx.w x1,@r0 ! + movx.w a0,@r5 ! + movx.w x0,@r5 ! + movx.w a1,@r5 ! + movx.w x1,@r5 ! + movx.w a0,@r1 ! + movx.w x0,@r1 ! + movx.w a1,@r1 ! + movx.w x1,@r1 ! + movx.w a0,@r4+ ! + movx.w x0,@r4+ ! + movx.w a1,@r4+ ! + movx.w x1,@r4+ ! + movx.w a0,@r0+ ! + movx.w x0,@r0+ ! + movx.w a1,@r0+ ! + movx.w x1,@r0+ ! + movx.w a0,@r5+ ! + movx.w x0,@r5+ ! + movx.w a1,@r5+ ! + movx.w x1,@r5+ ! + movx.w a0,@r1+ ! + movx.w x0,@r1+ ! + movx.w a1,@r1+ ! + movx.w x1,@r1+ ! + movx.w a0,@r4+r8 ! + movx.w x0,@r4+r8 ! + movx.w a1,@r4+r8 ! + movx.w x1,@r4+r8 ! + movx.w a0,@r0+r8 ! + movx.w x0,@r0+r8 ! + movx.w a1,@r0+r8 ! + movx.w x1,@r0+r8 ! + movx.w a0,@r5+r8 ! + movx.w x0,@r5+r8 ! + movx.w a1,@r5+r8 ! + movx.w x1,@r5+r8 ! + movx.w a0,@r1+r8 ! + movx.w x0,@r1+r8 ! + movx.w a1,@r1+r8 ! + movx.w x1,@r1+r8 ! + +movywayxdyx: ! + movy.w @r6,y0 ! + movy.w @r6,y1 ! + movy.w @r6,x0 ! + movy.w @r6,x1 ! + movy.w @r7,y0 ! + movy.w @r7,y1 ! + movy.w @r7,x0 ! + movy.w @r7,x1 ! + movy.w @r2,y0 ! + movy.w @r2,y1 ! + movy.w @r2,x0 ! + movy.w @r2,x1 ! + movy.w @r3,y0 ! + movy.w @r3,y1 ! + movy.w @r3,x0 ! + movy.w @r3,x1 ! + movy.w @r6+,y0 ! + movy.w @r6+,y1 ! + movy.w @r6+,x0 ! + movy.w @r6+,x1 ! + movy.w @r7+,y0 ! + movy.w @r7+,y1 ! + movy.w @r7+,x0 ! + movy.w @r7+,x1 ! + movy.w @r2+,y0 ! + movy.w @r2+,y1 ! + movy.w @r2+,x0 ! + movy.w @r2+,x1 ! + movy.w @r3+,y0 ! + movy.w @r3+,y1 ! + movy.w @r3+,x0 ! + movy.w @r3+,x1 ! + movy.w @r6+r9,y0 ! + movy.w @r6+r9,y1 ! + movy.w @r6+r9,x0 ! + movy.w @r6+r9,x1 ! + movy.w @r7+r9,y0 ! + movy.w @r7+r9,y1 ! + movy.w @r7+r9,x0 ! + movy.w @r7+r9,x1 ! + movy.w @r2+r9,y0 ! + movy.w @r2+r9,y1 ! + movy.w @r2+r9,x0 ! + movy.w @r2+r9,x1 ! + movy.w @r3+r9,y0 ! + movy.w @r3+r9,y1 ! + movy.w @r3+r9,x0 ! + movy.w @r3+r9,x1 ! + +movywdayayx: + movy.w a0,@r6 + movy.w a1,@r6 + movy.w y0,@r6 + movy.w y1,@r6 + movy.w a0,@r7 + movy.w a1,@r7 + movy.w y0,@r7 + movy.w y1,@r7 + movy.w a0,@r2 + movy.w a1,@r2 + movy.w y0,@r2 + movy.w y1,@r2 + movy.w a0,@r3 + movy.w a1,@r3 + movy.w y0,@r3 + movy.w y1,@r3 + movy.w a0,@r6+ + movy.w a1,@r6+ + movy.w y0,@r6+ + movy.w y1,@r6+ + movy.w a0,@r7+ + movy.w a1,@r7+ + movy.w y0,@r7+ + movy.w y1,@r7+ + movy.w a0,@r2+ + movy.w a1,@r2+ + movy.w y0,@r2+ + movy.w y1,@r2+ + movy.w a0,@r3+ + movy.w a1,@r3+ + movy.w y0,@r3+ + movy.w y1,@r3+ + movy.w a0,@r6+r9 + movy.w a1,@r6+r9 + movy.w y0,@r6+r9 + movy.w y1,@r6+r9 + movy.w a0,@r7+r9 + movy.w a1,@r7+r9 + movy.w y0,@r7+r9 + movy.w y1,@r7+r9 + movy.w a0,@r2+r9 + movy.w a1,@r2+r9 + movy.w y0,@r2+r9 + movy.w y1,@r2+r9 + movy.w a0,@r3+r9 + movy.w a1,@r3+r9 + movy.w y0,@r3+r9 + movy.w y1,@r3+r9 + + mov r4, r0 + mov r4, r1 + mov r4, r2 + mov r4, r3 + mov r4, r5 + mov r4, r6 + mov r5, r7 + +movxlaxydxy: + movx.l @r4,x0 + movx.l @r4,y0 + movx.l @r4,x1 + movx.l @r4,y1 + movx.l @r0,x0 + movx.l @r0,y0 + movx.l @r0,x1 + movx.l @r0,y1 + movx.l @r5,x0 + movx.l @r5,y0 + movx.l @r5,x1 + movx.l @r5,y1 + movx.l @r1,x0 + movx.l @r1,y0 + movx.l @r1,x1 + movx.l @r1,y1 + movx.l @r4+,x0 + movx.l @r4+,y0 + movx.l @r4+,x1 + movx.l @r4+,y1 + movx.l @r0+,x0 + movx.l @r0+,y0 + movx.l @r0+,x1 + movx.l @r0+,y1 + movx.l @r5+,x0 + movx.l @r5+,y0 + movx.l @r5+,x1 + movx.l @r5+,y1 + movx.l @r1+,x0 + movx.l @r1+,y0 + movx.l @r1+,x1 + movx.l @r1+,y1 + movx.l @r4+r8,x0 + movx.l @r4+r8,y0 + movx.l @r4+r8,x1 + movx.l @r4+r8,y1 + movx.l @r0+r8,x0 + movx.l @r0+r8,y0 + movx.l @r0+r8,x1 + movx.l @r0+r8,y1 + movx.l @r5+r8,x0 + movx.l @r5+r8,y0 + movx.l @r5+r8,x1 + movx.l @r5+r8,y1 + movx.l @r1+r8,x0 + movx.l @r1+r8,y0 + movx.l @r1+r8,x1 + movx.l @r1+r8,y1 + +movxldaxaxy: + movx.l a0,@r4 + movx.l x0,@r4 + movx.l a1,@r4 + movx.l x1,@r4 + movx.l a0,@r0 + movx.l x0,@r0 + movx.l a1,@r0 + movx.l x1,@r0 + movx.l a0,@r5 + movx.l x0,@r5 + movx.l a1,@r5 + movx.l x1,@r5 + movx.l a0,@r1 + movx.l x0,@r1 + movx.l a1,@r1 + movx.l x1,@r1 + movx.l a0,@r4+ + movx.l x0,@r4+ + movx.l a1,@r4+ + movx.l x1,@r4+ + movx.l a0,@r0+ + movx.l x0,@r0+ + movx.l a1,@r0+ + movx.l x1,@r0+ + movx.l a0,@r5+ + movx.l x0,@r5+ + movx.l a1,@r5+ + movx.l x1,@r5+ + movx.l a0,@r1+ + movx.l x0,@r1+ + movx.l a1,@r1+ + movx.l x1,@r1+ + movx.l a0,@r4+r8 + movx.l x0,@r4+r8 + movx.l a1,@r4+r8 + movx.l x1,@r4+r8 + movx.l a0,@r0+r8 + movx.l x0,@r0+r8 + movx.l a1,@r0+r8 + movx.l x1,@r0+r8 + movx.l a0,@r5+r8 + movx.l x0,@r5+r8 + movx.l a1,@r5+r8 + movx.l x1,@r5+r8 + movx.l a0,@r1+r8 + movx.l x0,@r1+r8 + movx.l a1,@r1+r8 + movx.l x1,@r1+r8 + +movylayxdyx: + movy.l @r6,y0 + movy.l @r6,y1 + movy.l @r6,x0 + movy.l @r6,x1 + movy.l @r7,y0 + movy.l @r7,y1 + movy.l @r7,x0 + movy.l @r7,x1 + movy.l @r2,y0 + movy.l @r2,y1 + movy.l @r2,x0 + movy.l @r2,x1 + movy.l @r3,y0 + movy.l @r3,y1 + movy.l @r3,x0 + movy.l @r3,x1 + movy.l @r6+,y0 + movy.l @r6+,y1 + movy.l @r6+,x0 + movy.l @r6+,x1 + movy.l @r7+,y0 + movy.l @r7+,y1 + movy.l @r7+,x0 + movy.l @r7+,x1 + movy.l @r2+,y0 + movy.l @r2+,y1 + movy.l @r2+,x0 + movy.l @r2+,x1 + movy.l @r3+,y0 + movy.l @r3+,y1 + movy.l @r3+,x0 + movy.l @r3+,x1 + movy.l @r6+r9,y0 + movy.l @r6+r9,y1 + movy.l @r6+r9,x0 + movy.l @r6+r9,x1 + movy.l @r7+r9,y0 + movy.l @r7+r9,y1 + movy.l @r7+r9,x0 + movy.l @r7+r9,x1 + movy.l @r2+r9,y0 + movy.l @r2+r9,y1 + movy.l @r2+r9,x0 + movy.l @r2+r9,x1 + movy.l @r3+r9,y0 + movy.l @r3+r9,y1 + movy.l @r3+r9,x0 + movy.l @r3+r9,x1 + +movyldayayx: + movy.l a0,@r6 + movy.l a1,@r6 + movy.l y0,@r6 + movy.l y1,@r6 + movy.l a0,@r7 + movy.l a1,@r7 + movy.l y0,@r7 + movy.l y1,@r7 + movy.l a0,@r2 + movy.l a1,@r2 + movy.l y0,@r2 + movy.l y1,@r2 + movy.l a0,@r3 + movy.l a1,@r3 + movy.l y0,@r3 + movy.l y1,@r3 + movy.l a0,@r6+ + movy.l a1,@r6+ + movy.l y0,@r6+ + movy.l y1,@r6+ + movy.l a0,@r7+ + movy.l a1,@r7+ + movy.l y0,@r7+ + movy.l y1,@r7+ + movy.l a0,@r2+ + movy.l a1,@r2+ + movy.l y0,@r2+ + movy.l y1,@r2+ + movy.l a0,@r3+ + movy.l a1,@r3+ + movy.l y0,@r3+ + movy.l y1,@r3+ + movy.l a0,@r6+r9 + movy.l a1,@r6+r9 + movy.l y0,@r6+r9 + movy.l y1,@r6+r9 + movy.l a0,@r7+r9 + movy.l a1,@r7+r9 + movy.l y0,@r7+r9 + movy.l y1,@r7+r9 + movy.l a0,@r2+r9 + movy.l a1,@r2+r9 + movy.l y0,@r2+r9 + movy.l y1,@r2+r9 + movy.l a0,@r3+r9 + movy.l a1,@r3+r9 + movy.l y0,@r3+r9 + movy.l y1,@r3+r9 + + pass + exit 0 diff --git a/sim/testsuite/sh/mulr.s b/sim/testsuite/sh/mulr.s new file mode 100644 index 00000000000..1e755ab2de7 --- /dev/null +++ b/sim/testsuite/sh/mulr.s @@ -0,0 +1,162 @@ +# sh testcase for mulr +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +mulr_1: ! multiply by one + set_grs_a5a5 + mov #1, r0 + mulr r0, r1 + assertreg0 1 + test_gr_a5a5 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +mulr_2: ! multiply by two + set_grs_a5a5 + mov #2, r0 + mov #12, r1 + mulr r0, r1 + assertreg0 2 + assertreg 24, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +mulr_3: ! multiply five by five + set_grs_a5a5 + mov #5, r0 + mov #5, r1 + mulr r0, r1 + assertreg0 5 + assertreg 25, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + +mulr_4: ! multiply 127 by 127 + set_grs_a5a5 + mov #127, r0 + mov #127, r1 + mulr r0, r1 + assertreg0 127 + assertreg 0x3f01, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +mulr_5: ! multiply -1 by -1 + set_grs_a5a5 + mov #-1, r0 + mov #-1, r1 + mulr r0, r1 + assertreg0 -1 + assertreg 1, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +mulr_6: ! multiply 46340 by 46340 + set_grs_a5a5 + movi20 #46340, r0 + movi20 #46340, r1 + mulr r0, r1 + assertreg0 46340 + assertreg 0x7ffea810, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +mulr_7: ! multiply 7ffff by 7ffff (overflow) + set_grs_a5a5 + movi20 #0x7ffff, r0 + movi20 #0x7ffff, r1 + mulr r0, r1 + assertreg0 0x7ffff + assertreg 0xfff00001, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + + pass + + exit 0 + +
\ No newline at end of file diff --git a/sim/testsuite/sh/pabs.s b/sim/testsuite/sh/pabs.s new file mode 100644 index 00000000000..6a9e4f24226 --- /dev/null +++ b/sim/testsuite/sh/pabs.s @@ -0,0 +1,54 @@ +# sh testcase for pabs +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + # FIXME: opcode table ambiguity in ignored bits 4-7. + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + pabs x0, x1 + pabs y0, y1 + assert_sreg 0x5a5a5a5b, x1 + assert_sreg 0x5a5a5a5b, y1 + pabs x1, x0 + pabs y1, y0 + assert_sreg 0x5a5a5a5b, x0 + assert_sreg 0x5a5a5a5b, y0 + + set_dcfalse + dct pabs a0, a0 + dct pabs m0, m0 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, m0 + set_dctrue + dct pabs a0, a0 + dct pabs m0, m0 + assert_sreg 0x5a5a5a5b, a0 + assert_sreg2 0x5a5a5a5b, m0 + + set_dctrue + dcf pabs a1, a1 + dcf pabs m1, m1 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m1 + set_dcfalse + dcf pabs a1, a1 + dcf pabs m1, m1 + assert_sreg2 0x5a5a5a5b, a1 + assert_sreg2 0x5a5a5a5b, m1 + + test_grs_a5a5 + + pass + exit 0 diff --git a/sim/testsuite/sh/padd.s b/sim/testsuite/sh/padd.s new file mode 100644 index 00000000000..072935dcdf5 --- /dev/null +++ b/sim/testsuite/sh/padd.s @@ -0,0 +1,54 @@ +# sh testcase for padd +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + padd x0, y0, a0 + assert_sreg 0x4b4b4b4a, a0 + + # 2 + 2 = 4 + mov #2, r0 + lds r0, x0 + lds r0, y0 + padd x0, y0, a0 + assert_sreg 4, a0 + + set_dcfalse + dct padd x0, y0, a1 + assert_sreg2 0xa5a5a5a5, a1 + set_dctrue + dct padd x0, y0, a1 + assert_sreg2 4, a1 + + set_dctrue + dcf padd x0, y0, m1 + assert_sreg2 0xa5a5a5a5, m1 + set_dcfalse + dcf padd x0, y0, m1 + assert_sreg2 4, m1 + + # padd / pmuls + + padd x0, y0, y0 pmuls x1, y1, m1 + assert_sreg 4, y0 + assert_sreg2 0x3fc838b2, m1 ! (int) 0xa5a5 x (int) 0xa5a5 x 2 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + + pass + exit 0 diff --git a/sim/testsuite/sh/paddc.s b/sim/testsuite/sh/paddc.s new file mode 100644 index 00000000000..0dd3b67b172 --- /dev/null +++ b/sim/testsuite/sh/paddc.s @@ -0,0 +1,39 @@ +# sh testcase for paddc +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + # 2 + 2 = 4 + set_dcfalse + mov #2, r0 + lds r0, x0 + lds r0, y0 + paddc x0, y0, a0 + assert_sreg 4, a0 + + # 2 + 2 + carry = 5 + set_dctrue + paddc x0, y0, a1 + assert_sreg2 5, a1 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + pass + exit 0 diff --git a/sim/testsuite/sh/pand.s b/sim/testsuite/sh/pand.s new file mode 100644 index 00000000000..cddf05892cb --- /dev/null +++ b/sim/testsuite/sh/pand.s @@ -0,0 +1,48 @@ +# sh testcase for pand +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + pand x0, y0, a0 + assert_sreg 0xa5a50000, a0 + + # 0xa5a5a5a5 & 0x5a5a5a5a == 0 + set_greg 0x5a5a5a5a r0 + lds r0, x0 + pand x0, y0, a0 + assert_sreg 0, a0 + + set_dcfalse + dct pand x0, y0, m0 + assert_sreg2 0xa5a5a5a5, m0 + set_dctrue + dct pand x0, y0, m0 + assert_sreg2 0, m0 + + set_dctrue + dcf pand x0, y0, m1 + assert_sreg2 0xa5a5a5a5, m1 + set_dcfalse + dcf pand x0, y0, m1 + assert_sreg2 0, m1 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, a1 + + pass + exit 0 diff --git a/sim/testsuite/sh/pass.s b/sim/testsuite/sh/pass.s new file mode 100644 index 00000000000..cc3bbccd740 --- /dev/null +++ b/sim/testsuite/sh/pass.s @@ -0,0 +1,14 @@ +# sh testcase, pass +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + test_grs_a5a5 + pass + + exit 0 + diff --git a/sim/testsuite/sh/pclr.s b/sim/testsuite/sh/pclr.s new file mode 100644 index 00000000000..c396f832dee --- /dev/null +++ b/sim/testsuite/sh/pclr.s @@ -0,0 +1,65 @@ +# sh testcase for pclr +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + # FIXME: opcode table ambiguity in ignored bits 4-7. + + .include "testutils.inc" + + start +pclr_cc: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + assert_sreg 0xa5a5a5a5, x0 + pclr x0 + assert_sreg 0, x0 + + set_dcfalse + dct pclr x1 + assert_sreg 0xa5a5a5a5, x1 + set_dctrue + dct pclr x1 + assert_sreg 0, x1 + + set_dctrue + dcf pclr y0 + assert_sreg 0xa5a5a5a5, y0 + set_dcfalse + dcf pclr y0 + assert_sreg 0, y0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +pclr_pmuls: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + pclr x0 pmuls y0, y1, a0 + + assert_sreg 0, x0 + assert_sreg 0x3fc838b2, a0 ! 0xa5a5 x 0xa5a5 + + test_grs_a5a5 + + pass + exit 0 diff --git a/sim/testsuite/sh/pdec.s b/sim/testsuite/sh/pdec.s new file mode 100644 index 00000000000..fa4b6a56e9c --- /dev/null +++ b/sim/testsuite/sh/pdec.s @@ -0,0 +1,110 @@ +# sh testcase for pdec +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +pdecx: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + pdec x0, y0 + assert_sreg 0xa5a40000, y0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +pdecy: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + pdec y0, x0 + assert_sreg 0xa5a40000, x0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +dct_pdecx: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_dcfalse + dct pdec x0, y0 + assert_sreg 0xa5a5a5a5, y0 + set_dctrue + dct pdec x0, y0 + assert_sreg 0xa5a40000, y0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +dcf_pdecy: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_dctrue + dcf pdec y0, x0 + assert_sreg 0xa5a5a5a5, x0 + set_dcfalse + dcf pdec y0, x0 + assert_sreg 0xa5a40000, x0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + pass + exit 0 diff --git a/sim/testsuite/sh/pdmsb.s b/sim/testsuite/sh/pdmsb.s new file mode 100644 index 00000000000..0cb78293265 --- /dev/null +++ b/sim/testsuite/sh/pdmsb.s @@ -0,0 +1,230 @@ +# sh testcase for pdmsb +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_sreg 0x0, x0 +L0: pdmsb x0, x1 +# assert_sreg 31<<16, x1 + set_sreg 0x1, x0 +L1: pdmsb x0, x1 + assert_sreg 30<<16, x1 + set_sreg 0x3, x0 +L2: pdmsb x0, x1 + assert_sreg 29<<16, x1 + set_sreg 0x7, x0 +L3: pdmsb x0, x1 + assert_sreg 28<<16, x1 + set_sreg 0xf, x0 +L4: pdmsb x0, x1 + assert_sreg 27<<16, x1 + set_sreg 0x1f, x0 +L5: pdmsb x0, x1 + assert_sreg 26<<16, x1 + set_sreg 0x3f, x0 +L6: pdmsb x0, x1 + assert_sreg 25<<16, x1 + set_sreg 0x7f, x0 +L7: pdmsb x0, x1 + assert_sreg 24<<16, x1 + set_sreg 0xff, x0 +L8: pdmsb x0, x1 + assert_sreg 23<<16, x1 + + set_sreg 0x1ff, x0 +L9: pdmsb x0, x1 + assert_sreg 22<<16, x1 + set_sreg 0x3ff, x0 +L10: pdmsb x0, x1 + assert_sreg 21<<16, x1 + set_sreg 0x7ff, x0 +L11: pdmsb x0, x1 + assert_sreg 20<<16, x1 + set_sreg 0xfff, x0 +L12: pdmsb x0, x1 + assert_sreg 19<<16, x1 + set_sreg 0x1fff, x0 +L13: pdmsb x0, x1 + assert_sreg 18<<16, x1 + set_sreg 0x3fff, x0 +L14: pdmsb x0, x1 + assert_sreg 17<<16, x1 + set_sreg 0x7fff, x0 +L15: pdmsb x0, x1 + assert_sreg 16<<16, x1 + set_sreg 0xffff, x0 +L16: pdmsb x0, x1 + assert_sreg 15<<16, x1 + + set_sreg 0x1ffff, x0 +L17: pdmsb x0, x1 + assert_sreg 14<<16, x1 + set_sreg 0x3ffff, x0 +L18: pdmsb x0, x1 + assert_sreg 13<<16, x1 + set_sreg 0x7ffff, x0 +L19: pdmsb x0, x1 + assert_sreg 12<<16, x1 + set_sreg 0xfffff, x0 +L20: pdmsb x0, x1 + assert_sreg 11<<16, x1 + set_sreg 0x1fffff, x0 +L21: pdmsb x0, x1 + assert_sreg 10<<16, x1 + set_sreg 0x3fffff, x0 +L22: pdmsb x0, x1 + assert_sreg 9<<16, x1 + set_sreg 0x7fffff, x0 +L23: pdmsb x0, x1 + assert_sreg 8<<16, x1 + set_sreg 0xffffff, x0 +L24: pdmsb x0, x1 + assert_sreg 7<<16, x1 + + set_sreg 0x1ffffff, x0 +L25: pdmsb x0, x1 + assert_sreg 6<<16, x1 + set_sreg 0x3ffffff, x0 +L26: pdmsb x0, x1 + assert_sreg 5<<16, x1 + set_sreg 0x7ffffff, x0 +L27: pdmsb x0, x1 + assert_sreg 4<<16, x1 + set_sreg 0xfffffff, x0 +L28: pdmsb x0, x1 + assert_sreg 3<<16, x1 + set_sreg 0x1fffffff, x0 +L29: pdmsb x0, x1 + assert_sreg 2<<16, x1 + set_sreg 0x3fffffff, x0 +L30: pdmsb x0, x1 + assert_sreg 1<<16, x1 + set_sreg 0x7fffffff, x0 +L31: pdmsb x0, x1 + assert_sreg 0<<16, x1 + set_sreg 0xffffffff, x0 +L32: pdmsb x0, x1 +# assert_sreg 31<<16, x1 + + set_sreg 0xfffffffe, x0 +L33: pdmsb x0, x1 + assert_sreg 30<<16, x1 + set_sreg 0xfffffffc, x0 +L34: pdmsb x0, x1 + assert_sreg 29<<16, x1 + set_sreg 0xfffffff8, x0 +L35: pdmsb x0, x1 + assert_sreg 28<<16, x1 + set_sreg 0xfffffff0, x0 +L36: pdmsb x0, x1 + assert_sreg 27<<16, x1 + set_sreg 0xffffffe0, x0 +L37: pdmsb x0, x1 + assert_sreg 26<<16, x1 + set_sreg 0xffffffc0, x0 +L38: pdmsb x0, x1 + assert_sreg 25<<16, x1 + set_sreg 0xffffff80, x0 +L39: pdmsb x0, x1 + assert_sreg 24<<16, x1 + set_sreg 0xffffff00, x0 +L40: pdmsb x0, x1 + assert_sreg 23<<16, x1 + + set_sreg 0xfffffe00, x0 +L41: pdmsb x0, x1 + assert_sreg 22<<16, x1 + set_sreg 0xfffffc00, x0 +L42: pdmsb x0, x1 + assert_sreg 21<<16, x1 + set_sreg 0xfffff800, x0 +L43: pdmsb x0, x1 + assert_sreg 20<<16, x1 + set_sreg 0xfffff000, x0 +L44: pdmsb x0, x1 + assert_sreg 19<<16, x1 + set_sreg 0xffffe000, x0 +L45: pdmsb x0, x1 + assert_sreg 18<<16, x1 + set_sreg 0xffffc000, x0 +L46: pdmsb x0, x1 + assert_sreg 17<<16, x1 + set_sreg 0xffff8000, x0 +L47: pdmsb x0, x1 + assert_sreg 16<<16, x1 + set_sreg 0xffff0000, x0 +L48: pdmsb x0, x1 + assert_sreg 15<<16, x1 + + set_sreg 0xfffe0000, x0 +L49: pdmsb x0, x1 + assert_sreg 14<<16, x1 + set_sreg 0xfffc0000, x0 +L50: pdmsb x0, x1 + assert_sreg 13<<16, x1 + set_sreg 0xfff80000, x0 +L51: pdmsb x0, x1 + assert_sreg 12<<16, x1 + set_sreg 0xfff00000, x0 +L52: pdmsb x0, x1 + assert_sreg 11<<16, x1 + set_sreg 0xffe00000, x0 +L53: pdmsb x0, x1 + assert_sreg 10<<16, x1 + set_sreg 0xffc00000, x0 +L54: pdmsb x0, x1 + assert_sreg 9<<16, x1 + set_sreg 0xff800000, x0 +L55: pdmsb x0, x1 + assert_sreg 8<<16, x1 + set_sreg 0xff000000, x0 +L56: pdmsb x0, x1 + assert_sreg 7<<16, x1 + + set_sreg 0xfe000000, x0 +L57: pdmsb x0, x1 + assert_sreg 6<<16, x1 + set_sreg 0xfc000000, x0 +L58: pdmsb x0, x1 + assert_sreg 5<<16, x1 + set_sreg 0xf8000000, x0 +L59: pdmsb x0, x1 + assert_sreg 4<<16, x1 + set_sreg 0xf0000000, x0 +L60: pdmsb x0, x1 + assert_sreg 3<<16, x1 + set_sreg 0xe0000000, x0 +L61: pdmsb x0, x1 + assert_sreg 2<<16, x1 + set_sreg 0xc0000000, x0 +L62: pdmsb x0, x1 + assert_sreg 1<<16, x1 + set_sreg 0x80000000, x0 +L63: pdmsb x0, x1 + assert_sreg 0<<16, x1 + set_sreg 0x00000000, x0 +L64: pdmsb x0, x1 +# assert_sreg 31<<16, x1 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + pass + exit 0 diff --git a/sim/testsuite/sh/pinc.s b/sim/testsuite/sh/pinc.s new file mode 100644 index 00000000000..0067bc00ebe --- /dev/null +++ b/sim/testsuite/sh/pinc.s @@ -0,0 +1,110 @@ +# sh testcase for pinc +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +pincx: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + pinc x0, y0 + assert_sreg 0xa5a60000, y0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +pincy: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + pinc y0, x0 + assert_sreg 0xa5a60000, x0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +dct_pincx: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_dcfalse + dct pinc x0, y0 + assert_sreg 0xa5a5a5a5, y0 + set_dctrue + dct pinc x0, y0 + assert_sreg 0xa5a60000, y0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +dcf_pincy: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_dctrue + dcf pinc y0, x0 + assert_sreg 0xa5a5a5a5, x0 + set_dcfalse + dcf pinc y0, x0 + assert_sreg 0xa5a60000, x0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + pass + exit 0 diff --git a/sim/testsuite/sh/pmuls.s b/sim/testsuite/sh/pmuls.s new file mode 100644 index 00000000000..4cff8787f4e --- /dev/null +++ b/sim/testsuite/sh/pmuls.s @@ -0,0 +1,33 @@ +# sh testcase for pmuls +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + # 2 x 2 = 8 (?) + # (I don't understand why the result is x2, + # but that's what it says in the manual...) + mov #2, r0 + shll16 r0 + lds r0, y0 + lds r0, y1 + pmuls y0, y1, a0 + + assert_sreg 8, a0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + pass + exit 0 + diff --git a/sim/testsuite/sh/prnd.s b/sim/testsuite/sh/prnd.s new file mode 100644 index 00000000000..897d5b9ded9 --- /dev/null +++ b/sim/testsuite/sh/prnd.s @@ -0,0 +1,90 @@ +# sh testcase for prnd +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + # FIXME: opcode table ambiguity in ignored bits 4-7. + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + # prnd(0xa5a5a5a5) = 0xa5a60000 + prnd x0, x0 + prnd y0, y0 + assert_sreg 0xa5a60000, x0 + assert_sreg 0xa5a60000, y0 + + # prnd(1) = 1 + mov #1, r0 + shll16 r0 + lds r0, x0 + pcopy x0, y0 + prnd x0, x0 + prnd y0, y0 + assert_sreg 0x10000, x0 + assert_sreg 0x10000, y0 + + # prnd(1.4999999) = 1 + mov #1, r0 + shll8 r0 + or #0x7f, r0 + shll8 r0 + or #0xff, r0 + lds r0, x0 + pcopy x0, y0 + prnd x0, x0 + prnd y0, y0 + assert_sreg 0x10000, x0 + assert_sreg 0x10000, y0 + + # prnd(1.5) = 2 + mov #1, r0 + shll8 r0 + or #0x80, r0 + shll8 r0 + lds r0, x0 + pcopy x0, y0 + prnd x0, x0 + prnd y0, y0 + assert_sreg 0x20000, x0 + assert_sreg 0x20000, y0 + + # dct prnd + set_dcfalse + dct prnd x0, x1 + dct prnd y0, y1 + assert_sreg2 0xa5a5a5a5, x1 + assert_sreg2 0xa5a5a5a5, y1 + set_dctrue + dct prnd x0, x1 + dct prnd y0, y1 + assert_sreg2 0x20000, x1 + assert_sreg2 0x20000, y1 + + # dcf prnd + set_dctrue + dcf prnd x0, m0 + dcf prnd y0, m1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + set_dcfalse + dcf prnd x0, m0 + dcf prnd y0, m1 + assert_sreg2 0x20000, m0 + assert_sreg2 0x20000, m1 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + pass + exit 0 diff --git a/sim/testsuite/sh/pshai.s b/sim/testsuite/sh/pshai.s new file mode 100644 index 00000000000..b2cdbbc81b8 --- /dev/null +++ b/sim/testsuite/sh/pshai.s @@ -0,0 +1,200 @@ +# sh testcase for psha <imm> +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +psha_imm: ! shift arithmetic, immediate operand + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_sreg 0x1, a0 + psha #0, a0 + assert_sreg 0x1, a0 + psha #-0, a0 + assert_sreg 0x1, a0 + + psha #1, a0 + assert_sreg 0x2, a0 + psha #-1, a0 + assert_sreg 0x1, a0 + + psha #2, a0 + assert_sreg 0x4, a0 + psha #-2, a0 + assert_sreg 0x1, a0 + + psha #3, a0 + assert_sreg 0x8, a0 + psha #-3, a0 + assert_sreg 0x1, a0 + + psha #4, a0 + assert_sreg 0x10, a0 + psha #-4, a0 + assert_sreg 0x1, a0 + + psha #5, a0 + assert_sreg 0x20, a0 + psha #-5, a0 + assert_sreg 0x1, a0 + + psha #6, a0 + assert_sreg 0x40, a0 + psha #-6, a0 + assert_sreg 0x1, a0 + + psha #7, a0 + assert_sreg 0x80, a0 + psha #-7, a0 + assert_sreg 0x1, a0 + + psha #8, a0 + assert_sreg 0x100, a0 + psha #-8, a0 + assert_sreg 0x1, a0 + + psha #9, a0 + assert_sreg 0x200, a0 + psha #-9, a0 + assert_sreg 0x1, a0 + + psha #10, a0 + assert_sreg 0x400, a0 + psha #-10, a0 + assert_sreg 0x1, a0 + + psha #11, a0 + assert_sreg 0x800, a0 + psha #-11, a0 + assert_sreg 0x1, a0 + + psha #12, a0 + assert_sreg 0x1000, a0 + psha #-12, a0 + assert_sreg 0x1, a0 + + psha #13, a0 + assert_sreg 0x2000, a0 + psha #-13, a0 + assert_sreg 0x1, a0 + + psha #14, a0 + assert_sreg 0x4000, a0 + psha #-14, a0 + assert_sreg 0x1, a0 + + psha #15, a0 + assert_sreg 0x8000, a0 + psha #-15, a0 + assert_sreg 0x1, a0 + + psha #16, a0 + assert_sreg 0x10000, a0 + psha #-16, a0 + assert_sreg 0x1, a0 + + psha #17, a0 + assert_sreg 0x20000, a0 + psha #-17, a0 + assert_sreg 0x1, a0 + + psha #18, a0 + assert_sreg 0x40000, a0 + psha #-18, a0 + assert_sreg 0x1, a0 + + psha #19, a0 + assert_sreg 0x80000, a0 + psha #-19, a0 + assert_sreg 0x1, a0 + + psha #20, a0 + assert_sreg 0x100000, a0 + psha #-20, a0 + assert_sreg 0x1, a0 + + psha #21, a0 + assert_sreg 0x200000, a0 + psha #-21, a0 + assert_sreg 0x1, a0 + + psha #22, a0 + assert_sreg 0x400000, a0 + psha #-22, a0 + assert_sreg 0x1, a0 + + psha #23, a0 + assert_sreg 0x800000, a0 + psha #-23, a0 + assert_sreg 0x1, a0 + + psha #24, a0 + assert_sreg 0x1000000, a0 + psha #-24, a0 + assert_sreg 0x1, a0 + + psha #25, a0 + assert_sreg 0x2000000, a0 + psha #-25, a0 + assert_sreg 0x1, a0 + + psha #26, a0 + assert_sreg 0x4000000, a0 + psha #-26, a0 + assert_sreg 0x1, a0 + + psha #27, a0 + assert_sreg 0x8000000, a0 + psha #-27, a0 + assert_sreg 0x1, a0 + + psha #28, a0 + assert_sreg 0x10000000, a0 + psha #-28, a0 + assert_sreg 0x1, a0 + + psha #29, a0 + assert_sreg 0x20000000, a0 + psha #-29, a0 + assert_sreg 0x1, a0 + + psha #30, a0 + assert_sreg 0x40000000, a0 + psha #-30, a0 + assert_sreg 0x1, a0 + + psha #31, a0 + assert_sreg 0x80000000, a0 + psha #-31, a0 + assert_sreg 0xffffffff, a0 + + psha #32, a0 + assert_sreg 0x00000000, a0 +# I don't grok what should happen here... +# psha #-32, a0 +# assert_sreg 0x0, a0 + + test_grs_a5a5 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + + pass + exit 0 + diff --git a/sim/testsuite/sh/pshar.s b/sim/testsuite/sh/pshar.s new file mode 100644 index 00000000000..01c4b5fdef2 --- /dev/null +++ b/sim/testsuite/sh/pshar.s @@ -0,0 +1,265 @@ +# sh testcase for psha <reg> +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +psha_reg: ! shift arithmetic, register operand + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_sreg 0x1, x0 + set_sreg 0x0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x10000, y0 + psha x0, y0, x0 + assert_sreg 0x2, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x20000, y0 + psha x0, y0, x0 + assert_sreg 0x4, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x30000, y0 + psha x0, y0, x0 + assert_sreg 0x8, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x40000, y0 + psha x0, y0, x0 + assert_sreg 0x10, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x50000, y0 + psha x0, y0, x0 + assert_sreg 0x20, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x60000, y0 + psha x0, y0, x0 + assert_sreg 0x40, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x70000, y0 + psha x0, y0, x0 + assert_sreg 0x80, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x80000, y0 + psha x0, y0, x0 + assert_sreg 0x100, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x90000, y0 + psha x0, y0, x0 + assert_sreg 0x200, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0xa0000, y0 + psha x0, y0, x0 + assert_sreg 0x400, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0xb0000, y0 + psha x0, y0, x0 + assert_sreg 0x800, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0xc0000, y0 + psha x0, y0, x0 + assert_sreg 0x1000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0xd0000, y0 + psha x0, y0, x0 + assert_sreg 0x2000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0xe0000, y0 + psha x0, y0, x0 + assert_sreg 0x4000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0xf0000, y0 + psha x0, y0, x0 + assert_sreg 0x8000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x100000, y0 + psha x0, y0, x0 + assert_sreg 0x10000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x110000, y0 + psha x0, y0, x0 + assert_sreg 0x20000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x120000, y0 + psha x0, y0, x0 + assert_sreg 0x40000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x130000, y0 + psha x0, y0, x0 + assert_sreg 0x80000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x140000, y0 + psha x0, y0, x0 + assert_sreg 0x100000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x150000, y0 + psha x0, y0, x0 + assert_sreg 0x200000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x160000, y0 + psha x0, y0, x0 + assert_sreg 0x400000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x170000, y0 + psha x0, y0, x0 + assert_sreg 0x800000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x180000, y0 + psha x0, y0, x0 + assert_sreg 0x1000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x190000, y0 + psha x0, y0, x0 + assert_sreg 0x2000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x1a0000, y0 + psha x0, y0, x0 + assert_sreg 0x4000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x1b0000, y0 + psha x0, y0, x0 + assert_sreg 0x8000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x1c0000, y0 + psha x0, y0, x0 + assert_sreg 0x10000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x1d0000, y0 + psha x0, y0, x0 + assert_sreg 0x20000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x1e0000, y0 + psha x0, y0, x0 + assert_sreg 0x40000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x1f0000, y0 + psha x0, y0, x0 + assert_sreg 0x80000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0xffffffff, x0 + + set_sreg 0x200000, y0 + psha x0, y0, x0 + assert_sreg 0x00000000, x0 +# I don't grok what should happen here... +# pneg y0, y0 +# psha x0, y0, x0 +# assert_sreg 0x0, x0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + + pass + exit 0 + diff --git a/sim/testsuite/sh/pshli.s b/sim/testsuite/sh/pshli.s new file mode 100644 index 00000000000..a6616e896ac --- /dev/null +++ b/sim/testsuite/sh/pshli.s @@ -0,0 +1,119 @@ +# sh testcase for pshl <imm> +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +pshl_imm: ! shift logical, immediate operand + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_sreg 0x10000, a0 + pshl #0, a0 + assert_sreg 0x10000, a0 + pshl #-0, a0 + assert_sreg 0x10000, a0 + + pshl #1, a0 + assert_sreg 0x20000, a0 + pshl #-1, a0 + assert_sreg 0x10000, a0 + + pshl #2, a0 + assert_sreg 0x40000, a0 + pshl #-2, a0 + assert_sreg 0x10000, a0 + + pshl #3, a0 + assert_sreg 0x80000, a0 + pshl #-3, a0 + assert_sreg 0x10000, a0 + + pshl #4, a0 + assert_sreg 0x100000, a0 + pshl #-4, a0 + assert_sreg 0x10000, a0 + + pshl #5, a0 + assert_sreg 0x200000, a0 + pshl #-5, a0 + assert_sreg 0x10000, a0 + + pshl #6, a0 + assert_sreg 0x400000, a0 + pshl #-6, a0 + assert_sreg 0x10000, a0 + + pshl #7, a0 + assert_sreg 0x800000, a0 + pshl #-7, a0 + assert_sreg 0x10000, a0 + + pshl #8, a0 + assert_sreg 0x1000000, a0 + pshl #-8, a0 + assert_sreg 0x10000, a0 + + pshl #9, a0 + assert_sreg 0x2000000, a0 + pshl #-9, a0 + assert_sreg 0x10000, a0 + + pshl #10, a0 + assert_sreg 0x4000000, a0 + pshl #-10, a0 + assert_sreg 0x10000, a0 + + pshl #11, a0 + assert_sreg 0x8000000, a0 + pshl #-11, a0 + assert_sreg 0x10000, a0 + + pshl #12, a0 + assert_sreg 0x10000000, a0 + pshl #-12, a0 + assert_sreg 0x10000, a0 + + pshl #13, a0 + assert_sreg 0x20000000, a0 + pshl #-13, a0 + assert_sreg 0x10000, a0 + + pshl #14, a0 + assert_sreg 0x40000000, a0 + pshl #-14, a0 + assert_sreg 0x10000, a0 + + pshl #15, a0 + assert_sreg 0x80000000, a0 + pshl #-15, a0 + assert_sreg 0x10000, a0 + + pshl #16, a0 + assert_sreg 0x00000000, a0 + pshl #-16, a0 + assert_sreg 0x0, a0 + + test_grs_a5a5 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + + pass + exit 0 + diff --git a/sim/testsuite/sh/pshlr.s b/sim/testsuite/sh/pshlr.s new file mode 100644 index 00000000000..36cb47f4188 --- /dev/null +++ b/sim/testsuite/sh/pshlr.s @@ -0,0 +1,152 @@ +# sh testcase for pshl <reg> +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +pshl_reg: ! shift arithmetic, register operand + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_sreg 0x10000, x0 + set_sreg 0x0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x10000, y0 + pshl x0, y0, x0 + assert_sreg 0x20000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x20000, y0 + pshl x0, y0, x0 + assert_sreg 0x40000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x30000, y0 + pshl x0, y0, x0 + assert_sreg 0x80000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x40000, y0 + pshl x0, y0, x0 + assert_sreg 0x100000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x50000, y0 + pshl x0, y0, x0 + assert_sreg 0x200000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x60000, y0 + pshl x0, y0, x0 + assert_sreg 0x400000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x70000, y0 + pshl x0, y0, x0 + assert_sreg 0x800000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x80000, y0 + pshl x0, y0, x0 + assert_sreg 0x1000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x90000, y0 + pshl x0, y0, x0 + assert_sreg 0x2000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xa0000, y0 + pshl x0, y0, x0 + assert_sreg 0x4000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xb0000, y0 + pshl x0, y0, x0 + assert_sreg 0x8000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xc0000, y0 + pshl x0, y0, x0 + assert_sreg 0x10000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xd0000, y0 + pshl x0, y0, x0 + assert_sreg 0x20000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xe0000, y0 + pshl x0, y0, x0 + assert_sreg 0x40000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xf0000, y0 + pshl x0, y0, x0 + assert_sreg 0x80000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x100000, y0 + pshl x0, y0, x0 + assert_sreg 0x00000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x0, x0 + + test_grs_a5a5 + assert_sreg2 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + + pass + exit 0 + diff --git a/sim/testsuite/sh/psub.s b/sim/testsuite/sh/psub.s new file mode 100644 index 00000000000..bcfd26e9514 --- /dev/null +++ b/sim/testsuite/sh/psub.s @@ -0,0 +1,64 @@ +# sh testcase for psub +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + +psub_sx_sy: + # 0xa5a5a5a5 minus 0xa5a5a5a5 equals zero + psub x0, y0, a0 + assert_sreg 0, a0 + +psub_sy_sx: + # 100 - 25 = 75 + mov #100, r0 + mov #25, r1 + lds r0, y1 + lds r1, x1 + psub y1, x1, a0 + assert_sreg 75, a0 + +dct_psub: + # 100 - 25 = 75 + set_dcfalse + dct psub y1, x1, a1 + assert_sreg2 0xa5a5a5a5, a1 + set_dctrue + dct psub y1, x1, a1 + assert_sreg2 75, a1 + +dcf_psub: + # 25 - 100 = -75 + set_dctrue + dcf psub x1, y1, m1 + assert_sreg2 0xa5a5a5a5, m1 + set_dcfalse + dcf psub x1, y1, m1 + assert_sreg2 -75, m1 + +psub_pmuls: + # 25 - 100 = -75, and 2 x 2 = 8 (yes, eight, not four) + mov #2, r0 + shll16 r0 + lds r0, x0 + lds r0, y0 + psub x1, y1, a1 pmuls x0, y0, a0 + assert_sreg 8, a0 + assert_sreg2 -75, a1 + + set_greg 0xa5a5a5a5, r0 + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + pass + exit 0 diff --git a/sim/testsuite/sh/pswap.s b/sim/testsuite/sh/pswap.s new file mode 100644 index 00000000000..5bd6a5939cc --- /dev/null +++ b/sim/testsuite/sh/pswap.s @@ -0,0 +1,177 @@ +# sh testcase for pswap +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +pswapx: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_greg 0xa5a57777, r0 + lds r0, x0 + pswap x0, y0 + assert_sreg 0x7777a5a5, y0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a57777, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +pswapy: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_greg 0xa5a57777, r0 + lds r0, y0 + pswap y0, x0 + assert_sreg 0x7777a5a5, x0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a57777, y0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +pswapa: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_greg 0xa5a57777, r0 + lds r0, a0 + pcopy a0, a1 + pswap a1, y0 + assert_sreg 0x7777a5a5, y0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a57777, a0 + assert_sreg2 0xa5a57777, a1 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +pswapm: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_greg 0xa5a57777, r0 + lds r0, a0 + pcopy a0, m1 + pswap m1, y0 + assert_sreg 0x7777a5a5, y0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a57777, a0 + assert_sreg2 0xa5a57777, m1 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + + +dct_pswapx: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_greg 0xa5a57777, r0 + lds r0, x0 + set_dcfalse + dct pswap x0, y0 + assert_sreg 0xa5a5a5a5, y0 + set_dctrue + dct pswap x0, y0 + assert_sreg 0x7777a5a5, y0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a57777, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +dcf_pswapy: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_greg 0xa5a57777, r0 + lds r0, x0 + set_dctrue + dcf pswap x0, y0 + assert_sreg 0xa5a5a5a5, y0 + set_dcfalse + dcf pswap x0, y0 + assert_sreg 0x7777a5a5, y0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a57777, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + pass + exit 0 diff --git a/sim/testsuite/sh/pushpop.s b/sim/testsuite/sh/pushpop.s new file mode 100644 index 00000000000..9ee5bfd6888 --- /dev/null +++ b/sim/testsuite/sh/pushpop.s @@ -0,0 +1,146 @@ +# sh testcase for push/pop (mov,movml,movmu...) insns. +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start +movml_1: + set_greg 0, r0 + set_greg 1, r1 + set_greg 2, r2 + set_greg 3, r3 + set_greg 4, r4 + set_greg 5, r5 + set_greg 6, r6 + set_greg 7, r7 + set_greg 8, r8 + set_greg 9, r9 + set_greg 10, r10 + set_greg 11, r11 + set_greg 12, r12 + set_greg 13, r13 + set_greg 14, r14 + set_sreg 15, pr + + movml.l r15,@-r15 + + assertmem stackt-4, 15 + assertmem stackt-8, 14 + assertmem stackt-12, 13 + assertmem stackt-16, 12 + assertmem stackt-20, 11 + assertmem stackt-24, 10 + assertmem stackt-28, 9 + assertmem stackt-32, 8 + assertmem stackt-36, 7 + assertmem stackt-40, 6 + assertmem stackt-44, 5 + assertmem stackt-48, 4 + assertmem stackt-52, 3 + assertmem stackt-56, 2 + assertmem stackt-60, 1 + assertmem stackt-64, 0 + + assertreg0 0 + assertreg 1, r1 + assertreg 2, r2 + assertreg 3, r3 + assertreg 4, r4 + assertreg 5, r5 + assertreg 6, r6 + assertreg 7, r7 + assertreg 8, r8 + assertreg 9, r9 + assertreg 10, r10 + assertreg 11, r11 + assertreg 12, r12 + assertreg 13, r13 + assertreg 14, r14 + mov r15, r0 + assertreg0 stackt-64 + +movml_2: + set_grs_a5a5 + movml.l @r15+, r15 + assert_sreg 15, pr + assertreg0 0 + assertreg 1, r1 + assertreg 2, r2 + assertreg 3, r3 + assertreg 4, r4 + assertreg 5, r5 + assertreg 6, r6 + assertreg 7, r7 + assertreg 8, r8 + assertreg 9, r9 + assertreg 10, r10 + assertreg 11, r11 + assertreg 12, r12 + assertreg 13, r13 + assertreg 14, r14 + mov r15, r0 + assertreg0 stackt + +movmu_1: + set_grs_a5a5 + add #1,r14 + add #2,r13 + add #3,r12 + set_sreg 0xa5a5,pr + + movmu.l r12,@-r15 + + assert_sreg 0xa5a5,pr + assertreg 0xa5a5a5a6, r14 + assertreg 0xa5a5a5a7, r13 + assertreg 0xa5a5a5a8, r12 + test_gr_a5a5 r11 + test_gr_a5a5 r10 + test_gr_a5a5 r9 + test_gr_a5a5 r8 + test_gr_a5a5 r7 + test_gr_a5a5 r6 + test_gr_a5a5 r5 + test_gr_a5a5 r4 + test_gr_a5a5 r3 + test_gr_a5a5 r2 + test_gr_a5a5 r1 + test_gr_a5a5 r0 + mov r15, r0 + assertreg stackt-16, r0 + + assertmem stackt-4, 0xa5a5 + assertmem stackt-8, 0xa5a5a5a6 + assertmem stackt-12, 0xa5a5a5a7 + assertmem stackt-16, 0xa5a5a5a8 + +movmu_2: + set_grs_a5a5 + movmu.l @r15+,r12 + + assert_sreg 0xa5a5, pr + assertreg 0xa5a5a5a6, r14 + assertreg 0xa5a5a5a7, r13 + assertreg 0xa5a5a5a8, r12 + test_gr_a5a5 r11 + test_gr_a5a5 r10 + test_gr_a5a5 r9 + test_gr_a5a5 r8 + test_gr_a5a5 r7 + test_gr_a5a5 r6 + test_gr_a5a5 r5 + test_gr_a5a5 r4 + test_gr_a5a5 r3 + test_gr_a5a5 r2 + test_gr_a5a5 r1 + test_gr_a5a5 r0 + mov r15, r0 + assertreg stackt, r0 + + pass + + exit 0 + +
\ No newline at end of file diff --git a/sim/testsuite/sh/resbank.s b/sim/testsuite/sh/resbank.s new file mode 100644 index 00000000000..33801b86586 --- /dev/null +++ b/sim/testsuite/sh/resbank.s @@ -0,0 +1,268 @@ +# sh testcase for ldbank stbank resbank +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .macro SEND reg bankno regno + set_greg ((\bankno << 7) + (\regno << 2)), \reg + .endm + + start + +stbank_1: + set_grs_a5a5 + mov #0, r0 + SEND r1, 0, 0 + stbank r0, @r1 + mov #1, r0 + SEND r1, 0, 1 + stbank r0, @r1 + mov #2, r0 + SEND r1, 0, 2 + stbank r0, @r1 + mov #3, r0 + SEND r1, 0, 3 + stbank r0, @r1 + mov #4, r0 + SEND r1, 0, 4 + stbank r0, @r1 + mov #5, r0 + SEND r1, 0, 5 + stbank r0, @r1 + mov #6, r0 + SEND r1, 0, 6 + stbank r0, @r1 + mov #7, r0 + SEND r1, 0, 7 + stbank r0, @r1 + mov #8, r0 + SEND r1, 0, 8 + stbank r0, @r1 + mov #9, r0 + SEND r1, 0, 9 + stbank r0, @r1 + mov #10, r0 + SEND r1, 0, 10 + stbank r0, @r1 + mov #11, r0 + SEND r1, 0, 11 + stbank r0, @r1 + mov #12, r0 + SEND r1, 0, 12 + stbank r0, @r1 + mov #13, r0 + SEND r1, 0, 13 + stbank r0, @r1 + mov #14, r0 + SEND r1, 0, 14 + stbank r0, @r1 + mov #15, r0 + SEND r1, 0, 15 + stbank r0, @r1 + mov #16, r0 + SEND r1, 0, 16 + stbank r0, @r1 + mov #17, r0 + SEND r1, 0, 17 + stbank r0, @r1 + mov #18, r0 + SEND r1, 0, 18 + stbank r0, @r1 + mov #19, r0 + SEND r1, 0, 19 + stbank r0, @r1 + + assertreg0 19 + assertreg 19 << 2, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +ldbank_1: + set_grs_a5a5 + SEND r1, 0, 0 + ldbank @r1, r0 + assertreg0 0 + SEND r1, 0, 1 + ldbank @r1, r0 + assertreg0 1 + SEND r1, 0, 2 + ldbank @r1, r0 + assertreg0 2 + SEND r1, 0, 3 + ldbank @r1, r0 + assertreg0 3 + SEND r1, 0, 4 + ldbank @r1, r0 + assertreg0 4 + SEND r1, 0, 5 + ldbank @r1, r0 + assertreg0 5 + SEND r1, 0, 6 + ldbank @r1, r0 + assertreg0 6 + SEND r1, 0, 7 + ldbank @r1, r0 + assertreg0 7 + SEND r1, 0, 8 + ldbank @r1, r0 + assertreg0 8 + SEND r1, 0, 9 + ldbank @r1, r0 + assertreg0 9 + SEND r1, 0, 10 + ldbank @r1, r0 + assertreg0 10 + SEND r1, 0, 11 + ldbank @r1, r0 + assertreg0 11 + SEND r1, 0, 12 + ldbank @r1, r0 + assertreg0 12 + SEND r1, 0, 13 + ldbank @r1, r0 + assertreg0 13 + SEND r1, 0, 14 + ldbank @r1, r0 + assertreg0 14 + SEND r1, 0, 15 + ldbank @r1, r0 + assertreg0 15 + SEND r1, 0, 16 + ldbank @r1, r0 + assertreg0 16 + SEND r1, 0, 17 + ldbank @r1, r0 + assertreg0 17 + SEND r1, 0, 18 + ldbank @r1, r0 + assertreg0 18 + SEND r1, 0, 19 + ldbank @r1, r0 + assertreg0 19 + + assertreg (19 << 2), r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +resbank_1: + set_grs_a5a5 + mov #1, r0 + trapa #13 ! magic trap, sets ibnr + + resbank + + assertreg0 0 + assertreg 1, r1 + assertreg 2, r2 + assertreg 3, r3 + assertreg 4, r4 + assertreg 5, r5 + assertreg 6, r6 + assertreg 7, r7 + assertreg 8, r8 + assertreg 9, r9 + assertreg 10, r10 + assertreg 11, r11 + assertreg 12, r12 + assertreg 13, r13 + assertreg 14, r14 + assert_sreg 15, mach + assert_sreg 17, pr + assert_creg 18, gbr + assert_sreg 19, macl + +resbank_2: + set_grs_a5a5 + movi20 #555, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + add #-1, r0 + mov.l r0, @-r15 + + set_sr_bit (1 << 14) ! set BO + + resbank + + assert_sreg 555, macl + assert_sreg 554, mach + assert_creg 553, gbr + assert_sreg 552, pr + assertreg 551, r14 + assertreg 550, r13 + assertreg 549, r12 + assertreg 548, r11 + assertreg 547, r10 + assertreg 546, r9 + assertreg 545, r8 + assertreg 544, r7 + assertreg 543, r6 + assertreg 542, r5 + assertreg 541, r4 + assertreg 540, r3 + assertreg 539, r2 + assertreg 538, r1 + assertreg0 537 + + mov r15, r0 + assertreg0 stackt + + pass + + exit 0 diff --git a/sim/testsuite/sh/sett.s b/sim/testsuite/sh/sett.s new file mode 100644 index 00000000000..fff2d2d4a6d --- /dev/null +++ b/sim/testsuite/sh/sett.s @@ -0,0 +1,65 @@ +# sh testcase for sett, clrt, movt +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start +sett_1: set_grs_a5a5 + sett + bt .Lsett + nop + fail +.Lsett: + test_grs_a5a5 + +clrt_1: set_grs_a5a5 + clrt + bf .Lclrt + nop + fail +.Lclrt: + test_grs_a5a5 + +movt_1: set_grs_a5a5 + sett + movt r1 + test_gr_a5a5 r0 + assertreg 1, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +movt_2: set_grs_a5a5 + clrt + movt r1 + test_gr_a5a5 r0 + assertreg 0, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 diff --git a/sim/testsuite/sh/shll.s b/sim/testsuite/sh/shll.s new file mode 100644 index 00000000000..ec2ea12d671 --- /dev/null +++ b/sim/testsuite/sh/shll.s @@ -0,0 +1,91 @@ +# sh testcase for shll +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +shll: + set_grs_a5a5 + mov #1, r1 + shll r1 + assertreg 2, r1 + shll r1 + assertreg 4, r1 + shll r1 + assertreg 8, r1 + shll r1 + assertreg 16, r1 + shll r1 + assertreg 32, r1 + shll r1 + assertreg 64, r1 + shll r1 + assertreg 0x80, r1 + shll r1 + assertreg 0x100, r1 + shll r1 + assertreg 0x200, r1 + shll r1 + assertreg 0x400, r1 + shll r1 + assertreg 0x800, r1 + shll r1 + assertreg 0x1000, r1 + shll r1 + assertreg 0x2000, r1 + shll r1 + assertreg 0x4000, r1 + shll r1 + assertreg 0x8000, r1 + shll r1 + assertreg 0x10000, r1 + shll r1 + assertreg 0x20000, r1 + shll r1 + assertreg 0x40000, r1 + shll r1 + assertreg 0x80000, r1 + shll r1 + assertreg 0x100000, r1 + shll r1 + assertreg 0x200000, r1 + shll r1 + assertreg 0x400000, r1 + shll r1 + assertreg 0x800000, r1 + shll r1 + assertreg 0x1000000, r1 + shll r1 + assertreg 0x2000000, r1 + shll r1 + assertreg 0x4000000, r1 + shll r1 + assertreg 0x8000000, r1 + shll r1 + assertreg 0x10000000, r1 + shll r1 + assertreg 0x20000000, r1 + shll r1 + assertreg 0x40000000, r1 + shll r1 + assertreg 0x80000000, r1 + shll r1 + assertreg 0, r1 + shll r1 + assertreg 0, r1 + + # another: + mov #1, r1 + shll r1 + shll r1 + shll r1 + assertreg 8, r1 + + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + + pass + exit 0 diff --git a/sim/testsuite/sh/shll16.s b/sim/testsuite/sh/shll16.s new file mode 100644 index 00000000000..4574835f8e3 --- /dev/null +++ b/sim/testsuite/sh/shll16.s @@ -0,0 +1,46 @@ +# sh testcase for shll16 +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +shll16: + set_grs_a5a5 + mov #0x18, r1 + shll16 r1 + assertreg 0x180000, r1 + shll16 r1 + assertreg 0, r1 + + # another: + mov #1, r1 + shll16 r1 + mov #1, r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + cmp/eq r1, r7 + bt okay + fail +okay: + set_greg 0xa5a5a5a5, r1 + set_greg 0xa5a5a5a5, r7 + test_grs_a5a5 + pass + exit 0 diff --git a/sim/testsuite/sh/shll2.s b/sim/testsuite/sh/shll2.s new file mode 100644 index 00000000000..01a784c9390 --- /dev/null +++ b/sim/testsuite/sh/shll2.s @@ -0,0 +1,51 @@ +# sh testcase for shll2 +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +shll2: + set_grs_a5a5 + mov #1, r1 + shll2 r1 + assertreg 4, r1 + shll2 r1 + assertreg 16, r1 + shll2 r1 + assertreg 64, r1 + shll2 r1 + assertreg 0x100, r1 + shll2 r1 + assertreg 0x400, r1 + shll2 r1 + assertreg 0x1000, r1 + shll2 r1 + assertreg 0x4000, r1 + shll2 r1 + assertreg 0x10000, r1 + shll2 r1 + assertreg 0x40000, r1 + shll2 r1 + assertreg 0x100000, r1 + shll2 r1 + assertreg 0x400000, r1 + shll2 r1 + assertreg 0x1000000, r1 + shll2 r1 + assertreg 0x4000000, r1 + shll2 r1 + assertreg 0x10000000, r1 + shll2 r1 + assertreg 0x40000000, r1 + shll2 r1 + assertreg 0, r1 + + set_greg 0xa5a5a5a5, r1 + test_grs_a5a5 + + pass + exit 0 + diff --git a/sim/testsuite/sh/shll8.s b/sim/testsuite/sh/shll8.s new file mode 100644 index 00000000000..71e241d1e6b --- /dev/null +++ b/sim/testsuite/sh/shll8.s @@ -0,0 +1,42 @@ +# sh testcase for shll8 +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +shll8: + set_grs_a5a5 + mov #1, r1 + shll8 r1 + assertreg 0x100, r1 + shll8 r1 + assertreg 0x10000, r1 + shll8 r1 + assertreg 0x1000000, r1 + shll8 r1 + assertreg 0, r1 + + # another: + mov #1, r1 + shll8 r1 + mov #1, r2 + shll r2 + shll r2 + shll r2 + shll r2 + shll r2 + shll r2 + shll r2 + shll r2 + cmp/eq r1, r2 + bt okay + fail +okay: + set_greg 0xa5a5a5a5, r1 + set_greg 0xa5a5a5a5, r2 + test_grs_a5a5 + pass + exit 0 diff --git a/sim/testsuite/sh/shlr.s b/sim/testsuite/sh/shlr.s new file mode 100644 index 00000000000..8755afb707f --- /dev/null +++ b/sim/testsuite/sh/shlr.s @@ -0,0 +1,42 @@ +# sh testcase for shlr +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +shlr: + set_grs_a5a5 + mov #0, r0 + or #192, r0 + shlr r0 + assertreg0 96 + shlr r0 + assertreg0 48 + shlr r0 + assertreg0 24 + shlr r0 + assertreg0 12 + shlr r0 + assertreg0 6 + shlr r0 + assertreg0 3 + + # Make sure a bit is shifted into T. + shlr r0 + bf wrong + assertreg0 1 + # Ditto. + shlr r0 + bf wrong + assertreg0 0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + pass + exit 0 + +wrong: + fail diff --git a/sim/testsuite/sh/shlr16.s b/sim/testsuite/sh/shlr16.s new file mode 100644 index 00000000000..1161c6666f9 --- /dev/null +++ b/sim/testsuite/sh/shlr16.s @@ -0,0 +1,20 @@ +# sh testcase for shlr16 +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +shrl16: + set_grs_a5a5 + shlr16 r0 + assertreg0 0xa5a5 + shlr16 r0 + assertreg0 0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + pass + exit 0 diff --git a/sim/testsuite/sh/shlr2.s b/sim/testsuite/sh/shlr2.s new file mode 100644 index 00000000000..ce554dd0f09 --- /dev/null +++ b/sim/testsuite/sh/shlr2.s @@ -0,0 +1,48 @@ +# sh testcase for shlr2 +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +shrl2: + set_grs_a5a5 + shlr2 r0 + assertreg0 0x29696969 + shlr2 r0 + assertreg0 0x0a5a5a5a + shlr2 r0 + assertreg0 0x02969696 + shlr2 r0 + assertreg0 0x00a5a5a5 + shlr2 r0 + assertreg0 0x00296969 + shlr2 r0 + assertreg0 0x000a5a5a + shlr2 r0 + assertreg0 0x00029696 + shlr2 r0 + assertreg0 0x0000a5a5 + shlr2 r0 + assertreg0 0x00002969 + shlr2 r0 + assertreg0 0x00000a5a + shlr2 r0 + assertreg0 0x00000296 + shlr2 r0 + assertreg0 0x000000a5 + shlr2 r0 + assertreg0 0x00000029 + shlr2 r0 + assertreg0 0x0000000a + shlr2 r0 + assertreg0 0x00000002 + shlr2 r0 + assertreg0 0 + + set_greg 0xa5a5a5a5 r0 + test_grs_a5a5 + pass + exit 0 diff --git a/sim/testsuite/sh/shlr8.s b/sim/testsuite/sh/shlr8.s new file mode 100644 index 00000000000..d609af119e3 --- /dev/null +++ b/sim/testsuite/sh/shlr8.s @@ -0,0 +1,24 @@ +# sh testcase for shlr8 +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +shrl8: + set_grs_a5a5 + shlr8 r0 + assertreg0 0xa5a5a5 + shlr8 r0 + assertreg0 0xa5a5 + shlr8 r0 + assertreg0 0xa5 + shlr8 r0 + assertreg0 0x0 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + pass + exit 0 diff --git a/sim/testsuite/sh/swap.s b/sim/testsuite/sh/swap.s new file mode 100644 index 00000000000..4dd6572695c --- /dev/null +++ b/sim/testsuite/sh/swap.s @@ -0,0 +1,59 @@ +# sh testcase for swap +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +swapb: + set_grs_a5a5 + mov #0x5a, r0 + shll8 r0 + or #0xa5, r0 + assertreg0 0x5aa5 + + swap.b r0, r1 + assertreg 0xa55a, r1 + + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +swapw: + set_grs_a5a5 + mov #0x5a, r0 + shll16 r0 + or #0xa5, r0 + assertreg0 0x5a00a5 + + swap.w r0, r1 + assertreg 0xa5005a, r1 + + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + exit 0 diff --git a/sim/testsuite/sh/testutils.inc b/sim/testsuite/sh/testutils.inc new file mode 100644 index 00000000000..c9644b40f8c --- /dev/null +++ b/sim/testsuite/sh/testutils.inc @@ -0,0 +1,617 @@ +# Support macros for the sh assembly test cases. + + .equ no_dsp, 0 + .equ yes_dsp, 1 + + .section .rodata + .align 2 +_pass: .string "pass\n" +_fail: .string "fail\n" +_stack: .fill 128, 4, 0 +stackt: + + .macro push reg + mov.l \reg, @-r15 + .endm + + .macro pop reg + mov.l @r15+, \reg + .endm + + .macro start + .text + .align 1 + .global start +start: mov.l stackp, r15 + bra main + nop + .align 2 +stackp: .long stackt +mpass: + mov #4, r4 + mov #1, r5 + mov.l ppass, r6 + mov #5, r7 + trapa #34 + rts + nop +mfail: + mov #4, r4 + mov #1, r5 + mov.l pfail, r6 + mov #5, r7 + trapa #34 + mov #1, r5 +mexit: + mov #1, r4 + mov #0, r6 + mov #0, r7 + trapa #34 + .align 2 +ppass: .long _pass +pfail: .long _fail + +mtesta5: + push r0 + mov.l a5a5, r0 + cmp/eq r1, r0 + bf mfail + cmp/eq r2, r0 + bf mfail + cmp/eq r3, r0 + bf mfail + cmp/eq r4, r0 + bf mfail + cmp/eq r5, r0 + bf mfail + cmp/eq r6, r0 + bf mfail + cmp/eq r7, r0 + bf mfail + cmp/eq r8, r0 + bf mfail + cmp/eq r9, r0 + bf mfail + cmp/eq r10, r0 + bf mfail + cmp/eq r11, r0 + bf mfail + cmp/eq r12, r0 + bf mfail + cmp/eq r13, r0 + bf mfail + cmp/eq r14, r0 + bf mfail + # restore and check r0 + pop r0 + cmp/eq r0, r1 + bf mfail + # pass + rts + nop +.if (sim_cpu == no_dsp) +mtesta5_fp: + push r0 + flds fr0, fpul + sts fpul, r0 + push r0 + mov.l a5a5, r0 + lds r0, fpul + fsts fpul, fr0 + fcmp/eq fr1, fr0 + bf mfail + fcmp/eq fr2, fr0 + bf mfail + fcmp/eq fr3, fr0 + bf mfail + fcmp/eq fr4, fr0 + bf mfail + fcmp/eq fr5, fr0 + bf mfail + fcmp/eq fr6, fr0 + bf mfail + fcmp/eq fr7, fr0 + bf mfail + fcmp/eq fr8, fr0 + bf mfail + fcmp/eq fr9, fr0 + bf mfail + fcmp/eq fr10, fr0 + bf mfail + fcmp/eq fr11, fr0 + bf mfail + fcmp/eq fr12, fr0 + bf mfail + fcmp/eq fr13, fr0 + bf mfail + fcmp/eq fr14, fr0 + bf mfail + fcmp/eq fr15, fr0 + bf mfail + # restore and check fr0 + pop r0 + lds r0, fpul + fsts fpul, fr0 + fcmp/eq fr0, fr1 + bf mfail + # restore r0 and pass + pop r0 + rts + nop +.endif + +mseta5: + mov.l a5a5, r0 + mov.l a5a5, r1 + mov.l a5a5, r2 + mov.l a5a5, r3 + mov.l a5a5, r4 + mov.l a5a5, r5 + mov.l a5a5, r6 + mov.l a5a5, r7 + mov.l a5a5, r8 + mov.l a5a5, r9 + mov.l a5a5, r10 + mov.l a5a5, r11 + mov.l a5a5, r12 + mov.l a5a5, r13 + mov.l a5a5, r14 + rts + nop + +.if (sim_cpu == no_dsp) +mseta5_fp: + push r0 + mov.l a5a5, r0 + lds r0, fpul + fsts fpul, fr0 + fsts fpul, fr1 + fsts fpul, fr2 + fsts fpul, fr3 + fsts fpul, fr4 + fsts fpul, fr5 + fsts fpul, fr6 + fsts fpul, fr7 + fsts fpul, fr8 + fsts fpul, fr9 + fsts fpul, fr10 + fsts fpul, fr11 + fsts fpul, fr12 + fsts fpul, fr13 + fsts fpul, fr14 + fsts fpul, fr15 + pop r0 + rts + nop +.endif + + .align 2 +a5a5: .long 0xa5a5a5a5 +main: + .endm + + .macro exit val + mov #\val, r5 + bra mexit + nop + .endm + + .macro pass + bsr mpass + nop + .endm + + .macro fail + bra mfail + nop + .endm + # Branch if false -- 8k range + .macro bf8k label + bt .Lbf8k\@ + bra \label +.Lbf8k\@: + .endm + + # Branch if true -- 8k range + .macro bt8k label + bf .Lbt8k\@ + bra \label +.Lbt8k\@: + .endm + + # Assert value of register (any general register but r0) + # Preserves r0 on stack, restores it on success. + .macro assertreg val reg + push r0 + mov.l .Larval\@, r0 + cmp/eq r0, \reg + bt .Lar\@ + fail + .align 2 +.Larval\@: + .long \val +.Lar\@: pop r0 + .endm + + # Assert value of register zero + # Preserves r1 on stack, restores it on success. + .macro assertreg0 val + push r1 + mov.l .Lazval\@, r1 + cmp/eq r1, r0 + bt .Laz\@ + fail + .align 2 +.Lazval\@: + .long \val +.Laz\@: pop r1 + .endm + + # Assert value of system register + # [mach, macl, pr, dsr, a0, x0, x1, y0, y1, ...] + .macro assert_sreg val reg + push r0 + sts \reg, r0 + assertreg0 \val + pop r0 + .endm + + # Assert value of system register that isn't directly stc-able + # [a1, m0, m1, ...] + .macro assert_sreg2 val reg + push r0 + sts a0, r0 + push r0 + pcopy \reg, a0 + sts a0, r0 + assertreg0 \val + pop r0 + lds r0, a0 + pop r0 + .endm + + # Assert value of control register + # [gbr, vbr, ssr, spc, sgr, dbr, r[0-7]_bank, sr, mod, re, rs, ...] + .macro assert_creg val reg + push r0 + stc \reg, r0 + assertreg0 \val + pop r0 + .endm + + # Assert integer value of fp register + # Preserves r0 on stack, restores it on success + # Assumes single-precision fp mode + .macro assert_fpreg_i val freg + push r0 + ftrc \freg, fpul + sts fpul, r0 + assertreg0 \val + pop r0 + .endm + + # Assert integer value of dp register + # Preserves r0 on stack, restores it on success + # Assumes double-precision fp mode + .macro assert_dpreg_i val dreg + push r0 + ftrc \dreg, fpul + sts fpul, r0 + assertreg0 \val + pop r0 + .endm + + # Assert hex value of fp register + # Preserves r0 on stack, restores it on success + # Assumes single-precision fp mode + .macro assert_fpreg_x val freg + push r0 + flds \freg, fpul + sts fpul, r0 + assertreg0 \val + pop r0 + .endm + + # Set FP bank 0 + # Saves and restores r0 and r1 + .macro bank0 + push r0 + push r1 + mov #32, r1 + shll16 r1 + not r1, r1 + sts fpscr, r0 + and r1, r0 + lds r0, fpscr + pop r1 + pop r0 + .endm + + # Set FP bank 1 + .macro bank1 + push r0 + push r1 + mov #32, r1 + shll16 r1 + sts fpscr, r0 + or r1, r0 + lds r0, fpscr + pop r1 + pop r0 + .endm + + # Set FP 32-bit xfer + .macro sz_32 + push r0 + push r1 + mov #16, r1 + shll16 r1 + not r1, r1 + sts fpscr, r0 + and r1, r0 + lds r0, fpscr + pop r1 + pop r0 + .endm + + # Set FP 64-bit xfer + .macro sz_64 + push r0 + push r1 + mov #16, r1 + shll16 r1 + sts fpscr, r0 + or r1, r0 + lds r0, fpscr + pop r1 + pop r0 + .endm + + # Set FP single precision + .macro single_prec + push r0 + push r1 + mov #8, r1 + shll16 r1 + not r1, r1 + sts fpscr, r0 + and r1, r0 + lds r0, fpscr + pop r1 + pop r0 + .endm + + # Set FP double precision + .macro double_prec + push r0 + push r1 + mov #8, r1 + shll16 r1 + sts fpscr, r0 + or r1, r0 + lds r0, fpscr + pop r1 + pop r0 + .endm + + .macro set_carry + sett + .endm + + .macro set_ovf + sett + .endm + + .macro clear_carry + clrt + .endm + + .macro clear_ovf + clrt + .endm + + # sets, clrs + + + .macro set_grs_a5a5 + bsr mseta5 + nop + .endm + + .macro set_greg val greg + mov.l gregval\@, \greg + bra set_greg\@ + nop + .align 2 +gregval\@: .long \val +set_greg\@: + .endm + + .macro set_fprs_a5a5 + bsr mseta5_fp + nop + .endm + + .macro test_grs_a5a5 + bsr mtesta5 + nop + .endm + + .macro test_fprs_a5a5 + bsr mtesta5_fp + nop + .endm + + .macro test_gr_a5a5 reg + assertreg 0xa5a5a5a5 \reg + .endm + + .macro test_fpr_a5a5 reg + assert_fpreg_x 0xa5a5a5a5 \reg + .endm + + .macro test_gr0_a5a5 + assertreg0 0xa5a5a5a5 + .endm + + # Perform a single to double precision floating point conversion. + # Assumes correct settings of fpscr. + .macro _s2d fpr dpr + flds \fpr, fpul + fcnvsd fpul, \dpr + .endm + + # Manipulate the status register + .macro set_sr val + push r0 + mov.l .Lsrval\@, r0 + ldc r0, sr + pop r0 + bra .Lsetsr\@ + nop + .align 2 +.Lsrval\@: + .long \val +.Lsetsr\@: + .endm + + .macro get_sr reg + stc sr, \reg + .endm + + .macro test_sr val + push r0 + get_sr r0 + assertreg0 \val + pop r0 + .endm + + .macro set_sr_bit val + push r0 + push r1 + get_sr r0 + mov.l .Lsrbitval\@, r1 + or r1, r0 + ldc r0, sr + pop r1 + pop r0 + bra .Lsrbit\@ + nop + .align 2 +.Lsrbitval\@: + .long \val +.Lsrbit\@: + .endm + + .macro test_sr_bit_set val + push r0 + push r1 + get_sr r0 + mov.l .Ltsbsval\@, r1 + tst r1, r0 + bf .Ltsbs\@ + fail + .align 2 +.Ltsbsval\@: + .long \val +.Ltsbs\@: + pop r1 + pop r0 + .endm + + .macro test_sr_bit_clear val + push r0 + push r1 + get_sr r0 + mov.l .Ltsbcval\@, r1 + not r0, r0 + tst r1, r0 + bf .Ltsbc\@ + fail + .align 2 +.Ltsbcval\@: + .long \val +.Ltsbc\@: + pop r1 + pop r0 + .endm + + # Set system registers + .macro set_sreg val reg + # [mach, macl, pr, dsr, a0, x0, x1, y0, y1, ...] + push r0 + mov.l .Lssrval\@, r0 + lds r0, \reg + pop r0 + bra .Lssr\@ + nop + .align 2 +.Lssrval\@: + .long \val +.Lssr\@: + .endm + + .macro set_sreg2 val reg + # [a1, m0, m1, ...] + push r0 + sts a0, r0 + push r0 + mov.l .Lssr2val\@, r0 + lds r0, a0 + pcopy a0, \reg + pop r0 + lds r0, a0 + pop r0 + bra .Lssr2_\@ + nop + .align 2 +.Lssr2val\@: + .long \val +.Lssr2_\@: + .endm + + + .macro set_creg val reg + # [gbr, vbr, ssr, spc, sgr, dbr... ] + push r0 + mov.l .Lscrval\@, r0 + ldc r0, \reg + pop r0 + bra .Lscr\@ + nop + .align 2 +.Lscrval\@: + .long \val +.Lscr\@: + .endm + + .macro set_dctrue + push r0 + sts dsr, r0 + or #1, r0 + lds r0, dsr + pop r0 + .endm + + .macro set_dcfalse + push r0 + sts dsr, r0 + not r0, r0 + or #1, r0 + not r0, r0 + lds r0, dsr + pop r0 + .endm + + .macro assertmem addr val + push r0 + mov.l .Laddr\@, r0 + mov.l @r0, r0 + assertreg0 \val + bra .Lam\@ + nop + .align 2 +.Laddr\@: + .long \addr +.Lam\@: pop r0 + .endm |