diff options
Diffstat (limited to 'sim/testsuite/bfin/c_dsp32shift_align16.s')
-rw-r--r-- | sim/testsuite/bfin/c_dsp32shift_align16.s | 210 |
1 files changed, 210 insertions, 0 deletions
diff --git a/sim/testsuite/bfin/c_dsp32shift_align16.s b/sim/testsuite/bfin/c_dsp32shift_align16.s new file mode 100644 index 00000000000..a6fd2841036 --- /dev/null +++ b/sim/testsuite/bfin/c_dsp32shift_align16.s @@ -0,0 +1,210 @@ +//Original:/testcases/core/c_dsp32shift_align16/c_dsp32shift_align16.dsp +// Spec Reference: dsp32shift align16 +# mach: bfin + +.include "testutils.inc" + start + +imm32 r0, 0x00000001; +imm32 r1, 0x01000801; +imm32 r2, 0x08200802; +imm32 r3, 0x08030803; +imm32 r4, 0x08004804; +imm32 r5, 0x08000505; +imm32 r6, 0x08000866; +imm32 r7, 0x08000807; +R1 = ALIGN16 ( R1 , R0 ); +R2 = ALIGN16 ( R2 , R0 ); +R3 = ALIGN16 ( R3 , R0 ); +R4 = ALIGN16 ( R4 , R0 ); +R5 = ALIGN16 ( R5 , R0 ); +R6 = ALIGN16 ( R6 , R0 ); +R7 = ALIGN16 ( R7 , R0 ); +R0 = ALIGN16 ( R0 , R0 ); +CHECKREG r0, 0x00010000; +CHECKREG r1, 0x08010000; +CHECKREG r2, 0x08020000; +CHECKREG r3, 0x08030000; +CHECKREG r4, 0x48040000; +CHECKREG r5, 0x05050000; +CHECKREG r6, 0x08660000; +CHECKREG r7, 0x08070000; + +imm32 r0, 0x0900d001; +imm32 r1, 0x09000002; +imm32 r2, 0x09400002; +imm32 r3, 0x09100003; +imm32 r4, 0x09020004; +imm32 r5, 0x09003005; +imm32 r6, 0x09000406; +imm32 r7, 0x09000057; +R0 = ALIGN16 ( R0 , R1 ); +R2 = ALIGN16 ( R2 , R1 ); +R3 = ALIGN16 ( R3 , R1 ); +R4 = ALIGN16 ( R4 , R1 ); +R5 = ALIGN16 ( R5 , R1 ); +R6 = ALIGN16 ( R6 , R1 ); +R7 = ALIGN16 ( R7 , R1 ); +R1 = ALIGN16 ( R1 , R1 ); +CHECKREG r0, 0xD0010900; +CHECKREG r1, 0x00020900; +CHECKREG r2, 0x00020900; +CHECKREG r3, 0x00030900; +CHECKREG r4, 0x00040900; +CHECKREG r5, 0x30050900; +CHECKREG r6, 0x04060900; +CHECKREG r7, 0x00570900; + + +imm32 r0, 0x0a00e001; +imm32 r1, 0x0a00e001; +imm32 r2, 0x0a00000f; +imm32 r3, 0x0a400010; +imm32 r4, 0x0a05e004; +imm32 r5, 0x0a006005; +imm32 r6, 0x0a00e706; +imm32 r7, 0x0a00e087; +R0 = ALIGN16 ( R0 , R2 ); +R1 = ALIGN16 ( R1 , R2 ); +R3 = ALIGN16 ( R3 , R2 ); +R4 = ALIGN16 ( R4 , R2 ); +R5 = ALIGN16 ( R5 , R2 ); +R6 = ALIGN16 ( R6 , R2 ); +R7 = ALIGN16 ( R7 , R2 ); +R2 = ALIGN16 ( R2 , R2 ); +CHECKREG r0, 0xE0010A00; +CHECKREG r1, 0xE0010A00; +CHECKREG r2, 0x000F0A00; +CHECKREG r3, 0x00100A00; +CHECKREG r4, 0xE0040A00; +CHECKREG r5, 0x60050A00; +CHECKREG r6, 0xE7060A00; +CHECKREG r7, 0xE0870A00; + +imm32 r0, 0x2b00f001; +imm32 r1, 0x0300f001; +imm32 r2, 0x0b40f002; +imm32 r3, 0x0b050010; +imm32 r4, 0x0b006004; +imm32 r5, 0x0b00f705; +imm32 r6, 0x0b00f086; +imm32 r7, 0x0b00f009; +R0 = ALIGN16 ( R0 , R3 ); +R1 = ALIGN16 ( R1 , R3 ); +R2 = ALIGN16 ( R2 , R3 ); +R4 = ALIGN16 ( R4 , R3 ); +R5 = ALIGN16 ( R5 , R3 ); +R6 = ALIGN16 ( R6 , R3 ); +R7 = ALIGN16 ( R7 , R3 ); +R3 = ALIGN16 ( R3 , R3 ); +CHECKREG r0, 0xF0010B05; +CHECKREG r1, 0xF0010B05; +CHECKREG r2, 0xF0020B05; +CHECKREG r3, 0x00100B05; +CHECKREG r4, 0x60040B05; +CHECKREG r5, 0xF7050B05; +CHECKREG r6, 0xF0860B05; +CHECKREG r7, 0xF0090B05; + +imm32 r0, 0x4c0000c0; +imm32 r1, 0x050100c0; +imm32 r2, 0x0c6200c0; +imm32 r3, 0x0c0700c0; +imm32 r4, 0x0c04800c; +imm32 r5, 0x0c0509c0; +imm32 r6, 0x0c060000; +imm32 r7, 0x0c0700ca; +R0 = ALIGN16 ( R0 , R4 ); +R1 = ALIGN16 ( R1 , R4 ); +R2 = ALIGN16 ( R2 , R4 ); +R3 = ALIGN16 ( R3 , R4 ); +R5 = ALIGN16 ( R5 , R4 ); +R6 = ALIGN16 ( R6 , R4 ); +R7 = ALIGN16 ( R7 , R4 ); +R4 = ALIGN16 ( R4 , R4 ); +CHECKREG r0, 0x00C00C04; +CHECKREG r1, 0x00C00C04; +CHECKREG r2, 0x00C00C04; +CHECKREG r3, 0x00C00C04; +CHECKREG r4, 0x800C0C04; +CHECKREG r5, 0x09C00C04; +CHECKREG r6, 0x00000C04; +CHECKREG r7, 0x00CA0C04; + +imm32 r0, 0xa00100d0; +imm32 r1, 0xa00100d1; +imm32 r2, 0xa00200d0; +imm32 r3, 0xa00300d0; +imm32 r4, 0xa00400d0; +imm32 r5, 0xa0050007; +imm32 r6, 0xa00600d0; +imm32 r7, 0xa00700d0; +R0 = ALIGN16 ( R0 , R5 ); +R1 = ALIGN16 ( R1 , R5 ); +R2 = ALIGN16 ( R2 , R5 ); +R3 = ALIGN16 ( R3 , R5 ); +R4 = ALIGN16 ( R4 , R5 ); +R6 = ALIGN16 ( R6 , R5 ); +R7 = ALIGN16 ( R7 , R5 ); +R5 = ALIGN16 ( R5 , R5 ); +CHECKREG r0, 0x00D0A005; +CHECKREG r1, 0x00D1A005; +CHECKREG r2, 0x00D0A005; +CHECKREG r3, 0x00D0A005; +CHECKREG r4, 0x00D0A005; +CHECKREG r5, 0x0007A005; +CHECKREG r6, 0x00D0A005; +CHECKREG r7, 0x00D0A005; + +imm32 r0, 0xb2010000; +imm32 r1, 0xb0310000; +imm32 r2, 0xb042000f; +imm32 r3, 0xbf030000; +imm32 r4, 0xba040000; +imm32 r5, 0xbb050000; +imm32 r6, 0xbc060009; +imm32 r7, 0xb0e70000; +R0 = ALIGN16 ( R0 , R6 ); +R1 = ALIGN16 ( R1 , R6 ); +R2 = ALIGN16 ( R2 , R6 ); +R3 = ALIGN16 ( R3 , R6 ); +R4 = ALIGN16 ( R4 , R6 ); +R5 = ALIGN16 ( R5 , R6 ); +R6 = ALIGN16 ( R6 , R6 ); +R7 = ALIGN16 ( R7 , R6 ); +CHECKREG r0, 0x0000BC06; +CHECKREG r1, 0x0000BC06; +CHECKREG r2, 0x000FBC06; +CHECKREG r3, 0x0000BC06; +CHECKREG r4, 0x0000BC06; +CHECKREG r5, 0x0000BC06; +CHECKREG r6, 0x0009BC06; +CHECKREG r7, 0x00000009; + +imm32 r0, 0xd23100e0; +imm32 r1, 0xd04500e0; +imm32 r2, 0xde32f0e0; +imm32 r3, 0xd90300e0; +imm32 r4, 0xd07400e0; +imm32 r5, 0xdef500e0; +imm32 r6, 0xd06600e0; +imm32 r7, 0xd0080023; +R1 = ALIGN16 ( R0 , R7 ); +R2 = ALIGN16 ( R1 , R7 ); +R3 = ALIGN16 ( R2 , R7 ); +R4 = ALIGN16 ( R3 , R7 ); +R5 = ALIGN16 ( R4 , R7 ); +R6 = ALIGN16 ( R5 , R7 ); +R7 = ALIGN16 ( R6 , R7 ); +R0 = ALIGN16 ( R7 , R7 ); +CHECKREG r0, 0xD008D008; +CHECKREG r1, 0x00E0D008; +CHECKREG r2, 0xD008D008; +CHECKREG r3, 0xD008D008; +CHECKREG r4, 0xD008D008; +CHECKREG r5, 0xD008D008; +CHECKREG r6, 0xD008D008; +CHECKREG r7, 0xD008D008; + + +pass |