diff options
Diffstat (limited to 'sim/testsuite/bfin/c_alu2op_conv_xb.s')
| -rw-r--r-- | sim/testsuite/bfin/c_alu2op_conv_xb.s | 211 |
1 files changed, 211 insertions, 0 deletions
diff --git a/sim/testsuite/bfin/c_alu2op_conv_xb.s b/sim/testsuite/bfin/c_alu2op_conv_xb.s new file mode 100644 index 00000000000..779a790dbee --- /dev/null +++ b/sim/testsuite/bfin/c_alu2op_conv_xb.s @@ -0,0 +1,211 @@ +//Original:/testcases/core/c_alu2op_conv_xb/c_alu2op_conv_xb.dsp +// Spec Reference: alu2op convert xb +# mach: bfin + +.include "testutils.inc" + start + + + +imm32 r0, 0x00789abc; +imm32 r1, 0x12345678; +imm32 r2, 0x23456789; +imm32 r3, 0x3456789a; +imm32 r4, 0x856789ab; +imm32 r5, 0x96789abc; +imm32 r6, 0xa789abcd; +imm32 r7, 0xb89abcde; +R0 = R0.B (X); +R1 = R0.B (X); +R2 = R0.B (X); +R3 = R0.B (X); +R4 = R0.B (X); +R5 = R0.B (X); +R6 = R0.B (X); +R7 = R0.B (X); +CHECKREG r0, 0xFFFFFFBC; +CHECKREG r1, 0xFFFFFFBC; +CHECKREG r2, 0xFFFFFFBC; +CHECKREG r3, 0xFFFFFFBC; +CHECKREG r4, 0xFFFFFFBC; +CHECKREG r5, 0xFFFFFFBC; +CHECKREG r6, 0xFFFFFFBC; +CHECKREG r7, 0xFFFFFFBC; + +imm32 r0, 0x01230002; +imm32 r1, 0x00374659; +imm32 r2, 0x93456789; +imm32 r3, 0xa456789a; +imm32 r4, 0xb56789ab; +imm32 r5, 0xc6789abc; +imm32 r6, 0xd789abcd; +imm32 r7, 0xe89abcde; +R0 = R1.B (X); +R2 = R1.B (X); +R3 = R1.B (X); +R4 = R1.B (X); +R5 = R1.B (X); +R6 = R1.B (X); +R7 = R1.B (X); +R1 = R1.B (X); +CHECKREG r0, 0x00000059; +CHECKREG r1, 0x00000059; +CHECKREG r2, 0x00000059; +CHECKREG r3, 0x00000059; +CHECKREG r4, 0x00000059; +CHECKREG r5, 0x00000059; +CHECKREG r6, 0x00000059; +CHECKREG r7, 0x00000059; + +imm32 r0, 0x10789abc; +imm32 r1, 0x11345678; +imm32 r2, 0x93156789; +imm32 r3, 0xd451789a; +imm32 r4, 0x856719ab; +imm32 r5, 0x267891bc; +imm32 r6, 0xa789ab1d; +imm32 r7, 0x989ab1de; +R0 = R2.B (X); +R1 = R2.B (X); +R3 = R2.B (X); +R4 = R2.B (X); +R5 = R2.B (X); +R6 = R2.B (X); +R7 = R2.B (X); +R2 = R2.B (X); +CHECKREG r0, 0xFFFFFF89; +CHECKREG r1, 0xFFFFFF89; +CHECKREG r2, 0xFFFFFF89; +CHECKREG r3, 0xFFFFFF89; +CHECKREG r4, 0xFFFFFF89; +CHECKREG r5, 0xFFFFFF89; +CHECKREG r6, 0xFFFFFF89; +CHECKREG r7, 0xFFFFFF89; + +imm32 r0, 0x21230002; +imm32 r1, 0x02374659; +imm32 r2, 0x93256789; +imm32 r3, 0xa952789a; +imm32 r4, 0xb59729ab; +imm32 r5, 0xc67992bc; +imm32 r6, 0xd7899b2d; +imm32 r7, 0xe89ab9d2; +R0 = R3.B (X); +R1 = R3.B (X); +R2 = R3.B (X); +R4 = R3.B (X); +R5 = R3.B (X); +R6 = R3.B (X); +R7 = R3.B (X); +R3 = R3.B (X); +CHECKREG r0, 0xFFFFFF9A; +CHECKREG r1, 0xFFFFFF9A; +CHECKREG r2, 0xFFFFFF9A; +CHECKREG r3, 0xFFFFFF9A; +CHECKREG r4, 0xFFFFFF9A; +CHECKREG r5, 0xFFFFFF9A; +CHECKREG r6, 0xFFFFFF9A; +CHECKREG r7, 0xFFFFFF9A; + +imm32 r0, 0xa0789abc; +imm32 r1, 0x1a345678; +imm32 r2, 0x23a56789; +imm32 r3, 0x645a789a; +imm32 r4, 0x8667a9ab; +imm32 r5, 0x96689abc; +imm32 r6, 0xa787abad; +imm32 r7, 0xb89a7cda; +R0 = R4.B (X); +R1 = R4.B (X); +R2 = R4.B (X); +R3 = R4.B (X); +R4 = R4.B (X); +R5 = R4.B (X); +R6 = R4.B (X); +R7 = R4.B (X); +CHECKREG r0, 0xFFFFFFAB; +CHECKREG r1, 0xFFFFFFAB; +CHECKREG r2, 0xFFFFFFAB; +CHECKREG r3, 0xFFFFFFAB; +CHECKREG r4, 0xFFFFFFAB; +CHECKREG r5, 0xFFFFFFAB; +CHECKREG r6, 0xFFFFFFAB; +CHECKREG r7, 0xFFFFFFAB; + +imm32 r0, 0xf1230002; +imm32 r1, 0x0f374659; +imm32 r2, 0x93f56789; +imm32 r3, 0xa45f789a; +imm32 r4, 0xb567f9ab; +imm32 r5, 0xc6789fbc; +imm32 r6, 0xd789abfd; +imm32 r7, 0xe89abcdf; +R0 = R5.B (X); +R1 = R5.B (X); +R2 = R5.B (X); +R3 = R5.B (X); +R4 = R5.B (X); +R6 = R5.B (X); +R7 = R5.B (X); +R5 = R5.B (X); +CHECKREG r0, 0xFFFFFFBC; +CHECKREG r1, 0xFFFFFFBC; +CHECKREG r2, 0xFFFFFFBC; +CHECKREG r3, 0xFFFFFFBC; +CHECKREG r4, 0xFFFFFFBC; +CHECKREG r5, 0xFFFFFFBC; +CHECKREG r6, 0xFFFFFFBC; +CHECKREG r7, 0xFFFFFFBC; + +imm32 r0, 0xe0789abc; +imm32 r1, 0xe2345678; +imm32 r2, 0x2e456789; +imm32 r3, 0x34e6789a; +imm32 r4, 0x856e89ab; +imm32 r5, 0x9678eabc; +imm32 r6, 0xa789aecd; +imm32 r7, 0xb89abcee; +R0 = R6.B (X); +R1 = R6.B (X); +R2 = R6.B (X); +R3 = R6.B (X); +R4 = R6.B (X); +R5 = R6.B (X); +R7 = R6.B (X); +R6 = R6.B (X); +CHECKREG r0, 0xFFFFFFCD; +CHECKREG r1, 0xFFFFFFCD; +CHECKREG r2, 0xFFFFFFCD; +CHECKREG r3, 0xFFFFFFCD; +CHECKREG r4, 0xFFFFFFCD; +CHECKREG r5, 0xFFFFFFCD; +CHECKREG r6, 0xFFFFFFCD; +CHECKREG r7, 0xFFFFFFCD; + +imm32 r0, 0x012300f5; +imm32 r1, 0x80374659; +imm32 r2, 0x98456589; +imm32 r3, 0xa486589a; +imm32 r4, 0xb56589ab; +imm32 r5, 0xc6588abc; +imm32 r6, 0xd589a8cd; +imm32 r7, 0x589abc88; +R0 = R7.B (X); +R1 = R7.B (X); +R2 = R7.B (X); +R3 = R7.B (X); +R4 = R7.B (X); +R5 = R7.B (X); +R6 = R7.B (X); +R7 = R7.B (X); +CHECKREG r0, 0xFFFFFF88; +CHECKREG r1, 0xFFFFFF88; +CHECKREG r2, 0xFFFFFF88; +CHECKREG r3, 0xFFFFFF88; +CHECKREG r4, 0xFFFFFF88; +CHECKREG r5, 0xFFFFFF88; +CHECKREG r6, 0xFFFFFF88; +CHECKREG r7, 0xFFFFFF88; + + +pass |