diff options
Diffstat (limited to 'sim/d30v/ChangeLog')
| -rw-r--r-- | sim/d30v/ChangeLog | 1333 |
1 files changed, 1333 insertions, 0 deletions
diff --git a/sim/d30v/ChangeLog b/sim/d30v/ChangeLog new file mode 100644 index 00000000000..668d89e6750 --- /dev/null +++ b/sim/d30v/ChangeLog @@ -0,0 +1,1333 @@ +1999-01-12 Frank Ch. Eigler <fche@cygnus.com> + + * engine.c (unqueue_writes): Make PSW conflict resolution code + conditional - disable it for MVTSYS || insn case. + +1999-01-11 Frank Ch. Eigler <fche@cygnus.com> + + * d30v-insns (do_sath): Drain PSW write queue before PSW_S_FLAG + update. + * engine.c (unqueue_writes): Make non-static. Remove PSW_V/VA + special case. + (do_parallel): Don't drain PSW write queue for MVTSYS || insn. + +1999-01-07 Frank Ch. Eigler <fche@cygnus.com> + + * d30v-insns (do_ld2h): Sign-extend loaded half-words. + +1999-01-05 Frank Ch. Eigler <fche@cygnus.com> + + * d30v-insns (do_ld2h): Read memory in word units. + (do_ld4bh): Ditto. Correct sign extension. + (do_ld4bhu): Ditto. + (do_st2h): Write memory in word units. + (do_st4hb): Ditto. + (st4hb): Correct mnemonic in igen template. + +1998-12-08 Frank Ch. Eigler <fche@cygnus.com> + + * d30v-insns: (do_ld2h): Don't update R0 nor R1 for double-word insn. + (do_ld2w): Ditto. + (do_ld4bh): Ditto. + (do_ld4bhu): Ditto. + (do_mulx2h): Ditto. + +1998-12-03 Frank Ch. Eigler <fche@cygnus.com> + + * d30v-insns (do_repeat): Don't set RP for repeat count 1. + +1998-12-03 Frank Ch. Eigler <fche@cygnus.com> + + * d30v-insns (do_src): Treat shift count -32 naturally instead of + producing zero result. + +1998-11-22 Frank Ch. Eigler <fche@cygnus.com> + + * d30v-insns (do_src): Limit SRC shift count to -32 .. 31. + +1998-11-16 Frank Ch. Eigler <fche@cygnus.com> + + * d30v-insns (dbt): Defer PSW/DPSW update with new DID_TRAP code 2. + * engine.c (unqueue_writes): Perform DBT processing on PSW/DPSW here. + +1998-11-12 Frank Ch. Eigler <fche@cygnus.com> + + * cpu.h (_sim_cpu): Removed is_delayed_call field, and associated + RPT_IS_CALL macro. + * sim-calls.c (sim_create_inferior): Don't initialize is_delayed_call. + * d30v-insns (do_dbra): Don't clear RPT_IS_CALL. (do_dbrai): Ditto. + (do_djmp): Ditto. (do_djmpi): Ditto. (do_repeat): Ditto. + * d30v-insns (do_dbsr): Don't set RPT_IS_CALL, but set R62 instead. + (do_dbsri): Ditto. (do_djsr): Dito. (do_djsri): Ditto. + * engine.c (sim_engine_run): Remove conditional setting of R62 based + upon RPT_IS_CALL. + +1998-11-08 Frank Ch. Eigler <fche@cygnus.com> + + * sim-calls.c (sim_open): Add dummy memory range over control + register region (0x40000000..0x4000FFFF). + +1998-11-06 Frank Ch. Eigler <fche@cygnus.com> + + * d30v-insns (do_mvfacc): Use loop to limit shift count to 63 .. 0. + +Tue Oct 13 11:01:16 1998 Frank Ch. Eigler <fche@cygnus.com> + + * d30v-insns (do_sra,do_srah,do_srl,do_srlh): Make shift + count -32 to produce zero result. + (do_src): Ditto for shift count == -64. + +Mon Oct 12 23:04:11 1998 Frank Ch. Eigler <fche@cygnus.com> + + * d30v-insns (ROT): Use 0x1f bit mask for rotate count masking. + (do_sra,do_srl): Use loop to limit shift count to -32 .. 31. + (do_srah,do_srlh): Use loop to limit shift count to -32 .. 31. + (sra2h,srl2h): Use loop to limit shift count to -16 .. 15. + (do_src): Use loop to limit shift count to -64 .. 63. + +Fri Oct 9 16:46:52 1998 Doug Evans <devans@canuck.cygnus.com> + + * sim-calls.c (get_insn_name): New fn. + (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS. + * sim-main.h (MAX_INSNS,INSN_NAME): Delete. + +Mon Sep 28 10:43:28 1998 Frank Ch. Eigler <fche@cygnus.com> + + * d30v-insns (do_sra,do_srah,do_srl,do_srlh,ROT,do_src): Use + correct MSB bit numbers for sign extension masks. + +Fri Sep 25 17:32:27 1998 Frank Ch. Eigler <fche@cygnus.com> + + * engine.c (do_parallel): Unqueue writes if MU instruction was + a MVTSYS, as identified by its left_kills_right_p side-effect. + +Fri Sep 25 12:31:34 1998 Frank Ch. Eigler <fche@cygnus.com> + + * d30v-insns (do_sra,do_srah,do_srl,do_srlh,ROT,do_src): Mask + shift/rotate counts to number of bits in width of operand; no + longer saturate at maxima. + +Tue Jul 14 18:39:23 1998 Frank Ch. Eigler <fche@cygnus.com> + + * cpu.h (left_kills_right_p): New flag for non-branch instructions + that, when executed in left slot of a -> sequential pair, kill the + right slot. + * d30v-insns (mvtsys): Set flag for PSW/PSWh/PSWl/FLAG operands. + * engine.c (do_2_short): Respect flag. + +Thu Jun 4 16:48:58 1998 David Taylor <taylor@texas.cygnus.com> + + * d30v-insns (do_trap): don't save the bPSW and PSW based on + current values because an instruction done in parallel with + the trap might change them, instead set a flag do that + unqueue_writes will take care of it. + * engine.c (unqueue_writes): finish trap handling + * cpu.h (_sim_cpu): add new field did_trap and a macro DID_TRAP + to make use of it; set by do_trap, tested and cleared by + unqueue_writes. + +Tue May 19 16:07:04 1998 Frank Ch. Eigler <fche@cygnus.com> + + * engine.c (unqueue_writes): Suppress the all enqueued writes to + the same flags in PSW except the last. + +Fri May 15 11:38:59 1998 Frank Ch. Eigler <fche@cygnus.com> + + * d30v-insns (RETI): Correct instruction spelling to "reit". + +Thu May 14 09:34:20 1998 Frank Ch. Eigler <fche@cygnus.com> + + * d30v-insns (dbt): Handle DBT at end of repeat block. + (do_trap, dbt): Clear PSW_RP if at end of repeat block. + +Thu May 14 07:41:41 1998 Frank Ch. Eigler <fche@cygnus.com> + + * engine.c (sim_engine_run): Trigger DDBT based on previous PC, + instead of next PC. + +Wed May 13 11:03:40 1998 Frank Ch. Eigler <fche@cygnus.com> + + * engine.c (sim_engine_run): Move DDBT handling after instruction + decode/execute stage. + +Tue May 12 12:14:53 1998 Frank Ch. Eigler <fche@cygnus.com> + + * d30v-insns (do_sat*): Correct "saturate to 0 bits" patch to + properly handle negative saturation inputs. + +Tue May 12 11:11:26 1998 Frank Ch. Eigler <fche@cygnus.com> + + * engine.c (sim_engine_run): Decrement RPT_C only under more + restricted conditions. + +Mon May 11 17:33:46 1998 Frank Ch. Eigler <fche@cygnus.com> + + * d30v-insns (do_sat*): Make "saturate to 0 bits" pass through data + unchanged. + +Mon May 11 16:27:04 1998 Frank Ch. Eigler <fche@cygnus.com> + + * engine.c (sim_engine_run): Implement DDBT (debugger debug trap) + functionality. + +Fri May 8 16:44:19 1998 Frank Ch. Eigler <fche@cygnus.com> + + * d30v-insns (do_trap): Set bPC to RPT_S if trap is last + instruction in repeat block. + (bsr*/jsr*): Set R62 (LINK) to RPT_S if subroutine branch + is last instruction in repeat block. + +Fri May 8 11:06:50 1998 Frank Ch. Eigler <fche@cygnus.com> + + * d30v-insns (do_sath): Query/update F4/PSW_S using proper flag + macro. + * cpu.h (PSW_S_FLAG): New flag number for PSW_S status bit. + +Wed May 6 19:40:56 1998 Doug Evans <devans@canuck.cygnus.com> + + * sim-main.h (INSN_NAME): New arg `cpu'. + +Fri May 1 14:24:30 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * d30v-insns: Fix parameter list to sim_engine_abort. + +Thu Apr 30 14:28:00 1998 Fred Fish <fnf@cygnus.com> + + * d30v-insns (do_sath): Add additional argument that determines + whether or not the F4 (PSW_S) bit in the PSW is updated. + (SAT2H): Do not update PSW_S bit. + (SATHp): Do update PSW_S bit. + +Tue Apr 28 23:36:00 1998 Fred Fish <fnf@cygnus.com> + + * d30v-insns (SRAHp, SRLHp): Immediate values are signed 6 bit + values, not 5 bit values. + +Wed Apr 29 12:57:55 1998 Frank Ch. Eigler <fche@cygnus.com> + + * d30v-insns (do_incr): Check modular arithmetic limits after + postincrement/postdecrement, rather than before, to match + erroneous hardware behavior. + +Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Apr 27 19:42:00 1998 Fred Fish <fnf@cygnus.com> + + * d30v-insns (do_trap): Clear all bits in PSW except SM and DB. + +Mon Apr 27 14:55:00 1998 Fred Fish <fnf@cygnus.com> + + * d30v-insns (do_mulx2h): Low order results go in ra+1, high + order in ra. + +Mon Apr 27 14:42:00 1998 Fred Fish <fnf@cygnus.com> + + * d30v-insns (do_mulx2h): Rewrite to do proper 32 bit signed + multiply of high and low fields from operands. + +Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Sun Apr 26 15:20:20 1998 Tom Tromey <tromey@cygnus.com> + + * acconfig.h: New file. + * configure.in: Reverted change of Apr 24; use sinclude again. + +Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Fri Apr 24 11:20:00 1998 Tom Tromey <tromey@cygnus.com> + + * configure.in: Don't call sinclude. + +Wed Apr 22 21:23:00 1998 Fred Fish <fnf@cygnus.com> + + * ic-d30v (RbU, RcU): Unsigned versions of Rb and Rc. + * d30v-insns (MVTACC): Use new RbU and RcU macros. + +Wed Apr 22 20:52:00 1998 Fred Fish <fnf@cygnus.com> + + * ic-d30v (RbHU,RbLU): Unsigned versions of RbH and RbL. + * d30v-insns (SRL2H): Use new RbHU and RbLU macros instead of + RbH and RbL. + +Mon Apr 13 16:59:00 1998 Fred Fish <fnf@cygnus.com> + + * d30v-insns (do_srl): Avoid undefined behavior of host compiler + when shifting left by more than 31 bits. + +Tue Apr 7 18:09:00 1998 Fred Fish <fnf@cygnus.com> + + * engine.c (sim_engine_run): Remove at_loop_end variable. Add + rp_was_set and rpt_c_was_nonzero variables. Major restructuring of + code before and after instruction execution to properly handle state + of the RP bit in the PSW, the value in RPT_C, and other loop related + problems. + +Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Apr 3 15:26:00 1998 Fred Fish <fnf@cygnus.com> + + * d30v-insns (do_trap): Use offset from EIT_VB rather than hardcoded + BASE_ADDRESS constant. + * cpu.h (BASE_ADDRESS): Remove constant not used any longer. + +Fri Apr 3 14:42:00 1998 Fred Fish <fnf@cygnus.com> + + * cpu.h (EIT_VB): Define macro to access EIT_VB register. + (EIT_VB_DEFAULT): Define value of EIT_VB register after reset. + * sim-calls.c (sim_create_inferior): Set EIT_VB to EIT_VB_DEFAULT. + +Tue Mar 31 19:00:00 1998 Fred Fish <fnf@cygnus.com> + + * d30v-insns (do_dbrai): RPT_S is cia plus pcdisp rather than + just pcdisp. + +Mon Mar 30 20:30:00 1998 Fred Fish <fnf@cygnus.com> + + * engine.c (sim_engine_run): Add at_loop_end. Rework end of loop + code to use this to both reset PSW_RP when needed and to set PC + to RPT_S for another pass through the loop. + +Mon Mar 30 16:12:00 1998 Fred Fish <fnf@cygnus.com> + + * engine.c (sim_engine_run): Change code that handles RPT_* regs + and PSW_RP bit in PSW so that PSW_RP is always set while executing + the loop and loop terminates upon completion of the pass for which + RPT_C is zero. More closely follow logic in architecture manual. + +Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Thu Mar 19 00:25:43 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-calls.c (sim_open): Move memory-region commands back to + before the call to sim_parse_args. + (d30v_option_handler): Implement extmem-size option using + memory-delete and memory-region commands. + + * sim-calls.c (d30v_option_handler): Use ANSI-C argument list, + correct number and type of arguments. + +Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Mar 11 13:56:32 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * alu.h (IMEM, MEM, STORE): Replace sim_core_*_map with exec_map, + read_map and write_map resp. + + * cpu.c (d30v_read_mem, d30v_write_mem): Ditto. + +Mon Mar 2 13:34:08 1998 Fred Fish <fnf@cygnus.com> + + * d30v-insns (do_repeat): Abort repeat instructions that have + a repeat count of zero. + +Fri Feb 27 18:44:12 1998 Doug Evans <devans@canuck.cygnus.com> + + * sim-calls.c (sim_open): Update call to sim_add_option_table. + +Thu Feb 26 18:34:31 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-calls.c (sim_info): Delete. + +Wed Feb 25 14:44:58 1998 Michael Meissner <meissner@cygnus.com> + + * d30v-insns (mvtsys): If moving to EIT_VB register, and with + valid bits. Optimize code somewhat. + + * cpu.h (eit_vector_base_cr): New CR we need to special case. + (EIT_VALID): Valid bits for EIT_VB register. + + * d30v-insns (mv{f,t}sys): When moving to/from PSWH, the value is + in the low 16 bits of the register. + + * d30v-insns (do_sra): Use a common WRITE32_QUEUE to write back + results. + (do_sr{a,l}h): Do shift in 32 bits, only truncate when writing + result back to the registers. + +Tue Feb 24 18:09:52 1998 Fred Fish <fnf@cygnus.com> + + * Makefile.in (tmp-igen): Use -G gen-zero-r0 option to force + r0 to always be zero. + * cpu.h (GPR_SET): Define. + +Tue Feb 24 14:12:57 1998 Michael Meissner <meissner@cygnus.com> + + * d30v-insns (do_sath): Do saturation in 32 bits, before + converting to 16. + (sat{,2h,z,hp}): Use imm_5, not imm to get proper zero extend. + (do_sath_p): Delete, no longer used. + (sathp): Call do_sath, not do_sath_p. + +Mon Feb 23 15:55:14 1998 Michael Meissner <meissner@cygnus.com> + + * d30v-insns (illegal,wrong_slot): Print \n after PC and before we + call sim_engine_halt. + (sr{a,l}hp): Implement missing instructions. + (do_trap): Print high order PSW bits in human readable fashion. + (do_{dbra{,i},dbsr{,i},djmp{,i},djsr{,i},repeat}): Set PSW bit RP. + + * alu.h (PSW_SET_QUEUE): New macro to set PSW bits. + + * engine.c (sim_engine_run): Check for RP bit being set, not RPT_C + being > 0. If RPT_C is decremented to 0, clear PSW RP bit. + +Fri Feb 20 10:13:34 1998 Fred Fish <fnf@cygnus.com> + + * cpu.h (BASE_ADDRESS): Change from 0xfffff000 to 0xfffff020. + +Tue Feb 17 12:39:52 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-calls.c (sim_store_register, sim_fetch_register): Pass in + length parameter. Return -1. + +Fri Feb 6 17:39:54 1998 Michael Meissner <meissner@cygnus.com> + + * d30v-insns (do_dbrai): Correct typo, use shift, not comparison. + +Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Jan 30 08:29:20 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * engine.c (sim_engine_run): Add parameter nr_cpus. + +Fri Jan 30 17:09:37 1998 Michael Meissner <meissner@cygnus.com> + + * d30v-insns (jsrtzr): Check for register == 0, not != 0. + +Wed Jan 21 17:52:04 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * engine.c (do_stack_swap): Make type of new_sp unsigned. + +Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Jan 5 16:04:17 1998 Andrew Cagney <cagney@sanguine.cygnus.com> + + * sim-calls.c (sim_info): Call profile_print. + + * sim-main.h: Enable instruction profiling. + +Thu Dec 18 12:21:38 1997 Michael Meissner <meissner@cygnus.com> + + * alu.h (ALU{16,32}_END): Change setting PSW to only set the carry + and overflow bits. Don't look at the current value of PSW. + (PSW_FLAG_SET_QUEUE): Only queue up setting the particular bit in + question. Don't look at the current value of PSW. + + * d30v-insns: All instructions that set the PSW, will only queue + up the particular bits in question that were set by the + instruction. Don't look at the current value of PSW. + +Wed Dec 17 11:41:44 1997 Michael Meissner <meissner@cygnus.com> + + * cpu.h (PSW_VALID): Allow EA/DB to be set in the PSW. + (DPSW_VALID): Like PSW_VALID, but it allows the DS bit to be set. + + * engine.c (trace_alu32): When changing BPSW/DPSW, print the + special PSW bits. + + * d30v-insns (do_cmp_cc): Fix cmpps and cmpng. + (do_cmp{,u}_cc): Print which cc value was used if not in switch + statement. + (do_cmpu_cc): Remove illegal cases CMPU{EQ,NE,PS,NG}. + (mvtsys): When setting BPSW or DPSW, and with DPSW_VALID. + +Tue Dec 16 18:17:26 1997 Michael Meissner <meissner@cygnus.com> + + * d30v-insns (mulx2h): Add missing instruction. Complain if + register is not even. + (do_{add,sub}h_ppp): Get correct high/low values. Also correctly + handle short immediates. + (do_ld{2w,4bh}): Don't load r0 if ra == 0. + + * engine.c (d30v_interrupt_event): Remove unused variable + (unqueue_writes): Ditto. + +Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Sat Dec 13 23:40:17 1997 Michael Meissner <meissner@cygnus.com> + + * cpu.h (_write{32,64}): New structures for keeping track of + queued writes to registers. + (_sim_cpu): Add _write{32,64} structures. Make is_delayed_call + unsigned32 also. + (WRITE{32,64}*): New macros for queueing up writes to registers. + + * alu.h (ALU16_END): Take field that says whether we are setting + the high or low half word. Queue up changes to registers. + (ALU32_END): Queue up changes to registers. + (PSW_FLAG_SET_QUEUE): Like PSW_FLAG_SET, except queues it up. + + * sim-main.h (do_stack_swap): Remove declaration. + + * engine.c (do_stack_swap): Make static. + (unqueue_writes): New function to unqueue all changes to 32 and 64 + bit registers in order. Implement --trace-alu. Reset high water + marks for # of queued registers. If PSW changed, possibly update + stack pointer. + (do_{long,2_short,parallel}): Unqueue register writes at the + appropriate time. + + * d30v-insns: Modify all insns to queue changes to registers, + rather than do them immediately so that parallel instructions get + the right values for inputs. Rewrite 16 bit operations to be done + in terms of masked 32 bit registers. Don't call do_stack_swap any + more here. + +Thu Dec 11 10:06:02 1997 Michael Meissner <meissner@cygnus.com> + + * sim-calls.c (d30v_option_handler): Add support for --extmem-size + to size external memory. + (sim_open): Ditto. Default if no --extmem-size option is 8 meg. + +Wed Dec 10 01:08:24 1997 Jim Blandy <jimb@zwingli.cygnus.com> + + * d30v-insns (do_rot2h): Clip rotate amounts to four bits. The + upper bits, and the sign of the rotation amount, are red herrings. + (do_sra, do_srl): Handle shifts greater than 32 bits. + (do_srah, do_sral): Properly sign-extend value and shift amount. + Handle shifts larger than 16 bits. + +Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Dec 1 15:10:44 1997 Michael Meissner <meissner@cygnus.com> + + * d30v-insns (do_sub2h): For short instruction, correctly + dupplicate lower 16 bits of immediate in upper 16 bits. + (sat2z): Fix typo that ignored the upper half of the register. + (do_satz): If < 0, set *ra to 0, if not call do_sat. + (mvtsys): Before setting PSW, and with PSW_VALID. + + * cpu.h (PSW_VALID): Mask for bits in PSW that is valid. + +Mon Dec 1 15:05:03 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * d30v-insns (do_trap): Pacify GCC - correct type of %ld arg in + printf, return dummy at end. + +Mon Dec 1 15:05:03 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * d30v-insns (do_add, do_addh_ppp, do_adds): Replace ALU_ADD with + ALU_ADDC. + (do_addc): Replace ALU_SET_CARRY / ALU_ADD_CA with ALU_ADDC_C. + (do_sub, do_subh_ppp): Replace ALU_SUB with ALU_SUBB. + (do_subb): Replace ALU_SET_CARRY / ALU_SUB_CA with ALU_SUBB_B. + + * alu.h (ALU16_END): Use ALU16_HAD_CARRY_BORROW instead of + ALU16_HAD_CARRY. + (ALU32_END): Ditto. + + * sim-main.h (string.h, strings.h): Include. + + * sim-calls.c: Delete inclusion of string.h and strings.h. + +Sun Nov 30 17:29:25 1997 Michael Meissner <meissner@cygnus.com> + + * configure.in (--enable-sim-trapdump): New switch to control + whether traps 0..30 dump out the registers or do the real trap. + * configure: Regenerate. + + * Makefile.in (SIM_EXTRA_CLFAGS): Add -DTRAPDUMP={0,1} if + appropriate --{en,dis}able-sim-trapdump is done. + + * sim-calls.c (OPTION_TRACE_CALL): Rename from OPTION_CALL_TRACE. + (OPTION_TRACE_TRAPDUMP): New option for --trace-trapdump. + (d30v_option_handler): Add support for --trace-trapdump. + (d30v_options): Ditto. + (sim_open): Ditto. + + * d30v-insns (do_trap): Do register dump if --trace-trapdump and + not the system call trap. Remove support for calling old function + sim_io_syscalls. + +Sat Nov 29 18:54:55 1997 Michael Meissner <meissner@cygnus.com> + + * cpu.h (_sim_cpu): Add trace_call_p, trace_action fields. + (TRACE_CALL_P): Non-zero if --trace-call. + (TRACE_ACTION): Non-zero if there is a tracing action at the end + of processing an instruction boundary. + (TRACE_ACTION_{CALL,RETURN}): Bits to say trace call & return. + (d30v_next_insn): Delete, now trace_action field in cpu state. + + * cpu.c (d30v_next_insn): Delete, now trace_action field in cpu + state. + (return_occurred): Minimum saved register to check is now 34. + + * engine.c (sim_engine_run): Change call tracing to use + trace_action field in cpu state. + + * sim-calls.c (d30v_option_handler): Handle d30v specific options. + (d30v_options): D30V specific options. Right now, --trace-call. + (sim_open): Register d30v specific options. + + * d30v-insns (call, return insns): Move --trace-debug call/return + tracing action to d30v specific --trace-call option. + +Fri Nov 28 20:12:48 1997 Michael Meissner <meissner@cygnus.com> + + * cpu.h (CREG): Rename from CR. + + * d30v-insns (do_{addc,subb}): Explicitly import the carry bit. + (do_trap): Use CREG, not CR. Switch to using cb_syscall. + +Thu Nov 27 19:25:43 1997 Michael Meissner <meissner@cygnus.com> + + * cpu.h (ACC): Define as short cut to accumulators. + + * d30v-insns (do_rot): Delete explicit function, use ROT32 to do + rotate instruction. + (do_trap): Make trap 30 print out accumulators and first 16 + control registers as well. + (do_avg): Sign extend to 64 bit type before doing add/shift. + (do_avg2h): Sign extend 16 bit chunks before doing add/shift. + +Wed Nov 26 15:20:24 1997 Doug Evans <devans@canuck.cygnus.com> + + * Makefile.in (NL_TARGET): Define. + +Wed Nov 26 16:55:38 1997 Michael Meissner <meissner@cygnus.com> + + * cpu.h (d30v_next_insn): New flag for things we are supposed to + trace between instruction words. + ({call,return}_occurred): Remove index argument. + (d30v_{read,write}_mem): Add declarations. + + * cpu.c (d30v_next_insn): New flag for things we are supposed to + trace between instruction words. + ({call,return}_occurred): Remove index argument. + (d30v_{read,write}_mem): New functions for reading/writing + simulated memory in the new common system call support. + + * d30v-insns: Set emacs C mode. + (call/return insns): Set bit to trace call at instruction + boundary, rather than doing it here. + (do_trap): Set up to use new common system call interface. + + * engine.c (sim_engine_run): If d30v_next_insn is non zero, do + function call/return tracing. + +Mon Nov 24 16:40:49 1997 Michael Meissner <meissner@cygnus.com> + + * d30v-insns (bnot): Correctly reset bit in question. + (do_trap): Use common system call emulation support, rather than + our home grown support. + +Sun Nov 23 22:47:20 1997 Michael Meissner <meissner@cygnus.com> + + * d30v-insns (mvfacc): Immediate field is unsigned, allowing + shifts of up to 63 to be encoded. Also do shift signed, rather + than unsigned. + + * ic-d30v (IMM_6S): Add field for 6 bit unsigned constants. + + * d30v-insns (cmpu): Short cmpu zero extends immediate, not sign + extends. + +Sat Nov 22 19:04:34 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * d30v-insns (illegal, wrong_slot): Replace SIGILL with + SIM_SIGILL. + + * sim-calls.c (signal.h): Do not include, replaced by + sim-signal.h. + + * sim-main.h (signal.h): Do not include, include sim-signal.h + instead. + +Fri Nov 21 09:33:54 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * cpu.c (call_occurred): Use ZALLOC instead of xmalloc. + (return_occurred): Use zfree instead of free. + +Wed Nov 19 13:28:09 1997 Michael Meissner <meissner@cygnus.com> + + * Makefile.in ({l,s}_{support,semantics}.o): Depend on the include + files in $(ENGINE_H). + + * d30v-insns (do_{add,addc,sub,subb}): ALU_{ADD,SUB}_CA now takes + a VAL argument to add/subtract along with the carry. + +Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com> + + * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS). + +Tue Nov 18 13:56:15 1997 Michael Meissner <meissner@cygnus.com> + + * d30v-insns (do_trap): Change to new system call numbers. Add + read emulation. + +Mon Nov 17 14:43:45 1997 Michael Meissner <meissner@cygnus.com> + + * d30v-insns (mulx): Add mulx instruction. + +Sun Nov 16 19:06:56 1997 Michael Meissner <meissner@cygnus.com> + + * cpu.c ({call,return}_occurred): New trace functions to mark + function calls and returns and check whether all saved registers + really were saved. + + * cpu.h ({call,return}_occurred): Add declaration. + + * d30v-insns ({bsr, jsr} patterns): Call call_occurred if + --trace-debug to trace function calls. + (jmp register pattern): If this is a jump r62 and --trace-debug, + call return_occurred to trace function calls. + (bsr{tnz,tzr}): Move setting r62 inside conditional against reg. + (do_ld2w): Grab memory in 64-bit chunk, to check alignment. + (do_st2w): Ditto. + +Sat Nov 15 20:57:57 1997 Michael Meissner <meissner@cygnus.com> + + * d30v-insns: Undo changes from Nov. 11, allowing for odd register + pairs, since the machine doesn't support such usage. Trap on odd + registers, rather than give a warning. Keep do_src and do_trap + changes. + +Fri Nov 14 11:59:29 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * d30v-insns (do_trap): Pacify compiler warnings for printf calls. + +Tue Nov 11 18:26:03 1997 Michael Meissner <meissner@cygnus.com> + + * d30v-insns (not_r63_reg): Rename from make_even_reg, only check + for register being r63. Change callers ld2{h,w}, ld4bh{,u}. + (get_reg_not_r63): Rename from get_even_reg, and only check for + register r63. Change callers st2{w,h}, st4b. + (do_src): Correct register pair for shift left. + (do_trap): Temporarily make trap 30 print out the registers. + +Tue Nov 4 08:51:22 1997 Michael Meissner <meissner@cygnus.com> + + * d30v-insns (do_trap): Make trap 31 be used for system calls. + Add primitive write and exit system calls. + + * Makefile (FILTER): New make variable to filter out known igen + warnings. + (tmp-igen): Add $(FILTER) on all 3 invocations of igen to filter + out warnings that should be ignored by default. + +Fri Oct 31 19:36:51 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-calls.c (sim_open): Change EIT to memory region. + +Fri Oct 17 16:51:31 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * alu.h (ALU16_END): Get result from ALU16_OVERFLOW_RESULT. + (ALU32_END): Get result from ALU32_OVERFLOW_RESULT. + +Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Sep 29 15:23:35 1997 Stu Grossman <grossman@babylon-5.cygnus.com> + + * d30v-insns (MVFSYS MVTSYS): Fix bit patterns so that these + instructions get recognised. + +Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Sep 24 17:51:43 1997 Stu Grossman <grossman@babylon-5.cygnus.com> + + * Makefile.in (SIM_OBJS): Add sim-break.o. + * (INCLUDE_DEPS): Add tconfig.h. + * alu.h (MEM STORE): Change to sim_core_read/write_unaligned to + allow for trapping unaligned accesses. + * cpu.h: Define SIM_BREAKPOINT as syscall 5 for intrinsic breakpoint + mechanism. + * d30v-insn (short syscall): Use syscall 5 for breakpoint insn. + * sim-calls.c (sim_fetch_register sim_store_register): Implement. + * tconfig.in: Define SIM_HAVE_BREAKPOINTS to enable intrinsic + breakpoint mechanism. + +Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * Makefile.in (SIM_WARNINGS, SIM_ALIGNMENT, SIM_ENDIAN, + SIM_HOSTENDIAN, SIM_RESERVED_BITS): Delete, moved to common. + (SIM_EXTRA_CFLAGS): Update. + +Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * configure.in: Specify strict alignment. + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Sep 12 16:13:04 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-calls.c (sim_open): Change memory to + internal inst. RAM h'00000000-h'0000ffff (64KB) + internal data RAM h'20000000-h'20007fff (32KB) + external RAM h'80000000-h'803fffff (4MB) + EIT h'fffff000-h'ffffffff + + +Thu Sep 11 08:59:34 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * Makefile.in (SIM_OBJS): Add sim-hrw.o module. + + * sim-calls.c (sim_read): Delete. use sim-hrw. + (sim_write): Delete, use sim-hrw. + + +Tue Sep 9 01:36:20 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * ic-d30v (imm_5): Update nr args passed to LSMASKED. + + * d30v-insns (do_sat, do_sath, do_sath_p, do_satz, do_satzh): Fix, + computing the max sat value incorrectly. + +Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Sep 5 09:15:33 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * d30v-insns (do_mac, do_macs, do_msub, do_mulxs): Use explicit + type cast instead of SIGNED64 macro. + +Thu Sep 4 10:28:45 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * Makefile.in (SIM_OBJS): Include sim-memopt.o module. + + * sim-calls.c (sim_open): Pass zero modulo arg to sim_core_attach + calls. + (sim_open): If no memory, use memory commands to establish d30v + ram. + (d30v_option_handler): Delete, replased by sim-memopt.c. + (sim_create_inferior): Call sim_module_init. + + * sim-main.h (struct sim_state): Remove members eit_ram, + sizeof_eit_ram, external_ram, baseof_external_ram, + sizeof_external_ram. Using generic memory model instead. + +Mon Sep 1 11:04:09 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-calls.c (sim_open): Use sim_state_alloc. + +Sat Aug 30 10:01:51 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-main.h (INVALID_INSTRUCTION_ADDRESS): Define. + + * engine.c (do_2_short): Compare with INVALID_INSTRUCTION_ADDRESS + not -1. + +Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Wed Aug 27 13:41:54 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-calls.c (sim_open): Add call to sim_analyze_program, update + call to sim_config. + + * sim-calls.c (sim_create_inferior): Add ABFD argument. + Initialize CPU registers including PC. + (sim_load): Delete, using sim-hload. + + * Makefile.in (SIM_OBJS): Add sim-hload.o module. + +Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Mon Aug 25 15:41:44 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-calls.c (sim_open): Add ABFD argument. + (sim_open): Move sim_config call to after sim_parse_args. + (sim_open): Check sim_config return status. + +Fri Aug 22 16:38:59 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * d30v-insns (do_subh_ppp): Correct name, was do_sub_ppp. + (do_subh_ppp): Compute rc=rb-src instead of src-rb. + (do_addh_ppp): Ditto. + +Fri Jun 27 14:43:20 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * d30v-insns (mvfsys, mvtsys): Switch instruction encodings, was + wrong. Update handling of PSW[DS] bit. + (dbt): Fix debug trap address. + + * cpu.h (NR_CONTROL_REGISTERS): Allow the full 64 registers. + +Tue Jun 24 12:41:55 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * d30v-insns (DBT, RTD): Swap the stack after updating the PSW. + (DBT): Use PSW_SET to update PSW. + + * alu.h (ALU16_END): Check for 16 bit carry and not 32 bit. + +Tue Jun 24 12:16:14 1997 Andrew Cagney <cagney@b2.cygnus.com> + + * d30v-insns (ppp, ccc, pp, XX, p): Update format functions so + that they are of class %s instead of class function. + +Tue Jun 10 12:26:39 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-main.h (engine_error, engine_restart, engine_halt, + engine_run_until_stop): Delete prototypes. Functions deleted + earlier. + (do_interrupt_handler): Add prototype. + (sim_state): Add pending_event member to struct. + + * sim-calls.c (sim_open): Configure interrupt handler. + * engine.c (d30v_interrupt_event): New function. Deliver external + interrupt to processor. + + * d30v-insns (do_stack_swap): Move function from here. + * engine.c (do_stack_swap): To here. + * sim-main.h (do_stack_swap): Add prototype. + + * cpu.h (registers): Change current_sp to an int. + * d30v-insn (do_stack_swap): Update. + +Thu Jun 5 12:54:35 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * d30v-insns (LD*, ST*): Disasemble XX == 0 as immed version of + instruction. + (str_XXX): Fix case of XX == 3 - return "-". + +Thu Jun 5 12:54:35 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * engine.c (sim_engine_run): Issuing L->R and R->L instructions in + wrong order. + + * d30v-insn (CMPUcc imm long): With of RB field should be 6 not + three. + (MUL, MUL2H, MULHX): X field 01 instead of 10. + +Thu Jun 5 12:54:35 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * d30v-insns (mvtsys): Don't modify DS bit when writing to PSW. + (dbt, rtd): New instructions. + + * cpu.h (NR_CONTROL_REGISTERS): Now 15. + (debug_program_status_word_cr, debug_program_counter_cr): Add + debug control registers. Renumber other control registers. + (PSW_DS): New PSW bit. + (DPC, DPSW): Define. + +Wed May 28 13:45:47 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * engine.c (sim_engine_run): Check the event queue on every cycle. + + * sim-calls.c (sim_size): Delete. + (sim_do_command): Call sim_args_command. + (sim_open): Move eit_ram and sizeof_eit_ram to sim_state struct. + (simulation): Delete global now depend on sd argument. + (sim_open): Initialize sim-watch. + (d30v_option_handler): New function, parse mem-size argument. + +Tue May 27 14:03:38 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-calls.c (sim_set_callbacks): Delete. + (sim_write): Pass NULL cpu arg to sim_core_write_buffer. + + * engine.c (engine_init): Delete. Handled in sim_open. + (engine_create): Ditto. + +Tue May 20 10:15:35 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-calls.c (sim_open): Add callback argument. + (sim_set_callbacks): Delete SIM_DESC argument. + +Mon May 19 14:59:32 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-calls.c (sim_open): Set the sim.base magic number. + +Fri May 16 15:25:59 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * d30v-insns: Replace engine_error with common sim_engine_abort. + * cpu.c (is_condition_ok, is_wrong_slot): Ditto. + + * engine.c (engine_run_until_stop): Rename this. + (sim_engine_run): To this. Simplify - most moved to common. + + * sim-calls.c (sim_stop_reason, sim_resume, sim_stop): + Delete. Replaced by common code. + + * engine.c (engine_error, engine_restart, engine_halt): Ditto. + + * sim-main.h (SIM_ENGINE_RESTART_HOOK, SIM_ENGINE_HALT_HOOK): + Define as NOPs. + +Mon May 5 23:05:41 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * alu.h (IMEM, MEM, STORE): Update to reflect changes to core in + ../common. + * sim-calls.c (sim_open): Ditto. + + * alu.h, cpu.h, cpu.c, d30v-insn, dc-short: Clean up copyright + notice. + +Fri May 2 12:01:38 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-calls.c (sim-options.h, sim-utils.h): Include. + * Makefile.in (sim-calls.o): Add dependencies. + + * d30v-insns (address_word): Remove cia argument from support + functions, igen now does this automatically. + + * Makefile.in (tmp-igen): Include line number information in + generated files. + + * sim-main.h (SIM_DESC): Remove sim_events and sim_core, moved to + simulator base type sim_state_base. + (sim-core.h, sim-events.h, sim-io.h): Replace with #include + "sim-base.h". + + * sim-main.h (sim_state): Track recomendations in common + directory. + * cpu.h (sim_cpu): Ditto. + * engine.c (do_2_short, do_parallel): Ditto. + * cpu.h (GPR): Ditto. + * alu.h (MEM, IMEM, STORE): Ditto. + * cpu.c (is_wrong_slot): Ditto. + * ic-d30v (Aa, Ab): Ditto. + +Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * Makefile.in (SIM_OBJS): Add sim-module.o, sim-profile.o. + * sim-calls.c (sim_open): Call sim_module_uninstall if argument + parsing fails. Call sim_post_argv_init. + (sim_close): Call sim_module_uninstall. + +Fri Apr 18 13:44:48 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-calls.c (sim_stop): New function. + +Thu Apr 17 02:57:55 1997 Doug Evans <dje@canuck.cygnus.com> + + * Makefile.in (SIM_OBJS): Add sim-load.o, sim-options.o, sim-trace.o. + (SIM_EXTRA_{LIBS,LIBDEPS,ALL,INSTALL}): Delete. + (SIM_RUN_OBJS): Change from run.o to nrun.o. + * cpu.h (sim_cpu): New member base. Delete members trace, sd. + (cpu_traces): Delete. + * engine.c (engine_init): Set backlink from cpu to state. + * sim-calls.c: #include bfd.h. + (sim_open): Set STATE_OPEN_KIND. Call sim_pre_argv_init, + sim_parse_args. + (sim_load): Return SIM_RC. New arg abfd. + Call sim_load_file to load file into simulator. + (sim_create_inferior): Return SIM_RC. Delete arg start_address. + (sim_trace): Delete. + * sim-main.h (struct sim_state): sim_state_base is typedef now. + (STATE_CPU): Define. + +Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com> + + * Makefile.in (SIM_EXTRA_DEPS): Define. + (SIM_OBJS): Add sim-utils.o. + (SIM_GEN): Delete tmp-common. + (SIM_EXTRA_CLEAN): Delete clean-common. + (BUILT_SRC_FROM_COMMON): Moved to ../common/Make-common.in. + (tmp-common,clean-common): Delete. + (ENGINE_H): sim-state.h renamed to sim-main.h. + (clean-igen): Delete tmp-insns. + + * cpu.c: sim-state.h renamed to sim-main.h. + * engine.c: Likewise. + * sim-calls.c: Likewise. + (zalloc,zfree): Moved to ../common/sim-utils.c. + * sim-main.h: Renamed from sim-state.h. + + * sim-calls.c (sim_open): New arg `kind'. + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Apr 2 11:13:15 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * Makefile.in (SIM_OBJS): Link in the recently added sim-config.o + + * engine.c (current_target_byte_order, current_host_byte_order, + current_environment, current_alignment, current_floating_point, + current_model_issue, current_stdio): Delete, moved to + ../common/sim-config.c + +Mon Mar 24 14:50:30 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * d30v-insns (do_ldw): Load 4 bytes not 2. + (do_incr, LD*, ST*): Increment register not its value. + +Mon Mar 24 09:59:53 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * cpu.c (is_wrong_slot): Ditto. + (is_condition_ok): Ditto. + + * sim-calls.c (sim_trace): Ditto. + + * engine.c (engine_init): Ditto. + (do_2_short): Ditto. + (engine_run_until_stop): Ditto. + + * d30v-insns (void): Update. For functions, remove `SIM_DESC sd' + and `cpu *processor' arguments as igen now handles this. + + * cpu.h: Rename struct _cpu to struct _sim_cpu. Rename variable + processor to cpu. + + * sim-state.h: Update. + +Fri Mar 21 12:52:12 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * d30v-insns (do_sat): Correct calculation of saturate lower + bound. + (do_sath): Ditto. + (do_satzh, do_satz): Arguments should be signed. + + * sim-calls.c (zalloc): Use malloc() instead of xmalloc() for + moment. + (filter_filename): Drop. + + * cpu.h (is_wrong_slot): Correct declaration name - was + is_valid_slot. + + * engine.c (do_parallel): Plicate GCC. + (engine_error): Ditto. + (engine_run_until_stop): Ditto. + * cpu.c (is_wrong_slot): Ditto. + (is_condition_ok): Ditto. + * sim-calls.c (sim_size): Ditto. + (sim_read): Ditto. + (sim_trace): Ditto. + + * engine.h, engine.c (engine_create): Add missing prototype to + header file. Clean up missing variables. + + * configure.in (unistd.h, string.h, strings.h): Configure in. + * configure, config.in: Rebuild. + +Thu Mar 20 19:40:20 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * d30v-insns (void): Provide a second emul instruction using a + branch prefix. + +Tue Mar 18 20:51:42 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * d30v-insn (do_sat*): Pass all necessary args. + +Tue Mar 18 18:49:10 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * d30v-insns (SAT*): Issue warning when bit overflow. + (EMUL): Exit with GPR[2] not 2. + +Tue Mar 18 14:24:09 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * sim-state.h: New file rename engine.h. + (sim_state): Rename engine strut to sim_state, rename events and + core members. + + * engine.c: Update. + * cpu.h, cpu.c: Ditto. + * alu.h: Ditto. + * d30v-insns: Ditto. + * sim-calls.c: Ditto. + + * Makefile.in (sim-*.c): Moved to ../common. + +Tue Mar 18 10:39:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * d30v-insns (do_mac): Adding wrong register. + (do_macs): Ditto. + (do_msub): Ditto. + (do_msubs): Ditto. + + * ic-d30v: Put back definitions of RaH, RaL, et.al. + (do_sra2h, do_srah): Use. + (do_srl2h, do_srlh): Use. + + * d30v-insns (SAT, SAT2H, SATp, SATZ): Implement saturate. + +Tue Mar 18 03:01:25 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * d30v-insns: Specify wild insted of reserved bits. + (void): + +Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * configure: Re-generate. + +Mon Mar 17 14:35:37 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * Makefile.in (SIM_EXTRA_CFLAGS), configure.in: Include SIM_* + options. Allow RESERVED_BITS to be configured. + * configure: Re-generate. + + * Makefile.in (sim-*.h): Drop, not needed. + (sim-*.c): Make each explicit so that they automatically update. + +Sat Mar 15 02:34:30 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * ic-d30v (imm long): Incorrect calculation. + + * d30v-insns (EMUL): Finish exit, write-string emul-call. + + * sim-calls.c (sim_trace): Have sim-trace enable basic instruction + tracing. + +Sat Mar 15 02:10:31 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * configure.in: Enable common options - endian, inline and + warnings. + * configure: Regenerate. + +Fri Mar 14 16:11:50 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * Makefile.in (cpu.o): Update dependencies. + * cpu.c (is_condition_ok): Update PSW bit manipulations. + +Fri Mar 14 12:49:20 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * configure.in: Autoconfig m4 + * configure: Regenerate. + + * Makefile.in: Use m4 to preprocess d30v-insns. + * d30v-insn: Adjust. + +Thu Mar 13 12:44:54 1997 Doug Evans <dje@canuck.cygnus.com> + + * sim-calls.c (sim_open): New SIM_DESC result. Argument is now + in argv form. + (other sim_*): New SIM_DESC argument. + +Wed Mar 12 19:05:45 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * sim-calls.c (sim_open): Create all the d30v RAM blocks. + + * engine.c (engine_run_until_stop): Handle delayed subroutine + call. + * d30v-insn: Ditto. + + * ic-d30v: For Rb and Rc always return the value and not the + equation. + * d30v-insn: Use. + + * ic-d30v (val_Ra): Returns 0 or RA. + * d30v-insn: Use. + + * d30v-insn (make_even_reg, get_even_reg): New functions. Force + the register index to be even, issusing a warning if it was not. + (LD*, ST*): Use. + +Wed Mar 12 14:57:26 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * d30v-insns (do_trap): Implement TRAP instruction. + + * alu.h (PSW_F, PSW_FLAG_VAL, PSW_FLAG_SET): New macro, map flag + onto PSW bit. + * ic-d30v: Drop F* expressions. + * d30v-insn: Use more explicit PSW_FLAG_ ops. + * cpu.h (PSW_*): Redo PSW bit values. + * alu.h (ALU*_END): Update. Fix setting of overflow - logic was + backwards. + + * d30v-insn (MVFSYS, MVTSYS): Implement. + * cpu.h (PSWH, PSWL): New macros for high, low word of PSW. + +Wed Mar 12 14:12:11 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * cpu.h (RPT_IS_CALL): New macro for processor field + is_delayed_call. That in turn used as a flag to indicate if a + delayed branch or delayed call is to occure. + * d30v-insns (do_dbra): Set/clear RPT_IS_CALL; + (do_dbrai): Ditto. + (do_dbsr): Ditto. + (do_dbsr): Ditto. + (do_djmp): Ditto. + (do_djmpi): Dotto. + (do_djsr): Ditto. + (do_djsri): Ditto. + (void): + + * d30v-insn (do_incr): Finish - handle modulo registers. + + * d30v-insns (CMPU): Include all possible compare + operations. Issue a warning where op defined by the processor + spec. + +Wed Mar 12 13:55:55 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * d30v-insns: Add a new instruction class _EMUL and a new + instruction EMUL that emulates a few basic IO operations. + + * Makefile.in (tmp-igen): Filter in emul instructions. + +Fri Mar 7 20:32:13 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * d30v-insns (void): Fill in the gaps. + +Wed Feb 26 09:31:10 1997 Andrew Cagney <cagney@kremvax.tpgi.com.au> + + * Makefile.in (tmp-igen): Include ic-d30v in dependencies. + + * ic-d30v (cache): Update to use H_word, L_word added to + sim-endian.h. + +Tue Feb 25 15:26:51 1997 Andrew Cagney <cagney@kremvax.tpgi.com.au> + + * Makefile.in (tmp-igen): Correctly run $(MAKE). + +Thu Feb 20 20:30:31 1997 Andrew Cagney <cagney@critters.cygnus.com> + + * Makefile.in (FROM_IGEN, FROM_COMMON): Make the igen generated + files dependant on tmp-igen. Define ENGINE_H. + +Sun Feb 16 16:42:48 1997 Andrew Cagney <cagney@critters.cygnus.com> + + * configure.in: New file - follow Doug Evans instructions. + * Makefile.in: Ditto. + |