diff options
Diffstat (limited to 'gas/testsuite/gas/ppc')
| -rw-r--r-- | gas/testsuite/gas/ppc/astest.d | 74 | ||||
| -rw-r--r-- | gas/testsuite/gas/ppc/astest.s | 52 | ||||
| -rw-r--r-- | gas/testsuite/gas/ppc/astest2.d | 75 | ||||
| -rw-r--r-- | gas/testsuite/gas/ppc/astest2.s | 52 | ||||
| -rw-r--r-- | gas/testsuite/gas/ppc/ppc.exp | 21 | ||||
| -rw-r--r-- | gas/testsuite/gas/ppc/simpshft.d | 27 | ||||
| -rw-r--r-- | gas/testsuite/gas/ppc/simpshft.s | 110 |
7 files changed, 411 insertions, 0 deletions
diff --git a/gas/testsuite/gas/ppc/astest.d b/gas/testsuite/gas/ppc/astest.d new file mode 100644 index 00000000000..68aab554dff --- /dev/null +++ b/gas/testsuite/gas/ppc/astest.d @@ -0,0 +1,74 @@ +#objdump: -Dr +#name: PowerPC test 1 + +.*: +file format elf32-powerpc + +Disassembly of section \.text: + +0+0000000 <foo>: + 0: 60 00 00 00 nop + 4: 60 00 00 00 nop + 8: 60 00 00 00 nop + +0+000000c <a>: + c: 48 00 00 04 b 10 <apfour> + +0+0000010 <apfour>: + 10: 48 00 00 08 b 18 <apfour\+0x8> + 14: 48 00 00 00 b 14 <apfour\+0x4> + 14: R_PPC_REL24 x + 18: 48 00 00 04 b 1c <apfour\+0xc> + 18: R_PPC_REL24 \.data\+0x4 + 1c: 48 00 00 00 b 1c <apfour\+0xc> + 1c: R_PPC_REL24 z + 20: 48 00 00 14 b 34 <apfour\+0x24> + 20: R_PPC_REL24 z\+0x14 + 24: 48 00 00 04 b 28 <apfour\+0x18> + 28: 48 00 00 00 b 28 <apfour\+0x18> + 28: R_PPC_REL24 a + 2c: 4b ff ff e4 b 10 <apfour> + 30: 48 00 00 04 b 34 <apfour\+0x24> + 30: R_PPC_REL24 a\+0x4 + 34: 4b ff ff e0 b 14 <apfour\+0x4> + 38: 48 00 00 00 b 38 <apfour\+0x28> + 38: R_PPC_LOCAL24PC a + 3c: 4b ff ff d4 b 10 <apfour> + + 40: 00 00 00 40 \.long 0x40 + 40: R_PPC_ADDR32 \.text\+0x40 + + 44: 00 00 00 4c \.long 0x4c + 44: R_PPC_ADDR32 \.text\+0x4c + 48: 00 00 00 00 \.long 0x0 + 48: R_PPC_REL32 x + 4c: 00 00 00 04 \.long 0x4 + 4c: R_PPC_REL32 x\+0x4 + \.\.\. + 50: R_PPC_REL32 z + 54: R_PPC_REL32 y + 58: R_PPC_ADDR32 x + 5c: R_PPC_ADDR32 y + 60: R_PPC_ADDR32 z + 64: ff ff ff fc fnmsub f31,f31,f31,f31 + 64: R_PPC_ADDR32 x\+0xf+ffffffc + 68: ff ff ff fc fnmsub f31,f31,f31,f31 + 68: R_PPC_ADDR32 y\+0xf+ffffffc + 6c: ff ff ff fc fnmsub f31,f31,f31,f31 + 6c: R_PPC_ADDR32 z\+0xf+ffffffc + 70: ff ff ff 9c \.long 0xffffff9c + 74: ff ff ff 9c \.long 0xffffff9c + \.\.\. + 78: R_PPC_ADDR32 a + 7c: R_PPC_ADDR32 b + 80: R_PPC_ADDR32 apfour + 84: ff ff ff fc fnmsub f31,f31,f31,f31 + 88: 00 00 00 02 \.long 0x2 + 88: R_PPC_ADDR32 apfour\+0x2 + 8c: 00 00 00 00 \.long 0x0 +Disassembly of section \.data: + +0+0000000 <x>: + 0: 00 00 00 00 \.long 0x0 + +0+0000004 <y>: + 4: 00 00 00 00 \.long 0x0 diff --git a/gas/testsuite/gas/ppc/astest.s b/gas/testsuite/gas/ppc/astest.s new file mode 100644 index 00000000000..f1af216313c --- /dev/null +++ b/gas/testsuite/gas/ppc/astest.s @@ -0,0 +1,52 @@ + .section ".data" + .globl x + .globl z +x: .long 0 +z = . + 4 +four = z - x - 4 +y: .long 0 + + .section ".text" +foo: + nop ; nop ; nop + .globl a +a: b .+4 +b: b .+8 + b x + b y + b z + b z+20 + b .+four + b a + b b + b a+4 + b b+4 + b a@local + b b@local + .long . + .long .+8 + .long x-. + .long x+4-. + .long z-. + .long y-. + .long x + .long y + .long z + .long x-four + .long y-four + .long z-four + .long a-. + .long b-. + .long a + .long b + +apfour = a + four + .long apfour + .long a-apfour + .long apfour+2 + .long apfour-b + + .type foo,@function + .type a,@function + .type b,@function + .type apfour,@function diff --git a/gas/testsuite/gas/ppc/astest2.d b/gas/testsuite/gas/ppc/astest2.d new file mode 100644 index 00000000000..740e3bfe19d --- /dev/null +++ b/gas/testsuite/gas/ppc/astest2.d @@ -0,0 +1,75 @@ +#objdump: -Dr +#name: PowerPC test 2 + +.*: +file format elf32-powerpc + +Disassembly of section .text: + +0+0000000 <foo>: + 0: 60 00 00 00 nop + 4: 60 00 00 00 nop + 8: 60 00 00 00 nop + c: 48 00 00 04 b 10 <foo\+0x10> + 10: 48 00 00 08 b 18 <foo\+0x18> + 14: 48 00 00 00 b 14 <foo\+0x14> + 14: R_PPC_REL24 x + 18: 48 00 00 04 b 1c <foo\+0x1c> + 18: R_PPC_REL24 .data\+0x4 + 1c: 48 00 00 00 b 1c <foo\+0x1c> + 1c: R_PPC_REL24 z + 20: 48 00 00 14 b 34 <foo\+0x34> + 20: R_PPC_REL24 z\+0x14 + 24: 48 00 00 04 b 28 <foo\+0x28> + 28: 48 00 00 00 b 28 <foo\+0x28> + 28: R_PPC_REL24 a + 2c: 48 00 00 50 b 7c <apfour> + 30: 48 00 00 04 b 34 <foo\+0x34> + 30: R_PPC_REL24 a\+0x4 + 34: 48 00 00 4c b 80 <apfour\+0x4> + 38: 48 00 00 00 b 38 <foo\+0x38> + 38: R_PPC_LOCAL24PC a + 3c: 48 00 00 40 b 7c <apfour> + + 40: 00 00 00 40 .long 0x40 + 40: R_PPC_ADDR32 .text\+0x40 + + 44: 00 00 00 4c .long 0x4c + 44: R_PPC_ADDR32 .text\+0x4c + 48: 00 00 00 00 .long 0x0 + 48: R_PPC_REL32 x + 4c: 00 00 00 04 .long 0x4 + 4c: R_PPC_REL32 x\+0x4 + ... + 50: R_PPC_REL32 z + 54: R_PPC_REL32 y + 58: R_PPC_ADDR32 x + 5c: R_PPC_ADDR32 y + 60: R_PPC_ADDR32 z + 64: ff ff ff fc fnmsub f31,f31,f31,f31 + 64: R_PPC_ADDR32 x\+0xf+ffffffc + 68: ff ff ff fc fnmsub f31,f31,f31,f31 + 68: R_PPC_ADDR32 y\+0xf+ffffffc + 6c: ff ff ff fc fnmsub f31,f31,f31,f31 + 6c: R_PPC_ADDR32 z\+0xf+ffffffc + 70: 00 00 00 08 .long 0x8 + 74: 00 00 00 08 .long 0x8 + +0+0000078 <a>: + 78: 00 00 00 00 .long 0x0 + 78: R_PPC_ADDR32 a + +0+000007c <apfour>: + ... + 7c: R_PPC_ADDR32 b + 80: R_PPC_ADDR32 apfour + 84: ff ff ff fc fnmsub f31,f31,f31,f31 + 88: 00 00 00 02 .long 0x2 + 88: R_PPC_ADDR32 apfour\+0x2 + 8c: 00 00 00 00 .long 0x0 +Disassembly of section .data: + +0+0000000 <x>: + 0: 00 00 00 00 .long 0x0 + +0+0000004 <y>: + 4: 00 00 00 00 .long 0x0 diff --git a/gas/testsuite/gas/ppc/astest2.s b/gas/testsuite/gas/ppc/astest2.s new file mode 100644 index 00000000000..5af223378fd --- /dev/null +++ b/gas/testsuite/gas/ppc/astest2.s @@ -0,0 +1,52 @@ +four = 4 + .section ".text" +foo: + nop ; nop ; nop + .globl a + b .+4 + b .+8 + b x + b y + b z + b z+20 + b .+four + b a + b b + b a+4 + b b+4 + b a@local + b b@local + .long . + .long .+8 + .long x-. + .long x+4-. + .long z-. + .long y-. + .long x + .long y + .long z + .long x-four + .long y-four + .long z-four + .long a-. + .long b-. +a: .long a +b: .long b + +apfour = a + four + .long apfour + .long a-apfour + .long apfour+2 + .long apfour-b + + .section ".data" + .globl x + .globl z +x: .long 0 +z = . + 4 +y: .long 0 + + .type foo,@function + .type a,@function + .type b,@function + .type apfour,@function diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp new file mode 100644 index 00000000000..572fbc345b4 --- /dev/null +++ b/gas/testsuite/gas/ppc/ppc.exp @@ -0,0 +1,21 @@ +# +# Some PowerPC tests +# + +# These tests are currently ELF specific, only because nobody has +# converted them to look for XCOFF relocations. + +if { [istarget powerpc*-*-*bsd*] \ + || [istarget powerpc*-*-elf*] \ + || [istarget powerpc*-*-eabi*] \ + || [istarget powerpc*-*-sysv4*] \ + || [istarget powerpc*-*-linux*] \ + || [istarget powerpc*-*-solaris*] \ + || [istarget powerpc*-*-rtems*] } then { + run_dump_test "astest" + run_dump_test "astest2" +} + +if { [istarget powerpc*-*-*] } then { + run_dump_test "simpshft" +} diff --git a/gas/testsuite/gas/ppc/simpshft.d b/gas/testsuite/gas/ppc/simpshft.d new file mode 100644 index 00000000000..06893d55395 --- /dev/null +++ b/gas/testsuite/gas/ppc/simpshft.d @@ -0,0 +1,27 @@ +#objdump: -s -j .text +#as: -mppc64 +#name: PowerPC test 3, simplified shifts + +.* + +Contents of section \.text: + 0000 78640fe0 7883f80e 78a545e4 78640020 xd..x...x.E.xd. + 0010 54640ffe 5083f800 54a5402e 5464043e Td..P...T.@.Td.> + 0020 78640004 786407e4 7864f806 7864ffe6 xd..xd..xd..xd.. + 0030 7864f842 7864ffe2 7864000c 7864080c xd.Bxd..xd..xd.. + 0040 78640fac 786407ec 78640000 78640800 xd..xd..xd..xd.. + 0050 7864f802 78640000 7864f802 78640800 xd..xd..xd..xd.. + 0060 78652010 786407e4 7864f806 78640000 xe .xd..xd..xd.. + 0070 7864f842 78640fe0 78640000 78640040 xd.Bxd..xd..xd.@ + 0080 786407e0 786407e4 786407a4 78640004 xd..xd..xd..xd.. + 0090 78640008 78640048 786407e8 78640fa8 xd..xd.Hxd..xd.. + 00a0 7864f80a 54640000 5464003e 5464f800 xd..Td..Td.>Td.. + 00b0 5464f83e 5464f87e 5464fffe 50640000 Td.>Td.~Td..Pd.. + 00c0 5064003e 50640ffe 5064f800 5064003e Pd.>Pd..Pd..Pd.> + 00d0 506407fe 5464003e 5464083e 5464f83e Pd..Td.>Td.>Td.> + 00e0 5464003e 5464f83e 5464083e 5c65203e Td.>Td.>Td.>\\e > + 00f0 5464003e 5464083c 5464f800 5464003e Td.>Td.<Td..Td.> + 0100 5464f87e 54640ffe 5464003e 5464007e Td.~Td..Td.>Td.~ + 0110 546407fe 5464003e 5464003c 54640000 Td..Td.>Td.<Td.. + 0120 5464003e 5464007e 546407fe 54640fbc Td.>Td.~Td..Td.. + 0130 5464f800 00000000 Td...... diff --git a/gas/testsuite/gas/ppc/simpshft.s b/gas/testsuite/gas/ppc/simpshft.s new file mode 100644 index 00000000000..39ff98d07b6 --- /dev/null +++ b/gas/testsuite/gas/ppc/simpshft.s @@ -0,0 +1,110 @@ +# These are all the examples from section F.4 of +# "PowerPC Microprocessor Family: The Programming Environments". +# 64-bit examples + extrdi %r4,%r3,1,0 + insrdi %r3,%r4,1,0 + sldi %r5,%r5,8 + clrldi %r4,%r3,32 +# 32-bit examples + extrwi %r4,%r3,1,0 + insrwi %r3,%r4,1,0 + slwi %r5,%r5,8 + clrlwi %r4,%r3,16 + + +# These test the remaining corner cases for 64-bit operations. + extldi %r4,%r3,1,0 + extldi %r4,%r3,64,0 + extldi %r4,%r3,1,63 + extldi %r4,%r3,64,63 # bit weird, that one. + + extrdi %r4,%r3,63,0 + extrdi %r4,%r3,1,62 + + insrdi %r4,%r3,64,0 + insrdi %r4,%r3,63,0 + insrdi %r4,%r3,1,62 + insrdi %r4,%r3,1,63 + + rotldi %r4,%r3,0 + rotldi %r4,%r3,1 + rotldi %r4,%r3,63 + + rotrdi %r4,%r3,0 + rotrdi %r4,%r3,1 + rotrdi %r4,%r3,63 + + rotld %r5,%r3,%r4 + + sldi %r4,%r3,0 + sldi %r4,%r3,63 + + srdi %r4,%r3,0 + srdi %r4,%r3,1 + srdi %r4,%r3,63 + + clrldi %r4,%r3,0 + clrldi %r4,%r3,1 + clrldi %r4,%r3,63 + + clrrdi %r4,%r3,0 + clrrdi %r4,%r3,1 + clrrdi %r4,%r3,63 + + clrlsldi %r4,%r3,0,0 + clrlsldi %r4,%r3,1,0 + clrlsldi %r4,%r3,63,0 + clrlsldi %r4,%r3,63,1 + clrlsldi %r4,%r3,63,63 + +# These test the remaining corner cases for 32-bit operations. + extlwi %r4,%r3,1,0 + extlwi %r4,%r3,32,0 + extlwi %r4,%r3,1,31 + extlwi %r4,%r3,32,31 # bit weird, that one. + + extrwi %r4,%r3,31,0 + extrwi %r4,%r3,1,30 + + inslwi %r4,%r3,1,0 + inslwi %r4,%r3,32,0 + inslwi %r4,%r3,1,31 + + insrwi %r4,%r3,1,0 + insrwi %r4,%r3,32,0 + insrwi %r4,%r3,1,31 + + rotlwi %r4,%r3,0 + rotlwi %r4,%r3,1 + rotlwi %r4,%r3,31 + + rotrwi %r4,%r3,0 + rotrwi %r4,%r3,1 + rotrwi %r4,%r3,31 + + rotlw %r5,%r3,%r4 + + slwi %r4,%r3,0 + slwi %r4,%r3,1 + slwi %r4,%r3,31 + + srwi %r4,%r3,0 + srwi %r4,%r3,1 + srwi %r4,%r3,31 + + clrlwi %r4,%r3,0 + clrlwi %r4,%r3,1 + clrlwi %r4,%r3,31 + + clrrwi %r4,%r3,0 + clrrwi %r4,%r3,1 + clrrwi %r4,%r3,31 + + clrlslwi %r4,%r3,0,0 + clrlslwi %r4,%r3,1,0 + clrlslwi %r4,%r3,31,0 + clrlslwi %r4,%r3,31,1 + clrlslwi %r4,%r3,31,31 + +# Force alignment so that we pass the test on AIX + .p2align 3 |