diff options
87 files changed, 790 insertions, 661 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index ac27947d44c..678a0a26017 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,61 @@ +2009-06-30 Nick Clifton <nickc@redhat.com> + + PR 10288 + * gas/arm/adrl.d: Update expected disassembly. + * gas/arm/arch4t-eabi.d: Likewise. + * gas/arm/arch4t.d: Likewise. + * gas/arm/arch6zk.d: Likewise. + * gas/arm/archv6t2.d: Likewise. + * gas/arm/arm-it.d: Likewise. + * gas/arm/arm3.d: Likewise. + * gas/arm/arm7dm.d: Likewise. + * gas/arm/arm7t.d: Likewise. + * gas/arm/backslash-at.d: Likewise. + * gas/arm/bl-local-v4t.d: Likewise. + * gas/arm/blx-local.d: Likewise. + * gas/arm/copro.d: Likewise. + * gas/arm/el_segundo.d: Likewise. + * gas/arm/float.d: Likewise. + * gas/arm/fp-save.d: Likewise. + * gas/arm/fpa-mem.d: Likewise. + * gas/arm/group-reloc-alu.d: Likewise. + * gas/arm/group-reloc-ldr.d: Likewise. + * gas/arm/group-reloc-ldrs.d: Likewise. + * gas/arm/immed.d: Likewise. + * gas/arm/inst.d: Likewise. + * gas/arm/iwmmxt.d: Likewise. + * gas/arm/ldconst.d: Likewise. + * gas/arm/macro1.d: Likewise. + * gas/arm/mapmisc.d: Likewise. + * gas/arm/mapsecs.d: Likewise. + * gas/arm/mapshort-eabi.d: Likewise. + * gas/arm/mapshort-elf.d: Likewise. + * gas/arm/movw-local.d: Likewise. + * gas/arm/neon-ldst-rm.d: Likewise. + * gas/arm/offset.d: Likewise. + * gas/arm/reg-alias.d: Likewise. + * gas/arm/relax_load_align.d: Likewise. + * gas/arm/tcompat.d: Likewise. + * gas/arm/tcompat2.d: Likewise. + * gas/arm/thumb-eabi.d: Likewise. + * gas/arm/thumb.d: Likewise. + * gas/arm/thumb1_unified.d: Likewise. + * gas/arm/thumb2_add.d: Likewise. + * gas/arm/thumb2_it.d: Likewise. + * gas/arm/thumb2_it_auto.d: Likewise. + * gas/arm/thumb2_pool.d: Likewise. + * gas/arm/thumb2_relax.d: Likewise. + * gas/arm/thumb32.d: Likewise. + * gas/arm/thumbv6.d: Likewise. + * gas/arm/thumbv6k.d: Likewise. + * gas/arm/tls.d: Likewise. + * gas/arm/vfp1.d: Likewise. + * gas/arm/vfp1_t2.d: Likewise. + * gas/arm/vfp1xD.d: Likewise. + * gas/arm/wince.d: Likewise. + * gas/arm/wince_inst.d: Likewise. + * gas/arm/xscale.d: Likewise. + 2009-06-29 Nick Clifton <nickc@redhat.com> PR 10288 diff --git a/gas/testsuite/gas/arm/adrl.d b/gas/testsuite/gas/arm/adrl.d index ccd4ef711b9..3261311c92d 100644 --- a/gas/testsuite/gas/arm/adrl.d +++ b/gas/testsuite/gas/arm/adrl.d @@ -7,20 +7,20 @@ Disassembly of section .text: ... -0+2000 <.*> e24f0008 sub r0, pc, #8 ; 0x8 +0+2000 <.*> e24f0008 sub r0, pc, #8 0+2004 <.*> e2400c20 sub r0, r0, #8192 ; 0x2000 -0+2008 <.*> e28f0020 add r0, pc, #32 ; 0x20 +0+2008 <.*> e28f0020 add r0, pc, #32 0+200c <.*> e2800c20 add r0, r0, #8192 ; 0x2000 -0+2010 <.*> e24f0018 sub r0, pc, #24 ; 0x18 -0+2014 <.*> e1a00000 nop \(mov r0,r0\) -0+2018 <.*> e28f0008 add r0, pc, #8 ; 0x8 -0+201c <.*> e1a00000 nop \(mov r0,r0\) -0+2020 <.*> 028f0000 addeq r0, pc, #0 ; 0x0 -0+2024 <.*> e1a00000 nop \(mov r0,r0\) +0+2010 <.*> e24f0018 sub r0, pc, #24 +0+2014 <.*> e1a00000 nop ; \(mov r0, r0\) +0+2018 <.*> e28f0008 add r0, pc, #8 +0+201c <.*> e1a00000 nop ; \(mov r0, r0\) +0+2020 <.*> 028f0000 addeq r0, pc, #0 +0+2024 <.*> e1a00000 nop ; \(mov r0, r0\) 0+2028 <.*> e24f0030 sub r0, pc, #48 ; 0x30 0+202c <.*> e2400c20 sub r0, r0, #8192 ; 0x2000 0+2030 <.*> e28f0c21 add r0, pc, #8448 ; 0x2100 -0+2034 <.*> e1a00000 nop \(mov r0,r0\) +0+2034 <.*> e1a00000 nop ; \(mov r0, r0\) ... 0+4030 <.*> e28fec01 add lr, pc, #256 ; 0x100 ... diff --git a/gas/testsuite/gas/arm/arch4t-eabi.d b/gas/testsuite/gas/arm/arch4t-eabi.d index dfab64d4e37..afd92f79ef2 100644 --- a/gas/testsuite/gas/arm/arch4t-eabi.d +++ b/gas/testsuite/gas/arm/arch4t-eabi.d @@ -18,23 +18,22 @@ Disassembly of section .text: 0+18 <[^>]+> 011510d3 ? ldrsbeq r1, \[r5, -r3\] 0+1c <[^>]+> 109620b7 ? ldrhne r2, \[r6\], r7 0+20 <[^>]+> 309720f8 ? ldrshcc r2, \[r7\], r8 -0+24 <[^>]+> e1d32fdf ? ldrsb r2, \[r3, #255\] -0+28 <[^>]+> e1541ffa ? ldrsh r1, \[r4, #-250\] -0+2c <[^>]+> e1d51fd0 ? ldrsb r1, \[r5, #240\] +0+24 <[^>]+> e1d32fdf ? ldrsb r2, \[r3, #255\].* +0+28 <[^>]+> e1541ffa ? ldrsh r1, \[r4, #-250\].* +0+2c <[^>]+> e1d51fd0 ? ldrsb r1, \[r5, #240\].* 0+30 <[^>]+> e1cf23b0 ? strh r2, \[pc, #48\] ; 0+68 <[^>]+> 0+34 <[^>]+> 11c330b0 ? strhne r3, \[r3\] -0+38 <[^>]+> e328f002 ? msr CPSR_f, #2 ; 0x2 +0+38 <[^>]+> e328f002 ? msr CPSR_f, #2 0+3c <[^>]+> e121f003 ? msr CPSR_c, r3 0+40 <[^>]+> e122f004 ? msr CPSR_x, r4 0+44 <[^>]+> e124f005 ? msr CPSR_s, r5 0+48 <[^>]+> e128f006 ? msr CPSR_f, r6 0+4c <[^>]+> e129f007 ? msr CPSR_fc, r7 -0+50 <[^>]+> e368f004 ? msr SPSR_f, #4 ; 0x4 +0+50 <[^>]+> e368f004 ? msr SPSR_f, #4 0+54 <[^>]+> e161f008 ? msr SPSR_c, r8 0+58 <[^>]+> e162f009 ? msr SPSR_x, r9 0+5c <[^>]+> e164f00a ? msr SPSR_s, sl 0+60 <[^>]+> e168f00b ? msr SPSR_f, fp 0+64 <[^>]+> e169f00c ? msr SPSR_fc, ip -0+68 <[^>]+> e1a00000 ? nop \(mov r0,r0\) -0+6c <[^>]+> e1a00000 ? nop \(mov r0,r0\) - +0+68 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) +0+6c <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) diff --git a/gas/testsuite/gas/arm/arch4t.d b/gas/testsuite/gas/arm/arch4t.d index 4ec95f402e9..665585234fb 100644 --- a/gas/testsuite/gas/arm/arch4t.d +++ b/gas/testsuite/gas/arm/arch4t.d @@ -16,23 +16,23 @@ Disassembly of section .text: 0+18 <[^>]+> 011510d3 ? ldrsbeq r1, \[r5, -r3\] 0+1c <[^>]+> 109620b7 ? ldrhne r2, \[r6\], r7 0+20 <[^>]+> 309720f8 ? ldrshcc r2, \[r7\], r8 -0+24 <[^>]+> e1d32fdf ? ldrsb r2, \[r3, #255\] -0+28 <[^>]+> e1541ffa ? ldrsh r1, \[r4, #-250\] -0+2c <[^>]+> e1d51fd0 ? ldrsb r1, \[r5, #240\] +0+24 <[^>]+> e1d32fdf ? ldrsb r2, \[r3, #255\].* +0+28 <[^>]+> e1541ffa ? ldrsh r1, \[r4, #-250\].* +0+2c <[^>]+> e1d51fd0 ? ldrsb r1, \[r5, #240\].* 0+30 <[^>]+> e1cf23b0 ? strh r2, \[pc, #48\] ; 0+68 <[^>]+> 0+34 <[^>]+> 11c330b0 ? strhne r3, \[r3\] -0+38 <[^>]+> e328f002 ? msr CPSR_f, #2 ; 0x2 +0+38 <[^>]+> e328f002 ? msr CPSR_f, #2 0+3c <[^>]+> e121f003 ? msr CPSR_c, r3 0+40 <[^>]+> e122f004 ? msr CPSR_x, r4 0+44 <[^>]+> e124f005 ? msr CPSR_s, r5 0+48 <[^>]+> e128f006 ? msr CPSR_f, r6 0+4c <[^>]+> e129f007 ? msr CPSR_fc, r7 -0+50 <[^>]+> e368f004 ? msr SPSR_f, #4 ; 0x4 +0+50 <[^>]+> e368f004 ? msr SPSR_f, #4 0+54 <[^>]+> e161f008 ? msr SPSR_c, r8 0+58 <[^>]+> e162f009 ? msr SPSR_x, r9 0+5c <[^>]+> e164f00a ? msr SPSR_s, sl 0+60 <[^>]+> e168f00b ? msr SPSR_f, fp 0+64 <[^>]+> e169f00c ? msr SPSR_fc, ip -0+68 <[^>]+> e1a00000 ? nop \(mov r0,r0\) -0+6c <[^>]+> e1a00000 ? nop \(mov r0,r0\) +0+68 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) +0+6c <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) diff --git a/gas/testsuite/gas/arm/arch6zk.d b/gas/testsuite/gas/arm/arch6zk.d index 6aa73ff7278..5ec8def063e 100644 --- a/gas/testsuite/gas/arm/arch6zk.d +++ b/gas/testsuite/gas/arm/arch6zk.d @@ -24,6 +24,6 @@ Disassembly of section .text: 0+040 <[^>]*> e320f002 ? wfe 0+044 <[^>]*> e320f003 ? wfi 0+048 <[^>]*> e320f001 ? yield -0+04c <[^>]*> e16ec371 ? smc 60465 -0+050 <[^>]*> 11613c7e ? smcne 5070 +0+04c <[^>]*> e16ec371 ? smc 60465.* +0+050 <[^>]*> 11613c7e ? smcne 5070.* #... diff --git a/gas/testsuite/gas/arm/archv6t2.d b/gas/testsuite/gas/arm/archv6t2.d index e6e57c843b9..cacf641fef1 100644 --- a/gas/testsuite/gas/arm/archv6t2.d +++ b/gas/testsuite/gas/arm/archv6t2.d @@ -34,10 +34,10 @@ Disassembly of section .text: 0+68 <[^>]+> e0600099 mls r0, r9, r0, r0 0+6c <[^>]+> e0600990 mls r0, r0, r9, r0 0+70 <[^>]+> e0609090 mls r0, r0, r0, r9 -0+74 <[^>]+> e3000000 movw r0, #0 ; 0x0 -0+78 <[^>]+> e3400000 movt r0, #0 ; 0x0 -0+7c <[^>]+> 13000000 movwne r0, #0 ; 0x0 -0+80 <[^>]+> e3009000 movw r9, #0 ; 0x0 +0+74 <[^>]+> e3000000 movw r0, #0 +0+78 <[^>]+> e3400000 movt r0, #0 +0+7c <[^>]+> 13000000 movwne r0, #0 +0+80 <[^>]+> e3009000 movw r9, #0 0+84 <[^>]+> e3000999 movw r0, #2457 ; 0x999 0+88 <[^>]+> e3090000 movw r0, #36864 ; 0x9000 0+8c <[^>]+> e0f900b0 ldrht r0, \[r9\] @@ -47,5 +47,5 @@ Disassembly of section .text: 0+9c <[^>]+> 10f900b0 ldrhtne r0, \[r9\] 0+a0 <[^>]+> e0b090b9 ldrht r9, \[r0\], r9 0+a4 <[^>]+> e03090b9 ldrht r9, \[r0\], -r9 -0+a8 <[^>]+> e0f099b9 ldrht r9, \[r0\], #153 -0+ac <[^>]+> e07099b9 ldrht r9, \[r0\], #-153 +0+a8 <[^>]+> e0f099b9 ldrht r9, \[r0\], #153.* +0+ac <[^>]+> e07099b9 ldrht r9, \[r0\], #-153.* diff --git a/gas/testsuite/gas/arm/arm-it.d b/gas/testsuite/gas/arm/arm-it.d index 674f815f1de..1abe0493437 100644 --- a/gas/testsuite/gas/arm/arm-it.d +++ b/gas/testsuite/gas/arm/arm-it.d @@ -5,5 +5,5 @@ .*: +file format .*arm.* Disassembly of section .text: -0+000 <[^>]*> 03a00000 ? moveq r0, #0 ; 0x0 +0+000 <[^>]*> 03a00000 ? moveq r0, #0 0+004 <[^>]*> e1a0f00e ? mov pc, lr diff --git a/gas/testsuite/gas/arm/arm3.d b/gas/testsuite/gas/arm/arm3.d index 41b6b7eb8fd..c4a1001ba10 100644 --- a/gas/testsuite/gas/arm/arm3.d +++ b/gas/testsuite/gas/arm/arm3.d @@ -8,4 +8,4 @@ Disassembly of section .text: 0+0 <[^>]*> e1080091 ? swp r0, r1, \[r8\] 0+4 <[^>]*> e1423093 ? swpb r3, r3, \[r2\] 0+8 <[^>]*> a1454091 ? swpbge r4, r1, \[r5\] -0+c <[^>]*> e1a00000 ? nop \(mov r0,r0\) +0+c <[^>]*> e1a00000 ? nop ; \(mov r0, r0\) diff --git a/gas/testsuite/gas/arm/arm7dm.d b/gas/testsuite/gas/arm/arm7dm.d index 43f64204e97..9411170dbdf 100644 --- a/gas/testsuite/gas/arm/arm7dm.d +++ b/gas/testsuite/gas/arm/arm7dm.d @@ -13,7 +13,7 @@ Disassembly of section .text: 0+14 <[^>]+> e0d01b99 ? smulls r1, r0, r9, fp 0+18 <[^>]+> 00b92994 ? umlalseq r2, r9, r4, r9 0+1c <[^>]+> a0eaee98 ? smlalge lr, sl, r8, lr -0+20 <[^>]+> e322f000 ? msr CPSR_x, #0 ; 0x0 -0+24 <[^>]+> e1a00000 ? nop \(mov r0,r0\) -0+28 <[^>]+> e1a00000 ? nop \(mov r0,r0\) -0+2c <[^>]+> e1a00000 ? nop \(mov r0,r0\) +0+20 <[^>]+> e322f000 ? msr CPSR_x, #0 +0+24 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) +0+28 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) +0+2c <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) diff --git a/gas/testsuite/gas/arm/arm7t.d b/gas/testsuite/gas/arm/arm7t.d index 37abd7a7781..2d1698426b0 100644 --- a/gas/testsuite/gas/arm/arm7t.d +++ b/gas/testsuite/gas/arm/arm7t.d @@ -66,5 +66,5 @@ Disassembly of section .text: [ ]*dc:.*fred 0+e0 <[^>]*> 0000c0de ? .* 0+e4 <[^>]*> 0000dead ? .* -0+e8 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) -0+ec <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) +0+e8 <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\) +0+ec <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\) diff --git a/gas/testsuite/gas/arm/backslash-at.d b/gas/testsuite/gas/arm/backslash-at.d index a8992bdb4fa..c87965f4d37 100644 --- a/gas/testsuite/gas/arm/backslash-at.d +++ b/gas/testsuite/gas/arm/backslash-at.d @@ -5,13 +5,13 @@ Disassembly of section .text: 0+000 <.*>.*615c.* -0+002 <foo> e3a00000 mov r0, #0 ; 0x0 -0+006 <foo\+0x4> e3a00000 mov r0, #0 ; 0x0 -0+00a <foo\+0x8> e3a00000 mov r0, #0 ; 0x0 -0+00e <foo\+0xc> e3a00001 mov r0, #1 ; 0x1 -0+012 <foo\+0x10> e3a00001 mov r0, #1 ; 0x1 -0+016 <foo\+0x14> e3a00001 mov r0, #1 ; 0x1 -0+01a <foo\+0x18> e3a00002 mov r0, #2 ; 0x2 -0+01e <foo\+0x1c> e3a00002 mov r0, #2 ; 0x2 -0+022 <foo\+0x20> e3a00002 mov r0, #2 ; 0x2 +0+002 <foo> e3a00000 mov r0, #0 +0+006 <foo\+0x4> e3a00000 mov r0, #0 +0+00a <foo\+0x8> e3a00000 mov r0, #0 +0+00e <foo\+0xc> e3a00001 mov r0, #1 +0+012 <foo\+0x10> e3a00001 mov r0, #1 +0+016 <foo\+0x14> e3a00001 mov r0, #1 +0+01a <foo\+0x18> e3a00002 mov r0, #2 +0+01e <foo\+0x1c> e3a00002 mov r0, #2 +0+022 <foo\+0x20> e3a00002 mov r0, #2 #... diff --git a/gas/testsuite/gas/arm/bl-local-v4t.d b/gas/testsuite/gas/arm/bl-local-v4t.d index b5af7fd59b2..767d9ce4784 100644 --- a/gas/testsuite/gas/arm/bl-local-v4t.d +++ b/gas/testsuite/gas/arm/bl-local-v4t.d @@ -1,6 +1,6 @@ #name: bl local instructions for v4t. #objdump: -drw --prefix-addresses --show-raw-insn -#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* *-*-elf #as: # stderr: blx-local-thumb.l @@ -11,9 +11,9 @@ Disassembly of section .text: 0+1e <[^>]*> e003 b.n 00+28 <[^>]*> 0+20 <[^>]*> f000 f808 bl 00+34 <[^>]*> 0+24 <[^>]*> f000 f802 bl 00+2c <[^>]*> -0+28 <[^>]*> 46c0 nop \(mov r8, r8\) -0+2a <[^>]*> 46c0 nop \(mov r8, r8\) -0+2c <[^>]*> 46c0 nop \(mov r8, r8\) +0+28 <[^>]*> 46c0 nop ; \(mov r8, r8\) +0+2a <[^>]*> 46c0 nop ; \(mov r8, r8\) +0+2c <[^>]*> 46c0 nop ; \(mov r8, r8\) ... -0+30 <[^>]*> e1a00000 nop \(mov r0,r0\) -0+34 <[^>]*> e1a00000 nop \(mov r0,r0\)
\ No newline at end of file +0+30 <[^>]*> e1a00000 nop ; \(mov r0, r0\) +0+34 <[^>]*> e1a00000 nop ; \(mov r0, r0\) diff --git a/gas/testsuite/gas/arm/blx-local.d b/gas/testsuite/gas/arm/blx-local.d index 4b7d53a85f1..5aae7bada61 100644 --- a/gas/testsuite/gas/arm/blx-local.d +++ b/gas/testsuite/gas/arm/blx-local.d @@ -1,6 +1,6 @@ #name: Local BLX instructions #objdump: -drw --prefix-addresses --show-raw-insn -#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* *-*-elf #as: # stderr: blx-local.l # Test assembler resolution of blx and bl instructions in ARM mode. @@ -15,15 +15,15 @@ Disassembly of section .text: 0+14 <[^>]*> eb00000a bl 00000044 <fooundefarm> 0+18 <[^>]*> fa000001 blx 00000024 <fooundefthumb> 0+1c <[^>]*> eb000000 bl 00000024 <fooundefthumb> -0+20 <[^>]*> 46c0 nop \(mov r8, r8\) -0+22 <[^>]*> 46c0 nop \(mov r8, r8\) -0+24 <[^>]*> 46c0 nop \(mov r8, r8\) -0+26 <[^>]*> 46c0 nop \(mov r8, r8\) +0+20 <[^>]*> 46c0 nop ; \(mov r8, r8\) +0+22 <[^>]*> 46c0 nop ; \(mov r8, r8\) +0+24 <[^>]*> 46c0 nop ; \(mov r8, r8\) +0+26 <[^>]*> 46c0 nop ; \(mov r8, r8\) 0+28 <[^>]*> 0bfffffd bleq 00000024 <fooundefthumb> 0+2c <[^>]*> 0afffffc beq 00000024 <fooundefthumb> 0+30 <[^>]*> eafffffb b 00000024 <fooundefthumb> 0+34 <[^>]*> 0bfffffe bleq 00000020 <foo> 34: R_ARM_JUMP24 foo 0+58 <[^>]*> 0afffffe beq 00000020 <foo> 38: R_ARM_JUMP24 foo 0+5c <[^>]*> eafffffe b 00000020 <foo> 3c: R_ARM_JUMP24 foo -0+60 <[^>]*> e1a00000 nop \(mov r0,r0\) -0+64 <[^>]*> e1a00000 nop \(mov r0,r0\) +0+60 <[^>]*> e1a00000 nop ; \(mov r0, r0\) +0+64 <[^>]*> e1a00000 nop ; \(mov r0, r0\) diff --git a/gas/testsuite/gas/arm/copro.d b/gas/testsuite/gas/arm/copro.d index b78d7eb4bd1..86340c4e91d 100644 --- a/gas/testsuite/gas/arm/copro.d +++ b/gas/testsuite/gas/arm/copro.d @@ -37,5 +37,5 @@ Disassembly of section .text: 0+06c <[^>]*> ec407e05 mcrr 14, 0, r7, r0, cr5 0+070 <[^>]*> ec507fff mrrc 15, 15, r7, r0, cr15 0+074 <[^>]*> ec407efe mcrr 14, 15, r7, r0, cr14 -0+078 <[^>]*> e1a00000 nop \(mov r0,r0\) -0+07c <[^>]*> e1a00000 nop \(mov r0,r0\) +0+078 <[^>]*> e1a00000 nop ; \(mov r0, r0\) +0+07c <[^>]*> e1a00000 nop ; \(mov r0, r0\) diff --git a/gas/testsuite/gas/arm/el_segundo.d b/gas/testsuite/gas/arm/el_segundo.d index 064c51f41a9..6126060bbdb 100644 --- a/gas/testsuite/gas/arm/el_segundo.d +++ b/gas/testsuite/gas/arm/el_segundo.d @@ -31,4 +31,4 @@ Disassembly of section \.text: 0+60 <[^>]+> e1220051 qsub r0, r1, r2 0+64 <[^>]+> e1620051 qdsub r0, r1, r2 0+68 <[^>]+> e1220051 qsub r0, r1, r2 -0+6c <[^>]+> e1a00000 nop \(mov r0,r0\) +0+6c <[^>]+> e1a00000 nop ; \(mov r0, r0\) diff --git a/gas/testsuite/gas/arm/float.d b/gas/testsuite/gas/arm/float.d index 46039dedd38..16d7eba2694 100644 --- a/gas/testsuite/gas/arm/float.d +++ b/gas/testsuite/gas/arm/float.d @@ -119,13 +119,13 @@ Disassembly of section .text: 0+1bc <[^>]+> 0ef3f114 ? cnfeeq f3, f4 0+1c0 <[^>]+> 0ef4f117 ? cnfeeq f4, f7 0+1c4 <[^>]+> eef4f11d ? cnfe f4, #5\.0 -0+1c8 <[^>]+> ed900200 ? lfm f0, 4, \[r0\] -0+1cc <[^>]+> ed900200 ? lfm f0, 4, \[r0\] +0+1c8 <[^>]+> ed900200 ? lfm f0, 4, \[r0\] ; \(ldc 2, cr0, \[r0\]\) +0+1cc <[^>]+> ed900200 ? lfm f0, 4, \[r0\] ; \(ldc 2, cr0, \[r0\]\) 0+1d0 <[^>]+> ed911210 ? lfm f1, 4, \[r1, #64\].* 0+1d4 <[^>]+> edae22ff ? sfm f2, 4, \[lr, #1020\]!.* 0+1d8 <[^>]+> 0c68f2ff ? sfmeq f7, 3, \[r8\], #-1020.* -0+1dc <[^>]+> eddf6200 ? lfm f6, 2, \[pc\] -0+1e0 <[^>]+> eca8f203 ? sfm f7, 1, \[r8\], #12 +0+1dc <[^>]+> eddf6200 ? lfm f6, 2, \[pc\] ; \(ldcl 2, cr6, \[pc\]\) +0+1e0 <[^>]+> eca8f203 ? sfm f7, 1, \[r8\], #12 ; \(stc 2, cr15, \[r8\], #12\) 0+1e4 <[^>]+> 0d16520c ? lfmeq f5, 4, \[r6, #-48\].* 0+1e8 <[^>]+> 1d42c209 ? sfmne f4, 3, \[r2, #-36\].* 0+1ec <[^>]+> 1d62c209 ? sfmne f4, 3, \[r2, #-36\]!.* diff --git a/gas/testsuite/gas/arm/fp-save.d b/gas/testsuite/gas/arm/fp-save.d index d32d93065fd..ddf1beb881a 100644 --- a/gas/testsuite/gas/arm/fp-save.d +++ b/gas/testsuite/gas/arm/fp-save.d @@ -6,4 +6,4 @@ .*: *file format .*arm.* Disassembly of section .text: -0+00 <[^>]*> ed2dc203[ ]+sfm[ ]+f4, 1, \[sp, #-12\]! +0+00 <[^>]*> ed2dc203[ ]+sfm[ ]+f4, 1, \[sp, #-12\]! ; \(stc 2, cr12, \[sp, #-12\]!\) diff --git a/gas/testsuite/gas/arm/fpa-mem.d b/gas/testsuite/gas/arm/fpa-mem.d index 4a638e1f900..18000b9dfc9 100644 --- a/gas/testsuite/gas/arm/fpa-mem.d +++ b/gas/testsuite/gas/arm/fpa-mem.d @@ -24,11 +24,11 @@ Disassembly of section .text: 0+34 <[^>]*> ec600101 ? stfe f0, \[r0\], #-4 0+38 <[^>]*> edc08100 ? stfp f0, \[r0\] 0+3c <[^>]*> ec608101 ? stfp f0, \[r0\], #-4 -0+40 <[^>]*> ed900200 ? lfm f0, 4, \[r0\] -0+44 <[^>]*> ed900200 ? lfm f0, 4, \[r0\] +0+40 <[^>]*> ed900200 ? lfm f0, 4, \[r0\] ; \(ldc 2, cr0, \[r0\]\) +0+44 <[^>]*> ed900200 ? lfm f0, 4, \[r0\] ; \(ldc 2, cr0, \[r0\]\) 0+48 <[^>]*> ed10020c ? lfm f0, 4, \[r0, #-48\].* -0+4c <[^>]*> ed800200 ? sfm f0, 4, \[r0\] +0+4c <[^>]*> ed800200 ? sfm f0, 4, \[r0\] ; \(stc 2, cr0, \[r0\]\) 0+50 <[^>]*> ed00020c ? sfm f0, 4, \[r0, #-48\].* -0+54 <[^>]*> ed800200 ? sfm f0, 4, \[r0\] +0+54 <[^>]*> ed800200 ? sfm f0, 4, \[r0\] ; \(stc 2, cr0, \[r0\]\) 0+58 <[^>]*> 5d800100 ? stfpls f0, \[r0\] 0+5c <[^>]*> 5d800100 ? stfpls f0, \[r0\] diff --git a/gas/testsuite/gas/arm/group-reloc-alu.d b/gas/testsuite/gas/arm/group-reloc-alu.d index ba2c6a68ec2..327de740535 100644 --- a/gas/testsuite/gas/arm/group-reloc-alu.d +++ b/gas/testsuite/gas/arm/group-reloc-alu.d @@ -165,4 +165,4 @@ Disassembly of section .text: 138: R_ARM_ALU_SB_G0_NC localsym 0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 13c: R_ARM_ALU_SB_G1_NC localsym -0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0 ; 0x0 +0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0 diff --git a/gas/testsuite/gas/arm/group-reloc-ldr.d b/gas/testsuite/gas/arm/group-reloc-ldr.d index 07bc98368d7..cd41b264aa3 100644 --- a/gas/testsuite/gas/arm/group-reloc-ldr.d +++ b/gas/testsuite/gas/arm/group-reloc-ldr.d @@ -197,4 +197,4 @@ Disassembly of section .text: 178: R_ARM_LDR_SB_G1 localsym 0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].* 17c: R_ARM_LDR_SB_G2 localsym -0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0 ; 0x0 +0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0 diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs.d b/gas/testsuite/gas/arm/group-reloc-ldrs.d index 5c3d883a787..49b8f092341 100644 --- a/gas/testsuite/gas/arm/group-reloc-ldrs.d +++ b/gas/testsuite/gas/arm/group-reloc-ldrs.d @@ -5,244 +5,244 @@ .*: +file format .*arm.* Disassembly of section .text: -0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff 0: R_ARM_LDRS_PC_G1 f -0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff 4: R_ARM_LDRS_PC_G2 f -0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff 8: R_ARM_LDRS_SB_G0 f -0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff c: R_ARM_LDRS_SB_G1 f -0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff 10: R_ARM_LDRS_SB_G2 f -0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff 14: R_ARM_LDRS_PC_G1 f -0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff 18: R_ARM_LDRS_PC_G2 f -0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff 1c: R_ARM_LDRS_SB_G0 f -0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff 20: R_ARM_LDRS_SB_G1 f -0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff 24: R_ARM_LDRS_SB_G2 f -0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff 28: R_ARM_LDRS_PC_G1 f -0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff 2c: R_ARM_LDRS_PC_G2 f -0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff 30: R_ARM_LDRS_SB_G0 f -0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff 34: R_ARM_LDRS_SB_G1 f -0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff 38: R_ARM_LDRS_SB_G2 f -0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff 3c: R_ARM_LDRS_PC_G1 f -0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff 40: R_ARM_LDRS_PC_G2 f -0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff 44: R_ARM_LDRS_SB_G0 f -0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff 48: R_ARM_LDRS_SB_G1 f -0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff 4c: R_ARM_LDRS_SB_G2 f -0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff 50: R_ARM_LDRS_PC_G1 f -0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff 54: R_ARM_LDRS_PC_G2 f -0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff 58: R_ARM_LDRS_SB_G0 f -0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff 5c: R_ARM_LDRS_SB_G1 f -0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff 60: R_ARM_LDRS_SB_G2 f -0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff 64: R_ARM_LDRS_PC_G1 f -0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff 68: R_ARM_LDRS_PC_G2 f -0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff 6c: R_ARM_LDRS_SB_G0 f -0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff 70: R_ARM_LDRS_SB_G1 f -0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff 74: R_ARM_LDRS_SB_G2 f -0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01 78: R_ARM_LDRS_PC_G1 f -0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01 7c: R_ARM_LDRS_PC_G2 f -0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01 80: R_ARM_LDRS_SB_G0 f -0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01 84: R_ARM_LDRS_SB_G1 f -0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01 88: R_ARM_LDRS_SB_G2 f -0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01 8c: R_ARM_LDRS_PC_G1 f -0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01 90: R_ARM_LDRS_PC_G2 f -0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01 94: R_ARM_LDRS_SB_G0 f -0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01 98: R_ARM_LDRS_SB_G1 f -0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01 9c: R_ARM_LDRS_SB_G2 f -0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01 a0: R_ARM_LDRS_PC_G1 f -0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01 a4: R_ARM_LDRS_PC_G2 f -0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01 a8: R_ARM_LDRS_SB_G0 f -0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01 ac: R_ARM_LDRS_SB_G1 f -0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01 b0: R_ARM_LDRS_SB_G2 f -0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01 b4: R_ARM_LDRS_PC_G1 f -0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01 b8: R_ARM_LDRS_PC_G2 f -0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01 bc: R_ARM_LDRS_SB_G0 f -0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01 c0: R_ARM_LDRS_SB_G1 f -0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01 c4: R_ARM_LDRS_SB_G2 f -0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01 c8: R_ARM_LDRS_PC_G1 f -0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01 cc: R_ARM_LDRS_PC_G2 f -0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01 d0: R_ARM_LDRS_SB_G0 f -0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01 d4: R_ARM_LDRS_SB_G1 f -0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01 d8: R_ARM_LDRS_SB_G2 f -0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01 dc: R_ARM_LDRS_PC_G1 f -0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01 e0: R_ARM_LDRS_PC_G2 f -0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01 e4: R_ARM_LDRS_SB_G0 f -0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01 e8: R_ARM_LDRS_SB_G1 f -0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01 ec: R_ARM_LDRS_SB_G2 f -0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff f0: R_ARM_LDRS_PC_G1 localsym -0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff f4: R_ARM_LDRS_PC_G2 localsym -0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff f8: R_ARM_LDRS_SB_G0 localsym -0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff fc: R_ARM_LDRS_SB_G1 localsym -0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff 100: R_ARM_LDRS_SB_G2 localsym -0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff 104: R_ARM_LDRS_PC_G1 localsym -0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff 108: R_ARM_LDRS_PC_G2 localsym -0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff 10c: R_ARM_LDRS_SB_G0 localsym -0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff 110: R_ARM_LDRS_SB_G1 localsym -0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff 114: R_ARM_LDRS_SB_G2 localsym -0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff 118: R_ARM_LDRS_PC_G1 localsym -0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff 11c: R_ARM_LDRS_PC_G2 localsym -0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff 120: R_ARM_LDRS_SB_G0 localsym -0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff 124: R_ARM_LDRS_SB_G1 localsym -0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff 128: R_ARM_LDRS_SB_G2 localsym -0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff 12c: R_ARM_LDRS_PC_G1 localsym -0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff 130: R_ARM_LDRS_PC_G2 localsym -0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff 134: R_ARM_LDRS_SB_G0 localsym -0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff 138: R_ARM_LDRS_SB_G1 localsym -0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff 13c: R_ARM_LDRS_SB_G2 localsym -0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff 140: R_ARM_LDRS_PC_G1 localsym -0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff 144: R_ARM_LDRS_PC_G2 localsym -0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff 148: R_ARM_LDRS_SB_G0 localsym -0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff 14c: R_ARM_LDRS_SB_G1 localsym -0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff 150: R_ARM_LDRS_SB_G2 localsym -0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff 154: R_ARM_LDRS_PC_G1 localsym -0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff 158: R_ARM_LDRS_PC_G2 localsym -0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff 15c: R_ARM_LDRS_SB_G0 localsym -0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff 160: R_ARM_LDRS_SB_G1 localsym -0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff 164: R_ARM_LDRS_SB_G2 localsym -0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01 168: R_ARM_LDRS_PC_G1 localsym -0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01 16c: R_ARM_LDRS_PC_G2 localsym -0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01 170: R_ARM_LDRS_SB_G0 localsym -0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01 174: R_ARM_LDRS_SB_G1 localsym -0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01 178: R_ARM_LDRS_SB_G2 localsym -0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01 17c: R_ARM_LDRS_PC_G1 localsym -0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01 180: R_ARM_LDRS_PC_G2 localsym -0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01 184: R_ARM_LDRS_SB_G0 localsym -0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01 188: R_ARM_LDRS_SB_G1 localsym -0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01 18c: R_ARM_LDRS_SB_G2 localsym -0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01 190: R_ARM_LDRS_PC_G1 localsym -0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01 194: R_ARM_LDRS_PC_G2 localsym -0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01 198: R_ARM_LDRS_SB_G0 localsym -0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01 19c: R_ARM_LDRS_SB_G1 localsym -0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01 1a0: R_ARM_LDRS_SB_G2 localsym -0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01 1a4: R_ARM_LDRS_PC_G1 localsym -0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01 1a8: R_ARM_LDRS_PC_G2 localsym -0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01 1ac: R_ARM_LDRS_SB_G0 localsym -0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01 1b0: R_ARM_LDRS_SB_G1 localsym -0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01 1b4: R_ARM_LDRS_SB_G2 localsym -0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01 1b8: R_ARM_LDRS_PC_G1 localsym -0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01 1bc: R_ARM_LDRS_PC_G2 localsym -0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01 1c0: R_ARM_LDRS_SB_G0 localsym -0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01 1c4: R_ARM_LDRS_SB_G1 localsym -0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01 1c8: R_ARM_LDRS_SB_G2 localsym -0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01 1cc: R_ARM_LDRS_PC_G1 localsym -0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01 1d0: R_ARM_LDRS_PC_G2 localsym -0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01 1d4: R_ARM_LDRS_SB_G0 localsym -0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01 1d8: R_ARM_LDRS_SB_G1 localsym -0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01 1dc: R_ARM_LDRS_SB_G2 localsym -0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0 ; 0x0 +0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0 diff --git a/gas/testsuite/gas/arm/immed.d b/gas/testsuite/gas/arm/immed.d index 62b7eb72e54..42ca13bc327 100644 --- a/gas/testsuite/gas/arm/immed.d +++ b/gas/testsuite/gas/arm/immed.d @@ -5,12 +5,12 @@ .*: +file format .*arm.* Disassembly of section .text: -0+0000 <[^>]+> e3a00000 ? mov r0, #0 ; 0x0 -0+0004 <[^>]+> e3e00003 ? mvn r0, #3 ; 0x3 +0+0000 <[^>]+> e3a00000 ? mov r0, #0 +0+0004 <[^>]+> e3e00003 ? mvn r0, #3 0+0008 <[^>]+> e51f0010 ? ldr r0, \[pc, #-16\] ; 0+0 <[^>]+> 0+000c <[^>]+> e51f0014 ? ldr r0, \[pc, #-20\] ; 0+0 <[^>]+> \.\.\. -0+1010 <[^>]+> e3a00008 ? mov r0, #8 ; 0x8 +0+1010 <[^>]+> e3a00008 ? mov r0, #8 0+1014 <[^>]+> e59f00e4 ? ldr r0, \[pc, #228\] ; 0+1100 <[^>]+> -0+1018 <[^>]+> e1a00000 ? nop \(mov r0,r0\) -0+101c <[^>]+> e1a00000 ? nop \(mov r0,r0\) +0+1018 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) +0+101c <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) diff --git a/gas/testsuite/gas/arm/inst.d b/gas/testsuite/gas/arm/inst.d index 4d56e8eca3d..d2ea4352a72 100644 --- a/gas/testsuite/gas/arm/inst.d +++ b/gas/testsuite/gas/arm/inst.d @@ -9,7 +9,7 @@ .*: +file format .*arm.* Disassembly of section .text: -0+000 <[^>]*> e3a00000 ? mov r0, #0 ; 0x0 +0+000 <[^>]*> e3a00000 ? mov r0, #0 0+004 <[^>]*> e1a01002 ? mov r1, r2 0+008 <[^>]*> e1a03184 ? lsl r3, r4, #3 0+00c <[^>]*> e1a05736 ? lsr r5, r6, r7 @@ -35,79 +35,79 @@ Disassembly of section .text: 0+05c <[^>]*> 31a01003 ? movcc r1, r3 0+060 <[^>]*> e1b00008 ? movs r0, r8 0+064 <[^>]*> 31b00007 ? movscc r0, r7 -0+068 <[^>]*> e281000a ? add r0, r1, #10 ; 0xa +0+068 <[^>]*> e281000a ? add r0, r1, #10 0+06c <[^>]*> e0832004 ? add r2, r3, r4 0+070 <[^>]*> e0865287 ? add r5, r6, r7, lsl #5 0+074 <[^>]*> e0821113 ? add r1, r2, r3, lsl r1 -0+078 <[^>]*> e201000a ? and r0, r1, #10 ; 0xa +0+078 <[^>]*> e201000a ? and r0, r1, #10 0+07c <[^>]*> e0032004 ? and r2, r3, r4 0+080 <[^>]*> e0065287 ? and r5, r6, r7, lsl #5 0+084 <[^>]*> e0021113 ? and r1, r2, r3, lsl r1 -0+088 <[^>]*> e221000a ? eor r0, r1, #10 ; 0xa +0+088 <[^>]*> e221000a ? eor r0, r1, #10 0+08c <[^>]*> e0232004 ? eor r2, r3, r4 0+090 <[^>]*> e0265287 ? eor r5, r6, r7, lsl #5 0+094 <[^>]*> e0221113 ? eor r1, r2, r3, lsl r1 -0+098 <[^>]*> e241000a ? sub r0, r1, #10 ; 0xa +0+098 <[^>]*> e241000a ? sub r0, r1, #10 0+09c <[^>]*> e0432004 ? sub r2, r3, r4 0+0a0 <[^>]*> e0465287 ? sub r5, r6, r7, lsl #5 0+0a4 <[^>]*> e0421113 ? sub r1, r2, r3, lsl r1 -0+0a8 <[^>]*> e2a1000a ? adc r0, r1, #10 ; 0xa +0+0a8 <[^>]*> e2a1000a ? adc r0, r1, #10 0+0ac <[^>]*> e0a32004 ? adc r2, r3, r4 0+0b0 <[^>]*> e0a65287 ? adc r5, r6, r7, lsl #5 0+0b4 <[^>]*> e0a21113 ? adc r1, r2, r3, lsl r1 -0+0b8 <[^>]*> e2c1000a ? sbc r0, r1, #10 ; 0xa +0+0b8 <[^>]*> e2c1000a ? sbc r0, r1, #10 0+0bc <[^>]*> e0c32004 ? sbc r2, r3, r4 0+0c0 <[^>]*> e0c65287 ? sbc r5, r6, r7, lsl #5 0+0c4 <[^>]*> e0c21113 ? sbc r1, r2, r3, lsl r1 -0+0c8 <[^>]*> e261000a ? rsb r0, r1, #10 ; 0xa +0+0c8 <[^>]*> e261000a ? rsb r0, r1, #10 0+0cc <[^>]*> e0632004 ? rsb r2, r3, r4 0+0d0 <[^>]*> e0665287 ? rsb r5, r6, r7, lsl #5 0+0d4 <[^>]*> e0621113 ? rsb r1, r2, r3, lsl r1 -0+0d8 <[^>]*> e2e1000a ? rsc r0, r1, #10 ; 0xa +0+0d8 <[^>]*> e2e1000a ? rsc r0, r1, #10 0+0dc <[^>]*> e0e32004 ? rsc r2, r3, r4 0+0e0 <[^>]*> e0e65287 ? rsc r5, r6, r7, lsl #5 0+0e4 <[^>]*> e0e21113 ? rsc r1, r2, r3, lsl r1 -0+0e8 <[^>]*> e381000a ? orr r0, r1, #10 ; 0xa +0+0e8 <[^>]*> e381000a ? orr r0, r1, #10 0+0ec <[^>]*> e1832004 ? orr r2, r3, r4 0+0f0 <[^>]*> e1865287 ? orr r5, r6, r7, lsl #5 0+0f4 <[^>]*> e1821113 ? orr r1, r2, r3, lsl r1 -0+0f8 <[^>]*> e3c1000a ? bic r0, r1, #10 ; 0xa +0+0f8 <[^>]*> e3c1000a ? bic r0, r1, #10 0+0fc <[^>]*> e1c32004 ? bic r2, r3, r4 0+100 <[^>]*> e1c65287 ? bic r5, r6, r7, lsl #5 0+104 <[^>]*> e1c21113 ? bic r1, r2, r3, lsl r1 -0+108 <[^>]*> e3e0000a ? mvn r0, #10 ; 0xa +0+108 <[^>]*> e3e0000a ? mvn r0, #10 0+10c <[^>]*> e1e02004 ? mvn r2, r4 0+110 <[^>]*> e1e05287 ? mvn r5, r7, lsl #5 0+114 <[^>]*> e1e01113 ? mvn r1, r3, lsl r1 -0+118 <[^>]*> e310000a ? tst r0, #10 ; 0xa +0+118 <[^>]*> e310000a ? tst r0, #10 0+11c <[^>]*> e1120004 ? tst r2, r4 0+120 <[^>]*> e1150287 ? tst r5, r7, lsl #5 0+124 <[^>]*> e1110113 ? tst r1, r3, lsl r1 -0+128 <[^>]*> e330000a ? teq r0, #10 ; 0xa +0+128 <[^>]*> e330000a ? teq r0, #10 0+12c <[^>]*> e1320004 ? teq r2, r4 0+130 <[^>]*> e1350287 ? teq r5, r7, lsl #5 0+134 <[^>]*> e1310113 ? teq r1, r3, lsl r1 -0+138 <[^>]*> e350000a ? cmp r0, #10 ; 0xa +0+138 <[^>]*> e350000a ? cmp r0, #10 0+13c <[^>]*> e1520004 ? cmp r2, r4 0+140 <[^>]*> e1550287 ? cmp r5, r7, lsl #5 0+144 <[^>]*> e1510113 ? cmp r1, r3, lsl r1 -0+148 <[^>]*> e370000a ? cmn r0, #10 ; 0xa +0+148 <[^>]*> e370000a ? cmn r0, #10 0+14c <[^>]*> e1720004 ? cmn r2, r4 0+150 <[^>]*> e1750287 ? cmn r5, r7, lsl #5 0+154 <[^>]*> e1710113 ? cmn r1, r3, lsl r1 -0+158 <[^>]*> e330f00a ? teqp r0, #10 ; 0xa +0+158 <[^>]*> e330f00a ? teqp r0, #10 0+15c <[^>]*> e132f004 ? teqp r2, r4 0+160 <[^>]*> e135f287 ? teqp r5, r7, lsl #5 0+164 <[^>]*> e131f113 ? teqp r1, r3, lsl r1 -0+168 <[^>]*> e370f00a ? cmnp r0, #10 ; 0xa +0+168 <[^>]*> e370f00a ? cmnp r0, #10 0+16c <[^>]*> e172f004 ? cmnp r2, r4 0+170 <[^>]*> e175f287 ? cmnp r5, r7, lsl #5 0+174 <[^>]*> e171f113 ? cmnp r1, r3, lsl r1 -0+178 <[^>]*> e350f00a ? cmpp r0, #10 ; 0xa +0+178 <[^>]*> e350f00a ? cmpp r0, #10 0+17c <[^>]*> e152f004 ? cmpp r2, r4 0+180 <[^>]*> e155f287 ? cmpp r5, r7, lsl #5 0+184 <[^>]*> e151f113 ? cmpp r1, r3, lsl r1 -0+188 <[^>]*> e310f00a ? tstp r0, #10 ; 0xa +0+188 <[^>]*> e310f00a ? tstp r0, #10 0+18c <[^>]*> e112f004 ? tstp r2, r4 0+190 <[^>]*> e115f287 ? tstp r5, r7, lsl #5 0+194 <[^>]*> e111f113 ? tstp r1, r3, lsl r1 diff --git a/gas/testsuite/gas/arm/iwmmxt.d b/gas/testsuite/gas/arm/iwmmxt.d index 5016796506a..1739ebb476f 100644 --- a/gas/testsuite/gas/arm/iwmmxt.d +++ b/gas/testsuite/gas/arm/iwmmxt.d @@ -168,4 +168,4 @@ Disassembly of section .text: 0+280 <[^>]*> ae377007[ ]+wandnge[ ]+wr7, wr7, wr7 0+284 <[^>]*> ee080110[ ]+tmcr[ ]+wcgr0, r0 0+288 <[^>]*> ee1a1110[ ]+tmrc[ ]+r1, wcgr2 -0+28c <[^>]*> e1a00000[ ]+nop[ ]+\(mov r0,r0\) +0+28c <[^>]*> e1a00000[ ]+nop[ ]+; \(mov r0, r0\) diff --git a/gas/testsuite/gas/arm/ldconst.d b/gas/testsuite/gas/arm/ldconst.d index 6ce123d2edd..3d06378513e 100644 --- a/gas/testsuite/gas/arm/ldconst.d +++ b/gas/testsuite/gas/arm/ldconst.d @@ -5,22 +5,22 @@ .*: +file format .*arm.* Disassembly of section .text: -0+00 <[^>]*> e3a00000 ? mov r0, #0 ; 0x0 +0+00 <[^>]*> e3a00000 ? mov r0, #0 0+04 <[^>]*> e3a004ff ? mov r0, #-16777216 ; 0xff000000 -0+08 <[^>]*> e3e00000 ? mvn r0, #0 ; 0x0 +0+08 <[^>]*> e3e00000 ? mvn r0, #0 0+0c <[^>]*> e51f0004 ? ldr r0, \[pc, #-4\] ; 0+10 <[^>]*> 0+10 <[^>]*> 0fff0000 ? .* -0+14 <[^>]*> e3a0e000 ? mov lr, #0 ; 0x0 +0+14 <[^>]*> e3a0e000 ? mov lr, #0 0+18 <[^>]*> e3a0e8ff ? mov lr, #16711680 ; 0xff0000 0+1c <[^>]*> e3e0e8ff ? mvn lr, #16711680 ; 0xff0000 0+20 <[^>]*> e51fe004 ? ldr lr, \[pc, #-4\] ; 0+24 <[^>]*> 0+24 <[^>]*> 00fff000 ? .* -0+28 <[^>]*> 03a00000 ? moveq r0, #0 ; 0x0 +0+28 <[^>]*> 03a00000 ? moveq r0, #0 0+2c <[^>]*> 03a00cff ? moveq r0, #65280 ; 0xff00 0+30 <[^>]*> 03e00cff ? mvneq r0, #65280 ; 0xff00 0+34 <[^>]*> 051f0004 ? ldreq r0, \[pc, #-4\] ; 0+38 <[^>]*> 0+38 <[^>]*> 000fff00 ? .* -0+3c <[^>]*> 43a0b000 ? movmi fp, #0 ; 0x0 +0+3c <[^>]*> 43a0b000 ? movmi fp, #0 0+40 <[^>]*> 43a0b0ff ? movmi fp, #255 ; 0xff 0+44 <[^>]*> 43e0b0ff ? mvnmi fp, #255 ; 0xff 0+48 <[^>]*> 451fb004 ? ldrmi fp, \[pc, #-4\] ; 0+4c <[^>]*> diff --git a/gas/testsuite/gas/arm/macro1.d b/gas/testsuite/gas/arm/macro1.d index c29bb626156..1e28877feda 100644 --- a/gas/testsuite/gas/arm/macro1.d +++ b/gas/testsuite/gas/arm/macro1.d @@ -7,6 +7,6 @@ Disassembly of section .text: 0+0 <[^>]*> e8bd8030 ? pop {r4, r5, pc} -0+4 <[^>]*> e1a00000 ? nop \(mov r0,r0\) -0+8 <[^>]*> e1a00000 ? nop \(mov r0,r0\) -0+c <[^>]*> e1a00000 ? nop \(mov r0,r0\) +0+4 <[^>]*> e1a00000 ? nop ; \(mov r0, r0\) +0+8 <[^>]*> e1a00000 ? nop ; \(mov r0, r0\) +0+c <[^>]*> e1a00000 ? nop ; \(mov r0, r0\) diff --git a/gas/testsuite/gas/arm/mapmisc.d b/gas/testsuite/gas/arm/mapmisc.d index b2954b72ebc..51170216dc2 100644 --- a/gas/testsuite/gas/arm/mapmisc.d +++ b/gas/testsuite/gas/arm/mapmisc.d @@ -53,43 +53,43 @@ SYMBOL TABLE: Disassembly of section .text: 00000000 <foo>: - 0: e1a00000 nop \(mov r0,r0\) + 0: e1a00000 nop ; \(mov r0, r0\) 4: 64636261 .word 0x64636261 - 8: e1a00000 nop \(mov r0,r0\) + 8: e1a00000 nop ; \(mov r0, r0\) c: 00636261 .word 0x00636261 - 10: e1a00000 nop \(mov r0,r0\) + 10: e1a00000 nop ; \(mov r0, r0\) 14: 00676665 .word 0x00676665 - 18: e1a00000 nop \(mov r0,r0\) + 18: e1a00000 nop ; \(mov r0, r0\) 1c: 006a6968 .word 0x006a6968 - 20: e1a00000 nop \(mov r0,r0\) + 20: e1a00000 nop ; \(mov r0, r0\) 24: 0000006b .word 0x0000006b - 28: e1a00000 nop \(mov r0,r0\) + 28: e1a00000 nop ; \(mov r0, r0\) 2c: 0000006c .word 0x0000006c 30: 00000000 .word 0x00000000 - 34: e1a00000 nop \(mov r0,r0\) + 34: e1a00000 nop ; \(mov r0, r0\) 38: 0000006d .word 0x0000006d ... - 48: e1a00000 nop \(mov r0,r0\) + 48: e1a00000 nop ; \(mov r0, r0\) 4c: 3fc00000 .word 0x3fc00000 - 50: e1a00000 nop \(mov r0,r0\) + 50: e1a00000 nop ; \(mov r0, r0\) 54: 40200000 .word 0x40200000 - 58: e1a00000 nop \(mov r0,r0\) + 58: e1a00000 nop ; \(mov r0, r0\) 5c: 00000000 .word 0x00000000 60: 400c0000 .word 0x400c0000 - 64: e1a00000 nop \(mov r0,r0\) + 64: e1a00000 nop ; \(mov r0, r0\) 68: 00000000 .word 0x00000000 6c: 40120000 .word 0x40120000 - 70: e1a00000 nop \(mov r0,r0\) + 70: e1a00000 nop ; \(mov r0, r0\) 74: 00000004 .word 0x00000004 78: 00000004 .word 0x00000004 7c: 00000004 .word 0x00000004 80: 00000004 .word 0x00000004 - 84: e1a00000 nop \(mov r0,r0\) + 84: e1a00000 nop ; \(mov r0, r0\) 88: 00000000 .word 0x00000000 - 8c: e1a00000 nop \(mov r0,r0\) + 8c: e1a00000 nop ; \(mov r0, r0\) 90: 00000000 .word 0x00000000 - 94: e1a00000 nop \(mov r0,r0\) + 94: e1a00000 nop ; \(mov r0, r0\) 98: 00000000 .word 0x00000000 - 9c: e1a00000 nop \(mov r0,r0\) + 9c: e1a00000 nop ; \(mov r0, r0\) a0: 7778797a .word 0x7778797a - a4: e1a00000 nop \(mov r0,r0\) + a4: e1a00000 nop ; \(mov r0, r0\) diff --git a/gas/testsuite/gas/arm/mapsecs.d b/gas/testsuite/gas/arm/mapsecs.d index 52bca8c8952..8cd0baf235c 100644 --- a/gas/testsuite/gas/arm/mapsecs.d +++ b/gas/testsuite/gas/arm/mapsecs.d @@ -29,17 +29,17 @@ SYMBOL TABLE: Disassembly of section .text.f1: 00000000 <f1>: - 0: e1a00000 nop \(mov r0,r0\) - 4: e1a00000 nop \(mov r0,r0\) + 0: e1a00000 nop ; \(mov r0, r0\) + 4: e1a00000 nop ; \(mov r0, r0\) 00000008 <f1a>: - 8: e1a00000 nop \(mov r0,r0\) + 8: e1a00000 nop ; \(mov r0, r0\) Disassembly of section .text.f2: 00000000 <f2>: - 0: e1a00000 nop \(mov r0,r0\) + 0: e1a00000 nop ; \(mov r0, r0\) 4: 00000001 .word 0x00000001 00000008 <f2a>: - 8: e1a00000 nop \(mov r0,r0\) + 8: e1a00000 nop ; \(mov r0, r0\) diff --git a/gas/testsuite/gas/arm/mapshort-eabi.d b/gas/testsuite/gas/arm/mapshort-eabi.d index c6ff62e8a56..4bcc0e1461b 100644 --- a/gas/testsuite/gas/arm/mapshort-eabi.d +++ b/gas/testsuite/gas/arm/mapshort-eabi.d @@ -29,14 +29,14 @@ SYMBOL TABLE: Disassembly of section .text: 0+00 <foo>: - 0: e1a00000 nop \(mov r0,r0\) - 4: 46c0 nop \(mov r8, r8\) - 6: 46c0 nop \(mov r8, r8\) + 0: e1a00000 nop ; \(mov r0, r0\) + 4: 46c0 nop ; \(mov r8, r8\) + 6: 46c0 nop ; \(mov r8, r8\) 8: 00000002 .word 0x00000002 c: 00010001 .word 0x00010001 10: 0003 .short 0x0003 - 12: 46c0 nop \(mov r8, r8\) - 14: 46c0 nop \(mov r8, r8\) + 12: 46c0 nop ; \(mov r8, r8\) + 14: 46c0 nop ; \(mov r8, r8\) 16: 0001 .short 0x0001 18: ebfffff8 bl 0 <foo> 1c: 0008 .short 0x0008 diff --git a/gas/testsuite/gas/arm/mapshort-elf.d b/gas/testsuite/gas/arm/mapshort-elf.d index e59337fe912..38b290e687c 100644 --- a/gas/testsuite/gas/arm/mapshort-elf.d +++ b/gas/testsuite/gas/arm/mapshort-elf.d @@ -28,14 +28,14 @@ SYMBOL TABLE: Disassembly of section .text: 0+00 <foo>: - 0: e1a00000 nop \(mov r0,r0\) - 4: 46c0 nop \(mov r8, r8\) - 6: 46c0 nop \(mov r8, r8\) + 0: e1a00000 nop ; \(mov r0, r0\) + 4: 46c0 nop ; \(mov r8, r8\) + 6: 46c0 nop ; \(mov r8, r8\) 8: 00000002 .word 0x00000002 c: 00010001 .word 0x00010001 10: 0003 .short 0x0003 - 12: 46c0 nop \(mov r8, r8\) - 14: 46c0 nop \(mov r8, r8\) + 12: 46c0 nop ; \(mov r8, r8\) + 14: 46c0 nop ; \(mov r8, r8\) 16: 0001 .short 0x0001 18: ebfffff8 bl 0 <foo> 1c: 0008 .short 0x0008 diff --git a/gas/testsuite/gas/arm/movw-local.d b/gas/testsuite/gas/arm/movw-local.d index 5fc7727fb09..af9562e4ab0 100644 --- a/gas/testsuite/gas/arm/movw-local.d +++ b/gas/testsuite/gas/arm/movw-local.d @@ -5,12 +5,12 @@ .*: +file format .*arm.* Disassembly of section .text: -0[0-9a-f]+ <[^>]+> e3000000 movw r0, #0 ; 0x0 +0[0-9a-f]+ <[^>]+> e3000000 movw r0, #0 0: R_ARM_MOVW_ABS_NC bar -0[0-9a-f]+ <[^>]+> e3400000 movt r0, #0 ; 0x0 +0[0-9a-f]+ <[^>]+> e3400000 movt r0, #0 4: R_ARM_MOVT_ABS bar -0[0-9a-f]+ <[^>]+> f240 0000 movw r0, #0 ; 0x0 +0[0-9a-f]+ <[^>]+> f240 0000 movw r0, #0 8: R_ARM_THM_MOVW_ABS_NC bar -0[0-9a-f]+ <[^>]+> f2c0 0000 movt r0, #0 ; 0x0 +0[0-9a-f]+ <[^>]+> f2c0 0000 movt r0, #0 c: R_ARM_THM_MOVT_ABS bar #... diff --git a/gas/testsuite/gas/arm/neon-ldst-rm.d b/gas/testsuite/gas/arm/neon-ldst-rm.d index 86285d6dc35..813672cd7bc 100644 --- a/gas/testsuite/gas/arm/neon-ldst-rm.d +++ b/gas/testsuite/gas/arm/neon-ldst-rm.d @@ -54,10 +54,10 @@ Disassembly of section \.text: 0[0-9a-f]+ <[^>]+> ed035b01 vstr d5, \[r3, #-4\] 0[0-9a-f]+ <[^>]+> ed835b01 vstr d5, \[r3, #4\] 0[0-9a-f]+ <[^>]+> ed935b00 vldr d5, \[r3\] -0[0-9a-f]+ <[^>]+> ed135b40 vldr d5, \[r3, #-256\] -0[0-9a-f]+ <[^>]+> ed935b40 vldr d5, \[r3, #256\] +0[0-9a-f]+ <[^>]+> ed135b40 vldr d5, \[r3, #-256\].* +0[0-9a-f]+ <[^>]+> ed935b40 vldr d5, \[r3, #256\].* 0[0-9a-f]+ <[^>]+> ed835b00 vstr d5, \[r3\] -0[0-9a-f]+ <[^>]+> ed035b40 vstr d5, \[r3, #-256\] -0[0-9a-f]+ <[^>]+> ed835b40 vstr d5, \[r3, #256\] +0[0-9a-f]+ <[^>]+> ed035b40 vstr d5, \[r3, #-256\].* +0[0-9a-f]+ <[^>]+> ed835b40 vstr d5, \[r3, #256\].* 0[0-9a-f]+ <forward> 000002bc .* 0[0-9a-f]+ <[^>]+> ed1f7b11 vldr d7, \[pc, #-68\] ; 0[0-9a-f]+ <backward> diff --git a/gas/testsuite/gas/arm/offset.d b/gas/testsuite/gas/arm/offset.d index f6957c074ed..1795477f05d 100644 --- a/gas/testsuite/gas/arm/offset.d +++ b/gas/testsuite/gas/arm/offset.d @@ -6,6 +6,6 @@ Disassembly of section .text: 0+0 <[^>]+> e51f0004 ? ldr r0, \[pc, #-4\] ; 0+4 <[^>]+> -0+4 <[^>]+> e1a00000 ? nop \(mov r0,r0\) -0+8 <[^>]+> e1a00000 ? nop \(mov r0,r0\) -0+c <[^>]+> e1a00000 ? nop \(mov r0,r0\) +0+4 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) +0+8 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) +0+c <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) diff --git a/gas/testsuite/gas/arm/reg-alias.d b/gas/testsuite/gas/arm/reg-alias.d index d9b4be29acb..06e87d83755 100644 --- a/gas/testsuite/gas/arm/reg-alias.d +++ b/gas/testsuite/gas/arm/reg-alias.d @@ -5,6 +5,6 @@ Disassembly of section .text: 0+0 <.*> ee060f10 mcr 15, 0, r0, cr6, cr0, \{0\} -0+4 <.*> e1a00000 nop \(mov r0,r0\) -0+8 <.*> e1a00000 nop \(mov r0,r0\) -0+c <.*> e1a00000 nop \(mov r0,r0\) +0+4 <.*> e1a00000 nop ; \(mov r0, r0\) +0+8 <.*> e1a00000 nop ; \(mov r0, r0\) +0+c <.*> e1a00000 nop ; \(mov r0, r0\) diff --git a/gas/testsuite/gas/arm/relax_load_align.d b/gas/testsuite/gas/arm/relax_load_align.d index 0147b49a686..776fc3bb473 100644 --- a/gas/testsuite/gas/arm/relax_load_align.d +++ b/gas/testsuite/gas/arm/relax_load_align.d @@ -5,5 +5,5 @@ Disassembly of section .text: 0+000 <[^>]+> f510 707a adds.w r0, r0, #1000 ; 0x3e8 -0+004 <[^>]+> 4800 ldr r0, \[pc, #0\] \(0+008 <[^>]+>\) -0+006 <[^>]+> 4800 ldr r0, \[pc, #0\] \(0+008 <[^>]+>\) +0+004 <[^>]+> 4800 ldr r0, \[pc, #0\] ; \(0+008 <[^>]+>\) +0+006 <[^>]+> 4800 ldr r0, \[pc, #0\] ; \(0+008 <[^>]+>\) diff --git a/gas/testsuite/gas/arm/tcompat.d b/gas/testsuite/gas/arm/tcompat.d index b333a31436a..6e378bfb4ed 100644 --- a/gas/testsuite/gas/arm/tcompat.d +++ b/gas/testsuite/gas/arm/tcompat.d @@ -28,10 +28,10 @@ Disassembly of section .text: 0+44 <[^>]*> 91a00970 ? rorls r0, r0, r9 0+48 <[^>]*> e1b008e0 ? rors r0, r0, #17 0+4c <[^>]*> e1a008e9 ? ror r0, r9, #17 -0+50 <[^>]*> e2690000 ? rsb r0, r9, #0 ; 0x0 -0+54 <[^>]*> e2709000 ? rsbs r9, r0, #0 ; 0x0 -0+58 <[^>]*> 92600000 ? rsbls r0, r0, #0 ; 0x0 -0+5c <[^>]*> 92799000 ? rsbsls r9, r9, #0 ; 0x0 +0+50 <[^>]*> e2690000 ? rsb r0, r9, #0 +0+54 <[^>]*> e2709000 ? rsbs r9, r0, #0 +0+58 <[^>]*> 92600000 ? rsbls r0, r0, #0 +0+5c <[^>]*> 92799000 ? rsbsls r9, r9, #0 0+60 <[^>]*> e92d000e ? push {r1, r2, r3} 0+64 <[^>]*> 992d8154 ? pushls {r2, r4, r6, r8, pc} 0+68 <[^>]*> e8bd000e ? pop {r1, r2, r3} @@ -47,8 +47,8 @@ Disassembly of section .text: 0+90 <[^>]*> e1800001 ? orr r0, r0, r1 0+94 <[^>]*> e1c00001 ? bic r0, r0, r1 0+98 <[^>]*> e0000091 ? mul r0, r1, r0 -0+9c <[^>]*> e1a00000 ? nop \(mov r0,r0\) +0+9c <[^>]*> e1a00000 ? nop ; \(mov r0, r0\) 0+a0 <[^>]*> e1a00069 ? rrx r0, r9 0+a4 <[^>]*> e1b09060 ? rrxs r9, r0 -0+a8 <[^>]*> e1a00000 ? nop \(mov r0,r0\) -0+ac <[^>]*> e1a00000 ? nop \(mov r0,r0\) +0+a8 <[^>]*> e1a00000 ? nop ; \(mov r0, r0\) +0+ac <[^>]*> e1a00000 ? nop ; \(mov r0, r0\) diff --git a/gas/testsuite/gas/arm/tcompat2.d b/gas/testsuite/gas/arm/tcompat2.d index ba39db1fad1..4c6de6160ad 100644 --- a/gas/testsuite/gas/arm/tcompat2.d +++ b/gas/testsuite/gas/arm/tcompat2.d @@ -20,7 +20,7 @@ Disassembly of section .text: 0+12 <[^>]*> 4308 * orrs r0, r1 0+14 <[^>]*> 4388 * bics r0, r1 0+16 <[^>]*> 4188 * sbcs r0, r1 -0+18 <[^>]*> 46c0 * nop \(mov r8, r8\) -0+1a <[^>]*> 46c0 * nop \(mov r8, r8\) -0+1c <[^>]*> 46c0 * nop \(mov r8, r8\) -0+1e <[^>]*> 46c0 * nop \(mov r8, r8\) +0+18 <[^>]*> 46c0 * nop ; \(mov r8, r8\) +0+1a <[^>]*> 46c0 * nop ; \(mov r8, r8\) +0+1c <[^>]*> 46c0 * nop ; \(mov r8, r8\) +0+1e <[^>]*> 46c0 * nop ; \(mov r8, r8\) diff --git a/gas/testsuite/gas/arm/thumb-eabi.d b/gas/testsuite/gas/arm/thumb-eabi.d index 64c04f93d0b..188a2e2e431 100644 --- a/gas/testsuite/gas/arm/thumb-eabi.d +++ b/gas/testsuite/gas/arm/thumb-eabi.d @@ -47,18 +47,18 @@ Disassembly of section \.text: 0+04a <[^>]+> 45f4 cmp ip, lr 0+04c <[^>]+> 4648 mov r0, r9 0+04e <[^>]+> 46a1 mov r9, r4 -0+050 <[^>]+> 46c0 nop \(mov r8, r8\) +0+050 <[^>]+> 46c0 nop ; \(mov r8, r8\) 0+052 <[^>]+> 4738 bx r7 0+054 <[^>]+> 4740 bx r8 -0+056 <[^>]+> 46c0 nop \(mov r8, r8\) +0+056 <[^>]+> 46c0 nop ; \(mov r8, r8\) 0+058 <[^>]+> 4778 bx pc -0+05a <[^>]+> 4b20 ldr r3, \[pc, #128\] \(0+0dc <[^>]+>\) -0+05c <[^>]+> 4c02 ldr r4, \[pc, #8\] \(0+068 <[^>]+>\) +0+05a <[^>]+> 4b20 ldr r3, \[pc, #128\] ; \(0+0dc <[^>]+>\) +0+05c <[^>]+> 4c02 ldr r4, \[pc, #8\] ; \(0+068 <[^>]+>\) 0+05e <[^>]+> 5088 str r0, \[r1, r2\] 0+060 <[^>]+> 5511 strb r1, \[r2, r4\] 0+062 <[^>]+> 59f5 ldr r5, \[r6, r7\] 0+064 <[^>]+> 5d62 ldrb r2, \[r4, r5\] -0+066 <[^>]+> 46c0 nop \(mov r8, r8\) +0+066 <[^>]+> 46c0 nop ; \(mov r8, r8\) 0+068 <[^>]+> 52d1 strh r1, \[r2, r3\] 0+06a <[^>]+> 5a23 ldrh r3, \[r4, r0\] 0+06c <[^>]+> 57f1 ldrsb r1, \[r6, r7\] @@ -75,7 +75,7 @@ Disassembly of section \.text: 0+082 <[^>]+> 93ff str r3, \[sp, #1020\].* 0+084 <[^>]+> 990b ldr r1, \[sp, #44\].* 0+086 <[^>]+> 9a00 ldr r2, \[sp, #0\] -0+088 <[^>]+> a7ff add r7, pc, #1020 \(adr r7, 0+488 <[^>]+>\) +0+088 <[^>]+> a7ff add r7, pc, #1020 ; \(adr r7, 0+488 <[^>]+>\) 0+08a <[^>]+> ac80 add r4, sp, #512.* 0+08c <[^>]+> b043 add sp, #268.* 0+08e <[^>]+> b09a sub sp, #104.* @@ -111,16 +111,16 @@ Disassembly of section \.text: 0+0ca <[^>]+> b07f add sp, #508.* 0+0cc <[^>]+> b0ff sub sp, #508.* 0+0ce <[^>]+> a8ff add r0, sp, #1020.* -0+0d0 <[^>]+> a0ff add r0, pc, #1020 \(adr r0, 0+4d0 <[^>]+>\) +0+0d0 <[^>]+> a0ff add r0, pc, #1020 ; \(adr r0, 0+4d0 <[^>]+>\) 0+0d2 <[^>]+> b01a add sp, #104.* 0+0d4 <[^>]+> b09a sub sp, #104.* 0+0d6 <[^>]+> a81a add r0, sp, #104.* -0+0d8 <[^>]+> a01a add r0, pc, #104 \(adr r0, 0+144 <[^>]+>\) +0+0d8 <[^>]+> a01a add r0, pc, #104 ; \(adr r0, 0+144 <[^>]+>\) 0+0da <[^>]+> 3168 adds r1, #104.* 0+0dc <[^>]+> 2668 movs r6, #104.* 0+0de <[^>]+> 2f68 cmp r7, #104.* -0+0e0 <[^>]+> 46c0 nop \(mov r8, r8\) -0+0e2 <[^>]+> 46c0 nop \(mov r8, r8\) +0+0e0 <[^>]+> 46c0 nop ; \(mov r8, r8\) +0+0e2 <[^>]+> 46c0 nop ; \(mov r8, r8\) 0+0e4 <[^>]+> eafffffe b 0+0e4 <[^>]+> 0+0e8 <[^>]+> ea000011 b 0+134 <[^>]+> 0+0ec <[^>]+> ebfffffc bl 0+0e4 <[^>]+> @@ -128,14 +128,14 @@ Disassembly of section \.text: 0+0f4 <[^>]+> e12fff10 bx r0 .*: R_ARM_V4BX.* 0+0f8 <[^>]+> ef123456 (swi|svc) 0x00123456 -0+0fc <[^>]+> a004 add r0, pc, #16 \(adr r0, 0+110 <[^>]+>\) +0+0fc <[^>]+> a004 add r0, pc, #16 ; \(adr r0, 0+110 <[^>]+>\) 0+0fe <[^>]+> e77f b.n 0+000 <[^>]+> 0+100 <[^>]+> e018 b.n 0+134 <[^>]+> 0+102 <[^>]+> f7ff ff7d bl 0+000 <[^>]+> 0+106 <[^>]+> f000 f815 bl 0+134 <[^>]+> 0+10a <[^>]+> 4700 bx r0 0+10c <[^>]+> dfff (swi|svc) 255.* -0+10e <[^>]+> 46c0 nop \(mov r8, r8\) +0+10e <[^>]+> 46c0 nop ; \(mov r8, r8\) 0+110 <[^>]+> d010 beq.n 0+134 <[^>]+> 0+112 <[^>]+> d10f bne.n 0+134 <[^>]+> 0+114 <[^>]+> d20e bcs.n 0+134 <[^>]+> @@ -157,9 +157,9 @@ Disassembly of section \.text: 0+134 <[^>]+> f000 fc00 bl 0+938 <[^>]+> \.\.\. 0+938 <[^>]+> f7ff fbfc bl 0+134 <[^>]+> -0+93c <[^>]+> 4801 ldr r0, \[pc, #4\] \(0+944 <[^>]+>\) -0+93e <[^>]+> 4801 ldr r0, \[pc, #4\] \(0+944 <[^>]+>\) -0+940 <[^>]+> 4801 ldr r0, \[pc, #4\] \(0+948 <[^>]+>\) -0+942 <[^>]+> 4801 ldr r0, \[pc, #4\] \(0+948 <[^>]+>\) -0+944 <[^>]+> 46c0 nop \(mov r8, r8\) -0+946 <[^>]+> 46c0 nop \(mov r8, r8\) +0+93c <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+944 <[^>]+>\) +0+93e <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+944 <[^>]+>\) +0+940 <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+948 <[^>]+>\) +0+942 <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+948 <[^>]+>\) +0+944 <[^>]+> 46c0 nop ; \(mov r8, r8\) +0+946 <[^>]+> 46c0 nop ; \(mov r8, r8\) diff --git a/gas/testsuite/gas/arm/thumb.d b/gas/testsuite/gas/arm/thumb.d index 2e8da00874a..7ee5582d600 100644 --- a/gas/testsuite/gas/arm/thumb.d +++ b/gas/testsuite/gas/arm/thumb.d @@ -48,18 +48,18 @@ Disassembly of section \.text: 0+04a <[^>]+> 45f4 cmp ip, lr 0+04c <[^>]+> 4648 mov r0, r9 0+04e <[^>]+> 46a1 mov r9, r4 -0+050 <[^>]+> 46c0 nop \(mov r8, r8\) +0+050 <[^>]+> 46c0 nop ; \(mov r8, r8\) 0+052 <[^>]+> 4738 bx r7 0+054 <[^>]+> 4740 bx r8 -0+056 <[^>]+> 46c0 nop \(mov r8, r8\) +0+056 <[^>]+> 46c0 nop ; \(mov r8, r8\) 0+058 <[^>]+> 4778 bx pc -0+05a <[^>]+> 4b20 ldr r3, \[pc, #128\] \(0+0dc <[^>]+>\) -0+05c <[^>]+> 4c02 ldr r4, \[pc, #8\] \(0+068 <[^>]+>\) +0+05a <[^>]+> 4b20 ldr r3, \[pc, #128\] ; \(0+0dc <[^>]+>\) +0+05c <[^>]+> 4c02 ldr r4, \[pc, #8\] ; \(0+068 <[^>]+>\) 0+05e <[^>]+> 5088 str r0, \[r1, r2\] 0+060 <[^>]+> 5511 strb r1, \[r2, r4\] 0+062 <[^>]+> 59f5 ldr r5, \[r6, r7\] 0+064 <[^>]+> 5d62 ldrb r2, \[r4, r5\] -0+066 <[^>]+> 46c0 nop \(mov r8, r8\) +0+066 <[^>]+> 46c0 nop ; \(mov r8, r8\) 0+068 <[^>]+> 52d1 strh r1, \[r2, r3\] 0+06a <[^>]+> 5a23 ldrh r3, \[r4, r0\] 0+06c <[^>]+> 57f1 ldrsb r1, \[r6, r7\] @@ -76,7 +76,7 @@ Disassembly of section \.text: 0+082 <[^>]+> 93ff str r3, \[sp, #1020\].* 0+084 <[^>]+> 990b ldr r1, \[sp, #44\].* 0+086 <[^>]+> 9a00 ldr r2, \[sp, #0\] -0+088 <[^>]+> a7ff add r7, pc, #1020 \(adr r7, 0+488 <[^>]+>\) +0+088 <[^>]+> a7ff add r7, pc, #1020 ; \(adr r7, 0+488 <[^>]+>\) 0+08a <[^>]+> ac80 add r4, sp, #512.* 0+08c <[^>]+> b043 add sp, #268.* 0+08e <[^>]+> b09a sub sp, #104.* @@ -112,30 +112,30 @@ Disassembly of section \.text: 0+0ca <[^>]+> b07f add sp, #508.* 0+0cc <[^>]+> b0ff sub sp, #508.* 0+0ce <[^>]+> a8ff add r0, sp, #1020.* -0+0d0 <[^>]+> a0ff add r0, pc, #1020 \(adr r0, 0+4d0 <[^>]+>\) +0+0d0 <[^>]+> a0ff add r0, pc, #1020 ; \(adr r0, 0+4d0 <[^>]+>\) 0+0d2 <[^>]+> b01a add sp, #104.* 0+0d4 <[^>]+> b09a sub sp, #104.* 0+0d6 <[^>]+> a81a add r0, sp, #104.* -0+0d8 <[^>]+> a01a add r0, pc, #104 \(adr r0, 0+144 <[^>]+>\) +0+0d8 <[^>]+> a01a add r0, pc, #104 ; \(adr r0, 0+144 <[^>]+>\) 0+0da <[^>]+> 3168 adds r1, #104.* 0+0dc <[^>]+> 2668 movs r6, #104.* 0+0de <[^>]+> 2f68 cmp r7, #104.* -0+0e0 <[^>]+> 46c0 nop \(mov r8, r8\) -0+0e2 <[^>]+> 46c0 nop \(mov r8, r8\) +0+0e0 <[^>]+> 46c0 nop ; \(mov r8, r8\) +0+0e2 <[^>]+> 46c0 nop ; \(mov r8, r8\) 0+0e4 <[^>]+> eafffffe b 0+0e4 <[^>]+> 0+0e8 <[^>]+> ea000011 b 0+134 <[^>]+> 0+0ec <[^>]+> ebfffffc bl 0+0e4 <[^>]+> 0+0f0 <[^>]+> eb00000f bl 0+134 <[^>]+> 0+0f4 <[^>]+> e12fff10 bx r0 0+0f8 <[^>]+> ef123456 (swi|svc) 0x00123456 -0+0fc <[^>]+> a004 add r0, pc, #16 \(adr r0, 0+110 <[^>]+>\) +0+0fc <[^>]+> a004 add r0, pc, #16 ; \(adr r0, 0+110 <[^>]+>\) 0+0fe <[^>]+> e77f b.n 0+000 <[^>]+> 0+100 <[^>]+> e018 b.n 0+134 <[^>]+> 0+102 <[^>]+> f7ff ff7d bl 0+000 <[^>]+> 0+106 <[^>]+> f000 f815 bl 0+134 <[^>]+> 0+10a <[^>]+> 4700 bx r0 0+10c <[^>]+> dfff (swi|svc) 255.* -0+10e <[^>]+> 46c0 nop \(mov r8, r8\) +0+10e <[^>]+> 46c0 nop ; \(mov r8, r8\) 0+110 <[^>]+> d010 beq.n 0+134 <[^>]+> 0+112 <[^>]+> d10f bne.n 0+134 <[^>]+> 0+114 <[^>]+> d20e bcs.n 0+134 <[^>]+> @@ -157,9 +157,9 @@ Disassembly of section \.text: 0+134 <[^>]+> f000 fc00 bl 0+938 <[^>]+> \.\.\. 0+938 <[^>]+> f7ff fbfc bl 0+134 <[^>]+> -0+93c <[^>]+> 4801 ldr r0, \[pc, #4\] \(0+944 <[^>]+>\) -0+93e <[^>]+> 4801 ldr r0, \[pc, #4\] \(0+944 <[^>]+>\) -0+940 <[^>]+> 4801 ldr r0, \[pc, #4\] \(0+948 <[^>]+>\) -0+942 <[^>]+> 4801 ldr r0, \[pc, #4\] \(0+948 <[^>]+>\) -0+944 <[^>]+> 46c0 nop \(mov r8, r8\) -0+946 <[^>]+> 46c0 nop \(mov r8, r8\) +0+93c <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+944 <[^>]+>\) +0+93e <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+944 <[^>]+>\) +0+940 <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+948 <[^>]+>\) +0+942 <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+948 <[^>]+>\) +0+944 <[^>]+> 46c0 nop ; \(mov r8, r8\) +0+946 <[^>]+> 46c0 nop ; \(mov r8, r8\) diff --git a/gas/testsuite/gas/arm/thumb1_unified.d b/gas/testsuite/gas/arm/thumb1_unified.d index 977d742eca2..e34f3978b17 100644 --- a/gas/testsuite/gas/arm/thumb1_unified.d +++ b/gas/testsuite/gas/arm/thumb1_unified.d @@ -10,8 +10,8 @@ Disassembly of section .text: 0[0-9a-f]+ <[^>]+> 3364 adds r3, #100.* 0[0-9a-f]+ <[^>]+> 3c83 subs r4, #131.* 0[0-9a-f]+ <[^>]+> 2d27 cmp r5, #39.* -0[0-9a-f]+ <[^>]+> a103 add r1, pc, #12 \(adr [^)]*\) -0[0-9a-f]+ <[^>]+> 4a03 ldr r2, \[pc, #12\] \([^)]*\) +0[0-9a-f]+ <[^>]+> a103 add r1, pc, #12 ; \(adr [^)]*\) +0[0-9a-f]+ <[^>]+> 4a03 ldr r2, \[pc, #12\] ; \([^)]*\) 0[0-9a-f]+ <[^>]+> 6863 ldr r3, \[r4, #4\] 0[0-9a-f]+ <[^>]+> 9d01 ldr r5, \[sp, #4\] 0[0-9a-f]+ <[^>]+> b001 add sp, #4 diff --git a/gas/testsuite/gas/arm/thumb2_add.d b/gas/testsuite/gas/arm/thumb2_add.d index d654c8e3f17..1c438968811 100644 --- a/gas/testsuite/gas/arm/thumb2_add.d +++ b/gas/testsuite/gas/arm/thumb2_add.d @@ -5,26 +5,26 @@ Disassembly of section .text: 0+000 <[^>]+> f60f 0000 addw r0, pc, #2048 ; 0x800 -0+004 <[^>]+> f20f 0900 addw r9, pc, #0 ; 0x0 +0+004 <[^>]+> f20f 0900 addw r9, pc, #0 0+008 <[^>]+> f20f 4900 addw r9, pc, #1024 ; 0x400 0+00c <[^>]+> f509 6880 add.w r8, r9, #1024 ; 0x400 0+010 <[^>]+> f209 1801 addw r8, r9, #257 ; 0x101 0+014 <[^>]+> f201 1301 addw r3, r1, #257 ; 0x101 0+018 <[^>]+> f6af 0000 subw r0, pc, #2048 ; 0x800 -0+01c <[^>]+> f2af 0900 subw r9, pc, #0 ; 0x0 +0+01c <[^>]+> f2af 0900 subw r9, pc, #0 0+020 <[^>]+> f2af 4900 subw r9, pc, #1024 ; 0x400 0+024 <[^>]+> f5a9 6880 sub.w r8, r9, #1024 ; 0x400 0+028 <[^>]+> f2a9 1801 subw r8, r9, #257 ; 0x101 0+02c <[^>]+> f2a1 1301 subw r3, r1, #257 ; 0x101 -0+030 <[^>]+> f103 0301 add.w r3, r3, #1 ; 0x1 -0+034 <[^>]+> f1a3 0301 sub.w r3, r3, #1 ; 0x1 -0+038 <[^>]+> b0c0 sub sp, #256.* +0+030 <[^>]+> f103 0301 add.w r3, r3, #1 +0+034 <[^>]+> f1a3 0301 sub.w r3, r3, #1 +0+038 <[^>]+> b0c0 sub sp, #256 ; 0x100 0+03a <[^>]+> f5ad 7d00 sub.w sp, sp, #512 ; 0x200 0+03e <[^>]+> f2ad 1d01 subw sp, sp, #257 ; 0x101 -0+042 <[^>]+> b040 add sp, #256.* +0+042 <[^>]+> b040 add sp, #256 ; 0x100 0+044 <[^>]+> f50d 7d00 add.w sp, sp, #512 ; 0x200 0+048 <[^>]+> f20d 1d01 addw sp, sp, #257 ; 0x101 -0+04c <[^>]+> a840 add r0, sp, #256.* +0+04c <[^>]+> a840 add r0, sp, #256 ; 0x100 0+04e <[^>]+> f50d 6580 add.w r5, sp, #1024 ; 0x400 0+052 <[^>]+> f20d 1901 addw r9, sp, #257 ; 0x101 0+056 <[^>]+> 4271 negs r1, r6 diff --git a/gas/testsuite/gas/arm/thumb2_it.d b/gas/testsuite/gas/arm/thumb2_it.d index 6e6bdb803c5..ab31cdb5839 100644 --- a/gas/testsuite/gas/arm/thumb2_it.d +++ b/gas/testsuite/gas/arm/thumb2_it.d @@ -56,7 +56,7 @@ Disassembly of section .text: 0+080 <[^>]+> 43c8 mvns r0, r1 0+082 <[^>]+> bf02 ittt eq 0+084 <[^>]+> 4248 negeq r0, r1 -0+086 <[^>]+> f1c8 0000 rsbeq r0, r8, #0 ; 0x0 -0+08a <[^>]+> f1d1 0000 rsbseq r0, r1, #0 ; 0x0 -0+08e <[^>]+> f1c1 0000 rsb r0, r1, #0 ; 0x0 +0+086 <[^>]+> f1c8 0000 rsbeq r0, r8, #0 +0+08a <[^>]+> f1d1 0000 rsbseq r0, r1, #0 +0+08e <[^>]+> f1c1 0000 rsb r0, r1, #0 0+092 <[^>]+> 4248 negs r0, r1 diff --git a/gas/testsuite/gas/arm/thumb2_it_auto.d b/gas/testsuite/gas/arm/thumb2_it_auto.d index c3fdbc2c22b..3cd465d26af 100644 --- a/gas/testsuite/gas/arm/thumb2_it_auto.d +++ b/gas/testsuite/gas/arm/thumb2_it_auto.d @@ -56,7 +56,7 @@ Disassembly of section .text: 0+080 <[^>]+> 43c8 mvns r0, r1 0+082 <[^>]+> bf02 ittt eq 0+084 <[^>]+> 4248 negeq r0, r1 -0+086 <[^>]+> f1c8 0000 rsbeq r0, r8, #0 ; 0x0 -0+08a <[^>]+> f1d1 0000 rsbseq r0, r1, #0 ; 0x0 -0+08e <[^>]+> f1c1 0000 rsb r0, r1, #0 ; 0x0 +0+086 <[^>]+> f1c8 0000 rsbeq r0, r8, #0 +0+08a <[^>]+> f1d1 0000 rsbseq r0, r1, #0 +0+08e <[^>]+> f1c1 0000 rsb r0, r1, #0 0+092 <[^>]+> 4248 negs r0, r1 diff --git a/gas/testsuite/gas/arm/thumb2_pool.d b/gas/testsuite/gas/arm/thumb2_pool.d index 752da7fb6aa..4d6ce4458e3 100644 --- a/gas/testsuite/gas/arm/thumb2_pool.d +++ b/gas/testsuite/gas/arm/thumb2_pool.d @@ -6,11 +6,11 @@ .*: +file format .*arm.* Disassembly of section .text: -0+000 <[^>]+> 4e04 ldr r6, \[pc, #16\] \(00+14 <[^>]+>\) -0+002 <[^>]+> 4904 ldr r1, \[pc, #16\] \(00+14 <[^>]+>\) +0+000 <[^>]+> 4e04 ldr r6, \[pc, #16\] ; \(00+14 <[^>]+>\) +0+002 <[^>]+> 4904 ldr r1, \[pc, #16\] ; \(00+14 <[^>]+>\) 0+004 <[^>]+> f8df 600c ldr\.w r6, \[pc, #12\] ; 00+14 <[^>]+> 0+008 <[^>]+> f8df 9008 ldr\.w r9, \[pc, #8\] ; 00+14 <[^>]+> 0+00c <[^>]+> bf00 nop 0+00e <[^>]+> f8df 5004 ldr\.w r5, \[pc, #4\] ; 00+14 <[^>]+> -0+012 <[^>]+> 4900 ldr r1, \[pc, #0\] \(00+14 <[^>]+>\) +0+012 <[^>]+> 4900 ldr r1, \[pc, #0\] ; \(00+14 <[^>]+>\) 0+014 <[^>]+> 12345678 ? .word 0x12345678 diff --git a/gas/testsuite/gas/arm/thumb2_relax.d b/gas/testsuite/gas/arm/thumb2_relax.d index ccaac70619d..e99d55c839f 100644 --- a/gas/testsuite/gas/arm/thumb2_relax.d +++ b/gas/testsuite/gas/arm/thumb2_relax.d @@ -84,7 +84,7 @@ Disassembly of section .text: 0+116 <[^>]+> f855 1d7c ldr.w r1, \[r5, #-124\]!.* 0+11a <[^>]+> 5929 ldr r1, \[r5, r4\] 0+11c <[^>]+> f859 100c ldr.w r1, \[r9, ip\] -0+120 <[^>]+> 4904 ldr r1, \[pc, #16\] \(0+134 <[^>]+>\) +0+120 <[^>]+> 4904 ldr r1, \[pc, #16\] ; \(0+134 <[^>]+>\) 0+122 <[^>]+> f8df 1010 ldr.w r1, \[pc, #16\] ; 0+134 <[^>]+> 0+126 <[^>]+> f8df 800c ldr.w r8, \[pc, #12\] ; 0+134 <[^>]+> 0+12a <[^>]+> f8df 100a ldr.w r1, \[pc, #10\] ; 0+136 <[^>]+> @@ -142,14 +142,14 @@ Disassembly of section .text: 0+1e0 <[^>]+> f8cf 1006 str.w r1, \[pc, #6\] ; 0+1ea <[^>]+> 0+1e4 <[^>]+> f84f 103a str.w r1, \[pc, #-58\] ; 0+1ae <[^>]+> 0+1e8 <[^>]+> bf00 nop -0+1ea <[^>]+> a104 add r1, pc, #16 \(adr r1, 0+1fc <[^>]+>\) -0+1ec <[^>]+> f20f 010c addw r1, pc, #12 ; 0xc -0+1f0 <[^>]+> f20f 0808 addw r8, pc, #8 ; 0x8 -0+1f4 <[^>]+> f20f 0106 addw r1, pc, #6 ; 0x6 -0+1f8 <[^>]+> f2af 0112 subw r1, pc, #18 ; 0x12 +0+1ea <[^>]+> a104 add r1, pc, #16 ; \(adr r1, 0+1fc <[^>]+>\) +0+1ec <[^>]+> f20f 010c addw r1, pc, #12 +0+1f0 <[^>]+> f20f 0808 addw r8, pc, #8 +0+1f4 <[^>]+> f20f 0106 addw r1, pc, #6 +0+1f8 <[^>]+> f2af 0112 subw r1, pc, #18 0+1fc <[^>]+> bf00 nop 0+1fe <[^>]+> bf00 nop -0+200 <[^>]+> f20f 0104 addw r1, pc, #4 ; 0x4 -0+204 <[^>]+> f20f 0102 addw r1, pc, #2 ; 0x2 +0+200 <[^>]+> f20f 0104 addw r1, pc, #4 +0+204 <[^>]+> f20f 0102 addw r1, pc, #2 0+208 <[^>]+> bf00 nop 0+20a <[^>]+> bf00 nop diff --git a/gas/testsuite/gas/arm/thumb32.d b/gas/testsuite/gas/arm/thumb32.d index b1a73b3f7cf..e53a23dd32f 100644 --- a/gas/testsuite/gas/arm/thumb32.d +++ b/gas/testsuite/gas/arm/thumb32.d @@ -8,7 +8,7 @@ .*: +file format .*arm.* Disassembly of section .text: -0[0-9a-f]+ <[^>]+> f041 0000 orr\.w r0, r1, #0 ; 0x0 +0[0-9a-f]+ <[^>]+> f041 0000 orr\.w r0, r1, #0 0[0-9a-f]+ <[^>]+> f041 00a5 orr\.w r0, r1, #165 ; 0xa5 0[0-9a-f]+ <[^>]+> f041 10a5 orr\.w r0, r1, #10813605 ; 0xa500a5 0[0-9a-f]+ <[^>]+> f041 20a5 orr\.w r0, r1, #2768282880 ; 0xa500a500 @@ -63,24 +63,24 @@ Disassembly of section .text: 0[0-9a-f]+ <[^>]+> eb00 0800 add\.w r8, r0, r0 0[0-9a-f]+ <[^>]+> 4401 add r1, r0 0[0-9a-f]+ <[^>]+> 4408 add r0, r1 -0[0-9a-f]+ <[^>]+> a000 add r0, pc, #0 \(adr r0, [0-9a-f]+ <[^>]+>\) -0[0-9a-f]+ <[^>]+> a500 add r5, pc, #0 \(adr r5, [0-9a-f]+ <[^>]+>\) -0[0-9a-f]+ <[^>]+> a081 add r0, pc, #516 \(adr r0, [0-9a-f]+ <[^>]+>\) +0[0-9a-f]+ <[^>]+> a000 add r0, pc, #0 ; \(adr r0, [0-9a-f]+ <[^>]+>\) +0[0-9a-f]+ <[^>]+> a500 add r5, pc, #0 ; \(adr r5, [0-9a-f]+ <[^>]+>\) +0[0-9a-f]+ <[^>]+> a081 add r0, pc, #516 ; \(adr r0, [0-9a-f]+ <[^>]+>\) 0[0-9a-f]+ <[^>]+> a800 add r0, sp, #0 0[0-9a-f]+ <[^>]+> ad00 add r5, sp, #0 0[0-9a-f]+ <[^>]+> a881 add r0, sp, #516.* 0[0-9a-f]+ <[^>]+> b000 add sp, #0 0[0-9a-f]+ <[^>]+> b000 add sp, #0 0[0-9a-f]+ <[^>]+> b041 add sp, #260.* -0[0-9a-f]+ <[^>]+> f100 0000 add\.w r0, r0, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f110 0000 adds\.w r0, r0, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f100 0900 add\.w r9, r0, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f109 0000 add\.w r0, r9, #0 ; 0x0 +0[0-9a-f]+ <[^>]+> f100 0000 add\.w r0, r0, #0 +0[0-9a-f]+ <[^>]+> f110 0000 adds\.w r0, r0, #0 +0[0-9a-f]+ <[^>]+> f100 0900 add\.w r9, r0, #0 +0[0-9a-f]+ <[^>]+> f109 0000 add\.w r0, r9, #0 0[0-9a-f]+ <[^>]+> f100 0081 add\.w r0, r0, #129 ; 0x81 0[0-9a-f]+ <[^>]+> f513 3580 adds\.w r5, r3, #65536 ; 0x10000 -0[0-9a-f]+ <[^>]+> f10d 0001 add\.w r0, sp, #1 ; 0x1 -0[0-9a-f]+ <[^>]+> f10d 0900 add\.w r9, sp, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f10d 0d04 add\.w sp, sp, #4 ; 0x4 +0[0-9a-f]+ <[^>]+> f10d 0001 add\.w r0, sp, #1 +0[0-9a-f]+ <[^>]+> f10d 0900 add\.w r9, sp, #0 +0[0-9a-f]+ <[^>]+> f10d 0d04 add\.w sp, sp, #4 0[0-9a-f]+ <[^>]+> eb00 0000 add\.w r0, r0, r0 0[0-9a-f]+ <[^>]+> eb10 0000 adds\.w r0, r0, r0 0[0-9a-f]+ <[^>]+> eb00 0900 add\.w r9, r0, r0 @@ -109,11 +109,11 @@ Disassembly of section .text: 0[0-9a-f]+ <[^>]+> ebb8 0800 subs\.w r8, r8, r0 0[0-9a-f]+ <[^>]+> ebb0 0008 subs\.w r0, r0, r8 0[0-9a-f]+ <[^>]+> f5b0 7082 subs\.w r0, r0, #260 ; 0x104 -0[0-9a-f]+ <[^>]+> f1b2 0104 subs\.w r1, r2, #4 ; 0x4 +0[0-9a-f]+ <[^>]+> f1b2 0104 subs\.w r1, r2, #4 0[0-9a-f]+ <[^>]+> f5b3 3580 subs\.w r5, r3, #65536 ; 0x10000 -0[0-9a-f]+ <[^>]+> f1ad 0104 sub\.w r1, sp, #4 ; 0x4 -0[0-9a-f]+ <[^>]+> f1ad 0900 sub\.w r9, sp, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f1ad 0d04 sub\.w sp, sp, #4 ; 0x4 +0[0-9a-f]+ <[^>]+> f1ad 0104 sub\.w r1, sp, #4 +0[0-9a-f]+ <[^>]+> f1ad 0900 sub\.w r9, sp, #0 +0[0-9a-f]+ <[^>]+> f1ad 0d04 sub\.w sp, sp, #4 0[0-9a-f]+ <[^>]+> 4140 adcs r0, r0 0[0-9a-f]+ <[^>]+> 4145 adcs r5, r0 0[0-9a-f]+ <[^>]+> 4168 adcs r0, r5 @@ -637,9 +637,9 @@ Disassembly of section .text: 0[0-9a-f]+ <[^>]+> ea7f 0009 mvns\.w r0, r9 0[0-9a-f]+ <[^>]+> f06f 0081 mvn\.w r0, #129 ; 0x81 0[0-9a-f]+ <[^>]+> f06f 0581 mvn\.w r5, #129 ; 0x81 -0[0-9a-f]+ <[^>]+> f240 0000 movw r0, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f2c0 0000 movt r0, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f240 0900 movw r9, #0 ; 0x0 +0[0-9a-f]+ <[^>]+> f240 0000 movw r0, #0 +0[0-9a-f]+ <[^>]+> f2c0 0000 movt r0, #0 +0[0-9a-f]+ <[^>]+> f240 0900 movw r9, #0 0[0-9a-f]+ <[^>]+> f249 0000 movw r0, #36864 ; 0x9000 0[0-9a-f]+ <[^>]+> f640 0000 movw r0, #2048 ; 0x800 0[0-9a-f]+ <[^>]+> f240 5000 movw r0, #1280 ; 0x500 @@ -674,13 +674,13 @@ Disassembly of section .text: 0[0-9a-f]+ <[^>]+> 4240 negs r0, r0 0[0-9a-f]+ <[^>]+> 4268 negs r0, r5 0[0-9a-f]+ <[^>]+> 4245 negs r5, r0 -0[0-9a-f]+ <[^>]+> f1d0 0000 rsbs r0, r0, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f1d0 0500 rsbs r5, r0, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f1d5 0000 rsbs r0, r5, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f1c9 0000 rsb r0, r9, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f1c0 0900 rsb r9, r0, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f1d9 0000 rsbs r0, r9, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f1d0 0900 rsbs r9, r0, #0 ; 0x0 +0[0-9a-f]+ <[^>]+> f1d0 0000 rsbs r0, r0, #0 +0[0-9a-f]+ <[^>]+> f1d0 0500 rsbs r5, r0, #0 +0[0-9a-f]+ <[^>]+> f1d5 0000 rsbs r0, r5, #0 +0[0-9a-f]+ <[^>]+> f1c9 0000 rsb r0, r9, #0 +0[0-9a-f]+ <[^>]+> f1c0 0900 rsb r9, r0, #0 +0[0-9a-f]+ <[^>]+> f1d9 0000 rsbs r0, r9, #0 +0[0-9a-f]+ <[^>]+> f1d0 0900 rsbs r9, r0, #0 0[0-9a-f]+ <[^>]+> eac0 0000 pkhbt r0, r0, r0 0[0-9a-f]+ <[^>]+> eac0 0900 pkhbt r9, r0, r0 0[0-9a-f]+ <[^>]+> eac9 0000 pkhbt r0, r9, r0 @@ -842,7 +842,7 @@ Disassembly of section .text: 0[0-9a-f]+ <[^>]+> fa71 f002 rors\.w r0, r1, r2 0[0-9a-f]+ <[^>]+> ea4f 0132 mov.w r1, r2, rrx 0[0-9a-f]+ <[^>]+> ea5f 0334 movs.w r3, r4, rrx -0[0-9a-f]+ <[^>]+> f7f0 8000 smc #0 ; 0x0 +0[0-9a-f]+ <[^>]+> f7f0 8000 smc #0 0[0-9a-f]+ <[^>]+> f7fd 8bca smc #43981 ; 0xabcd 0[0-9a-f]+ <[^>]+> fb10 0000 smlabb r0, r0, r0, r0 0[0-9a-f]+ <[^>]+> fb10 0900 smlabb r9, r0, r0, r0 @@ -964,7 +964,7 @@ Disassembly of section .text: 0[0-9a-f]+ <[^>]+> f8df 1155 ldr\.w r1, \[pc, #341\] ; 0+d6d <[^>]+> 0[0-9a-f]+ <[^>]+> f85f 12aa ldr\.w r1, \[pc, #-682\] ; 0+972 <[^>]+> 0[0-9a-f]+ <[^>]+> f85f 1155 ldr\.w r1, \[pc, #-341\] ; 0+acb <[^>]+> -0[0-9a-f]+ <[^>]+> f200 0900 addw r9, r0, #0 ; 0x0 +0[0-9a-f]+ <[^>]+> f200 0900 addw r9, r0, #0 0[0-9a-f]+ <[^>]+> f60f 76ff addw r6, pc, #4095 ; 0xfff 0[0-9a-f]+ <[^>]+> f6a9 2685 subw r6, r9, #2693 ; 0xa85 0[0-9a-f]+ <[^>]+> f2a9 567a subw r6, r9, #1402 ; 0x57a diff --git a/gas/testsuite/gas/arm/thumbv6.d b/gas/testsuite/gas/arm/thumbv6.d index 5dc821455dd..5da70351c23 100644 --- a/gas/testsuite/gas/arm/thumbv6.d +++ b/gas/testsuite/gas/arm/thumbv6.d @@ -17,7 +17,7 @@ Disassembly of section .text: 0+012 <[^>]*> b251 * sxtb r1, r2 0+014 <[^>]*> b2a3 * uxth r3, r4 0+016 <[^>]*> b2f5 * uxtb r5, r6 -0+018 <[^>]*> 46c0 * nop[ ]+\(mov r8, r8\) -0+01a <[^>]*> 46c0 * nop[ ]+\(mov r8, r8\) -0+01c <[^>]*> 46c0 * nop[ ]+\(mov r8, r8\) -0+01e <[^>]*> 46c0 * nop[ ]+\(mov r8, r8\) +0+018 <[^>]*> 46c0 * nop[ ]+; \(mov r8, r8\) +0+01a <[^>]*> 46c0 * nop[ ]+; \(mov r8, r8\) +0+01c <[^>]*> 46c0 * nop[ ]+; \(mov r8, r8\) +0+01e <[^>]*> 46c0 * nop[ ]+; \(mov r8, r8\) diff --git a/gas/testsuite/gas/arm/thumbv6k.d b/gas/testsuite/gas/arm/thumbv6k.d index 54a1d31ca63..1dd30eca8c0 100644 --- a/gas/testsuite/gas/arm/thumbv6k.d +++ b/gas/testsuite/gas/arm/thumbv6k.d @@ -9,7 +9,7 @@ Disassembly of section .text: 0+002 <[^>]*> bf20 * wfe 0+004 <[^>]*> bf30 * wfi 0+006 <[^>]*> bf40 * sev -0+008 <[^>]*> 46c0 * nop[ \t]+\(mov r8, r8\) -0+00a <[^>]*> 46c0 * nop[ \t]+\(mov r8, r8\) -0+00c <[^>]*> 46c0 * nop[ \t]+\(mov r8, r8\) -0+00e <[^>]*> 46c0 * nop[ \t]+\(mov r8, r8\) +0+008 <[^>]*> 46c0 * nop[ \t]+; \(mov r8, r8\) +0+00a <[^>]*> 46c0 * nop[ \t]+; \(mov r8, r8\) +0+00c <[^>]*> 46c0 * nop[ \t]+; \(mov r8, r8\) +0+00e <[^>]*> 46c0 * nop[ \t]+; \(mov r8, r8\) diff --git a/gas/testsuite/gas/arm/tls.d b/gas/testsuite/gas/arm/tls.d index 5189dfff01f..6401f29f53e 100644 --- a/gas/testsuite/gas/arm/tls.d +++ b/gas/testsuite/gas/arm/tls.d @@ -12,8 +12,8 @@ Disassembly of section .text: 00+0 <main>: - 0: e1a00000 nop \(mov r0,r0\) - 4: e1a00000 nop \(mov r0,r0\) + 0: e1a00000 nop ; \(mov r0, r0\) + 4: e1a00000 nop ; \(mov r0, r0\) 8: e1a0f00e mov pc, lr c: 00000000 .word 0x00000000 c: R_ARM_TLS_GD32 a diff --git a/gas/testsuite/gas/arm/vfp1.d b/gas/testsuite/gas/arm/vfp1.d index d23fd8429be..a7a127a3da9 100644 --- a/gas/testsuite/gas/arm/vfp1.d +++ b/gas/testsuite/gas/arm/vfp1.d @@ -112,12 +112,12 @@ Disassembly of section .text: 0+198 <[^>]*> ed910b00 vldr d0, \[r1\] 0+19c <[^>]*> ed9e0b00 vldr d0, \[lr\] 0+1a0 <[^>]*> ed900b00 vldr d0, \[r0\] -0+1a4 <[^>]*> ed900bff vldr d0, \[r0, #1020\] -0+1a8 <[^>]*> ed100bff vldr d0, \[r0, #-1020\] +0+1a4 <[^>]*> ed900bff vldr d0, \[r0, #1020\].* +0+1a8 <[^>]*> ed100bff vldr d0, \[r0, #-1020\].* 0+1ac <[^>]*> ed901b00 vldr d1, \[r0\] 0+1b0 <[^>]*> ed902b00 vldr d2, \[r0\] 0+1b4 <[^>]*> ed90fb00 vldr d15, \[r0\] -0+1b8 <[^>]*> ed8ccbc9 vstr d12, \[ip, #804\] +0+1b8 <[^>]*> ed8ccbc9 vstr d12, \[ip, #804\].* 0+1bc <[^>]*> ec901b02 vldmia r0, {d1} 0+1c0 <[^>]*> ec902b02 vldmia r0, {d2} 0+1c4 <[^>]*> ec90fb02 vldmia r0, {d15} @@ -188,6 +188,6 @@ Disassembly of section .text: 0+2c8 <[^>]*> 0e1f7b10 vmoveq\.32 r7, d15\[0\] 0+2cc <[^>]*> 0e21fb10 vmoveq\.32 d1\[1\], pc 0+2d0 <[^>]*> 0e0f1b10 vmoveq\.32 d15\[0\], r1 -0+2d4 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) -0+2d8 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) -0+2dc <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) +0+2d4 <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\) +0+2d8 <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\) +0+2dc <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\) diff --git a/gas/testsuite/gas/arm/vfp1_t2.d b/gas/testsuite/gas/arm/vfp1_t2.d index 8b3fbc323e1..2ff52fdecd7 100644 --- a/gas/testsuite/gas/arm/vfp1_t2.d +++ b/gas/testsuite/gas/arm/vfp1_t2.d @@ -112,12 +112,12 @@ Disassembly of section .text: 0+198 <[^>]*> ed91 0b00 vldr d0, \[r1\] 0+19c <[^>]*> ed9e 0b00 vldr d0, \[lr\] 0+1a0 <[^>]*> ed90 0b00 vldr d0, \[r0\] -0+1a4 <[^>]*> ed90 0bff vldr d0, \[r0, #1020\] -0+1a8 <[^>]*> ed10 0bff vldr d0, \[r0, #-1020\] +0+1a4 <[^>]*> ed90 0bff vldr d0, \[r0, #1020\].* +0+1a8 <[^>]*> ed10 0bff vldr d0, \[r0, #-1020\].* 0+1ac <[^>]*> ed90 1b00 vldr d1, \[r0\] 0+1b0 <[^>]*> ed90 2b00 vldr d2, \[r0\] 0+1b4 <[^>]*> ed90 fb00 vldr d15, \[r0\] -0+1b8 <[^>]*> ed8c cbc9 vstr d12, \[ip, #804\] +0+1b8 <[^>]*> ed8c cbc9 vstr d12, \[ip, #804\].* 0+1bc <[^>]*> ec90 1b02 vldmia r0, {d1} 0+1c0 <[^>]*> ec90 2b02 vldmia r0, {d2} 0+1c4 <[^>]*> ec90 fb02 vldmia r0, {d15} diff --git a/gas/testsuite/gas/arm/vfp1xD.d b/gas/testsuite/gas/arm/vfp1xD.d index 1ec68b9944b..8de7dd4a0e3 100644 --- a/gas/testsuite/gas/arm/vfp1xD.d +++ b/gas/testsuite/gas/arm/vfp1xD.d @@ -249,5 +249,5 @@ Disassembly of section .text: 0+3bc <[^>]*> eee70a10 (vmsr|fmxr) mvfr0, r0 0+3c0 <[^>]*> eee60a10 (vmsr|fmxr) mvfr1, r0 0+3c4 <[^>]*> eeec0a10 (vmsr|fmxr) <impl def 0xc>, r0 -0+3c8 <[^>]*> e1a00000 nop \(mov r0,r0\) -0+3cc <[^>]*> e1a00000 nop \(mov r0,r0\) +0+3c8 <[^>]*> e1a00000 nop ; \(mov r0, r0\) +0+3cc <[^>]*> e1a00000 nop ; \(mov r0, r0\) diff --git a/gas/testsuite/gas/arm/wince.d b/gas/testsuite/gas/arm/wince.d index 1770cacd4f1..1608db98db3 100644 --- a/gas/testsuite/gas/arm/wince.d +++ b/gas/testsuite/gas/arm/wince.d @@ -11,9 +11,9 @@ Disassembly of section .text: 0+000 <global_data> 00000007 andeq r0, r0, r7 0: ARM_32 global_data -0+004 <global_sym> e1a00000 nop \(mov r0,r0\) -0+008 <global_sym\+0x4> e1a00000 nop \(mov r0,r0\) -0+000c <global_sym\+0x8> e1a00000 nop \(mov r0,r0\) +0+004 <global_sym> e1a00000 nop ; \(mov r0, r0\) +0+008 <global_sym\+0x4> e1a00000 nop ; \(mov r0, r0\) +0+000c <global_sym\+0x8> e1a00000 nop ; \(mov r0, r0\) 0+010 <global_sym\+0xc> eafffffb b f+ff8 <global_sym\+0xf+ff4> 10: ARM_26D global_sym\+0xf+ffc 0+018 <global_sym\+0x14> ebfffffa bl f+ff4 <global_sym\+0xf+ff0> diff --git a/gas/testsuite/gas/arm/wince_inst.d b/gas/testsuite/gas/arm/wince_inst.d index 7b05a42b486..5c145828d6a 100644 --- a/gas/testsuite/gas/arm/wince_inst.d +++ b/gas/testsuite/gas/arm/wince_inst.d @@ -11,7 +11,7 @@ .*: +file format .*arm.* Disassembly of section .text: -0+000 <[^>]*> e3a00000 ? mov r0, #0 ; 0x0 +0+000 <[^>]*> e3a00000 ? mov r0, #0 0+004 <[^>]*> e1a01002 ? mov r1, r2 0+008 <[^>]*> e1a03184 ? lsl r3, r4, #3 0+00c <[^>]*> e1a05736 ? lsr r5, r6, r7 @@ -37,79 +37,79 @@ Disassembly of section .text: 0+05c <[^>]*> 31a01003 ? movcc r1, r3 0+060 <[^>]*> e1b00008 ? movs r0, r8 0+064 <[^>]*> 31b00007 ? movscc r0, r7 -0+068 <[^>]*> e281000a ? add r0, r1, #10 ; 0xa +0+068 <[^>]*> e281000a ? add r0, r1, #10 0+06c <[^>]*> e0832004 ? add r2, r3, r4 0+070 <[^>]*> e0865287 ? add r5, r6, r7, lsl #5 0+074 <[^>]*> e0821113 ? add r1, r2, r3, lsl r1 -0+078 <[^>]*> e201000a ? and r0, r1, #10 ; 0xa +0+078 <[^>]*> e201000a ? and r0, r1, #10 0+07c <[^>]*> e0032004 ? and r2, r3, r4 0+080 <[^>]*> e0065287 ? and r5, r6, r7, lsl #5 0+084 <[^>]*> e0021113 ? and r1, r2, r3, lsl r1 -0+088 <[^>]*> e221000a ? eor r0, r1, #10 ; 0xa +0+088 <[^>]*> e221000a ? eor r0, r1, #10 0+08c <[^>]*> e0232004 ? eor r2, r3, r4 0+090 <[^>]*> e0265287 ? eor r5, r6, r7, lsl #5 0+094 <[^>]*> e0221113 ? eor r1, r2, r3, lsl r1 -0+098 <[^>]*> e241000a ? sub r0, r1, #10 ; 0xa +0+098 <[^>]*> e241000a ? sub r0, r1, #10 0+09c <[^>]*> e0432004 ? sub r2, r3, r4 0+0a0 <[^>]*> e0465287 ? sub r5, r6, r7, lsl #5 0+0a4 <[^>]*> e0421113 ? sub r1, r2, r3, lsl r1 -0+0a8 <[^>]*> e2a1000a ? adc r0, r1, #10 ; 0xa +0+0a8 <[^>]*> e2a1000a ? adc r0, r1, #10 0+0ac <[^>]*> e0a32004 ? adc r2, r3, r4 0+0b0 <[^>]*> e0a65287 ? adc r5, r6, r7, lsl #5 0+0b4 <[^>]*> e0a21113 ? adc r1, r2, r3, lsl r1 -0+0b8 <[^>]*> e2c1000a ? sbc r0, r1, #10 ; 0xa +0+0b8 <[^>]*> e2c1000a ? sbc r0, r1, #10 0+0bc <[^>]*> e0c32004 ? sbc r2, r3, r4 0+0c0 <[^>]*> e0c65287 ? sbc r5, r6, r7, lsl #5 0+0c4 <[^>]*> e0c21113 ? sbc r1, r2, r3, lsl r1 -0+0c8 <[^>]*> e261000a ? rsb r0, r1, #10 ; 0xa +0+0c8 <[^>]*> e261000a ? rsb r0, r1, #10 0+0cc <[^>]*> e0632004 ? rsb r2, r3, r4 0+0d0 <[^>]*> e0665287 ? rsb r5, r6, r7, lsl #5 0+0d4 <[^>]*> e0621113 ? rsb r1, r2, r3, lsl r1 -0+0d8 <[^>]*> e2e1000a ? rsc r0, r1, #10 ; 0xa +0+0d8 <[^>]*> e2e1000a ? rsc r0, r1, #10 0+0dc <[^>]*> e0e32004 ? rsc r2, r3, r4 0+0e0 <[^>]*> e0e65287 ? rsc r5, r6, r7, lsl #5 0+0e4 <[^>]*> e0e21113 ? rsc r1, r2, r3, lsl r1 -0+0e8 <[^>]*> e381000a ? orr r0, r1, #10 ; 0xa +0+0e8 <[^>]*> e381000a ? orr r0, r1, #10 0+0ec <[^>]*> e1832004 ? orr r2, r3, r4 0+0f0 <[^>]*> e1865287 ? orr r5, r6, r7, lsl #5 0+0f4 <[^>]*> e1821113 ? orr r1, r2, r3, lsl r1 -0+0f8 <[^>]*> e3c1000a ? bic r0, r1, #10 ; 0xa +0+0f8 <[^>]*> e3c1000a ? bic r0, r1, #10 0+0fc <[^>]*> e1c32004 ? bic r2, r3, r4 0+100 <[^>]*> e1c65287 ? bic r5, r6, r7, lsl #5 0+104 <[^>]*> e1c21113 ? bic r1, r2, r3, lsl r1 -0+108 <[^>]*> e3e0000a ? mvn r0, #10 ; 0xa +0+108 <[^>]*> e3e0000a ? mvn r0, #10 0+10c <[^>]*> e1e02004 ? mvn r2, r4 0+110 <[^>]*> e1e05287 ? mvn r5, r7, lsl #5 0+114 <[^>]*> e1e01113 ? mvn r1, r3, lsl r1 -0+118 <[^>]*> e310000a ? tst r0, #10 ; 0xa +0+118 <[^>]*> e310000a ? tst r0, #10 0+11c <[^>]*> e1120004 ? tst r2, r4 0+120 <[^>]*> e1150287 ? tst r5, r7, lsl #5 0+124 <[^>]*> e1110113 ? tst r1, r3, lsl r1 -0+128 <[^>]*> e330000a ? teq r0, #10 ; 0xa +0+128 <[^>]*> e330000a ? teq r0, #10 0+12c <[^>]*> e1320004 ? teq r2, r4 0+130 <[^>]*> e1350287 ? teq r5, r7, lsl #5 0+134 <[^>]*> e1310113 ? teq r1, r3, lsl r1 -0+138 <[^>]*> e350000a ? cmp r0, #10 ; 0xa +0+138 <[^>]*> e350000a ? cmp r0, #10 0+13c <[^>]*> e1520004 ? cmp r2, r4 0+140 <[^>]*> e1550287 ? cmp r5, r7, lsl #5 0+144 <[^>]*> e1510113 ? cmp r1, r3, lsl r1 -0+148 <[^>]*> e370000a ? cmn r0, #10 ; 0xa +0+148 <[^>]*> e370000a ? cmn r0, #10 0+14c <[^>]*> e1720004 ? cmn r2, r4 0+150 <[^>]*> e1750287 ? cmn r5, r7, lsl #5 0+154 <[^>]*> e1710113 ? cmn r1, r3, lsl r1 -0+158 <[^>]*> e330f00a ? teqp r0, #10 ; 0xa +0+158 <[^>]*> e330f00a ? teqp r0, #10 0+15c <[^>]*> e132f004 ? teqp r2, r4 0+160 <[^>]*> e135f287 ? teqp r5, r7, lsl #5 0+164 <[^>]*> e131f113 ? teqp r1, r3, lsl r1 -0+168 <[^>]*> e370f00a ? cmnp r0, #10 ; 0xa +0+168 <[^>]*> e370f00a ? cmnp r0, #10 0+16c <[^>]*> e172f004 ? cmnp r2, r4 0+170 <[^>]*> e175f287 ? cmnp r5, r7, lsl #5 0+174 <[^>]*> e171f113 ? cmnp r1, r3, lsl r1 -0+178 <[^>]*> e350f00a ? cmpp r0, #10 ; 0xa +0+178 <[^>]*> e350f00a ? cmpp r0, #10 0+17c <[^>]*> e152f004 ? cmpp r2, r4 0+180 <[^>]*> e155f287 ? cmpp r5, r7, lsl #5 0+184 <[^>]*> e151f113 ? cmpp r1, r3, lsl r1 -0+188 <[^>]*> e310f00a ? tstp r0, #10 ; 0xa +0+188 <[^>]*> e310f00a ? tstp r0, #10 0+18c <[^>]*> e112f004 ? tstp r2, r4 0+190 <[^>]*> e115f287 ? tstp r5, r7, lsl #5 0+194 <[^>]*> e111f113 ? tstp r1, r3, lsl r1 diff --git a/gas/testsuite/gas/arm/xscale.d b/gas/testsuite/gas/arm/xscale.d index b08dfcad046..da4d1d7bfe9 100644 --- a/gas/testsuite/gas/arm/xscale.d +++ b/gas/testsuite/gas/arm/xscale.d @@ -24,14 +24,14 @@ Disassembly of section .text: 0+38 <[^>]*> f7d2f003 pld \[r2, r3\] 0+3c <[^>]*> f754f285 pld \[r4, -r5, lsl #5\] 0+40 <[^>]*> e1c100d0 ldrd r0, \[r1\] -0+44 <[^>]*> 01c327d8 ldrdeq r2, \[r3, #120\] +0+44 <[^>]*> 01c327d8 ldrdeq r2, \[r3, #120\].* 0+48 <[^>]*> b10540d6 ldrdlt r4, \[r5, -r6\] -0+4c <[^>]*> e16a88f9 strd r8, \[sl, #-137\]! +0+4c <[^>]*> e16a88f9 strd r8, \[sl, #-137\]!.* 0+50 <[^>]*> e1ac00fd strd r0, \[ip, sp\]! 0+54 <[^>]*> 30ce21f0 strdcc r2, \[lr\], #16 0+58 <[^>]*> 708640f8 strdvc r4, \[r6\], r8 0+5c <[^>]*> e5910000 ldr r0, \[r1\] 0+60 <[^>]*> e5832000 str r2, \[r3\] -0+64 <[^>]*> e321f011 msr CPSR_c, #17 ; 0x11 -0+68 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) -0+6c <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) +0+64 <[^>]*> e321f011 msr CPSR_c, #17 +0+68 <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\) +0+6c <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\) diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog index 2e13629d6d2..33337974fbd 100644 --- a/ld/testsuite/ChangeLog +++ b/ld/testsuite/ChangeLog @@ -1,3 +1,35 @@ +2009-06-30 Nick Clifton <nickc@redhat.com> + + PR 10288 + * ld-arm/arm-app.d: Update expcted disassembly. + * ld-arm/arm-be8.d: Likewise. + * ld-arm/arm-call.d: Likewise. + * ld-arm/arm-lib-plt32.d: Likewise. + * ld-arm/arm-lib.d: Likewise. + * ld-arm/arm-movwt.d: Likewise. + * ld-arm/arm-pic-veneer.d: Likewise. + * ld-arm/armthumb-lib.d: Likewise. + * ld-arm/armv4-bx.d: Likewise. + * ld-arm/cortex-a8-fix-b-rel-arm.d: Likewise. + * ld-arm/farcall-mixed-app-v5.d: Likewise. + * ld-arm/farcall-mixed-app.d: Likewise. + * ld-arm/farcall-mixed-lib.d: Likewise. + * ld-arm/farcall-thumb-arm-pic-veneer.d: Likewise. + * ld-arm/farcall-thumb-arm-short.d: Likewise. + * ld-arm/farcall-thumb-arm.d: Likewise. + * ld-arm/farcall-thumb-thumb-m-pic-veneer.d: Likewise. + * ld-arm/farcall-thumb-thumb-m.d: Likewise. + * ld-arm/farcall-thumb-thumb-pic-veneer.d: Likewise. + * ld-arm/farcall-thumb-thumb.d: Likewise. + * ld-arm/group-relocs.d: Likewise. + * ld-arm/mixed-app-v5.d: Likewise. + * ld-arm/mixed-app.d: Likewise. + * ld-arm/mixed-lib.d: Likewise. + * ld-arm/movw-merge.d: Likewise. + * ld-arm/thumb2-b-interwork.d: Likewise. + * ld-arm/tls-app.d: Likewise. + * ld-arm/tls-lib.d: Likewise. + 2009-06-29 Nick Clifton <nickc@redhat.com> PR 10288 diff --git a/ld/testsuite/ld-arm/arm-app-abs32.d b/ld/testsuite/ld-arm/arm-app-abs32.d index 25c1754c43b..dbee189625b 100644 --- a/ld/testsuite/ld-arm/arm-app-abs32.d +++ b/ld/testsuite/ld-arm/arm-app-abs32.d @@ -12,7 +12,7 @@ Disassembly of section .plt: .*: e08fe00e add lr, pc, lr .*: e5bef008 ldr pc, \[lr, #8\]! .*: .* .* - .*: e28fc6.* add ip, pc, #.* ; .* + .*: e28fc6.* add ip, pc, #.* .*: e28cca.* add ip, ip, #.* ; .* .*: e5bcf.* ldr pc, \[ip, #.*\]!.* Disassembly of section .text: diff --git a/ld/testsuite/ld-arm/arm-app.d b/ld/testsuite/ld-arm/arm-app.d index dfb41413cd8..7730e904117 100644 --- a/ld/testsuite/ld-arm/arm-app.d +++ b/ld/testsuite/ld-arm/arm-app.d @@ -12,7 +12,7 @@ Disassembly of section .plt: .*: e08fe00e add lr, pc, lr .*: e5bef008 ldr pc, \[lr, #8\]! .*: .* - .*: e28fc6.* add ip, pc, #.* ; 0x.* + .*: e28fc6.* add ip, pc, #.* .*: e28cca.* add ip, ip, #.* ; 0x.* .*: e5bcf.* ldr pc, \[ip, #.*\]!.* Disassembly of section .text: diff --git a/ld/testsuite/ld-arm/arm-be8.d b/ld/testsuite/ld-arm/arm-be8.d index 9a7207fc9ad..16090b3d663 100644 --- a/ld/testsuite/ld-arm/arm-be8.d +++ b/ld/testsuite/ld-arm/arm-be8.d @@ -4,11 +4,11 @@ Disassembly of section .text: 00008000 <arm>: - 8000: e3a00000 mov r0, #0 ; 0x0 + 8000: e3a00000 mov r0, #0 8004: e12fff1e bx lr 00008008 <thumb>: - 8008: 46c0 nop \(mov r8, r8\) + 8008: 46c0 nop ; \(mov r8, r8\) 800a: 4770 bx lr 800c: f7ff fffc bl 8008 <thumb> diff --git a/ld/testsuite/ld-arm/arm-call.d b/ld/testsuite/ld-arm/arm-call.d index f4a9d789720..891208d074c 100644 --- a/ld/testsuite/ld-arm/arm-call.d +++ b/ld/testsuite/ld-arm/arm-call.d @@ -26,7 +26,7 @@ Disassembly of section .text: 00008038 <t4>: 8038: 4770 bx lr - 803a: 46c0 nop \(mov r8, r8\) + 803a: 46c0 nop ; \(mov r8, r8\) 0000803c <arm>: 803c: e12fff1e bx lr @@ -40,7 +40,7 @@ Disassembly of section .text: 0000804a <t5>: 804a: f000 f801 bl 8050 <local_thumb> - 804e: 46c0 nop \(mov r8, r8\) + 804e: 46c0 nop ; \(mov r8, r8\) 00008050 <local_thumb>: 8050: f7ff fff1 bl 8036 <t3> diff --git a/ld/testsuite/ld-arm/arm-lib-plt32.d b/ld/testsuite/ld-arm/arm-lib-plt32.d index 55fdd5889a6..3413dffeb6c 100644 --- a/ld/testsuite/ld-arm/arm-lib-plt32.d +++ b/ld/testsuite/ld-arm/arm-lib-plt32.d @@ -12,7 +12,7 @@ Disassembly of section .plt: .*: e08fe00e add lr, pc, lr .*: e5bef008 ldr pc, \[lr, #8\]! .*: .* - .*: e28fc6.* add ip, pc, #.* ; 0x.* + .*: e28fc6.* add ip, pc, #.* .*: e28cca.* add ip, ip, #.* ; 0x.* .*: e5bcf.* ldr pc, \[ip, #.*\]!.* Disassembly of section .text: diff --git a/ld/testsuite/ld-arm/arm-lib.d b/ld/testsuite/ld-arm/arm-lib.d index 132f0602475..3a1c777ca42 100644 --- a/ld/testsuite/ld-arm/arm-lib.d +++ b/ld/testsuite/ld-arm/arm-lib.d @@ -12,7 +12,7 @@ Disassembly of section .plt: .*: e08fe00e add lr, pc, lr .*: e5bef008 ldr pc, \[lr, #8\]! .*: .* - .*: e28fc6.* add ip, pc, #.* ; 0x.* + .*: e28fc6.* add ip, pc, #.* .*: e28cca.* add ip, ip, #.* ; 0x.* .*: e5bcf.* ldr pc, \[ip, #.*\]!.* Disassembly of section .text: diff --git a/ld/testsuite/ld-arm/arm-movwt.d b/ld/testsuite/ld-arm/arm-movwt.d index bf551648d6d..7d558b76170 100644 --- a/ld/testsuite/ld-arm/arm-movwt.d +++ b/ld/testsuite/ld-arm/arm-movwt.d @@ -4,21 +4,21 @@ Disassembly of section .text: 00008000 <[^>]*>: - 8000: e3000000 movw r0, #0 ; 0x0 + 8000: e3000000 movw r0, #0 8004: e3411234 movt r1, #4660 ; 0x1234 8008: e3082000 movw r2, #32768 ; 0x8000 800c: e3413233 movt r3, #4659 ; 0x1233 - 8010: e3004011 movw r4, #17 ; 0x11 + 8010: e3004011 movw r4, #17 8014: e3415234 movt r5, #4660 ; 0x1234 8018: e3086011 movw r6, #32785 ; 0x8011 801c: e3417233 movt r7, #4659 ; 0x1233 00008020 <[^>]*>: - 8020: f240 0700 movw r7, #0 ; 0x0 + 8020: f240 0700 movw r7, #0 8024: f2c1 2634 movt r6, #4660 ; 0x1234 8028: f248 0500 movw r5, #32768 ; 0x8000 802c: f2c1 2433 movt r4, #4659 ; 0x1233 - 8030: f240 0311 movw r3, #17 ; 0x11 + 8030: f240 0311 movw r3, #17 8034: f2c1 2234 movt r2, #4660 ; 0x1234 8038: f248 0111 movw r1, #32785 ; 0x8011 803c: f2c1 2033 movt r0, #4659 ; 0x1233 diff --git a/ld/testsuite/ld-arm/arm-pic-veneer.d b/ld/testsuite/ld-arm/arm-pic-veneer.d index edcdb83fc77..08e107b6626 100644 --- a/ld/testsuite/ld-arm/arm-pic-veneer.d +++ b/ld/testsuite/ld-arm/arm-pic-veneer.d @@ -7,7 +7,7 @@ Disassembly of section .text: 8000: ea...... b 800. <.*> 00008004 <foo>: - 8004: 46c0 nop \(mov r8, r8\) + 8004: 46c0 nop ; \(mov r8, r8\) 8006: 4770 bx lr 00008008 <__foo_from_arm>: diff --git a/ld/testsuite/ld-arm/armthumb-lib.d b/ld/testsuite/ld-arm/armthumb-lib.d index 497cb340b5a..6486ad55338 100644 --- a/ld/testsuite/ld-arm/armthumb-lib.d +++ b/ld/testsuite/ld-arm/armthumb-lib.d @@ -12,7 +12,7 @@ Disassembly of section .plt: .*: e08fe00e add lr, pc, lr .*: e5bef008 ldr pc, \[lr, #8\]! .*: .* - .*: e28fc6.* add ip, pc, #.* ; 0x.* + .*: e28fc6.* add ip, pc, #.* .*: e28cca.* add ip, ip, #.* ; 0x.* .*: e5bcf.* ldr pc, \[ip, #.*\]!.* Disassembly of section .text: @@ -23,19 +23,19 @@ Disassembly of section .text: .*: ebfffff. bl .* <lib_func1-0x..?> .*: e89d6800 ldm sp, {fp, sp, lr} .*: e12fff1e bx lr - .*: e1a00000 nop \(mov r0,r0\) - .*: e1a00000 nop \(mov r0,r0\) - .*: e1a00000 nop \(mov r0,r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) .* <__real_lib_func2>: .*: 4770 bx lr - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) .* <lib_func2>: .*: e59fc004 ldr ip, \[pc, #4\] ; .* <lib_func2\+0xc> diff --git a/ld/testsuite/ld-arm/armv4-bx.d b/ld/testsuite/ld-arm/armv4-bx.d index 095b38740f8..b30af8c3493 100644 --- a/ld/testsuite/ld-arm/armv4-bx.d +++ b/ld/testsuite/ld-arm/armv4-bx.d @@ -9,11 +9,11 @@ Disassembly of section \.text: 8008: 0a000002 beq 8018 \<__bx_r0\> 0000800c <__bx_r14>: - 800c: e31e0001 tst lr, #1 ; 0x1 + 800c: e31e0001 tst lr, #1 8010: 01a0f00e moveq pc, lr 8014: e12fff1e bx lr 00008018 <__bx_r0>: - 8018: e3100001 tst r0, #1 ; 0x1 + 8018: e3100001 tst r0, #1 801c: 01a0f000 moveq pc, r0 8020: e12fff10 bx r0 diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-arm.d b/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-arm.d index 0a2b0bd47f3..195a51bd45b 100644 --- a/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-arm.d +++ b/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-arm.d @@ -79,5 +79,5 @@ Disassembly of section \.text: 00009010 <__targetfn_from_thumb>: 9010: 4778 bx pc - 9012: 46c0 nop \(mov r8, r8\) + 9012: 46c0 nop ; \(mov r8, r8\) 9014: eaffffb9 b 8f00 <targetfn> diff --git a/ld/testsuite/ld-arm/farcall-mixed-app-v5.d b/ld/testsuite/ld-arm/farcall-mixed-app-v5.d index 035d1f87e6a..d0ff22e43a5 100644 --- a/ld/testsuite/ld-arm/farcall-mixed-app-v5.d +++ b/ld/testsuite/ld-arm/farcall-mixed-app-v5.d @@ -12,10 +12,10 @@ Disassembly of section .plt: .*: e08fe00e add lr, pc, lr .*: e5bef008 ldr pc, \[lr, #8\]! .*: .* - .*: e28fc6.* add ip, pc, #.* ; 0x.* + .*: e28fc6.* add ip, pc, #.* .*: e28cca.* add ip, ip, #.* ; 0x.* .*: e5bcf.* ldr pc, \[ip, #.*\]!.* - .*: e28fc6.* add ip, pc, #.* ; 0x.* + .*: e28fc6.* add ip, pc, #.* .*: e28cca.* add ip, ip, #.* ; 0x.* .*: e5bcf.* ldr pc, \[ip, #.*\]!.* @@ -29,16 +29,16 @@ Disassembly of section .text: .*: ebfffff4 bl .* <_start-0x18> .*: e89d6800 ldm sp, {fp, sp, lr} .*: e12fff1e bx lr - .*: e1a00000 nop \(mov r0,r0\) + .*: e1a00000 nop ; \(mov r0, r0\) .* <app_tfunc_close>: .*: b500 push {lr} .*: f7ff efe2 blx .* <_start-0x18> .*: bd00 pop {pc} .*: 4770 bx lr - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) .* <__app_func_veneer>: .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__app_func_veneer\+0x4> @@ -53,14 +53,14 @@ Disassembly of section .far_arm: .*: eb000007 bl .* <__lib_func2_veneer> .*: e89d6800 ldm sp, {fp, sp, lr} .*: e12fff1e bx lr - .*: e1a00000 nop \(mov r0,r0\) - .*: e1a00000 nop \(mov r0,r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) .* <app_func2>: .*: e12fff1e bx lr - .*: e1a00000 nop \(mov r0,r0\) - .*: e1a00000 nop \(mov r0,r0\) - .*: e1a00000 nop \(mov r0,r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) .* <__lib_func2_veneer>: .*: e51ff004 ldr pc, \[pc, #-4\] ; 2100034 <__lib_func2_veneer\+0x4> @@ -76,9 +76,9 @@ Disassembly of section .far_thumb: .*: f000 e806 blx .* <__lib_func2_from_thumb> .*: bd00 pop {pc} .*: 4770 bx lr - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) .* <__lib_func2_from_thumb>: .*: e51ff004 ldr pc, \[pc, #-4\] ; 2200014 <__lib_func2_from_thumb\+0x4> diff --git a/ld/testsuite/ld-arm/farcall-mixed-app.d b/ld/testsuite/ld-arm/farcall-mixed-app.d index 695c49a295b..5b6eafb6536 100644 --- a/ld/testsuite/ld-arm/farcall-mixed-app.d +++ b/ld/testsuite/ld-arm/farcall-mixed-app.d @@ -13,11 +13,11 @@ Disassembly of section .plt: .*: e5bef008 ldr pc, \[lr, #8\]! .*: .* .*: 4778 bx pc - .*: 46c0 nop \(mov r8, r8\) - .*: e28fc6.* add ip, pc, #.* ; 0x.* + .*: 46c0 nop ; \(mov r8, r8\) + .*: e28fc6.* add ip, pc, #.* .*: e28cca.* add ip, ip, #.* ; 0x.* .*: e5bcf.* ldr pc, \[ip, #.*\]!.* - .*: e28fc6.* add ip, pc, #.* ; 0x.* + .*: e28fc6.* add ip, pc, #.* .*: e28cca.* add ip, ip, #.* ; 0x.* .*: e5bcf.* ldr pc, \[ip, #.*\]!.* @@ -31,16 +31,16 @@ Disassembly of section .text: .*: ebfffff1 bl .* <_start-0x24> .*: e89d6800 ldm sp, {fp, sp, lr} .*: e12fff1e bx lr - .*: e1a00000 nop \(mov r0,r0\) + .*: e1a00000 nop ; \(mov r0, r0\) .* <app_tfunc_close>: .*: b500 push {lr} .*: f7ff ffd9 bl 8218 <_start-0x28> .*: bd00 pop {pc} .*: 4770 bx lr - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) .* <__app_func_veneer>: .*: e51ff004 ldr pc, \[pc, #-4\] ; 8274 <__app_func_veneer\+0x4> @@ -55,14 +55,14 @@ Disassembly of section .far_arm: .*: eb000007 bl .* <__lib_func2_veneer> .*: e89d6800 ldm sp, {fp, sp, lr} .*: e12fff1e bx lr - .*: e1a00000 nop \(mov r0,r0\) - .*: e1a00000 nop \(mov r0,r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) .* <app_func2>: .*: e12fff1e bx lr - .*: e1a00000 nop \(mov r0,r0\) - .*: e1a00000 nop \(mov r0,r0\) - .*: e1a00000 nop \(mov r0,r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) .* <__lib_func2_veneer>: .*: e51ff004 ldr pc, \[pc, #-4\] ; 2100034 <__lib_func2_veneer\+0x4> @@ -78,13 +78,13 @@ Disassembly of section .far_thumb: .*: f000 f805 bl .* <__lib_func2_from_thumb> .*: bd00 pop {pc} .*: 4770 bx lr - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) .* <__lib_func2_from_thumb>: .*: 4778 bx pc - .*: 46c0 nop \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) .*: e51ff004 ldr pc, \[pc, #-4\] ; 2200018 <__lib_func2_from_thumb\+0x8> .*: 0000821c .word 0x0000821c .*: 00000000 .word 0x00000000 diff --git a/ld/testsuite/ld-arm/farcall-mixed-lib.d b/ld/testsuite/ld-arm/farcall-mixed-lib.d index 2cf164eb2cf..e03fb3c6add 100644 --- a/ld/testsuite/ld-arm/farcall-mixed-lib.d +++ b/ld/testsuite/ld-arm/farcall-mixed-lib.d @@ -11,16 +11,16 @@ Disassembly of section .plt: .*: e08fe00e add lr, pc, lr .*: e5bef008 ldr pc, \[lr, #8\]! .*: .* - .*: e28fc6.* add ip, pc, #.* ; 0x.* + .*: e28fc6.* add ip, pc, #.* .*: e28cca.* add ip, ip, #.* ; 0x.* .*: e5bcf.* ldr pc, \[ip, #.*\]!.* - .*: e28fc6.* add ip, pc, #.* ; 0x.* + .*: e28fc6.* add ip, pc, #.* .*: e28cca.* add ip, ip, #.* ; 0x.* .*: e5bcf.* ldr pc, \[ip, #.*\]!.* - .*: e28fc6.* add ip, pc, #.* ; 0x.* + .*: e28fc6.* add ip, pc, #.* .*: e28cca.* add ip, ip, #.* ; 0x.* .*: e5bcf.* ldr pc, \[ip, #.*\]!.* - .*: e28fc6.* add ip, pc, #.* ; 0x.* + .*: e28fc6.* add ip, pc, #.* .*: e28cca.* add ip, ip, #.* ; 0x.* .*: e5bcf.* ldr pc, \[ip, #.*\]!.* @@ -43,13 +43,13 @@ Disassembly of section .text: .*: f000 e810 blx 100035c <__lib_func3_from_thumb> .*: f000 e81a blx 1000374 <__lib_func4_from_thumb> .*: 4770 bx lr - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) .* <__app_func_from_thumb>: .*: e59fc000 ldr ip, \[pc, #0\] ; 1000358 <__app_func_from_thumb\+0x8> @@ -76,9 +76,9 @@ Disassembly of section .text: .*: f000 e80c blx 20003ac <__app_func_from_thumb> .*: f000 e804 blx 20003a0 <__app_func_weak_from_thumb> .*: 4770 bx lr - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) .* <__app_func_weak_from_thumb>: .*: e59fc000 ldr ip, \[pc, #0\] ; 20003a8 <__app_func_weak_from_thumb\+0x8> diff --git a/ld/testsuite/ld-arm/farcall-thumb-arm-pic-veneer.d b/ld/testsuite/ld-arm/farcall-thumb-arm-pic-veneer.d index 6ac6e5c0f93..e22824adbea 100644 --- a/ld/testsuite/ld-arm/farcall-thumb-arm-pic-veneer.d +++ b/ld/testsuite/ld-arm/farcall-thumb-arm-pic-veneer.d @@ -9,7 +9,7 @@ Disassembly of section .text: 00001008 <__bar_from_thumb>: 1008: 4778 bx pc - 100a: 46c0 nop \(mov r8, r8\) + 100a: 46c0 nop ; \(mov r8, r8\) 100c: e59fc000 ldr ip, \[pc, #0\] ; 1014 <__bar_from_thumb\+0xc> 1010: e08cf00f add pc, ip, pc 1014: 01fffffc .word 0x01fffffc diff --git a/ld/testsuite/ld-arm/farcall-thumb-arm-short.d b/ld/testsuite/ld-arm/farcall-thumb-arm-short.d index ed235d3b02a..f4caf87b87a 100644 --- a/ld/testsuite/ld-arm/farcall-thumb-arm-short.d +++ b/ld/testsuite/ld-arm/farcall-thumb-arm-short.d @@ -9,7 +9,7 @@ Disassembly of section .text: 00001008 <__bar_from_thumb>: 1008: 4778 bx pc - 100a: 46c0 nop \(mov r8, r8\) + 100a: 46c0 nop ; \(mov r8, r8\) 100c: ea000400 b 2014 <bar> Disassembly of section .foo: diff --git a/ld/testsuite/ld-arm/farcall-thumb-arm.d b/ld/testsuite/ld-arm/farcall-thumb-arm.d index 25ee1f4fce1..fb12cf03557 100644 --- a/ld/testsuite/ld-arm/farcall-thumb-arm.d +++ b/ld/testsuite/ld-arm/farcall-thumb-arm.d @@ -9,7 +9,7 @@ Disassembly of section .text: 00001008 <__bar_from_thumb>: 1008: 4778 bx pc - 100a: 46c0 nop \(mov r8, r8\) + 100a: 46c0 nop ; \(mov r8, r8\) 100c: e51ff004 ldr pc, \[pc, #-4\] ; 1010 <__bar_from_thumb\+0x8> 1010: 02001014 .word 0x02001014 1014: 00000000 .word 0x00000000 diff --git a/ld/testsuite/ld-arm/farcall-thumb-thumb-m-pic-veneer.d b/ld/testsuite/ld-arm/farcall-thumb-thumb-m-pic-veneer.d index c96ea3f19a4..79e6449dc0e 100644 --- a/ld/testsuite/ld-arm/farcall-thumb-thumb-m-pic-veneer.d +++ b/ld/testsuite/ld-arm/farcall-thumb-thumb-m-pic-veneer.d @@ -9,7 +9,7 @@ Disassembly of section .text: 00001008 <__bar_veneer>: 1008: b401 push {r0} - 100a: 4802 ldr r0, \[pc, #8\] \(1014 <__bar_veneer\+0xc>\) + 100a: 4802 ldr r0, \[pc, #8\] ; \(1014 <__bar_veneer\+0xc>\) 100c: 46fc mov ip, pc 100e: 4484 add ip, r0 1010: bc01 pop {r0} diff --git a/ld/testsuite/ld-arm/farcall-thumb-thumb-m.d b/ld/testsuite/ld-arm/farcall-thumb-thumb-m.d index c98f00a2904..84782b8151e 100644 --- a/ld/testsuite/ld-arm/farcall-thumb-thumb-m.d +++ b/ld/testsuite/ld-arm/farcall-thumb-thumb-m.d @@ -9,7 +9,7 @@ Disassembly of section .text: 00001008 <__bar_veneer>: 1008: b401 push {r0} - 100a: 4802 ldr r0, \[pc, #8\] \(1014 <__bar_veneer\+0xc>\) + 100a: 4802 ldr r0, \[pc, #8\] ; \(1014 <__bar_veneer\+0xc>\) 100c: 4684 mov ip, r0 100e: bc01 pop {r0} 1010: 4760 bx ip diff --git a/ld/testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d b/ld/testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d index 96549a59a30..8c2cddf9107 100644 --- a/ld/testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d +++ b/ld/testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d @@ -9,7 +9,7 @@ Disassembly of section .text: 00001008 <__bar_veneer>: 1008: 4778 bx pc - 100a: 46c0 nop \(mov r8, r8\) + 100a: 46c0 nop ; \(mov r8, r8\) 100c: e59fc004 ldr ip, \[pc, #4\] ; 1018 <__bar_veneer\+0x10> 1010: e08fc00c add ip, pc, ip 1014: e12fff1c bx ip diff --git a/ld/testsuite/ld-arm/farcall-thumb-thumb.d b/ld/testsuite/ld-arm/farcall-thumb-thumb.d index e4a96eaae88..8ea41c7ba24 100644 --- a/ld/testsuite/ld-arm/farcall-thumb-thumb.d +++ b/ld/testsuite/ld-arm/farcall-thumb-thumb.d @@ -9,7 +9,7 @@ Disassembly of section .text: 00001008 <__bar_veneer>: 1008: 4778 bx pc - 100a: 46c0 nop \(mov r8, r8\) + 100a: 46c0 nop ; \(mov r8, r8\) 100c: e59fc000 ldr ip, \[pc, #0\] ; 1014 <__bar_veneer\+0xc> 1010: e12fff1c bx ip 1014: 02001015 .word 0x02001015 diff --git a/ld/testsuite/ld-arm/group-relocs.d b/ld/testsuite/ld-arm/group-relocs.d index 2f072f96274..e81739dc803 100644 --- a/ld/testsuite/ld-arm/group-relocs.d +++ b/ld/testsuite/ld-arm/group-relocs.d @@ -10,7 +10,7 @@ Disassembly of section .text: 800c: e28f08ff add r0, pc, #16711680 ; 0xff0000 8010: e2800c6e add r0, r0, #28160 ; 0x6e00 8014: e28000e4 add r0, r0, #228 ; 0xe4 - 8018: e2800000 add r0, r0, #0 ; 0x0 + 8018: e2800000 add r0, r0, #0 801c: e28f0cee add r0, pc, #60928 ; 0xee00 8020: e28000f0 add r0, r0, #240 ; 0xf0 8024: e28008ff add r0, r0, #16711680 ; 0xff0000 @@ -53,17 +53,17 @@ Disassembly of section .text: 80b8: ed90003c ldc 0, cr0, \[r0, #240\].* 000080bc <one_group_needed_alu_pc>: - 80bc: e3a00000 mov r0, #0 ; 0x0 + 80bc: e3a00000 mov r0, #0 Disassembly of section zero: 00000000 <one_group_needed_alu_sb>: - 0: e3a00000 mov r0, #0 ; 0x0 + 0: e3a00000 mov r0, #0 Disassembly of section alpha: 0000eef0 <two_groups_needed_alu_pc>: - eef0: e3a00000 mov r0, #0 ; 0x0 + eef0: e3a00000 mov r0, #0 Disassembly of section beta: 00ffeef0 <three_groups_needed_alu_pc>: - ffeef0: e3a00000 mov r0, #0 ; 0x0 + ffeef0: e3a00000 mov r0, #0 #... diff --git a/ld/testsuite/ld-arm/mixed-app-v5.d b/ld/testsuite/ld-arm/mixed-app-v5.d index 426708b8129..0b1b986e368 100644 --- a/ld/testsuite/ld-arm/mixed-app-v5.d +++ b/ld/testsuite/ld-arm/mixed-app-v5.d @@ -12,10 +12,10 @@ Disassembly of section .plt: .*: e08fe00e add lr, pc, lr .*: e5bef008 ldr pc, \[lr, #8\]! .*: .* - .*: e28fc6.* add ip, pc, #.* ; 0x.* + .*: e28fc6.* add ip, pc, #.* .*: e28cca.* add ip, ip, #.* ; 0x.* .*: e5bcf.* ldr pc, \[ip, #.*\]!.* - .*: e28fc6.* add ip, pc, #.* ; 0x.* + .*: e28fc6.* add ip, pc, #.* .*: e28cca.* add ip, ip, #.* ; 0x.* .*: e5bcf.* ldr pc, \[ip, #.*\]!.* Disassembly of section .text: @@ -26,9 +26,9 @@ Disassembly of section .text: .*: eb000004 bl .* <app_func> .*: e89d6800 ldm sp, {fp, sp, lr} .*: e12fff1e bx lr - .*: e1a00000 nop \(mov r0,r0\) - .*: e1a00000 nop \(mov r0,r0\) - .*: e1a00000 nop \(mov r0,r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) .* <app_func>: .*: e1a0c00d mov ip, sp @@ -36,21 +36,21 @@ Disassembly of section .text: .*: ebfffff. bl .* .*: e89d6800 ldm sp, {fp, sp, lr} .*: e12fff1e bx lr - .*: e1a00000 nop \(mov r0,r0\) - .*: e1a00000 nop \(mov r0,r0\) - .*: e1a00000 nop \(mov r0,r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) .* <app_func2>: .*: e12fff1e bx lr - .*: e1a00000 nop \(mov r0,r0\) - .*: e1a00000 nop \(mov r0,r0\) - .*: e1a00000 nop \(mov r0,r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) .* <app_tfunc>: .*: b500 push {lr} .*: f7ff efc. blx .* <_start-0x..> .*: bd00 pop {pc} .*: 4770 bx lr - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) diff --git a/ld/testsuite/ld-arm/mixed-app.d b/ld/testsuite/ld-arm/mixed-app.d index 9d18b0a2957..d8188a2db77 100644 --- a/ld/testsuite/ld-arm/mixed-app.d +++ b/ld/testsuite/ld-arm/mixed-app.d @@ -13,11 +13,11 @@ Disassembly of section .plt: .*: e5bef008 ldr pc, \[lr, #8\]! .*: .* .*: 4778 bx pc - .*: 46c0 nop \(mov r8, r8\) - .*: e28fc6.* add ip, pc, #.* ; 0x.* + .*: 46c0 nop ; \(mov r8, r8\) + .*: e28fc6.* add ip, pc, #.* .*: e28cca.* add ip, ip, #.* ; 0x.* .*: e5bcf.* ldr pc, \[ip, #.*\]!.* - .*: e28fc6.* add ip, pc, #.* ; 0x.* + .*: e28fc6.* add ip, pc, #.* .*: e28cca.* add ip, ip, #.* ; 0x.* .*: e5bcf.* ldr pc, \[ip, #.*\]!.* Disassembly of section .text: @@ -28,9 +28,9 @@ Disassembly of section .text: .*: eb000004 bl .* <app_func> .*: e89d6800 ldm sp, {fp, sp, lr} .*: e12fff1e bx lr - .*: e1a00000 nop \(mov r0,r0\) - .*: e1a00000 nop \(mov r0,r0\) - .*: e1a00000 nop \(mov r0,r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) .* <app_func>: .*: e1a0c00d mov ip, sp @@ -38,21 +38,21 @@ Disassembly of section .text: .*: ebffff.. bl .* .*: e89d6800 ldm sp, {fp, sp, lr} .*: e12fff1e bx lr - .*: e1a00000 nop \(mov r0,r0\) - .*: e1a00000 nop \(mov r0,r0\) - .*: e1a00000 nop \(mov r0,r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) .* <app_func2>: .*: e12fff1e bx lr - .*: e1a00000 nop \(mov r0,r0\) - .*: e1a00000 nop \(mov r0,r0\) - .*: e1a00000 nop \(mov r0,r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) .* <app_tfunc>: .*: b500 push {lr} .*: f7ff ffc. bl .* <_start-0x..> .*: bd00 pop {pc} .*: 4770 bx lr - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) diff --git a/ld/testsuite/ld-arm/mixed-lib.d b/ld/testsuite/ld-arm/mixed-lib.d index 2fc40a6089e..bcd2e41fcd4 100644 --- a/ld/testsuite/ld-arm/mixed-lib.d +++ b/ld/testsuite/ld-arm/mixed-lib.d @@ -12,7 +12,7 @@ Disassembly of section .plt: .*: e08fe00e add lr, pc, lr .*: e5bef008 ldr pc, \[lr, #8\]! .*: .* - .*: e28fc6.* add ip, pc, #.* ; 0x.* + .*: e28fc6.* add ip, pc, #.* .*: e28cca.* add ip, ip, #.* ; 0x.* .*: e5bcf.* ldr pc, \[ip, #.*\]!.* Disassembly of section .text: @@ -23,16 +23,16 @@ Disassembly of section .text: .*: ebfffff. bl .* <lib_func1-0x..?> .*: e89d6800 ldm sp, {fp, sp, lr} .*: e12fff1e bx lr - .*: e1a00000 nop \(mov r0,r0\) - .*: e1a00000 nop \(mov r0,r0\) - .*: e1a00000 nop \(mov r0,r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) .* <lib_func2>: .*: 4770 bx lr - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) - .*: 46c0 nop \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) diff --git a/ld/testsuite/ld-arm/movw-merge.d b/ld/testsuite/ld-arm/movw-merge.d index 2df473780b5..40e1681af84 100644 --- a/ld/testsuite/ld-arm/movw-merge.d +++ b/ld/testsuite/ld-arm/movw-merge.d @@ -5,9 +5,9 @@ Disassembly of section .text: 00008000 <[^>]*>: 8000: e3080013 movw r0, #32787 ; 0x8013 - 8004: e3400000 movt r0, #0 ; 0x0 + 8004: e3400000 movt r0, #0 00008008 <[^>]*>: 8008: f248 0013 movw r0, #32787 ; 0x8013 - 800c: f2c0 0000 movt r0, #0 ; 0x0 + 800c: f2c0 0000 movt r0, #0 diff --git a/ld/testsuite/ld-arm/thumb2-b-interwork.d b/ld/testsuite/ld-arm/thumb2-b-interwork.d index b2f9a018009..431989c7f60 100644 --- a/ld/testsuite/ld-arm/thumb2-b-interwork.d +++ b/ld/testsuite/ld-arm/thumb2-b-interwork.d @@ -11,6 +11,6 @@ Disassembly of section .text: 00008008 <__bar_from_thumb>: 8008: 4778 bx pc - 800a: 46c0 nop \(mov r8, r8\) + 800a: 46c0 nop ; \(mov r8, r8\) 800c: eafffffc b 8004 <bar> diff --git a/ld/testsuite/ld-arm/tls-app.d b/ld/testsuite/ld-arm/tls-app.d index fd3d6380087..53ba947b7a7 100644 --- a/ld/testsuite/ld-arm/tls-app.d +++ b/ld/testsuite/ld-arm/tls-app.d @@ -7,8 +7,8 @@ start address 0x00008204 Disassembly of section .text: 00008204 <foo>: - 8204: e1a00000 nop \(mov r0,r0\) - 8208: e1a00000 nop \(mov r0,r0\) + 8204: e1a00000 nop ; \(mov r0, r0\) + 8208: e1a00000 nop ; \(mov r0, r0\) 820c: e1a0f00e mov pc, lr 8210: 000080bc .word 0x000080bc 8214: 000080b4 .word 0x000080b4 diff --git a/ld/testsuite/ld-arm/tls-lib.d b/ld/testsuite/ld-arm/tls-lib.d index 774ac91203f..4580ead4fdd 100644 --- a/ld/testsuite/ld-arm/tls-lib.d +++ b/ld/testsuite/ld-arm/tls-lib.d @@ -7,8 +7,8 @@ start address 0x.* Disassembly of section .text: .* <foo>: - .*: e1a00000 nop \(mov r0,r0\) - .*: e1a00000 nop \(mov r0,r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) .*: e1a0f00e mov pc, lr .*: 00008098 .word 0x00008098 .*: 0000808c .word 0x0000808c diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 2ba42d6ac26..d3febd0f39a 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,13 @@ +2009-06-30 Nick Clifton <nickc@redhat.com> + + PR 10288 + * arm-dis.c (coprocessor): Print the LDC and STC versions of the + LFM and SFM instructions as comments,. + Improve consistency of formatting for instructions displayed as + comments and decimal values displayed with their hexadecimal + equivalents. + Formatting tidy ups. + 2009-06-29 Nick Clifton <nickc@redhat.com> PR 10288 diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index bee84549322..20cb875ef92 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -48,8 +48,8 @@ struct opcode32 { unsigned long arch; /* Architecture defining this insn. */ - unsigned long value; /* Recognise insn if (op & mask) == value. */ - unsigned long mask; /* If arch == 0 then value is a sentinel. */ + unsigned long value; /* If arch == 0 then value is a sentinel. */ + unsigned long mask; /* Recognise insn if (op & mask) == value. */ const char * assembler; /* How to disassemble this insn. */ }; @@ -104,8 +104,7 @@ struct opcode16 versions. %i print 5-bit immediate in bits 8,3..0 (print "32" when 0) - %r print register offset address for wldt/wstr instruction -*/ + %r print register offset address for wldt/wstr instruction. */ enum { @@ -206,7 +205,7 @@ static const struct opcode32 coprocessor_opcodes[] = {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"}, { 0, SENTINEL_IWMMXT_END, 0, "" }, - /* Floating point coprocessor (FPA) instructions */ + /* Floating point coprocessor (FPA) instructions. */ {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, @@ -248,10 +247,10 @@ static const struct opcode32 coprocessor_opcodes[] = {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, - {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, - {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, + {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A\t; (stc%22'l%c %8-11d, cr%12-15d, %A)"}, + {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A\t; (ldc%22'l%c %8-11d, cr%12-15d, %A)"}, - /* Register load/store */ + /* Register load/store. */ {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"}, {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"}, {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"}, @@ -274,7 +273,7 @@ static const struct opcode32 coprocessor_opcodes[] = {FPU_VFP_EXT_V1xD, 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, {FPU_VFP_EXT_V1xD, 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, - /* Data transfer between ARM and NEON registers */ + /* Data transfer between ARM and NEON registers. */ {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"}, {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"}, {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"}, @@ -293,7 +292,7 @@ static const struct opcode32 coprocessor_opcodes[] = {FPU_NEON_FP16, 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"}, {FPU_NEON_FP16, 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"}, - /* Floating point coprocessor (VFP) instructions */ + /* Floating point coprocessor (VFP) instructions. */ {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"}, {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"}, {FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"}, @@ -500,20 +499,20 @@ static const struct opcode32 coprocessor_opcodes[] = %<bitfield>'c print specified char iff bitfield is all ones %<bitfield>`c print specified char iff bitfield is all zeroes - %<bitfield>?ab... select from array of values in big endian order */ + %<bitfield>?ab... select from array of values in big endian order. */ static const struct opcode32 neon_opcodes[] = { - /* Extract */ + /* Extract. */ {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, - /* Move data element to all lanes */ + /* Move data element to all lanes. */ {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"}, {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"}, {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"}, - /* Table lookup */ + /* Table lookup. */ {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"}, {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"}, @@ -521,7 +520,7 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_FP16, 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"}, {FPU_NEON_FP16, 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"}, - /* Two registers, miscellaneous */ + /* Two registers, miscellaneous. */ {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"}, @@ -556,7 +555,7 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"}, - /* Three registers of the same length */ + /* Three registers of the same length. */ {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, @@ -611,7 +610,7 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - /* One register and an immediate value */ + /* One register and an immediate value. */ {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"}, {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"}, {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"}, @@ -626,7 +625,7 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"}, {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"}, - /* Two registers and a shift amount */ + /* Two registers and a shift amount. */ {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, @@ -686,7 +685,7 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"}, - /* Three registers of different lengths */ + /* Three registers of different lengths. */ {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"}, {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, @@ -705,7 +704,7 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, - /* Two registers and a scalar */ + /* Two registers and a scalar. */ {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, @@ -729,7 +728,7 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, - /* Element and structure load/store */ + /* Element and structure load/store. */ {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"}, {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"}, {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"}, @@ -791,7 +790,7 @@ static const struct opcode32 neon_opcodes[] = static const struct opcode32 arm_opcodes[] = { /* ARM instructions. */ - {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"}, + {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"}, {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19r, %0-3r, %8-11r"}, {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, @@ -836,7 +835,7 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"}, {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"}, - /* ARM V6 instructions. */ + /* ARM V6 instructions. */ {ARM_EXT_V6, 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"}, {ARM_EXT_V6, 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"}, {ARM_EXT_V6, 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"}, @@ -1109,7 +1108,7 @@ static const struct opcode16 thumb_opcodes[] = /* This is BLX(2). BLX(1) is a 32-bit instruction. */ {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */ /* ARM V4T ISA (Thumb v1). */ - {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t(mov r8, r8)"}, + {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"}, /* Format 4. */ {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"}, {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"}, @@ -1160,7 +1159,7 @@ static const struct opcode16 thumb_opcodes[] = {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"}, {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"}, /* format 6 */ - {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t(%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */ + {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */ /* format 9 */ {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"}, {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"}, @@ -1173,7 +1172,7 @@ static const struct opcode16 thumb_opcodes[] = {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"}, {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"}, /* format 12 */ - {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t(adr %8-10r, %0-7a)"}, + {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"}, {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"}, /* format 15 */ {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"}, @@ -1520,7 +1519,8 @@ static bfd_vma ifthen_address; #define IFTHEN_COND ((ifthen_state >> 4) & 0xf) /* Cached mapping symbol state. */ -enum map_type { +enum map_type +{ MAP_ARM, MAP_THUMB, MAP_DATA @@ -1547,7 +1547,9 @@ set_arm_regname_option (int option) } int -get_arm_regnames (int option, const char **setname, const char **setdescription, +get_arm_regnames (int option, + const char **setname, + const char **setdescription, const char *const **register_names) { *setname = regnames[option].name; @@ -1559,11 +1561,13 @@ get_arm_regnames (int option, const char **setname, const char **setdescription, /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?. Returns pointer to following character of the format string and fills in *VALUEP and *WIDTHP with the extracted value and number of - bits extracted. WIDTHP can be NULL. */ + bits extracted. WIDTHP can be NULL. */ static const char * -arm_decode_bitfield (const char *ptr, unsigned long insn, - unsigned long *valuep, int *widthp) +arm_decode_bitfield (const char *ptr, + unsigned long insn, + unsigned long *valuep, + int *widthp) { unsigned long value = 0; int width = 0; @@ -1635,7 +1639,9 @@ arm_decode_shift (long given, fprintf_ftype func, void *stream, recognised coprocessor instruction. */ static bfd_boolean -print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given, +print_insn_coprocessor (bfd_vma pc, + struct disassemble_info *info, + long given, bfd_boolean thumb) { const struct opcode32 *insn; @@ -1734,9 +1740,8 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given, if ((given & (1 << 24)) != 0) { if (offset) - func (stream, ", #%s%d]%s", - ((given & 0x00800000) == 0 ? "-" : ""), - offset * 4, + func (stream, ", #%d]%s", + value_in_comment, ((given & 0x00200000) != 0 ? "!" : "")); else func (stream, "]"); @@ -1748,12 +1753,13 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given, if (given & (1 << 21)) { if (offset) - func (stream, ", #%s%d", - ((given & 0x00800000) == 0 ? "-" : ""), - offset * 4); + func (stream, ", #%d", value_in_comment); } else - func (stream, ", {%d}", offset); + { + func (stream, ", {%d}", offset); + value_in_comment = offset; + } } } break; @@ -1785,6 +1791,8 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given, if (!add) offset = -offset; func (stream, ", #%d", offset); + if (rn != 15) + value_in_comment = offset; } func (stream, "]"); if (rn == 15) @@ -1960,7 +1968,7 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given, func (stream, "%c", *c); break; case '?': - func (stream, "%c", c[(1 << width) - (int)value]); + func (stream, "%c", c[(1 << width) - (int) value]); c += 1 << width; break; default: @@ -2491,7 +2499,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) break; case 'E': - /* Neon encoded constant for mov, mvn, vorr, vbic */ + /* Neon encoded constant for mov, mvn, vorr, vbic. */ { int bits = 0; int cmode = (given >> 8) & 0xf; @@ -2508,19 +2516,19 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) if (cmode < 8) { shift = (cmode >> 1) & 3; - value = (unsigned long)bits << (8 * shift); + value = (unsigned long) bits << (8 * shift); size = 32; } else if (cmode < 12) { shift = (cmode >> 1) & 1; - value = (unsigned long)bits << (8 * shift); + value = (unsigned long) bits << (8 * shift); size = 16; } else if (cmode < 14) { shift = (cmode & 1) + 1; - value = (unsigned long)bits << (8 * shift); + value = (unsigned long) bits << (8 * shift); value |= (1ul << (8 * shift)) - 1; size = 32; } @@ -2528,7 +2536,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) { if (op) { - /* bit replication into bytes */ + /* Bit replication into bytes. */ int ix; unsigned long mask; @@ -2546,20 +2554,20 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) } else { - /* byte replication */ - value = (unsigned long)bits; + /* Byte replication. */ + value = (unsigned long) bits; size = 8; } } else if (!op) { - /* floating point encoding */ + /* Floating point encoding. */ int tmp; - value = (unsigned long)(bits & 0x7f) << 19; - value |= (unsigned long)(bits & 0x80) << 24; + value = (unsigned long) (bits & 0x7f) << 19; + value |= (unsigned long) (bits & 0x80) << 24; tmp = bits & 0x40 ? 0x3c : 0x40; - value |= (unsigned long)tmp << 24; + value |= (unsigned long) tmp << 24; size = 32; isfloat = 1; } @@ -2703,7 +2711,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) func (stream, "%c", *c); break; case '?': - func (stream, "%c", c[(1 << width) - (int)value]); + func (stream, "%c", c[(1 << width) - (int) value]); c += 1 << width; break; default: @@ -2796,27 +2804,28 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) } else { + int offset = ((given & 0xf00) >> 4) | (given & 0xf); + + if ((given & 0x00800000) == 0) + offset = -offset; + func (stream, "[%s", arm_regnames[(given >> 16) & 0xf]); + if ((given & 0x01000000) != 0) { /* Pre-indexed. */ if ((given & 0x00400000) == 0x00400000) { /* Immediate. */ - int offset = ((given & 0xf00) >> 4) | (given & 0xf); - if (offset) - func (stream, ", #%s%d", - (((given & 0x00800000) == 0) - ? "-" : ""), offset); + func (stream, ", #%d", offset); + value_in_comment = offset; } else { /* Register. */ - func (stream, ", %s%s", - (((given & 0x00800000) == 0) - ? "-" : ""), + func (stream, ", %s%s", offset < 0 ? "-" : "", arm_regnames[given & 0xf]); } @@ -2829,21 +2838,17 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) if ((given & 0x00400000) == 0x00400000) { /* Immediate. */ - int offset = ((given & 0xf00) >> 4) | (given & 0xf); - if (offset) - func (stream, "], #%s%d", - (((given & 0x00800000) == 0) - ? "-" : ""), offset); + func (stream, "], #%d", offset); else func (stream, "]"); + + value_in_comment = offset; } else { /* Register. */ - func (stream, "], %s%s", - (((given & 0x00800000) == 0) - ? "-" : ""), + func (stream, "], %s%s", offset < 0 ? "-" : "", arm_regnames[given & 0xf]); } } @@ -2890,9 +2895,11 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) { int rotate = (given & 0xf00) >> 7; int immed = (given & 0xff); + immed = (((immed << (32 - rotate)) | (immed >> rotate)) & 0xffffffff); - func (stream, "#%d\t; 0x%x", immed, immed); + func (stream, "#%d", immed); + value_in_comment = immed; } else arm_decode_shift (given, func, stream, 1); @@ -2921,9 +2928,8 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) if ((given & (1 << 24)) != 0) { if (offset) - func (stream, ", #%s%d]%s", - ((given & 0x00800000) == 0 ? "-" : ""), - offset * 4, + func (stream, ", #%d]%s", + value_in_comment, ((given & 0x00200000) != 0 ? "!" : "")); else func (stream, "]"); @@ -2935,12 +2941,13 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) if (given & (1 << 21)) { if (offset) - func (stream, ", #%s%d", - ((given & 0x00800000) == 0 ? "-" : ""), - offset * 4); + func (stream, ", #%d", value_in_comment); } else - func (stream, ", {%d}", offset); + { + func (stream, ", {%d}", offset); + value_in_comment = offset; + } } } break; @@ -2983,12 +2990,12 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) case 'U': switch (given & 0xf) { - case 0xf: func(stream, "sy"); break; - case 0x7: func(stream, "un"); break; - case 0xe: func(stream, "st"); break; - case 0x6: func(stream, "unst"); break; + case 0xf: func (stream, "sy"); break; + case 0x7: func (stream, "un"); break; + case 0xe: func (stream, "st"); break; + case 0x6: func (stream, "unst"); break; default: - func(stream, "#%d", (int)given & 0xf); + func (stream, "#%d", (int) given & 0xf); break; } break; @@ -3043,7 +3050,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) func (stream, "%c", *c); break; case '?': - func (stream, "%c", c[(1 << width) - (int)value]); + func (stream, "%c", c[(1 << width) - (int) value]); c += 1 << width; break; default: @@ -3057,6 +3064,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) imm = (given & 0xf) | ((given & 0xfff00) >> 4); func (stream, "%d", imm); + value_in_comment = imm; } break; @@ -3066,8 +3074,8 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) { long msb = (given & 0x001f0000) >> 16; long lsb = (given & 0x00000f80) >> 7; - long width = msb - lsb + 1; + if (width > 0) func (stream, "#%lu, #%lu", lsb, width); else @@ -3082,7 +3090,9 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) long hi = (given & 0x000f0000) >> 4; long lo = (given & 0x00000fff); long imm16 = hi | lo; - func (stream, "#%lu\t; 0x%lx", imm16, imm16); + + func (stream, "#%lu", imm16); + value_in_comment = imm16; } break; @@ -3366,6 +3376,7 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) } /* Return the name of an V7M special register. */ + static const char * psr_name (int regno) { @@ -3443,16 +3454,19 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) case 'I': { unsigned int imm12 = 0; + imm12 |= (given & 0x000000ffu); imm12 |= (given & 0x00007000u) >> 4; imm12 |= (given & 0x04000000u) >> 15; - func (stream, "#%u\t; 0x%x", imm12, imm12); + func (stream, "#%u", imm12); + value_in_comment = imm12; } break; case 'M': { unsigned int bits = 0, imm, imm8, mod; + bits |= (given & 0x000000ffu); bits |= (given & 0x00007000u) >> 4; bits |= (given & 0x04000000u) >> 15; @@ -3469,28 +3483,33 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) imm8 = (bits & 0x07f) | 0x80; imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff); } - func (stream, "#%u\t; 0x%x", imm, imm); + func (stream, "#%u", imm); + value_in_comment = imm; } break; case 'J': { unsigned int imm = 0; + imm |= (given & 0x000000ffu); imm |= (given & 0x00007000u) >> 4; imm |= (given & 0x04000000u) >> 15; imm |= (given & 0x000f0000u) >> 4; - func (stream, "#%u\t; 0x%x", imm, imm); + func (stream, "#%u", imm); + value_in_comment = imm; } break; case 'K': { unsigned int imm = 0; + imm |= (given & 0x000f0000u) >> 16; imm |= (given & 0x00000ff0u) >> 0; imm |= (given & 0x0000000fu) << 12; - func (stream, "#%u\t; 0x%x", imm, imm); + func (stream, "#%u", imm); + value_in_comment = imm; } break; @@ -3643,7 +3662,10 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) value_in_comment = off * 4 * U ? 1 : -1; } else - func (stream, "{%u}", off); + { + func (stream, "{%u}", off); + value_in_comment = off; + } } } break; @@ -3690,6 +3712,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) { unsigned int msb = (given & 0x0000001f); unsigned int lsb = 0; + lsb |= (given & 0x000000c0u) >> 6; lsb |= (given & 0x00007000u) >> 10; func (stream, "#%u, #%u", lsb, msb - lsb + 1); @@ -3700,6 +3723,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) { unsigned int width = (given & 0x0000001f) + 1; unsigned int lsb = 0; + lsb |= (given & 0x000000c0u) >> 6; lsb |= (given & 0x00007000u) >> 10; func (stream, "#%u, #%u", lsb, width); @@ -3750,6 +3774,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) case 's': { unsigned int shift = 0; + shift |= (given & 0x000000c0u) >> 6; shift |= (given & 0x00007000u) >> 10; if (given & 0x00200000u) @@ -3763,6 +3788,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) case 'R': { unsigned int rot = (given & 0x00000030) >> 4; + if (rot) func (stream, ", ror #%u", rot * 8); } @@ -3771,12 +3797,12 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) case 'U': switch (given & 0xf) { - case 0xf: func(stream, "sy"); break; - case 0x7: func(stream, "un"); break; - case 0xe: func(stream, "st"); break; - case 0x6: func(stream, "unst"); break; + case 0xf: func (stream, "sy"); break; + case 0x7: func (stream, "un"); break; + case 0xe: func (stream, "st"); break; + case 0x6: func (stream, "unst"); break; default: - func(stream, "#%d", (int)given & 0xf); + func (stream, "#%d", (int) given & 0xf); break; } break; @@ -3844,7 +3870,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) break; case '?': - func (stream, "%c", c[(1 << width) - (int)val]); + func (stream, "%c", c[(1 << width) - (int) val]); c += 1 << width; break; @@ -3871,7 +3897,8 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) /* Print data bytes on INFO->STREAM. */ static void -print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, struct disassemble_info *info, +print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, + struct disassemble_info *info, long given) { switch (info->bytes_per_chunk) @@ -3967,8 +3994,10 @@ parse_disassembler_options (char *options) /* Search back through the insn stream to determine if this instruction is conditionally executed. */ + static void -find_ifthen_state (bfd_vma pc, struct disassemble_info *info, +find_ifthen_state (bfd_vma pc, + struct disassemble_info *info, bfd_boolean little) { unsigned char b[2]; @@ -3993,7 +4022,7 @@ find_ifthen_state (bfd_vma pc, struct disassemble_info *info, IT instruction until we find a definite instruction boundary. */ for (;;) { - if (addr == 0 || info->symbol_at_address_func(addr, info)) + if (addr == 0 || info->symbol_at_address_func (addr, info)) { /* A symbol must be on an instruction boundary, and will not be within an IT block. */ @@ -4003,7 +4032,7 @@ find_ifthen_state (bfd_vma pc, struct disassemble_info *info, return; } addr -= 2; - status = info->read_memory_func (addr, (bfd_byte *)b, 2, info); + status = info->read_memory_func (addr, (bfd_byte *) b, 2, info); if (status) return; @@ -4047,7 +4076,8 @@ find_ifthen_state (bfd_vma pc, struct disassemble_info *info, Returns nonzero if *MAP_TYPE was set. */ static int -get_sym_code_type (struct disassemble_info *info, int n, +get_sym_code_type (struct disassemble_info *info, + int n, enum map_type *map_type) { elf_symbol_type *es; @@ -4065,7 +4095,7 @@ get_sym_code_type (struct disassemble_info *info, int n, } /* Check for mapping symbols. */ - name = bfd_asymbol_name(info->symtab[n]); + name = bfd_asymbol_name (info->symtab[n]); if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd') && (name[2] == 0 || name[2] == '.')) { @@ -4315,7 +4345,7 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) info->bytes_per_chunk = size; printer = print_insn_data; - status = info->read_memory_func (pc, (bfd_byte *)b, size, info); + status = info->read_memory_func (pc, (bfd_byte *) b, size, info); given = 0; if (little) for (i = size - 1; i >= 0; i--) @@ -4348,7 +4378,7 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) info->bytes_per_chunk = 2; size = 2; - status = info->read_memory_func (pc, (bfd_byte *)b, 2, info); + status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); if (little_code) given = (b[0]) | (b[1] << 8); else |