diff options
37 files changed, 17361 insertions, 16720 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index e829630c7e1..7e4fd19e002 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,50 @@ +2005-10-28 Dave Brolley <brolley@redhat.com> + + * All CGEN-generated sources: Regenerate. + + Contribute the following changes: + 2005-09-19 Dave Brolley <brolley@redhat.com> + + * disassemble.c (disassemble_init_for_target): Add 'break' to case for + bfd_arch_tic4x. Use cgen_bitset_create and cgen_bitset_set for + bfd_arch_m32c case. + + 2005-02-16 Dave Brolley <brolley@redhat.com> + + * cgen-dis.in: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename + cgen_isa_mask_* to cgen_bitset_*. + * cgen-opc.c: Likewise. + + 2003-11-28 Richard Sandiford <rsandifo@redhat.com> + + * cgen-dis.in (print_insn_@arch@): Fix comparison with cached isas. + * *-dis.c: Regenerate. + + 2003-06-05 DJ Delorie <dj@redhat.com> + + * cgen-dis.in (print_insn_@arch@): Copy prev_isas, don't assign + it, as it may point to a reused buffer. Set prev_isas when we + change cpus. + + 2002-12-13 Dave Brolley <brolley@redhat.com> + + * cgen-opc.c (cgen_isa_mask_create): New support function for + CGEN_ISA_MASK. + (cgen_isa_mask_init): Ditto. + (cgen_isa_mask_clear): Ditto. + (cgen_isa_mask_add): Ditto. + (cgen_isa_mask_set): Ditto. + (cgen_isa_supported): Ditto. + (cgen_isa_mask_compare): Ditto. + (cgen_isa_mask_intersection): Ditto. + (cgen_isa_mask_copy): Ditto. + (cgen_isa_mask_combine): Ditto. + * cgen-dis.in (libiberty.h): #include it. + (isas): Renamed from 'isa' and now (CGEN_ISA_MASK *). + (print_insn_@arch@): Use CGEN_ISA_MASK and support functions. + * Makefile.am (CGENDEPS): Add utils-cgen.scm and attrs.scm. + * Makefile.in: Regenerated. + 2005-10-27 DJ Delorie <dj@redhat.com> * m32c-asm.c: Regenerate. diff --git a/opcodes/cgen-dis.in b/opcodes/cgen-dis.in index bc2a7d3e668..5f29e2852f8 100644 --- a/opcodes/cgen-dis.in +++ b/opcodes/cgen-dis.in @@ -4,7 +4,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-dis.in isn't - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -347,7 +347,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) typedef struct cpu_desc_list { struct cpu_desc_list *next; - int isa; + CGEN_BITSET *isa; int mach; int endian; CGEN_CPU_DESC cd; @@ -359,11 +359,12 @@ print_insn_@arch@ (bfd_vma pc, disassemble_info *info) static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; static CGEN_CPU_DESC cd = 0; - static int prev_isa; + static CGEN_BITSET *prev_isa; static int prev_mach; static int prev_endian; int length; - int isa,mach; + CGEN_BITSET *isa; + int mach; int endian = (info->endian == BFD_ENDIAN_BIG ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); @@ -386,25 +387,34 @@ print_insn_@arch@ (bfd_vma pc, disassemble_info *info) #endif #ifdef CGEN_COMPUTE_ISA - isa = CGEN_COMPUTE_ISA (info); + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } #else isa = info->insn_sets; #endif /* If we've switched cpu's, try to find a handle we've used before */ if (cd - && (isa != prev_isa + && (cgen_bitset_compare (isa, prev_isa) != 0 || mach != prev_mach || endian != prev_endian)) { cd = 0; for (cl = cd_list; cl; cl = cl->next) { - if (cl->isa == isa && + if (cgen_bitset_compare (cl->isa, isa) == 0 && cl->mach == mach && cl->endian == endian) { cd = cl->cd; + prev_isa = cd->isas; break; } } @@ -420,7 +430,7 @@ print_insn_@arch@ (bfd_vma pc, disassemble_info *info) abort (); mach_name = arch_type->printable_name; - prev_isa = isa; + prev_isa = cgen_bitset_copy (isa); prev_mach = mach; prev_endian = endian; cd = @arch@_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, @@ -433,7 +443,7 @@ print_insn_@arch@ (bfd_vma pc, disassemble_info *info) /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; - cl->isa = isa; + cl->isa = prev_isa; cl->mach = mach; cl->endian = endian; cl->next = cd_list; diff --git a/opcodes/cgen-opc.c b/opcodes/cgen-opc.c index d34aac826cf..dbc51751a05 100644 --- a/opcodes/cgen-opc.c +++ b/opcodes/cgen-opc.c @@ -613,3 +613,151 @@ cgen_signed_overflow_ok_p (CGEN_CPU_DESC cd) { return cd->signed_overflow_ok_p; } +/* Functions for manipulating CGEN_BITSET. */ + +/* Create a bit mask. */ +CGEN_BITSET * +cgen_bitset_create (unsigned bit_count) +{ + CGEN_BITSET * mask = xmalloc (sizeof (* mask)); + cgen_bitset_init (mask, bit_count); + return mask; +} + +/* Initialize an existing bit mask. */ + +void +cgen_bitset_init (CGEN_BITSET * mask, unsigned bit_count) +{ + if (! mask) + return; + mask->length = (bit_count / 8) + 1; + mask->bits = xmalloc (mask->length); + cgen_bitset_clear (mask); +} + +/* Clear the bits of a bit mask. */ + +void +cgen_bitset_clear (CGEN_BITSET * mask) +{ + unsigned i; + + if (! mask) + return; + + for (i = 0; i < mask->length; ++i) + mask->bits[i] = 0; +} + +/* Add a bit to a bit mask. */ + +void +cgen_bitset_add (CGEN_BITSET * mask, unsigned bit_num) +{ + int byte_ix, bit_ix; + int bit_mask; + + if (! mask) + return; + byte_ix = bit_num / 8; + bit_ix = bit_num % 8; + bit_mask = 1 << (7 - bit_ix); + mask->bits[byte_ix] |= bit_mask; +} + +/* Set a bit mask. */ + +void +cgen_bitset_set (CGEN_BITSET * mask, unsigned bit_num) +{ + if (! mask) + return; + cgen_bitset_clear (mask); + cgen_bitset_add (mask, bit_num); +} + +/* Test for a bit in a bit mask. + Returns 1 if the bit is found */ + +int +cgen_bitset_contains (CGEN_BITSET * mask, unsigned bit_num) +{ + int byte_ix, bit_ix; + int bit_mask; + + if (! mask) + return 1; /* No bit restrictions. */ + + byte_ix = bit_num / 8; + bit_ix = 7 - (bit_num % 8); + bit_mask = 1 << bit_ix; + return (mask->bits[byte_ix] & bit_mask) >> bit_ix; +} + +/* Compare two bit masks for equality. + Returns 0 if they are equal. */ + +int +cgen_bitset_compare (CGEN_BITSET * mask1, CGEN_BITSET * mask2) +{ + if (mask1 == mask2) + return 0; + if (! mask1 || ! mask2) + return 1; + if (mask1->length != mask2->length) + return 1; + return memcmp (mask1->bits, mask2->bits, mask1->length); +} + +/* Test two bit masks for common bits. + Returns 1 if a common bit is found. */ + +int +cgen_bitset_intersect_p (CGEN_BITSET * mask1, CGEN_BITSET * mask2) +{ + unsigned i, limit; + + if (mask1 == mask2) + return 1; + if (! mask1 || ! mask2) + return 0; + limit = mask1->length < mask2->length ? mask1->length : mask2->length; + + for (i = 0; i < limit; ++i) + if ((mask1->bits[i] & mask2->bits[i])) + return 1; + + return 0; +} + +/* Make a copy of a bit mask. */ + +CGEN_BITSET * +cgen_bitset_copy (CGEN_BITSET * mask) +{ + CGEN_BITSET* newmask; + + if (! mask) + return NULL; + newmask = cgen_bitset_create ((mask->length * 8) - 1); + memcpy (newmask->bits, mask->bits, mask->length); + return newmask; +} + +/* Combine two bit masks. */ + +void +cgen_bitset_union (CGEN_BITSET * mask1, CGEN_BITSET * mask2, + CGEN_BITSET * result) +{ + unsigned i; + + if (! mask1 || ! mask2 || ! result + || mask1->length != mask2->length + || mask1->length != result->length) + return; + + for (i = 0; i < result->length; ++i) + result->bits[i] = mask1->bits[i] | mask2->bits[i]; +} diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 507606807f9..007731a7ef2 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -452,14 +452,19 @@ disassemble_init_for_target (struct disassemble_info * info) #ifdef ARCH_tic4x case bfd_arch_tic4x: info->skip_zeroes = 32; + break; #endif #ifdef ARCH_m32c case bfd_arch_m32c: info->endian = BFD_ENDIAN_BIG; - if (info->mach == bfd_mach_m16c) - info->insn_sets = 1 << ISA_M16C; - else - info->insn_sets = 1 << ISA_M32C; + if (! info->insn_sets) + { + info->insn_sets = cgen_bitset_create (ISA_MAX); + if (info->mach == bfd_mach_m16c) + cgen_bitset_set (info->insn_sets, ISA_M16C); + else + cgen_bitset_set (info->insn_sets, ISA_M32C); + } break; #endif default: diff --git a/opcodes/fr30-desc.c b/opcodes/fr30-desc.c index 768fce6ebc0..a8c2a357b6c 100644 --- a/opcodes/fr30-desc.c +++ b/opcodes/fr30-desc.c @@ -128,25 +128,25 @@ static const CGEN_MACH fr30_cgen_mach_table[] = { static CGEN_KEYWORD_ENTRY fr30_cgen_opval_gr_names_entries[] = { - { "r0", 0, {0, {0}}, 0, 0 }, - { "r1", 1, {0, {0}}, 0, 0 }, - { "r2", 2, {0, {0}}, 0, 0 }, - { "r3", 3, {0, {0}}, 0, 0 }, - { "r4", 4, {0, {0}}, 0, 0 }, - { "r5", 5, {0, {0}}, 0, 0 }, - { "r6", 6, {0, {0}}, 0, 0 }, - { "r7", 7, {0, {0}}, 0, 0 }, - { "r8", 8, {0, {0}}, 0, 0 }, - { "r9", 9, {0, {0}}, 0, 0 }, - { "r10", 10, {0, {0}}, 0, 0 }, - { "r11", 11, {0, {0}}, 0, 0 }, - { "r12", 12, {0, {0}}, 0, 0 }, - { "r13", 13, {0, {0}}, 0, 0 }, - { "r14", 14, {0, {0}}, 0, 0 }, - { "r15", 15, {0, {0}}, 0, 0 }, - { "ac", 13, {0, {0}}, 0, 0 }, - { "fp", 14, {0, {0}}, 0, 0 }, - { "sp", 15, {0, {0}}, 0, 0 } + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "ac", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "fp", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 15, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD fr30_cgen_opval_gr_names = @@ -158,22 +158,22 @@ CGEN_KEYWORD fr30_cgen_opval_gr_names = static CGEN_KEYWORD_ENTRY fr30_cgen_opval_cr_names_entries[] = { - { "cr0", 0, {0, {0}}, 0, 0 }, - { "cr1", 1, {0, {0}}, 0, 0 }, - { "cr2", 2, {0, {0}}, 0, 0 }, - { "cr3", 3, {0, {0}}, 0, 0 }, - { "cr4", 4, {0, {0}}, 0, 0 }, - { "cr5", 5, {0, {0}}, 0, 0 }, - { "cr6", 6, {0, {0}}, 0, 0 }, - { "cr7", 7, {0, {0}}, 0, 0 }, - { "cr8", 8, {0, {0}}, 0, 0 }, - { "cr9", 9, {0, {0}}, 0, 0 }, - { "cr10", 10, {0, {0}}, 0, 0 }, - { "cr11", 11, {0, {0}}, 0, 0 }, - { "cr12", 12, {0, {0}}, 0, 0 }, - { "cr13", 13, {0, {0}}, 0, 0 }, - { "cr14", 14, {0, {0}}, 0, 0 }, - { "cr15", 15, {0, {0}}, 0, 0 } + { "cr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "cr1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "cr2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "cr3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "cr4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "cr5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "cr6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "cr7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "cr8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "cr9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "cr10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "cr11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "cr12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "cr13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "cr14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "cr15", 15, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD fr30_cgen_opval_cr_names = @@ -185,12 +185,12 @@ CGEN_KEYWORD fr30_cgen_opval_cr_names = static CGEN_KEYWORD_ENTRY fr30_cgen_opval_dr_names_entries[] = { - { "tbr", 0, {0, {0}}, 0, 0 }, - { "rp", 1, {0, {0}}, 0, 0 }, - { "ssp", 2, {0, {0}}, 0, 0 }, - { "usp", 3, {0, {0}}, 0, 0 }, - { "mdh", 4, {0, {0}}, 0, 0 }, - { "mdl", 5, {0, {0}}, 0, 0 } + { "tbr", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "rp", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "ssp", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "usp", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "mdh", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "mdl", 5, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD fr30_cgen_opval_dr_names = @@ -202,7 +202,7 @@ CGEN_KEYWORD fr30_cgen_opval_dr_names = static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] = { - { "ps", 0, {0, {0}}, 0, 0 } + { "ps", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD fr30_cgen_opval_h_ps = @@ -214,7 +214,7 @@ CGEN_KEYWORD fr30_cgen_opval_h_ps = static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] = { - { "r13", 0, {0, {0}}, 0, 0 } + { "r13", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD fr30_cgen_opval_h_r13 = @@ -226,7 +226,7 @@ CGEN_KEYWORD fr30_cgen_opval_h_r13 = static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] = { - { "r14", 0, {0, {0}}, 0, 0 } + { "r14", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD fr30_cgen_opval_h_r14 = @@ -238,7 +238,7 @@ CGEN_KEYWORD fr30_cgen_opval_h_r14 = static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] = { - { "r15", 0, {0, {0}}, 0, 0 } + { "r15", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD fr30_cgen_opval_h_r15 = @@ -259,32 +259,32 @@ CGEN_KEYWORD fr30_cgen_opval_h_r15 = const CGEN_HW_ENTRY fr30_cgen_hw_table[] = { - { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } }, - { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } }, - { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } }, - { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_dr_names, { 0, { (1<<MACH_BASE) } } }, - { "h-ps", HW_H_PS, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, { (1<<MACH_BASE) } } }, - { "h-r13", HW_H_R13, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, { (1<<MACH_BASE) } } }, - { "h-r14", HW_H_R14, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, { (1<<MACH_BASE) } } }, - { "h-r15", HW_H_R15, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, { (1<<MACH_BASE) } } }, - { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-tbit", HW_H_TBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-d0bit", HW_H_D0BIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-d1bit", HW_H_D1BIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-ccr", HW_H_CCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-scr", HW_H_SCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-ilm", HW_H_ILM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} } + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_dr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-ps", HW_H_PS, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-r13", HW_H_R13, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-r14", HW_H_R14, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-r15", HW_H_R15, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-tbit", HW_H_TBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-d0bit", HW_H_D0BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-d1bit", HW_H_D1BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-ccr", HW_H_CCR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-scr", HW_H_SCR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-ilm", HW_H_ILM, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } }; #undef A @@ -300,49 +300,49 @@ const CGEN_HW_ENTRY fr30_cgen_hw_table[] = const CGEN_IFLD fr30_cgen_ifld_table[] = { - { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_I20, "f-i20", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } }, - { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, - { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, - { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } }, - { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } }, - { 0, 0, 0, 0, 0, 0, {0, {0}} } + { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_I20, "f-i20", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } }; #undef A @@ -381,203 +381,203 @@ const CGEN_OPERAND fr30_cgen_operand_table[] = /* pc: program counter */ { "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_NIL] } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* Ri: destination register */ { "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RI] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* Rj: source register */ { "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJ] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* Ric: target register coproc insn */ { "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RIC] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* Rjc: source register coproc insn */ { "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJC] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* CRi: coprocessor register */ { "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRI] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* CRj: coprocessor register */ { "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRJ] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* Rs1: dedicated register */ { "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS1] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* Rs2: dedicated register */ { "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS2] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* R13: General Register 13 */ { "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* R14: General Register 14 */ { "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* R15: General Register 15 */ { "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ps: Program Status register */ { "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* u4: 4 bit unsigned immediate */ { "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* u4c: 4 bit unsigned immediate */ { "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4C] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* u8: 8 bit unsigned immediate */ { "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U8] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* i8: 8 bit unsigned immediate */ { "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I8] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* udisp6: 6 bit unsigned immediate */ { "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_UDISP6] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* disp8: 8 bit signed immediate */ { "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP8] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* disp9: 9 bit signed immediate */ { "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP9] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* disp10: 10 bit signed immediate */ { "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP10] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* s10: 10 bit signed immediate */ { "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_S10] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* u10: 10 bit unsigned immediate */ { "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U10] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* i32: 32 bit immediate */ { "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I32] } }, - { 0|A(HASH_PREFIX)|A(SIGN_OPT), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX)|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, /* m4: 4 bit negative immediate */ { "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_M4] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* i20: 20 bit immediate */ { "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20, { 2, { (const PTR) &FR30_F_I20_MULTI_IFIELD[0] } }, - { 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, /* dir8: 8 bit direct address */ { "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR8] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* dir9: 9 bit direct address */ { "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR9] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* dir10: 10 bit direct address */ { "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR10] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* label9: 9 bit pc relative address */ { "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL9] } }, - { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, + { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, /* label12: 12 bit pc relative address */ { "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL12] } }, - { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, + { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, /* reglist_low_ld: 8 bit low register mask for ldm */ { "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_LD] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* reglist_hi_ld: 8 bit high register mask for ldm */ { "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_LD] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* reglist_low_st: 8 bit low register mask for stm */ { "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_ST] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* reglist_hi_st: 8 bit high register mask for stm */ { "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_ST] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* cc: condition codes */ { "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CC] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ccc: coprocessor calc */ { "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8, { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CCC] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* nbit: negative bit */ { "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* vbit: overflow bit */ { "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* zbit: zero bit */ { "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* cbit: carry bit */ { "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* ibit: interrupt bit */ { "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* sbit: stack bit */ { "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* tbit: trace trap bit */ { "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* d0bit: division 0 bit */ { "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* d1bit: division 1 bit */ { "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* ccr: condition code bits */ { "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* scr: system condition bits */ { "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* ilm: interrupt level mask */ { "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* sentinel */ { 0, 0, 0, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { 0 } } } + { 0, { { { (1<<MACH_BASE), 0 } } } } } }; #undef A @@ -597,831 +597,831 @@ static const CGEN_IBASE fr30_cgen_insn_table[MAX_INSNS] = /* Special null first entry. A `num' value of zero is thus invalid. Also, the special `invalid' insn resides here. */ - { 0, 0, 0, 0, {0, {0}} }, + { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* add $Rj,$Ri */ { FR30_INSN_ADD, "add", "add", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* add $u4,$Ri */ { FR30_INSN_ADDI, "addi", "add", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* add2 $m4,$Ri */ { FR30_INSN_ADD2, "add2", "add2", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* addc $Rj,$Ri */ { FR30_INSN_ADDC, "addc", "addc", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* addn $Rj,$Ri */ { FR30_INSN_ADDN, "addn", "addn", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* addn $u4,$Ri */ { FR30_INSN_ADDNI, "addni", "addn", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* addn2 $m4,$Ri */ { FR30_INSN_ADDN2, "addn2", "addn2", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* sub $Rj,$Ri */ { FR30_INSN_SUB, "sub", "sub", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* subc $Rj,$Ri */ { FR30_INSN_SUBC, "subc", "subc", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* subn $Rj,$Ri */ { FR30_INSN_SUBN, "subn", "subn", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* cmp $Rj,$Ri */ { FR30_INSN_CMP, "cmp", "cmp", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* cmp $u4,$Ri */ { FR30_INSN_CMPI, "cmpi", "cmp", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* cmp2 $m4,$Ri */ { FR30_INSN_CMP2, "cmp2", "cmp2", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* and $Rj,$Ri */ { FR30_INSN_AND, "and", "and", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* or $Rj,$Ri */ { FR30_INSN_OR, "or", "or", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* eor $Rj,$Ri */ { FR30_INSN_EOR, "eor", "eor", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* and $Rj,@$Ri */ { FR30_INSN_ANDM, "andm", "and", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* andh $Rj,@$Ri */ { FR30_INSN_ANDH, "andh", "andh", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* andb $Rj,@$Ri */ { FR30_INSN_ANDB, "andb", "andb", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* or $Rj,@$Ri */ { FR30_INSN_ORM, "orm", "or", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* orh $Rj,@$Ri */ { FR30_INSN_ORH, "orh", "orh", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* orb $Rj,@$Ri */ { FR30_INSN_ORB, "orb", "orb", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* eor $Rj,@$Ri */ { FR30_INSN_EORM, "eorm", "eor", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* eorh $Rj,@$Ri */ { FR30_INSN_EORH, "eorh", "eorh", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* eorb $Rj,@$Ri */ { FR30_INSN_EORB, "eorb", "eorb", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* bandl $u4,@$Ri */ { FR30_INSN_BANDL, "bandl", "bandl", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* borl $u4,@$Ri */ { FR30_INSN_BORL, "borl", "borl", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* beorl $u4,@$Ri */ { FR30_INSN_BEORL, "beorl", "beorl", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* bandh $u4,@$Ri */ { FR30_INSN_BANDH, "bandh", "bandh", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* borh $u4,@$Ri */ { FR30_INSN_BORH, "borh", "borh", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* beorh $u4,@$Ri */ { FR30_INSN_BEORH, "beorh", "beorh", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* btstl $u4,@$Ri */ { FR30_INSN_BTSTL, "btstl", "btstl", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* btsth $u4,@$Ri */ { FR30_INSN_BTSTH, "btsth", "btsth", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* mul $Rj,$Ri */ { FR30_INSN_MUL, "mul", "mul", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* mulu $Rj,$Ri */ { FR30_INSN_MULU, "mulu", "mulu", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* mulh $Rj,$Ri */ { FR30_INSN_MULH, "mulh", "mulh", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* muluh $Rj,$Ri */ { FR30_INSN_MULUH, "muluh", "muluh", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* div0s $Ri */ { FR30_INSN_DIV0S, "div0s", "div0s", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* div0u $Ri */ { FR30_INSN_DIV0U, "div0u", "div0u", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* div1 $Ri */ { FR30_INSN_DIV1, "div1", "div1", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* div2 $Ri */ { FR30_INSN_DIV2, "div2", "div2", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* div3 */ { FR30_INSN_DIV3, "div3", "div3", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* div4s */ { FR30_INSN_DIV4S, "div4s", "div4s", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* lsl $Rj,$Ri */ { FR30_INSN_LSL, "lsl", "lsl", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* lsl $u4,$Ri */ { FR30_INSN_LSLI, "lsli", "lsl", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* lsl2 $u4,$Ri */ { FR30_INSN_LSL2, "lsl2", "lsl2", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* lsr $Rj,$Ri */ { FR30_INSN_LSR, "lsr", "lsr", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* lsr $u4,$Ri */ { FR30_INSN_LSRI, "lsri", "lsr", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* lsr2 $u4,$Ri */ { FR30_INSN_LSR2, "lsr2", "lsr2", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* asr $Rj,$Ri */ { FR30_INSN_ASR, "asr", "asr", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* asr $u4,$Ri */ { FR30_INSN_ASRI, "asri", "asr", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* asr2 $u4,$Ri */ { FR30_INSN_ASR2, "asr2", "asr2", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ldi:8 $i8,$Ri */ { FR30_INSN_LDI8, "ldi8", "ldi:8", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ldi:20 $i20,$Ri */ { FR30_INSN_LDI20, "ldi20", "ldi:20", 32, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* ldi:32 $i32,$Ri */ { FR30_INSN_LDI32, "ldi32", "ldi:32", 48, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* ld @$Rj,$Ri */ { FR30_INSN_LD, "ld", "ld", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* lduh @$Rj,$Ri */ { FR30_INSN_LDUH, "lduh", "lduh", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ldub @$Rj,$Ri */ { FR30_INSN_LDUB, "ldub", "ldub", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ld @($R13,$Rj),$Ri */ { FR30_INSN_LDR13, "ldr13", "ld", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* lduh @($R13,$Rj),$Ri */ { FR30_INSN_LDR13UH, "ldr13uh", "lduh", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ldub @($R13,$Rj),$Ri */ { FR30_INSN_LDR13UB, "ldr13ub", "ldub", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ld @($R14,$disp10),$Ri */ { FR30_INSN_LDR14, "ldr14", "ld", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* lduh @($R14,$disp9),$Ri */ { FR30_INSN_LDR14UH, "ldr14uh", "lduh", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ldub @($R14,$disp8),$Ri */ { FR30_INSN_LDR14UB, "ldr14ub", "ldub", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ld @($R15,$udisp6),$Ri */ { FR30_INSN_LDR15, "ldr15", "ld", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ld @$R15+,$Ri */ { FR30_INSN_LDR15GR, "ldr15gr", "ld", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ld @$R15+,$Rs2 */ { FR30_INSN_LDR15DR, "ldr15dr", "ld", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ld @$R15+,$ps */ { FR30_INSN_LDR15PS, "ldr15ps", "ld", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* st $Ri,@$Rj */ { FR30_INSN_ST, "st", "st", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* sth $Ri,@$Rj */ { FR30_INSN_STH, "sth", "sth", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* stb $Ri,@$Rj */ { FR30_INSN_STB, "stb", "stb", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* st $Ri,@($R13,$Rj) */ { FR30_INSN_STR13, "str13", "st", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* sth $Ri,@($R13,$Rj) */ { FR30_INSN_STR13H, "str13h", "sth", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* stb $Ri,@($R13,$Rj) */ { FR30_INSN_STR13B, "str13b", "stb", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* st $Ri,@($R14,$disp10) */ { FR30_INSN_STR14, "str14", "st", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* sth $Ri,@($R14,$disp9) */ { FR30_INSN_STR14H, "str14h", "sth", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* stb $Ri,@($R14,$disp8) */ { FR30_INSN_STR14B, "str14b", "stb", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* st $Ri,@($R15,$udisp6) */ { FR30_INSN_STR15, "str15", "st", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* st $Ri,@-$R15 */ { FR30_INSN_STR15GR, "str15gr", "st", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* st $Rs2,@-$R15 */ { FR30_INSN_STR15DR, "str15dr", "st", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* st $ps,@-$R15 */ { FR30_INSN_STR15PS, "str15ps", "st", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov $Rj,$Ri */ { FR30_INSN_MOV, "mov", "mov", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov $Rs1,$Ri */ { FR30_INSN_MOVDR, "movdr", "mov", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov $ps,$Ri */ { FR30_INSN_MOVPS, "movps", "mov", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov $Ri,$Rs1 */ { FR30_INSN_MOV2DR, "mov2dr", "mov", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov $Ri,$ps */ { FR30_INSN_MOV2PS, "mov2ps", "mov", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* jmp @$Ri */ { FR30_INSN_JMP, "jmp", "jmp", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* jmp:d @$Ri */ { FR30_INSN_JMPD, "jmpd", "jmp:d", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* call @$Ri */ { FR30_INSN_CALLR, "callr", "call", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* call:d @$Ri */ { FR30_INSN_CALLRD, "callrd", "call:d", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* call $label12 */ { FR30_INSN_CALL, "call", "call", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* call:d $label12 */ { FR30_INSN_CALLD, "calld", "call:d", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* ret */ { FR30_INSN_RET, "ret", "ret", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* ret:d */ { FR30_INSN_RET_D, "ret:d", "ret:d", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* int $u8 */ { FR30_INSN_INT, "int", "int", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* inte */ { FR30_INSN_INTE, "inte", "inte", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* reti */ { FR30_INSN_RETI, "reti", "reti", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* bra:d $label9 */ { FR30_INSN_BRAD, "brad", "bra:d", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* bra $label9 */ { FR30_INSN_BRA, "bra", "bra", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* bno:d $label9 */ { FR30_INSN_BNOD, "bnod", "bno:d", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* bno $label9 */ { FR30_INSN_BNO, "bno", "bno", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* beq:d $label9 */ { FR30_INSN_BEQD, "beqd", "beq:d", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* beq $label9 */ { FR30_INSN_BEQ, "beq", "beq", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* bne:d $label9 */ { FR30_INSN_BNED, "bned", "bne:d", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* bne $label9 */ { FR30_INSN_BNE, "bne", "bne", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* bc:d $label9 */ { FR30_INSN_BCD, "bcd", "bc:d", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* bc $label9 */ { FR30_INSN_BC, "bc", "bc", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* bnc:d $label9 */ { FR30_INSN_BNCD, "bncd", "bnc:d", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* bnc $label9 */ { FR30_INSN_BNC, "bnc", "bnc", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* bn:d $label9 */ { FR30_INSN_BND, "bnd", "bn:d", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* bn $label9 */ { FR30_INSN_BN, "bn", "bn", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* bp:d $label9 */ { FR30_INSN_BPD, "bpd", "bp:d", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* bp $label9 */ { FR30_INSN_BP, "bp", "bp", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* bv:d $label9 */ { FR30_INSN_BVD, "bvd", "bv:d", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* bv $label9 */ { FR30_INSN_BV, "bv", "bv", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* bnv:d $label9 */ { FR30_INSN_BNVD, "bnvd", "bnv:d", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* bnv $label9 */ { FR30_INSN_BNV, "bnv", "bnv", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* blt:d $label9 */ { FR30_INSN_BLTD, "bltd", "blt:d", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* blt $label9 */ { FR30_INSN_BLT, "blt", "blt", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* bge:d $label9 */ { FR30_INSN_BGED, "bged", "bge:d", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* bge $label9 */ { FR30_INSN_BGE, "bge", "bge", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* ble:d $label9 */ { FR30_INSN_BLED, "bled", "ble:d", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* ble $label9 */ { FR30_INSN_BLE, "ble", "ble", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* bgt:d $label9 */ { FR30_INSN_BGTD, "bgtd", "bgt:d", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* bgt $label9 */ { FR30_INSN_BGT, "bgt", "bgt", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* bls:d $label9 */ { FR30_INSN_BLSD, "blsd", "bls:d", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* bls $label9 */ { FR30_INSN_BLS, "bls", "bls", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* bhi:d $label9 */ { FR30_INSN_BHID, "bhid", "bhi:d", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* bhi $label9 */ { FR30_INSN_BHI, "bhi", "bhi", 16, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* dmov $R13,@$dir10 */ { FR30_INSN_DMOVR13, "dmovr13", "dmov", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* dmovh $R13,@$dir9 */ { FR30_INSN_DMOVR13H, "dmovr13h", "dmovh", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* dmovb $R13,@$dir8 */ { FR30_INSN_DMOVR13B, "dmovr13b", "dmovb", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* dmov @$R13+,@$dir10 */ { FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* dmovh @$R13+,@$dir9 */ { FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* dmovb @$R13+,@$dir8 */ { FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* dmov @$R15+,@$dir10 */ { FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* dmov @$dir10,$R13 */ { FR30_INSN_DMOV2R13, "dmov2r13", "dmov", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* dmovh @$dir9,$R13 */ { FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* dmovb @$dir8,$R13 */ { FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* dmov @$dir10,@$R13+ */ { FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* dmovh @$dir9,@$R13+ */ { FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* dmovb @$dir8,@$R13+ */ { FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* dmov @$dir10,@-$R15 */ { FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* ldres @$Ri+,$u4 */ { FR30_INSN_LDRES, "ldres", "ldres", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* stres $u4,@$Ri+ */ { FR30_INSN_STRES, "stres", "stres", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* copop $u4c,$ccc,$CRj,$CRi */ { FR30_INSN_COPOP, "copop", "copop", 32, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* copld $u4c,$ccc,$Rjc,$CRi */ { FR30_INSN_COPLD, "copld", "copld", 32, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* copst $u4c,$ccc,$CRj,$Ric */ { FR30_INSN_COPST, "copst", "copst", 32, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* copsv $u4c,$ccc,$CRj,$Ric */ { FR30_INSN_COPSV, "copsv", "copsv", 32, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* nop */ { FR30_INSN_NOP, "nop", "nop", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* andccr $u8 */ { FR30_INSN_ANDCCR, "andccr", "andccr", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* orccr $u8 */ { FR30_INSN_ORCCR, "orccr", "orccr", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* stilm $u8 */ { FR30_INSN_STILM, "stilm", "stilm", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* addsp $s10 */ { FR30_INSN_ADDSP, "addsp", "addsp", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* extsb $Ri */ { FR30_INSN_EXTSB, "extsb", "extsb", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* extub $Ri */ { FR30_INSN_EXTUB, "extub", "extub", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* extsh $Ri */ { FR30_INSN_EXTSH, "extsh", "extsh", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* extuh $Ri */ { FR30_INSN_EXTUH, "extuh", "extuh", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ldm0 ($reglist_low_ld) */ { FR30_INSN_LDM0, "ldm0", "ldm0", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* ldm1 ($reglist_hi_ld) */ { FR30_INSN_LDM1, "ldm1", "ldm1", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* stm0 ($reglist_low_st) */ { FR30_INSN_STM0, "stm0", "stm0", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* stm1 ($reglist_hi_st) */ { FR30_INSN_STM1, "stm1", "stm1", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* enter $u10 */ { FR30_INSN_ENTER, "enter", "enter", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* leave */ { FR30_INSN_LEAVE, "leave", "leave", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* xchb @$Rj,$Ri */ { FR30_INSN_XCHB, "xchb", "xchb", 16, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, }; @@ -1544,7 +1544,7 @@ static void fr30_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) { int i; - unsigned int isas = cd->isas; + CGEN_BITSET *isas = cd->isas; unsigned int machs = cd->machs; cd->int_insn_p = CGEN_INT_INSN_P; @@ -1556,7 +1556,7 @@ fr30_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) - if (((1 << i) & isas) != 0) + if (cgen_bitset_contains (isas, i)) { const CGEN_ISA *isa = & fr30_cgen_isa_table[i]; @@ -1641,7 +1641,7 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) { CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); static int init_p; - unsigned int isas = 0; /* 0 = "unspecified" */ + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ unsigned int machs = 0; /* 0 = "unspecified" */ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; va_list ap; @@ -1660,7 +1660,7 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) switch (arg_type) { case CGEN_CPU_OPEN_ISAS : - isas = va_arg (ap, unsigned int); + isas = va_arg (ap, CGEN_BITSET *); break; case CGEN_CPU_OPEN_MACHS : machs = va_arg (ap, unsigned int); @@ -1691,9 +1691,6 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) machs = (1 << MAX_MACHS) - 1; /* Base mach is always selected. */ machs |= 1; - /* ISA unspecified means "all". */ - if (isas == 0) - isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) { /* ??? If target has only one, could have a default. */ @@ -1701,7 +1698,7 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) abort (); } - cd->isas = isas; + cd->isas = cgen_bitset_copy (isas); cd->machs = machs; cd->endian = endian; /* FIXME: for the sparc case we can determine insn-endianness statically. diff --git a/opcodes/fr30-desc.h b/opcodes/fr30-desc.h index 7741fafcb2e..509a69b88e5 100644 --- a/opcodes/fr30-desc.h +++ b/opcodes/fr30-desc.h @@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc., #ifndef FR30_CPU_H #define FR30_CPU_H +#include "opcode/cgen-bitset.h" + #define CGEN_ARCH fr30 /* Given symbol S, return fr30_cgen_<S>. */ @@ -156,6 +158,15 @@ typedef enum cgen_ifld_attr { /* Number of non-boolean elements in cgen_ifld_attr. */ #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) + /* Enum declaration for fr30 ifield types. */ typedef enum ifield_type { FR30_F_NIL, FR30_F_ANYOF, FR30_F_OP1, FR30_F_OP2 @@ -184,6 +195,13 @@ typedef enum cgen_hw_attr { /* Number of non-boolean elements in cgen_hw_attr. */ #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) + /* Enum declaration for fr30 hardware types. */ typedef enum cgen_hw_type { HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR @@ -210,6 +228,18 @@ typedef enum cgen_operand_attr { /* Number of non-boolean elements in cgen_operand_attr. */ #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0) + /* Enum declaration for fr30 operand types. */ typedef enum cgen_operand_type { FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC @@ -246,6 +276,20 @@ typedef enum cgen_insn_attr { /* Number of non-boolean elements in cgen_insn_attr. */ #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) +#define CGEN_ATTR_CGEN_INSN_NOT_IN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NOT_IN_DELAY_SLOT)) != 0) + /* cgen.h uses things we just defined. */ #include "opcode/cgen.h" diff --git a/opcodes/fr30-dis.c b/opcodes/fr30-dis.c index 0f7c8e895f5..740e4f4bfcd 100644 --- a/opcodes/fr30-dis.c +++ b/opcodes/fr30-dis.c @@ -4,7 +4,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-dis.in isn't - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -607,7 +607,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) typedef struct cpu_desc_list { struct cpu_desc_list *next; - int isa; + CGEN_BITSET *isa; int mach; int endian; CGEN_CPU_DESC cd; @@ -619,11 +619,12 @@ print_insn_fr30 (bfd_vma pc, disassemble_info *info) static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; static CGEN_CPU_DESC cd = 0; - static int prev_isa; + static CGEN_BITSET *prev_isa; static int prev_mach; static int prev_endian; int length; - int isa,mach; + CGEN_BITSET *isa; + int mach; int endian = (info->endian == BFD_ENDIAN_BIG ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); @@ -646,25 +647,34 @@ print_insn_fr30 (bfd_vma pc, disassemble_info *info) #endif #ifdef CGEN_COMPUTE_ISA - isa = CGEN_COMPUTE_ISA (info); + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } #else isa = info->insn_sets; #endif /* If we've switched cpu's, try to find a handle we've used before */ if (cd - && (isa != prev_isa + && (cgen_bitset_compare (isa, prev_isa) != 0 || mach != prev_mach || endian != prev_endian)) { cd = 0; for (cl = cd_list; cl; cl = cl->next) { - if (cl->isa == isa && + if (cgen_bitset_compare (cl->isa, isa) == 0 && cl->mach == mach && cl->endian == endian) { cd = cl->cd; + prev_isa = cd->isas; break; } } @@ -680,7 +690,7 @@ print_insn_fr30 (bfd_vma pc, disassemble_info *info) abort (); mach_name = arch_type->printable_name; - prev_isa = isa; + prev_isa = cgen_bitset_copy (isa); prev_mach = mach; prev_endian = endian; cd = fr30_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, @@ -693,7 +703,7 @@ print_insn_fr30 (bfd_vma pc, disassemble_info *info) /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; - cl->isa = isa; + cl->isa = prev_isa; cl->mach = mach; cl->endian = endian; cl->next = cd_list; diff --git a/opcodes/fr30-opc.c b/opcodes/fr30-opc.c index 0eefb4693a7..be92c6d77bf 100644 --- a/opcodes/fr30-opc.c +++ b/opcodes/fr30-opc.c @@ -1228,17 +1228,17 @@ static const CGEN_IBASE fr30_cgen_macro_insn_table[] = /* ldi8 $i8,$Ri */ { -1, "ldi8m", "ldi8", 16, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } } + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } }, /* ldi20 $i20,$Ri */ { -1, "ldi20m", "ldi20", 32, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } } + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } }, /* ldi32 $i32,$Ri */ { -1, "ldi32m", "ldi32", 48, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } } + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } }, }; diff --git a/opcodes/frv-desc.c b/opcodes/frv-desc.c index bff97d83ed1..39235a6a164 100644 --- a/opcodes/frv-desc.c +++ b/opcodes/frv-desc.c @@ -296,72 +296,72 @@ static const CGEN_MACH frv_cgen_mach_table[] = { static CGEN_KEYWORD_ENTRY frv_cgen_opval_gr_names_entries[] = { - { "sp", 1, {0, {0}}, 0, 0 }, - { "fp", 2, {0, {0}}, 0, 0 }, - { "gr0", 0, {0, {0}}, 0, 0 }, - { "gr1", 1, {0, {0}}, 0, 0 }, - { "gr2", 2, {0, {0}}, 0, 0 }, - { "gr3", 3, {0, {0}}, 0, 0 }, - { "gr4", 4, {0, {0}}, 0, 0 }, - { "gr5", 5, {0, {0}}, 0, 0 }, - { "gr6", 6, {0, {0}}, 0, 0 }, - { "gr7", 7, {0, {0}}, 0, 0 }, - { "gr8", 8, {0, {0}}, 0, 0 }, - { "gr9", 9, {0, {0}}, 0, 0 }, - { "gr10", 10, {0, {0}}, 0, 0 }, - { "gr11", 11, {0, {0}}, 0, 0 }, - { "gr12", 12, {0, {0}}, 0, 0 }, - { "gr13", 13, {0, {0}}, 0, 0 }, - { "gr14", 14, {0, {0}}, 0, 0 }, - { "gr15", 15, {0, {0}}, 0, 0 }, - { "gr16", 16, {0, {0}}, 0, 0 }, - { "gr17", 17, {0, {0}}, 0, 0 }, - { "gr18", 18, {0, {0}}, 0, 0 }, - { "gr19", 19, {0, {0}}, 0, 0 }, - { "gr20", 20, {0, {0}}, 0, 0 }, - { "gr21", 21, {0, {0}}, 0, 0 }, - { "gr22", 22, {0, {0}}, 0, 0 }, - { "gr23", 23, {0, {0}}, 0, 0 }, - { "gr24", 24, {0, {0}}, 0, 0 }, - { "gr25", 25, {0, {0}}, 0, 0 }, - { "gr26", 26, {0, {0}}, 0, 0 }, - { "gr27", 27, {0, {0}}, 0, 0 }, - { "gr28", 28, {0, {0}}, 0, 0 }, - { "gr29", 29, {0, {0}}, 0, 0 }, - { "gr30", 30, {0, {0}}, 0, 0 }, - { "gr31", 31, {0, {0}}, 0, 0 }, - { "gr32", 32, {0, {0}}, 0, 0 }, - { "gr33", 33, {0, {0}}, 0, 0 }, - { "gr34", 34, {0, {0}}, 0, 0 }, - { "gr35", 35, {0, {0}}, 0, 0 }, - { "gr36", 36, {0, {0}}, 0, 0 }, - { "gr37", 37, {0, {0}}, 0, 0 }, - { "gr38", 38, {0, {0}}, 0, 0 }, - { "gr39", 39, {0, {0}}, 0, 0 }, - { "gr40", 40, {0, {0}}, 0, 0 }, - { "gr41", 41, {0, {0}}, 0, 0 }, - { "gr42", 42, {0, {0}}, 0, 0 }, - { "gr43", 43, {0, {0}}, 0, 0 }, - { "gr44", 44, {0, {0}}, 0, 0 }, - { "gr45", 45, {0, {0}}, 0, 0 }, - { "gr46", 46, {0, {0}}, 0, 0 }, - { "gr47", 47, {0, {0}}, 0, 0 }, - { "gr48", 48, {0, {0}}, 0, 0 }, - { "gr49", 49, {0, {0}}, 0, 0 }, - { "gr50", 50, {0, {0}}, 0, 0 }, - { "gr51", 51, {0, {0}}, 0, 0 }, - { "gr52", 52, {0, {0}}, 0, 0 }, - { "gr53", 53, {0, {0}}, 0, 0 }, - { "gr54", 54, {0, {0}}, 0, 0 }, - { "gr55", 55, {0, {0}}, 0, 0 }, - { "gr56", 56, {0, {0}}, 0, 0 }, - { "gr57", 57, {0, {0}}, 0, 0 }, - { "gr58", 58, {0, {0}}, 0, 0 }, - { "gr59", 59, {0, {0}}, 0, 0 }, - { "gr60", 60, {0, {0}}, 0, 0 }, - { "gr61", 61, {0, {0}}, 0, 0 }, - { "gr62", 62, {0, {0}}, 0, 0 }, - { "gr63", 63, {0, {0}}, 0, 0 } + { "sp", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "fp", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "gr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "gr1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "gr2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "gr3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "gr4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "gr5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "gr6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "gr7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "gr8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "gr9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "gr10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "gr11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "gr12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "gr13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "gr14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "gr15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "gr16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "gr17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "gr18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "gr19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "gr20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "gr21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "gr22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "gr23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "gr24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "gr25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "gr26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "gr27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "gr28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "gr29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "gr30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "gr31", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "gr32", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "gr33", 33, {0, {{{0, 0}}}}, 0, 0 }, + { "gr34", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "gr35", 35, {0, {{{0, 0}}}}, 0, 0 }, + { "gr36", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "gr37", 37, {0, {{{0, 0}}}}, 0, 0 }, + { "gr38", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "gr39", 39, {0, {{{0, 0}}}}, 0, 0 }, + { "gr40", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "gr41", 41, {0, {{{0, 0}}}}, 0, 0 }, + { "gr42", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "gr43", 43, {0, {{{0, 0}}}}, 0, 0 }, + { "gr44", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "gr45", 45, {0, {{{0, 0}}}}, 0, 0 }, + { "gr46", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "gr47", 47, {0, {{{0, 0}}}}, 0, 0 }, + { "gr48", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "gr49", 49, {0, {{{0, 0}}}}, 0, 0 }, + { "gr50", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "gr51", 51, {0, {{{0, 0}}}}, 0, 0 }, + { "gr52", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "gr53", 53, {0, {{{0, 0}}}}, 0, 0 }, + { "gr54", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "gr55", 55, {0, {{{0, 0}}}}, 0, 0 }, + { "gr56", 56, {0, {{{0, 0}}}}, 0, 0 }, + { "gr57", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "gr58", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "gr59", 59, {0, {{{0, 0}}}}, 0, 0 }, + { "gr60", 60, {0, {{{0, 0}}}}, 0, 0 }, + { "gr61", 61, {0, {{{0, 0}}}}, 0, 0 }, + { "gr62", 62, {0, {{{0, 0}}}}, 0, 0 }, + { "gr63", 63, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD frv_cgen_opval_gr_names = @@ -373,70 +373,70 @@ CGEN_KEYWORD frv_cgen_opval_gr_names = static CGEN_KEYWORD_ENTRY frv_cgen_opval_fr_names_entries[] = { - { "fr0", 0, {0, {0}}, 0, 0 }, - { "fr1", 1, {0, {0}}, 0, 0 }, - { "fr2", 2, {0, {0}}, 0, 0 }, - { "fr3", 3, {0, {0}}, 0, 0 }, - { "fr4", 4, {0, {0}}, 0, 0 }, - { "fr5", 5, {0, {0}}, 0, 0 }, - { "fr6", 6, {0, {0}}, 0, 0 }, - { "fr7", 7, {0, {0}}, 0, 0 }, - { "fr8", 8, {0, {0}}, 0, 0 }, - { "fr9", 9, {0, {0}}, 0, 0 }, - { "fr10", 10, {0, {0}}, 0, 0 }, - { "fr11", 11, {0, {0}}, 0, 0 }, - { "fr12", 12, {0, {0}}, 0, 0 }, - { "fr13", 13, {0, {0}}, 0, 0 }, - { "fr14", 14, {0, {0}}, 0, 0 }, - { "fr15", 15, {0, {0}}, 0, 0 }, - { "fr16", 16, {0, {0}}, 0, 0 }, - { "fr17", 17, {0, {0}}, 0, 0 }, - { "fr18", 18, {0, {0}}, 0, 0 }, - { "fr19", 19, {0, {0}}, 0, 0 }, - { "fr20", 20, {0, {0}}, 0, 0 }, - { "fr21", 21, {0, {0}}, 0, 0 }, - { "fr22", 22, {0, {0}}, 0, 0 }, - { "fr23", 23, {0, {0}}, 0, 0 }, - { "fr24", 24, {0, {0}}, 0, 0 }, - { "fr25", 25, {0, {0}}, 0, 0 }, - { "fr26", 26, {0, {0}}, 0, 0 }, - { "fr27", 27, {0, {0}}, 0, 0 }, - { "fr28", 28, {0, {0}}, 0, 0 }, - { "fr29", 29, {0, {0}}, 0, 0 }, - { "fr30", 30, {0, {0}}, 0, 0 }, - { "fr31", 31, {0, {0}}, 0, 0 }, - { "fr32", 32, {0, {0}}, 0, 0 }, - { "fr33", 33, {0, {0}}, 0, 0 }, - { "fr34", 34, {0, {0}}, 0, 0 }, - { "fr35", 35, {0, {0}}, 0, 0 }, - { "fr36", 36, {0, {0}}, 0, 0 }, - { "fr37", 37, {0, {0}}, 0, 0 }, - { "fr38", 38, {0, {0}}, 0, 0 }, - { "fr39", 39, {0, {0}}, 0, 0 }, - { "fr40", 40, {0, {0}}, 0, 0 }, - { "fr41", 41, {0, {0}}, 0, 0 }, - { "fr42", 42, {0, {0}}, 0, 0 }, - { "fr43", 43, {0, {0}}, 0, 0 }, - { "fr44", 44, {0, {0}}, 0, 0 }, - { "fr45", 45, {0, {0}}, 0, 0 }, - { "fr46", 46, {0, {0}}, 0, 0 }, - { "fr47", 47, {0, {0}}, 0, 0 }, - { "fr48", 48, {0, {0}}, 0, 0 }, - { "fr49", 49, {0, {0}}, 0, 0 }, - { "fr50", 50, {0, {0}}, 0, 0 }, - { "fr51", 51, {0, {0}}, 0, 0 }, - { "fr52", 52, {0, {0}}, 0, 0 }, - { "fr53", 53, {0, {0}}, 0, 0 }, - { "fr54", 54, {0, {0}}, 0, 0 }, - { "fr55", 55, {0, {0}}, 0, 0 }, - { "fr56", 56, {0, {0}}, 0, 0 }, - { "fr57", 57, {0, {0}}, 0, 0 }, - { "fr58", 58, {0, {0}}, 0, 0 }, - { "fr59", 59, {0, {0}}, 0, 0 }, - { "fr60", 60, {0, {0}}, 0, 0 }, - { "fr61", 61, {0, {0}}, 0, 0 }, - { "fr62", 62, {0, {0}}, 0, 0 }, - { "fr63", 63, {0, {0}}, 0, 0 } + { "fr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "fr1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "fr2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "fr3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "fr4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "fr5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "fr6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "fr7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "fr8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "fr9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "fr10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "fr11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "fr12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "fr13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "fr14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "fr15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "fr16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "fr17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "fr18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "fr19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "fr20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "fr21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "fr22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "fr23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "fr24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "fr25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "fr26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "fr27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "fr28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "fr29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "fr30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "fr31", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "fr32", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "fr33", 33, {0, {{{0, 0}}}}, 0, 0 }, + { "fr34", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "fr35", 35, {0, {{{0, 0}}}}, 0, 0 }, + { "fr36", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "fr37", 37, {0, {{{0, 0}}}}, 0, 0 }, + { "fr38", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "fr39", 39, {0, {{{0, 0}}}}, 0, 0 }, + { "fr40", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "fr41", 41, {0, {{{0, 0}}}}, 0, 0 }, + { "fr42", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "fr43", 43, {0, {{{0, 0}}}}, 0, 0 }, + { "fr44", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "fr45", 45, {0, {{{0, 0}}}}, 0, 0 }, + { "fr46", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "fr47", 47, {0, {{{0, 0}}}}, 0, 0 }, + { "fr48", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "fr49", 49, {0, {{{0, 0}}}}, 0, 0 }, + { "fr50", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "fr51", 51, {0, {{{0, 0}}}}, 0, 0 }, + { "fr52", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "fr53", 53, {0, {{{0, 0}}}}, 0, 0 }, + { "fr54", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "fr55", 55, {0, {{{0, 0}}}}, 0, 0 }, + { "fr56", 56, {0, {{{0, 0}}}}, 0, 0 }, + { "fr57", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "fr58", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "fr59", 59, {0, {{{0, 0}}}}, 0, 0 }, + { "fr60", 60, {0, {{{0, 0}}}}, 0, 0 }, + { "fr61", 61, {0, {{{0, 0}}}}, 0, 0 }, + { "fr62", 62, {0, {{{0, 0}}}}, 0, 0 }, + { "fr63", 63, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD frv_cgen_opval_fr_names = @@ -448,70 +448,70 @@ CGEN_KEYWORD frv_cgen_opval_fr_names = static CGEN_KEYWORD_ENTRY frv_cgen_opval_cpr_names_entries[] = { - { "cpr0", 0, {0, {0}}, 0, 0 }, - { "cpr1", 1, {0, {0}}, 0, 0 }, - { "cpr2", 2, {0, {0}}, 0, 0 }, - { "cpr3", 3, {0, {0}}, 0, 0 }, - { "cpr4", 4, {0, {0}}, 0, 0 }, - { "cpr5", 5, {0, {0}}, 0, 0 }, - { "cpr6", 6, {0, {0}}, 0, 0 }, - { "cpr7", 7, {0, {0}}, 0, 0 }, - { "cpr8", 8, {0, {0}}, 0, 0 }, - { "cpr9", 9, {0, {0}}, 0, 0 }, - { "cpr10", 10, {0, {0}}, 0, 0 }, - { "cpr11", 11, {0, {0}}, 0, 0 }, - { "cpr12", 12, {0, {0}}, 0, 0 }, - { "cpr13", 13, {0, {0}}, 0, 0 }, - { "cpr14", 14, {0, {0}}, 0, 0 }, - { "cpr15", 15, {0, {0}}, 0, 0 }, - { "cpr16", 16, {0, {0}}, 0, 0 }, - { "cpr17", 17, {0, {0}}, 0, 0 }, - { "cpr18", 18, {0, {0}}, 0, 0 }, - { "cpr19", 19, {0, {0}}, 0, 0 }, - { "cpr20", 20, {0, {0}}, 0, 0 }, - { "cpr21", 21, {0, {0}}, 0, 0 }, - { "cpr22", 22, {0, {0}}, 0, 0 }, - { "cpr23", 23, {0, {0}}, 0, 0 }, - { "cpr24", 24, {0, {0}}, 0, 0 }, - { "cpr25", 25, {0, {0}}, 0, 0 }, - { "cpr26", 26, {0, {0}}, 0, 0 }, - { "cpr27", 27, {0, {0}}, 0, 0 }, - { "cpr28", 28, {0, {0}}, 0, 0 }, - { "cpr29", 29, {0, {0}}, 0, 0 }, - { "cpr30", 30, {0, {0}}, 0, 0 }, - { "cpr31", 31, {0, {0}}, 0, 0 }, - { "cpr32", 32, {0, {0}}, 0, 0 }, - { "cpr33", 33, {0, {0}}, 0, 0 }, - { "cpr34", 34, {0, {0}}, 0, 0 }, - { "cpr35", 35, {0, {0}}, 0, 0 }, - { "cpr36", 36, {0, {0}}, 0, 0 }, - { "cpr37", 37, {0, {0}}, 0, 0 }, - { "cpr38", 38, {0, {0}}, 0, 0 }, - { "cpr39", 39, {0, {0}}, 0, 0 }, - { "cpr40", 40, {0, {0}}, 0, 0 }, - { "cpr41", 41, {0, {0}}, 0, 0 }, - { "cpr42", 42, {0, {0}}, 0, 0 }, - { "cpr43", 43, {0, {0}}, 0, 0 }, - { "cpr44", 44, {0, {0}}, 0, 0 }, - { "cpr45", 45, {0, {0}}, 0, 0 }, - { "cpr46", 46, {0, {0}}, 0, 0 }, - { "cpr47", 47, {0, {0}}, 0, 0 }, - { "cpr48", 48, {0, {0}}, 0, 0 }, - { "cpr49", 49, {0, {0}}, 0, 0 }, - { "cpr50", 50, {0, {0}}, 0, 0 }, - { "cpr51", 51, {0, {0}}, 0, 0 }, - { "cpr52", 52, {0, {0}}, 0, 0 }, - { "cpr53", 53, {0, {0}}, 0, 0 }, - { "cpr54", 54, {0, {0}}, 0, 0 }, - { "cpr55", 55, {0, {0}}, 0, 0 }, - { "cpr56", 56, {0, {0}}, 0, 0 }, - { "cpr57", 57, {0, {0}}, 0, 0 }, - { "cpr58", 58, {0, {0}}, 0, 0 }, - { "cpr59", 59, {0, {0}}, 0, 0 }, - { "cpr60", 60, {0, {0}}, 0, 0 }, - { "cpr61", 61, {0, {0}}, 0, 0 }, - { "cpr62", 62, {0, {0}}, 0, 0 }, - { "cpr63", 63, {0, {0}}, 0, 0 } + { "cpr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr31", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr32", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr33", 33, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr34", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr35", 35, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr36", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr37", 37, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr38", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr39", 39, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr40", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr41", 41, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr42", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr43", 43, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr44", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr45", 45, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr46", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr47", 47, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr48", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr49", 49, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr50", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr51", 51, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr52", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr53", 53, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr54", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr55", 55, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr56", 56, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr57", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr58", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr59", 59, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr60", 60, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr61", 61, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr62", 62, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr63", 63, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD frv_cgen_opval_cpr_names = @@ -523,1028 +523,1028 @@ CGEN_KEYWORD frv_cgen_opval_cpr_names = static CGEN_KEYWORD_ENTRY frv_cgen_opval_spr_names_entries[] = { - { "psr", 0, {0, {0}}, 0, 0 }, - { "pcsr", 1, {0, {0}}, 0, 0 }, - { "bpcsr", 2, {0, {0}}, 0, 0 }, - { "tbr", 3, {0, {0}}, 0, 0 }, - { "bpsr", 4, {0, {0}}, 0, 0 }, - { "hsr0", 16, {0, {0}}, 0, 0 }, - { "hsr1", 17, {0, {0}}, 0, 0 }, - { "hsr2", 18, {0, {0}}, 0, 0 }, - { "hsr3", 19, {0, {0}}, 0, 0 }, - { "hsr4", 20, {0, {0}}, 0, 0 }, - { "hsr5", 21, {0, {0}}, 0, 0 }, - { "hsr6", 22, {0, {0}}, 0, 0 }, - { "hsr7", 23, {0, {0}}, 0, 0 }, - { "hsr8", 24, {0, {0}}, 0, 0 }, - { "hsr9", 25, {0, {0}}, 0, 0 }, - { "hsr10", 26, {0, {0}}, 0, 0 }, - { "hsr11", 27, {0, {0}}, 0, 0 }, - { "hsr12", 28, {0, {0}}, 0, 0 }, - { "hsr13", 29, {0, {0}}, 0, 0 }, - { "hsr14", 30, {0, {0}}, 0, 0 }, - { "hsr15", 31, {0, {0}}, 0, 0 }, - { "hsr16", 32, {0, {0}}, 0, 0 }, - { "hsr17", 33, {0, {0}}, 0, 0 }, - { "hsr18", 34, {0, {0}}, 0, 0 }, - { "hsr19", 35, {0, {0}}, 0, 0 }, - { "hsr20", 36, {0, {0}}, 0, 0 }, - { "hsr21", 37, {0, {0}}, 0, 0 }, - { "hsr22", 38, {0, {0}}, 0, 0 }, - { "hsr23", 39, {0, {0}}, 0, 0 }, - { "hsr24", 40, {0, {0}}, 0, 0 }, - { "hsr25", 41, {0, {0}}, 0, 0 }, - { "hsr26", 42, {0, {0}}, 0, 0 }, - { "hsr27", 43, {0, {0}}, 0, 0 }, - { "hsr28", 44, {0, {0}}, 0, 0 }, - { "hsr29", 45, {0, {0}}, 0, 0 }, - { "hsr30", 46, {0, {0}}, 0, 0 }, - { "hsr31", 47, {0, {0}}, 0, 0 }, - { "hsr32", 48, {0, {0}}, 0, 0 }, - { "hsr33", 49, {0, {0}}, 0, 0 }, - { "hsr34", 50, {0, {0}}, 0, 0 }, - { "hsr35", 51, {0, {0}}, 0, 0 }, - { "hsr36", 52, {0, {0}}, 0, 0 }, - { "hsr37", 53, {0, {0}}, 0, 0 }, - { "hsr38", 54, {0, {0}}, 0, 0 }, - { "hsr39", 55, {0, {0}}, 0, 0 }, - { "hsr40", 56, {0, {0}}, 0, 0 }, - { "hsr41", 57, {0, {0}}, 0, 0 }, - { "hsr42", 58, {0, {0}}, 0, 0 }, - { "hsr43", 59, {0, {0}}, 0, 0 }, - { "hsr44", 60, {0, {0}}, 0, 0 }, - { "hsr45", 61, {0, {0}}, 0, 0 }, - { "hsr46", 62, {0, {0}}, 0, 0 }, - { "hsr47", 63, {0, {0}}, 0, 0 }, - { "hsr48", 64, {0, {0}}, 0, 0 }, - { "hsr49", 65, {0, {0}}, 0, 0 }, - { "hsr50", 66, {0, {0}}, 0, 0 }, - { "hsr51", 67, {0, {0}}, 0, 0 }, - { "hsr52", 68, {0, {0}}, 0, 0 }, - { "hsr53", 69, {0, {0}}, 0, 0 }, - { "hsr54", 70, {0, {0}}, 0, 0 }, - { "hsr55", 71, {0, {0}}, 0, 0 }, - { "hsr56", 72, {0, {0}}, 0, 0 }, - { "hsr57", 73, {0, {0}}, 0, 0 }, - { "hsr58", 74, {0, {0}}, 0, 0 }, - { "hsr59", 75, {0, {0}}, 0, 0 }, - { "hsr60", 76, {0, {0}}, 0, 0 }, - { "hsr61", 77, {0, {0}}, 0, 0 }, - { "hsr62", 78, {0, {0}}, 0, 0 }, - { "hsr63", 79, {0, {0}}, 0, 0 }, - { "ccr", 256, {0, {0}}, 0, 0 }, - { "cccr", 263, {0, {0}}, 0, 0 }, - { "lr", 272, {0, {0}}, 0, 0 }, - { "lcr", 273, {0, {0}}, 0, 0 }, - { "iacc0h", 280, {0, {0}}, 0, 0 }, - { "iacc0l", 281, {0, {0}}, 0, 0 }, - { "isr", 288, {0, {0}}, 0, 0 }, - { "neear0", 352, {0, {0}}, 0, 0 }, - { "neear1", 353, {0, {0}}, 0, 0 }, - { "neear2", 354, {0, {0}}, 0, 0 }, - { "neear3", 355, {0, {0}}, 0, 0 }, - { "neear4", 356, {0, {0}}, 0, 0 }, - { "neear5", 357, {0, {0}}, 0, 0 }, - { "neear6", 358, {0, {0}}, 0, 0 }, - { "neear7", 359, {0, {0}}, 0, 0 }, - { "neear8", 360, {0, {0}}, 0, 0 }, - { "neear9", 361, {0, {0}}, 0, 0 }, - { "neear10", 362, {0, {0}}, 0, 0 }, - { "neear11", 363, {0, {0}}, 0, 0 }, - { "neear12", 364, {0, {0}}, 0, 0 }, - { "neear13", 365, {0, {0}}, 0, 0 }, - { "neear14", 366, {0, {0}}, 0, 0 }, - { "neear15", 367, {0, {0}}, 0, 0 }, - { "neear16", 368, {0, {0}}, 0, 0 }, - { "neear17", 369, {0, {0}}, 0, 0 }, - { "neear18", 370, {0, {0}}, 0, 0 }, - { "neear19", 371, {0, {0}}, 0, 0 }, - { "neear20", 372, {0, {0}}, 0, 0 }, - { "neear21", 373, {0, {0}}, 0, 0 }, - { "neear22", 374, {0, {0}}, 0, 0 }, - { "neear23", 375, {0, {0}}, 0, 0 }, - { "neear24", 376, {0, {0}}, 0, 0 }, - { "neear25", 377, {0, {0}}, 0, 0 }, - { "neear26", 378, {0, {0}}, 0, 0 }, - { "neear27", 379, {0, {0}}, 0, 0 }, - { "neear28", 380, {0, {0}}, 0, 0 }, - { "neear29", 381, {0, {0}}, 0, 0 }, - { "neear30", 382, {0, {0}}, 0, 0 }, - { "neear31", 383, {0, {0}}, 0, 0 }, - { "nesr0", 384, {0, {0}}, 0, 0 }, - { "nesr1", 385, {0, {0}}, 0, 0 }, - { "nesr2", 386, {0, {0}}, 0, 0 }, - { "nesr3", 387, {0, {0}}, 0, 0 }, - { "nesr4", 388, {0, {0}}, 0, 0 }, - { "nesr5", 389, {0, {0}}, 0, 0 }, - { "nesr6", 390, {0, {0}}, 0, 0 }, - { "nesr7", 391, {0, {0}}, 0, 0 }, - { "nesr8", 392, {0, {0}}, 0, 0 }, - { "nesr9", 393, {0, {0}}, 0, 0 }, - { "nesr10", 394, {0, {0}}, 0, 0 }, - { "nesr11", 395, {0, {0}}, 0, 0 }, - { "nesr12", 396, {0, {0}}, 0, 0 }, - { "nesr13", 397, {0, {0}}, 0, 0 }, - { "nesr14", 398, {0, {0}}, 0, 0 }, - { "nesr15", 399, {0, {0}}, 0, 0 }, - { "nesr16", 400, {0, {0}}, 0, 0 }, - { "nesr17", 401, {0, {0}}, 0, 0 }, - { "nesr18", 402, {0, {0}}, 0, 0 }, - { "nesr19", 403, {0, {0}}, 0, 0 }, - { "nesr20", 404, {0, {0}}, 0, 0 }, - { "nesr21", 405, {0, {0}}, 0, 0 }, - { "nesr22", 406, {0, {0}}, 0, 0 }, - { "nesr23", 407, {0, {0}}, 0, 0 }, - { "nesr24", 408, {0, {0}}, 0, 0 }, - { "nesr25", 409, {0, {0}}, 0, 0 }, - { "nesr26", 410, {0, {0}}, 0, 0 }, - { "nesr27", 411, {0, {0}}, 0, 0 }, - { "nesr28", 412, {0, {0}}, 0, 0 }, - { "nesr29", 413, {0, {0}}, 0, 0 }, - { "nesr30", 414, {0, {0}}, 0, 0 }, - { "nesr31", 415, {0, {0}}, 0, 0 }, - { "necr", 416, {0, {0}}, 0, 0 }, - { "gner0", 432, {0, {0}}, 0, 0 }, - { "gner1", 433, {0, {0}}, 0, 0 }, - { "fner0", 434, {0, {0}}, 0, 0 }, - { "fner1", 435, {0, {0}}, 0, 0 }, - { "epcr0", 512, {0, {0}}, 0, 0 }, - { "epcr1", 513, {0, {0}}, 0, 0 }, - { "epcr2", 514, {0, {0}}, 0, 0 }, - { "epcr3", 515, {0, {0}}, 0, 0 }, - { "epcr4", 516, {0, {0}}, 0, 0 }, - { "epcr5", 517, {0, {0}}, 0, 0 }, - { "epcr6", 518, {0, {0}}, 0, 0 }, - { "epcr7", 519, {0, {0}}, 0, 0 }, - { "epcr8", 520, {0, {0}}, 0, 0 }, - { "epcr9", 521, {0, {0}}, 0, 0 }, - { "epcr10", 522, {0, {0}}, 0, 0 }, - { "epcr11", 523, {0, {0}}, 0, 0 }, - { "epcr12", 524, {0, {0}}, 0, 0 }, - { "epcr13", 525, {0, {0}}, 0, 0 }, - { "epcr14", 526, {0, {0}}, 0, 0 }, - { "epcr15", 527, {0, {0}}, 0, 0 }, - { "epcr16", 528, {0, {0}}, 0, 0 }, - { "epcr17", 529, {0, {0}}, 0, 0 }, - { "epcr18", 530, {0, {0}}, 0, 0 }, - { "epcr19", 531, {0, {0}}, 0, 0 }, - { "epcr20", 532, {0, {0}}, 0, 0 }, - { "epcr21", 533, {0, {0}}, 0, 0 }, - { "epcr22", 534, {0, {0}}, 0, 0 }, - { "epcr23", 535, {0, {0}}, 0, 0 }, - { "epcr24", 536, {0, {0}}, 0, 0 }, - { "epcr25", 537, {0, {0}}, 0, 0 }, - { "epcr26", 538, {0, {0}}, 0, 0 }, - { "epcr27", 539, {0, {0}}, 0, 0 }, - { "epcr28", 540, {0, {0}}, 0, 0 }, - { "epcr29", 541, {0, {0}}, 0, 0 }, - { "epcr30", 542, {0, {0}}, 0, 0 }, - { "epcr31", 543, {0, {0}}, 0, 0 }, - { "epcr32", 544, {0, {0}}, 0, 0 }, - { "epcr33", 545, {0, {0}}, 0, 0 }, - { "epcr34", 546, {0, {0}}, 0, 0 }, - { "epcr35", 547, {0, {0}}, 0, 0 }, - { "epcr36", 548, {0, {0}}, 0, 0 }, - { "epcr37", 549, {0, {0}}, 0, 0 }, - { "epcr38", 550, {0, {0}}, 0, 0 }, - { "epcr39", 551, {0, {0}}, 0, 0 }, - { "epcr40", 552, {0, {0}}, 0, 0 }, - { "epcr41", 553, {0, {0}}, 0, 0 }, - { "epcr42", 554, {0, {0}}, 0, 0 }, - { "epcr43", 555, {0, {0}}, 0, 0 }, - { "epcr44", 556, {0, {0}}, 0, 0 }, - { "epcr45", 557, {0, {0}}, 0, 0 }, - { "epcr46", 558, {0, {0}}, 0, 0 }, - { "epcr47", 559, {0, {0}}, 0, 0 }, - { "epcr48", 560, {0, {0}}, 0, 0 }, - { "epcr49", 561, {0, {0}}, 0, 0 }, - { "epcr50", 562, {0, {0}}, 0, 0 }, - { "epcr51", 563, {0, {0}}, 0, 0 }, - { "epcr52", 564, {0, {0}}, 0, 0 }, - { "epcr53", 565, {0, {0}}, 0, 0 }, - { "epcr54", 566, {0, {0}}, 0, 0 }, - { "epcr55", 567, {0, {0}}, 0, 0 }, - { "epcr56", 568, {0, {0}}, 0, 0 }, - { "epcr57", 569, {0, {0}}, 0, 0 }, - { "epcr58", 570, {0, {0}}, 0, 0 }, - { "epcr59", 571, {0, {0}}, 0, 0 }, - { "epcr60", 572, {0, {0}}, 0, 0 }, - { "epcr61", 573, {0, {0}}, 0, 0 }, - { "epcr62", 574, {0, {0}}, 0, 0 }, - { "epcr63", 575, {0, {0}}, 0, 0 }, - { "esr0", 576, {0, {0}}, 0, 0 }, - { "esr1", 577, {0, {0}}, 0, 0 }, - { "esr2", 578, {0, {0}}, 0, 0 }, - { "esr3", 579, {0, {0}}, 0, 0 }, - { "esr4", 580, {0, {0}}, 0, 0 }, - { "esr5", 581, {0, {0}}, 0, 0 }, - { "esr6", 582, {0, {0}}, 0, 0 }, - { "esr7", 583, {0, {0}}, 0, 0 }, - { "esr8", 584, {0, {0}}, 0, 0 }, - { "esr9", 585, {0, {0}}, 0, 0 }, - { "esr10", 586, {0, {0}}, 0, 0 }, - { "esr11", 587, {0, {0}}, 0, 0 }, - { "esr12", 588, {0, {0}}, 0, 0 }, - { "esr13", 589, {0, {0}}, 0, 0 }, - { "esr14", 590, {0, {0}}, 0, 0 }, - { "esr15", 591, {0, {0}}, 0, 0 }, - { "esr16", 592, {0, {0}}, 0, 0 }, - { "esr17", 593, {0, {0}}, 0, 0 }, - { "esr18", 594, {0, {0}}, 0, 0 }, - { "esr19", 595, {0, {0}}, 0, 0 }, - { "esr20", 596, {0, {0}}, 0, 0 }, - { "esr21", 597, {0, {0}}, 0, 0 }, - { "esr22", 598, {0, {0}}, 0, 0 }, - { "esr23", 599, {0, {0}}, 0, 0 }, - { "esr24", 600, {0, {0}}, 0, 0 }, - { "esr25", 601, {0, {0}}, 0, 0 }, - { "esr26", 602, {0, {0}}, 0, 0 }, - { "esr27", 603, {0, {0}}, 0, 0 }, - { "esr28", 604, {0, {0}}, 0, 0 }, - { "esr29", 605, {0, {0}}, 0, 0 }, - { "esr30", 606, {0, {0}}, 0, 0 }, - { "esr31", 607, {0, {0}}, 0, 0 }, - { "esr32", 608, {0, {0}}, 0, 0 }, - { "esr33", 609, {0, {0}}, 0, 0 }, - { "esr34", 610, {0, {0}}, 0, 0 }, - { "esr35", 611, {0, {0}}, 0, 0 }, - { "esr36", 612, {0, {0}}, 0, 0 }, - { "esr37", 613, {0, {0}}, 0, 0 }, - { "esr38", 614, {0, {0}}, 0, 0 }, - { "esr39", 615, {0, {0}}, 0, 0 }, - { "esr40", 616, {0, {0}}, 0, 0 }, - { "esr41", 617, {0, {0}}, 0, 0 }, - { "esr42", 618, {0, {0}}, 0, 0 }, - { "esr43", 619, {0, {0}}, 0, 0 }, - { "esr44", 620, {0, {0}}, 0, 0 }, - { "esr45", 621, {0, {0}}, 0, 0 }, - { "esr46", 622, {0, {0}}, 0, 0 }, - { "esr47", 623, {0, {0}}, 0, 0 }, - { "esr48", 624, {0, {0}}, 0, 0 }, - { "esr49", 625, {0, {0}}, 0, 0 }, - { "esr50", 626, {0, {0}}, 0, 0 }, - { "esr51", 627, {0, {0}}, 0, 0 }, - { "esr52", 628, {0, {0}}, 0, 0 }, - { "esr53", 629, {0, {0}}, 0, 0 }, - { "esr54", 630, {0, {0}}, 0, 0 }, - { "esr55", 631, {0, {0}}, 0, 0 }, - { "esr56", 632, {0, {0}}, 0, 0 }, - { "esr57", 633, {0, {0}}, 0, 0 }, - { "esr58", 634, {0, {0}}, 0, 0 }, - { "esr59", 635, {0, {0}}, 0, 0 }, - { "esr60", 636, {0, {0}}, 0, 0 }, - { "esr61", 637, {0, {0}}, 0, 0 }, - { "esr62", 638, {0, {0}}, 0, 0 }, - { "esr63", 639, {0, {0}}, 0, 0 }, - { "eir0", 640, {0, {0}}, 0, 0 }, - { "eir1", 641, {0, {0}}, 0, 0 }, - { "eir2", 642, {0, {0}}, 0, 0 }, - { "eir3", 643, {0, {0}}, 0, 0 }, - { "eir4", 644, {0, {0}}, 0, 0 }, - { "eir5", 645, {0, {0}}, 0, 0 }, - { "eir6", 646, {0, {0}}, 0, 0 }, - { "eir7", 647, {0, {0}}, 0, 0 }, - { "eir8", 648, {0, {0}}, 0, 0 }, - { "eir9", 649, {0, {0}}, 0, 0 }, - { "eir10", 650, {0, {0}}, 0, 0 }, - { "eir11", 651, {0, {0}}, 0, 0 }, - { "eir12", 652, {0, {0}}, 0, 0 }, - { "eir13", 653, {0, {0}}, 0, 0 }, - { "eir14", 654, {0, {0}}, 0, 0 }, - { "eir15", 655, {0, {0}}, 0, 0 }, - { "eir16", 656, {0, {0}}, 0, 0 }, - { "eir17", 657, {0, {0}}, 0, 0 }, - { "eir18", 658, {0, {0}}, 0, 0 }, - { "eir19", 659, {0, {0}}, 0, 0 }, - { "eir20", 660, {0, {0}}, 0, 0 }, - { "eir21", 661, {0, {0}}, 0, 0 }, - { "eir22", 662, {0, {0}}, 0, 0 }, - { "eir23", 663, {0, {0}}, 0, 0 }, - { "eir24", 664, {0, {0}}, 0, 0 }, - { "eir25", 665, {0, {0}}, 0, 0 }, - { "eir26", 666, {0, {0}}, 0, 0 }, - { "eir27", 667, {0, {0}}, 0, 0 }, - { "eir28", 668, {0, {0}}, 0, 0 }, - { "eir29", 669, {0, {0}}, 0, 0 }, - { "eir30", 670, {0, {0}}, 0, 0 }, - { "eir31", 671, {0, {0}}, 0, 0 }, - { "esfr0", 672, {0, {0}}, 0, 0 }, - { "esfr1", 673, {0, {0}}, 0, 0 }, - { "sr0", 768, {0, {0}}, 0, 0 }, - { "sr1", 769, {0, {0}}, 0, 0 }, - { "sr2", 770, {0, {0}}, 0, 0 }, - { "sr3", 771, {0, {0}}, 0, 0 }, - { "scr0", 832, {0, {0}}, 0, 0 }, - { "scr1", 833, {0, {0}}, 0, 0 }, - { "scr2", 834, {0, {0}}, 0, 0 }, - { "scr3", 835, {0, {0}}, 0, 0 }, - { "fsr0", 1024, {0, {0}}, 0, 0 }, - { "fsr1", 1025, {0, {0}}, 0, 0 }, - { "fsr2", 1026, {0, {0}}, 0, 0 }, - { "fsr3", 1027, {0, {0}}, 0, 0 }, - { "fsr4", 1028, {0, {0}}, 0, 0 }, - { "fsr5", 1029, {0, {0}}, 0, 0 }, - { "fsr6", 1030, {0, {0}}, 0, 0 }, - { "fsr7", 1031, {0, {0}}, 0, 0 }, - { "fsr8", 1032, {0, {0}}, 0, 0 }, - { "fsr9", 1033, {0, {0}}, 0, 0 }, - { "fsr10", 1034, {0, {0}}, 0, 0 }, - { "fsr11", 1035, {0, {0}}, 0, 0 }, - { "fsr12", 1036, {0, {0}}, 0, 0 }, - { "fsr13", 1037, {0, {0}}, 0, 0 }, - { "fsr14", 1038, {0, {0}}, 0, 0 }, - { "fsr15", 1039, {0, {0}}, 0, 0 }, - { "fsr16", 1040, {0, {0}}, 0, 0 }, - { "fsr17", 1041, {0, {0}}, 0, 0 }, - { "fsr18", 1042, {0, {0}}, 0, 0 }, - { "fsr19", 1043, {0, {0}}, 0, 0 }, - { "fsr20", 1044, {0, {0}}, 0, 0 }, - { "fsr21", 1045, {0, {0}}, 0, 0 }, - { "fsr22", 1046, {0, {0}}, 0, 0 }, - { "fsr23", 1047, {0, {0}}, 0, 0 }, - { "fsr24", 1048, {0, {0}}, 0, 0 }, - { "fsr25", 1049, {0, {0}}, 0, 0 }, - { "fsr26", 1050, {0, {0}}, 0, 0 }, - { "fsr27", 1051, {0, {0}}, 0, 0 }, - { "fsr28", 1052, {0, {0}}, 0, 0 }, - { "fsr29", 1053, {0, {0}}, 0, 0 }, - { "fsr30", 1054, {0, {0}}, 0, 0 }, - { "fsr31", 1055, {0, {0}}, 0, 0 }, - { "fsr32", 1056, {0, {0}}, 0, 0 }, - { "fsr33", 1057, {0, {0}}, 0, 0 }, - { "fsr34", 1058, {0, {0}}, 0, 0 }, - { "fsr35", 1059, {0, {0}}, 0, 0 }, - { "fsr36", 1060, {0, {0}}, 0, 0 }, - { "fsr37", 1061, {0, {0}}, 0, 0 }, - { "fsr38", 1062, {0, {0}}, 0, 0 }, - { "fsr39", 1063, {0, {0}}, 0, 0 }, - { "fsr40", 1064, {0, {0}}, 0, 0 }, - { "fsr41", 1065, {0, {0}}, 0, 0 }, - { "fsr42", 1066, {0, {0}}, 0, 0 }, - { "fsr43", 1067, {0, {0}}, 0, 0 }, - { "fsr44", 1068, {0, {0}}, 0, 0 }, - { "fsr45", 1069, {0, {0}}, 0, 0 }, - { "fsr46", 1070, {0, {0}}, 0, 0 }, - { "fsr47", 1071, {0, {0}}, 0, 0 }, - { "fsr48", 1072, {0, {0}}, 0, 0 }, - { "fsr49", 1073, {0, {0}}, 0, 0 }, - { "fsr50", 1074, {0, {0}}, 0, 0 }, - { "fsr51", 1075, {0, {0}}, 0, 0 }, - { "fsr52", 1076, {0, {0}}, 0, 0 }, - { "fsr53", 1077, {0, {0}}, 0, 0 }, - { "fsr54", 1078, {0, {0}}, 0, 0 }, - { "fsr55", 1079, {0, {0}}, 0, 0 }, - { "fsr56", 1080, {0, {0}}, 0, 0 }, - { "fsr57", 1081, {0, {0}}, 0, 0 }, - { "fsr58", 1082, {0, {0}}, 0, 0 }, - { "fsr59", 1083, {0, {0}}, 0, 0 }, - { "fsr60", 1084, {0, {0}}, 0, 0 }, - { "fsr61", 1085, {0, {0}}, 0, 0 }, - { "fsr62", 1086, {0, {0}}, 0, 0 }, - { "fsr63", 1087, {0, {0}}, 0, 0 }, - { "fqop0", 1088, {0, {0}}, 0, 0 }, - { "fqop1", 1090, {0, {0}}, 0, 0 }, - { "fqop2", 1092, {0, {0}}, 0, 0 }, - { "fqop3", 1094, {0, {0}}, 0, 0 }, - { "fqop4", 1096, {0, {0}}, 0, 0 }, - { "fqop5", 1098, {0, {0}}, 0, 0 }, - { "fqop6", 1100, {0, {0}}, 0, 0 }, - { "fqop7", 1102, {0, {0}}, 0, 0 }, - { "fqop8", 1104, {0, {0}}, 0, 0 }, - { "fqop9", 1106, {0, {0}}, 0, 0 }, - { "fqop10", 1108, {0, {0}}, 0, 0 }, - { "fqop11", 1110, {0, {0}}, 0, 0 }, - { "fqop12", 1112, {0, {0}}, 0, 0 }, - { "fqop13", 1114, {0, {0}}, 0, 0 }, - { "fqop14", 1116, {0, {0}}, 0, 0 }, - { "fqop15", 1118, {0, {0}}, 0, 0 }, - { "fqop16", 1120, {0, {0}}, 0, 0 }, - { "fqop17", 1122, {0, {0}}, 0, 0 }, - { "fqop18", 1124, {0, {0}}, 0, 0 }, - { "fqop19", 1126, {0, {0}}, 0, 0 }, - { "fqop20", 1128, {0, {0}}, 0, 0 }, - { "fqop21", 1130, {0, {0}}, 0, 0 }, - { "fqop22", 1132, {0, {0}}, 0, 0 }, - { "fqop23", 1134, {0, {0}}, 0, 0 }, - { "fqop24", 1136, {0, {0}}, 0, 0 }, - { "fqop25", 1138, {0, {0}}, 0, 0 }, - { "fqop26", 1140, {0, {0}}, 0, 0 }, - { "fqop27", 1142, {0, {0}}, 0, 0 }, - { "fqop28", 1144, {0, {0}}, 0, 0 }, - { "fqop29", 1146, {0, {0}}, 0, 0 }, - { "fqop30", 1148, {0, {0}}, 0, 0 }, - { "fqop31", 1150, {0, {0}}, 0, 0 }, - { "fqst0", 1089, {0, {0}}, 0, 0 }, - { "fqst1", 1091, {0, {0}}, 0, 0 }, - { "fqst2", 1093, {0, {0}}, 0, 0 }, - { "fqst3", 1095, {0, {0}}, 0, 0 }, - { "fqst4", 1097, {0, {0}}, 0, 0 }, - { "fqst5", 1099, {0, {0}}, 0, 0 }, - { "fqst6", 1101, {0, {0}}, 0, 0 }, - { "fqst7", 1103, {0, {0}}, 0, 0 }, - { "fqst8", 1105, {0, {0}}, 0, 0 }, - { "fqst9", 1107, {0, {0}}, 0, 0 }, - { "fqst10", 1109, {0, {0}}, 0, 0 }, - { "fqst11", 1111, {0, {0}}, 0, 0 }, - { "fqst12", 1113, {0, {0}}, 0, 0 }, - { "fqst13", 1115, {0, {0}}, 0, 0 }, - { "fqst14", 1117, {0, {0}}, 0, 0 }, - { "fqst15", 1119, {0, {0}}, 0, 0 }, - { "fqst16", 1121, {0, {0}}, 0, 0 }, - { "fqst17", 1123, {0, {0}}, 0, 0 }, - { "fqst18", 1125, {0, {0}}, 0, 0 }, - { "fqst19", 1127, {0, {0}}, 0, 0 }, - { "fqst20", 1129, {0, {0}}, 0, 0 }, - { "fqst21", 1131, {0, {0}}, 0, 0 }, - { "fqst22", 1133, {0, {0}}, 0, 0 }, - { "fqst23", 1135, {0, {0}}, 0, 0 }, - { "fqst24", 1137, {0, {0}}, 0, 0 }, - { "fqst25", 1139, {0, {0}}, 0, 0 }, - { "fqst26", 1141, {0, {0}}, 0, 0 }, - { "fqst27", 1143, {0, {0}}, 0, 0 }, - { "fqst28", 1145, {0, {0}}, 0, 0 }, - { "fqst29", 1147, {0, {0}}, 0, 0 }, - { "fqst30", 1149, {0, {0}}, 0, 0 }, - { "fqst31", 1151, {0, {0}}, 0, 0 }, - { "mcilr0", 1272, {0, {0}}, 0, 0 }, - { "mcilr1", 1273, {0, {0}}, 0, 0 }, - { "msr0", 1280, {0, {0}}, 0, 0 }, - { "msr1", 1281, {0, {0}}, 0, 0 }, - { "msr2", 1282, {0, {0}}, 0, 0 }, - { "msr3", 1283, {0, {0}}, 0, 0 }, - { "msr4", 1284, {0, {0}}, 0, 0 }, - { "msr5", 1285, {0, {0}}, 0, 0 }, - { "msr6", 1286, {0, {0}}, 0, 0 }, - { "msr7", 1287, {0, {0}}, 0, 0 }, - { "msr8", 1288, {0, {0}}, 0, 0 }, - { "msr9", 1289, {0, {0}}, 0, 0 }, - { "msr10", 1290, {0, {0}}, 0, 0 }, - { "msr11", 1291, {0, {0}}, 0, 0 }, - { "msr12", 1292, {0, {0}}, 0, 0 }, - { "msr13", 1293, {0, {0}}, 0, 0 }, - { "msr14", 1294, {0, {0}}, 0, 0 }, - { "msr15", 1295, {0, {0}}, 0, 0 }, - { "msr16", 1296, {0, {0}}, 0, 0 }, - { "msr17", 1297, {0, {0}}, 0, 0 }, - { "msr18", 1298, {0, {0}}, 0, 0 }, - { "msr19", 1299, {0, {0}}, 0, 0 }, - { "msr20", 1300, {0, {0}}, 0, 0 }, - { "msr21", 1301, {0, {0}}, 0, 0 }, - { "msr22", 1302, {0, {0}}, 0, 0 }, - { "msr23", 1303, {0, {0}}, 0, 0 }, - { "msr24", 1304, {0, {0}}, 0, 0 }, - { "msr25", 1305, {0, {0}}, 0, 0 }, - { "msr26", 1306, {0, {0}}, 0, 0 }, - { "msr27", 1307, {0, {0}}, 0, 0 }, - { "msr28", 1308, {0, {0}}, 0, 0 }, - { "msr29", 1309, {0, {0}}, 0, 0 }, - { "msr30", 1310, {0, {0}}, 0, 0 }, - { "msr31", 1311, {0, {0}}, 0, 0 }, - { "msr32", 1312, {0, {0}}, 0, 0 }, - { "msr33", 1313, {0, {0}}, 0, 0 }, - { "msr34", 1314, {0, {0}}, 0, 0 }, - { "msr35", 1315, {0, {0}}, 0, 0 }, - { "msr36", 1316, {0, {0}}, 0, 0 }, - { "msr37", 1317, {0, {0}}, 0, 0 }, - { "msr38", 1318, {0, {0}}, 0, 0 }, - { "msr39", 1319, {0, {0}}, 0, 0 }, - { "msr40", 1320, {0, {0}}, 0, 0 }, - { "msr41", 1321, {0, {0}}, 0, 0 }, - { "msr42", 1322, {0, {0}}, 0, 0 }, - { "msr43", 1323, {0, {0}}, 0, 0 }, - { "msr44", 1324, {0, {0}}, 0, 0 }, - { "msr45", 1325, {0, {0}}, 0, 0 }, - { "msr46", 1326, {0, {0}}, 0, 0 }, - { "msr47", 1327, {0, {0}}, 0, 0 }, - { "msr48", 1328, {0, {0}}, 0, 0 }, - { "msr49", 1329, {0, {0}}, 0, 0 }, - { "msr50", 1330, {0, {0}}, 0, 0 }, - { "msr51", 1331, {0, {0}}, 0, 0 }, - { "msr52", 1332, {0, {0}}, 0, 0 }, - { "msr53", 1333, {0, {0}}, 0, 0 }, - { "msr54", 1334, {0, {0}}, 0, 0 }, - { "msr55", 1335, {0, {0}}, 0, 0 }, - { "msr56", 1336, {0, {0}}, 0, 0 }, - { "msr57", 1337, {0, {0}}, 0, 0 }, - { "msr58", 1338, {0, {0}}, 0, 0 }, - { "msr59", 1339, {0, {0}}, 0, 0 }, - { "msr60", 1340, {0, {0}}, 0, 0 }, - { "msr61", 1341, {0, {0}}, 0, 0 }, - { "msr62", 1342, {0, {0}}, 0, 0 }, - { "msr63", 1343, {0, {0}}, 0, 0 }, - { "mqop0", 1344, {0, {0}}, 0, 0 }, - { "mqop1", 1346, {0, {0}}, 0, 0 }, - { "mqop2", 1348, {0, {0}}, 0, 0 }, - { "mqop3", 1350, {0, {0}}, 0, 0 }, - { "mqop4", 1352, {0, {0}}, 0, 0 }, - { "mqop5", 1354, {0, {0}}, 0, 0 }, - { "mqop6", 1356, {0, {0}}, 0, 0 }, - { "mqop7", 1358, {0, {0}}, 0, 0 }, - { "mqop8", 1360, {0, {0}}, 0, 0 }, - { "mqop9", 1362, {0, {0}}, 0, 0 }, - { "mqop10", 1364, {0, {0}}, 0, 0 }, - { "mqop11", 1366, {0, {0}}, 0, 0 }, - { "mqop12", 1368, {0, {0}}, 0, 0 }, - { "mqop13", 1370, {0, {0}}, 0, 0 }, - { "mqop14", 1372, {0, {0}}, 0, 0 }, - { "mqop15", 1374, {0, {0}}, 0, 0 }, - { "mqop16", 1376, {0, {0}}, 0, 0 }, - { "mqop17", 1378, {0, {0}}, 0, 0 }, - { "mqop18", 1380, {0, {0}}, 0, 0 }, - { "mqop19", 1382, {0, {0}}, 0, 0 }, - { "mqop20", 1384, {0, {0}}, 0, 0 }, - { "mqop21", 1386, {0, {0}}, 0, 0 }, - { "mqop22", 1388, {0, {0}}, 0, 0 }, - { "mqop23", 1390, {0, {0}}, 0, 0 }, - { "mqop24", 1392, {0, {0}}, 0, 0 }, - { "mqop25", 1394, {0, {0}}, 0, 0 }, - { "mqop26", 1396, {0, {0}}, 0, 0 }, - { "mqop27", 1398, {0, {0}}, 0, 0 }, - { "mqop28", 1400, {0, {0}}, 0, 0 }, - { "mqop29", 1402, {0, {0}}, 0, 0 }, - { "mqop30", 1404, {0, {0}}, 0, 0 }, - { "mqop31", 1406, {0, {0}}, 0, 0 }, - { "mqst0", 1345, {0, {0}}, 0, 0 }, - { "mqst1", 1347, {0, {0}}, 0, 0 }, - { "mqst2", 1349, {0, {0}}, 0, 0 }, - { "mqst3", 1351, {0, {0}}, 0, 0 }, - { "mqst4", 1353, {0, {0}}, 0, 0 }, - { "mqst5", 1355, {0, {0}}, 0, 0 }, - { "mqst6", 1357, {0, {0}}, 0, 0 }, - { "mqst7", 1359, {0, {0}}, 0, 0 }, - { "mqst8", 1361, {0, {0}}, 0, 0 }, - { "mqst9", 1363, {0, {0}}, 0, 0 }, - { "mqst10", 1365, {0, {0}}, 0, 0 }, - { "mqst11", 1367, {0, {0}}, 0, 0 }, - { "mqst12", 1369, {0, {0}}, 0, 0 }, - { "mqst13", 1371, {0, {0}}, 0, 0 }, - { "mqst14", 1373, {0, {0}}, 0, 0 }, - { "mqst15", 1375, {0, {0}}, 0, 0 }, - { "mqst16", 1377, {0, {0}}, 0, 0 }, - { "mqst17", 1379, {0, {0}}, 0, 0 }, - { "mqst18", 1381, {0, {0}}, 0, 0 }, - { "mqst19", 1383, {0, {0}}, 0, 0 }, - { "mqst20", 1385, {0, {0}}, 0, 0 }, - { "mqst21", 1387, {0, {0}}, 0, 0 }, - { "mqst22", 1389, {0, {0}}, 0, 0 }, - { "mqst23", 1391, {0, {0}}, 0, 0 }, - { "mqst24", 1393, {0, {0}}, 0, 0 }, - { "mqst25", 1395, {0, {0}}, 0, 0 }, - { "mqst26", 1397, {0, {0}}, 0, 0 }, - { "mqst27", 1399, {0, {0}}, 0, 0 }, - { "mqst28", 1401, {0, {0}}, 0, 0 }, - { "mqst29", 1403, {0, {0}}, 0, 0 }, - { "mqst30", 1405, {0, {0}}, 0, 0 }, - { "mqst31", 1407, {0, {0}}, 0, 0 }, - { "ear0", 1536, {0, {0}}, 0, 0 }, - { "ear1", 1537, {0, {0}}, 0, 0 }, - { "ear2", 1538, {0, {0}}, 0, 0 }, - { "ear3", 1539, {0, {0}}, 0, 0 }, - { "ear4", 1540, {0, {0}}, 0, 0 }, - { "ear5", 1541, {0, {0}}, 0, 0 }, - { "ear6", 1542, {0, {0}}, 0, 0 }, - { "ear7", 1543, {0, {0}}, 0, 0 }, - { "ear8", 1544, {0, {0}}, 0, 0 }, - { "ear9", 1545, {0, {0}}, 0, 0 }, - { "ear10", 1546, {0, {0}}, 0, 0 }, - { "ear11", 1547, {0, {0}}, 0, 0 }, - { "ear12", 1548, {0, {0}}, 0, 0 }, - { "ear13", 1549, {0, {0}}, 0, 0 }, - { "ear14", 1550, {0, {0}}, 0, 0 }, - { "ear15", 1551, {0, {0}}, 0, 0 }, - { "ear16", 1552, {0, {0}}, 0, 0 }, - { "ear17", 1553, {0, {0}}, 0, 0 }, - { "ear18", 1554, {0, {0}}, 0, 0 }, - { "ear19", 1555, {0, {0}}, 0, 0 }, - { "ear20", 1556, {0, {0}}, 0, 0 }, - { "ear21", 1557, {0, {0}}, 0, 0 }, - { "ear22", 1558, {0, {0}}, 0, 0 }, - { "ear23", 1559, {0, {0}}, 0, 0 }, - { "ear24", 1560, {0, {0}}, 0, 0 }, - { "ear25", 1561, {0, {0}}, 0, 0 }, - { "ear26", 1562, {0, {0}}, 0, 0 }, - { "ear27", 1563, {0, {0}}, 0, 0 }, - { "ear28", 1564, {0, {0}}, 0, 0 }, - { "ear29", 1565, {0, {0}}, 0, 0 }, - { "ear30", 1566, {0, {0}}, 0, 0 }, - { "ear31", 1567, {0, {0}}, 0, 0 }, - { "ear32", 1568, {0, {0}}, 0, 0 }, - { "ear33", 1569, {0, {0}}, 0, 0 }, - { "ear34", 1570, {0, {0}}, 0, 0 }, - { "ear35", 1571, {0, {0}}, 0, 0 }, - { "ear36", 1572, {0, {0}}, 0, 0 }, - { "ear37", 1573, {0, {0}}, 0, 0 }, - { "ear38", 1574, {0, {0}}, 0, 0 }, - { "ear39", 1575, {0, {0}}, 0, 0 }, - { "ear40", 1576, {0, {0}}, 0, 0 }, - { "ear41", 1577, {0, {0}}, 0, 0 }, - { "ear42", 1578, {0, {0}}, 0, 0 }, - { "ear43", 1579, {0, {0}}, 0, 0 }, - { "ear44", 1580, {0, {0}}, 0, 0 }, - { "ear45", 1581, {0, {0}}, 0, 0 }, - { "ear46", 1582, {0, {0}}, 0, 0 }, - { "ear47", 1583, {0, {0}}, 0, 0 }, - { "ear48", 1584, {0, {0}}, 0, 0 }, - { "ear49", 1585, {0, {0}}, 0, 0 }, - { "ear50", 1586, {0, {0}}, 0, 0 }, - { "ear51", 1587, {0, {0}}, 0, 0 }, - { "ear52", 1588, {0, {0}}, 0, 0 }, - { "ear53", 1589, {0, {0}}, 0, 0 }, - { "ear54", 1590, {0, {0}}, 0, 0 }, - { "ear55", 1591, {0, {0}}, 0, 0 }, - { "ear56", 1592, {0, {0}}, 0, 0 }, - { "ear57", 1593, {0, {0}}, 0, 0 }, - { "ear58", 1594, {0, {0}}, 0, 0 }, - { "ear59", 1595, {0, {0}}, 0, 0 }, - { "ear60", 1596, {0, {0}}, 0, 0 }, - { "ear61", 1597, {0, {0}}, 0, 0 }, - { "ear62", 1598, {0, {0}}, 0, 0 }, - { "ear63", 1599, {0, {0}}, 0, 0 }, - { "edr0", 1600, {0, {0}}, 0, 0 }, - { "edr1", 1601, {0, {0}}, 0, 0 }, - { "edr2", 1602, {0, {0}}, 0, 0 }, - { "edr3", 1603, {0, {0}}, 0, 0 }, - { "edr4", 1604, {0, {0}}, 0, 0 }, - { "edr5", 1605, {0, {0}}, 0, 0 }, - { "edr6", 1606, {0, {0}}, 0, 0 }, - { "edr7", 1607, {0, {0}}, 0, 0 }, - { "edr8", 1608, {0, {0}}, 0, 0 }, - { "edr9", 1609, {0, {0}}, 0, 0 }, - { "edr10", 1610, {0, {0}}, 0, 0 }, - { "edr11", 1611, {0, {0}}, 0, 0 }, - { "edr12", 1612, {0, {0}}, 0, 0 }, - { "edr13", 1613, {0, {0}}, 0, 0 }, - { "edr14", 1614, {0, {0}}, 0, 0 }, - { "edr15", 1615, {0, {0}}, 0, 0 }, - { "edr16", 1616, {0, {0}}, 0, 0 }, - { "edr17", 1617, {0, {0}}, 0, 0 }, - { "edr18", 1618, {0, {0}}, 0, 0 }, - { "edr19", 1619, {0, {0}}, 0, 0 }, - { "edr20", 1620, {0, {0}}, 0, 0 }, - { "edr21", 1621, {0, {0}}, 0, 0 }, - { "edr22", 1622, {0, {0}}, 0, 0 }, - { "edr23", 1623, {0, {0}}, 0, 0 }, - { "edr24", 1624, {0, {0}}, 0, 0 }, - { "edr25", 1625, {0, {0}}, 0, 0 }, - { "edr26", 1626, {0, {0}}, 0, 0 }, - { "edr27", 1627, {0, {0}}, 0, 0 }, - { "edr28", 1628, {0, {0}}, 0, 0 }, - { "edr29", 1629, {0, {0}}, 0, 0 }, - { "edr30", 1630, {0, {0}}, 0, 0 }, - { "edr31", 1631, {0, {0}}, 0, 0 }, - { "edr32", 1632, {0, {0}}, 0, 0 }, - { "edr33", 1636, {0, {0}}, 0, 0 }, - { "edr34", 1634, {0, {0}}, 0, 0 }, - { "edr35", 1635, {0, {0}}, 0, 0 }, - { "edr36", 1636, {0, {0}}, 0, 0 }, - { "edr37", 1637, {0, {0}}, 0, 0 }, - { "edr38", 1638, {0, {0}}, 0, 0 }, - { "edr39", 1639, {0, {0}}, 0, 0 }, - { "edr40", 1640, {0, {0}}, 0, 0 }, - { "edr41", 1641, {0, {0}}, 0, 0 }, - { "edr42", 1642, {0, {0}}, 0, 0 }, - { "edr43", 1643, {0, {0}}, 0, 0 }, - { "edr44", 1644, {0, {0}}, 0, 0 }, - { "edr45", 1645, {0, {0}}, 0, 0 }, - { "edr46", 1646, {0, {0}}, 0, 0 }, - { "edr47", 1647, {0, {0}}, 0, 0 }, - { "edr48", 1648, {0, {0}}, 0, 0 }, - { "edr49", 1649, {0, {0}}, 0, 0 }, - { "edr50", 1650, {0, {0}}, 0, 0 }, - { "edr51", 1651, {0, {0}}, 0, 0 }, - { "edr52", 1652, {0, {0}}, 0, 0 }, - { "edr53", 1653, {0, {0}}, 0, 0 }, - { "edr54", 1654, {0, {0}}, 0, 0 }, - { "edr55", 1655, {0, {0}}, 0, 0 }, - { "edr56", 1656, {0, {0}}, 0, 0 }, - { "edr57", 1657, {0, {0}}, 0, 0 }, - { "edr58", 1658, {0, {0}}, 0, 0 }, - { "edr59", 1659, {0, {0}}, 0, 0 }, - { "edr60", 1660, {0, {0}}, 0, 0 }, - { "edr61", 1661, {0, {0}}, 0, 0 }, - { "edr62", 1662, {0, {0}}, 0, 0 }, - { "edr63", 1663, {0, {0}}, 0, 0 }, - { "iamlr0", 1664, {0, {0}}, 0, 0 }, - { "iamlr1", 1665, {0, {0}}, 0, 0 }, - { "iamlr2", 1666, {0, {0}}, 0, 0 }, - { "iamlr3", 1667, {0, {0}}, 0, 0 }, - { "iamlr4", 1668, {0, {0}}, 0, 0 }, - { "iamlr5", 1669, {0, {0}}, 0, 0 }, - { "iamlr6", 1670, {0, {0}}, 0, 0 }, - { "iamlr7", 1671, {0, {0}}, 0, 0 }, - { "iamlr8", 1672, {0, {0}}, 0, 0 }, - { "iamlr9", 1673, {0, {0}}, 0, 0 }, - { "iamlr10", 1674, {0, {0}}, 0, 0 }, - { "iamlr11", 1675, {0, {0}}, 0, 0 }, - { "iamlr12", 1676, {0, {0}}, 0, 0 }, - { "iamlr13", 1677, {0, {0}}, 0, 0 }, - { "iamlr14", 1678, {0, {0}}, 0, 0 }, - { "iamlr15", 1679, {0, {0}}, 0, 0 }, - { "iamlr16", 1680, {0, {0}}, 0, 0 }, - { "iamlr17", 1681, {0, {0}}, 0, 0 }, - { "iamlr18", 1682, {0, {0}}, 0, 0 }, - { "iamlr19", 1683, {0, {0}}, 0, 0 }, - { "iamlr20", 1684, {0, {0}}, 0, 0 }, - { "iamlr21", 1685, {0, {0}}, 0, 0 }, - { "iamlr22", 1686, {0, {0}}, 0, 0 }, - { "iamlr23", 1687, {0, {0}}, 0, 0 }, - { "iamlr24", 1688, {0, {0}}, 0, 0 }, - { "iamlr25", 1689, {0, {0}}, 0, 0 }, - { "iamlr26", 1690, {0, {0}}, 0, 0 }, - { "iamlr27", 1691, {0, {0}}, 0, 0 }, - { "iamlr28", 1692, {0, {0}}, 0, 0 }, - { "iamlr29", 1693, {0, {0}}, 0, 0 }, - { "iamlr30", 1694, {0, {0}}, 0, 0 }, - { "iamlr31", 1695, {0, {0}}, 0, 0 }, - { "iamlr32", 1696, {0, {0}}, 0, 0 }, - { "iamlr33", 1697, {0, {0}}, 0, 0 }, - { "iamlr34", 1698, {0, {0}}, 0, 0 }, - { "iamlr35", 1699, {0, {0}}, 0, 0 }, - { "iamlr36", 1700, {0, {0}}, 0, 0 }, - { "iamlr37", 1701, {0, {0}}, 0, 0 }, - { "iamlr38", 1702, {0, {0}}, 0, 0 }, - { "iamlr39", 1703, {0, {0}}, 0, 0 }, - { "iamlr40", 1704, {0, {0}}, 0, 0 }, - { "iamlr41", 1705, {0, {0}}, 0, 0 }, - { "iamlr42", 1706, {0, {0}}, 0, 0 }, - { "iamlr43", 1707, {0, {0}}, 0, 0 }, - { "iamlr44", 1708, {0, {0}}, 0, 0 }, - { "iamlr45", 1709, {0, {0}}, 0, 0 }, - { "iamlr46", 1710, {0, {0}}, 0, 0 }, - { "iamlr47", 1711, {0, {0}}, 0, 0 }, - { "iamlr48", 1712, {0, {0}}, 0, 0 }, - { "iamlr49", 1713, {0, {0}}, 0, 0 }, - { "iamlr50", 1714, {0, {0}}, 0, 0 }, - { "iamlr51", 1715, {0, {0}}, 0, 0 }, - { "iamlr52", 1716, {0, {0}}, 0, 0 }, - { "iamlr53", 1717, {0, {0}}, 0, 0 }, - { "iamlr54", 1718, {0, {0}}, 0, 0 }, - { "iamlr55", 1719, {0, {0}}, 0, 0 }, - { "iamlr56", 1720, {0, {0}}, 0, 0 }, - { "iamlr57", 1721, {0, {0}}, 0, 0 }, - { "iamlr58", 1722, {0, {0}}, 0, 0 }, - { "iamlr59", 1723, {0, {0}}, 0, 0 }, - { "iamlr60", 1724, {0, {0}}, 0, 0 }, - { "iamlr61", 1725, {0, {0}}, 0, 0 }, - { "iamlr62", 1726, {0, {0}}, 0, 0 }, - { "iamlr63", 1727, {0, {0}}, 0, 0 }, - { "iampr0", 1728, {0, {0}}, 0, 0 }, - { "iampr1", 1729, {0, {0}}, 0, 0 }, - { "iampr2", 1730, {0, {0}}, 0, 0 }, - { "iampr3", 1731, {0, {0}}, 0, 0 }, - { "iampr4", 1732, {0, {0}}, 0, 0 }, - { "iampr5", 1733, {0, {0}}, 0, 0 }, - { "iampr6", 1734, {0, {0}}, 0, 0 }, - { "iampr7", 1735, {0, {0}}, 0, 0 }, - { "iampr8", 1736, {0, {0}}, 0, 0 }, - { "iampr9", 1737, {0, {0}}, 0, 0 }, - { "iampr10", 1738, {0, {0}}, 0, 0 }, - { "iampr11", 1739, {0, {0}}, 0, 0 }, - { "iampr12", 1740, {0, {0}}, 0, 0 }, - { "iampr13", 1741, {0, {0}}, 0, 0 }, - { "iampr14", 1742, {0, {0}}, 0, 0 }, - { "iampr15", 1743, {0, {0}}, 0, 0 }, - { "iampr16", 1744, {0, {0}}, 0, 0 }, - { "iampr17", 1745, {0, {0}}, 0, 0 }, - { "iampr18", 1746, {0, {0}}, 0, 0 }, - { "iampr19", 1747, {0, {0}}, 0, 0 }, - { "iampr20", 1748, {0, {0}}, 0, 0 }, - { "iampr21", 1749, {0, {0}}, 0, 0 }, - { "iampr22", 1750, {0, {0}}, 0, 0 }, - { "iampr23", 1751, {0, {0}}, 0, 0 }, - { "iampr24", 1752, {0, {0}}, 0, 0 }, - { "iampr25", 1753, {0, {0}}, 0, 0 }, - { "iampr26", 1754, {0, {0}}, 0, 0 }, - { "iampr27", 1755, {0, {0}}, 0, 0 }, - { "iampr28", 1756, {0, {0}}, 0, 0 }, - { "iampr29", 1757, {0, {0}}, 0, 0 }, - { "iampr30", 1758, {0, {0}}, 0, 0 }, - { "iampr31", 1759, {0, {0}}, 0, 0 }, - { "iampr32", 1760, {0, {0}}, 0, 0 }, - { "iampr33", 1761, {0, {0}}, 0, 0 }, - { "iampr34", 1762, {0, {0}}, 0, 0 }, - { "iampr35", 1763, {0, {0}}, 0, 0 }, - { "iampr36", 1764, {0, {0}}, 0, 0 }, - { "iampr37", 1765, {0, {0}}, 0, 0 }, - { "iampr38", 1766, {0, {0}}, 0, 0 }, - { "iampr39", 1767, {0, {0}}, 0, 0 }, - { "iampr40", 1768, {0, {0}}, 0, 0 }, - { "iampr41", 1769, {0, {0}}, 0, 0 }, - { "iampr42", 1770, {0, {0}}, 0, 0 }, - { "iampr43", 1771, {0, {0}}, 0, 0 }, - { "iampr44", 1772, {0, {0}}, 0, 0 }, - { "iampr45", 1773, {0, {0}}, 0, 0 }, - { "iampr46", 1774, {0, {0}}, 0, 0 }, - { "iampr47", 1775, {0, {0}}, 0, 0 }, - { "iampr48", 1776, {0, {0}}, 0, 0 }, - { "iampr49", 1777, {0, {0}}, 0, 0 }, - { "iampr50", 1778, {0, {0}}, 0, 0 }, - { "iampr51", 1779, {0, {0}}, 0, 0 }, - { "iampr52", 1780, {0, {0}}, 0, 0 }, - { "iampr53", 1781, {0, {0}}, 0, 0 }, - { "iampr54", 1782, {0, {0}}, 0, 0 }, - { "iampr55", 1783, {0, {0}}, 0, 0 }, - { "iampr56", 1784, {0, {0}}, 0, 0 }, - { "iampr57", 1785, {0, {0}}, 0, 0 }, - { "iampr58", 1786, {0, {0}}, 0, 0 }, - { "iampr59", 1787, {0, {0}}, 0, 0 }, - { "iampr60", 1788, {0, {0}}, 0, 0 }, - { "iampr61", 1789, {0, {0}}, 0, 0 }, - { "iampr62", 1790, {0, {0}}, 0, 0 }, - { "iampr63", 1791, {0, {0}}, 0, 0 }, - { "damlr0", 1792, {0, {0}}, 0, 0 }, - { "damlr1", 1793, {0, {0}}, 0, 0 }, - { "damlr2", 1794, {0, {0}}, 0, 0 }, - { "damlr3", 1795, {0, {0}}, 0, 0 }, - { "damlr4", 1796, {0, {0}}, 0, 0 }, - { "damlr5", 1797, {0, {0}}, 0, 0 }, - { "damlr6", 1798, {0, {0}}, 0, 0 }, - { "damlr7", 1799, {0, {0}}, 0, 0 }, - { "damlr8", 1800, {0, {0}}, 0, 0 }, - { "damlr9", 1801, {0, {0}}, 0, 0 }, - { "damlr10", 1802, {0, {0}}, 0, 0 }, - { "damlr11", 1803, {0, {0}}, 0, 0 }, - { "damlr12", 1804, {0, {0}}, 0, 0 }, - { "damlr13", 1805, {0, {0}}, 0, 0 }, - { "damlr14", 1806, {0, {0}}, 0, 0 }, - { "damlr15", 1807, {0, {0}}, 0, 0 }, - { "damlr16", 1808, {0, {0}}, 0, 0 }, - { "damlr17", 1809, {0, {0}}, 0, 0 }, - { "damlr18", 1810, {0, {0}}, 0, 0 }, - { "damlr19", 1811, {0, {0}}, 0, 0 }, - { "damlr20", 1812, {0, {0}}, 0, 0 }, - { "damlr21", 1813, {0, {0}}, 0, 0 }, - { "damlr22", 1814, {0, {0}}, 0, 0 }, - { "damlr23", 1815, {0, {0}}, 0, 0 }, - { "damlr24", 1816, {0, {0}}, 0, 0 }, - { "damlr25", 1817, {0, {0}}, 0, 0 }, - { "damlr26", 1818, {0, {0}}, 0, 0 }, - { "damlr27", 1819, {0, {0}}, 0, 0 }, - { "damlr28", 1820, {0, {0}}, 0, 0 }, - { "damlr29", 1821, {0, {0}}, 0, 0 }, - { "damlr30", 1822, {0, {0}}, 0, 0 }, - { "damlr31", 1823, {0, {0}}, 0, 0 }, - { "damlr32", 1824, {0, {0}}, 0, 0 }, - { "damlr33", 1825, {0, {0}}, 0, 0 }, - { "damlr34", 1826, {0, {0}}, 0, 0 }, - { "damlr35", 1827, {0, {0}}, 0, 0 }, - { "damlr36", 1828, {0, {0}}, 0, 0 }, - { "damlr37", 1829, {0, {0}}, 0, 0 }, - { "damlr38", 1830, {0, {0}}, 0, 0 }, - { "damlr39", 1831, {0, {0}}, 0, 0 }, - { "damlr40", 1832, {0, {0}}, 0, 0 }, - { "damlr41", 1833, {0, {0}}, 0, 0 }, - { "damlr42", 1834, {0, {0}}, 0, 0 }, - { "damlr43", 1835, {0, {0}}, 0, 0 }, - { "damlr44", 1836, {0, {0}}, 0, 0 }, - { "damlr45", 1837, {0, {0}}, 0, 0 }, - { "damlr46", 1838, {0, {0}}, 0, 0 }, - { "damlr47", 1839, {0, {0}}, 0, 0 }, - { "damlr48", 1840, {0, {0}}, 0, 0 }, - { "damlr49", 1841, {0, {0}}, 0, 0 }, - { "damlr50", 1842, {0, {0}}, 0, 0 }, - { "damlr51", 1843, {0, {0}}, 0, 0 }, - { "damlr52", 1844, {0, {0}}, 0, 0 }, - { "damlr53", 1845, {0, {0}}, 0, 0 }, - { "damlr54", 1846, {0, {0}}, 0, 0 }, - { "damlr55", 1847, {0, {0}}, 0, 0 }, - { "damlr56", 1848, {0, {0}}, 0, 0 }, - { "damlr57", 1849, {0, {0}}, 0, 0 }, - { "damlr58", 1850, {0, {0}}, 0, 0 }, - { "damlr59", 1851, {0, {0}}, 0, 0 }, - { "damlr60", 1852, {0, {0}}, 0, 0 }, - { "damlr61", 1853, {0, {0}}, 0, 0 }, - { "damlr62", 1854, {0, {0}}, 0, 0 }, - { "damlr63", 1855, {0, {0}}, 0, 0 }, - { "dampr0", 1856, {0, {0}}, 0, 0 }, - { "dampr1", 1857, {0, {0}}, 0, 0 }, - { "dampr2", 1858, {0, {0}}, 0, 0 }, - { "dampr3", 1859, {0, {0}}, 0, 0 }, - { "dampr4", 1860, {0, {0}}, 0, 0 }, - { "dampr5", 1861, {0, {0}}, 0, 0 }, - { "dampr6", 1862, {0, {0}}, 0, 0 }, - { "dampr7", 1863, {0, {0}}, 0, 0 }, - { "dampr8", 1864, {0, {0}}, 0, 0 }, - { "dampr9", 1865, {0, {0}}, 0, 0 }, - { "dampr10", 1866, {0, {0}}, 0, 0 }, - { "dampr11", 1867, {0, {0}}, 0, 0 }, - { "dampr12", 1868, {0, {0}}, 0, 0 }, - { "dampr13", 1869, {0, {0}}, 0, 0 }, - { "dampr14", 1870, {0, {0}}, 0, 0 }, - { "dampr15", 1871, {0, {0}}, 0, 0 }, - { "dampr16", 1872, {0, {0}}, 0, 0 }, - { "dampr17", 1873, {0, {0}}, 0, 0 }, - { "dampr18", 1874, {0, {0}}, 0, 0 }, - { "dampr19", 1875, {0, {0}}, 0, 0 }, - { "dampr20", 1876, {0, {0}}, 0, 0 }, - { "dampr21", 1877, {0, {0}}, 0, 0 }, - { "dampr22", 1878, {0, {0}}, 0, 0 }, - { "dampr23", 1879, {0, {0}}, 0, 0 }, - { "dampr24", 1880, {0, {0}}, 0, 0 }, - { "dampr25", 1881, {0, {0}}, 0, 0 }, - { "dampr26", 1882, {0, {0}}, 0, 0 }, - { "dampr27", 1883, {0, {0}}, 0, 0 }, - { "dampr28", 1884, {0, {0}}, 0, 0 }, - { "dampr29", 1885, {0, {0}}, 0, 0 }, - { "dampr30", 1886, {0, {0}}, 0, 0 }, - { "dampr31", 1887, {0, {0}}, 0, 0 }, - { "dampr32", 1888, {0, {0}}, 0, 0 }, - { "dampr33", 1889, {0, {0}}, 0, 0 }, - { "dampr34", 1890, {0, {0}}, 0, 0 }, - { "dampr35", 1891, {0, {0}}, 0, 0 }, - { "dampr36", 1892, {0, {0}}, 0, 0 }, - { "dampr37", 1893, {0, {0}}, 0, 0 }, - { "dampr38", 1894, {0, {0}}, 0, 0 }, - { "dampr39", 1895, {0, {0}}, 0, 0 }, - { "dampr40", 1896, {0, {0}}, 0, 0 }, - { "dampr41", 1897, {0, {0}}, 0, 0 }, - { "dampr42", 1898, {0, {0}}, 0, 0 }, - { "dampr43", 1899, {0, {0}}, 0, 0 }, - { "dampr44", 1900, {0, {0}}, 0, 0 }, - { "dampr45", 1901, {0, {0}}, 0, 0 }, - { "dampr46", 1902, {0, {0}}, 0, 0 }, - { "dampr47", 1903, {0, {0}}, 0, 0 }, - { "dampr48", 1904, {0, {0}}, 0, 0 }, - { "dampr49", 1905, {0, {0}}, 0, 0 }, - { "dampr50", 1906, {0, {0}}, 0, 0 }, - { "dampr51", 1907, {0, {0}}, 0, 0 }, - { "dampr52", 1908, {0, {0}}, 0, 0 }, - { "dampr53", 1909, {0, {0}}, 0, 0 }, - { "dampr54", 1910, {0, {0}}, 0, 0 }, - { "dampr55", 1911, {0, {0}}, 0, 0 }, - { "dampr56", 1912, {0, {0}}, 0, 0 }, - { "dampr57", 1913, {0, {0}}, 0, 0 }, - { "dampr58", 1914, {0, {0}}, 0, 0 }, - { "dampr59", 1915, {0, {0}}, 0, 0 }, - { "dampr60", 1916, {0, {0}}, 0, 0 }, - { "dampr61", 1917, {0, {0}}, 0, 0 }, - { "dampr62", 1918, {0, {0}}, 0, 0 }, - { "dampr63", 1919, {0, {0}}, 0, 0 }, - { "amcr", 1920, {0, {0}}, 0, 0 }, - { "stbar", 1921, {0, {0}}, 0, 0 }, - { "mmcr", 1922, {0, {0}}, 0, 0 }, - { "iamvr1", 1925, {0, {0}}, 0, 0 }, - { "damvr1", 1927, {0, {0}}, 0, 0 }, - { "cxnr", 1936, {0, {0}}, 0, 0 }, - { "ttbr", 1937, {0, {0}}, 0, 0 }, - { "tplr", 1938, {0, {0}}, 0, 0 }, - { "tppr", 1939, {0, {0}}, 0, 0 }, - { "tpxr", 1940, {0, {0}}, 0, 0 }, - { "timerh", 1952, {0, {0}}, 0, 0 }, - { "timerl", 1953, {0, {0}}, 0, 0 }, - { "timerd", 1954, {0, {0}}, 0, 0 }, - { "dcr", 2048, {0, {0}}, 0, 0 }, - { "brr", 2049, {0, {0}}, 0, 0 }, - { "nmar", 2050, {0, {0}}, 0, 0 }, - { "btbr", 2051, {0, {0}}, 0, 0 }, - { "ibar0", 2052, {0, {0}}, 0, 0 }, - { "ibar1", 2053, {0, {0}}, 0, 0 }, - { "ibar2", 2054, {0, {0}}, 0, 0 }, - { "ibar3", 2055, {0, {0}}, 0, 0 }, - { "dbar0", 2056, {0, {0}}, 0, 0 }, - { "dbar1", 2057, {0, {0}}, 0, 0 }, - { "dbar2", 2058, {0, {0}}, 0, 0 }, - { "dbar3", 2059, {0, {0}}, 0, 0 }, - { "dbdr00", 2060, {0, {0}}, 0, 0 }, - { "dbdr01", 2061, {0, {0}}, 0, 0 }, - { "dbdr02", 2062, {0, {0}}, 0, 0 }, - { "dbdr03", 2063, {0, {0}}, 0, 0 }, - { "dbdr10", 2064, {0, {0}}, 0, 0 }, - { "dbdr11", 2065, {0, {0}}, 0, 0 }, - { "dbdr12", 2066, {0, {0}}, 0, 0 }, - { "dbdr13", 2067, {0, {0}}, 0, 0 }, - { "dbdr20", 2068, {0, {0}}, 0, 0 }, - { "dbdr21", 2069, {0, {0}}, 0, 0 }, - { "dbdr22", 2070, {0, {0}}, 0, 0 }, - { "dbdr23", 2071, {0, {0}}, 0, 0 }, - { "dbdr30", 2072, {0, {0}}, 0, 0 }, - { "dbdr31", 2073, {0, {0}}, 0, 0 }, - { "dbdr32", 2074, {0, {0}}, 0, 0 }, - { "dbdr33", 2075, {0, {0}}, 0, 0 }, - { "dbmr00", 2076, {0, {0}}, 0, 0 }, - { "dbmr01", 2077, {0, {0}}, 0, 0 }, - { "dbmr02", 2078, {0, {0}}, 0, 0 }, - { "dbmr03", 2079, {0, {0}}, 0, 0 }, - { "dbmr10", 2080, {0, {0}}, 0, 0 }, - { "dbmr11", 2081, {0, {0}}, 0, 0 }, - { "dbmr12", 2082, {0, {0}}, 0, 0 }, - { "dbmr13", 2083, {0, {0}}, 0, 0 }, - { "dbmr20", 2084, {0, {0}}, 0, 0 }, - { "dbmr21", 2085, {0, {0}}, 0, 0 }, - { "dbmr22", 2086, {0, {0}}, 0, 0 }, - { "dbmr23", 2087, {0, {0}}, 0, 0 }, - { "dbmr30", 2088, {0, {0}}, 0, 0 }, - { "dbmr31", 2089, {0, {0}}, 0, 0 }, - { "dbmr32", 2090, {0, {0}}, 0, 0 }, - { "dbmr33", 2091, {0, {0}}, 0, 0 }, - { "cpcfr", 2092, {0, {0}}, 0, 0 }, - { "cpcr", 2093, {0, {0}}, 0, 0 }, - { "cpsr", 2094, {0, {0}}, 0, 0 }, - { "cpesr0", 2096, {0, {0}}, 0, 0 }, - { "cpesr1", 2097, {0, {0}}, 0, 0 }, - { "cpemr0", 2098, {0, {0}}, 0, 0 }, - { "cpemr1", 2099, {0, {0}}, 0, 0 }, - { "ihsr8", 3848, {0, {0}}, 0, 0 } + { "psr", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "pcsr", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "bpcsr", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "tbr", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "bpsr", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr0", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr1", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr2", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr3", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr4", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr5", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr6", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr7", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr8", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr9", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr10", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr11", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr12", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr13", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr14", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr15", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr16", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr17", 33, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr18", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr19", 35, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr20", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr21", 37, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr22", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr23", 39, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr24", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr25", 41, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr26", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr27", 43, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr28", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr29", 45, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr30", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr31", 47, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr32", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr33", 49, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr34", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr35", 51, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr36", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr37", 53, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr38", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr39", 55, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr40", 56, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr41", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr42", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr43", 59, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr44", 60, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr45", 61, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr46", 62, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr47", 63, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr48", 64, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr49", 65, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr50", 66, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr51", 67, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr52", 68, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr53", 69, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr54", 70, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr55", 71, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr56", 72, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr57", 73, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr58", 74, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr59", 75, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr60", 76, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr61", 77, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr62", 78, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr63", 79, {0, {{{0, 0}}}}, 0, 0 }, + { "ccr", 256, {0, {{{0, 0}}}}, 0, 0 }, + { "cccr", 263, {0, {{{0, 0}}}}, 0, 0 }, + { "lr", 272, {0, {{{0, 0}}}}, 0, 0 }, + { "lcr", 273, {0, {{{0, 0}}}}, 0, 0 }, + { "iacc0h", 280, {0, {{{0, 0}}}}, 0, 0 }, + { "iacc0l", 281, {0, {{{0, 0}}}}, 0, 0 }, + { "isr", 288, {0, {{{0, 0}}}}, 0, 0 }, + { "neear0", 352, {0, {{{0, 0}}}}, 0, 0 }, + { "neear1", 353, {0, {{{0, 0}}}}, 0, 0 }, + { "neear2", 354, {0, {{{0, 0}}}}, 0, 0 }, + { "neear3", 355, {0, {{{0, 0}}}}, 0, 0 }, + { "neear4", 356, {0, {{{0, 0}}}}, 0, 0 }, + { "neear5", 357, {0, {{{0, 0}}}}, 0, 0 }, + { "neear6", 358, {0, {{{0, 0}}}}, 0, 0 }, + { "neear7", 359, {0, {{{0, 0}}}}, 0, 0 }, + { "neear8", 360, {0, {{{0, 0}}}}, 0, 0 }, + { "neear9", 361, {0, {{{0, 0}}}}, 0, 0 }, + { "neear10", 362, {0, {{{0, 0}}}}, 0, 0 }, + { "neear11", 363, {0, {{{0, 0}}}}, 0, 0 }, + { "neear12", 364, {0, {{{0, 0}}}}, 0, 0 }, + { "neear13", 365, {0, {{{0, 0}}}}, 0, 0 }, + { "neear14", 366, {0, {{{0, 0}}}}, 0, 0 }, + { "neear15", 367, {0, {{{0, 0}}}}, 0, 0 }, + { "neear16", 368, {0, {{{0, 0}}}}, 0, 0 }, + { "neear17", 369, {0, {{{0, 0}}}}, 0, 0 }, + { "neear18", 370, {0, {{{0, 0}}}}, 0, 0 }, + { "neear19", 371, {0, {{{0, 0}}}}, 0, 0 }, + { "neear20", 372, {0, {{{0, 0}}}}, 0, 0 }, + { "neear21", 373, {0, {{{0, 0}}}}, 0, 0 }, + { "neear22", 374, {0, {{{0, 0}}}}, 0, 0 }, + { "neear23", 375, {0, {{{0, 0}}}}, 0, 0 }, + { "neear24", 376, {0, {{{0, 0}}}}, 0, 0 }, + { "neear25", 377, {0, {{{0, 0}}}}, 0, 0 }, + { "neear26", 378, {0, {{{0, 0}}}}, 0, 0 }, + { "neear27", 379, {0, {{{0, 0}}}}, 0, 0 }, + { "neear28", 380, {0, {{{0, 0}}}}, 0, 0 }, + { "neear29", 381, {0, {{{0, 0}}}}, 0, 0 }, + { "neear30", 382, {0, {{{0, 0}}}}, 0, 0 }, + { "neear31", 383, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr0", 384, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr1", 385, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr2", 386, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr3", 387, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr4", 388, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr5", 389, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr6", 390, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr7", 391, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr8", 392, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr9", 393, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr10", 394, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr11", 395, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr12", 396, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr13", 397, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr14", 398, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr15", 399, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr16", 400, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr17", 401, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr18", 402, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr19", 403, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr20", 404, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr21", 405, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr22", 406, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr23", 407, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr24", 408, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr25", 409, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr26", 410, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr27", 411, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr28", 412, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr29", 413, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr30", 414, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr31", 415, {0, {{{0, 0}}}}, 0, 0 }, + { "necr", 416, {0, {{{0, 0}}}}, 0, 0 }, + { "gner0", 432, {0, {{{0, 0}}}}, 0, 0 }, + { "gner1", 433, {0, {{{0, 0}}}}, 0, 0 }, + { "fner0", 434, {0, {{{0, 0}}}}, 0, 0 }, + { "fner1", 435, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr0", 512, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr1", 513, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr2", 514, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr3", 515, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr4", 516, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr5", 517, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr6", 518, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr7", 519, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr8", 520, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr9", 521, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr10", 522, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr11", 523, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr12", 524, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr13", 525, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr14", 526, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr15", 527, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr16", 528, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr17", 529, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr18", 530, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr19", 531, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr20", 532, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr21", 533, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr22", 534, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr23", 535, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr24", 536, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr25", 537, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr26", 538, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr27", 539, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr28", 540, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr29", 541, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr30", 542, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr31", 543, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr32", 544, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr33", 545, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr34", 546, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr35", 547, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr36", 548, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr37", 549, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr38", 550, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr39", 551, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr40", 552, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr41", 553, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr42", 554, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr43", 555, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr44", 556, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr45", 557, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr46", 558, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr47", 559, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr48", 560, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr49", 561, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr50", 562, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr51", 563, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr52", 564, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr53", 565, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr54", 566, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr55", 567, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr56", 568, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr57", 569, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr58", 570, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr59", 571, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr60", 572, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr61", 573, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr62", 574, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr63", 575, {0, {{{0, 0}}}}, 0, 0 }, + { "esr0", 576, {0, {{{0, 0}}}}, 0, 0 }, + { "esr1", 577, {0, {{{0, 0}}}}, 0, 0 }, + { "esr2", 578, {0, {{{0, 0}}}}, 0, 0 }, + { "esr3", 579, {0, {{{0, 0}}}}, 0, 0 }, + { "esr4", 580, {0, {{{0, 0}}}}, 0, 0 }, + { "esr5", 581, {0, {{{0, 0}}}}, 0, 0 }, + { "esr6", 582, {0, {{{0, 0}}}}, 0, 0 }, + { "esr7", 583, {0, {{{0, 0}}}}, 0, 0 }, + { "esr8", 584, {0, {{{0, 0}}}}, 0, 0 }, + { "esr9", 585, {0, {{{0, 0}}}}, 0, 0 }, + { "esr10", 586, {0, {{{0, 0}}}}, 0, 0 }, + { "esr11", 587, {0, {{{0, 0}}}}, 0, 0 }, + { "esr12", 588, {0, {{{0, 0}}}}, 0, 0 }, + { "esr13", 589, {0, {{{0, 0}}}}, 0, 0 }, + { "esr14", 590, {0, {{{0, 0}}}}, 0, 0 }, + { "esr15", 591, {0, {{{0, 0}}}}, 0, 0 }, + { "esr16", 592, {0, {{{0, 0}}}}, 0, 0 }, + { "esr17", 593, {0, {{{0, 0}}}}, 0, 0 }, + { "esr18", 594, {0, {{{0, 0}}}}, 0, 0 }, + { "esr19", 595, {0, {{{0, 0}}}}, 0, 0 }, + { "esr20", 596, {0, {{{0, 0}}}}, 0, 0 }, + { "esr21", 597, {0, {{{0, 0}}}}, 0, 0 }, + { "esr22", 598, {0, {{{0, 0}}}}, 0, 0 }, + { "esr23", 599, {0, {{{0, 0}}}}, 0, 0 }, + { "esr24", 600, {0, {{{0, 0}}}}, 0, 0 }, + { "esr25", 601, {0, {{{0, 0}}}}, 0, 0 }, + { "esr26", 602, {0, {{{0, 0}}}}, 0, 0 }, + { "esr27", 603, {0, {{{0, 0}}}}, 0, 0 }, + { "esr28", 604, {0, {{{0, 0}}}}, 0, 0 }, + { "esr29", 605, {0, {{{0, 0}}}}, 0, 0 }, + { "esr30", 606, {0, {{{0, 0}}}}, 0, 0 }, + { "esr31", 607, {0, {{{0, 0}}}}, 0, 0 }, + { "esr32", 608, {0, {{{0, 0}}}}, 0, 0 }, + { "esr33", 609, {0, {{{0, 0}}}}, 0, 0 }, + { "esr34", 610, {0, {{{0, 0}}}}, 0, 0 }, + { "esr35", 611, {0, {{{0, 0}}}}, 0, 0 }, + { "esr36", 612, {0, {{{0, 0}}}}, 0, 0 }, + { "esr37", 613, {0, {{{0, 0}}}}, 0, 0 }, + { "esr38", 614, {0, {{{0, 0}}}}, 0, 0 }, + { "esr39", 615, {0, {{{0, 0}}}}, 0, 0 }, + { "esr40", 616, {0, {{{0, 0}}}}, 0, 0 }, + { "esr41", 617, {0, {{{0, 0}}}}, 0, 0 }, + { "esr42", 618, {0, {{{0, 0}}}}, 0, 0 }, + { "esr43", 619, {0, {{{0, 0}}}}, 0, 0 }, + { "esr44", 620, {0, {{{0, 0}}}}, 0, 0 }, + { "esr45", 621, {0, {{{0, 0}}}}, 0, 0 }, + { "esr46", 622, {0, {{{0, 0}}}}, 0, 0 }, + { "esr47", 623, {0, {{{0, 0}}}}, 0, 0 }, + { "esr48", 624, {0, {{{0, 0}}}}, 0, 0 }, + { "esr49", 625, {0, {{{0, 0}}}}, 0, 0 }, + { "esr50", 626, {0, {{{0, 0}}}}, 0, 0 }, + { "esr51", 627, {0, {{{0, 0}}}}, 0, 0 }, + { "esr52", 628, {0, {{{0, 0}}}}, 0, 0 }, + { "esr53", 629, {0, {{{0, 0}}}}, 0, 0 }, + { "esr54", 630, {0, {{{0, 0}}}}, 0, 0 }, + { "esr55", 631, {0, {{{0, 0}}}}, 0, 0 }, + { "esr56", 632, {0, {{{0, 0}}}}, 0, 0 }, + { "esr57", 633, {0, {{{0, 0}}}}, 0, 0 }, + { "esr58", 634, {0, {{{0, 0}}}}, 0, 0 }, + { "esr59", 635, {0, {{{0, 0}}}}, 0, 0 }, + { "esr60", 636, {0, {{{0, 0}}}}, 0, 0 }, + { "esr61", 637, {0, {{{0, 0}}}}, 0, 0 }, + { "esr62", 638, {0, {{{0, 0}}}}, 0, 0 }, + { "esr63", 639, {0, {{{0, 0}}}}, 0, 0 }, + { "eir0", 640, {0, {{{0, 0}}}}, 0, 0 }, + { "eir1", 641, {0, {{{0, 0}}}}, 0, 0 }, + { "eir2", 642, {0, {{{0, 0}}}}, 0, 0 }, + { "eir3", 643, {0, {{{0, 0}}}}, 0, 0 }, + { "eir4", 644, {0, {{{0, 0}}}}, 0, 0 }, + { "eir5", 645, {0, {{{0, 0}}}}, 0, 0 }, + { "eir6", 646, {0, {{{0, 0}}}}, 0, 0 }, + { "eir7", 647, {0, {{{0, 0}}}}, 0, 0 }, + { "eir8", 648, {0, {{{0, 0}}}}, 0, 0 }, + { "eir9", 649, {0, {{{0, 0}}}}, 0, 0 }, + { "eir10", 650, {0, {{{0, 0}}}}, 0, 0 }, + { "eir11", 651, {0, {{{0, 0}}}}, 0, 0 }, + { "eir12", 652, {0, {{{0, 0}}}}, 0, 0 }, + { "eir13", 653, {0, {{{0, 0}}}}, 0, 0 }, + { "eir14", 654, {0, {{{0, 0}}}}, 0, 0 }, + { "eir15", 655, {0, {{{0, 0}}}}, 0, 0 }, + { "eir16", 656, {0, {{{0, 0}}}}, 0, 0 }, + { "eir17", 657, {0, {{{0, 0}}}}, 0, 0 }, + { "eir18", 658, {0, {{{0, 0}}}}, 0, 0 }, + { "eir19", 659, {0, {{{0, 0}}}}, 0, 0 }, + { "eir20", 660, {0, {{{0, 0}}}}, 0, 0 }, + { "eir21", 661, {0, {{{0, 0}}}}, 0, 0 }, + { "eir22", 662, {0, {{{0, 0}}}}, 0, 0 }, + { "eir23", 663, {0, {{{0, 0}}}}, 0, 0 }, + { "eir24", 664, {0, {{{0, 0}}}}, 0, 0 }, + { "eir25", 665, {0, {{{0, 0}}}}, 0, 0 }, + { "eir26", 666, {0, {{{0, 0}}}}, 0, 0 }, + { "eir27", 667, {0, {{{0, 0}}}}, 0, 0 }, + { "eir28", 668, {0, {{{0, 0}}}}, 0, 0 }, + { "eir29", 669, {0, {{{0, 0}}}}, 0, 0 }, + { "eir30", 670, {0, {{{0, 0}}}}, 0, 0 }, + { "eir31", 671, {0, {{{0, 0}}}}, 0, 0 }, + { "esfr0", 672, {0, {{{0, 0}}}}, 0, 0 }, + { "esfr1", 673, {0, {{{0, 0}}}}, 0, 0 }, + { "sr0", 768, {0, {{{0, 0}}}}, 0, 0 }, + { "sr1", 769, {0, {{{0, 0}}}}, 0, 0 }, + { "sr2", 770, {0, {{{0, 0}}}}, 0, 0 }, + { "sr3", 771, {0, {{{0, 0}}}}, 0, 0 }, + { "scr0", 832, {0, {{{0, 0}}}}, 0, 0 }, + { "scr1", 833, {0, {{{0, 0}}}}, 0, 0 }, + { "scr2", 834, {0, {{{0, 0}}}}, 0, 0 }, + { "scr3", 835, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr0", 1024, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr1", 1025, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr2", 1026, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr3", 1027, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr4", 1028, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr5", 1029, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr6", 1030, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr7", 1031, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr8", 1032, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr9", 1033, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr10", 1034, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr11", 1035, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr12", 1036, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr13", 1037, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr14", 1038, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr15", 1039, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr16", 1040, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr17", 1041, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr18", 1042, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr19", 1043, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr20", 1044, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr21", 1045, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr22", 1046, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr23", 1047, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr24", 1048, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr25", 1049, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr26", 1050, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr27", 1051, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr28", 1052, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr29", 1053, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr30", 1054, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr31", 1055, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr32", 1056, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr33", 1057, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr34", 1058, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr35", 1059, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr36", 1060, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr37", 1061, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr38", 1062, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr39", 1063, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr40", 1064, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr41", 1065, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr42", 1066, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr43", 1067, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr44", 1068, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr45", 1069, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr46", 1070, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr47", 1071, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr48", 1072, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr49", 1073, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr50", 1074, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr51", 1075, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr52", 1076, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr53", 1077, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr54", 1078, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr55", 1079, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr56", 1080, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr57", 1081, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr58", 1082, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr59", 1083, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr60", 1084, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr61", 1085, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr62", 1086, {0, {{{0, 0}}}}, 0, 0 }, + { "fsr63", 1087, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop0", 1088, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop1", 1090, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop2", 1092, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop3", 1094, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop4", 1096, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop5", 1098, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop6", 1100, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop7", 1102, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop8", 1104, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop9", 1106, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop10", 1108, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop11", 1110, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop12", 1112, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop13", 1114, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop14", 1116, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop15", 1118, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop16", 1120, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop17", 1122, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop18", 1124, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop19", 1126, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop20", 1128, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop21", 1130, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop22", 1132, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop23", 1134, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop24", 1136, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop25", 1138, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop26", 1140, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop27", 1142, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop28", 1144, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop29", 1146, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop30", 1148, {0, {{{0, 0}}}}, 0, 0 }, + { "fqop31", 1150, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst0", 1089, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst1", 1091, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst2", 1093, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst3", 1095, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst4", 1097, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst5", 1099, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst6", 1101, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst7", 1103, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst8", 1105, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst9", 1107, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst10", 1109, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst11", 1111, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst12", 1113, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst13", 1115, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst14", 1117, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst15", 1119, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst16", 1121, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst17", 1123, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst18", 1125, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst19", 1127, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst20", 1129, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst21", 1131, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst22", 1133, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst23", 1135, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst24", 1137, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst25", 1139, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst26", 1141, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst27", 1143, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst28", 1145, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst29", 1147, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst30", 1149, {0, {{{0, 0}}}}, 0, 0 }, + { "fqst31", 1151, {0, {{{0, 0}}}}, 0, 0 }, + { "mcilr0", 1272, {0, {{{0, 0}}}}, 0, 0 }, + { "mcilr1", 1273, {0, {{{0, 0}}}}, 0, 0 }, + { "msr0", 1280, {0, {{{0, 0}}}}, 0, 0 }, + { "msr1", 1281, {0, {{{0, 0}}}}, 0, 0 }, + { "msr2", 1282, {0, {{{0, 0}}}}, 0, 0 }, + { "msr3", 1283, {0, {{{0, 0}}}}, 0, 0 }, + { "msr4", 1284, {0, {{{0, 0}}}}, 0, 0 }, + { "msr5", 1285, {0, {{{0, 0}}}}, 0, 0 }, + { "msr6", 1286, {0, {{{0, 0}}}}, 0, 0 }, + { "msr7", 1287, {0, {{{0, 0}}}}, 0, 0 }, + { "msr8", 1288, {0, {{{0, 0}}}}, 0, 0 }, + { "msr9", 1289, {0, {{{0, 0}}}}, 0, 0 }, + { "msr10", 1290, {0, {{{0, 0}}}}, 0, 0 }, + { "msr11", 1291, {0, {{{0, 0}}}}, 0, 0 }, + { "msr12", 1292, {0, {{{0, 0}}}}, 0, 0 }, + { "msr13", 1293, {0, {{{0, 0}}}}, 0, 0 }, + { "msr14", 1294, {0, {{{0, 0}}}}, 0, 0 }, + { "msr15", 1295, {0, {{{0, 0}}}}, 0, 0 }, + { "msr16", 1296, {0, {{{0, 0}}}}, 0, 0 }, + { "msr17", 1297, {0, {{{0, 0}}}}, 0, 0 }, + { "msr18", 1298, {0, {{{0, 0}}}}, 0, 0 }, + { "msr19", 1299, {0, {{{0, 0}}}}, 0, 0 }, + { "msr20", 1300, {0, {{{0, 0}}}}, 0, 0 }, + { "msr21", 1301, {0, {{{0, 0}}}}, 0, 0 }, + { "msr22", 1302, {0, {{{0, 0}}}}, 0, 0 }, + { "msr23", 1303, {0, {{{0, 0}}}}, 0, 0 }, + { "msr24", 1304, {0, {{{0, 0}}}}, 0, 0 }, + { "msr25", 1305, {0, {{{0, 0}}}}, 0, 0 }, + { "msr26", 1306, {0, {{{0, 0}}}}, 0, 0 }, + { "msr27", 1307, {0, {{{0, 0}}}}, 0, 0 }, + { "msr28", 1308, {0, {{{0, 0}}}}, 0, 0 }, + { "msr29", 1309, {0, {{{0, 0}}}}, 0, 0 }, + { "msr30", 1310, {0, {{{0, 0}}}}, 0, 0 }, + { "msr31", 1311, {0, {{{0, 0}}}}, 0, 0 }, + { "msr32", 1312, {0, {{{0, 0}}}}, 0, 0 }, + { "msr33", 1313, {0, {{{0, 0}}}}, 0, 0 }, + { "msr34", 1314, {0, {{{0, 0}}}}, 0, 0 }, + { "msr35", 1315, {0, {{{0, 0}}}}, 0, 0 }, + { "msr36", 1316, {0, {{{0, 0}}}}, 0, 0 }, + { "msr37", 1317, {0, {{{0, 0}}}}, 0, 0 }, + { "msr38", 1318, {0, {{{0, 0}}}}, 0, 0 }, + { "msr39", 1319, {0, {{{0, 0}}}}, 0, 0 }, + { "msr40", 1320, {0, {{{0, 0}}}}, 0, 0 }, + { "msr41", 1321, {0, {{{0, 0}}}}, 0, 0 }, + { "msr42", 1322, {0, {{{0, 0}}}}, 0, 0 }, + { "msr43", 1323, {0, {{{0, 0}}}}, 0, 0 }, + { "msr44", 1324, {0, {{{0, 0}}}}, 0, 0 }, + { "msr45", 1325, {0, {{{0, 0}}}}, 0, 0 }, + { "msr46", 1326, {0, {{{0, 0}}}}, 0, 0 }, + { "msr47", 1327, {0, {{{0, 0}}}}, 0, 0 }, + { "msr48", 1328, {0, {{{0, 0}}}}, 0, 0 }, + { "msr49", 1329, {0, {{{0, 0}}}}, 0, 0 }, + { "msr50", 1330, {0, {{{0, 0}}}}, 0, 0 }, + { "msr51", 1331, {0, {{{0, 0}}}}, 0, 0 }, + { "msr52", 1332, {0, {{{0, 0}}}}, 0, 0 }, + { "msr53", 1333, {0, {{{0, 0}}}}, 0, 0 }, + { "msr54", 1334, {0, {{{0, 0}}}}, 0, 0 }, + { "msr55", 1335, {0, {{{0, 0}}}}, 0, 0 }, + { "msr56", 1336, {0, {{{0, 0}}}}, 0, 0 }, + { "msr57", 1337, {0, {{{0, 0}}}}, 0, 0 }, + { "msr58", 1338, {0, {{{0, 0}}}}, 0, 0 }, + { "msr59", 1339, {0, {{{0, 0}}}}, 0, 0 }, + { "msr60", 1340, {0, {{{0, 0}}}}, 0, 0 }, + { "msr61", 1341, {0, {{{0, 0}}}}, 0, 0 }, + { "msr62", 1342, {0, {{{0, 0}}}}, 0, 0 }, + { "msr63", 1343, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop0", 1344, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop1", 1346, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop2", 1348, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop3", 1350, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop4", 1352, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop5", 1354, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop6", 1356, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop7", 1358, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop8", 1360, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop9", 1362, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop10", 1364, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop11", 1366, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop12", 1368, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop13", 1370, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop14", 1372, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop15", 1374, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop16", 1376, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop17", 1378, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop18", 1380, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop19", 1382, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop20", 1384, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop21", 1386, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop22", 1388, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop23", 1390, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop24", 1392, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop25", 1394, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop26", 1396, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop27", 1398, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop28", 1400, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop29", 1402, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop30", 1404, {0, {{{0, 0}}}}, 0, 0 }, + { "mqop31", 1406, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst0", 1345, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst1", 1347, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst2", 1349, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst3", 1351, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst4", 1353, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst5", 1355, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst6", 1357, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst7", 1359, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst8", 1361, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst9", 1363, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst10", 1365, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst11", 1367, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst12", 1369, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst13", 1371, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst14", 1373, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst15", 1375, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst16", 1377, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst17", 1379, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst18", 1381, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst19", 1383, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst20", 1385, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst21", 1387, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst22", 1389, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst23", 1391, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst24", 1393, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst25", 1395, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst26", 1397, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst27", 1399, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst28", 1401, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst29", 1403, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst30", 1405, {0, {{{0, 0}}}}, 0, 0 }, + { "mqst31", 1407, {0, {{{0, 0}}}}, 0, 0 }, + { "ear0", 1536, {0, {{{0, 0}}}}, 0, 0 }, + { "ear1", 1537, {0, {{{0, 0}}}}, 0, 0 }, + { "ear2", 1538, {0, {{{0, 0}}}}, 0, 0 }, + { "ear3", 1539, {0, {{{0, 0}}}}, 0, 0 }, + { "ear4", 1540, {0, {{{0, 0}}}}, 0, 0 }, + { "ear5", 1541, {0, {{{0, 0}}}}, 0, 0 }, + { "ear6", 1542, {0, {{{0, 0}}}}, 0, 0 }, + { "ear7", 1543, {0, {{{0, 0}}}}, 0, 0 }, + { "ear8", 1544, {0, {{{0, 0}}}}, 0, 0 }, + { "ear9", 1545, {0, {{{0, 0}}}}, 0, 0 }, + { "ear10", 1546, {0, {{{0, 0}}}}, 0, 0 }, + { "ear11", 1547, {0, {{{0, 0}}}}, 0, 0 }, + { "ear12", 1548, {0, {{{0, 0}}}}, 0, 0 }, + { "ear13", 1549, {0, {{{0, 0}}}}, 0, 0 }, + { "ear14", 1550, {0, {{{0, 0}}}}, 0, 0 }, + { "ear15", 1551, {0, {{{0, 0}}}}, 0, 0 }, + { "ear16", 1552, {0, {{{0, 0}}}}, 0, 0 }, + { "ear17", 1553, {0, {{{0, 0}}}}, 0, 0 }, + { "ear18", 1554, {0, {{{0, 0}}}}, 0, 0 }, + { "ear19", 1555, {0, {{{0, 0}}}}, 0, 0 }, + { "ear20", 1556, {0, {{{0, 0}}}}, 0, 0 }, + { "ear21", 1557, {0, {{{0, 0}}}}, 0, 0 }, + { "ear22", 1558, {0, {{{0, 0}}}}, 0, 0 }, + { "ear23", 1559, {0, {{{0, 0}}}}, 0, 0 }, + { "ear24", 1560, {0, {{{0, 0}}}}, 0, 0 }, + { "ear25", 1561, {0, {{{0, 0}}}}, 0, 0 }, + { "ear26", 1562, {0, {{{0, 0}}}}, 0, 0 }, + { "ear27", 1563, {0, {{{0, 0}}}}, 0, 0 }, + { "ear28", 1564, {0, {{{0, 0}}}}, 0, 0 }, + { "ear29", 1565, {0, {{{0, 0}}}}, 0, 0 }, + { "ear30", 1566, {0, {{{0, 0}}}}, 0, 0 }, + { "ear31", 1567, {0, {{{0, 0}}}}, 0, 0 }, + { "ear32", 1568, {0, {{{0, 0}}}}, 0, 0 }, + { "ear33", 1569, {0, {{{0, 0}}}}, 0, 0 }, + { "ear34", 1570, {0, {{{0, 0}}}}, 0, 0 }, + { "ear35", 1571, {0, {{{0, 0}}}}, 0, 0 }, + { "ear36", 1572, {0, {{{0, 0}}}}, 0, 0 }, + { "ear37", 1573, {0, {{{0, 0}}}}, 0, 0 }, + { "ear38", 1574, {0, {{{0, 0}}}}, 0, 0 }, + { "ear39", 1575, {0, {{{0, 0}}}}, 0, 0 }, + { "ear40", 1576, {0, {{{0, 0}}}}, 0, 0 }, + { "ear41", 1577, {0, {{{0, 0}}}}, 0, 0 }, + { "ear42", 1578, {0, {{{0, 0}}}}, 0, 0 }, + { "ear43", 1579, {0, {{{0, 0}}}}, 0, 0 }, + { "ear44", 1580, {0, {{{0, 0}}}}, 0, 0 }, + { "ear45", 1581, {0, {{{0, 0}}}}, 0, 0 }, + { "ear46", 1582, {0, {{{0, 0}}}}, 0, 0 }, + { "ear47", 1583, {0, {{{0, 0}}}}, 0, 0 }, + { "ear48", 1584, {0, {{{0, 0}}}}, 0, 0 }, + { "ear49", 1585, {0, {{{0, 0}}}}, 0, 0 }, + { "ear50", 1586, {0, {{{0, 0}}}}, 0, 0 }, + { "ear51", 1587, {0, {{{0, 0}}}}, 0, 0 }, + { "ear52", 1588, {0, {{{0, 0}}}}, 0, 0 }, + { "ear53", 1589, {0, {{{0, 0}}}}, 0, 0 }, + { "ear54", 1590, {0, {{{0, 0}}}}, 0, 0 }, + { "ear55", 1591, {0, {{{0, 0}}}}, 0, 0 }, + { "ear56", 1592, {0, {{{0, 0}}}}, 0, 0 }, + { "ear57", 1593, {0, {{{0, 0}}}}, 0, 0 }, + { "ear58", 1594, {0, {{{0, 0}}}}, 0, 0 }, + { "ear59", 1595, {0, {{{0, 0}}}}, 0, 0 }, + { "ear60", 1596, {0, {{{0, 0}}}}, 0, 0 }, + { "ear61", 1597, {0, {{{0, 0}}}}, 0, 0 }, + { "ear62", 1598, {0, {{{0, 0}}}}, 0, 0 }, + { "ear63", 1599, {0, {{{0, 0}}}}, 0, 0 }, + { "edr0", 1600, {0, {{{0, 0}}}}, 0, 0 }, + { "edr1", 1601, {0, {{{0, 0}}}}, 0, 0 }, + { "edr2", 1602, {0, {{{0, 0}}}}, 0, 0 }, + { "edr3", 1603, {0, {{{0, 0}}}}, 0, 0 }, + { "edr4", 1604, {0, {{{0, 0}}}}, 0, 0 }, + { "edr5", 1605, {0, {{{0, 0}}}}, 0, 0 }, + { "edr6", 1606, {0, {{{0, 0}}}}, 0, 0 }, + { "edr7", 1607, {0, {{{0, 0}}}}, 0, 0 }, + { "edr8", 1608, {0, {{{0, 0}}}}, 0, 0 }, + { "edr9", 1609, {0, {{{0, 0}}}}, 0, 0 }, + { "edr10", 1610, {0, {{{0, 0}}}}, 0, 0 }, + { "edr11", 1611, {0, {{{0, 0}}}}, 0, 0 }, + { "edr12", 1612, {0, {{{0, 0}}}}, 0, 0 }, + { "edr13", 1613, {0, {{{0, 0}}}}, 0, 0 }, + { "edr14", 1614, {0, {{{0, 0}}}}, 0, 0 }, + { "edr15", 1615, {0, {{{0, 0}}}}, 0, 0 }, + { "edr16", 1616, {0, {{{0, 0}}}}, 0, 0 }, + { "edr17", 1617, {0, {{{0, 0}}}}, 0, 0 }, + { "edr18", 1618, {0, {{{0, 0}}}}, 0, 0 }, + { "edr19", 1619, {0, {{{0, 0}}}}, 0, 0 }, + { "edr20", 1620, {0, {{{0, 0}}}}, 0, 0 }, + { "edr21", 1621, {0, {{{0, 0}}}}, 0, 0 }, + { "edr22", 1622, {0, {{{0, 0}}}}, 0, 0 }, + { "edr23", 1623, {0, {{{0, 0}}}}, 0, 0 }, + { "edr24", 1624, {0, {{{0, 0}}}}, 0, 0 }, + { "edr25", 1625, {0, {{{0, 0}}}}, 0, 0 }, + { "edr26", 1626, {0, {{{0, 0}}}}, 0, 0 }, + { "edr27", 1627, {0, {{{0, 0}}}}, 0, 0 }, + { "edr28", 1628, {0, {{{0, 0}}}}, 0, 0 }, + { "edr29", 1629, {0, {{{0, 0}}}}, 0, 0 }, + { "edr30", 1630, {0, {{{0, 0}}}}, 0, 0 }, + { "edr31", 1631, {0, {{{0, 0}}}}, 0, 0 }, + { "edr32", 1632, {0, {{{0, 0}}}}, 0, 0 }, + { "edr33", 1636, {0, {{{0, 0}}}}, 0, 0 }, + { "edr34", 1634, {0, {{{0, 0}}}}, 0, 0 }, + { "edr35", 1635, {0, {{{0, 0}}}}, 0, 0 }, + { "edr36", 1636, {0, {{{0, 0}}}}, 0, 0 }, + { "edr37", 1637, {0, {{{0, 0}}}}, 0, 0 }, + { "edr38", 1638, {0, {{{0, 0}}}}, 0, 0 }, + { "edr39", 1639, {0, {{{0, 0}}}}, 0, 0 }, + { "edr40", 1640, {0, {{{0, 0}}}}, 0, 0 }, + { "edr41", 1641, {0, {{{0, 0}}}}, 0, 0 }, + { "edr42", 1642, {0, {{{0, 0}}}}, 0, 0 }, + { "edr43", 1643, {0, {{{0, 0}}}}, 0, 0 }, + { "edr44", 1644, {0, {{{0, 0}}}}, 0, 0 }, + { "edr45", 1645, {0, {{{0, 0}}}}, 0, 0 }, + { "edr46", 1646, {0, {{{0, 0}}}}, 0, 0 }, + { "edr47", 1647, {0, {{{0, 0}}}}, 0, 0 }, + { "edr48", 1648, {0, {{{0, 0}}}}, 0, 0 }, + { "edr49", 1649, {0, {{{0, 0}}}}, 0, 0 }, + { "edr50", 1650, {0, {{{0, 0}}}}, 0, 0 }, + { "edr51", 1651, {0, {{{0, 0}}}}, 0, 0 }, + { "edr52", 1652, {0, {{{0, 0}}}}, 0, 0 }, + { "edr53", 1653, {0, {{{0, 0}}}}, 0, 0 }, + { "edr54", 1654, {0, {{{0, 0}}}}, 0, 0 }, + { "edr55", 1655, {0, {{{0, 0}}}}, 0, 0 }, + { "edr56", 1656, {0, {{{0, 0}}}}, 0, 0 }, + { "edr57", 1657, {0, {{{0, 0}}}}, 0, 0 }, + { "edr58", 1658, {0, {{{0, 0}}}}, 0, 0 }, + { "edr59", 1659, {0, {{{0, 0}}}}, 0, 0 }, + { "edr60", 1660, {0, {{{0, 0}}}}, 0, 0 }, + { "edr61", 1661, {0, {{{0, 0}}}}, 0, 0 }, + { "edr62", 1662, {0, {{{0, 0}}}}, 0, 0 }, + { "edr63", 1663, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr0", 1664, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr1", 1665, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr2", 1666, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr3", 1667, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr4", 1668, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr5", 1669, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr6", 1670, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr7", 1671, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr8", 1672, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr9", 1673, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr10", 1674, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr11", 1675, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr12", 1676, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr13", 1677, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr14", 1678, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr15", 1679, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr16", 1680, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr17", 1681, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr18", 1682, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr19", 1683, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr20", 1684, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr21", 1685, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr22", 1686, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr23", 1687, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr24", 1688, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr25", 1689, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr26", 1690, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr27", 1691, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr28", 1692, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr29", 1693, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr30", 1694, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr31", 1695, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr32", 1696, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr33", 1697, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr34", 1698, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr35", 1699, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr36", 1700, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr37", 1701, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr38", 1702, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr39", 1703, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr40", 1704, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr41", 1705, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr42", 1706, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr43", 1707, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr44", 1708, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr45", 1709, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr46", 1710, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr47", 1711, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr48", 1712, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr49", 1713, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr50", 1714, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr51", 1715, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr52", 1716, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr53", 1717, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr54", 1718, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr55", 1719, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr56", 1720, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr57", 1721, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr58", 1722, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr59", 1723, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr60", 1724, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr61", 1725, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr62", 1726, {0, {{{0, 0}}}}, 0, 0 }, + { "iamlr63", 1727, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr0", 1728, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr1", 1729, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr2", 1730, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr3", 1731, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr4", 1732, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr5", 1733, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr6", 1734, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr7", 1735, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr8", 1736, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr9", 1737, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr10", 1738, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr11", 1739, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr12", 1740, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr13", 1741, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr14", 1742, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr15", 1743, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr16", 1744, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr17", 1745, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr18", 1746, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr19", 1747, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr20", 1748, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr21", 1749, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr22", 1750, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr23", 1751, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr24", 1752, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr25", 1753, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr26", 1754, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr27", 1755, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr28", 1756, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr29", 1757, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr30", 1758, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr31", 1759, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr32", 1760, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr33", 1761, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr34", 1762, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr35", 1763, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr36", 1764, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr37", 1765, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr38", 1766, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr39", 1767, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr40", 1768, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr41", 1769, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr42", 1770, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr43", 1771, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr44", 1772, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr45", 1773, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr46", 1774, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr47", 1775, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr48", 1776, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr49", 1777, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr50", 1778, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr51", 1779, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr52", 1780, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr53", 1781, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr54", 1782, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr55", 1783, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr56", 1784, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr57", 1785, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr58", 1786, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr59", 1787, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr60", 1788, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr61", 1789, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr62", 1790, {0, {{{0, 0}}}}, 0, 0 }, + { "iampr63", 1791, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr0", 1792, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr1", 1793, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr2", 1794, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr3", 1795, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr4", 1796, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr5", 1797, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr6", 1798, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr7", 1799, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr8", 1800, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr9", 1801, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr10", 1802, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr11", 1803, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr12", 1804, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr13", 1805, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr14", 1806, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr15", 1807, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr16", 1808, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr17", 1809, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr18", 1810, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr19", 1811, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr20", 1812, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr21", 1813, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr22", 1814, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr23", 1815, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr24", 1816, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr25", 1817, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr26", 1818, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr27", 1819, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr28", 1820, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr29", 1821, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr30", 1822, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr31", 1823, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr32", 1824, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr33", 1825, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr34", 1826, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr35", 1827, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr36", 1828, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr37", 1829, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr38", 1830, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr39", 1831, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr40", 1832, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr41", 1833, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr42", 1834, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr43", 1835, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr44", 1836, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr45", 1837, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr46", 1838, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr47", 1839, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr48", 1840, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr49", 1841, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr50", 1842, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr51", 1843, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr52", 1844, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr53", 1845, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr54", 1846, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr55", 1847, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr56", 1848, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr57", 1849, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr58", 1850, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr59", 1851, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr60", 1852, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr61", 1853, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr62", 1854, {0, {{{0, 0}}}}, 0, 0 }, + { "damlr63", 1855, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr0", 1856, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr1", 1857, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr2", 1858, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr3", 1859, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr4", 1860, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr5", 1861, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr6", 1862, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr7", 1863, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr8", 1864, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr9", 1865, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr10", 1866, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr11", 1867, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr12", 1868, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr13", 1869, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr14", 1870, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr15", 1871, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr16", 1872, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr17", 1873, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr18", 1874, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr19", 1875, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr20", 1876, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr21", 1877, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr22", 1878, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr23", 1879, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr24", 1880, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr25", 1881, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr26", 1882, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr27", 1883, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr28", 1884, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr29", 1885, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr30", 1886, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr31", 1887, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr32", 1888, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr33", 1889, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr34", 1890, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr35", 1891, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr36", 1892, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr37", 1893, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr38", 1894, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr39", 1895, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr40", 1896, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr41", 1897, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr42", 1898, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr43", 1899, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr44", 1900, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr45", 1901, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr46", 1902, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr47", 1903, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr48", 1904, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr49", 1905, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr50", 1906, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr51", 1907, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr52", 1908, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr53", 1909, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr54", 1910, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr55", 1911, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr56", 1912, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr57", 1913, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr58", 1914, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr59", 1915, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr60", 1916, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr61", 1917, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr62", 1918, {0, {{{0, 0}}}}, 0, 0 }, + { "dampr63", 1919, {0, {{{0, 0}}}}, 0, 0 }, + { "amcr", 1920, {0, {{{0, 0}}}}, 0, 0 }, + { "stbar", 1921, {0, {{{0, 0}}}}, 0, 0 }, + { "mmcr", 1922, {0, {{{0, 0}}}}, 0, 0 }, + { "iamvr1", 1925, {0, {{{0, 0}}}}, 0, 0 }, + { "damvr1", 1927, {0, {{{0, 0}}}}, 0, 0 }, + { "cxnr", 1936, {0, {{{0, 0}}}}, 0, 0 }, + { "ttbr", 1937, {0, {{{0, 0}}}}, 0, 0 }, + { "tplr", 1938, {0, {{{0, 0}}}}, 0, 0 }, + { "tppr", 1939, {0, {{{0, 0}}}}, 0, 0 }, + { "tpxr", 1940, {0, {{{0, 0}}}}, 0, 0 }, + { "timerh", 1952, {0, {{{0, 0}}}}, 0, 0 }, + { "timerl", 1953, {0, {{{0, 0}}}}, 0, 0 }, + { "timerd", 1954, {0, {{{0, 0}}}}, 0, 0 }, + { "dcr", 2048, {0, {{{0, 0}}}}, 0, 0 }, + { "brr", 2049, {0, {{{0, 0}}}}, 0, 0 }, + { "nmar", 2050, {0, {{{0, 0}}}}, 0, 0 }, + { "btbr", 2051, {0, {{{0, 0}}}}, 0, 0 }, + { "ibar0", 2052, {0, {{{0, 0}}}}, 0, 0 }, + { "ibar1", 2053, {0, {{{0, 0}}}}, 0, 0 }, + { "ibar2", 2054, {0, {{{0, 0}}}}, 0, 0 }, + { "ibar3", 2055, {0, {{{0, 0}}}}, 0, 0 }, + { "dbar0", 2056, {0, {{{0, 0}}}}, 0, 0 }, + { "dbar1", 2057, {0, {{{0, 0}}}}, 0, 0 }, + { "dbar2", 2058, {0, {{{0, 0}}}}, 0, 0 }, + { "dbar3", 2059, {0, {{{0, 0}}}}, 0, 0 }, + { "dbdr00", 2060, {0, {{{0, 0}}}}, 0, 0 }, + { "dbdr01", 2061, {0, {{{0, 0}}}}, 0, 0 }, + { "dbdr02", 2062, {0, {{{0, 0}}}}, 0, 0 }, + { "dbdr03", 2063, {0, {{{0, 0}}}}, 0, 0 }, + { "dbdr10", 2064, {0, {{{0, 0}}}}, 0, 0 }, + { "dbdr11", 2065, {0, {{{0, 0}}}}, 0, 0 }, + { "dbdr12", 2066, {0, {{{0, 0}}}}, 0, 0 }, + { "dbdr13", 2067, {0, {{{0, 0}}}}, 0, 0 }, + { "dbdr20", 2068, {0, {{{0, 0}}}}, 0, 0 }, + { "dbdr21", 2069, {0, {{{0, 0}}}}, 0, 0 }, + { "dbdr22", 2070, {0, {{{0, 0}}}}, 0, 0 }, + { "dbdr23", 2071, {0, {{{0, 0}}}}, 0, 0 }, + { "dbdr30", 2072, {0, {{{0, 0}}}}, 0, 0 }, + { "dbdr31", 2073, {0, {{{0, 0}}}}, 0, 0 }, + { "dbdr32", 2074, {0, {{{0, 0}}}}, 0, 0 }, + { "dbdr33", 2075, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr00", 2076, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr01", 2077, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr02", 2078, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr03", 2079, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr10", 2080, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr11", 2081, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr12", 2082, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr13", 2083, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr20", 2084, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr21", 2085, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr22", 2086, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr23", 2087, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr30", 2088, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr31", 2089, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr32", 2090, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr33", 2091, {0, {{{0, 0}}}}, 0, 0 }, + { "cpcfr", 2092, {0, {{{0, 0}}}}, 0, 0 }, + { "cpcr", 2093, {0, {{{0, 0}}}}, 0, 0 }, + { "cpsr", 2094, {0, {{{0, 0}}}}, 0, 0 }, + { "cpesr0", 2096, {0, {{{0, 0}}}}, 0, 0 }, + { "cpesr1", 2097, {0, {{{0, 0}}}}, 0, 0 }, + { "cpemr0", 2098, {0, {{{0, 0}}}}, 0, 0 }, + { "cpemr1", 2099, {0, {{{0, 0}}}}, 0, 0 }, + { "ihsr8", 3848, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD frv_cgen_opval_spr_names = @@ -1556,70 +1556,70 @@ CGEN_KEYWORD frv_cgen_opval_spr_names = static CGEN_KEYWORD_ENTRY frv_cgen_opval_accg_names_entries[] = { - { "accg0", 0, {0, {0}}, 0, 0 }, - { "accg1", 1, {0, {0}}, 0, 0 }, - { "accg2", 2, {0, {0}}, 0, 0 }, - { "accg3", 3, {0, {0}}, 0, 0 }, - { "accg4", 4, {0, {0}}, 0, 0 }, - { "accg5", 5, {0, {0}}, 0, 0 }, - { "accg6", 6, {0, {0}}, 0, 0 }, - { "accg7", 7, {0, {0}}, 0, 0 }, - { "accg8", 8, {0, {0}}, 0, 0 }, - { "accg9", 9, {0, {0}}, 0, 0 }, - { "accg10", 10, {0, {0}}, 0, 0 }, - { "accg11", 11, {0, {0}}, 0, 0 }, - { "accg12", 12, {0, {0}}, 0, 0 }, - { "accg13", 13, {0, {0}}, 0, 0 }, - { "accg14", 14, {0, {0}}, 0, 0 }, - { "accg15", 15, {0, {0}}, 0, 0 }, - { "accg16", 16, {0, {0}}, 0, 0 }, - { "accg17", 17, {0, {0}}, 0, 0 }, - { "accg18", 18, {0, {0}}, 0, 0 }, - { "accg19", 19, {0, {0}}, 0, 0 }, - { "accg20", 20, {0, {0}}, 0, 0 }, - { "accg21", 21, {0, {0}}, 0, 0 }, - { "accg22", 22, {0, {0}}, 0, 0 }, - { "accg23", 23, {0, {0}}, 0, 0 }, - { "accg24", 24, {0, {0}}, 0, 0 }, - { "accg25", 25, {0, {0}}, 0, 0 }, - { "accg26", 26, {0, {0}}, 0, 0 }, - { "accg27", 27, {0, {0}}, 0, 0 }, - { "accg28", 28, {0, {0}}, 0, 0 }, - { "accg29", 29, {0, {0}}, 0, 0 }, - { "accg30", 30, {0, {0}}, 0, 0 }, - { "accg31", 31, {0, {0}}, 0, 0 }, - { "accg32", 32, {0, {0}}, 0, 0 }, - { "accg33", 33, {0, {0}}, 0, 0 }, - { "accg34", 34, {0, {0}}, 0, 0 }, - { "accg35", 35, {0, {0}}, 0, 0 }, - { "accg36", 36, {0, {0}}, 0, 0 }, - { "accg37", 37, {0, {0}}, 0, 0 }, - { "accg38", 38, {0, {0}}, 0, 0 }, - { "accg39", 39, {0, {0}}, 0, 0 }, - { "accg40", 40, {0, {0}}, 0, 0 }, - { "accg41", 41, {0, {0}}, 0, 0 }, - { "accg42", 42, {0, {0}}, 0, 0 }, - { "accg43", 43, {0, {0}}, 0, 0 }, - { "accg44", 44, {0, {0}}, 0, 0 }, - { "accg45", 45, {0, {0}}, 0, 0 }, - { "accg46", 46, {0, {0}}, 0, 0 }, - { "accg47", 47, {0, {0}}, 0, 0 }, - { "accg48", 48, {0, {0}}, 0, 0 }, - { "accg49", 49, {0, {0}}, 0, 0 }, - { "accg50", 50, {0, {0}}, 0, 0 }, - { "accg51", 51, {0, {0}}, 0, 0 }, - { "accg52", 52, {0, {0}}, 0, 0 }, - { "accg53", 53, {0, {0}}, 0, 0 }, - { "accg54", 54, {0, {0}}, 0, 0 }, - { "accg55", 55, {0, {0}}, 0, 0 }, - { "accg56", 56, {0, {0}}, 0, 0 }, - { "accg57", 57, {0, {0}}, 0, 0 }, - { "accg58", 58, {0, {0}}, 0, 0 }, - { "accg59", 59, {0, {0}}, 0, 0 }, - { "accg60", 60, {0, {0}}, 0, 0 }, - { "accg61", 61, {0, {0}}, 0, 0 }, - { "accg62", 62, {0, {0}}, 0, 0 }, - { "accg63", 63, {0, {0}}, 0, 0 } + { "accg0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "accg1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "accg2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "accg3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "accg4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "accg5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "accg6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "accg7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "accg8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "accg9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "accg10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "accg11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "accg12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "accg13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "accg14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "accg15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "accg16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "accg17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "accg18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "accg19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "accg20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "accg21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "accg22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "accg23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "accg24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "accg25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "accg26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "accg27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "accg28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "accg29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "accg30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "accg31", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "accg32", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "accg33", 33, {0, {{{0, 0}}}}, 0, 0 }, + { "accg34", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "accg35", 35, {0, {{{0, 0}}}}, 0, 0 }, + { "accg36", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "accg37", 37, {0, {{{0, 0}}}}, 0, 0 }, + { "accg38", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "accg39", 39, {0, {{{0, 0}}}}, 0, 0 }, + { "accg40", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "accg41", 41, {0, {{{0, 0}}}}, 0, 0 }, + { "accg42", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "accg43", 43, {0, {{{0, 0}}}}, 0, 0 }, + { "accg44", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "accg45", 45, {0, {{{0, 0}}}}, 0, 0 }, + { "accg46", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "accg47", 47, {0, {{{0, 0}}}}, 0, 0 }, + { "accg48", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "accg49", 49, {0, {{{0, 0}}}}, 0, 0 }, + { "accg50", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "accg51", 51, {0, {{{0, 0}}}}, 0, 0 }, + { "accg52", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "accg53", 53, {0, {{{0, 0}}}}, 0, 0 }, + { "accg54", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "accg55", 55, {0, {{{0, 0}}}}, 0, 0 }, + { "accg56", 56, {0, {{{0, 0}}}}, 0, 0 }, + { "accg57", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "accg58", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "accg59", 59, {0, {{{0, 0}}}}, 0, 0 }, + { "accg60", 60, {0, {{{0, 0}}}}, 0, 0 }, + { "accg61", 61, {0, {{{0, 0}}}}, 0, 0 }, + { "accg62", 62, {0, {{{0, 0}}}}, 0, 0 }, + { "accg63", 63, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD frv_cgen_opval_accg_names = @@ -1631,70 +1631,70 @@ CGEN_KEYWORD frv_cgen_opval_accg_names = static CGEN_KEYWORD_ENTRY frv_cgen_opval_acc_names_entries[] = { - { "acc0", 0, {0, {0}}, 0, 0 }, - { "acc1", 1, {0, {0}}, 0, 0 }, - { "acc2", 2, {0, {0}}, 0, 0 }, - { "acc3", 3, {0, {0}}, 0, 0 }, - { "acc4", 4, {0, {0}}, 0, 0 }, - { "acc5", 5, {0, {0}}, 0, 0 }, - { "acc6", 6, {0, {0}}, 0, 0 }, - { "acc7", 7, {0, {0}}, 0, 0 }, - { "acc8", 8, {0, {0}}, 0, 0 }, - { "acc9", 9, {0, {0}}, 0, 0 }, - { "acc10", 10, {0, {0}}, 0, 0 }, - { "acc11", 11, {0, {0}}, 0, 0 }, - { "acc12", 12, {0, {0}}, 0, 0 }, - { "acc13", 13, {0, {0}}, 0, 0 }, - { "acc14", 14, {0, {0}}, 0, 0 }, - { "acc15", 15, {0, {0}}, 0, 0 }, - { "acc16", 16, {0, {0}}, 0, 0 }, - { "acc17", 17, {0, {0}}, 0, 0 }, - { "acc18", 18, {0, {0}}, 0, 0 }, - { "acc19", 19, {0, {0}}, 0, 0 }, - { "acc20", 20, {0, {0}}, 0, 0 }, - { "acc21", 21, {0, {0}}, 0, 0 }, - { "acc22", 22, {0, {0}}, 0, 0 }, - { "acc23", 23, {0, {0}}, 0, 0 }, - { "acc24", 24, {0, {0}}, 0, 0 }, - { "acc25", 25, {0, {0}}, 0, 0 }, - { "acc26", 26, {0, {0}}, 0, 0 }, - { "acc27", 27, {0, {0}}, 0, 0 }, - { "acc28", 28, {0, {0}}, 0, 0 }, - { "acc29", 29, {0, {0}}, 0, 0 }, - { "acc30", 30, {0, {0}}, 0, 0 }, - { "acc31", 31, {0, {0}}, 0, 0 }, - { "acc32", 32, {0, {0}}, 0, 0 }, - { "acc33", 33, {0, {0}}, 0, 0 }, - { "acc34", 34, {0, {0}}, 0, 0 }, - { "acc35", 35, {0, {0}}, 0, 0 }, - { "acc36", 36, {0, {0}}, 0, 0 }, - { "acc37", 37, {0, {0}}, 0, 0 }, - { "acc38", 38, {0, {0}}, 0, 0 }, - { "acc39", 39, {0, {0}}, 0, 0 }, - { "acc40", 40, {0, {0}}, 0, 0 }, - { "acc41", 41, {0, {0}}, 0, 0 }, - { "acc42", 42, {0, {0}}, 0, 0 }, - { "acc43", 43, {0, {0}}, 0, 0 }, - { "acc44", 44, {0, {0}}, 0, 0 }, - { "acc45", 45, {0, {0}}, 0, 0 }, - { "acc46", 46, {0, {0}}, 0, 0 }, - { "acc47", 47, {0, {0}}, 0, 0 }, - { "acc48", 48, {0, {0}}, 0, 0 }, - { "acc49", 49, {0, {0}}, 0, 0 }, - { "acc50", 50, {0, {0}}, 0, 0 }, - { "acc51", 51, {0, {0}}, 0, 0 }, - { "acc52", 52, {0, {0}}, 0, 0 }, - { "acc53", 53, {0, {0}}, 0, 0 }, - { "acc54", 54, {0, {0}}, 0, 0 }, - { "acc55", 55, {0, {0}}, 0, 0 }, - { "acc56", 56, {0, {0}}, 0, 0 }, - { "acc57", 57, {0, {0}}, 0, 0 }, - { "acc58", 58, {0, {0}}, 0, 0 }, - { "acc59", 59, {0, {0}}, 0, 0 }, - { "acc60", 60, {0, {0}}, 0, 0 }, - { "acc61", 61, {0, {0}}, 0, 0 }, - { "acc62", 62, {0, {0}}, 0, 0 }, - { "acc63", 63, {0, {0}}, 0, 0 } + { "acc0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "acc1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "acc2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "acc3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "acc4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "acc5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "acc6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "acc7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "acc8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "acc9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "acc10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "acc11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "acc12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "acc13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "acc14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "acc15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "acc16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "acc17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "acc18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "acc19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "acc20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "acc21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "acc22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "acc23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "acc24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "acc25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "acc26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "acc27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "acc28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "acc29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "acc30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "acc31", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "acc32", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "acc33", 33, {0, {{{0, 0}}}}, 0, 0 }, + { "acc34", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "acc35", 35, {0, {{{0, 0}}}}, 0, 0 }, + { "acc36", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "acc37", 37, {0, {{{0, 0}}}}, 0, 0 }, + { "acc38", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "acc39", 39, {0, {{{0, 0}}}}, 0, 0 }, + { "acc40", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "acc41", 41, {0, {{{0, 0}}}}, 0, 0 }, + { "acc42", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "acc43", 43, {0, {{{0, 0}}}}, 0, 0 }, + { "acc44", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "acc45", 45, {0, {{{0, 0}}}}, 0, 0 }, + { "acc46", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "acc47", 47, {0, {{{0, 0}}}}, 0, 0 }, + { "acc48", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "acc49", 49, {0, {{{0, 0}}}}, 0, 0 }, + { "acc50", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "acc51", 51, {0, {{{0, 0}}}}, 0, 0 }, + { "acc52", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "acc53", 53, {0, {{{0, 0}}}}, 0, 0 }, + { "acc54", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "acc55", 55, {0, {{{0, 0}}}}, 0, 0 }, + { "acc56", 56, {0, {{{0, 0}}}}, 0, 0 }, + { "acc57", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "acc58", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "acc59", 59, {0, {{{0, 0}}}}, 0, 0 }, + { "acc60", 60, {0, {{{0, 0}}}}, 0, 0 }, + { "acc61", 61, {0, {{{0, 0}}}}, 0, 0 }, + { "acc62", 62, {0, {{{0, 0}}}}, 0, 0 }, + { "acc63", 63, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD frv_cgen_opval_acc_names = @@ -1706,7 +1706,7 @@ CGEN_KEYWORD frv_cgen_opval_acc_names = static CGEN_KEYWORD_ENTRY frv_cgen_opval_iacc0_names_entries[] = { - { "iacc0", 0, {0, {0}}, 0, 0 } + { "iacc0", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD frv_cgen_opval_iacc0_names = @@ -1718,10 +1718,10 @@ CGEN_KEYWORD frv_cgen_opval_iacc0_names = static CGEN_KEYWORD_ENTRY frv_cgen_opval_iccr_names_entries[] = { - { "icc0", 0, {0, {0}}, 0, 0 }, - { "icc1", 1, {0, {0}}, 0, 0 }, - { "icc2", 2, {0, {0}}, 0, 0 }, - { "icc3", 3, {0, {0}}, 0, 0 } + { "icc0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "icc1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "icc2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "icc3", 3, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD frv_cgen_opval_iccr_names = @@ -1733,10 +1733,10 @@ CGEN_KEYWORD frv_cgen_opval_iccr_names = static CGEN_KEYWORD_ENTRY frv_cgen_opval_fccr_names_entries[] = { - { "fcc0", 0, {0, {0}}, 0, 0 }, - { "fcc1", 1, {0, {0}}, 0, 0 }, - { "fcc2", 2, {0, {0}}, 0, 0 }, - { "fcc3", 3, {0, {0}}, 0, 0 } + { "fcc0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "fcc1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "fcc2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "fcc3", 3, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD frv_cgen_opval_fccr_names = @@ -1748,14 +1748,14 @@ CGEN_KEYWORD frv_cgen_opval_fccr_names = static CGEN_KEYWORD_ENTRY frv_cgen_opval_cccr_names_entries[] = { - { "cc0", 0, {0, {0}}, 0, 0 }, - { "cc1", 1, {0, {0}}, 0, 0 }, - { "cc2", 2, {0, {0}}, 0, 0 }, - { "cc3", 3, {0, {0}}, 0, 0 }, - { "cc4", 4, {0, {0}}, 0, 0 }, - { "cc5", 5, {0, {0}}, 0, 0 }, - { "cc6", 6, {0, {0}}, 0, 0 }, - { "cc7", 7, {0, {0}}, 0, 0 } + { "cc0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "cc1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "cc2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "cc3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "cc4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "cc5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "cc6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "cc7", 7, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD frv_cgen_opval_cccr_names = @@ -1767,9 +1767,9 @@ CGEN_KEYWORD frv_cgen_opval_cccr_names = static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_pack_entries[] = { - { "", 1, {0, {0}}, 0, 0 }, - { ".p", 0, {0, {0}}, 0, 0 }, - { ".P", 0, {0, {0}}, 0, 0 } + { "", 1, {0, {{{0, 0}}}}, 0, 0 }, + { ".p", 0, {0, {{{0, 0}}}}, 0, 0 }, + { ".P", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD frv_cgen_opval_h_pack = @@ -1781,10 +1781,10 @@ CGEN_KEYWORD frv_cgen_opval_h_pack = static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_taken_entries[] = { - { "", 2, {0, {0}}, 0, 0 }, - { "", 0, {0, {0}}, 0, 0 }, - { "", 1, {0, {0}}, 0, 0 }, - { "", 3, {0, {0}}, 0, 0 } + { "", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "", 3, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD frv_cgen_opval_h_hint_taken = @@ -1796,10 +1796,10 @@ CGEN_KEYWORD frv_cgen_opval_h_hint_taken = static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_not_taken_entries[] = { - { "", 0, {0, {0}}, 0, 0 }, - { "", 1, {0, {0}}, 0, 0 }, - { "", 2, {0, {0}}, 0, 0 }, - { "", 3, {0, {0}}, 0, 0 } + { "", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "", 3, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD frv_cgen_opval_h_hint_not_taken = @@ -1820,57 +1820,57 @@ CGEN_KEYWORD frv_cgen_opval_h_hint_not_taken = const CGEN_HW_ENTRY frv_cgen_hw_table[] = { - { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-reloc-ann", HW_H_RELOC_ANN, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } }, - { "h-psr_imple", HW_H_PSR_IMPLE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-psr_ver", HW_H_PSR_VER, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-psr_ice", HW_H_PSR_ICE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-psr_nem", HW_H_PSR_NEM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-psr_cm", HW_H_PSR_CM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-psr_be", HW_H_PSR_BE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-psr_esr", HW_H_PSR_ESR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-psr_ef", HW_H_PSR_EF, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-psr_em", HW_H_PSR_EM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-psr_pil", HW_H_PSR_PIL, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-psr_ps", HW_H_PSR_PS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-psr_et", HW_H_PSR_ET, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-psr_s", HW_H_PSR_S, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-tbr_tba", HW_H_TBR_TBA, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-tbr_tt", HW_H_TBR_TT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-bpsr_bs", HW_H_BPSR_BS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-bpsr_bet", HW_H_BPSR_BET, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } }, - { "h-gr_double", HW_H_GR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, - { "h-gr_hi", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, - { "h-gr_lo", HW_H_GR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, - { "h-fr", HW_H_FR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } }, - { "h-fr_double", HW_H_FR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, - { "h-fr_int", HW_H_FR_INT, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, - { "h-fr_hi", HW_H_FR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, - { "h-fr_lo", HW_H_FR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, - { "h-fr_0", HW_H_FR_0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, - { "h-fr_1", HW_H_FR_1, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, - { "h-fr_2", HW_H_FR_2, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, - { "h-fr_3", HW_H_FR_3, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, - { "h-cpr", HW_H_CPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(PROFILE), { (1<<MACH_FRV) } } }, - { "h-cpr_double", HW_H_CPR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_FRV) } } }, - { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_spr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } }, - { "h-accg", HW_H_ACCG, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_accg_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, - { "h-acc40S", HW_H_ACC40S, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, - { "h-acc40U", HW_H_ACC40U, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, - { "h-iacc0", HW_H_IACC0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iacc0_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_FR400)|(1<<MACH_FR450) } } }, - { "h-iccr", HW_H_ICCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } }, - { "h-fccr", HW_H_FCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } }, - { "h-cccr", HW_H_CCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } }, - { "h-pack", HW_H_PACK, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_pack, { 0, { (1<<MACH_BASE) } } }, - { "h-hint-taken", HW_H_HINT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_taken, { 0, { (1<<MACH_BASE) } } }, - { "h-hint-not-taken", HW_H_HINT_NOT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_not_taken, { 0, { (1<<MACH_BASE) } } }, - { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} } + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-reloc-ann", HW_H_RELOC_ANN, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-psr_imple", HW_H_PSR_IMPLE, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-psr_ver", HW_H_PSR_VER, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-psr_ice", HW_H_PSR_ICE, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-psr_nem", HW_H_PSR_NEM, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-psr_cm", HW_H_PSR_CM, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-psr_be", HW_H_PSR_BE, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-psr_esr", HW_H_PSR_ESR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-psr_ef", HW_H_PSR_EF, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-psr_em", HW_H_PSR_EM, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-psr_pil", HW_H_PSR_PIL, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-psr_ps", HW_H_PSR_PS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-psr_et", HW_H_PSR_ET, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-psr_s", HW_H_PSR_S, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-tbr_tba", HW_H_TBR_TBA, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-tbr_tt", HW_H_TBR_TT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-bpsr_bs", HW_H_BPSR_BS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-bpsr_bet", HW_H_BPSR_BET, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-gr_double", HW_H_GR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-gr_hi", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-gr_lo", HW_H_GR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-fr", HW_H_FR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-fr_double", HW_H_FR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-fr_int", HW_H_FR_INT, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-fr_hi", HW_H_FR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-fr_lo", HW_H_FR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-fr_0", HW_H_FR_0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-fr_1", HW_H_FR_1, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-fr_2", HW_H_FR_2, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-fr_3", HW_H_FR_3, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-cpr", HW_H_CPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(PROFILE), { { { (1<<MACH_FRV), 0 } } } } }, + { "h-cpr_double", HW_H_CPR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_FRV), 0 } } } } }, + { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_spr_names, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-accg", HW_H_ACCG, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_accg_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-acc40S", HW_H_ACC40S, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-acc40U", HW_H_ACC40U, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-iacc0", HW_H_IACC0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iacc0_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_FR400)|(1<<MACH_FR450), 0 } } } } }, + { "h-iccr", HW_H_ICCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iccr_names, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-fccr", HW_H_FCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fccr_names, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-cccr", HW_H_CCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cccr_names, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-pack", HW_H_PACK, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_pack, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-hint-taken", HW_H_HINT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_taken, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-hint-not-taken", HW_H_HINT_NOT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_not_taken, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } }; #undef A @@ -1886,112 +1886,112 @@ const CGEN_HW_ENTRY frv_cgen_hw_table[] = const CGEN_IFLD frv_cgen_ifld_table[] = { - { FRV_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_PACK, "f-pack", 0, 32, 31, 1, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_OP, "f-op", 0, 32, 24, 7, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_OPE1, "f-ope1", 0, 32, 11, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_OPE2, "f-ope2", 0, 32, 9, 4, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_OPE3, "f-ope3", 0, 32, 15, 3, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_OPE4, "f-ope4", 0, 32, 7, 2, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_GRI, "f-GRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_GRJ, "f-GRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_GRK, "f-GRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_FRI, "f-FRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_FRJ, "f-FRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_FRK, "f-FRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_CPRI, "f-CPRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_CPRJ, "f-CPRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_CPRK, "f-CPRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_ACCGI, "f-ACCGi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_ACCGK, "f-ACCGk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_ACC40SI, "f-ACC40Si", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_ACC40UI, "f-ACC40Ui", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_ACC40SK, "f-ACC40Sk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_ACC40UK, "f-ACC40Uk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_CRI, "f-CRi", 0, 32, 14, 3, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_CRJ, "f-CRj", 0, 32, 2, 3, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_CRK, "f-CRk", 0, 32, 27, 3, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_CCI, "f-CCi", 0, 32, 11, 3, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_CRJ_INT, "f-CRj_int", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_CRJ_FLOAT, "f-CRj_float", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_ICCI_1, "f-ICCi_1", 0, 32, 11, 2, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_ICCI_2, "f-ICCi_2", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_ICCI_3, "f-ICCi_3", 0, 32, 1, 2, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_FCCI_1, "f-FCCi_1", 0, 32, 11, 2, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_FCCI_2, "f-FCCi_2", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_FCCI_3, "f-FCCi_3", 0, 32, 1, 2, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_FCCK, "f-FCCk", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_EIR, "f-eir", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_S10, "f-s10", 0, 32, 9, 10, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_S12, "f-s12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_D12, "f-d12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_U16, "f-u16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_S16, "f-s16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_S6, "f-s6", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_S6_1, "f-s6_1", 0, 32, 11, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_U6, "f-u6", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_S5, "f-s5", 0, 32, 4, 5, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_U12_H, "f-u12-h", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_U12_L, "f-u12-l", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_U12, "f-u12", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { FRV_F_INT_CC, "f-int-cc", 0, 32, 30, 4, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_FLT_CC, "f-flt-cc", 0, 32, 30, 4, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_COND, "f-cond", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_CCOND, "f-ccond", 0, 32, 12, 1, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_HINT, "f-hint", 0, 32, 17, 2, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_LI, "f-LI", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_LOCK, "f-lock", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_DEBUG, "f-debug", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_A, "f-A", 0, 32, 17, 1, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_AE, "f-ae", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_SPR_H, "f-spr-h", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_SPR_L, "f-spr-l", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_SPR, "f-spr", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { FRV_F_LABEL16, "f-label16", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, - { FRV_F_LABELH6, "f-labelH6", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_LABELL18, "f-labelL18", 0, 32, 17, 18, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_LABEL24, "f-label24", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { FRV_F_LRAE, "f-LRAE", 0, 32, 5, 1, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_LRAD, "f-LRAD", 0, 32, 4, 1, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_LRAS, "f-LRAS", 0, 32, 3, 1, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_TLBPROPX, "f-TLBPRopx", 0, 32, 28, 3, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_TLBPRL, "f-TLBPRL", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } } }, - { FRV_F_ICCI_1_NULL, "f-ICCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_ICCI_2_NULL, "f-ICCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_ICCI_3_NULL, "f-ICCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_FCCI_1_NULL, "f-FCCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_FCCI_2_NULL, "f-FCCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_FCCI_3_NULL, "f-FCCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_RS_NULL, "f-rs-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_GRI_NULL, "f-GRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_GRJ_NULL, "f-GRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_GRK_NULL, "f-GRk-null", 0, 32, 30, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_FRI_NULL, "f-FRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_FRJ_NULL, "f-FRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_ACCJ_NULL, "f-ACCj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_RD_NULL, "f-rd-null", 0, 32, 30, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_COND_NULL, "f-cond-null", 0, 32, 30, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_CCOND_NULL, "f-ccond-null", 0, 32, 12, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_S12_NULL, "f-s12-null", 0, 32, 11, 12, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_LABEL16_NULL, "f-label16-null", 0, 32, 15, 16, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_MISC_NULL_1, "f-misc-null-1", 0, 32, 30, 5, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_MISC_NULL_2, "f-misc-null-2", 0, 32, 11, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_MISC_NULL_3, "f-misc-null-3", 0, 32, 11, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_MISC_NULL_4, "f-misc-null-4", 0, 32, 17, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_MISC_NULL_5, "f-misc-null-5", 0, 32, 17, 16, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_MISC_NULL_6, "f-misc-null-6", 0, 32, 30, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_MISC_NULL_7, "f-misc-null-7", 0, 32, 17, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_MISC_NULL_8, "f-misc-null-8", 0, 32, 5, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_MISC_NULL_9, "f-misc-null-9", 0, 32, 5, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_MISC_NULL_10, "f-misc-null-10", 0, 32, 16, 5, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_MISC_NULL_11, "f-misc-null-11", 0, 32, 5, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_LRA_NULL, "f-LRA-null", 0, 32, 2, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_TLBPR_NULL, "f-TLBPR-null", 0, 32, 30, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_LI_OFF, "f-LI-off", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_LI_ON, "f-LI-on", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { FRV_F_RELOC_ANN, "f-reloc-ann", 0, 32, 0, 0, { 0, { (1<<MACH_BASE) } } }, - { 0, 0, 0, 0, 0, 0, {0, {0}} } + { FRV_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_PACK, "f-pack", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_OP, "f-op", 0, 32, 24, 7, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_OPE1, "f-ope1", 0, 32, 11, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_OPE2, "f-ope2", 0, 32, 9, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_OPE3, "f-ope3", 0, 32, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_OPE4, "f-ope4", 0, 32, 7, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_GRI, "f-GRi", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_GRJ, "f-GRj", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_GRK, "f-GRk", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_FRI, "f-FRi", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_FRJ, "f-FRj", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_FRK, "f-FRk", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_CPRI, "f-CPRi", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_CPRJ, "f-CPRj", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_CPRK, "f-CPRk", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_ACCGI, "f-ACCGi", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_ACCGK, "f-ACCGk", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_ACC40SI, "f-ACC40Si", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_ACC40UI, "f-ACC40Ui", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_ACC40SK, "f-ACC40Sk", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_ACC40UK, "f-ACC40Uk", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_CRI, "f-CRi", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_CRJ, "f-CRj", 0, 32, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_CRK, "f-CRk", 0, 32, 27, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_CCI, "f-CCi", 0, 32, 11, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_CRJ_INT, "f-CRj_int", 0, 32, 26, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_CRJ_FLOAT, "f-CRj_float", 0, 32, 26, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_ICCI_1, "f-ICCi_1", 0, 32, 11, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_ICCI_2, "f-ICCi_2", 0, 32, 26, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_ICCI_3, "f-ICCi_3", 0, 32, 1, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_FCCI_1, "f-FCCi_1", 0, 32, 11, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_FCCI_2, "f-FCCi_2", 0, 32, 26, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_FCCI_3, "f-FCCi_3", 0, 32, 1, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_FCCK, "f-FCCk", 0, 32, 26, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_EIR, "f-eir", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_S10, "f-s10", 0, 32, 9, 10, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_S12, "f-s12", 0, 32, 11, 12, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_D12, "f-d12", 0, 32, 11, 12, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_U16, "f-u16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_S16, "f-s16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_S6, "f-s6", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_S6_1, "f-s6_1", 0, 32, 11, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_U6, "f-u6", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_S5, "f-s5", 0, 32, 4, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_U12_H, "f-u12-h", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_U12_L, "f-u12-l", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_U12, "f-u12", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_INT_CC, "f-int-cc", 0, 32, 30, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_FLT_CC, "f-flt-cc", 0, 32, 30, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_COND, "f-cond", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_CCOND, "f-ccond", 0, 32, 12, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_HINT, "f-hint", 0, 32, 17, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_LI, "f-LI", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_LOCK, "f-lock", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_DEBUG, "f-debug", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_A, "f-A", 0, 32, 17, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_AE, "f-ae", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_SPR_H, "f-spr-h", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_SPR_L, "f-spr-l", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_SPR, "f-spr", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_LABEL16, "f-label16", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_LABELH6, "f-labelH6", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_LABELL18, "f-labelL18", 0, 32, 17, 18, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_LABEL24, "f-label24", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_LRAE, "f-LRAE", 0, 32, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_LRAD, "f-LRAD", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_LRAS, "f-LRAS", 0, 32, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_TLBPROPX, "f-TLBPRopx", 0, 32, 28, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_TLBPRL, "f-TLBPRL", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_ICCI_1_NULL, "f-ICCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_ICCI_2_NULL, "f-ICCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_ICCI_3_NULL, "f-ICCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_FCCI_1_NULL, "f-FCCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_FCCI_2_NULL, "f-FCCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_FCCI_3_NULL, "f-FCCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_RS_NULL, "f-rs-null", 0, 32, 17, 6, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_GRI_NULL, "f-GRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_GRJ_NULL, "f-GRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_GRK_NULL, "f-GRk-null", 0, 32, 30, 6, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_FRI_NULL, "f-FRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_FRJ_NULL, "f-FRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_ACCJ_NULL, "f-ACCj-null", 0, 32, 5, 6, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_RD_NULL, "f-rd-null", 0, 32, 30, 6, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_COND_NULL, "f-cond-null", 0, 32, 30, 4, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_CCOND_NULL, "f-ccond-null", 0, 32, 12, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_S12_NULL, "f-s12-null", 0, 32, 11, 12, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_LABEL16_NULL, "f-label16-null", 0, 32, 15, 16, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_MISC_NULL_1, "f-misc-null-1", 0, 32, 30, 5, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_MISC_NULL_2, "f-misc-null-2", 0, 32, 11, 6, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_MISC_NULL_3, "f-misc-null-3", 0, 32, 11, 4, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_MISC_NULL_4, "f-misc-null-4", 0, 32, 17, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_MISC_NULL_5, "f-misc-null-5", 0, 32, 17, 16, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_MISC_NULL_6, "f-misc-null-6", 0, 32, 30, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_MISC_NULL_7, "f-misc-null-7", 0, 32, 17, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_MISC_NULL_8, "f-misc-null-8", 0, 32, 5, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_MISC_NULL_9, "f-misc-null-9", 0, 32, 5, 4, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_MISC_NULL_10, "f-misc-null-10", 0, 32, 16, 5, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_MISC_NULL_11, "f-misc-null-11", 0, 32, 5, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_LRA_NULL, "f-LRA-null", 0, 32, 2, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_TLBPR_NULL, "f-TLBPR-null", 0, 32, 30, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_LI_OFF, "f-LI-off", 0, 32, 25, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_LI_ON, "f-LI-on", 0, 32, 25, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { FRV_F_RELOC_ANN, "f-reloc-ann", 0, 32, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } }; #undef A @@ -2044,363 +2044,363 @@ const CGEN_OPERAND frv_cgen_operand_table[] = /* pc: program counter */ { "pc", FRV_OPERAND_PC, HW_H_PC, 0, 0, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_NIL] } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* pack: packing bit */ { "pack", FRV_OPERAND_PACK, HW_H_PACK, 31, 1, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_PACK] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* GRi: source register 1 */ { "GRi", FRV_OPERAND_GRI, HW_H_GR, 17, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRI] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* GRj: source register 2 */ { "GRj", FRV_OPERAND_GRJ, HW_H_GR, 5, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRJ] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* GRk: destination register */ { "GRk", FRV_OPERAND_GRK, HW_H_GR, 30, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* GRkhi: destination register */ { "GRkhi", FRV_OPERAND_GRKHI, HW_H_GR_HI, 30, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* GRklo: destination register */ { "GRklo", FRV_OPERAND_GRKLO, HW_H_GR_LO, 30, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* GRdoublek: destination register */ { "GRdoublek", FRV_OPERAND_GRDOUBLEK, HW_H_GR_DOUBLE, 30, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ACC40Si: signed accumulator */ { "ACC40Si", FRV_OPERAND_ACC40SI, HW_H_ACC40S, 17, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SI] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ACC40Ui: unsigned accumulator */ { "ACC40Ui", FRV_OPERAND_ACC40UI, HW_H_ACC40U, 17, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UI] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ACC40Sk: target accumulator */ { "ACC40Sk", FRV_OPERAND_ACC40SK, HW_H_ACC40S, 30, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SK] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ACC40Uk: target accumulator */ { "ACC40Uk", FRV_OPERAND_ACC40UK, HW_H_ACC40U, 30, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UK] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ACCGi: source register */ { "ACCGi", FRV_OPERAND_ACCGI, HW_H_ACCG, 17, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGI] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ACCGk: target register */ { "ACCGk", FRV_OPERAND_ACCGK, HW_H_ACCG, 30, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGK] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* CPRi: source register */ { "CPRi", FRV_OPERAND_CPRI, HW_H_CPR, 17, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRI] } }, - { 0, { (1<<MACH_FRV) } } }, + { 0, { { { (1<<MACH_FRV), 0 } } } } }, /* CPRj: source register */ { "CPRj", FRV_OPERAND_CPRJ, HW_H_CPR, 5, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRJ] } }, - { 0, { (1<<MACH_FRV) } } }, + { 0, { { { (1<<MACH_FRV), 0 } } } } }, /* CPRk: destination register */ { "CPRk", FRV_OPERAND_CPRK, HW_H_CPR, 30, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } }, - { 0, { (1<<MACH_FRV) } } }, + { 0, { { { (1<<MACH_FRV), 0 } } } } }, /* CPRdoublek: destination register */ { "CPRdoublek", FRV_OPERAND_CPRDOUBLEK, HW_H_CPR_DOUBLE, 30, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } }, - { 0, { (1<<MACH_FRV) } } }, + { 0, { { { (1<<MACH_FRV), 0 } } } } }, /* FRinti: source register 1 */ { "FRinti", FRV_OPERAND_FRINTI, HW_H_FR_INT, 17, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* FRintj: source register 2 */ { "FRintj", FRV_OPERAND_FRINTJ, HW_H_FR_INT, 5, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* FRintk: target register */ { "FRintk", FRV_OPERAND_FRINTK, HW_H_FR_INT, 30, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* FRi: source register 1 */ { "FRi", FRV_OPERAND_FRI, HW_H_FR, 17, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* FRj: source register 2 */ { "FRj", FRV_OPERAND_FRJ, HW_H_FR, 5, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* FRk: destination register */ { "FRk", FRV_OPERAND_FRK, HW_H_FR, 30, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* FRkhi: destination register */ { "FRkhi", FRV_OPERAND_FRKHI, HW_H_FR_HI, 30, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* FRklo: destination register */ { "FRklo", FRV_OPERAND_FRKLO, HW_H_FR_LO, 30, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* FRdoublei: source register 1 */ { "FRdoublei", FRV_OPERAND_FRDOUBLEI, HW_H_FR_DOUBLE, 17, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* FRdoublej: source register 2 */ { "FRdoublej", FRV_OPERAND_FRDOUBLEJ, HW_H_FR_DOUBLE, 5, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* FRdoublek: target register */ { "FRdoublek", FRV_OPERAND_FRDOUBLEK, HW_H_FR_DOUBLE, 30, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* CRi: source register 1 */ { "CRi", FRV_OPERAND_CRI, HW_H_CCCR, 14, 3, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRI] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* CRj: source register 2 */ { "CRj", FRV_OPERAND_CRJ, HW_H_CCCR, 2, 3, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* CRj_int: destination register */ { "CRj_int", FRV_OPERAND_CRJ_INT, HW_H_CCCR, 26, 2, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_INT] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* CRj_float: destination register */ { "CRj_float", FRV_OPERAND_CRJ_FLOAT, HW_H_CCCR, 26, 2, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_FLOAT] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* CRk: destination register */ { "CRk", FRV_OPERAND_CRK, HW_H_CCCR, 27, 3, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRK] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* CCi: condition register */ { "CCi", FRV_OPERAND_CCI, HW_H_CCCR, 11, 3, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCI] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ICCi_1: condition register */ { "ICCi_1", FRV_OPERAND_ICCI_1, HW_H_ICCR, 11, 2, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_1] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ICCi_2: condition register */ { "ICCi_2", FRV_OPERAND_ICCI_2, HW_H_ICCR, 26, 2, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_2] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ICCi_3: condition register */ { "ICCi_3", FRV_OPERAND_ICCI_3, HW_H_ICCR, 1, 2, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_3] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* FCCi_1: condition register */ { "FCCi_1", FRV_OPERAND_FCCI_1, HW_H_FCCR, 11, 2, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_1] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* FCCi_2: condition register */ { "FCCi_2", FRV_OPERAND_FCCI_2, HW_H_FCCR, 26, 2, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_2] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* FCCi_3: condition register */ { "FCCi_3", FRV_OPERAND_FCCI_3, HW_H_FCCR, 1, 2, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_3] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* FCCk: condition register */ { "FCCk", FRV_OPERAND_FCCK, HW_H_FCCR, 26, 2, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCK] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* eir: exception insn reg */ { "eir", FRV_OPERAND_EIR, HW_H_UINT, 17, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_EIR] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* s10: 10 bit signed immediate */ { "s10", FRV_OPERAND_S10, HW_H_SINT, 9, 10, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S10] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* u16: 16 bit unsigned immediate */ { "u16", FRV_OPERAND_U16, HW_H_UINT, 15, 16, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* s16: 16 bit signed immediate */ { "s16", FRV_OPERAND_S16, HW_H_SINT, 15, 16, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* s6: 6 bit signed immediate */ { "s6", FRV_OPERAND_S6, HW_H_SINT, 5, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* s6_1: 6 bit signed immediate */ { "s6_1", FRV_OPERAND_S6_1, HW_H_SINT, 11, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6_1] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* u6: 6 bit unsigned immediate */ { "u6", FRV_OPERAND_U6, HW_H_UINT, 5, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U6] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* s5: 5 bit signed immediate */ { "s5", FRV_OPERAND_S5, HW_H_SINT, 4, 5, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S5] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* cond: conditional arithmetic */ { "cond", FRV_OPERAND_COND, HW_H_UINT, 8, 1, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_COND] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* ccond: lr branch condition */ { "ccond", FRV_OPERAND_CCOND, HW_H_UINT, 12, 1, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCOND] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* hint: 2 bit branch predictor */ { "hint", FRV_OPERAND_HINT, HW_H_UINT, 17, 2, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* hint_taken: 2 bit branch predictor */ { "hint_taken", FRV_OPERAND_HINT_TAKEN, HW_H_HINT_TAKEN, 17, 2, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* hint_not_taken: 2 bit branch predictor */ { "hint_not_taken", FRV_OPERAND_HINT_NOT_TAKEN, HW_H_HINT_NOT_TAKEN, 17, 2, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* LI: link indicator */ { "LI", FRV_OPERAND_LI, HW_H_UINT, 25, 1, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LI] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* lock: cache lock indicator */ { "lock", FRV_OPERAND_LOCK, HW_H_UINT, 25, 1, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LOCK] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* debug: debug mode indicator */ { "debug", FRV_OPERAND_DEBUG, HW_H_UINT, 25, 1, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_DEBUG] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* ae: all entries indicator */ { "ae", FRV_OPERAND_AE, HW_H_UINT, 25, 1, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_AE] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* label16: 18 bit pc relative address */ { "label16", FRV_OPERAND_LABEL16, HW_H_IADDR, 15, 16, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABEL16] } }, - { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, + { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, /* LRAE: Load Real Address E flag */ { "LRAE", FRV_OPERAND_LRAE, HW_H_UINT, 5, 1, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAE] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* LRAD: Load Real Address D flag */ { "LRAD", FRV_OPERAND_LRAD, HW_H_UINT, 4, 1, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAD] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* LRAS: Load Real Address S flag */ { "LRAS", FRV_OPERAND_LRAS, HW_H_UINT, 3, 1, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAS] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* TLBPRopx: TLB Probe operation number */ { "TLBPRopx", FRV_OPERAND_TLBPROPX, HW_H_UINT, 28, 3, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_TLBPROPX] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* TLBPRL: TLB Probe L flag */ { "TLBPRL", FRV_OPERAND_TLBPRL, HW_H_UINT, 25, 1, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_TLBPRL] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* A0: A==0 operand of mclracc */ { "A0", FRV_OPERAND_A0, HW_H_UINT, 17, 1, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* A1: A==1 operand of mclracc */ { "A1", FRV_OPERAND_A1, HW_H_UINT, 17, 1, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* FRintieven: (even) source register 1 */ { "FRintieven", FRV_OPERAND_FRINTIEVEN, HW_H_FR_INT, 17, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* FRintjeven: (even) source register 2 */ { "FRintjeven", FRV_OPERAND_FRINTJEVEN, HW_H_FR_INT, 5, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* FRintkeven: (even) target register */ { "FRintkeven", FRV_OPERAND_FRINTKEVEN, HW_H_FR_INT, 30, 6, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* d12: 12 bit signed immediate */ { "d12", FRV_OPERAND_D12, HW_H_SINT, 11, 12, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* s12: 12 bit signed immediate */ { "s12", FRV_OPERAND_S12, HW_H_SINT, 11, 12, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* u12: 12 bit signed immediate */ { "u12", FRV_OPERAND_U12, HW_H_SINT, 5, 12, { 2, { (const PTR) &FRV_F_U12_MULTI_IFIELD[0] } }, - { 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, /* spr: special purpose register */ { "spr", FRV_OPERAND_SPR, HW_H_SPR, 17, 12, { 2, { (const PTR) &FRV_F_SPR_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, /* ulo16: 16 bit unsigned immediate, for #lo() */ { "ulo16", FRV_OPERAND_ULO16, HW_H_UINT, 15, 16, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* slo16: 16 bit unsigned immediate, for #lo() */ { "slo16", FRV_OPERAND_SLO16, HW_H_SINT, 15, 16, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* uhi16: 16 bit unsigned immediate, for #hi() */ { "uhi16", FRV_OPERAND_UHI16, HW_H_UINT, 15, 16, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* label24: 26 bit pc relative address */ { "label24", FRV_OPERAND_LABEL24, HW_H_IADDR, 17, 24, { 2, { (const PTR) &FRV_F_LABEL24_MULTI_IFIELD[0] } }, - { 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } }, + { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, /* psr_esr: PSR.ESR bit */ { "psr_esr", FRV_OPERAND_PSR_ESR, HW_H_PSR_ESR, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* psr_s: PSR.S bit */ { "psr_s", FRV_OPERAND_PSR_S, HW_H_PSR_S, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* psr_ps: PSR.PS bit */ { "psr_ps", FRV_OPERAND_PSR_PS, HW_H_PSR_PS, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* psr_et: PSR.ET bit */ { "psr_et", FRV_OPERAND_PSR_ET, HW_H_PSR_ET, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* bpsr_bs: BPSR.BS bit */ { "bpsr_bs", FRV_OPERAND_BPSR_BS, HW_H_BPSR_BS, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* bpsr_bet: BPSR.BET bit */ { "bpsr_bet", FRV_OPERAND_BPSR_BET, HW_H_BPSR_BET, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* tbr_tba: TBR.TBA */ { "tbr_tba", FRV_OPERAND_TBR_TBA, HW_H_TBR_TBA, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* tbr_tt: TBR.TT */ { "tbr_tt", FRV_OPERAND_TBR_TT, HW_H_TBR_TT, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* ldann: ld annotation */ { "ldann", FRV_OPERAND_LDANN, HW_H_RELOC_ANN, 0, 0, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* lddann: ldd annotation */ { "lddann", FRV_OPERAND_LDDANN, HW_H_RELOC_ANN, 0, 0, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* callann: call annotation */ { "callann", FRV_OPERAND_CALLANN, HW_H_RELOC_ANN, 0, 0, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* sentinel */ { 0, 0, 0, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { 0 } } } + { 0, { { { (1<<MACH_BASE), 0 } } } } } }; #undef A @@ -2420,3721 +2420,3721 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* Special null first entry. A `num' value of zero is thus invalid. Also, the special `invalid' insn resides here. */ - { 0, 0, 0, 0, {0, {0}} }, + { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_NIL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* add$pack $GRi,$GRj,$GRk */ { FRV_INSN_ADD, "add", "add", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* sub$pack $GRi,$GRj,$GRk */ { FRV_INSN_SUB, "sub", "sub", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* and$pack $GRi,$GRj,$GRk */ { FRV_INSN_AND, "and", "and", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* or$pack $GRi,$GRj,$GRk */ { FRV_INSN_OR, "or", "or", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* xor$pack $GRi,$GRj,$GRk */ { FRV_INSN_XOR, "xor", "xor", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* not$pack $GRj,$GRk */ { FRV_INSN_NOT, "not", "not", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* sdiv$pack $GRi,$GRj,$GRk */ { FRV_INSN_SDIV, "sdiv", "sdiv", 32, - { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } } }, /* nsdiv$pack $GRi,$GRj,$GRk */ { FRV_INSN_NSDIV, "nsdiv", "nsdiv", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } } }, /* udiv$pack $GRi,$GRj,$GRk */ { FRV_INSN_UDIV, "udiv", "udiv", 32, - { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } } }, /* nudiv$pack $GRi,$GRj,$GRk */ { FRV_INSN_NUDIV, "nudiv", "nudiv", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } } }, /* smul$pack $GRi,$GRj,$GRdoublek */ { FRV_INSN_SMUL, "smul", "smul", 32, - { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } } }, /* umul$pack $GRi,$GRj,$GRdoublek */ { FRV_INSN_UMUL, "umul", "umul", 32, - { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } } }, /* smu$pack $GRi,$GRj */ { FRV_INSN_SMU, "smu", "smu", 32, - { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IACC, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } } + { 0|A(AUDIO), { { { (1<<MACH_FR400)|(1<<MACH_FR450), 0 } }, { { UNIT_IACC, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* smass$pack $GRi,$GRj */ { FRV_INSN_SMASS, "smass", "smass", 32, - { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IACC, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } } + { 0|A(AUDIO), { { { (1<<MACH_FR400)|(1<<MACH_FR450), 0 } }, { { UNIT_IACC, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* smsss$pack $GRi,$GRj */ { FRV_INSN_SMSSS, "smsss", "smsss", 32, - { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IACC, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } } + { 0|A(AUDIO), { { { (1<<MACH_FR400)|(1<<MACH_FR450), 0 } }, { { UNIT_IACC, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* sll$pack $GRi,$GRj,$GRk */ { FRV_INSN_SLL, "sll", "sll", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* srl$pack $GRi,$GRj,$GRk */ { FRV_INSN_SRL, "srl", "srl", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* sra$pack $GRi,$GRj,$GRk */ { FRV_INSN_SRA, "sra", "sra", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* slass$pack $GRi,$GRj,$GRk */ { FRV_INSN_SLASS, "slass", "slass", 32, - { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } } + { 0|A(AUDIO), { { { (1<<MACH_FR400)|(1<<MACH_FR450), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* scutss$pack $GRj,$GRk */ { FRV_INSN_SCUTSS, "scutss", "scutss", 32, - { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_I0, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } } + { 0|A(AUDIO), { { { (1<<MACH_FR400)|(1<<MACH_FR450), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* scan$pack $GRi,$GRj,$GRk */ { FRV_INSN_SCAN, "scan", "scan", 32, - { 0, { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_SCAN, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* cadd$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CADD, "cadd", "cadd", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* csub$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CSUB, "csub", "csub", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* cand$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CAND, "cand", "cand", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* cor$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_COR, "cor", "cor", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* cxor$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CXOR, "cxor", "cxor", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* cnot$pack $GRj,$GRk,$CCi,$cond */ { FRV_INSN_CNOT, "cnot", "cnot", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */ { FRV_INSN_CSMUL, "csmul", "csmul", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } } }, /* csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CSDIV, "csdiv", "csdiv", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } } }, /* cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CUDIV, "cudiv", "cudiv", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } } }, /* csll$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CSLL, "csll", "csll", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* csrl$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CSRL, "csrl", "csrl", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* csra$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CSRA, "csra", "csra", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* cscan$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CSCAN, "cscan", "cscan", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_SCAN, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* addcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ { FRV_INSN_ADDCC, "addcc", "addcc", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* subcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ { FRV_INSN_SUBCC, "subcc", "subcc", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* andcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ { FRV_INSN_ANDCC, "andcc", "andcc", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* orcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ { FRV_INSN_ORCC, "orcc", "orcc", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* xorcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ { FRV_INSN_XORCC, "xorcc", "xorcc", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* sllcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ { FRV_INSN_SLLCC, "sllcc", "sllcc", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* srlcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ { FRV_INSN_SRLCC, "srlcc", "srlcc", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* sracc$pack $GRi,$GRj,$GRk,$ICCi_1 */ { FRV_INSN_SRACC, "sracc", "sracc", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* smulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */ { FRV_INSN_SMULCC, "smulcc", "smulcc", 32, - { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } } }, /* umulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */ { FRV_INSN_UMULCC, "umulcc", "umulcc", 32, - { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } } }, /* caddcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CADDCC, "caddcc", "caddcc", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* csubcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CSUBCC, "csubcc", "csubcc", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */ { FRV_INSN_CSMULCC, "csmulcc", "csmulcc", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } } }, /* candcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CANDCC, "candcc", "candcc", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* corcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CORCC, "corcc", "corcc", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* cxorcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CXORCC, "cxorcc", "cxorcc", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* csllcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CSLLCC, "csllcc", "csllcc", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* csrlcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CSRLCC, "csrlcc", "csrlcc", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* csracc$pack $GRi,$GRj,$GRk,$CCi,$cond */ { FRV_INSN_CSRACC, "csracc", "csracc", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* addx$pack $GRi,$GRj,$GRk,$ICCi_1 */ { FRV_INSN_ADDX, "addx", "addx", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* subx$pack $GRi,$GRj,$GRk,$ICCi_1 */ { FRV_INSN_SUBX, "subx", "subx", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* addxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ { FRV_INSN_ADDXCC, "addxcc", "addxcc", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* subxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ { FRV_INSN_SUBXCC, "subxcc", "subxcc", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* addss$pack $GRi,$GRj,$GRk */ { FRV_INSN_ADDSS, "addss", "addss", 32, - { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } } + { 0|A(AUDIO), { { { (1<<MACH_FR400)|(1<<MACH_FR450), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* subss$pack $GRi,$GRj,$GRk */ { FRV_INSN_SUBSS, "subss", "subss", 32, - { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } } + { 0|A(AUDIO), { { { (1<<MACH_FR400)|(1<<MACH_FR450), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* addi$pack $GRi,$s12,$GRk */ { FRV_INSN_ADDI, "addi", "addi", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* subi$pack $GRi,$s12,$GRk */ { FRV_INSN_SUBI, "subi", "subi", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* andi$pack $GRi,$s12,$GRk */ { FRV_INSN_ANDI, "andi", "andi", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* ori$pack $GRi,$s12,$GRk */ { FRV_INSN_ORI, "ori", "ori", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* xori$pack $GRi,$s12,$GRk */ { FRV_INSN_XORI, "xori", "xori", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* sdivi$pack $GRi,$s12,$GRk */ { FRV_INSN_SDIVI, "sdivi", "sdivi", 32, - { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } } }, /* nsdivi$pack $GRi,$s12,$GRk */ { FRV_INSN_NSDIVI, "nsdivi", "nsdivi", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } } }, /* udivi$pack $GRi,$s12,$GRk */ { FRV_INSN_UDIVI, "udivi", "udivi", 32, - { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } } }, /* nudivi$pack $GRi,$s12,$GRk */ { FRV_INSN_NUDIVI, "nudivi", "nudivi", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } } }, /* smuli$pack $GRi,$s12,$GRdoublek */ { FRV_INSN_SMULI, "smuli", "smuli", 32, - { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } } }, /* umuli$pack $GRi,$s12,$GRdoublek */ { FRV_INSN_UMULI, "umuli", "umuli", 32, - { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } } }, /* slli$pack $GRi,$s12,$GRk */ { FRV_INSN_SLLI, "slli", "slli", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* srli$pack $GRi,$s12,$GRk */ { FRV_INSN_SRLI, "srli", "srli", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* srai$pack $GRi,$s12,$GRk */ { FRV_INSN_SRAI, "srai", "srai", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* scani$pack $GRi,$s12,$GRk */ { FRV_INSN_SCANI, "scani", "scani", 32, - { 0, { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_SCAN, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* addicc$pack $GRi,$s10,$GRk,$ICCi_1 */ { FRV_INSN_ADDICC, "addicc", "addicc", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* subicc$pack $GRi,$s10,$GRk,$ICCi_1 */ { FRV_INSN_SUBICC, "subicc", "subicc", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* andicc$pack $GRi,$s10,$GRk,$ICCi_1 */ { FRV_INSN_ANDICC, "andicc", "andicc", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* oricc$pack $GRi,$s10,$GRk,$ICCi_1 */ { FRV_INSN_ORICC, "oricc", "oricc", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* xoricc$pack $GRi,$s10,$GRk,$ICCi_1 */ { FRV_INSN_XORICC, "xoricc", "xoricc", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* smulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */ { FRV_INSN_SMULICC, "smulicc", "smulicc", 32, - { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } } }, /* umulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */ { FRV_INSN_UMULICC, "umulicc", "umulicc", 32, - { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } } }, /* sllicc$pack $GRi,$s10,$GRk,$ICCi_1 */ { FRV_INSN_SLLICC, "sllicc", "sllicc", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* srlicc$pack $GRi,$s10,$GRk,$ICCi_1 */ { FRV_INSN_SRLICC, "srlicc", "srlicc", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* sraicc$pack $GRi,$s10,$GRk,$ICCi_1 */ { FRV_INSN_SRAICC, "sraicc", "sraicc", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* addxi$pack $GRi,$s10,$GRk,$ICCi_1 */ { FRV_INSN_ADDXI, "addxi", "addxi", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* subxi$pack $GRi,$s10,$GRk,$ICCi_1 */ { FRV_INSN_SUBXI, "subxi", "subxi", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* addxicc$pack $GRi,$s10,$GRk,$ICCi_1 */ { FRV_INSN_ADDXICC, "addxicc", "addxicc", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* subxicc$pack $GRi,$s10,$GRk,$ICCi_1 */ { FRV_INSN_SUBXICC, "subxicc", "subxicc", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* cmpb$pack $GRi,$GRj,$ICCi_1 */ { FRV_INSN_CMPB, "cmpb", "cmpb", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* cmpba$pack $GRi,$GRj,$ICCi_1 */ { FRV_INSN_CMPBA, "cmpba", "cmpba", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* setlo$pack $ulo16,$GRklo */ { FRV_INSN_SETLO, "setlo", "setlo", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* sethi$pack $uhi16,$GRkhi */ { FRV_INSN_SETHI, "sethi", "sethi", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* setlos$pack $slo16,$GRk */ { FRV_INSN_SETLOS, "setlos", "setlos", 32, - { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } } }, /* ldsb$pack @($GRi,$GRj),$GRk */ { FRV_INSN_LDSB, "ldsb", "ldsb", 32, - { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* ldub$pack @($GRi,$GRj),$GRk */ { FRV_INSN_LDUB, "ldub", "ldub", 32, - { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* ldsh$pack @($GRi,$GRj),$GRk */ { FRV_INSN_LDSH, "ldsh", "ldsh", 32, - { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* lduh$pack @($GRi,$GRj),$GRk */ { FRV_INSN_LDUH, "lduh", "lduh", 32, - { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* ld$pack $ldann($GRi,$GRj),$GRk */ { FRV_INSN_LD, "ld", "ld", 32, - { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* ldbf$pack @($GRi,$GRj),$FRintk */ { FRV_INSN_LDBF, "ldbf", "ldbf", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* ldhf$pack @($GRi,$GRj),$FRintk */ { FRV_INSN_LDHF, "ldhf", "ldhf", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* ldf$pack @($GRi,$GRj),$FRintk */ { FRV_INSN_LDF, "ldf", "ldf", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* ldc$pack @($GRi,$GRj),$CPRk */ { FRV_INSN_LDC, "ldc", "ldc", 32, - { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* nldsb$pack @($GRi,$GRj),$GRk */ { FRV_INSN_NLDSB, "nldsb", "nldsb", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nldub$pack @($GRi,$GRj),$GRk */ { FRV_INSN_NLDUB, "nldub", "nldub", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nldsh$pack @($GRi,$GRj),$GRk */ { FRV_INSN_NLDSH, "nldsh", "nldsh", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nlduh$pack @($GRi,$GRj),$GRk */ { FRV_INSN_NLDUH, "nlduh", "nlduh", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nld$pack @($GRi,$GRj),$GRk */ { FRV_INSN_NLD, "nld", "nld", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nldbf$pack @($GRi,$GRj),$FRintk */ { FRV_INSN_NLDBF, "nldbf", "nldbf", 32, - { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nldhf$pack @($GRi,$GRj),$FRintk */ { FRV_INSN_NLDHF, "nldhf", "nldhf", 32, - { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nldf$pack @($GRi,$GRj),$FRintk */ { FRV_INSN_NLDF, "nldf", "nldf", 32, - { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* ldd$pack $lddann($GRi,$GRj),$GRdoublek */ { FRV_INSN_LDD, "ldd", "ldd", 32, - { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* lddf$pack @($GRi,$GRj),$FRdoublek */ { FRV_INSN_LDDF, "lddf", "lddf", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* lddc$pack @($GRi,$GRj),$CPRdoublek */ { FRV_INSN_LDDC, "lddc", "lddc", 32, - { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nldd$pack @($GRi,$GRj),$GRdoublek */ { FRV_INSN_NLDD, "nldd", "nldd", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nlddf$pack @($GRi,$GRj),$FRdoublek */ { FRV_INSN_NLDDF, "nlddf", "nlddf", 32, - { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* ldq$pack @($GRi,$GRj),$GRk */ { FRV_INSN_LDQ, "ldq", "ldq", 32, - { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* ldqf$pack @($GRi,$GRj),$FRintk */ { FRV_INSN_LDQF, "ldqf", "ldqf", 32, - { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } } + { 0|A(FR_ACCESS), { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* ldqc$pack @($GRi,$GRj),$CPRk */ { FRV_INSN_LDQC, "ldqc", "ldqc", 32, - { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* nldq$pack @($GRi,$GRj),$GRk */ { FRV_INSN_NLDQ, "nldq", "nldq", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* nldqf$pack @($GRi,$GRj),$FRintk */ { FRV_INSN_NLDQF, "nldqf", "nldqf", 32, - { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } } + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* ldsbu$pack @($GRi,$GRj),$GRk */ { FRV_INSN_LDSBU, "ldsbu", "ldsbu", 32, - { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* ldubu$pack @($GRi,$GRj),$GRk */ { FRV_INSN_LDUBU, "ldubu", "ldubu", 32, - { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* ldshu$pack @($GRi,$GRj),$GRk */ { FRV_INSN_LDSHU, "ldshu", "ldshu", 32, - { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* lduhu$pack @($GRi,$GRj),$GRk */ { FRV_INSN_LDUHU, "lduhu", "lduhu", 32, - { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* ldu$pack @($GRi,$GRj),$GRk */ { FRV_INSN_LDU, "ldu", "ldu", 32, - { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nldsbu$pack @($GRi,$GRj),$GRk */ { FRV_INSN_NLDSBU, "nldsbu", "nldsbu", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nldubu$pack @($GRi,$GRj),$GRk */ { FRV_INSN_NLDUBU, "nldubu", "nldubu", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nldshu$pack @($GRi,$GRj),$GRk */ { FRV_INSN_NLDSHU, "nldshu", "nldshu", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nlduhu$pack @($GRi,$GRj),$GRk */ { FRV_INSN_NLDUHU, "nlduhu", "nlduhu", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nldu$pack @($GRi,$GRj),$GRk */ { FRV_INSN_NLDU, "nldu", "nldu", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* ldbfu$pack @($GRi,$GRj),$FRintk */ { FRV_INSN_LDBFU, "ldbfu", "ldbfu", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* ldhfu$pack @($GRi,$GRj),$FRintk */ { FRV_INSN_LDHFU, "ldhfu", "ldhfu", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* ldfu$pack @($GRi,$GRj),$FRintk */ { FRV_INSN_LDFU, "ldfu", "ldfu", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* ldcu$pack @($GRi,$GRj),$CPRk */ { FRV_INSN_LDCU, "ldcu", "ldcu", 32, - { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* nldbfu$pack @($GRi,$GRj),$FRintk */ { FRV_INSN_NLDBFU, "nldbfu", "nldbfu", 32, - { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nldhfu$pack @($GRi,$GRj),$FRintk */ { FRV_INSN_NLDHFU, "nldhfu", "nldhfu", 32, - { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nldfu$pack @($GRi,$GRj),$FRintk */ { FRV_INSN_NLDFU, "nldfu", "nldfu", 32, - { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* lddu$pack @($GRi,$GRj),$GRdoublek */ { FRV_INSN_LDDU, "lddu", "lddu", 32, - { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nlddu$pack @($GRi,$GRj),$GRdoublek */ { FRV_INSN_NLDDU, "nlddu", "nlddu", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* lddfu$pack @($GRi,$GRj),$FRdoublek */ { FRV_INSN_LDDFU, "lddfu", "lddfu", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* lddcu$pack @($GRi,$GRj),$CPRdoublek */ { FRV_INSN_LDDCU, "lddcu", "lddcu", 32, - { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nlddfu$pack @($GRi,$GRj),$FRdoublek */ { FRV_INSN_NLDDFU, "nlddfu", "nlddfu", 32, - { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* ldqu$pack @($GRi,$GRj),$GRk */ { FRV_INSN_LDQU, "ldqu", "ldqu", 32, - { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* nldqu$pack @($GRi,$GRj),$GRk */ { FRV_INSN_NLDQU, "nldqu", "nldqu", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* ldqfu$pack @($GRi,$GRj),$FRintk */ { FRV_INSN_LDQFU, "ldqfu", "ldqfu", 32, - { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } } + { 0|A(FR_ACCESS), { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* ldqcu$pack @($GRi,$GRj),$CPRk */ { FRV_INSN_LDQCU, "ldqcu", "ldqcu", 32, - { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* nldqfu$pack @($GRi,$GRj),$FRintk */ { FRV_INSN_NLDQFU, "nldqfu", "nldqfu", 32, - { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } } + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* ldsbi$pack @($GRi,$d12),$GRk */ { FRV_INSN_LDSBI, "ldsbi", "ldsbi", 32, - { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* ldshi$pack @($GRi,$d12),$GRk */ { FRV_INSN_LDSHI, "ldshi", "ldshi", 32, - { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* ldi$pack @($GRi,$d12),$GRk */ { FRV_INSN_LDI, "ldi", "ldi", 32, - { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* ldubi$pack @($GRi,$d12),$GRk */ { FRV_INSN_LDUBI, "ldubi", "ldubi", 32, - { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* lduhi$pack @($GRi,$d12),$GRk */ { FRV_INSN_LDUHI, "lduhi", "lduhi", 32, - { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* ldbfi$pack @($GRi,$d12),$FRintk */ { FRV_INSN_LDBFI, "ldbfi", "ldbfi", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* ldhfi$pack @($GRi,$d12),$FRintk */ { FRV_INSN_LDHFI, "ldhfi", "ldhfi", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* ldfi$pack @($GRi,$d12),$FRintk */ { FRV_INSN_LDFI, "ldfi", "ldfi", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nldsbi$pack @($GRi,$d12),$GRk */ { FRV_INSN_NLDSBI, "nldsbi", "nldsbi", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nldubi$pack @($GRi,$d12),$GRk */ { FRV_INSN_NLDUBI, "nldubi", "nldubi", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nldshi$pack @($GRi,$d12),$GRk */ { FRV_INSN_NLDSHI, "nldshi", "nldshi", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nlduhi$pack @($GRi,$d12),$GRk */ { FRV_INSN_NLDUHI, "nlduhi", "nlduhi", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nldi$pack @($GRi,$d12),$GRk */ { FRV_INSN_NLDI, "nldi", "nldi", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nldbfi$pack @($GRi,$d12),$FRintk */ { FRV_INSN_NLDBFI, "nldbfi", "nldbfi", 32, - { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nldhfi$pack @($GRi,$d12),$FRintk */ { FRV_INSN_NLDHFI, "nldhfi", "nldhfi", 32, - { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nldfi$pack @($GRi,$d12),$FRintk */ { FRV_INSN_NLDFI, "nldfi", "nldfi", 32, - { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* lddi$pack @($GRi,$d12),$GRdoublek */ { FRV_INSN_LDDI, "lddi", "lddi", 32, - { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* lddfi$pack @($GRi,$d12),$FRdoublek */ { FRV_INSN_LDDFI, "lddfi", "lddfi", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nlddi$pack @($GRi,$d12),$GRdoublek */ { FRV_INSN_NLDDI, "nlddi", "nlddi", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* nlddfi$pack @($GRi,$d12),$FRdoublek */ { FRV_INSN_NLDDFI, "nlddfi", "nlddfi", 32, - { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* ldqi$pack @($GRi,$d12),$GRk */ { FRV_INSN_LDQI, "ldqi", "ldqi", 32, - { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* ldqfi$pack @($GRi,$d12),$FRintk */ { FRV_INSN_LDQFI, "ldqfi", "ldqfi", 32, - { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } } + { 0|A(FR_ACCESS), { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* nldqfi$pack @($GRi,$d12),$FRintk */ { FRV_INSN_NLDQFI, "nldqfi", "nldqfi", 32, - { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } } + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* stb$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_STB, "stb", "stb", 32, - { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* sth$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_STH, "sth", "sth", 32, - { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* st$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_ST, "st", "st", 32, - { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* stbf$pack $FRintk,@($GRi,$GRj) */ { FRV_INSN_STBF, "stbf", "stbf", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* sthf$pack $FRintk,@($GRi,$GRj) */ { FRV_INSN_STHF, "sthf", "sthf", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* stf$pack $FRintk,@($GRi,$GRj) */ { FRV_INSN_STF, "stf", "stf", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* stc$pack $CPRk,@($GRi,$GRj) */ { FRV_INSN_STC, "stc", "stc", 32, - { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* std$pack $GRdoublek,@($GRi,$GRj) */ { FRV_INSN_STD, "std", "std", 32, - { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* stdf$pack $FRdoublek,@($GRi,$GRj) */ { FRV_INSN_STDF, "stdf", "stdf", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* stdc$pack $CPRdoublek,@($GRi,$GRj) */ { FRV_INSN_STDC, "stdc", "stdc", 32, - { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* stq$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_STQ, "stq", "stq", 32, - { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* stqf$pack $FRintk,@($GRi,$GRj) */ { FRV_INSN_STQF, "stqf", "stqf", 32, - { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } } + { 0|A(FR_ACCESS), { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* stqc$pack $CPRk,@($GRi,$GRj) */ { FRV_INSN_STQC, "stqc", "stqc", 32, - { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* stbu$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_STBU, "stbu", "stbu", 32, - { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* sthu$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_STHU, "sthu", "sthu", 32, - { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* stu$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_STU, "stu", "stu", 32, - { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* stbfu$pack $FRintk,@($GRi,$GRj) */ { FRV_INSN_STBFU, "stbfu", "stbfu", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* sthfu$pack $FRintk,@($GRi,$GRj) */ { FRV_INSN_STHFU, "sthfu", "sthfu", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* stfu$pack $FRintk,@($GRi,$GRj) */ { FRV_INSN_STFU, "stfu", "stfu", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* stcu$pack $CPRk,@($GRi,$GRj) */ { FRV_INSN_STCU, "stcu", "stcu", 32, - { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* stdu$pack $GRdoublek,@($GRi,$GRj) */ { FRV_INSN_STDU, "stdu", "stdu", 32, - { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* stdfu$pack $FRdoublek,@($GRi,$GRj) */ { FRV_INSN_STDFU, "stdfu", "stdfu", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* stdcu$pack $CPRdoublek,@($GRi,$GRj) */ { FRV_INSN_STDCU, "stdcu", "stdcu", 32, - { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* stqu$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_STQU, "stqu", "stqu", 32, - { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* stqfu$pack $FRintk,@($GRi,$GRj) */ { FRV_INSN_STQFU, "stqfu", "stqfu", 32, - { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } } + { 0|A(FR_ACCESS), { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* stqcu$pack $CPRk,@($GRi,$GRj) */ { FRV_INSN_STQCU, "stqcu", "stqcu", 32, - { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* cldsb$pack @($GRi,$GRj),$GRk,$CCi,$cond */ { FRV_INSN_CLDSB, "cldsb", "cldsb", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* cldub$pack @($GRi,$GRj),$GRk,$CCi,$cond */ { FRV_INSN_CLDUB, "cldub", "cldub", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* cldsh$pack @($GRi,$GRj),$GRk,$CCi,$cond */ { FRV_INSN_CLDSH, "cldsh", "cldsh", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* clduh$pack @($GRi,$GRj),$GRk,$CCi,$cond */ { FRV_INSN_CLDUH, "clduh", "clduh", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* cld$pack @($GRi,$GRj),$GRk,$CCi,$cond */ { FRV_INSN_CLD, "cld", "cld", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* cldbf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ { FRV_INSN_CLDBF, "cldbf", "cldbf", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* cldhf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ { FRV_INSN_CLDHF, "cldhf", "cldhf", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* cldf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ { FRV_INSN_CLDF, "cldf", "cldf", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* cldd$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */ { FRV_INSN_CLDD, "cldd", "cldd", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* clddf$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */ { FRV_INSN_CLDDF, "clddf", "clddf", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* cldq$pack @($GRi,$GRj),$GRk,$CCi,$cond */ { FRV_INSN_CLDQ, "cldq", "cldq", 32, - { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } } + { 0|A(CONDITIONAL), { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* cldsbu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ { FRV_INSN_CLDSBU, "cldsbu", "cldsbu", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* cldubu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ { FRV_INSN_CLDUBU, "cldubu", "cldubu", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* cldshu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ { FRV_INSN_CLDSHU, "cldshu", "cldshu", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* clduhu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ { FRV_INSN_CLDUHU, "clduhu", "clduhu", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* cldu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ { FRV_INSN_CLDU, "cldu", "cldu", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* cldbfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ { FRV_INSN_CLDBFU, "cldbfu", "cldbfu", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* cldhfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ { FRV_INSN_CLDHFU, "cldhfu", "cldhfu", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* cldfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ { FRV_INSN_CLDFU, "cldfu", "cldfu", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */ { FRV_INSN_CLDDU, "clddu", "clddu", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */ { FRV_INSN_CLDDFU, "clddfu", "clddfu", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } } }, /* cldqu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ { FRV_INSN_CLDQU, "cldqu", "cldqu", 32, - { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } } + { 0|A(CONDITIONAL), { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* cstb$pack $GRk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTB, "cstb", "cstb", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* csth$pack $GRk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTH, "csth", "csth", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* cst$pack $GRk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CST, "cst", "cst", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* cstbf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTBF, "cstbf", "cstbf", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* csthf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTHF, "csthf", "csthf", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* cstf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTF, "cstf", "cstf", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* cstd$pack $GRdoublek,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTD, "cstd", "cstd", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* cstdf$pack $FRdoublek,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTDF, "cstdf", "cstdf", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTQ, "cstq", "cstq", 32, - { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } } + { 0|A(CONDITIONAL), { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* cstbu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTBU, "cstbu", "cstbu", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* csthu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTHU, "csthu", "csthu", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* cstu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTU, "cstu", "cstu", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* cstbfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTBFU, "cstbfu", "cstbfu", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* csthfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTHFU, "csthfu", "csthfu", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* cstfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTFU, "cstfu", "cstfu", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* cstdu$pack $GRdoublek,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTDU, "cstdu", "cstdu", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* cstdfu$pack $FRdoublek,@($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CSTDFU, "cstdfu", "cstdfu", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* stbi$pack $GRk,@($GRi,$d12) */ { FRV_INSN_STBI, "stbi", "stbi", 32, - { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* sthi$pack $GRk,@($GRi,$d12) */ { FRV_INSN_STHI, "sthi", "sthi", 32, - { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* sti$pack $GRk,@($GRi,$d12) */ { FRV_INSN_STI, "sti", "sti", 32, - { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* stbfi$pack $FRintk,@($GRi,$d12) */ { FRV_INSN_STBFI, "stbfi", "stbfi", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* sthfi$pack $FRintk,@($GRi,$d12) */ { FRV_INSN_STHFI, "sthfi", "sthfi", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* stfi$pack $FRintk,@($GRi,$d12) */ { FRV_INSN_STFI, "stfi", "stfi", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* stdi$pack $GRdoublek,@($GRi,$d12) */ { FRV_INSN_STDI, "stdi", "stdi", 32, - { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* stdfi$pack $FRdoublek,@($GRi,$d12) */ { FRV_INSN_STDFI, "stdfi", "stdfi", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } } }, /* stqi$pack $GRk,@($GRi,$d12) */ { FRV_INSN_STQI, "stqi", "stqi", 32, - { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* stqfi$pack $FRintk,@($GRi,$d12) */ { FRV_INSN_STQFI, "stqfi", "stqfi", 32, - { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } } + { 0|A(FR_ACCESS), { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* swap$pack @($GRi,$GRj),$GRk */ { FRV_INSN_SWAP, "swap", "swap", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } } }, /* swapi$pack @($GRi,$d12),$GRk */ { FRV_INSN_SWAPI, "swapi", "swapi", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } } }, /* cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond */ { FRV_INSN_CSWAP, "cswap", "cswap", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } } }, /* movgf$pack $GRj,$FRintk */ { FRV_INSN_MOVGF, "movgf", "movgf", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_4, 0 } }, { { FR450_MAJOR_I_4, 0 } }, { { FR500_MAJOR_I_4, 0 } }, { { FR550_MAJOR_I_5, 0 } } } } }, /* movfg$pack $FRintk,$GRj */ { FRV_INSN_MOVFG, "movfg", "movfg", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_4, 0 } }, { { FR450_MAJOR_I_4, 0 } }, { { FR500_MAJOR_I_4, 0 } }, { { FR550_MAJOR_I_5, 0 } } } } }, /* movgfd$pack $GRj,$FRintk */ { FRV_INSN_MOVGFD, "movgfd", "movgfd", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_4, 0 } }, { { FR450_MAJOR_I_4, 0 } }, { { FR500_MAJOR_I_4, 0 } }, { { FR550_MAJOR_I_5, 0 } } } } }, /* movfgd$pack $FRintk,$GRj */ { FRV_INSN_MOVFGD, "movfgd", "movfgd", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_4, 0 } }, { { FR450_MAJOR_I_4, 0 } }, { { FR500_MAJOR_I_4, 0 } }, { { FR550_MAJOR_I_5, 0 } } } } }, /* movgfq$pack $GRj,$FRintk */ { FRV_INSN_MOVGFQ, "movgfq", "movgfq", 32, - { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_4, FR550_MAJOR_NONE } } + { 0|A(FR_ACCESS), { { { (1<<MACH_FRV), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_4, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* movfgq$pack $FRintk,$GRj */ { FRV_INSN_MOVFGQ, "movfgq", "movfgq", 32, - { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_4, FR550_MAJOR_NONE } } + { 0|A(FR_ACCESS), { { { (1<<MACH_FRV), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_4, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* cmovgf$pack $GRj,$FRintk,$CCi,$cond */ { FRV_INSN_CMOVGF, "cmovgf", "cmovgf", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_4, 0 } }, { { FR450_MAJOR_I_4, 0 } }, { { FR500_MAJOR_I_4, 0 } }, { { FR550_MAJOR_I_5, 0 } } } } }, /* cmovfg$pack $FRintk,$GRj,$CCi,$cond */ { FRV_INSN_CMOVFG, "cmovfg", "cmovfg", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_4, 0 } }, { { FR450_MAJOR_I_4, 0 } }, { { FR500_MAJOR_I_4, 0 } }, { { FR550_MAJOR_I_5, 0 } } } } }, /* cmovgfd$pack $GRj,$FRintk,$CCi,$cond */ { FRV_INSN_CMOVGFD, "cmovgfd", "cmovgfd", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_4, 0 } }, { { FR450_MAJOR_I_4, 0 } }, { { FR500_MAJOR_I_4, 0 } }, { { FR550_MAJOR_I_5, 0 } } } } }, /* cmovfgd$pack $FRintk,$GRj,$CCi,$cond */ { FRV_INSN_CMOVFGD, "cmovfgd", "cmovfgd", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_4, 0 } }, { { FR450_MAJOR_I_4, 0 } }, { { FR500_MAJOR_I_4, 0 } }, { { FR550_MAJOR_I_5, 0 } } } } }, /* movgs$pack $GRj,$spr */ { FRV_INSN_MOVGS, "movgs", "movgs", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } } }, /* movsg$pack $spr,$GRj */ { FRV_INSN_MOVSG, "movsg", "movsg", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } } }, /* bra$pack $hint_taken$label16 */ { FRV_INSN_BRA, "bra", "bra", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* bno$pack$hint_not_taken */ { FRV_INSN_BNO, "bno", "bno", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* beq$pack $ICCi_2,$hint,$label16 */ { FRV_INSN_BEQ, "beq", "beq", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* bne$pack $ICCi_2,$hint,$label16 */ { FRV_INSN_BNE, "bne", "bne", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* ble$pack $ICCi_2,$hint,$label16 */ { FRV_INSN_BLE, "ble", "ble", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* bgt$pack $ICCi_2,$hint,$label16 */ { FRV_INSN_BGT, "bgt", "bgt", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* blt$pack $ICCi_2,$hint,$label16 */ { FRV_INSN_BLT, "blt", "blt", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* bge$pack $ICCi_2,$hint,$label16 */ { FRV_INSN_BGE, "bge", "bge", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* bls$pack $ICCi_2,$hint,$label16 */ { FRV_INSN_BLS, "bls", "bls", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* bhi$pack $ICCi_2,$hint,$label16 */ { FRV_INSN_BHI, "bhi", "bhi", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* bc$pack $ICCi_2,$hint,$label16 */ { FRV_INSN_BC, "bc", "bc", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* bnc$pack $ICCi_2,$hint,$label16 */ { FRV_INSN_BNC, "bnc", "bnc", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* bn$pack $ICCi_2,$hint,$label16 */ { FRV_INSN_BN, "bn", "bn", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* bp$pack $ICCi_2,$hint,$label16 */ { FRV_INSN_BP, "bp", "bp", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* bv$pack $ICCi_2,$hint,$label16 */ { FRV_INSN_BV, "bv", "bv", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* bnv$pack $ICCi_2,$hint,$label16 */ { FRV_INSN_BNV, "bnv", "bnv", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* fbra$pack $hint_taken$label16 */ { FRV_INSN_FBRA, "fbra", "fbra", 32, - { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(FR_ACCESS)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* fbno$pack$hint_not_taken */ { FRV_INSN_FBNO, "fbno", "fbno", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* fbne$pack $FCCi_2,$hint,$label16 */ { FRV_INSN_FBNE, "fbne", "fbne", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* fbeq$pack $FCCi_2,$hint,$label16 */ { FRV_INSN_FBEQ, "fbeq", "fbeq", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* fblg$pack $FCCi_2,$hint,$label16 */ { FRV_INSN_FBLG, "fblg", "fblg", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* fbue$pack $FCCi_2,$hint,$label16 */ { FRV_INSN_FBUE, "fbue", "fbue", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* fbul$pack $FCCi_2,$hint,$label16 */ { FRV_INSN_FBUL, "fbul", "fbul", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* fbge$pack $FCCi_2,$hint,$label16 */ { FRV_INSN_FBGE, "fbge", "fbge", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* fblt$pack $FCCi_2,$hint,$label16 */ { FRV_INSN_FBLT, "fblt", "fblt", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* fbuge$pack $FCCi_2,$hint,$label16 */ { FRV_INSN_FBUGE, "fbuge", "fbuge", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* fbug$pack $FCCi_2,$hint,$label16 */ { FRV_INSN_FBUG, "fbug", "fbug", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* fble$pack $FCCi_2,$hint,$label16 */ { FRV_INSN_FBLE, "fble", "fble", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* fbgt$pack $FCCi_2,$hint,$label16 */ { FRV_INSN_FBGT, "fbgt", "fbgt", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* fbule$pack $FCCi_2,$hint,$label16 */ { FRV_INSN_FBULE, "fbule", "fbule", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* fbu$pack $FCCi_2,$hint,$label16 */ { FRV_INSN_FBU, "fbu", "fbu", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* fbo$pack $FCCi_2,$hint,$label16 */ { FRV_INSN_FBO, "fbo", "fbo", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } } }, /* bctrlr$pack $ccond,$hint */ { FRV_INSN_BCTRLR, "bctrlr", "bctrlr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* bralr$pack$hint_taken */ { FRV_INSN_BRALR, "bralr", "bralr", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* bnolr$pack$hint_not_taken */ { FRV_INSN_BNOLR, "bnolr", "bnolr", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* beqlr$pack $ICCi_2,$hint */ { FRV_INSN_BEQLR, "beqlr", "beqlr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* bnelr$pack $ICCi_2,$hint */ { FRV_INSN_BNELR, "bnelr", "bnelr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* blelr$pack $ICCi_2,$hint */ { FRV_INSN_BLELR, "blelr", "blelr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* bgtlr$pack $ICCi_2,$hint */ { FRV_INSN_BGTLR, "bgtlr", "bgtlr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* bltlr$pack $ICCi_2,$hint */ { FRV_INSN_BLTLR, "bltlr", "bltlr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* bgelr$pack $ICCi_2,$hint */ { FRV_INSN_BGELR, "bgelr", "bgelr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* blslr$pack $ICCi_2,$hint */ { FRV_INSN_BLSLR, "blslr", "blslr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* bhilr$pack $ICCi_2,$hint */ { FRV_INSN_BHILR, "bhilr", "bhilr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* bclr$pack $ICCi_2,$hint */ { FRV_INSN_BCLR, "bclr", "bclr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* bnclr$pack $ICCi_2,$hint */ { FRV_INSN_BNCLR, "bnclr", "bnclr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* bnlr$pack $ICCi_2,$hint */ { FRV_INSN_BNLR, "bnlr", "bnlr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* bplr$pack $ICCi_2,$hint */ { FRV_INSN_BPLR, "bplr", "bplr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* bvlr$pack $ICCi_2,$hint */ { FRV_INSN_BVLR, "bvlr", "bvlr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* bnvlr$pack $ICCi_2,$hint */ { FRV_INSN_BNVLR, "bnvlr", "bnvlr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* fbralr$pack$hint_taken */ { FRV_INSN_FBRALR, "fbralr", "fbralr", 32, - { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(FR_ACCESS)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* fbnolr$pack$hint_not_taken */ { FRV_INSN_FBNOLR, "fbnolr", "fbnolr", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* fbeqlr$pack $FCCi_2,$hint */ { FRV_INSN_FBEQLR, "fbeqlr", "fbeqlr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* fbnelr$pack $FCCi_2,$hint */ { FRV_INSN_FBNELR, "fbnelr", "fbnelr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* fblglr$pack $FCCi_2,$hint */ { FRV_INSN_FBLGLR, "fblglr", "fblglr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* fbuelr$pack $FCCi_2,$hint */ { FRV_INSN_FBUELR, "fbuelr", "fbuelr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* fbullr$pack $FCCi_2,$hint */ { FRV_INSN_FBULLR, "fbullr", "fbullr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* fbgelr$pack $FCCi_2,$hint */ { FRV_INSN_FBGELR, "fbgelr", "fbgelr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* fbltlr$pack $FCCi_2,$hint */ { FRV_INSN_FBLTLR, "fbltlr", "fbltlr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* fbugelr$pack $FCCi_2,$hint */ { FRV_INSN_FBUGELR, "fbugelr", "fbugelr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* fbuglr$pack $FCCi_2,$hint */ { FRV_INSN_FBUGLR, "fbuglr", "fbuglr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* fblelr$pack $FCCi_2,$hint */ { FRV_INSN_FBLELR, "fblelr", "fblelr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* fbgtlr$pack $FCCi_2,$hint */ { FRV_INSN_FBGTLR, "fbgtlr", "fbgtlr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* fbulelr$pack $FCCi_2,$hint */ { FRV_INSN_FBULELR, "fbulelr", "fbulelr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* fbulr$pack $FCCi_2,$hint */ { FRV_INSN_FBULR, "fbulr", "fbulr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* fbolr$pack $FCCi_2,$hint */ { FRV_INSN_FBOLR, "fbolr", "fbolr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } } }, /* bcralr$pack $ccond$hint_taken */ { FRV_INSN_BCRALR, "bcralr", "bcralr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* bcnolr$pack$hint_not_taken */ { FRV_INSN_BCNOLR, "bcnolr", "bcnolr", 32, - { 0, { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* bceqlr$pack $ICCi_2,$ccond,$hint */ { FRV_INSN_BCEQLR, "bceqlr", "bceqlr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* bcnelr$pack $ICCi_2,$ccond,$hint */ { FRV_INSN_BCNELR, "bcnelr", "bcnelr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* bclelr$pack $ICCi_2,$ccond,$hint */ { FRV_INSN_BCLELR, "bclelr", "bclelr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* bcgtlr$pack $ICCi_2,$ccond,$hint */ { FRV_INSN_BCGTLR, "bcgtlr", "bcgtlr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* bcltlr$pack $ICCi_2,$ccond,$hint */ { FRV_INSN_BCLTLR, "bcltlr", "bcltlr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* bcgelr$pack $ICCi_2,$ccond,$hint */ { FRV_INSN_BCGELR, "bcgelr", "bcgelr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* bclslr$pack $ICCi_2,$ccond,$hint */ { FRV_INSN_BCLSLR, "bclslr", "bclslr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* bchilr$pack $ICCi_2,$ccond,$hint */ { FRV_INSN_BCHILR, "bchilr", "bchilr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* bcclr$pack $ICCi_2,$ccond,$hint */ { FRV_INSN_BCCLR, "bcclr", "bcclr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* bcnclr$pack $ICCi_2,$ccond,$hint */ { FRV_INSN_BCNCLR, "bcnclr", "bcnclr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* bcnlr$pack $ICCi_2,$ccond,$hint */ { FRV_INSN_BCNLR, "bcnlr", "bcnlr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* bcplr$pack $ICCi_2,$ccond,$hint */ { FRV_INSN_BCPLR, "bcplr", "bcplr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* bcvlr$pack $ICCi_2,$ccond,$hint */ { FRV_INSN_BCVLR, "bcvlr", "bcvlr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* bcnvlr$pack $ICCi_2,$ccond,$hint */ { FRV_INSN_BCNVLR, "bcnvlr", "bcnvlr", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* fcbralr$pack $ccond$hint_taken */ { FRV_INSN_FCBRALR, "fcbralr", "fcbralr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* fcbnolr$pack$hint_not_taken */ { FRV_INSN_FCBNOLR, "fcbnolr", "fcbnolr", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* fcbeqlr$pack $FCCi_2,$ccond,$hint */ { FRV_INSN_FCBEQLR, "fcbeqlr", "fcbeqlr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* fcbnelr$pack $FCCi_2,$ccond,$hint */ { FRV_INSN_FCBNELR, "fcbnelr", "fcbnelr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* fcblglr$pack $FCCi_2,$ccond,$hint */ { FRV_INSN_FCBLGLR, "fcblglr", "fcblglr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* fcbuelr$pack $FCCi_2,$ccond,$hint */ { FRV_INSN_FCBUELR, "fcbuelr", "fcbuelr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* fcbullr$pack $FCCi_2,$ccond,$hint */ { FRV_INSN_FCBULLR, "fcbullr", "fcbullr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* fcbgelr$pack $FCCi_2,$ccond,$hint */ { FRV_INSN_FCBGELR, "fcbgelr", "fcbgelr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* fcbltlr$pack $FCCi_2,$ccond,$hint */ { FRV_INSN_FCBLTLR, "fcbltlr", "fcbltlr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* fcbugelr$pack $FCCi_2,$ccond,$hint */ { FRV_INSN_FCBUGELR, "fcbugelr", "fcbugelr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* fcbuglr$pack $FCCi_2,$ccond,$hint */ { FRV_INSN_FCBUGLR, "fcbuglr", "fcbuglr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* fcblelr$pack $FCCi_2,$ccond,$hint */ { FRV_INSN_FCBLELR, "fcblelr", "fcblelr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* fcbgtlr$pack $FCCi_2,$ccond,$hint */ { FRV_INSN_FCBGTLR, "fcbgtlr", "fcbgtlr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* fcbulelr$pack $FCCi_2,$ccond,$hint */ { FRV_INSN_FCBULELR, "fcbulelr", "fcbulelr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* fcbulr$pack $FCCi_2,$ccond,$hint */ { FRV_INSN_FCBULR, "fcbulr", "fcbulr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* fcbolr$pack $FCCi_2,$ccond,$hint */ { FRV_INSN_FCBOLR, "fcbolr", "fcbolr", 32, - { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } } + { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } } }, /* jmpl$pack @($GRi,$GRj) */ { FRV_INSN_JMPL, "jmpl", "jmpl", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_5, 0 } }, { { FR450_MAJOR_I_5, 0 } }, { { FR500_MAJOR_I_5, 0 } }, { { FR550_MAJOR_I_6, 0 } } } } }, /* calll$pack $callann($GRi,$GRj) */ { FRV_INSN_CALLL, "calll", "calll", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_5, 0 } }, { { FR450_MAJOR_I_5, 0 } }, { { FR500_MAJOR_I_5, 0 } }, { { FR550_MAJOR_I_6, 0 } } } } }, /* jmpil$pack @($GRi,$s12) */ { FRV_INSN_JMPIL, "jmpil", "jmpil", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_5, 0 } }, { { FR450_MAJOR_I_5, 0 } }, { { FR500_MAJOR_I_5, 0 } }, { { FR550_MAJOR_I_6, 0 } } } } }, /* callil$pack @($GRi,$s12) */ { FRV_INSN_CALLIL, "callil", "callil", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_5, 0 } }, { { FR450_MAJOR_I_5, 0 } }, { { FR500_MAJOR_I_5, 0 } }, { { FR550_MAJOR_I_6, 0 } } } } }, /* call$pack $label24 */ { FRV_INSN_CALL, "call", "call", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_4, FR450_MAJOR_B_4, FR500_MAJOR_B_4, FR550_MAJOR_B_4 } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_4, 0 } }, { { FR450_MAJOR_B_4, 0 } }, { { FR500_MAJOR_B_4, 0 } }, { { FR550_MAJOR_B_4, 0 } } } } }, /* rett$pack $debug */ { FRV_INSN_RETT, "rett", "rett", 32, - { 0|A(PRIVILEGED)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } } + { 0|A(PRIVILEGED)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } } }, /* rei$pack $eir */ { FRV_INSN_REI, "rei", "rei", 32, - { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_1, FR550_MAJOR_NONE } } + { 0|A(PRIVILEGED), { { { (1<<MACH_FRV), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* tra$pack $GRi,$GRj */ { FRV_INSN_TRA, "tra", "tra", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tno$pack */ { FRV_INSN_TNO, "tno", "tno", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* teq$pack $ICCi_2,$GRi,$GRj */ { FRV_INSN_TEQ, "teq", "teq", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tne$pack $ICCi_2,$GRi,$GRj */ { FRV_INSN_TNE, "tne", "tne", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tle$pack $ICCi_2,$GRi,$GRj */ { FRV_INSN_TLE, "tle", "tle", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tgt$pack $ICCi_2,$GRi,$GRj */ { FRV_INSN_TGT, "tgt", "tgt", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tlt$pack $ICCi_2,$GRi,$GRj */ { FRV_INSN_TLT, "tlt", "tlt", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tge$pack $ICCi_2,$GRi,$GRj */ { FRV_INSN_TGE, "tge", "tge", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tls$pack $ICCi_2,$GRi,$GRj */ { FRV_INSN_TLS, "tls", "tls", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* thi$pack $ICCi_2,$GRi,$GRj */ { FRV_INSN_THI, "thi", "thi", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tc$pack $ICCi_2,$GRi,$GRj */ { FRV_INSN_TC, "tc", "tc", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tnc$pack $ICCi_2,$GRi,$GRj */ { FRV_INSN_TNC, "tnc", "tnc", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tn$pack $ICCi_2,$GRi,$GRj */ { FRV_INSN_TN, "tn", "tn", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tp$pack $ICCi_2,$GRi,$GRj */ { FRV_INSN_TP, "tp", "tp", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tv$pack $ICCi_2,$GRi,$GRj */ { FRV_INSN_TV, "tv", "tv", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tnv$pack $ICCi_2,$GRi,$GRj */ { FRV_INSN_TNV, "tnv", "tnv", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftra$pack $GRi,$GRj */ { FRV_INSN_FTRA, "ftra", "ftra", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftno$pack */ { FRV_INSN_FTNO, "ftno", "ftno", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftne$pack $FCCi_2,$GRi,$GRj */ { FRV_INSN_FTNE, "ftne", "ftne", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* fteq$pack $FCCi_2,$GRi,$GRj */ { FRV_INSN_FTEQ, "fteq", "fteq", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftlg$pack $FCCi_2,$GRi,$GRj */ { FRV_INSN_FTLG, "ftlg", "ftlg", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftue$pack $FCCi_2,$GRi,$GRj */ { FRV_INSN_FTUE, "ftue", "ftue", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftul$pack $FCCi_2,$GRi,$GRj */ { FRV_INSN_FTUL, "ftul", "ftul", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftge$pack $FCCi_2,$GRi,$GRj */ { FRV_INSN_FTGE, "ftge", "ftge", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftlt$pack $FCCi_2,$GRi,$GRj */ { FRV_INSN_FTLT, "ftlt", "ftlt", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftuge$pack $FCCi_2,$GRi,$GRj */ { FRV_INSN_FTUGE, "ftuge", "ftuge", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftug$pack $FCCi_2,$GRi,$GRj */ { FRV_INSN_FTUG, "ftug", "ftug", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftle$pack $FCCi_2,$GRi,$GRj */ { FRV_INSN_FTLE, "ftle", "ftle", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftgt$pack $FCCi_2,$GRi,$GRj */ { FRV_INSN_FTGT, "ftgt", "ftgt", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftule$pack $FCCi_2,$GRi,$GRj */ { FRV_INSN_FTULE, "ftule", "ftule", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftu$pack $FCCi_2,$GRi,$GRj */ { FRV_INSN_FTU, "ftu", "ftu", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* fto$pack $FCCi_2,$GRi,$GRj */ { FRV_INSN_FTO, "fto", "fto", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tira$pack $GRi,$s12 */ { FRV_INSN_TIRA, "tira", "tira", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tino$pack */ { FRV_INSN_TINO, "tino", "tino", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tieq$pack $ICCi_2,$GRi,$s12 */ { FRV_INSN_TIEQ, "tieq", "tieq", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tine$pack $ICCi_2,$GRi,$s12 */ { FRV_INSN_TINE, "tine", "tine", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tile$pack $ICCi_2,$GRi,$s12 */ { FRV_INSN_TILE, "tile", "tile", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tigt$pack $ICCi_2,$GRi,$s12 */ { FRV_INSN_TIGT, "tigt", "tigt", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tilt$pack $ICCi_2,$GRi,$s12 */ { FRV_INSN_TILT, "tilt", "tilt", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tige$pack $ICCi_2,$GRi,$s12 */ { FRV_INSN_TIGE, "tige", "tige", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tils$pack $ICCi_2,$GRi,$s12 */ { FRV_INSN_TILS, "tils", "tils", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tihi$pack $ICCi_2,$GRi,$s12 */ { FRV_INSN_TIHI, "tihi", "tihi", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tic$pack $ICCi_2,$GRi,$s12 */ { FRV_INSN_TIC, "tic", "tic", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tinc$pack $ICCi_2,$GRi,$s12 */ { FRV_INSN_TINC, "tinc", "tinc", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tin$pack $ICCi_2,$GRi,$s12 */ { FRV_INSN_TIN, "tin", "tin", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tip$pack $ICCi_2,$GRi,$s12 */ { FRV_INSN_TIP, "tip", "tip", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tiv$pack $ICCi_2,$GRi,$s12 */ { FRV_INSN_TIV, "tiv", "tiv", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* tinv$pack $ICCi_2,$GRi,$s12 */ { FRV_INSN_TINV, "tinv", "tinv", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftira$pack $GRi,$s12 */ { FRV_INSN_FTIRA, "ftira", "ftira", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftino$pack */ { FRV_INSN_FTINO, "ftino", "ftino", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftine$pack $FCCi_2,$GRi,$s12 */ { FRV_INSN_FTINE, "ftine", "ftine", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftieq$pack $FCCi_2,$GRi,$s12 */ { FRV_INSN_FTIEQ, "ftieq", "ftieq", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftilg$pack $FCCi_2,$GRi,$s12 */ { FRV_INSN_FTILG, "ftilg", "ftilg", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftiue$pack $FCCi_2,$GRi,$s12 */ { FRV_INSN_FTIUE, "ftiue", "ftiue", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftiul$pack $FCCi_2,$GRi,$s12 */ { FRV_INSN_FTIUL, "ftiul", "ftiul", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftige$pack $FCCi_2,$GRi,$s12 */ { FRV_INSN_FTIGE, "ftige", "ftige", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftilt$pack $FCCi_2,$GRi,$s12 */ { FRV_INSN_FTILT, "ftilt", "ftilt", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftiuge$pack $FCCi_2,$GRi,$s12 */ { FRV_INSN_FTIUGE, "ftiuge", "ftiuge", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftiug$pack $FCCi_2,$GRi,$s12 */ { FRV_INSN_FTIUG, "ftiug", "ftiug", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftile$pack $FCCi_2,$GRi,$s12 */ { FRV_INSN_FTILE, "ftile", "ftile", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftigt$pack $FCCi_2,$GRi,$s12 */ { FRV_INSN_FTIGT, "ftigt", "ftigt", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftiule$pack $FCCi_2,$GRi,$s12 */ { FRV_INSN_FTIULE, "ftiule", "ftiule", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftiu$pack $FCCi_2,$GRi,$s12 */ { FRV_INSN_FTIU, "ftiu", "ftiu", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* ftio$pack $FCCi_2,$GRi,$s12 */ { FRV_INSN_FTIO, "ftio", "ftio", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* break$pack */ { FRV_INSN_BREAK, "break", "break", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* mtrap$pack */ { FRV_INSN_MTRAP, "mtrap", "mtrap", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } } }, /* andcr$pack $CRi,$CRj,$CRk */ { FRV_INSN_ANDCR, "andcr", "andcr", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_6, 0 } }, { { FR450_MAJOR_B_6, 0 } }, { { FR500_MAJOR_B_6, 0 } }, { { FR550_MAJOR_B_6, 0 } } } } }, /* orcr$pack $CRi,$CRj,$CRk */ { FRV_INSN_ORCR, "orcr", "orcr", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_6, 0 } }, { { FR450_MAJOR_B_6, 0 } }, { { FR500_MAJOR_B_6, 0 } }, { { FR550_MAJOR_B_6, 0 } } } } }, /* xorcr$pack $CRi,$CRj,$CRk */ { FRV_INSN_XORCR, "xorcr", "xorcr", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_6, 0 } }, { { FR450_MAJOR_B_6, 0 } }, { { FR500_MAJOR_B_6, 0 } }, { { FR550_MAJOR_B_6, 0 } } } } }, /* nandcr$pack $CRi,$CRj,$CRk */ { FRV_INSN_NANDCR, "nandcr", "nandcr", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_6, 0 } }, { { FR450_MAJOR_B_6, 0 } }, { { FR500_MAJOR_B_6, 0 } }, { { FR550_MAJOR_B_6, 0 } } } } }, /* norcr$pack $CRi,$CRj,$CRk */ { FRV_INSN_NORCR, "norcr", "norcr", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_6, 0 } }, { { FR450_MAJOR_B_6, 0 } }, { { FR500_MAJOR_B_6, 0 } }, { { FR550_MAJOR_B_6, 0 } } } } }, /* andncr$pack $CRi,$CRj,$CRk */ { FRV_INSN_ANDNCR, "andncr", "andncr", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_6, 0 } }, { { FR450_MAJOR_B_6, 0 } }, { { FR500_MAJOR_B_6, 0 } }, { { FR550_MAJOR_B_6, 0 } } } } }, /* orncr$pack $CRi,$CRj,$CRk */ { FRV_INSN_ORNCR, "orncr", "orncr", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_6, 0 } }, { { FR450_MAJOR_B_6, 0 } }, { { FR500_MAJOR_B_6, 0 } }, { { FR550_MAJOR_B_6, 0 } } } } }, /* nandncr$pack $CRi,$CRj,$CRk */ { FRV_INSN_NANDNCR, "nandncr", "nandncr", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_6, 0 } }, { { FR450_MAJOR_B_6, 0 } }, { { FR500_MAJOR_B_6, 0 } }, { { FR550_MAJOR_B_6, 0 } } } } }, /* norncr$pack $CRi,$CRj,$CRk */ { FRV_INSN_NORNCR, "norncr", "norncr", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_6, 0 } }, { { FR450_MAJOR_B_6, 0 } }, { { FR500_MAJOR_B_6, 0 } }, { { FR550_MAJOR_B_6, 0 } } } } }, /* notcr$pack $CRj,$CRk */ { FRV_INSN_NOTCR, "notcr", "notcr", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_6, 0 } }, { { FR450_MAJOR_B_6, 0 } }, { { FR500_MAJOR_B_6, 0 } }, { { FR550_MAJOR_B_6, 0 } } } } }, /* ckra$pack $CRj_int */ { FRV_INSN_CKRA, "ckra", "ckra", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* ckno$pack $CRj_int */ { FRV_INSN_CKNO, "ckno", "ckno", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* ckeq$pack $ICCi_3,$CRj_int */ { FRV_INSN_CKEQ, "ckeq", "ckeq", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* ckne$pack $ICCi_3,$CRj_int */ { FRV_INSN_CKNE, "ckne", "ckne", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* ckle$pack $ICCi_3,$CRj_int */ { FRV_INSN_CKLE, "ckle", "ckle", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* ckgt$pack $ICCi_3,$CRj_int */ { FRV_INSN_CKGT, "ckgt", "ckgt", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cklt$pack $ICCi_3,$CRj_int */ { FRV_INSN_CKLT, "cklt", "cklt", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* ckge$pack $ICCi_3,$CRj_int */ { FRV_INSN_CKGE, "ckge", "ckge", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* ckls$pack $ICCi_3,$CRj_int */ { FRV_INSN_CKLS, "ckls", "ckls", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* ckhi$pack $ICCi_3,$CRj_int */ { FRV_INSN_CKHI, "ckhi", "ckhi", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* ckc$pack $ICCi_3,$CRj_int */ { FRV_INSN_CKC, "ckc", "ckc", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cknc$pack $ICCi_3,$CRj_int */ { FRV_INSN_CKNC, "cknc", "cknc", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* ckn$pack $ICCi_3,$CRj_int */ { FRV_INSN_CKN, "ckn", "ckn", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* ckp$pack $ICCi_3,$CRj_int */ { FRV_INSN_CKP, "ckp", "ckp", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* ckv$pack $ICCi_3,$CRj_int */ { FRV_INSN_CKV, "ckv", "ckv", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cknv$pack $ICCi_3,$CRj_int */ { FRV_INSN_CKNV, "cknv", "cknv", 32, - { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* fckra$pack $CRj_float */ { FRV_INSN_FCKRA, "fckra", "fckra", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* fckno$pack $CRj_float */ { FRV_INSN_FCKNO, "fckno", "fckno", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* fckne$pack $FCCi_3,$CRj_float */ { FRV_INSN_FCKNE, "fckne", "fckne", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* fckeq$pack $FCCi_3,$CRj_float */ { FRV_INSN_FCKEQ, "fckeq", "fckeq", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* fcklg$pack $FCCi_3,$CRj_float */ { FRV_INSN_FCKLG, "fcklg", "fcklg", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* fckue$pack $FCCi_3,$CRj_float */ { FRV_INSN_FCKUE, "fckue", "fckue", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* fckul$pack $FCCi_3,$CRj_float */ { FRV_INSN_FCKUL, "fckul", "fckul", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* fckge$pack $FCCi_3,$CRj_float */ { FRV_INSN_FCKGE, "fckge", "fckge", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* fcklt$pack $FCCi_3,$CRj_float */ { FRV_INSN_FCKLT, "fcklt", "fcklt", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* fckuge$pack $FCCi_3,$CRj_float */ { FRV_INSN_FCKUGE, "fckuge", "fckuge", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* fckug$pack $FCCi_3,$CRj_float */ { FRV_INSN_FCKUG, "fckug", "fckug", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* fckle$pack $FCCi_3,$CRj_float */ { FRV_INSN_FCKLE, "fckle", "fckle", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* fckgt$pack $FCCi_3,$CRj_float */ { FRV_INSN_FCKGT, "fckgt", "fckgt", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* fckule$pack $FCCi_3,$CRj_float */ { FRV_INSN_FCKULE, "fckule", "fckule", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* fcku$pack $FCCi_3,$CRj_float */ { FRV_INSN_FCKU, "fcku", "fcku", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* fcko$pack $FCCi_3,$CRj_float */ { FRV_INSN_FCKO, "fcko", "fcko", 32, - { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cckra$pack $CRj_int,$CCi,$cond */ { FRV_INSN_CCKRA, "cckra", "cckra", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cckno$pack $CRj_int,$CCi,$cond */ { FRV_INSN_CCKNO, "cckno", "cckno", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cckeq$pack $ICCi_3,$CRj_int,$CCi,$cond */ { FRV_INSN_CCKEQ, "cckeq", "cckeq", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cckne$pack $ICCi_3,$CRj_int,$CCi,$cond */ { FRV_INSN_CCKNE, "cckne", "cckne", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cckle$pack $ICCi_3,$CRj_int,$CCi,$cond */ { FRV_INSN_CCKLE, "cckle", "cckle", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cckgt$pack $ICCi_3,$CRj_int,$CCi,$cond */ { FRV_INSN_CCKGT, "cckgt", "cckgt", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* ccklt$pack $ICCi_3,$CRj_int,$CCi,$cond */ { FRV_INSN_CCKLT, "ccklt", "ccklt", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cckge$pack $ICCi_3,$CRj_int,$CCi,$cond */ { FRV_INSN_CCKGE, "cckge", "cckge", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cckls$pack $ICCi_3,$CRj_int,$CCi,$cond */ { FRV_INSN_CCKLS, "cckls", "cckls", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cckhi$pack $ICCi_3,$CRj_int,$CCi,$cond */ { FRV_INSN_CCKHI, "cckhi", "cckhi", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cckc$pack $ICCi_3,$CRj_int,$CCi,$cond */ { FRV_INSN_CCKC, "cckc", "cckc", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* ccknc$pack $ICCi_3,$CRj_int,$CCi,$cond */ { FRV_INSN_CCKNC, "ccknc", "ccknc", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cckn$pack $ICCi_3,$CRj_int,$CCi,$cond */ { FRV_INSN_CCKN, "cckn", "cckn", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cckp$pack $ICCi_3,$CRj_int,$CCi,$cond */ { FRV_INSN_CCKP, "cckp", "cckp", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cckv$pack $ICCi_3,$CRj_int,$CCi,$cond */ { FRV_INSN_CCKV, "cckv", "cckv", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* ccknv$pack $ICCi_3,$CRj_int,$CCi,$cond */ { FRV_INSN_CCKNV, "ccknv", "ccknv", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cfckra$pack $CRj_float,$CCi,$cond */ { FRV_INSN_CFCKRA, "cfckra", "cfckra", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cfckno$pack $CRj_float,$CCi,$cond */ { FRV_INSN_CFCKNO, "cfckno", "cfckno", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cfckne$pack $FCCi_3,$CRj_float,$CCi,$cond */ { FRV_INSN_CFCKNE, "cfckne", "cfckne", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cfckeq$pack $FCCi_3,$CRj_float,$CCi,$cond */ { FRV_INSN_CFCKEQ, "cfckeq", "cfckeq", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cfcklg$pack $FCCi_3,$CRj_float,$CCi,$cond */ { FRV_INSN_CFCKLG, "cfcklg", "cfcklg", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cfckue$pack $FCCi_3,$CRj_float,$CCi,$cond */ { FRV_INSN_CFCKUE, "cfckue", "cfckue", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cfckul$pack $FCCi_3,$CRj_float,$CCi,$cond */ { FRV_INSN_CFCKUL, "cfckul", "cfckul", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cfckge$pack $FCCi_3,$CRj_float,$CCi,$cond */ { FRV_INSN_CFCKGE, "cfckge", "cfckge", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cfcklt$pack $FCCi_3,$CRj_float,$CCi,$cond */ { FRV_INSN_CFCKLT, "cfcklt", "cfcklt", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cfckuge$pack $FCCi_3,$CRj_float,$CCi,$cond */ { FRV_INSN_CFCKUGE, "cfckuge", "cfckuge", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cfckug$pack $FCCi_3,$CRj_float,$CCi,$cond */ { FRV_INSN_CFCKUG, "cfckug", "cfckug", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cfckle$pack $FCCi_3,$CRj_float,$CCi,$cond */ { FRV_INSN_CFCKLE, "cfckle", "cfckle", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cfckgt$pack $FCCi_3,$CRj_float,$CCi,$cond */ { FRV_INSN_CFCKGT, "cfckgt", "cfckgt", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cfckule$pack $FCCi_3,$CRj_float,$CCi,$cond */ { FRV_INSN_CFCKULE, "cfckule", "cfckule", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cfcku$pack $FCCi_3,$CRj_float,$CCi,$cond */ { FRV_INSN_CFCKU, "cfcku", "cfcku", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cfcko$pack $FCCi_3,$CRj_float,$CCi,$cond */ { FRV_INSN_CFCKO, "cfcko", "cfcko", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } } }, /* cjmpl$pack @($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CJMPL, "cjmpl", "cjmpl", 32, - { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } } + { 0|A(CONDITIONAL)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_5, 0 } }, { { FR450_MAJOR_I_5, 0 } }, { { FR500_MAJOR_I_5, 0 } }, { { FR550_MAJOR_I_6, 0 } } } } }, /* ccalll$pack @($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CCALLL, "ccalll", "ccalll", 32, - { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } } + { 0|A(CONDITIONAL)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_5, 0 } }, { { FR450_MAJOR_I_5, 0 } }, { { FR500_MAJOR_I_5, 0 } }, { { FR550_MAJOR_I_6, 0 } } } } }, /* ici$pack @($GRi,$GRj) */ { FRV_INSN_ICI, "ici", "ici", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } } }, /* dci$pack @($GRi,$GRj) */ { FRV_INSN_DCI, "dci", "dci", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } } }, /* icei$pack @($GRi,$GRj),$ae */ { FRV_INSN_ICEI, "icei", "icei", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_C_2 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_C_2, 0 } } } } }, /* dcei$pack @($GRi,$GRj),$ae */ { FRV_INSN_DCEI, "dcei", "dcei", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_C_2 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_C_2, 0 } } } } }, /* dcf$pack @($GRi,$GRj) */ { FRV_INSN_DCF, "dcf", "dcf", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } } }, /* dcef$pack @($GRi,$GRj),$ae */ { FRV_INSN_DCEF, "dcef", "dcef", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_C_2 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_C_2, 0 } } } } }, /* witlb$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_WITLB, "witlb", "witlb", 32, - { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } } + { 0|A(PRIVILEGED), { { { (1<<MACH_FRV), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* wdtlb$pack $GRk,@($GRi,$GRj) */ { FRV_INSN_WDTLB, "wdtlb", "wdtlb", 32, - { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } } + { 0|A(PRIVILEGED), { { { (1<<MACH_FRV), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* itlbi$pack @($GRi,$GRj) */ { FRV_INSN_ITLBI, "itlbi", "itlbi", 32, - { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } } + { 0|A(PRIVILEGED), { { { (1<<MACH_FRV), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* dtlbi$pack @($GRi,$GRj) */ { FRV_INSN_DTLBI, "dtlbi", "dtlbi", 32, - { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } } + { 0|A(PRIVILEGED), { { { (1<<MACH_FRV), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* icpl$pack $GRi,$GRj,$lock */ { FRV_INSN_ICPL, "icpl", "icpl", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } } }, /* dcpl$pack $GRi,$GRj,$lock */ { FRV_INSN_DCPL, "dcpl", "dcpl", 32, - { 0, { (1<<MACH_BASE), UNIT_DCPL, FR400_MAJOR_C_2, FR450_MAJOR_I_2, FR500_MAJOR_C_2, FR550_MAJOR_I_8 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_DCPL, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_I_8, 0 } } } } }, /* icul$pack $GRi */ { FRV_INSN_ICUL, "icul", "icul", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } } }, /* dcul$pack $GRi */ { FRV_INSN_DCUL, "dcul", "dcul", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } } }, /* bar$pack */ { FRV_INSN_BAR, "bar", "bar", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } } }, /* membar$pack */ { FRV_INSN_MEMBAR, "membar", "membar", 32, - { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } } }, /* lrai$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */ { FRV_INSN_LRAI, "lrai", "lrai", 32, - { 0, { (1<<MACH_FR450), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FR450), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* lrad$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */ { FRV_INSN_LRAD, "lrad", "lrad", 32, - { 0, { (1<<MACH_FR450), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FR450), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* tlbpr$pack $GRi,$GRj,$TLBPRopx,$TLBPRL */ { FRV_INSN_TLBPR, "tlbpr", "tlbpr", 32, - { 0, { (1<<MACH_FR450), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FR450), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */ { FRV_INSN_COP1, "cop1", "cop1", 32, - { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* cop2$pack $s6_1,$CPRi,$CPRj,$CPRk */ { FRV_INSN_COP2, "cop2", "cop2", 32, - { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* clrgr$pack $GRk */ { FRV_INSN_CLRGR, "clrgr", "clrgr", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_I01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_6, 0 } }, { { FR550_MAJOR_I_7, 0 } } } } }, /* clrfr$pack $FRk */ { FRV_INSN_CLRFR, "clrfr", "clrfr", 32, - { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_I01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_6, 0 } }, { { FR550_MAJOR_I_7, 0 } } } } }, /* clrga$pack */ { FRV_INSN_CLRGA, "clrga", "clrga", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_I01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_6, 0 } }, { { FR550_MAJOR_I_7, 0 } } } } }, /* clrfa$pack */ { FRV_INSN_CLRFA, "clrfa", "clrfa", 32, - { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_I01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_6, 0 } }, { { FR550_MAJOR_I_7, 0 } } } } }, /* commitgr$pack $GRk */ { FRV_INSN_COMMITGR, "commitgr", "commitgr", 32, - { 0, { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } } + { 0, { { { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), 0 } }, { { UNIT_I01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_6, 0 } }, { { FR550_MAJOR_I_7, 0 } } } } }, /* commitfr$pack $FRk */ { FRV_INSN_COMMITFR, "commitfr", "commitfr", 32, - { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), 0 } }, { { UNIT_I01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_6, 0 } }, { { FR550_MAJOR_I_7, 0 } } } } }, /* commitga$pack */ { FRV_INSN_COMMITGA, "commitga", "commitga", 32, - { 0, { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } } + { 0, { { { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), 0 } }, { { UNIT_I01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_6, 0 } }, { { FR550_MAJOR_I_7, 0 } } } } }, /* commitfa$pack */ { FRV_INSN_COMMITFA, "commitfa", "commitfa", 32, - { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } } + { 0|A(FR_ACCESS), { { { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), 0 } }, { { UNIT_I01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_6, 0 } }, { { FR550_MAJOR_I_7, 0 } } } } }, /* fitos$pack $FRintj,$FRk */ { FRV_INSN_FITOS, "fitos", "fitos", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_F_2, 0 } } } } }, /* fstoi$pack $FRj,$FRintk */ { FRV_INSN_FSTOI, "fstoi", "fstoi", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_F_2, 0 } } } } }, /* fitod$pack $FRintj,$FRdoublek */ { FRV_INSN_FITOD, "fitod", "fitod", 32, - { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* fdtoi$pack $FRdoublej,$FRintk */ { FRV_INSN_FDTOI, "fdtoi", "fdtoi", 32, - { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* fditos$pack $FRintj,$FRk */ { FRV_INSN_FDITOS, "fditos", "fditos", 32, - { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* fdstoi$pack $FRj,$FRintk */ { FRV_INSN_FDSTOI, "fdstoi", "fdstoi", 32, - { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* nfditos$pack $FRintj,$FRk */ { FRV_INSN_NFDITOS, "nfditos", "nfditos", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* nfdstoi$pack $FRj,$FRintk */ { FRV_INSN_NFDSTOI, "nfdstoi", "nfdstoi", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* cfitos$pack $FRintj,$FRk,$CCi,$cond */ { FRV_INSN_CFITOS, "cfitos", "cfitos", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_F_2, 0 } } } } }, /* cfstoi$pack $FRj,$FRintk,$CCi,$cond */ { FRV_INSN_CFSTOI, "cfstoi", "cfstoi", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_F_2, 0 } } } } }, /* nfitos$pack $FRintj,$FRk */ { FRV_INSN_NFITOS, "nfitos", "nfitos", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_F_2, 0 } } } } }, /* nfstoi$pack $FRj,$FRintk */ { FRV_INSN_NFSTOI, "nfstoi", "nfstoi", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_F_2, 0 } } } } }, /* fmovs$pack $FRj,$FRk */ { FRV_INSN_FMOVS, "fmovs", "fmovs", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_F_2, 0 } } } } }, /* fmovd$pack $FRdoublej,$FRdoublek */ { FRV_INSN_FMOVD, "fmovd", "fmovd", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* fdmovs$pack $FRj,$FRk */ { FRV_INSN_FDMOVS, "fdmovs", "fdmovs", 32, - { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* cfmovs$pack $FRj,$FRk,$CCi,$cond */ { FRV_INSN_CFMOVS, "cfmovs", "cfmovs", 32, - { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } } + { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_F_2, 0 } } } } }, /* fnegs$pack $FRj,$FRk */ { FRV_INSN_FNEGS, "fnegs", "fnegs", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_F_2, 0 } } } } }, /* fnegd$pack $FRdoublej,$FRdoublek */ { FRV_INSN_FNEGD, "fnegd", "fnegd", 32, - { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* fdnegs$pack $FRj,$FRk */ { FRV_INSN_FDNEGS, "fdnegs", "fdnegs", 32, - { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* cfnegs$pack $FRj,$FRk,$CCi,$cond */ { FRV_INSN_CFNEGS, "cfnegs", "cfnegs", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_F_2, 0 } } } } }, /* fabss$pack $FRj,$FRk */ { FRV_INSN_FABSS, "fabss", "fabss", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_F_2, 0 } } } } }, /* fabsd$pack $FRdoublej,$FRdoublek */ { FRV_INSN_FABSD, "fabsd", "fabsd", 32, - { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* fdabss$pack $FRj,$FRk */ { FRV_INSN_FDABSS, "fdabss", "fdabss", 32, - { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* cfabss$pack $FRj,$FRk,$CCi,$cond */ { FRV_INSN_CFABSS, "cfabss", "cfabss", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_F_2, 0 } } } } }, /* fsqrts$pack $FRj,$FRk */ { FRV_INSN_FSQRTS, "fsqrts", "fsqrts", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_4, 0 } }, { { FR550_MAJOR_F_3, 0 } } } } }, /* fdsqrts$pack $FRj,$FRk */ { FRV_INSN_FDSQRTS, "fdsqrts", "fdsqrts", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_4, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* nfdsqrts$pack $FRj,$FRk */ { FRV_INSN_NFDSQRTS, "nfdsqrts", "nfdsqrts", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_4, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* fsqrtd$pack $FRdoublej,$FRdoublek */ { FRV_INSN_FSQRTD, "fsqrtd", "fsqrtd", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_4, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* cfsqrts$pack $FRj,$FRk,$CCi,$cond */ { FRV_INSN_CFSQRTS, "cfsqrts", "cfsqrts", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_4, 0 } }, { { FR550_MAJOR_F_3, 0 } } } } }, /* nfsqrts$pack $FRj,$FRk */ { FRV_INSN_NFSQRTS, "nfsqrts", "nfsqrts", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_4, 0 } }, { { FR550_MAJOR_F_3, 0 } } } } }, /* fadds$pack $FRi,$FRj,$FRk */ { FRV_INSN_FADDS, "fadds", "fadds", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_2, 0 } }, { { FR550_MAJOR_F_2, 0 } } } } }, /* fsubs$pack $FRi,$FRj,$FRk */ { FRV_INSN_FSUBS, "fsubs", "fsubs", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_2, 0 } }, { { FR550_MAJOR_F_2, 0 } } } } }, /* fmuls$pack $FRi,$FRj,$FRk */ { FRV_INSN_FMULS, "fmuls", "fmuls", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_F_3 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_3, 0 } }, { { FR550_MAJOR_F_3, 0 } } } } }, /* fdivs$pack $FRi,$FRj,$FRk */ { FRV_INSN_FDIVS, "fdivs", "fdivs", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_4, 0 } }, { { FR550_MAJOR_F_3, 0 } } } } }, /* faddd$pack $FRdoublei,$FRdoublej,$FRdoublek */ { FRV_INSN_FADDD, "faddd", "faddd", 32, - { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* fsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */ { FRV_INSN_FSUBD, "fsubd", "fsubd", 32, - { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* fmuld$pack $FRdoublei,$FRdoublej,$FRdoublek */ { FRV_INSN_FMULD, "fmuld", "fmuld", 32, - { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_3, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* fdivd$pack $FRdoublei,$FRdoublej,$FRdoublek */ { FRV_INSN_FDIVD, "fdivd", "fdivd", 32, - { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_4, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* cfadds$pack $FRi,$FRj,$FRk,$CCi,$cond */ { FRV_INSN_CFADDS, "cfadds", "cfadds", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_2, 0 } }, { { FR550_MAJOR_F_2, 0 } } } } }, /* cfsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */ { FRV_INSN_CFSUBS, "cfsubs", "cfsubs", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_2, 0 } }, { { FR550_MAJOR_F_2, 0 } } } } }, /* cfmuls$pack $FRi,$FRj,$FRk,$CCi,$cond */ { FRV_INSN_CFMULS, "cfmuls", "cfmuls", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_F_3 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_3, 0 } }, { { FR550_MAJOR_F_3, 0 } } } } }, /* cfdivs$pack $FRi,$FRj,$FRk,$CCi,$cond */ { FRV_INSN_CFDIVS, "cfdivs", "cfdivs", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_4, 0 } }, { { FR550_MAJOR_F_3, 0 } } } } }, /* nfadds$pack $FRi,$FRj,$FRk */ { FRV_INSN_NFADDS, "nfadds", "nfadds", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_2, 0 } }, { { FR550_MAJOR_F_2, 0 } } } } }, /* nfsubs$pack $FRi,$FRj,$FRk */ { FRV_INSN_NFSUBS, "nfsubs", "nfsubs", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_2, 0 } }, { { FR550_MAJOR_F_2, 0 } } } } }, /* nfmuls$pack $FRi,$FRj,$FRk */ { FRV_INSN_NFMULS, "nfmuls", "nfmuls", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_F_3 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_3, 0 } }, { { FR550_MAJOR_F_3, 0 } } } } }, /* nfdivs$pack $FRi,$FRj,$FRk */ { FRV_INSN_NFDIVS, "nfdivs", "nfdivs", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_4, 0 } }, { { FR550_MAJOR_F_3, 0 } } } } }, /* fcmps$pack $FRi,$FRj,$FCCi_2 */ { FRV_INSN_FCMPS, "fcmps", "fcmps", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_2, 0 } }, { { FR550_MAJOR_F_2, 0 } } } } }, /* fcmpd$pack $FRdoublei,$FRdoublej,$FCCi_2 */ { FRV_INSN_FCMPD, "fcmpd", "fcmpd", 32, - { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* cfcmps$pack $FRi,$FRj,$FCCi_2,$CCi,$cond */ { FRV_INSN_CFCMPS, "cfcmps", "cfcmps", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_2, 0 } }, { { FR550_MAJOR_F_2, 0 } } } } }, /* fdcmps$pack $FRi,$FRj,$FCCi_2 */ { FRV_INSN_FDCMPS, "fdcmps", "fdcmps", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_6, 0 } }, { { FR550_MAJOR_F_4, 0 } } } } }, /* fmadds$pack $FRi,$FRj,$FRk */ { FRV_INSN_FMADDS, "fmadds", "fmadds", 32, - { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* fmsubs$pack $FRi,$FRj,$FRk */ { FRV_INSN_FMSUBS, "fmsubs", "fmsubs", 32, - { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* fmaddd$pack $FRdoublei,$FRdoublej,$FRdoublek */ { FRV_INSN_FMADDD, "fmaddd", "fmaddd", 32, - { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* fmsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */ { FRV_INSN_FMSUBD, "fmsubd", "fmsubd", 32, - { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* fdmadds$pack $FRi,$FRj,$FRk */ { FRV_INSN_FDMADDS, "fdmadds", "fdmadds", 32, - { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* nfdmadds$pack $FRi,$FRj,$FRk */ { FRV_INSN_NFDMADDS, "nfdmadds", "nfdmadds", 32, - { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* cfmadds$pack $FRi,$FRj,$FRk,$CCi,$cond */ { FRV_INSN_CFMADDS, "cfmadds", "cfmadds", 32, - { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } } + { 0|A(CONDITIONAL), { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* cfmsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */ { FRV_INSN_CFMSUBS, "cfmsubs", "cfmsubs", 32, - { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } } + { 0|A(CONDITIONAL), { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* nfmadds$pack $FRi,$FRj,$FRk */ { FRV_INSN_NFMADDS, "nfmadds", "nfmadds", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* nfmsubs$pack $FRi,$FRj,$FRk */ { FRV_INSN_NFMSUBS, "nfmsubs", "nfmsubs", 32, - { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } } + { 0|A(NON_EXCEPTING), { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* fmas$pack $FRi,$FRj,$FRk */ { FRV_INSN_FMAS, "fmas", "fmas", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_F_4, 0 } } } } }, /* fmss$pack $FRi,$FRj,$FRk */ { FRV_INSN_FMSS, "fmss", "fmss", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_F_4, 0 } } } } }, /* fdmas$pack $FRi,$FRj,$FRk */ { FRV_INSN_FDMAS, "fdmas", "fdmas", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* fdmss$pack $FRi,$FRj,$FRk */ { FRV_INSN_FDMSS, "fdmss", "fdmss", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* nfdmas$pack $FRi,$FRj,$FRk */ { FRV_INSN_NFDMAS, "nfdmas", "nfdmas", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* nfdmss$pack $FRi,$FRj,$FRk */ { FRV_INSN_NFDMSS, "nfdmss", "nfdmss", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* cfmas$pack $FRi,$FRj,$FRk,$CCi,$cond */ { FRV_INSN_CFMAS, "cfmas", "cfmas", 32, - { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_F_4, 0 } } } } }, /* cfmss$pack $FRi,$FRj,$FRk,$CCi,$cond */ { FRV_INSN_CFMSS, "cfmss", "cfmss", 32, - { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_F_4, 0 } } } } }, /* fmad$pack $FRi,$FRj,$FRk */ { FRV_INSN_FMAD, "fmad", "fmad", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* fmsd$pack $FRi,$FRj,$FRk */ { FRV_INSN_FMSD, "fmsd", "fmsd", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* nfmas$pack $FRi,$FRj,$FRk */ { FRV_INSN_NFMAS, "nfmas", "nfmas", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_F_4, 0 } } } } }, /* nfmss$pack $FRi,$FRj,$FRk */ { FRV_INSN_NFMSS, "nfmss", "nfmss", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_F_4, 0 } } } } }, /* fdadds$pack $FRi,$FRj,$FRk */ { FRV_INSN_FDADDS, "fdadds", "fdadds", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_6, 0 } }, { { FR550_MAJOR_F_4, 0 } } } } }, /* fdsubs$pack $FRi,$FRj,$FRk */ { FRV_INSN_FDSUBS, "fdsubs", "fdsubs", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_6, 0 } }, { { FR550_MAJOR_F_4, 0 } } } } }, /* fdmuls$pack $FRi,$FRj,$FRk */ { FRV_INSN_FDMULS, "fdmuls", "fdmuls", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_7, 0 } }, { { FR550_MAJOR_F_4, 0 } } } } }, /* fddivs$pack $FRi,$FRj,$FRk */ { FRV_INSN_FDDIVS, "fddivs", "fddivs", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_7, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* fdsads$pack $FRi,$FRj,$FRk */ { FRV_INSN_FDSADS, "fdsads", "fdsads", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_6, 0 } }, { { FR550_MAJOR_F_4, 0 } } } } }, /* fdmulcs$pack $FRi,$FRj,$FRk */ { FRV_INSN_FDMULCS, "fdmulcs", "fdmulcs", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_7, 0 } }, { { FR550_MAJOR_F_4, 0 } } } } }, /* nfdmulcs$pack $FRi,$FRj,$FRk */ { FRV_INSN_NFDMULCS, "nfdmulcs", "nfdmulcs", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_7, 0 } }, { { FR550_MAJOR_F_4, 0 } } } } }, /* nfdadds$pack $FRi,$FRj,$FRk */ { FRV_INSN_NFDADDS, "nfdadds", "nfdadds", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_6, 0 } }, { { FR550_MAJOR_F_4, 0 } } } } }, /* nfdsubs$pack $FRi,$FRj,$FRk */ { FRV_INSN_NFDSUBS, "nfdsubs", "nfdsubs", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_6, 0 } }, { { FR550_MAJOR_F_4, 0 } } } } }, /* nfdmuls$pack $FRi,$FRj,$FRk */ { FRV_INSN_NFDMULS, "nfdmuls", "nfdmuls", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_7, 0 } }, { { FR550_MAJOR_F_4, 0 } } } } }, /* nfddivs$pack $FRi,$FRj,$FRk */ { FRV_INSN_NFDDIVS, "nfddivs", "nfddivs", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_7, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* nfdsads$pack $FRi,$FRj,$FRk */ { FRV_INSN_NFDSADS, "nfdsads", "nfdsads", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_6, 0 } }, { { FR550_MAJOR_F_4, 0 } } } } }, /* nfdcmps$pack $FRi,$FRj,$FCCi_2 */ { FRV_INSN_NFDCMPS, "nfdcmps", "nfdcmps", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_6, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* mhsetlos$pack $u12,$FRklo */ { FRV_INSN_MHSETLOS, "mhsetlos", "mhsetlos", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_5, 0 } } } } }, /* mhsethis$pack $u12,$FRkhi */ { FRV_INSN_MHSETHIS, "mhsethis", "mhsethis", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_5, 0 } } } } }, /* mhdsets$pack $u12,$FRintk */ { FRV_INSN_MHDSETS, "mhdsets", "mhdsets", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_5, 0 } } } } }, /* mhsetloh$pack $s5,$FRklo */ { FRV_INSN_MHSETLOH, "mhsetloh", "mhsetloh", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_5, 0 } } } } }, /* mhsethih$pack $s5,$FRkhi */ { FRV_INSN_MHSETHIH, "mhsethih", "mhsethih", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_5, 0 } } } } }, /* mhdseth$pack $s5,$FRintk */ { FRV_INSN_MHDSETH, "mhdseth", "mhdseth", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_5, 0 } } } } }, /* mand$pack $FRinti,$FRintj,$FRintk */ { FRV_INSN_MAND, "mand", "mand", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* mor$pack $FRinti,$FRintj,$FRintk */ { FRV_INSN_MOR, "mor", "mor", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* mxor$pack $FRinti,$FRintj,$FRintk */ { FRV_INSN_MXOR, "mxor", "mxor", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* cmand$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ { FRV_INSN_CMAND, "cmand", "cmand", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* cmor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ { FRV_INSN_CMOR, "cmor", "cmor", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* cmxor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ { FRV_INSN_CMXOR, "cmxor", "cmxor", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* mnot$pack $FRintj,$FRintk */ { FRV_INSN_MNOT, "mnot", "mnot", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* cmnot$pack $FRintj,$FRintk,$CCi,$cond */ { FRV_INSN_CMNOT, "cmnot", "cmnot", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* mrotli$pack $FRinti,$u6,$FRintk */ { FRV_INSN_MROTLI, "mrotli", "mrotli", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* mrotri$pack $FRinti,$u6,$FRintk */ { FRV_INSN_MROTRI, "mrotri", "mrotri", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* mwcut$pack $FRinti,$FRintj,$FRintk */ { FRV_INSN_MWCUT, "mwcut", "mwcut", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* mwcuti$pack $FRinti,$u6,$FRintk */ { FRV_INSN_MWCUTI, "mwcuti", "mwcuti", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* mcut$pack $ACC40Si,$FRintj,$FRintk */ { FRV_INSN_MCUT, "mcut", "mcut", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* mcuti$pack $ACC40Si,$s6,$FRintk */ { FRV_INSN_MCUTI, "mcuti", "mcuti", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_5, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_5, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* mcutss$pack $ACC40Si,$FRintj,$FRintk */ { FRV_INSN_MCUTSS, "mcutss", "mcutss", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* mcutssi$pack $ACC40Si,$s6,$FRintk */ { FRV_INSN_MCUTSSI, "mcutssi", "mcutssi", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_5, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_5, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* mdcutssi$pack $ACC40Si,$s6,$FRintkeven */ { FRV_INSN_MDCUTSSI, "mdcutssi", "mdcutssi", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_MDCUTSSI, FR400_MAJOR_M_2, FR450_MAJOR_M_6, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_MDCUTSSI, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_6, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* maveh$pack $FRinti,$FRintj,$FRintk */ { FRV_INSN_MAVEH, "maveh", "maveh", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* msllhi$pack $FRinti,$u6,$FRintk */ { FRV_INSN_MSLLHI, "msllhi", "msllhi", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* msrlhi$pack $FRinti,$u6,$FRintk */ { FRV_INSN_MSRLHI, "msrlhi", "msrlhi", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* msrahi$pack $FRinti,$u6,$FRintk */ { FRV_INSN_MSRAHI, "msrahi", "msrahi", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* mdrotli$pack $FRintieven,$s6,$FRintkeven */ { FRV_INSN_MDROTLI, "mdrotli", "mdrotli", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMLOW, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* mcplhi$pack $FRinti,$u6,$FRintk */ { FRV_INSN_MCPLHI, "mcplhi", "mcplhi", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMLOW, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* mcpli$pack $FRinti,$u6,$FRintk */ { FRV_INSN_MCPLI, "mcpli", "mcpli", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMLOW, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* msaths$pack $FRinti,$FRintj,$FRintk */ { FRV_INSN_MSATHS, "msaths", "msaths", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MQSATHS, "mqsaths", "mqsaths", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_2 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* msathu$pack $FRinti,$FRintj,$FRintk */ { FRV_INSN_MSATHU, "msathu", "msathu", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* mcmpsh$pack $FRinti,$FRintj,$FCCk */ { FRV_INSN_MCMPSH, "mcmpsh", "mcmpsh", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* mcmpuh$pack $FRinti,$FRintj,$FCCk */ { FRV_INSN_MCMPUH, "mcmpuh", "mcmpuh", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* mabshs$pack $FRintj,$FRintk */ { FRV_INSN_MABSHS, "mabshs", "mabshs", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_2 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* maddhss$pack $FRinti,$FRintj,$FRintk */ { FRV_INSN_MADDHSS, "maddhss", "maddhss", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* maddhus$pack $FRinti,$FRintj,$FRintk */ { FRV_INSN_MADDHUS, "maddhus", "maddhus", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* msubhss$pack $FRinti,$FRintj,$FRintk */ { FRV_INSN_MSUBHSS, "msubhss", "msubhss", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* msubhus$pack $FRinti,$FRintj,$FRintk */ { FRV_INSN_MSUBHUS, "msubhus", "msubhus", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* cmaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ { FRV_INSN_CMADDHSS, "cmaddhss", "cmaddhss", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* cmaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ { FRV_INSN_CMADDHUS, "cmaddhus", "cmaddhus", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* cmsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ { FRV_INSN_CMSUBHSS, "cmsubhss", "cmsubhss", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* cmsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ { FRV_INSN_CMSUBHUS, "cmsubhus", "cmsubhus", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* mqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MQADDHSS, "mqaddhss", "mqaddhss", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* mqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MQADDHUS, "mqaddhus", "mqaddhus", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* mqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MQSUBHSS, "mqsubhss", "mqsubhss", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* mqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MQSUBHUS, "mqsubhus", "mqsubhus", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* cmqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ { FRV_INSN_CMQADDHSS, "cmqaddhss", "cmqaddhss", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* cmqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ { FRV_INSN_CMQADDHUS, "cmqaddhus", "cmqaddhus", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* cmqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ { FRV_INSN_CMQSUBHSS, "cmqsubhss", "cmqsubhss", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* cmqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ { FRV_INSN_CMQSUBHUS, "cmqsubhus", "cmqsubhus", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } } }, /* mqlclrhs$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MQLCLRHS, "mqlclrhs", "mqlclrhs", 32, - { 0, { (1<<MACH_FR450), UNIT_FM0, FR400_MAJOR_NONE, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FR450), 0 } }, { { UNIT_FM0, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* mqlmths$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MQLMTHS, "mqlmths", "mqlmths", 32, - { 0, { (1<<MACH_FR450), UNIT_FM0, FR400_MAJOR_NONE, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FR450), 0 } }, { { UNIT_FM0, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* mqsllhi$pack $FRintieven,$u6,$FRintkeven */ { FRV_INSN_MQSLLHI, "mqsllhi", "mqsllhi", 32, - { 0, { (1<<MACH_FR450), UNIT_FM0, FR400_MAJOR_NONE, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FR450), 0 } }, { { UNIT_FM0, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* mqsrahi$pack $FRintieven,$u6,$FRintkeven */ { FRV_INSN_MQSRAHI, "mqsrahi", "mqsrahi", 32, - { 0, { (1<<MACH_FR450), UNIT_FM0, FR400_MAJOR_NONE, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FR450), 0 } }, { { UNIT_FM0, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* maddaccs$pack $ACC40Si,$ACC40Sk */ { FRV_INSN_MADDACCS, "maddaccs", "maddaccs", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* msubaccs$pack $ACC40Si,$ACC40Sk */ { FRV_INSN_MSUBACCS, "msubaccs", "msubaccs", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mdaddaccs$pack $ACC40Si,$ACC40Sk */ { FRV_INSN_MDADDACCS, "mdaddaccs", "mdaddaccs", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_MDUALACC, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mdsubaccs$pack $ACC40Si,$ACC40Sk */ { FRV_INSN_MDSUBACCS, "mdsubaccs", "mdsubaccs", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_MDUALACC, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* masaccs$pack $ACC40Si,$ACC40Sk */ { FRV_INSN_MASACCS, "masaccs", "masaccs", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mdasaccs$pack $ACC40Si,$ACC40Sk */ { FRV_INSN_MDASACCS, "mdasaccs", "mdasaccs", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_MDUALACC, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mmulhs$pack $FRinti,$FRintj,$ACC40Sk */ { FRV_INSN_MMULHS, "mmulhs", "mmulhs", 32, - { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0|A(PRESERVE_OVF), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mmulhu$pack $FRinti,$FRintj,$ACC40Sk */ { FRV_INSN_MMULHU, "mmulhu", "mmulhu", 32, - { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0|A(PRESERVE_OVF), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mmulxhs$pack $FRinti,$FRintj,$ACC40Sk */ { FRV_INSN_MMULXHS, "mmulxhs", "mmulxhs", 32, - { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0|A(PRESERVE_OVF), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mmulxhu$pack $FRinti,$FRintj,$ACC40Sk */ { FRV_INSN_MMULXHU, "mmulxhu", "mmulxhu", 32, - { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0|A(PRESERVE_OVF), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* cmmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMMULHS, "cmmulhs", "cmmulhs", 32, - { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* cmmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMMULHU, "cmmulhu", "cmmulhu", 32, - { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMULHS, "mqmulhs", "mqmulhs", 32, - { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0|A(PRESERVE_OVF), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMULHU, "mqmulhu", "mqmulhu", 32, - { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0|A(PRESERVE_OVF), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mqmulxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMULXHS, "mqmulxhs", "mqmulxhs", 32, - { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0|A(PRESERVE_OVF), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mqmulxhu$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMULXHU, "mqmulxhu", "mqmulxhu", 32, - { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0|A(PRESERVE_OVF), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* cmqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMQMULHS, "cmqmulhs", "cmqmulhs", 32, - { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* cmqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMQMULHU, "cmqmulhu", "cmqmulhu", 32, - { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mmachs$pack $FRinti,$FRintj,$ACC40Sk */ { FRV_INSN_MMACHS, "mmachs", "mmachs", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mmachu$pack $FRinti,$FRintj,$ACC40Uk */ { FRV_INSN_MMACHU, "mmachu", "mmachu", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mmrdhs$pack $FRinti,$FRintj,$ACC40Sk */ { FRV_INSN_MMRDHS, "mmrdhs", "mmrdhs", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mmrdhu$pack $FRinti,$FRintj,$ACC40Uk */ { FRV_INSN_MMRDHU, "mmrdhu", "mmrdhu", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* cmmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMMACHS, "cmmachs", "cmmachs", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* cmmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */ { FRV_INSN_CMMACHU, "cmmachu", "cmmachu", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMACHS, "mqmachs", "mqmachs", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk */ { FRV_INSN_MQMACHU, "mqmachu", "mqmachu", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* cmqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMQMACHS, "cmqmachs", "cmqmachs", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* cmqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk,$CCi,$cond */ { FRV_INSN_CMQMACHU, "cmqmachu", "cmqmachu", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mqxmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQXMACHS, "mqxmachs", "mqxmachs", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mqxmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQXMACXHS, "mqxmacxhs", "mqxmacxhs", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mqmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMACXHS, "mqmacxhs", "mqmacxhs", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } } + { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */ { FRV_INSN_MCPXRS, "mcpxrs", "mcpxrs", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mcpxru$pack $FRinti,$FRintj,$ACC40Sk */ { FRV_INSN_MCPXRU, "mcpxru", "mcpxru", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mcpxis$pack $FRinti,$FRintj,$ACC40Sk */ { FRV_INSN_MCPXIS, "mcpxis", "mcpxis", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mcpxiu$pack $FRinti,$FRintj,$ACC40Sk */ { FRV_INSN_MCPXIU, "mcpxiu", "mcpxiu", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* cmcpxrs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMCPXRS, "cmcpxrs", "cmcpxrs", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* cmcpxru$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMCPXRU, "cmcpxru", "cmcpxru", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* cmcpxis$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMCPXIS, "cmcpxis", "cmcpxis", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* cmcpxiu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMCPXIU, "cmcpxiu", "cmcpxiu", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mqcpxrs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQCPXRS, "mqcpxrs", "mqcpxrs", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mqcpxru$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQCPXRU, "mqcpxru", "mqcpxru", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mqcpxis$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQCPXIS, "mqcpxis", "mqcpxis", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mqcpxiu$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQCPXIU, "mqcpxiu", "mqcpxiu", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } } }, /* mexpdhw$pack $FRinti,$u6,$FRintk */ { FRV_INSN_MEXPDHW, "mexpdhw", "mexpdhw", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond */ { FRV_INSN_CMEXPDHW, "cmexpdhw", "cmexpdhw", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* mexpdhd$pack $FRinti,$u6,$FRintkeven */ { FRV_INSN_MEXPDHD, "mexpdhd", "mexpdhd", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* cmexpdhd$pack $FRinti,$u6,$FRintkeven,$CCi,$cond */ { FRV_INSN_CMEXPDHD, "cmexpdhd", "cmexpdhd", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* mpackh$pack $FRinti,$FRintj,$FRintk */ { FRV_INSN_MPACKH, "mpackh", "mpackh", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* mdpackh$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MDPACKH, "mdpackh", "mdpackh", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_5, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_5, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* munpackh$pack $FRinti,$FRintkeven */ { FRV_INSN_MUNPACKH, "munpackh", "munpackh", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* mdunpackh$pack $FRintieven,$FRintk */ { FRV_INSN_MDUNPACKH, "mdunpackh", "mdunpackh", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_7, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_M_7, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* mbtoh$pack $FRintj,$FRintkeven */ { FRV_INSN_MBTOH, "mbtoh", "mbtoh", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* cmbtoh$pack $FRintj,$FRintkeven,$CCi,$cond */ { FRV_INSN_CMBTOH, "cmbtoh", "cmbtoh", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* mhtob$pack $FRintjeven,$FRintk */ { FRV_INSN_MHTOB, "mhtob", "mhtob", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* cmhtob$pack $FRintjeven,$FRintk,$CCi,$cond */ { FRV_INSN_CMHTOB, "cmhtob", "cmhtob", 32, - { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } } + { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* mbtohe$pack $FRintj,$FRintk */ { FRV_INSN_MBTOHE, "mbtohe", "mbtohe", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_7, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_M_7, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* cmbtohe$pack $FRintj,$FRintk,$CCi,$cond */ { FRV_INSN_CMBTOHE, "cmbtohe", "cmbtohe", 32, - { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_7, FR550_MAJOR_NONE } } + { 0|A(CONDITIONAL), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_M_7, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* mnop$pack */ { FRV_INSN_MNOP, "mnop", "mnop", 32, - { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_1 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_1, 0 } } } } }, /* mclracc$pack $ACC40Sk,$A0 */ { FRV_INSN_MCLRACC_0, "mclracc-0", "mclracc", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_3, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_3, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* mclracc$pack $ACC40Sk,$A1 */ { FRV_INSN_MCLRACC_1, "mclracc-1", "mclracc", 32, - { 0, { (1<<MACH_BASE), UNIT_MCLRACC_1, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_6, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MCLRACC_1, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_6, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* mrdacc$pack $ACC40Si,$FRintk */ { FRV_INSN_MRDACC, "mrdacc", "mrdacc", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_5, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_5, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* mrdaccg$pack $ACCGi,$FRintk */ { FRV_INSN_MRDACCG, "mrdaccg", "mrdaccg", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_5, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_5, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* mwtacc$pack $FRinti,$ACC40Sk */ { FRV_INSN_MWTACC, "mwtacc", "mwtacc", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_3, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_3, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* mwtaccg$pack $FRinti,$ACCGk */ { FRV_INSN_MWTACCG, "mwtaccg", "mwtaccg", 32, - { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_3, FR550_MAJOR_M_3 } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_3, 0 } }, { { FR550_MAJOR_M_3, 0 } } } } }, /* mcop1$pack $FRi,$FRj,$FRk */ { FRV_INSN_MCOP1, "mcop1", "mcop1", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_1, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* mcop2$pack $FRi,$FRj,$FRk */ { FRV_INSN_MCOP2, "mcop2", "mcop2", 32, - { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_1, FR550_MAJOR_NONE } } + { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* fnop$pack */ { FRV_INSN_FNOP, "fnop", "fnop", 32, - { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_8, FR550_MAJOR_F_1 } } + { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_8, 0 } }, { { FR550_MAJOR_F_1, 0 } } } } }, }; @@ -6257,7 +6257,7 @@ static void frv_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) { int i; - unsigned int isas = cd->isas; + CGEN_BITSET *isas = cd->isas; unsigned int machs = cd->machs; cd->int_insn_p = CGEN_INT_INSN_P; @@ -6269,7 +6269,7 @@ frv_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) - if (((1 << i) & isas) != 0) + if (cgen_bitset_contains (isas, i)) { const CGEN_ISA *isa = & frv_cgen_isa_table[i]; @@ -6354,7 +6354,7 @@ frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) { CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); static int init_p; - unsigned int isas = 0; /* 0 = "unspecified" */ + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ unsigned int machs = 0; /* 0 = "unspecified" */ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; va_list ap; @@ -6373,7 +6373,7 @@ frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) switch (arg_type) { case CGEN_CPU_OPEN_ISAS : - isas = va_arg (ap, unsigned int); + isas = va_arg (ap, CGEN_BITSET *); break; case CGEN_CPU_OPEN_MACHS : machs = va_arg (ap, unsigned int); @@ -6404,9 +6404,6 @@ frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) machs = (1 << MAX_MACHS) - 1; /* Base mach is always selected. */ machs |= 1; - /* ISA unspecified means "all". */ - if (isas == 0) - isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) { /* ??? If target has only one, could have a default. */ @@ -6414,7 +6411,7 @@ frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) abort (); } - cd->isas = isas; + cd->isas = cgen_bitset_copy (isas); cd->machs = machs; cd->endian = endian; /* FIXME: for the sparc case we can determine insn-endianness statically. diff --git a/opcodes/frv-desc.h b/opcodes/frv-desc.h index 8b506dc2a16..d94447f9fdb 100644 --- a/opcodes/frv-desc.h +++ b/opcodes/frv-desc.h @@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc., #ifndef FRV_CPU_H #define FRV_CPU_H +#include "opcode/cgen-bitset.h" + #define CGEN_ARCH frv /* Given symbol S, return frv_cgen_<S>. */ @@ -617,6 +619,15 @@ typedef enum cgen_ifld_attr { /* Number of non-boolean elements in cgen_ifld_attr. */ #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) + /* Enum declaration for frv ifield types. */ typedef enum ifield_type { FRV_F_NIL, FRV_F_ANYOF, FRV_F_PACK, FRV_F_OP @@ -661,6 +672,13 @@ typedef enum cgen_hw_attr { /* Number of non-boolean elements in cgen_hw_attr. */ #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) + /* Enum declaration for frv hardware types. */ typedef enum cgen_hw_type { HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR @@ -693,6 +711,18 @@ typedef enum cgen_operand_attr { /* Number of non-boolean elements in cgen_operand_attr. */ #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0) + /* Enum declaration for frv operand types. */ typedef enum cgen_operand_type { FRV_OPERAND_PC, FRV_OPERAND_PACK, FRV_OPERAND_GRI, FRV_OPERAND_GRJ @@ -742,6 +772,30 @@ typedef enum cgen_insn_attr { /* Number of non-boolean elements in cgen_insn_attr. */ #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_UNIT_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_UNIT-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_FR400_MAJOR_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_FR400_MAJOR-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_FR450_MAJOR_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_FR450_MAJOR-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_FR500_MAJOR_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_FR500_MAJOR-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_FR550_MAJOR_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_FR550_MAJOR-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) +#define CGEN_ATTR_CGEN_INSN_PRIVILEGED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PRIVILEGED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NON_EXCEPTING_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NON_EXCEPTING)) != 0) +#define CGEN_ATTR_CGEN_INSN_CONDITIONAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_CONDITIONAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_FR_ACCESS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_FR_ACCESS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PRESERVE_OVF_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PRESERVE_OVF)) != 0) +#define CGEN_ATTR_CGEN_INSN_AUDIO_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_AUDIO)) != 0) + /* cgen.h uses things we just defined. */ #include "opcode/cgen.h" diff --git a/opcodes/frv-dis.c b/opcodes/frv-dis.c index a82fe2b6846..f74eb6251cc 100644 --- a/opcodes/frv-dis.c +++ b/opcodes/frv-dis.c @@ -4,7 +4,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-dis.in isn't - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -704,7 +704,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) typedef struct cpu_desc_list { struct cpu_desc_list *next; - int isa; + CGEN_BITSET *isa; int mach; int endian; CGEN_CPU_DESC cd; @@ -716,11 +716,12 @@ print_insn_frv (bfd_vma pc, disassemble_info *info) static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; static CGEN_CPU_DESC cd = 0; - static int prev_isa; + static CGEN_BITSET *prev_isa; static int prev_mach; static int prev_endian; int length; - int isa,mach; + CGEN_BITSET *isa; + int mach; int endian = (info->endian == BFD_ENDIAN_BIG ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); @@ -743,25 +744,34 @@ print_insn_frv (bfd_vma pc, disassemble_info *info) #endif #ifdef CGEN_COMPUTE_ISA - isa = CGEN_COMPUTE_ISA (info); + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } #else isa = info->insn_sets; #endif /* If we've switched cpu's, try to find a handle we've used before */ if (cd - && (isa != prev_isa + && (cgen_bitset_compare (isa, prev_isa) != 0 || mach != prev_mach || endian != prev_endian)) { cd = 0; for (cl = cd_list; cl; cl = cl->next) { - if (cl->isa == isa && + if (cgen_bitset_compare (cl->isa, isa) == 0 && cl->mach == mach && cl->endian == endian) { cd = cl->cd; + prev_isa = cd->isas; break; } } @@ -777,7 +787,7 @@ print_insn_frv (bfd_vma pc, disassemble_info *info) abort (); mach_name = arch_type->printable_name; - prev_isa = isa; + prev_isa = cgen_bitset_copy (isa); prev_mach = mach; prev_endian = endian; cd = frv_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, @@ -790,7 +800,7 @@ print_insn_frv (bfd_vma pc, disassemble_info *info) /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; - cl->isa = isa; + cl->isa = prev_isa; cl->mach = mach; cl->endian = endian; cl->next = cd_list; diff --git a/opcodes/frv-opc.c b/opcodes/frv-opc.c index 293ae61f6e9..d3e2b351e1a 100644 --- a/opcodes/frv-opc.c +++ b/opcodes/frv-opc.c @@ -38,7 +38,7 @@ with this program; if not, write to the Free Software Foundation, Inc., development tree. */ bfd_boolean -frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) +frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach) { switch (mach) { @@ -62,7 +62,7 @@ frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) /* Returns TRUE if {MAJOR,MACH} supports floating point insns. */ bfd_boolean -frv_is_float_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) +frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach) { switch (mach) { @@ -81,7 +81,7 @@ frv_is_float_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) /* Returns TRUE if {MAJOR,MACH} supports media insns. */ bfd_boolean -frv_is_media_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) +frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach) { switch (mach) { @@ -225,7 +225,7 @@ static VLIW_COMBO fr550_allowed_vliw[] = /* Some insns are assigned specialized implementation units which map to different actual implementation units on different machines. These tables perform that mapping. */ -static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] = +static CGEN_ATTR_VALUE_ENUM_TYPE fr400_unit_mapping[] = { /* unit in insn actual unit */ /* NIL */ UNIT_NIL, @@ -260,7 +260,7 @@ static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] = /* Some insns are assigned specialized implementation units which map to different actual implementation units on different machines. These tables perform that mapping. */ -static CGEN_ATTR_VALUE_TYPE fr450_unit_mapping[] = +static CGEN_ATTR_VALUE_ENUM_TYPE fr450_unit_mapping[] = { /* unit in insn actual unit */ /* NIL */ UNIT_NIL, @@ -292,7 +292,7 @@ static CGEN_ATTR_VALUE_TYPE fr450_unit_mapping[] = /* MCLRACC-1*/ UNIT_FM0 /* mclracc,A==1 insn only in FM0 unit. */ }; -static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] = +static CGEN_ATTR_VALUE_ENUM_TYPE fr500_unit_mapping[] = { /* unit in insn actual unit */ /* NIL */ UNIT_NIL, @@ -324,7 +324,7 @@ static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] = /* MCLRACC-1*/ UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit. */ }; -static CGEN_ATTR_VALUE_TYPE fr550_unit_mapping[] = +static CGEN_ATTR_VALUE_ENUM_TYPE fr550_unit_mapping[] = { /* unit in insn actual unit */ /* NIL */ UNIT_NIL, @@ -390,7 +390,7 @@ frv_vliw_reset (FRV_VLIW *vliw, unsigned long mach, unsigned long elf_flags) *_allowed_vliw tables above. */ static bfd_boolean match_unit (FRV_VLIW *vliw, - CGEN_ATTR_VALUE_TYPE unit1, CGEN_ATTR_VALUE_TYPE unit2) + CGEN_ATTR_VALUE_ENUM_TYPE unit1, CGEN_ATTR_VALUE_ENUM_TYPE unit2) { /* Map any specialized implementation units to actual ones. */ unit1 = vliw->unit_mapping[unit1]; @@ -442,7 +442,7 @@ match_vliw (VLIW_COMBO *vliw1, VLIW_COMBO *vliw2, int vliw_size) If one is found then return it. Otherwise return NULL. */ static VLIW_COMBO * -add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit) +add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE unit) { int next = vliw->next_slot; VLIW_COMBO *current = vliw->current_vliw; @@ -473,7 +473,7 @@ add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit) Returns TRUE if found, FALSE otherwise. */ static bfd_boolean -find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) +find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major) { int i; @@ -488,7 +488,7 @@ find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) types. */ static bfd_boolean -fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) +fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major) { /* In the cpu file, all media insns are represented as being allowed in both media units. This makes it easier since this is the case for fr500. @@ -508,9 +508,9 @@ fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) } static bfd_boolean -fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) +fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major) { - CGEN_ATTR_VALUE_TYPE other_major; + CGEN_ATTR_VALUE_ENUM_TYPE other_major; /* Our caller guarantees there's at least one other instruction. */ other_major = CGEN_INSN_ATTR_VALUE (vliw->insn[0], CGEN_INSN_FR450_MAJOR); @@ -543,7 +543,7 @@ fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) } static bfd_boolean -find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit) +find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE unit) { int i; @@ -556,8 +556,8 @@ find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit) static bfd_boolean find_major_in_slot (FRV_VLIW *vliw, - CGEN_ATTR_VALUE_TYPE major, - CGEN_ATTR_VALUE_TYPE slot) + CGEN_ATTR_VALUE_ENUM_TYPE major, + CGEN_ATTR_VALUE_ENUM_TYPE slot) { int i; @@ -612,11 +612,11 @@ fr550_find_float_in_vliw (FRV_VLIW *vliw) static bfd_boolean fr550_check_insn_major_constraints (FRV_VLIW *vliw, - CGEN_ATTR_VALUE_TYPE major, + CGEN_ATTR_VALUE_ENUM_TYPE major, const CGEN_INSN *insn) { - CGEN_ATTR_VALUE_TYPE unit; - CGEN_ATTR_VALUE_TYPE slot = (*vliw->current_vliw)[vliw->next_slot]; + CGEN_ATTR_VALUE_ENUM_TYPE unit; + CGEN_ATTR_VALUE_ENUM_TYPE slot = (*vliw->current_vliw)[vliw->next_slot]; switch (slot) { case UNIT_I2: @@ -662,7 +662,7 @@ fr550_check_insn_major_constraints (FRV_VLIW *vliw, } static bfd_boolean -fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) +fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major) { /* TODO: A table might be faster for some of the more complex instances here. */ @@ -770,7 +770,7 @@ fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) static bfd_boolean check_insn_major_constraints (FRV_VLIW *vliw, - CGEN_ATTR_VALUE_TYPE major, + CGEN_ATTR_VALUE_ENUM_TYPE major, const CGEN_INSN *insn) { switch (vliw->mach) @@ -796,8 +796,8 @@ int frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn) { int index; - CGEN_ATTR_VALUE_TYPE major; - CGEN_ATTR_VALUE_TYPE unit; + CGEN_ATTR_VALUE_ENUM_TYPE major; + CGEN_ATTR_VALUE_ENUM_TYPE unit; VLIW_COMBO *new_vliw; if (vliw->constraint_violation || CGEN_INSN_INVALID_P (insn)) @@ -6046,37 +6046,37 @@ static const CGEN_IBASE frv_cgen_macro_insn_table[] = /* nop$pack */ { -1, "nop", "nop", 32, - { 0|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } } + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* ret$pack */ { -1, "ret", "ret", 32, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_NONE } } + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* cmp$pack $GRi,$GRj,$ICCi_1 */ { -1, "cmp", "cmp", 32, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } } + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* cmpi$pack $GRi,$s10,$ICCi_1 */ { -1, "cmpi", "cmpi", 32, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } } + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* ccmp$pack $GRi,$GRj,$CCi,$cond */ { -1, "ccmp", "ccmp", 32, - { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } } + { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* mov$pack $GRi,$GRk */ { -1, "mov", "mov", 32, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } } + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, /* cmov$pack $GRi,$GRk,$CCi,$cond */ { -1, "cmov", "cmov", 32, - { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } } + { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } }, }; diff --git a/opcodes/frv-opc.h b/opcodes/frv-opc.h index 50e1041851f..fb04b95f2f4 100644 --- a/opcodes/frv-opc.h +++ b/opcodes/frv-opc.h @@ -39,7 +39,7 @@ with this program; if not, write to the Free Software Foundation, Inc., #define FRV_VLIW_SIZE 8 /* fr550 has largest vliw size of 8. */ #define PAD_VLIW_COMBO ,UNIT_NIL,UNIT_NIL,UNIT_NIL,UNIT_NIL -typedef CGEN_ATTR_VALUE_TYPE VLIW_COMBO[FRV_VLIW_SIZE]; +typedef CGEN_ATTR_VALUE_ENUM_TYPE VLIW_COMBO[FRV_VLIW_SIZE]; typedef struct { @@ -47,15 +47,15 @@ typedef struct int constraint_violation; unsigned long mach; unsigned long elf_flags; - CGEN_ATTR_VALUE_TYPE * unit_mapping; + CGEN_ATTR_VALUE_ENUM_TYPE * unit_mapping; VLIW_COMBO * current_vliw; - CGEN_ATTR_VALUE_TYPE major[FRV_VLIW_SIZE]; + CGEN_ATTR_VALUE_ENUM_TYPE major[FRV_VLIW_SIZE]; const CGEN_INSN * insn[FRV_VLIW_SIZE]; } FRV_VLIW; -int frv_is_branch_major (CGEN_ATTR_VALUE_TYPE, unsigned long); -int frv_is_float_major (CGEN_ATTR_VALUE_TYPE, unsigned long); -int frv_is_media_major (CGEN_ATTR_VALUE_TYPE, unsigned long); +int frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long); +int frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long); +int frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long); int frv_is_branch_insn (const CGEN_INSN *); int frv_is_float_insn (const CGEN_INSN *); int frv_is_media_insn (const CGEN_INSN *); diff --git a/opcodes/ip2k-desc.c b/opcodes/ip2k-desc.c index ca48ba2a579..289fdd6bfec 100644 --- a/opcodes/ip2k-desc.c +++ b/opcodes/ip2k-desc.c @@ -130,127 +130,127 @@ static const CGEN_MACH ip2k_cgen_mach_table[] = { static CGEN_KEYWORD_ENTRY ip2k_cgen_opval_register_names_entries[] = { - { "ADDRSEL", 2, {0, {0}}, 0, 0 }, - { "ADDRX", 3, {0, {0}}, 0, 0 }, - { "IPH", 4, {0, {0}}, 0, 0 }, - { "IPL", 5, {0, {0}}, 0, 0 }, - { "SPH", 6, {0, {0}}, 0, 0 }, - { "SPL", 7, {0, {0}}, 0, 0 }, - { "PCH", 8, {0, {0}}, 0, 0 }, - { "PCL", 9, {0, {0}}, 0, 0 }, - { "WREG", 10, {0, {0}}, 0, 0 }, - { "STATUS", 11, {0, {0}}, 0, 0 }, - { "DPH", 12, {0, {0}}, 0, 0 }, - { "DPL", 13, {0, {0}}, 0, 0 }, - { "SPDREG", 14, {0, {0}}, 0, 0 }, - { "MULH", 15, {0, {0}}, 0, 0 }, - { "ADDRH", 16, {0, {0}}, 0, 0 }, - { "ADDRL", 17, {0, {0}}, 0, 0 }, - { "DATAH", 18, {0, {0}}, 0, 0 }, - { "DATAL", 19, {0, {0}}, 0, 0 }, - { "INTVECH", 20, {0, {0}}, 0, 0 }, - { "INTVECL", 21, {0, {0}}, 0, 0 }, - { "INTSPD", 22, {0, {0}}, 0, 0 }, - { "INTF", 23, {0, {0}}, 0, 0 }, - { "INTE", 24, {0, {0}}, 0, 0 }, - { "INTED", 25, {0, {0}}, 0, 0 }, - { "FCFG", 26, {0, {0}}, 0, 0 }, - { "TCTRL", 27, {0, {0}}, 0, 0 }, - { "XCFG", 28, {0, {0}}, 0, 0 }, - { "EMCFG", 29, {0, {0}}, 0, 0 }, - { "IPCH", 30, {0, {0}}, 0, 0 }, - { "IPCL", 31, {0, {0}}, 0, 0 }, - { "RAIN", 32, {0, {0}}, 0, 0 }, - { "RAOUT", 33, {0, {0}}, 0, 0 }, - { "RADIR", 34, {0, {0}}, 0, 0 }, - { "LFSRH", 35, {0, {0}}, 0, 0 }, - { "RBIN", 36, {0, {0}}, 0, 0 }, - { "RBOUT", 37, {0, {0}}, 0, 0 }, - { "RBDIR", 38, {0, {0}}, 0, 0 }, - { "LFSRL", 39, {0, {0}}, 0, 0 }, - { "RCIN", 40, {0, {0}}, 0, 0 }, - { "RCOUT", 41, {0, {0}}, 0, 0 }, - { "RCDIR", 42, {0, {0}}, 0, 0 }, - { "LFSRA", 43, {0, {0}}, 0, 0 }, - { "RDIN", 44, {0, {0}}, 0, 0 }, - { "RDOUT", 45, {0, {0}}, 0, 0 }, - { "RDDIR", 46, {0, {0}}, 0, 0 }, - { "REIN", 48, {0, {0}}, 0, 0 }, - { "REOUT", 49, {0, {0}}, 0, 0 }, - { "REDIR", 50, {0, {0}}, 0, 0 }, - { "RFIN", 52, {0, {0}}, 0, 0 }, - { "RFOUT", 53, {0, {0}}, 0, 0 }, - { "RFDIR", 54, {0, {0}}, 0, 0 }, - { "RGOUT", 57, {0, {0}}, 0, 0 }, - { "RGDIR", 58, {0, {0}}, 0, 0 }, - { "RTTMR", 64, {0, {0}}, 0, 0 }, - { "RTCFG", 65, {0, {0}}, 0, 0 }, - { "T0TMR", 66, {0, {0}}, 0, 0 }, - { "T0CFG", 67, {0, {0}}, 0, 0 }, - { "T1CNTH", 68, {0, {0}}, 0, 0 }, - { "T1CNTL", 69, {0, {0}}, 0, 0 }, - { "T1CAP1H", 70, {0, {0}}, 0, 0 }, - { "T1CAP1L", 71, {0, {0}}, 0, 0 }, - { "T1CAP2H", 72, {0, {0}}, 0, 0 }, - { "T1CMP2H", 72, {0, {0}}, 0, 0 }, - { "T1CAP2L", 73, {0, {0}}, 0, 0 }, - { "T1CMP2L", 73, {0, {0}}, 0, 0 }, - { "T1CMP1H", 74, {0, {0}}, 0, 0 }, - { "T1CMP1L", 75, {0, {0}}, 0, 0 }, - { "T1CFG1H", 76, {0, {0}}, 0, 0 }, - { "T1CFG1L", 77, {0, {0}}, 0, 0 }, - { "T1CFG2H", 78, {0, {0}}, 0, 0 }, - { "T1CFG2L", 79, {0, {0}}, 0, 0 }, - { "ADCH", 80, {0, {0}}, 0, 0 }, - { "ADCL", 81, {0, {0}}, 0, 0 }, - { "ADCCFG", 82, {0, {0}}, 0, 0 }, - { "ADCTMR", 83, {0, {0}}, 0, 0 }, - { "T2CNTH", 84, {0, {0}}, 0, 0 }, - { "T2CNTL", 85, {0, {0}}, 0, 0 }, - { "T2CAP1H", 86, {0, {0}}, 0, 0 }, - { "T2CAP1L", 87, {0, {0}}, 0, 0 }, - { "T2CAP2H", 88, {0, {0}}, 0, 0 }, - { "T2CMP2H", 88, {0, {0}}, 0, 0 }, - { "T2CAP2L", 89, {0, {0}}, 0, 0 }, - { "T2CMP2L", 89, {0, {0}}, 0, 0 }, - { "T2CMP1H", 90, {0, {0}}, 0, 0 }, - { "T2CMP1L", 91, {0, {0}}, 0, 0 }, - { "T2CFG1H", 92, {0, {0}}, 0, 0 }, - { "T2CFG1L", 93, {0, {0}}, 0, 0 }, - { "T2CFG2H", 94, {0, {0}}, 0, 0 }, - { "T2CFG2L", 95, {0, {0}}, 0, 0 }, - { "S1TMRH", 96, {0, {0}}, 0, 0 }, - { "S1TMRL", 97, {0, {0}}, 0, 0 }, - { "S1TBUFH", 98, {0, {0}}, 0, 0 }, - { "S1TBUFL", 99, {0, {0}}, 0, 0 }, - { "S1TCFG", 100, {0, {0}}, 0, 0 }, - { "S1RCNT", 101, {0, {0}}, 0, 0 }, - { "S1RBUFH", 102, {0, {0}}, 0, 0 }, - { "S1RBUFL", 103, {0, {0}}, 0, 0 }, - { "S1RCFG", 104, {0, {0}}, 0, 0 }, - { "S1RSYNC", 105, {0, {0}}, 0, 0 }, - { "S1INTF", 106, {0, {0}}, 0, 0 }, - { "S1INTE", 107, {0, {0}}, 0, 0 }, - { "S1MODE", 108, {0, {0}}, 0, 0 }, - { "S1SMASK", 109, {0, {0}}, 0, 0 }, - { "PSPCFG", 110, {0, {0}}, 0, 0 }, - { "CMPCFG", 111, {0, {0}}, 0, 0 }, - { "S2TMRH", 112, {0, {0}}, 0, 0 }, - { "S2TMRL", 113, {0, {0}}, 0, 0 }, - { "S2TBUFH", 114, {0, {0}}, 0, 0 }, - { "S2TBUFL", 115, {0, {0}}, 0, 0 }, - { "S2TCFG", 116, {0, {0}}, 0, 0 }, - { "S2RCNT", 117, {0, {0}}, 0, 0 }, - { "S2RBUFH", 118, {0, {0}}, 0, 0 }, - { "S2RBUFL", 119, {0, {0}}, 0, 0 }, - { "S2RCFG", 120, {0, {0}}, 0, 0 }, - { "S2RSYNC", 121, {0, {0}}, 0, 0 }, - { "S2INTF", 122, {0, {0}}, 0, 0 }, - { "S2INTE", 123, {0, {0}}, 0, 0 }, - { "S2MODE", 124, {0, {0}}, 0, 0 }, - { "S2SMASK", 125, {0, {0}}, 0, 0 }, - { "CALLH", 126, {0, {0}}, 0, 0 }, - { "CALLL", 127, {0, {0}}, 0, 0 } + { "ADDRSEL", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "ADDRX", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "IPH", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "IPL", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "SPH", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "SPL", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "PCH", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "PCL", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "WREG", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "STATUS", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "DPH", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "DPL", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "SPDREG", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "MULH", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "ADDRH", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "ADDRL", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "DATAH", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "DATAL", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "INTVECH", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "INTVECL", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "INTSPD", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "INTF", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "INTE", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "INTED", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "FCFG", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "TCTRL", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "XCFG", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "EMCFG", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "IPCH", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "IPCL", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "RAIN", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "RAOUT", 33, {0, {{{0, 0}}}}, 0, 0 }, + { "RADIR", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "LFSRH", 35, {0, {{{0, 0}}}}, 0, 0 }, + { "RBIN", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "RBOUT", 37, {0, {{{0, 0}}}}, 0, 0 }, + { "RBDIR", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "LFSRL", 39, {0, {{{0, 0}}}}, 0, 0 }, + { "RCIN", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "RCOUT", 41, {0, {{{0, 0}}}}, 0, 0 }, + { "RCDIR", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "LFSRA", 43, {0, {{{0, 0}}}}, 0, 0 }, + { "RDIN", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "RDOUT", 45, {0, {{{0, 0}}}}, 0, 0 }, + { "RDDIR", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "REIN", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "REOUT", 49, {0, {{{0, 0}}}}, 0, 0 }, + { "REDIR", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "RFIN", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "RFOUT", 53, {0, {{{0, 0}}}}, 0, 0 }, + { "RFDIR", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "RGOUT", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "RGDIR", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "RTTMR", 64, {0, {{{0, 0}}}}, 0, 0 }, + { "RTCFG", 65, {0, {{{0, 0}}}}, 0, 0 }, + { "T0TMR", 66, {0, {{{0, 0}}}}, 0, 0 }, + { "T0CFG", 67, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CNTH", 68, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CNTL", 69, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CAP1H", 70, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CAP1L", 71, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CAP2H", 72, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CMP2H", 72, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CAP2L", 73, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CMP2L", 73, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CMP1H", 74, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CMP1L", 75, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CFG1H", 76, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CFG1L", 77, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CFG2H", 78, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CFG2L", 79, {0, {{{0, 0}}}}, 0, 0 }, + { "ADCH", 80, {0, {{{0, 0}}}}, 0, 0 }, + { "ADCL", 81, {0, {{{0, 0}}}}, 0, 0 }, + { "ADCCFG", 82, {0, {{{0, 0}}}}, 0, 0 }, + { "ADCTMR", 83, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CNTH", 84, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CNTL", 85, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CAP1H", 86, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CAP1L", 87, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CAP2H", 88, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CMP2H", 88, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CAP2L", 89, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CMP2L", 89, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CMP1H", 90, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CMP1L", 91, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CFG1H", 92, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CFG1L", 93, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CFG2H", 94, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CFG2L", 95, {0, {{{0, 0}}}}, 0, 0 }, + { "S1TMRH", 96, {0, {{{0, 0}}}}, 0, 0 }, + { "S1TMRL", 97, {0, {{{0, 0}}}}, 0, 0 }, + { "S1TBUFH", 98, {0, {{{0, 0}}}}, 0, 0 }, + { "S1TBUFL", 99, {0, {{{0, 0}}}}, 0, 0 }, + { "S1TCFG", 100, {0, {{{0, 0}}}}, 0, 0 }, + { "S1RCNT", 101, {0, {{{0, 0}}}}, 0, 0 }, + { "S1RBUFH", 102, {0, {{{0, 0}}}}, 0, 0 }, + { "S1RBUFL", 103, {0, {{{0, 0}}}}, 0, 0 }, + { "S1RCFG", 104, {0, {{{0, 0}}}}, 0, 0 }, + { "S1RSYNC", 105, {0, {{{0, 0}}}}, 0, 0 }, + { "S1INTF", 106, {0, {{{0, 0}}}}, 0, 0 }, + { "S1INTE", 107, {0, {{{0, 0}}}}, 0, 0 }, + { "S1MODE", 108, {0, {{{0, 0}}}}, 0, 0 }, + { "S1SMASK", 109, {0, {{{0, 0}}}}, 0, 0 }, + { "PSPCFG", 110, {0, {{{0, 0}}}}, 0, 0 }, + { "CMPCFG", 111, {0, {{{0, 0}}}}, 0, 0 }, + { "S2TMRH", 112, {0, {{{0, 0}}}}, 0, 0 }, + { "S2TMRL", 113, {0, {{{0, 0}}}}, 0, 0 }, + { "S2TBUFH", 114, {0, {{{0, 0}}}}, 0, 0 }, + { "S2TBUFL", 115, {0, {{{0, 0}}}}, 0, 0 }, + { "S2TCFG", 116, {0, {{{0, 0}}}}, 0, 0 }, + { "S2RCNT", 117, {0, {{{0, 0}}}}, 0, 0 }, + { "S2RBUFH", 118, {0, {{{0, 0}}}}, 0, 0 }, + { "S2RBUFL", 119, {0, {{{0, 0}}}}, 0, 0 }, + { "S2RCFG", 120, {0, {{{0, 0}}}}, 0, 0 }, + { "S2RSYNC", 121, {0, {{{0, 0}}}}, 0, 0 }, + { "S2INTF", 122, {0, {{{0, 0}}}}, 0, 0 }, + { "S2INTE", 123, {0, {{{0, 0}}}}, 0, 0 }, + { "S2MODE", 124, {0, {{{0, 0}}}}, 0, 0 }, + { "S2SMASK", 125, {0, {{{0, 0}}}}, 0, 0 }, + { "CALLH", 126, {0, {{{0, 0}}}}, 0, 0 }, + { "CALLL", 127, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD ip2k_cgen_opval_register_names = @@ -271,20 +271,20 @@ CGEN_KEYWORD ip2k_cgen_opval_register_names = const CGEN_HW_ENTRY ip2k_cgen_hw_table[] = { - { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-spr", HW_H_SPR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-registers", HW_H_REGISTERS, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-stack", HW_H_STACK, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-pabits", HW_H_PABITS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-dcbit", HW_H_DCBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } }, - { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} } + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-spr", HW_H_SPR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-registers", HW_H_REGISTERS, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-stack", HW_H_STACK, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-pabits", HW_H_PABITS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-dcbit", HW_H_DCBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } }, + { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } }; #undef A @@ -300,24 +300,24 @@ const CGEN_HW_ENTRY ip2k_cgen_hw_table[] = const CGEN_IFLD ip2k_cgen_ifld_table[] = { - { IP2K_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, - { IP2K_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, - { IP2K_F_IMM8, "f-imm8", 0, 16, 7, 8, { 0, { (1<<MACH_BASE) } } }, - { IP2K_F_REG, "f-reg", 0, 16, 8, 9, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, - { IP2K_F_ADDR16CJP, "f-addr16cjp", 0, 16, 12, 13, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, - { IP2K_F_DIR, "f-dir", 0, 16, 9, 1, { 0, { (1<<MACH_BASE) } } }, - { IP2K_F_BITNO, "f-bitno", 0, 16, 11, 3, { 0, { (1<<MACH_BASE) } } }, - { IP2K_F_OP3, "f-op3", 0, 16, 15, 3, { 0, { (1<<MACH_BASE) } } }, - { IP2K_F_OP4, "f-op4", 0, 16, 15, 4, { 0, { (1<<MACH_BASE) } } }, - { IP2K_F_OP4MID, "f-op4mid", 0, 16, 11, 4, { 0, { (1<<MACH_BASE) } } }, - { IP2K_F_OP6, "f-op6", 0, 16, 15, 6, { 0, { (1<<MACH_BASE) } } }, - { IP2K_F_OP8, "f-op8", 0, 16, 15, 8, { 0, { (1<<MACH_BASE) } } }, - { IP2K_F_OP6_10LOW, "f-op6-10low", 0, 16, 9, 10, { 0, { (1<<MACH_BASE) } } }, - { IP2K_F_OP6_7LOW, "f-op6-7low", 0, 16, 9, 7, { 0, { (1<<MACH_BASE) } } }, - { IP2K_F_RETI3, "f-reti3", 0, 16, 2, 3, { 0, { (1<<MACH_BASE) } } }, - { IP2K_F_SKIPB, "f-skipb", 0, 16, 12, 1, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, - { IP2K_F_PAGE3, "f-page3", 0, 16, 2, 3, { 0, { (1<<MACH_BASE) } } }, - { 0, 0, 0, 0, 0, 0, {0, {0}} } + { IP2K_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { IP2K_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { IP2K_F_IMM8, "f-imm8", 0, 16, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { IP2K_F_REG, "f-reg", 0, 16, 8, 9, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { IP2K_F_ADDR16CJP, "f-addr16cjp", 0, 16, 12, 13, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { IP2K_F_DIR, "f-dir", 0, 16, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { IP2K_F_BITNO, "f-bitno", 0, 16, 11, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { IP2K_F_OP3, "f-op3", 0, 16, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { IP2K_F_OP4, "f-op4", 0, 16, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { IP2K_F_OP4MID, "f-op4mid", 0, 16, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { IP2K_F_OP6, "f-op6", 0, 16, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { IP2K_F_OP8, "f-op8", 0, 16, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { IP2K_F_OP6_10LOW, "f-op6-10low", 0, 16, 9, 10, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { IP2K_F_OP6_7LOW, "f-op6-7low", 0, 16, 9, 7, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { IP2K_F_RETI3, "f-reti3", 0, 16, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { IP2K_F_SKIPB, "f-skipb", 0, 16, 12, 1, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { IP2K_F_PAGE3, "f-page3", 0, 16, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } }; #undef A @@ -349,59 +349,59 @@ const CGEN_OPERAND ip2k_cgen_operand_table[] = /* pc: program counter */ { "pc", IP2K_OPERAND_PC, HW_H_PC, 0, 0, { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_NIL] } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* addr16cjp: 13-bit address */ { "addr16cjp", IP2K_OPERAND_ADDR16CJP, HW_H_UINT, 12, 13, { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_ADDR16CJP] } }, - { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, + { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, /* fr: register */ { "fr", IP2K_OPERAND_FR, HW_H_REGISTERS, 8, 9, { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_REG] } }, - { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, + { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, /* lit8: 8-bit signed literal */ { "lit8", IP2K_OPERAND_LIT8, HW_H_SINT, 7, 8, { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* bitno: bit number */ { "bitno", IP2K_OPERAND_BITNO, HW_H_UINT, 11, 3, { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_BITNO] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* addr16p: page number */ { "addr16p", IP2K_OPERAND_ADDR16P, HW_H_UINT, 2, 3, { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_PAGE3] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* addr16h: high 8 bits of address */ { "addr16h", IP2K_OPERAND_ADDR16H, HW_H_UINT, 7, 8, { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* addr16l: low 8 bits of address */ { "addr16l", IP2K_OPERAND_ADDR16L, HW_H_UINT, 7, 8, { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* reti3: reti flags */ { "reti3", IP2K_OPERAND_RETI3, HW_H_UINT, 2, 3, { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_RETI3] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* pabits: page bits */ { "pabits", IP2K_OPERAND_PABITS, HW_H_PABITS, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* zbit: zero bit */ { "zbit", IP2K_OPERAND_ZBIT, HW_H_ZBIT, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* cbit: carry bit */ { "cbit", IP2K_OPERAND_CBIT, HW_H_CBIT, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* dcbit: digit carry bit */ { "dcbit", IP2K_OPERAND_DCBIT, HW_H_DCBIT, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* sentinel */ { 0, 0, 0, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { 0 } } } + { 0, { { { (1<<MACH_BASE), 0 } } } } } }; #undef A @@ -421,436 +421,436 @@ static const CGEN_IBASE ip2k_cgen_insn_table[MAX_INSNS] = /* Special null first entry. A `num' value of zero is thus invalid. Also, the special `invalid' insn resides here. */ - { 0, 0, 0, 0, {0, {0}} }, + { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* jmp $addr16cjp */ { IP2K_INSN_JMP, "jmp", "jmp", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* call $addr16cjp */ { IP2K_INSN_CALL, "call", "call", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* sb $fr,$bitno */ { IP2K_INSN_SB, "sb", "sb", 16, - { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* snb $fr,$bitno */ { IP2K_INSN_SNB, "snb", "snb", 16, - { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* setb $fr,$bitno */ { IP2K_INSN_SETB, "setb", "setb", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* clrb $fr,$bitno */ { IP2K_INSN_CLRB, "clrb", "clrb", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* xor W,#$lit8 */ { IP2K_INSN_XORW_L, "xorw_l", "xor", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* and W,#$lit8 */ { IP2K_INSN_ANDW_L, "andw_l", "and", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* or W,#$lit8 */ { IP2K_INSN_ORW_L, "orw_l", "or", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* add W,#$lit8 */ { IP2K_INSN_ADDW_L, "addw_l", "add", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* sub W,#$lit8 */ { IP2K_INSN_SUBW_L, "subw_l", "sub", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* cmp W,#$lit8 */ { IP2K_INSN_CMPW_L, "cmpw_l", "cmp", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* retw #$lit8 */ { IP2K_INSN_RETW_L, "retw_l", "retw", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* cse W,#$lit8 */ { IP2K_INSN_CSEW_L, "csew_l", "cse", 16, - { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* csne W,#$lit8 */ { IP2K_INSN_CSNEW_L, "csnew_l", "csne", 16, - { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* push #$lit8 */ { IP2K_INSN_PUSH_L, "push_l", "push", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* muls W,#$lit8 */ { IP2K_INSN_MULSW_L, "mulsw_l", "muls", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mulu W,#$lit8 */ { IP2K_INSN_MULUW_L, "muluw_l", "mulu", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* loadl #$lit8 */ { IP2K_INSN_LOADL_L, "loadl_l", "loadl", 16, - { 0|A(EXT_SKIP_INSN), { (1<<MACH_BASE) } } + { 0|A(EXT_SKIP_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* loadh #$lit8 */ { IP2K_INSN_LOADH_L, "loadh_l", "loadh", 16, - { 0|A(EXT_SKIP_INSN), { (1<<MACH_BASE) } } + { 0|A(EXT_SKIP_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* loadl $addr16l */ { IP2K_INSN_LOADL_A, "loadl_a", "loadl", 16, - { 0|A(EXT_SKIP_INSN), { (1<<MACH_BASE) } } + { 0|A(EXT_SKIP_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* loadh $addr16h */ { IP2K_INSN_LOADH_A, "loadh_a", "loadh", 16, - { 0|A(EXT_SKIP_INSN), { (1<<MACH_BASE) } } + { 0|A(EXT_SKIP_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* addc $fr,W */ { IP2K_INSN_ADDCFR_W, "addcfr_w", "addc", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* addc W,$fr */ { IP2K_INSN_ADDCW_FR, "addcw_fr", "addc", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* incsnz $fr */ { IP2K_INSN_INCSNZ_FR, "incsnz_fr", "incsnz", 16, - { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* incsnz W,$fr */ { IP2K_INSN_INCSNZW_FR, "incsnzw_fr", "incsnz", 16, - { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* muls W,$fr */ { IP2K_INSN_MULSW_FR, "mulsw_fr", "muls", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mulu W,$fr */ { IP2K_INSN_MULUW_FR, "muluw_fr", "mulu", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* decsnz $fr */ { IP2K_INSN_DECSNZ_FR, "decsnz_fr", "decsnz", 16, - { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* decsnz W,$fr */ { IP2K_INSN_DECSNZW_FR, "decsnzw_fr", "decsnz", 16, - { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* subc W,$fr */ { IP2K_INSN_SUBCW_FR, "subcw_fr", "subc", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* subc $fr,W */ { IP2K_INSN_SUBCFR_W, "subcfr_w", "subc", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* pop $fr */ { IP2K_INSN_POP_FR, "pop_fr", "pop", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* push $fr */ { IP2K_INSN_PUSH_FR, "push_fr", "push", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* cse W,$fr */ { IP2K_INSN_CSEW_FR, "csew_fr", "cse", 16, - { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* csne W,$fr */ { IP2K_INSN_CSNEW_FR, "csnew_fr", "csne", 16, - { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* incsz $fr */ { IP2K_INSN_INCSZ_FR, "incsz_fr", "incsz", 16, - { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* incsz W,$fr */ { IP2K_INSN_INCSZW_FR, "incszw_fr", "incsz", 16, - { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* swap $fr */ { IP2K_INSN_SWAP_FR, "swap_fr", "swap", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* swap W,$fr */ { IP2K_INSN_SWAPW_FR, "swapw_fr", "swap", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* rl $fr */ { IP2K_INSN_RL_FR, "rl_fr", "rl", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* rl W,$fr */ { IP2K_INSN_RLW_FR, "rlw_fr", "rl", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* rr $fr */ { IP2K_INSN_RR_FR, "rr_fr", "rr", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* rr W,$fr */ { IP2K_INSN_RRW_FR, "rrw_fr", "rr", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* decsz $fr */ { IP2K_INSN_DECSZ_FR, "decsz_fr", "decsz", 16, - { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* decsz W,$fr */ { IP2K_INSN_DECSZW_FR, "decszw_fr", "decsz", 16, - { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* inc $fr */ { IP2K_INSN_INC_FR, "inc_fr", "inc", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* inc W,$fr */ { IP2K_INSN_INCW_FR, "incw_fr", "inc", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* not $fr */ { IP2K_INSN_NOT_FR, "not_fr", "not", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* not W,$fr */ { IP2K_INSN_NOTW_FR, "notw_fr", "not", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* test $fr */ { IP2K_INSN_TEST_FR, "test_fr", "test", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov W,#$lit8 */ { IP2K_INSN_MOVW_L, "movw_l", "mov", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov $fr,W */ { IP2K_INSN_MOVFR_W, "movfr_w", "mov", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov W,$fr */ { IP2K_INSN_MOVW_FR, "movw_fr", "mov", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* add $fr,W */ { IP2K_INSN_ADDFR_W, "addfr_w", "add", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* add W,$fr */ { IP2K_INSN_ADDW_FR, "addw_fr", "add", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* xor $fr,W */ { IP2K_INSN_XORFR_W, "xorfr_w", "xor", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* xor W,$fr */ { IP2K_INSN_XORW_FR, "xorw_fr", "xor", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* and $fr,W */ { IP2K_INSN_ANDFR_W, "andfr_w", "and", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* and W,$fr */ { IP2K_INSN_ANDW_FR, "andw_fr", "and", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* or $fr,W */ { IP2K_INSN_ORFR_W, "orfr_w", "or", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* or W,$fr */ { IP2K_INSN_ORW_FR, "orw_fr", "or", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* dec $fr */ { IP2K_INSN_DEC_FR, "dec_fr", "dec", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* dec W,$fr */ { IP2K_INSN_DECW_FR, "decw_fr", "dec", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* sub $fr,W */ { IP2K_INSN_SUBFR_W, "subfr_w", "sub", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* sub W,$fr */ { IP2K_INSN_SUBW_FR, "subw_fr", "sub", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* clr $fr */ { IP2K_INSN_CLR_FR, "clr_fr", "clr", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* cmp W,$fr */ { IP2K_INSN_CMPW_FR, "cmpw_fr", "cmp", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* speed #$lit8 */ { IP2K_INSN_SPEED, "speed", "speed", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ireadi */ { IP2K_INSN_IREADI, "ireadi", "ireadi", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* iwritei */ { IP2K_INSN_IWRITEI, "iwritei", "iwritei", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* fread */ { IP2K_INSN_FREAD, "fread", "fread", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* fwrite */ { IP2K_INSN_FWRITE, "fwrite", "fwrite", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* iread */ { IP2K_INSN_IREAD, "iread", "iread", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* iwrite */ { IP2K_INSN_IWRITE, "iwrite", "iwrite", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* page $addr16p */ { IP2K_INSN_PAGE, "page", "page", 16, - { 0|A(EXT_SKIP_INSN), { (1<<MACH_BASE) } } + { 0|A(EXT_SKIP_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* system */ { IP2K_INSN_SYSTEM, "system", "system", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* reti #$reti3 */ { IP2K_INSN_RETI, "reti", "reti", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ret */ { IP2K_INSN_RET, "ret", "ret", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* int */ { IP2K_INSN_INT, "int", "int", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* breakx */ { IP2K_INSN_BREAKX, "breakx", "breakx", 16, - { 0|A(EXT_SKIP_INSN), { (1<<MACH_BASE) } } + { 0|A(EXT_SKIP_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* cwdt */ { IP2K_INSN_CWDT, "cwdt", "cwdt", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ferase */ { IP2K_INSN_FERASE, "ferase", "ferase", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* retnp */ { IP2K_INSN_RETNP, "retnp", "retnp", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* break */ { IP2K_INSN_BREAK, "break", "break", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* nop */ { IP2K_INSN_NOP, "nop", "nop", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, }; @@ -973,7 +973,7 @@ static void ip2k_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) { int i; - unsigned int isas = cd->isas; + CGEN_BITSET *isas = cd->isas; unsigned int machs = cd->machs; cd->int_insn_p = CGEN_INT_INSN_P; @@ -985,7 +985,7 @@ ip2k_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) - if (((1 << i) & isas) != 0) + if (cgen_bitset_contains (isas, i)) { const CGEN_ISA *isa = & ip2k_cgen_isa_table[i]; @@ -1070,7 +1070,7 @@ ip2k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) { CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); static int init_p; - unsigned int isas = 0; /* 0 = "unspecified" */ + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ unsigned int machs = 0; /* 0 = "unspecified" */ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; va_list ap; @@ -1089,7 +1089,7 @@ ip2k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) switch (arg_type) { case CGEN_CPU_OPEN_ISAS : - isas = va_arg (ap, unsigned int); + isas = va_arg (ap, CGEN_BITSET *); break; case CGEN_CPU_OPEN_MACHS : machs = va_arg (ap, unsigned int); @@ -1120,9 +1120,6 @@ ip2k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) machs = (1 << MAX_MACHS) - 1; /* Base mach is always selected. */ machs |= 1; - /* ISA unspecified means "all". */ - if (isas == 0) - isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) { /* ??? If target has only one, could have a default. */ @@ -1130,7 +1127,7 @@ ip2k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) abort (); } - cd->isas = isas; + cd->isas = cgen_bitset_copy (isas); cd->machs = machs; cd->endian = endian; /* FIXME: for the sparc case we can determine insn-endianness statically. diff --git a/opcodes/ip2k-desc.h b/opcodes/ip2k-desc.h index fa85fbdf366..125849fbc8d 100644 --- a/opcodes/ip2k-desc.h +++ b/opcodes/ip2k-desc.h @@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc., #ifndef IP2K_CPU_H #define IP2K_CPU_H +#include "opcode/cgen-bitset.h" + #define CGEN_ARCH ip2k /* Given symbol S, return ip2k_cgen_<S>. */ @@ -160,6 +162,15 @@ typedef enum cgen_ifld_attr { /* Number of non-boolean elements in cgen_ifld_attr. */ #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) + /* Enum declaration for ip2k ifield types. */ typedef enum ifield_type { IP2K_F_NIL, IP2K_F_ANYOF, IP2K_F_IMM8, IP2K_F_REG @@ -182,6 +193,13 @@ typedef enum cgen_hw_attr { /* Number of non-boolean elements in cgen_hw_attr. */ #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) + /* Enum declaration for ip2k hardware types. */ typedef enum cgen_hw_type { HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR @@ -204,6 +222,17 @@ typedef enum cgen_operand_attr { /* Number of non-boolean elements in cgen_operand_attr. */ #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) + /* Enum declaration for ip2k operand types. */ typedef enum cgen_operand_type { IP2K_OPERAND_PC, IP2K_OPERAND_ADDR16CJP, IP2K_OPERAND_FR, IP2K_OPERAND_LIT8 @@ -231,6 +260,21 @@ typedef enum cgen_insn_attr { /* Number of non-boolean elements in cgen_insn_attr. */ #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) +#define CGEN_ATTR_CGEN_INSN_EXT_SKIP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_EXT_SKIP_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIPA_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIPA)) != 0) + /* cgen.h uses things we just defined. */ #include "opcode/cgen.h" diff --git a/opcodes/ip2k-dis.c b/opcodes/ip2k-dis.c index 95cb9e49e97..b80e97fb6a1 100644 --- a/opcodes/ip2k-dis.c +++ b/opcodes/ip2k-dis.c @@ -4,7 +4,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-dis.in isn't - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -596,7 +596,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) typedef struct cpu_desc_list { struct cpu_desc_list *next; - int isa; + CGEN_BITSET *isa; int mach; int endian; CGEN_CPU_DESC cd; @@ -608,11 +608,12 @@ print_insn_ip2k (bfd_vma pc, disassemble_info *info) static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; static CGEN_CPU_DESC cd = 0; - static int prev_isa; + static CGEN_BITSET *prev_isa; static int prev_mach; static int prev_endian; int length; - int isa,mach; + CGEN_BITSET *isa; + int mach; int endian = (info->endian == BFD_ENDIAN_BIG ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); @@ -635,25 +636,34 @@ print_insn_ip2k (bfd_vma pc, disassemble_info *info) #endif #ifdef CGEN_COMPUTE_ISA - isa = CGEN_COMPUTE_ISA (info); + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } #else isa = info->insn_sets; #endif /* If we've switched cpu's, try to find a handle we've used before */ if (cd - && (isa != prev_isa + && (cgen_bitset_compare (isa, prev_isa) != 0 || mach != prev_mach || endian != prev_endian)) { cd = 0; for (cl = cd_list; cl; cl = cl->next) { - if (cl->isa == isa && + if (cgen_bitset_compare (cl->isa, isa) == 0 && cl->mach == mach && cl->endian == endian) { cd = cl->cd; + prev_isa = cd->isas; break; } } @@ -669,7 +679,7 @@ print_insn_ip2k (bfd_vma pc, disassemble_info *info) abort (); mach_name = arch_type->printable_name; - prev_isa = isa; + prev_isa = cgen_bitset_copy (isa); prev_mach = mach; prev_endian = endian; cd = ip2k_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, @@ -682,7 +692,7 @@ print_insn_ip2k (bfd_vma pc, disassemble_info *info) /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; - cl->isa = isa; + cl->isa = prev_isa; cl->mach = mach; cl->endian = endian; cl->next = cd_list; diff --git a/opcodes/ip2k-opc.c b/opcodes/ip2k-opc.c index dd4648f8f11..30a734ec1ff 100644 --- a/opcodes/ip2k-opc.c +++ b/opcodes/ip2k-opc.c @@ -726,32 +726,32 @@ static const CGEN_IBASE ip2k_cgen_macro_insn_table[] = /* sc */ { -1, "sc", "sc", 16, - { 0|A(ALIAS), { (1<<MACH_BASE) } } + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } }, /* snc */ { -1, "snc", "snc", 16, - { 0|A(ALIAS), { (1<<MACH_BASE) } } + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } }, /* sz */ { -1, "sz", "sz", 16, - { 0|A(ALIAS), { (1<<MACH_BASE) } } + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } }, /* snz */ { -1, "snz", "snz", 16, - { 0|A(ALIAS), { (1<<MACH_BASE) } } + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } }, /* skip */ { -1, "skip", "skip", 16, - { 0|A(SKIPA)|A(ALIAS), { (1<<MACH_BASE) } } + { 0|A(SKIPA)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } }, /* skip */ { -1, "skipb", "skip", 16, - { 0|A(SKIPA)|A(ALIAS), { (1<<MACH_BASE) } } + { 0|A(SKIPA)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } }, }; diff --git a/opcodes/m32c-asm.c b/opcodes/m32c-asm.c index 02475eadfc6..e2d8c490646 100644 --- a/opcodes/m32c-asm.c +++ b/opcodes/m32c-asm.c @@ -794,14 +794,14 @@ m32c_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) { int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); - int isas = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ISA); + CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA); /* If attributes are absent, assume no restriction. */ if (machs == 0) machs = ~0; return ((machs & cd->machs) - && (isas & cd->isas)); + && cgen_bitset_intersect_p (& isas, cd->isas)); } /* Parse a set of registers, R0,R1,A0,A1,SB,FB. */ diff --git a/opcodes/m32c-desc.c b/opcodes/m32c-desc.c index f0b56eefdd7..12b9a1b385a 100644 --- a/opcodes/m32c-desc.c +++ b/opcodes/m32c-desc.c @@ -134,10 +134,10 @@ static const CGEN_MACH m32c_cgen_mach_table[] = { static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_entries[] = { - { "r0", 0, {0, {0}}, 0, 0 }, - { "r1", 1, {0, {0}}, 0, 0 }, - { "r2", 2, {0, {0}}, 0, 0 }, - { "r3", 3, {0, {0}}, 0, 0 } + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_gr = @@ -149,10 +149,10 @@ CGEN_KEYWORD m32c_cgen_opval_h_gr = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_QI_entries[] = { - { "r0l", 0, {0, {0}}, 0, 0 }, - { "r0h", 1, {0, {0}}, 0, 0 }, - { "r1l", 2, {0, {0}}, 0, 0 }, - { "r1h", 3, {0, {0}}, 0, 0 } + { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r0h", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r1l", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r1h", 3, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_gr_QI = @@ -164,10 +164,10 @@ CGEN_KEYWORD m32c_cgen_opval_h_gr_QI = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_HI_entries[] = { - { "r0", 0, {0, {0}}, 0, 0 }, - { "r1", 1, {0, {0}}, 0, 0 }, - { "r2", 2, {0, {0}}, 0, 0 }, - { "r3", 3, {0, {0}}, 0, 0 } + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_gr_HI = @@ -179,8 +179,8 @@ CGEN_KEYWORD m32c_cgen_opval_h_gr_HI = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_SI_entries[] = { - { "r2r0", 0, {0, {0}}, 0, 0 }, - { "r3r1", 1, {0, {0}}, 0, 0 } + { "r2r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r3r1", 1, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_gr_SI = @@ -192,8 +192,8 @@ CGEN_KEYWORD m32c_cgen_opval_h_gr_SI = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_QI_entries[] = { - { "r0l", 0, {0, {0}}, 0, 0 }, - { "r1l", 1, {0, {0}}, 0, 0 } + { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1l", 1, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_QI = @@ -205,8 +205,8 @@ CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_QI = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_HI_entries[] = { - { "r0", 0, {0, {0}}, 0, 0 }, - { "r1", 1, {0, {0}}, 0, 0 } + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_HI = @@ -218,7 +218,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_HI = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_entries[] = { - { "r0l", 0, {0, {0}}, 0, 0 } + { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r0l = @@ -230,7 +230,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r0l = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0h_entries[] = { - { "r0h", 0, {0, {0}}, 0, 0 } + { "r0h", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r0h = @@ -242,7 +242,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r0h = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1l_entries[] = { - { "r1l", 0, {0, {0}}, 0, 0 } + { "r1l", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r1l = @@ -254,7 +254,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r1l = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1h_entries[] = { - { "r1h", 0, {0, {0}}, 0, 0 } + { "r1h", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r1h = @@ -266,7 +266,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r1h = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0_entries[] = { - { "r0", 0, {0, {0}}, 0, 0 } + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r0 = @@ -278,7 +278,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r0 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1_entries[] = { - { "r1", 0, {0, {0}}, 0, 0 } + { "r1", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r1 = @@ -290,7 +290,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r1 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2_entries[] = { - { "r2", 0, {0, {0}}, 0, 0 } + { "r2", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r2 = @@ -302,7 +302,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r2 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3_entries[] = { - { "r3", 0, {0, {0}}, 0, 0 } + { "r3", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r3 = @@ -314,8 +314,8 @@ CGEN_KEYWORD m32c_cgen_opval_h_r3 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_r0h_entries[] = { - { "r0l", 0, {0, {0}}, 0, 0 }, - { "r0h", 1, {0, {0}}, 0, 0 } + { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r0h", 1, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r0l_r0h = @@ -327,7 +327,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r0l_r0h = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2r0_entries[] = { - { "r2r0", 0, {0, {0}}, 0, 0 } + { "r2r0", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r2r0 = @@ -339,7 +339,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r2r0 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3r1_entries[] = { - { "r3r1", 0, {0, {0}}, 0, 0 } + { "r3r1", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r3r1 = @@ -351,7 +351,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r3r1 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1r2r0_entries[] = { - { "r1r2r0", 0, {0, {0}}, 0, 0 } + { "r1r2r0", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_r1r2r0 = @@ -363,8 +363,8 @@ CGEN_KEYWORD m32c_cgen_opval_h_r1r2r0 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_entries[] = { - { "a0", 0, {0, {0}}, 0, 0 }, - { "a1", 1, {0, {0}}, 0, 0 } + { "a0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "a1", 1, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_ar = @@ -376,8 +376,8 @@ CGEN_KEYWORD m32c_cgen_opval_h_ar = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_QI_entries[] = { - { "a0", 0, {0, {0}}, 0, 0 }, - { "a1", 1, {0, {0}}, 0, 0 } + { "a0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "a1", 1, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_ar_QI = @@ -389,8 +389,8 @@ CGEN_KEYWORD m32c_cgen_opval_h_ar_QI = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_HI_entries[] = { - { "a0", 0, {0, {0}}, 0, 0 }, - { "a1", 1, {0, {0}}, 0, 0 } + { "a0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "a1", 1, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_ar_HI = @@ -402,7 +402,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_ar_HI = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_SI_entries[] = { - { "a1a0", 0, {0, {0}}, 0, 0 } + { "a1a0", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_ar_SI = @@ -414,7 +414,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_ar_SI = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a0_entries[] = { - { "a0", 0, {0, {0}}, 0, 0 } + { "a0", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_a0 = @@ -426,7 +426,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_a0 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a1_entries[] = { - { "a1", 1, {0, {0}}, 0, 0 } + { "a1", 1, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_a1 = @@ -438,24 +438,24 @@ CGEN_KEYWORD m32c_cgen_opval_h_a1 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16_entries[] = { - { "geu", 0, {0, {0}}, 0, 0 }, - { "c", 0, {0, {0}}, 0, 0 }, - { "gtu", 1, {0, {0}}, 0, 0 }, - { "eq", 2, {0, {0}}, 0, 0 }, - { "z", 2, {0, {0}}, 0, 0 }, - { "n", 3, {0, {0}}, 0, 0 }, - { "le", 4, {0, {0}}, 0, 0 }, - { "o", 5, {0, {0}}, 0, 0 }, - { "ge", 6, {0, {0}}, 0, 0 }, - { "ltu", 248, {0, {0}}, 0, 0 }, - { "nc", 248, {0, {0}}, 0, 0 }, - { "leu", 249, {0, {0}}, 0, 0 }, - { "ne", 250, {0, {0}}, 0, 0 }, - { "nz", 250, {0, {0}}, 0, 0 }, - { "pz", 251, {0, {0}}, 0, 0 }, - { "gt", 252, {0, {0}}, 0, 0 }, - { "no", 253, {0, {0}}, 0, 0 }, - { "lt", 254, {0, {0}}, 0, 0 } + { "geu", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "c", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "gtu", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "eq", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "z", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "n", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "le", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "o", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "ge", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "ltu", 248, {0, {{{0, 0}}}}, 0, 0 }, + { "nc", 248, {0, {{{0, 0}}}}, 0, 0 }, + { "leu", 249, {0, {{{0, 0}}}}, 0, 0 }, + { "ne", 250, {0, {{{0, 0}}}}, 0, 0 }, + { "nz", 250, {0, {{{0, 0}}}}, 0, 0 }, + { "pz", 251, {0, {{{0, 0}}}}, 0, 0 }, + { "gt", 252, {0, {{{0, 0}}}}, 0, 0 }, + { "no", 253, {0, {{{0, 0}}}}, 0, 0 }, + { "lt", 254, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cond16 = @@ -467,24 +467,24 @@ CGEN_KEYWORD m32c_cgen_opval_h_cond16 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16c_entries[] = { - { "geu", 0, {0, {0}}, 0, 0 }, - { "c", 0, {0, {0}}, 0, 0 }, - { "gtu", 1, {0, {0}}, 0, 0 }, - { "eq", 2, {0, {0}}, 0, 0 }, - { "z", 2, {0, {0}}, 0, 0 }, - { "n", 3, {0, {0}}, 0, 0 }, - { "ltu", 4, {0, {0}}, 0, 0 }, - { "nc", 4, {0, {0}}, 0, 0 }, - { "leu", 5, {0, {0}}, 0, 0 }, - { "ne", 6, {0, {0}}, 0, 0 }, - { "nz", 6, {0, {0}}, 0, 0 }, - { "pz", 7, {0, {0}}, 0, 0 }, - { "le", 8, {0, {0}}, 0, 0 }, - { "o", 9, {0, {0}}, 0, 0 }, - { "ge", 10, {0, {0}}, 0, 0 }, - { "gt", 12, {0, {0}}, 0, 0 }, - { "no", 13, {0, {0}}, 0, 0 }, - { "lt", 14, {0, {0}}, 0, 0 } + { "geu", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "c", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "gtu", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "eq", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "z", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "n", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "ltu", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "nc", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "leu", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "ne", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "nz", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "pz", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "le", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "o", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "ge", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "gt", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "no", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "lt", 14, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cond16c = @@ -496,12 +496,12 @@ CGEN_KEYWORD m32c_cgen_opval_h_cond16c = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_entries[] = { - { "le", 8, {0, {0}}, 0, 0 }, - { "o", 9, {0, {0}}, 0, 0 }, - { "ge", 10, {0, {0}}, 0, 0 }, - { "gt", 12, {0, {0}}, 0, 0 }, - { "no", 13, {0, {0}}, 0, 0 }, - { "lt", 14, {0, {0}}, 0, 0 } + { "le", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "o", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "ge", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "gt", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "no", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "lt", 14, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cond16j = @@ -513,18 +513,18 @@ CGEN_KEYWORD m32c_cgen_opval_h_cond16j = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_5_entries[] = { - { "geu", 0, {0, {0}}, 0, 0 }, - { "c", 0, {0, {0}}, 0, 0 }, - { "gtu", 1, {0, {0}}, 0, 0 }, - { "eq", 2, {0, {0}}, 0, 0 }, - { "z", 2, {0, {0}}, 0, 0 }, - { "n", 3, {0, {0}}, 0, 0 }, - { "ltu", 4, {0, {0}}, 0, 0 }, - { "nc", 4, {0, {0}}, 0, 0 }, - { "leu", 5, {0, {0}}, 0, 0 }, - { "ne", 6, {0, {0}}, 0, 0 }, - { "nz", 6, {0, {0}}, 0, 0 }, - { "pz", 7, {0, {0}}, 0, 0 } + { "geu", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "c", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "gtu", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "eq", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "z", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "n", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "ltu", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "nc", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "leu", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "ne", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "nz", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "pz", 7, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cond16j_5 = @@ -536,24 +536,24 @@ CGEN_KEYWORD m32c_cgen_opval_h_cond16j_5 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond32_entries[] = { - { "ltu", 0, {0, {0}}, 0, 0 }, - { "nc", 0, {0, {0}}, 0, 0 }, - { "leu", 1, {0, {0}}, 0, 0 }, - { "ne", 2, {0, {0}}, 0, 0 }, - { "nz", 2, {0, {0}}, 0, 0 }, - { "pz", 3, {0, {0}}, 0, 0 }, - { "no", 4, {0, {0}}, 0, 0 }, - { "gt", 5, {0, {0}}, 0, 0 }, - { "ge", 6, {0, {0}}, 0, 0 }, - { "geu", 8, {0, {0}}, 0, 0 }, - { "c", 8, {0, {0}}, 0, 0 }, - { "gtu", 9, {0, {0}}, 0, 0 }, - { "eq", 10, {0, {0}}, 0, 0 }, - { "z", 10, {0, {0}}, 0, 0 }, - { "n", 11, {0, {0}}, 0, 0 }, - { "o", 12, {0, {0}}, 0, 0 }, - { "le", 13, {0, {0}}, 0, 0 }, - { "lt", 14, {0, {0}}, 0, 0 } + { "ltu", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "nc", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "leu", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "ne", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "nz", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "pz", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "no", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "gt", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "ge", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "geu", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "c", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "gtu", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "eq", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "z", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "n", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "o", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "le", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "lt", 14, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cond32 = @@ -565,14 +565,14 @@ CGEN_KEYWORD m32c_cgen_opval_h_cond32 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr1_32_entries[] = { - { "dct0", 0, {0, {0}}, 0, 0 }, - { "dct1", 1, {0, {0}}, 0, 0 }, - { "flg", 2, {0, {0}}, 0, 0 }, - { "svf", 3, {0, {0}}, 0, 0 }, - { "drc0", 4, {0, {0}}, 0, 0 }, - { "drc1", 5, {0, {0}}, 0, 0 }, - { "dmd0", 6, {0, {0}}, 0, 0 }, - { "dmd1", 7, {0, {0}}, 0, 0 } + { "dct0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "dct1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "flg", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "svf", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "drc0", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "drc1", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "dmd0", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "dmd1", 7, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cr1_32 = @@ -584,13 +584,13 @@ CGEN_KEYWORD m32c_cgen_opval_h_cr1_32 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr2_32_entries[] = { - { "intb", 0, {0, {0}}, 0, 0 }, - { "sp", 1, {0, {0}}, 0, 0 }, - { "sb", 2, {0, {0}}, 0, 0 }, - { "fb", 3, {0, {0}}, 0, 0 }, - { "svp", 4, {0, {0}}, 0, 0 }, - { "vct", 5, {0, {0}}, 0, 0 }, - { "isp", 7, {0, {0}}, 0, 0 } + { "intb", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "sb", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "fb", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "svp", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "vct", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "isp", 7, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cr2_32 = @@ -602,12 +602,12 @@ CGEN_KEYWORD m32c_cgen_opval_h_cr2_32 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr3_32_entries[] = { - { "dma0", 2, {0, {0}}, 0, 0 }, - { "dma1", 3, {0, {0}}, 0, 0 }, - { "dra0", 4, {0, {0}}, 0, 0 }, - { "dra1", 5, {0, {0}}, 0, 0 }, - { "dsa0", 6, {0, {0}}, 0, 0 }, - { "dsa1", 7, {0, {0}}, 0, 0 } + { "dma0", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "dma1", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "dra0", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "dra1", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "dsa0", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "dsa1", 7, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cr3_32 = @@ -619,13 +619,13 @@ CGEN_KEYWORD m32c_cgen_opval_h_cr3_32 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr_16_entries[] = { - { "intbl", 1, {0, {0}}, 0, 0 }, - { "intbh", 2, {0, {0}}, 0, 0 }, - { "flg", 3, {0, {0}}, 0, 0 }, - { "isp", 4, {0, {0}}, 0, 0 }, - { "sp", 5, {0, {0}}, 0, 0 }, - { "sb", 6, {0, {0}}, 0, 0 }, - { "fb", 7, {0, {0}}, 0, 0 } + { "intbl", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "intbh", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "flg", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "isp", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "sb", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "fb", 7, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_cr_16 = @@ -637,14 +637,14 @@ CGEN_KEYWORD m32c_cgen_opval_h_cr_16 = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_flags_entries[] = { - { "c", 0, {0, {0}}, 0, 0 }, - { "d", 1, {0, {0}}, 0, 0 }, - { "z", 2, {0, {0}}, 0, 0 }, - { "s", 3, {0, {0}}, 0, 0 }, - { "b", 4, {0, {0}}, 0, 0 }, - { "o", 5, {0, {0}}, 0, 0 }, - { "i", 6, {0, {0}}, 0, 0 }, - { "u", 7, {0, {0}}, 0, 0 } + { "c", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "d", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "z", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "s", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "b", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "o", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "i", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "u", 7, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_flags = @@ -656,22 +656,22 @@ CGEN_KEYWORD m32c_cgen_opval_h_flags = static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_shimm_entries[] = { - { "1", 0, {0, {0}}, 0, 0 }, - { "2", 1, {0, {0}}, 0, 0 }, - { "3", 2, {0, {0}}, 0, 0 }, - { "4", 3, {0, {0}}, 0, 0 }, - { "5", 4, {0, {0}}, 0, 0 }, - { "6", 5, {0, {0}}, 0, 0 }, - { "7", 6, {0, {0}}, 0, 0 }, - { "8", 7, {0, {0}}, 0, 0 }, - { "-1", -8, {0, {0}}, 0, 0 }, - { "-2", -7, {0, {0}}, 0, 0 }, - { "-3", -6, {0, {0}}, 0, 0 }, - { "-4", -5, {0, {0}}, 0, 0 }, - { "-5", -4, {0, {0}}, 0, 0 }, - { "-6", -3, {0, {0}}, 0, 0 }, - { "-7", -2, {0, {0}}, 0, 0 }, - { "-8", -1, {0, {0}}, 0, 0 } + { "1", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "2", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "3", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "4", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "5", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "6", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "7", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "8", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "-1", -8, {0, {{{0, 0}}}}, 0, 0 }, + { "-2", -7, {0, {{{0, 0}}}}, 0, 0 }, + { "-3", -6, {0, {{{0, 0}}}}, 0, 0 }, + { "-4", -5, {0, {{{0, 0}}}}, 0, 0 }, + { "-5", -4, {0, {{{0, 0}}}}, 0, 0 }, + { "-6", -3, {0, {{{0, 0}}}}, 0, 0 }, + { "-7", -2, {0, {{{0, 0}}}}, 0, 0 }, + { "-8", -1, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32c_cgen_opval_h_shimm = @@ -692,82 +692,82 @@ CGEN_KEYWORD m32c_cgen_opval_h_shimm = const CGEN_HW_ENTRY m32c_cgen_hw_table[] = { - { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr, { 0|A(CACHE_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-gr-QI", HW_H_GR_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_QI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-gr-HI", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_HI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-gr-SI", HW_H_GR_SI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_SI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-gr-ext-QI", HW_H_GR_EXT_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_ext_QI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-gr-ext-HI", HW_H_GR_EXT_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_ext_HI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-r0l", HW_H_R0L, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0l, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-r0h", HW_H_R0H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0h, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-r1l", HW_H_R1L, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1l, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-r1h", HW_H_R1H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1h, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-r1", HW_H_R1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-r2", HW_H_R2, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r2, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-r3", HW_H_R3, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r3, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-r0l-r0h", HW_H_R0L_R0H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0l_r0h, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-r2r0", HW_H_R2R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r2r0, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-r3r1", HW_H_R3R1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r3r1, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-r1r2r0", HW_H_R1R2R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1r2r0, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-ar", HW_H_AR, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-ar-QI", HW_H_AR_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_QI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-ar-HI", HW_H_AR_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_HI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-ar-SI", HW_H_AR_SI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_SI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-a0", HW_H_A0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_a0, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-a1", HW_H_A1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_a1, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-sb", HW_H_SB, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-fb", HW_H_FB, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-sp", HW_H_SP, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-obit", HW_H_OBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-ubit", HW_H_UBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-bbit", HW_H_BBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-dbit", HW_H_DBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-dct0", HW_H_DCT0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-dct1", HW_H_DCT1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-svf", HW_H_SVF, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-drc0", HW_H_DRC0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-drc1", HW_H_DRC1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-dmd0", HW_H_DMD0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-dmd1", HW_H_DMD1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-intb", HW_H_INTB, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-svp", HW_H_SVP, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-vct", HW_H_VCT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-isp", HW_H_ISP, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-dma0", HW_H_DMA0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-dma1", HW_H_DMA1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-dra0", HW_H_DRA0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-dra1", HW_H_DRA1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-dsa0", HW_H_DSA0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-dsa1", HW_H_DSA1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-cond16", HW_H_COND16, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, - { "h-cond16c", HW_H_COND16C, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16c, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, - { "h-cond16j", HW_H_COND16J, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16j, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, - { "h-cond16j-5", HW_H_COND16J_5, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16j_5, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, - { "h-cond32", HW_H_COND32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond32, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { "h-cr1-32", HW_H_CR1_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr1_32, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { "h-cr2-32", HW_H_CR2_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr2_32, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { "h-cr3-32", HW_H_CR3_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr3_32, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { "h-cr-16", HW_H_CR_16, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr_16, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, - { "h-flags", HW_H_FLAGS, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_flags, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-shimm", HW_H_SHIMM, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_shimm, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-bit-index", HW_H_BIT_INDEX, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { "h-src-index", HW_H_SRC_INDEX, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { "h-dst-index", HW_H_DST_INDEX, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { "h-src-indirect", HW_H_SRC_INDIRECT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-dst-indirect", HW_H_DST_INDIRECT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { "h-none", HW_H_NONE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} } + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr, { 0|A(CACHE_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-gr-QI", HW_H_GR_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_QI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-gr-HI", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_HI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-gr-SI", HW_H_GR_SI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_SI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-gr-ext-QI", HW_H_GR_EXT_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_ext_QI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-gr-ext-HI", HW_H_GR_EXT_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_ext_HI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-r0l", HW_H_R0L, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0l, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-r0h", HW_H_R0H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0h, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-r1l", HW_H_R1L, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1l, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-r1h", HW_H_R1H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1h, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-r1", HW_H_R1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-r2", HW_H_R2, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r2, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-r3", HW_H_R3, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r3, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-r0l-r0h", HW_H_R0L_R0H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0l_r0h, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-r2r0", HW_H_R2R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r2r0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-r3r1", HW_H_R3R1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r3r1, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-r1r2r0", HW_H_R1R2R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1r2r0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-ar", HW_H_AR, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-ar-QI", HW_H_AR_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_QI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-ar-HI", HW_H_AR_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_HI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-ar-SI", HW_H_AR_SI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_SI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-a0", HW_H_A0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_a0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-a1", HW_H_A1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_a1, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-sb", HW_H_SB, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-fb", HW_H_FB, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-sp", HW_H_SP, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-obit", HW_H_OBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-ubit", HW_H_UBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-bbit", HW_H_BBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-dbit", HW_H_DBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-dct0", HW_H_DCT0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-dct1", HW_H_DCT1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-svf", HW_H_SVF, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-drc0", HW_H_DRC0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-drc1", HW_H_DRC1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-dmd0", HW_H_DMD0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-dmd1", HW_H_DMD1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-intb", HW_H_INTB, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-svp", HW_H_SVP, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-vct", HW_H_VCT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-isp", HW_H_ISP, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-dma0", HW_H_DMA0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-dma1", HW_H_DMA1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-dra0", HW_H_DRA0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-dra1", HW_H_DRA1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-dsa0", HW_H_DSA0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-dsa1", HW_H_DSA1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-cond16", HW_H_COND16, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, + { "h-cond16c", HW_H_COND16C, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16c, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, + { "h-cond16j", HW_H_COND16J, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16j, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, + { "h-cond16j-5", HW_H_COND16J_5, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16j_5, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, + { "h-cond32", HW_H_COND32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond32, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { "h-cr1-32", HW_H_CR1_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr1_32, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { "h-cr2-32", HW_H_CR2_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr2_32, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { "h-cr3-32", HW_H_CR3_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr3_32, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { "h-cr-16", HW_H_CR_16, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr_16, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, + { "h-flags", HW_H_FLAGS, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_flags, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-shimm", HW_H_SHIMM, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_shimm, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-bit-index", HW_H_BIT_INDEX, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { "h-src-index", HW_H_SRC_INDEX, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { "h-dst-index", HW_H_DST_INDEX, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { "h-src-indirect", HW_H_SRC_INDIRECT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-dst-indirect", HW_H_DST_INDIRECT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-none", HW_H_NONE, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } } }; #undef A @@ -783,164 +783,164 @@ const CGEN_HW_ENTRY m32c_cgen_hw_table[] = const CGEN_IFLD m32c_cgen_ifld_table[] = { - { M32C_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, - { M32C_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, - { M32C_F_0_1, "f-0-1", 0, 32, 0, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_0_2, "f-0-2", 0, 32, 0, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_0_3, "f-0-3", 0, 32, 0, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_0_4, "f-0-4", 0, 32, 0, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_1_3, "f-1-3", 0, 32, 1, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_2_2, "f-2-2", 0, 32, 2, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_3_4, "f-3-4", 0, 32, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_3_1, "f-3-1", 0, 32, 3, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_4_1, "f-4-1", 0, 32, 4, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_4_3, "f-4-3", 0, 32, 4, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_4_4, "f-4-4", 0, 32, 4, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_4_6, "f-4-6", 0, 32, 4, 6, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_5_1, "f-5-1", 0, 32, 5, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_5_3, "f-5-3", 0, 32, 5, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_6_2, "f-6-2", 0, 32, 6, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_7_1, "f-7-1", 0, 32, 7, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_8_1, "f-8-1", 0, 32, 8, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_8_2, "f-8-2", 0, 32, 8, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_8_3, "f-8-3", 0, 32, 8, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_8_4, "f-8-4", 0, 32, 8, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_8_8, "f-8-8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_9_3, "f-9-3", 0, 32, 9, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_9_1, "f-9-1", 0, 32, 9, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_10_1, "f-10-1", 0, 32, 10, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_10_2, "f-10-2", 0, 32, 10, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_10_3, "f-10-3", 0, 32, 10, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_11_1, "f-11-1", 0, 32, 11, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_12_1, "f-12-1", 0, 32, 12, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_12_2, "f-12-2", 0, 32, 12, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_12_3, "f-12-3", 0, 32, 12, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_12_4, "f-12-4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_12_6, "f-12-6", 0, 32, 12, 6, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_13_3, "f-13-3", 0, 32, 13, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_14_1, "f-14-1", 0, 32, 14, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_14_2, "f-14-2", 0, 32, 14, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_15_1, "f-15-1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_16_1, "f-16-1", 0, 32, 16, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_16_2, "f-16-2", 0, 32, 16, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_16_4, "f-16-4", 0, 32, 16, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_16_8, "f-16-8", 0, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_18_1, "f-18-1", 0, 32, 18, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_18_2, "f-18-2", 0, 32, 18, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_18_3, "f-18-3", 0, 32, 18, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_20_1, "f-20-1", 0, 32, 20, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_20_3, "f-20-3", 0, 32, 20, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_20_2, "f-20-2", 0, 32, 20, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_20_4, "f-20-4", 0, 32, 20, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_21_3, "f-21-3", 0, 32, 21, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_24_2, "f-24-2", 0, 32, 24, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_24_8, "f-24-8", 0, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_32_16, "f-32-16", 32, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_SRC16_RN, "f-src16-rn", 0, 32, 10, 2, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, - { M32C_F_SRC16_AN, "f-src16-an", 0, 32, 11, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, - { M32C_F_SRC32_AN_UNPREFIXED, "f-src32-an-unprefixed", 0, 32, 11, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { M32C_F_SRC32_AN_PREFIXED, "f-src32-an-prefixed", 0, 32, 19, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { M32C_F_SRC32_RN_UNPREFIXED_QI, "f-src32-rn-unprefixed-QI", 0, 32, 10, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { M32C_F_SRC32_RN_PREFIXED_QI, "f-src32-rn-prefixed-QI", 0, 32, 18, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { M32C_F_SRC32_RN_UNPREFIXED_HI, "f-src32-rn-unprefixed-HI", 0, 32, 10, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { M32C_F_SRC32_RN_PREFIXED_HI, "f-src32-rn-prefixed-HI", 0, 32, 18, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { M32C_F_SRC32_RN_UNPREFIXED_SI, "f-src32-rn-unprefixed-SI", 0, 32, 10, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { M32C_F_SRC32_RN_PREFIXED_SI, "f-src32-rn-prefixed-SI", 0, 32, 18, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { M32C_F_DST32_RN_EXT_UNPREFIXED, "f-dst32-rn-ext-unprefixed", 0, 32, 9, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { M32C_F_DST16_RN, "f-dst16-rn", 0, 32, 14, 2, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, - { M32C_F_DST16_RN_EXT, "f-dst16-rn-ext", 0, 32, 14, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, - { M32C_F_DST16_RN_QI_S, "f-dst16-rn-QI-s", 0, 32, 5, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, - { M32C_F_DST16_AN, "f-dst16-an", 0, 32, 15, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, - { M32C_F_DST16_AN_S, "f-dst16-an-s", 0, 32, 4, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, - { M32C_F_DST32_AN_UNPREFIXED, "f-dst32-an-unprefixed", 0, 32, 9, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { M32C_F_DST32_AN_PREFIXED, "f-dst32-an-prefixed", 0, 32, 17, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { M32C_F_DST32_RN_UNPREFIXED_QI, "f-dst32-rn-unprefixed-QI", 0, 32, 8, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { M32C_F_DST32_RN_PREFIXED_QI, "f-dst32-rn-prefixed-QI", 0, 32, 16, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { M32C_F_DST32_RN_UNPREFIXED_HI, "f-dst32-rn-unprefixed-HI", 0, 32, 8, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { M32C_F_DST32_RN_PREFIXED_HI, "f-dst32-rn-prefixed-HI", 0, 32, 16, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { M32C_F_DST32_RN_UNPREFIXED_SI, "f-dst32-rn-unprefixed-SI", 0, 32, 8, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { M32C_F_DST32_RN_PREFIXED_SI, "f-dst32-rn-prefixed-SI", 0, 32, 16, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { M32C_F_DST16_1_S, "f-dst16-1-S", 0, 32, 5, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, - { M32C_F_IMM_8_S4, "f-imm-8-s4", 0, 32, 8, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_IMM_12_S4, "f-imm-12-s4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_IMM_13_U3, "f-imm-13-u3", 0, 32, 13, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_IMM_20_S4, "f-imm-20-s4", 0, 32, 20, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_IMM1_S, "f-imm1-S", 0, 32, 2, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, - { M32C_F_IMM3_S, "f-imm3-S", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_8_U6, "f-dsp-8-u6", 0, 32, 8, 6, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_8_U8, "f-dsp-8-u8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_8_S8, "f-dsp-8-s8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_10_U6, "f-dsp-10-u6", 0, 32, 10, 6, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_16_U8, "f-dsp-16-u8", 0, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_16_S8, "f-dsp-16-s8", 0, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_24_U8, "f-dsp-24-u8", 0, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_24_S8, "f-dsp-24-s8", 0, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_32_U8, "f-dsp-32-u8", 32, 32, 0, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_32_S8, "f-dsp-32-s8", 32, 32, 0, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_40_U8, "f-dsp-40-u8", 32, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_40_S8, "f-dsp-40-s8", 32, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_48_U8, "f-dsp-48-u8", 32, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_48_S8, "f-dsp-48-s8", 32, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_56_U8, "f-dsp-56-u8", 32, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_56_S8, "f-dsp-56-s8", 32, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_64_U8, "f-dsp-64-u8", 64, 32, 0, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_64_S8, "f-dsp-64-s8", 64, 32, 0, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_8_U16, "f-dsp-8-u16", 0, 32, 8, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_8_S16, "f-dsp-8-s16", 0, 32, 8, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_16_U16, "f-dsp-16-u16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_16_S16, "f-dsp-16-s16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_24_U16, "f-dsp-24-u16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_24_S16, "f-dsp-24-s16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_32_U16, "f-dsp-32-u16", 32, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_32_S16, "f-dsp-32-s16", 32, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_40_U16, "f-dsp-40-u16", 32, 32, 8, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_40_S16, "f-dsp-40-s16", 32, 32, 8, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_48_U16, "f-dsp-48-u16", 32, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_48_S16, "f-dsp-48-s16", 32, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_64_U16, "f-dsp-64-u16", 64, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_8_S24, "f-dsp-8-s24", 0, 32, 8, 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_8_U24, "f-dsp-8-u24", 0, 32, 8, 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_16_U24, "f-dsp-16-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_24_U24, "f-dsp-24-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_32_U24, "f-dsp-32-u24", 32, 32, 0, 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_40_U24, "f-dsp-40-u24", 32, 32, 8, 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_40_S32, "f-dsp-40-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_48_U24, "f-dsp-48-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_16_S32, "f-dsp-16-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_24_S32, "f-dsp-24-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_32_S32, "f-dsp-32-s32", 32, 32, 0, 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_48_U32, "f-dsp-48-u32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_48_S32, "f-dsp-48-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_56_S16, "f-dsp-56-s16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_DSP_64_S16, "f-dsp-64-s16", 64, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_BITNO16_S, "f-bitno16-S", 0, 32, 5, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_BITNO32_PREFIXED, "f-bitno32-prefixed", 0, 32, 21, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_BITNO32_UNPREFIXED, "f-bitno32-unprefixed", 0, 32, 13, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_BITBASE16_U11_S, "f-bitbase16-u11-S", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_BITBASE32_16_U11_UNPREFIXED, "f-bitbase32-16-u11-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_BITBASE32_16_S11_UNPREFIXED, "f-bitbase32-16-s11-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_BITBASE32_16_U19_UNPREFIXED, "f-bitbase32-16-u19-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_BITBASE32_16_S19_UNPREFIXED, "f-bitbase32-16-s19-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_BITBASE32_16_U27_UNPREFIXED, "f-bitbase32-16-u27-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_BITBASE32_24_U11_PREFIXED, "f-bitbase32-24-u11-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_BITBASE32_24_S11_PREFIXED, "f-bitbase32-24-s11-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_BITBASE32_24_U19_PREFIXED, "f-bitbase32-24-u19-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_BITBASE32_24_S19_PREFIXED, "f-bitbase32-24-s19-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_BITBASE32_24_U27_PREFIXED, "f-bitbase32-24-u27-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_LAB_5_3, "f-lab-5-3", 0, 32, 5, 3, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_LAB32_JMP_S, "f-lab32-jmp-s", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_LAB_8_8, "f-lab-8-8", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_LAB_8_16, "f-lab-8-16", 0, 32, 8, 16, { 0|A(SIGN_OPT)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_LAB_8_24, "f-lab-8-24", 0, 32, 8, 24, { 0|A(ABS_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_LAB_16_8, "f-lab-16-8", 0, 32, 16, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_LAB_24_8, "f-lab-24-8", 0, 32, 24, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_LAB_32_8, "f-lab-32-8", 32, 32, 0, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_LAB_40_8, "f-lab-40-8", 32, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_COND16, "f-cond16", 0, 32, 12, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_COND16J_5, "f-cond16j-5", 0, 32, 5, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_COND32, "f-cond32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { M32C_F_COND32J, "f-cond32j", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, - { 0, 0, 0, 0, 0, 0, {0, {0}} } + { M32C_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { M32C_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { M32C_F_0_1, "f-0-1", 0, 32, 0, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_0_2, "f-0-2", 0, 32, 0, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_0_3, "f-0-3", 0, 32, 0, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_0_4, "f-0-4", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_1_3, "f-1-3", 0, 32, 1, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_2_2, "f-2-2", 0, 32, 2, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_3_4, "f-3-4", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_3_1, "f-3-1", 0, 32, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_4_1, "f-4-1", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_4_3, "f-4-3", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_4_4, "f-4-4", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_4_6, "f-4-6", 0, 32, 4, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_5_1, "f-5-1", 0, 32, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_5_3, "f-5-3", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_6_2, "f-6-2", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_7_1, "f-7-1", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_8_1, "f-8-1", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_8_2, "f-8-2", 0, 32, 8, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_8_3, "f-8-3", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_8_4, "f-8-4", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_8_8, "f-8-8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_9_3, "f-9-3", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_9_1, "f-9-1", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_10_1, "f-10-1", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_10_2, "f-10-2", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_10_3, "f-10-3", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_11_1, "f-11-1", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_12_1, "f-12-1", 0, 32, 12, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_12_2, "f-12-2", 0, 32, 12, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_12_3, "f-12-3", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_12_4, "f-12-4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_12_6, "f-12-6", 0, 32, 12, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_13_3, "f-13-3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_14_1, "f-14-1", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_14_2, "f-14-2", 0, 32, 14, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_15_1, "f-15-1", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_16_1, "f-16-1", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_16_2, "f-16-2", 0, 32, 16, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_16_4, "f-16-4", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_16_8, "f-16-8", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_18_1, "f-18-1", 0, 32, 18, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_18_2, "f-18-2", 0, 32, 18, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_18_3, "f-18-3", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_20_1, "f-20-1", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_20_3, "f-20-3", 0, 32, 20, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_20_2, "f-20-2", 0, 32, 20, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_20_4, "f-20-4", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_21_3, "f-21-3", 0, 32, 21, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_24_2, "f-24-2", 0, 32, 24, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_24_8, "f-24-8", 0, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_32_16, "f-32-16", 32, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_SRC16_RN, "f-src16-rn", 0, 32, 10, 2, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, + { M32C_F_SRC16_AN, "f-src16-an", 0, 32, 11, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, + { M32C_F_SRC32_AN_UNPREFIXED, "f-src32-an-unprefixed", 0, 32, 11, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { M32C_F_SRC32_AN_PREFIXED, "f-src32-an-prefixed", 0, 32, 19, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { M32C_F_SRC32_RN_UNPREFIXED_QI, "f-src32-rn-unprefixed-QI", 0, 32, 10, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { M32C_F_SRC32_RN_PREFIXED_QI, "f-src32-rn-prefixed-QI", 0, 32, 18, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { M32C_F_SRC32_RN_UNPREFIXED_HI, "f-src32-rn-unprefixed-HI", 0, 32, 10, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { M32C_F_SRC32_RN_PREFIXED_HI, "f-src32-rn-prefixed-HI", 0, 32, 18, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { M32C_F_SRC32_RN_UNPREFIXED_SI, "f-src32-rn-unprefixed-SI", 0, 32, 10, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { M32C_F_SRC32_RN_PREFIXED_SI, "f-src32-rn-prefixed-SI", 0, 32, 18, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { M32C_F_DST32_RN_EXT_UNPREFIXED, "f-dst32-rn-ext-unprefixed", 0, 32, 9, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { M32C_F_DST16_RN, "f-dst16-rn", 0, 32, 14, 2, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, + { M32C_F_DST16_RN_EXT, "f-dst16-rn-ext", 0, 32, 14, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, + { M32C_F_DST16_RN_QI_S, "f-dst16-rn-QI-s", 0, 32, 5, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, + { M32C_F_DST16_AN, "f-dst16-an", 0, 32, 15, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, + { M32C_F_DST16_AN_S, "f-dst16-an-s", 0, 32, 4, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, + { M32C_F_DST32_AN_UNPREFIXED, "f-dst32-an-unprefixed", 0, 32, 9, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { M32C_F_DST32_AN_PREFIXED, "f-dst32-an-prefixed", 0, 32, 17, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { M32C_F_DST32_RN_UNPREFIXED_QI, "f-dst32-rn-unprefixed-QI", 0, 32, 8, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { M32C_F_DST32_RN_PREFIXED_QI, "f-dst32-rn-prefixed-QI", 0, 32, 16, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { M32C_F_DST32_RN_UNPREFIXED_HI, "f-dst32-rn-unprefixed-HI", 0, 32, 8, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { M32C_F_DST32_RN_PREFIXED_HI, "f-dst32-rn-prefixed-HI", 0, 32, 16, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { M32C_F_DST32_RN_UNPREFIXED_SI, "f-dst32-rn-unprefixed-SI", 0, 32, 8, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { M32C_F_DST32_RN_PREFIXED_SI, "f-dst32-rn-prefixed-SI", 0, 32, 16, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { M32C_F_DST16_1_S, "f-dst16-1-S", 0, 32, 5, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, + { M32C_F_IMM_8_S4, "f-imm-8-s4", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_IMM_12_S4, "f-imm-12-s4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_IMM_13_U3, "f-imm-13-u3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_IMM_20_S4, "f-imm-20-s4", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_IMM1_S, "f-imm1-S", 0, 32, 2, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, + { M32C_F_IMM3_S, "f-imm3-S", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_8_U6, "f-dsp-8-u6", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_8_U8, "f-dsp-8-u8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_8_S8, "f-dsp-8-s8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_10_U6, "f-dsp-10-u6", 0, 32, 10, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_16_U8, "f-dsp-16-u8", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_16_S8, "f-dsp-16-s8", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_24_U8, "f-dsp-24-u8", 0, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_24_S8, "f-dsp-24-s8", 0, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_32_U8, "f-dsp-32-u8", 32, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_32_S8, "f-dsp-32-s8", 32, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_40_U8, "f-dsp-40-u8", 32, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_40_S8, "f-dsp-40-s8", 32, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_48_U8, "f-dsp-48-u8", 32, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_48_S8, "f-dsp-48-s8", 32, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_56_U8, "f-dsp-56-u8", 32, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_56_S8, "f-dsp-56-s8", 32, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_64_U8, "f-dsp-64-u8", 64, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_64_S8, "f-dsp-64-s8", 64, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_8_U16, "f-dsp-8-u16", 0, 32, 8, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_8_S16, "f-dsp-8-s16", 0, 32, 8, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_16_U16, "f-dsp-16-u16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_16_S16, "f-dsp-16-s16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_24_U16, "f-dsp-24-u16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_24_S16, "f-dsp-24-s16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_32_U16, "f-dsp-32-u16", 32, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_32_S16, "f-dsp-32-s16", 32, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_40_U16, "f-dsp-40-u16", 32, 32, 8, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_40_S16, "f-dsp-40-s16", 32, 32, 8, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_48_U16, "f-dsp-48-u16", 32, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_48_S16, "f-dsp-48-s16", 32, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_64_U16, "f-dsp-64-u16", 64, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_8_S24, "f-dsp-8-s24", 0, 32, 8, 24, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_8_U24, "f-dsp-8-u24", 0, 32, 8, 24, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_16_U24, "f-dsp-16-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_24_U24, "f-dsp-24-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_32_U24, "f-dsp-32-u24", 32, 32, 0, 24, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_40_U24, "f-dsp-40-u24", 32, 32, 8, 24, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_40_S32, "f-dsp-40-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_48_U24, "f-dsp-48-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_16_S32, "f-dsp-16-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_24_S32, "f-dsp-24-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_32_S32, "f-dsp-32-s32", 32, 32, 0, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_48_U32, "f-dsp-48-u32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_48_S32, "f-dsp-48-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_56_S16, "f-dsp-56-s16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_DSP_64_S16, "f-dsp-64-s16", 64, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_BITNO16_S, "f-bitno16-S", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_BITNO32_PREFIXED, "f-bitno32-prefixed", 0, 32, 21, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_BITNO32_UNPREFIXED, "f-bitno32-unprefixed", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_BITBASE16_U11_S, "f-bitbase16-u11-S", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_BITBASE32_16_U11_UNPREFIXED, "f-bitbase32-16-u11-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_BITBASE32_16_S11_UNPREFIXED, "f-bitbase32-16-s11-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_BITBASE32_16_U19_UNPREFIXED, "f-bitbase32-16-u19-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_BITBASE32_16_S19_UNPREFIXED, "f-bitbase32-16-s19-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_BITBASE32_16_U27_UNPREFIXED, "f-bitbase32-16-u27-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_BITBASE32_24_U11_PREFIXED, "f-bitbase32-24-u11-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_BITBASE32_24_S11_PREFIXED, "f-bitbase32-24-s11-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_BITBASE32_24_U19_PREFIXED, "f-bitbase32-24-u19-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_BITBASE32_24_S19_PREFIXED, "f-bitbase32-24-s19-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_BITBASE32_24_U27_PREFIXED, "f-bitbase32-24-u27-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_LAB_5_3, "f-lab-5-3", 0, 32, 5, 3, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_LAB32_JMP_S, "f-lab32-jmp-s", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_LAB_8_8, "f-lab-8-8", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_LAB_8_16, "f-lab-8-16", 0, 32, 8, 16, { 0|A(SIGN_OPT)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_LAB_8_24, "f-lab-8-24", 0, 32, 8, 24, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_LAB_16_8, "f-lab-16-8", 0, 32, 16, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_LAB_24_8, "f-lab-24-8", 0, 32, 24, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_LAB_32_8, "f-lab-32-8", 32, 32, 0, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_LAB_40_8, "f-lab-40-8", 32, 32, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_COND16, "f-cond16", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_COND16J_5, "f-cond16j-5", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_COND32, "f-cond32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { M32C_F_COND32J, "f-cond32j", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } } }; #undef A @@ -1158,827 +1158,827 @@ const CGEN_OPERAND m32c_cgen_operand_table[] = /* pc: program counter */ { "pc", M32C_OPERAND_PC, HW_H_PC, 0, 0, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_NIL] } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* Src16RnQI: general register QI view */ { "Src16RnQI", M32C_OPERAND_SRC16RNQI, HW_H_GR_QI, 10, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_RN] } }, - { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, /* Src16RnHI: general register QH view */ { "Src16RnHI", M32C_OPERAND_SRC16RNHI, HW_H_GR_HI, 10, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_RN] } }, - { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, /* Src32RnUnprefixedQI: general register QI view */ { "Src32RnUnprefixedQI", M32C_OPERAND_SRC32RNUNPREFIXEDQI, HW_H_GR_QI, 10, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_QI] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Src32RnUnprefixedHI: general register HI view */ { "Src32RnUnprefixedHI", M32C_OPERAND_SRC32RNUNPREFIXEDHI, HW_H_GR_HI, 10, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_HI] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Src32RnUnprefixedSI: general register SI view */ { "Src32RnUnprefixedSI", M32C_OPERAND_SRC32RNUNPREFIXEDSI, HW_H_GR_SI, 10, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_SI] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Src32RnPrefixedQI: general register QI view */ { "Src32RnPrefixedQI", M32C_OPERAND_SRC32RNPREFIXEDQI, HW_H_GR_QI, 18, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_QI] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Src32RnPrefixedHI: general register HI view */ { "Src32RnPrefixedHI", M32C_OPERAND_SRC32RNPREFIXEDHI, HW_H_GR_HI, 18, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_HI] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Src32RnPrefixedSI: general register SI view */ { "Src32RnPrefixedSI", M32C_OPERAND_SRC32RNPREFIXEDSI, HW_H_GR_SI, 18, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_SI] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Src16An: address register */ { "Src16An", M32C_OPERAND_SRC16AN, HW_H_AR, 11, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } }, - { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, /* Src16AnQI: address register QI view */ { "Src16AnQI", M32C_OPERAND_SRC16ANQI, HW_H_AR_QI, 11, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } }, - { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, /* Src16AnHI: address register HI view */ { "Src16AnHI", M32C_OPERAND_SRC16ANHI, HW_H_AR_HI, 11, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } }, - { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, /* Src32AnUnprefixed: address register */ { "Src32AnUnprefixed", M32C_OPERAND_SRC32ANUNPREFIXED, HW_H_AR, 11, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Src32AnUnprefixedQI: address register QI view */ { "Src32AnUnprefixedQI", M32C_OPERAND_SRC32ANUNPREFIXEDQI, HW_H_AR_QI, 11, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Src32AnUnprefixedHI: address register HI view */ { "Src32AnUnprefixedHI", M32C_OPERAND_SRC32ANUNPREFIXEDHI, HW_H_AR_HI, 11, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Src32AnUnprefixedSI: address register SI view */ { "Src32AnUnprefixedSI", M32C_OPERAND_SRC32ANUNPREFIXEDSI, HW_H_AR, 11, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Src32AnPrefixed: address register */ { "Src32AnPrefixed", M32C_OPERAND_SRC32ANPREFIXED, HW_H_AR, 19, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Src32AnPrefixedQI: address register QI view */ { "Src32AnPrefixedQI", M32C_OPERAND_SRC32ANPREFIXEDQI, HW_H_AR_QI, 19, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Src32AnPrefixedHI: address register HI view */ { "Src32AnPrefixedHI", M32C_OPERAND_SRC32ANPREFIXEDHI, HW_H_AR_HI, 19, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Src32AnPrefixedSI: address register SI view */ { "Src32AnPrefixedSI", M32C_OPERAND_SRC32ANPREFIXEDSI, HW_H_AR, 19, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Dst16RnQI: general register QI view */ { "Dst16RnQI", M32C_OPERAND_DST16RNQI, HW_H_GR_QI, 14, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } }, - { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, /* Dst16RnHI: general register HI view */ { "Dst16RnHI", M32C_OPERAND_DST16RNHI, HW_H_GR_HI, 14, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } }, - { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, /* Dst16RnSI: general register SI view */ { "Dst16RnSI", M32C_OPERAND_DST16RNSI, HW_H_GR_SI, 14, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } }, - { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, /* Dst16RnExtQI: general register QI/HI view for 'ext' insns */ { "Dst16RnExtQI", M32C_OPERAND_DST16RNEXTQI, HW_H_GR_EXT_QI, 14, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_EXT] } }, - { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, /* Dst32R0QI-S: general register QI view */ { "Dst32R0QI-S", M32C_OPERAND_DST32R0QI_S, HW_H_R0L, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Dst32R0HI-S: general register HI view */ { "Dst32R0HI-S", M32C_OPERAND_DST32R0HI_S, HW_H_R0, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Dst32RnUnprefixedQI: general register QI view */ { "Dst32RnUnprefixedQI", M32C_OPERAND_DST32RNUNPREFIXEDQI, HW_H_GR_QI, 8, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_QI] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Dst32RnUnprefixedHI: general register HI view */ { "Dst32RnUnprefixedHI", M32C_OPERAND_DST32RNUNPREFIXEDHI, HW_H_GR_HI, 8, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_HI] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Dst32RnUnprefixedSI: general register SI view */ { "Dst32RnUnprefixedSI", M32C_OPERAND_DST32RNUNPREFIXEDSI, HW_H_GR_SI, 8, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_SI] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Dst32RnExtUnprefixedQI: general register QI view */ { "Dst32RnExtUnprefixedQI", M32C_OPERAND_DST32RNEXTUNPREFIXEDQI, HW_H_GR_EXT_QI, 9, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_EXT_UNPREFIXED] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Dst32RnExtUnprefixedHI: general register HI view */ { "Dst32RnExtUnprefixedHI", M32C_OPERAND_DST32RNEXTUNPREFIXEDHI, HW_H_GR_EXT_HI, 9, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_EXT_UNPREFIXED] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Dst32RnPrefixedQI: general register QI view */ { "Dst32RnPrefixedQI", M32C_OPERAND_DST32RNPREFIXEDQI, HW_H_GR_QI, 16, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_QI] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Dst32RnPrefixedHI: general register HI view */ { "Dst32RnPrefixedHI", M32C_OPERAND_DST32RNPREFIXEDHI, HW_H_GR_HI, 16, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_HI] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Dst32RnPrefixedSI: general register SI view */ { "Dst32RnPrefixedSI", M32C_OPERAND_DST32RNPREFIXEDSI, HW_H_GR_SI, 16, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_SI] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Dst16RnQI-S: general register QI view */ { "Dst16RnQI-S", M32C_OPERAND_DST16RNQI_S, HW_H_R0L_R0H, 5, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_QI_S] } }, - { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, /* Dst16AnQI-S: address register QI view */ { "Dst16AnQI-S", M32C_OPERAND_DST16ANQI_S, HW_H_AR_QI, 5, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_QI_S] } }, - { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, /* Bit16Rn: general register bit view */ { "Bit16Rn", M32C_OPERAND_BIT16RN, HW_H_GR_HI, 14, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } }, - { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, /* Bit32RnPrefixed: general register bit view */ { "Bit32RnPrefixed", M32C_OPERAND_BIT32RNPREFIXED, HW_H_GR_QI, 16, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_QI] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Bit32RnUnprefixed: general register bit view */ { "Bit32RnUnprefixed", M32C_OPERAND_BIT32RNUNPREFIXED, HW_H_GR_QI, 8, 2, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_QI] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* R0: r0 */ { "R0", M32C_OPERAND_R0, HW_H_R0, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* R1: r1 */ { "R1", M32C_OPERAND_R1, HW_H_R1, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* R2: r2 */ { "R2", M32C_OPERAND_R2, HW_H_R2, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* R3: r3 */ { "R3", M32C_OPERAND_R3, HW_H_R3, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* R0l: r0l */ { "R0l", M32C_OPERAND_R0L, HW_H_R0L, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* R0h: r0h */ { "R0h", M32C_OPERAND_R0H, HW_H_R0H, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* R2R0: r2r0 */ { "R2R0", M32C_OPERAND_R2R0, HW_H_R2R0, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* R3R1: r3r1 */ { "R3R1", M32C_OPERAND_R3R1, HW_H_R3R1, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* R1R2R0: r1r2r0 */ { "R1R2R0", M32C_OPERAND_R1R2R0, HW_H_R1R2R0, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dst16An: address register */ { "Dst16An", M32C_OPERAND_DST16AN, HW_H_AR, 15, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } }, - { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, /* Dst16AnQI: address register QI view */ { "Dst16AnQI", M32C_OPERAND_DST16ANQI, HW_H_AR_QI, 15, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } }, - { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, /* Dst16AnHI: address register HI view */ { "Dst16AnHI", M32C_OPERAND_DST16ANHI, HW_H_AR_HI, 15, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } }, - { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, /* Dst16AnSI: address register SI view */ { "Dst16AnSI", M32C_OPERAND_DST16ANSI, HW_H_AR_SI, 15, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } }, - { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, /* Dst16An-S: address register HI view */ { "Dst16An-S", M32C_OPERAND_DST16AN_S, HW_H_AR_HI, 4, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN_S] } }, - { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, /* Dst32AnUnprefixed: address register */ { "Dst32AnUnprefixed", M32C_OPERAND_DST32ANUNPREFIXED, HW_H_AR, 9, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Dst32AnUnprefixedQI: address register QI view */ { "Dst32AnUnprefixedQI", M32C_OPERAND_DST32ANUNPREFIXEDQI, HW_H_AR_QI, 9, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Dst32AnUnprefixedHI: address register HI view */ { "Dst32AnUnprefixedHI", M32C_OPERAND_DST32ANUNPREFIXEDHI, HW_H_AR_HI, 9, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Dst32AnUnprefixedSI: address register SI view */ { "Dst32AnUnprefixedSI", M32C_OPERAND_DST32ANUNPREFIXEDSI, HW_H_AR, 9, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Dst32AnExtUnprefixed: address register */ { "Dst32AnExtUnprefixed", M32C_OPERAND_DST32ANEXTUNPREFIXED, HW_H_AR, 9, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Dst32AnPrefixed: address register */ { "Dst32AnPrefixed", M32C_OPERAND_DST32ANPREFIXED, HW_H_AR, 17, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Dst32AnPrefixedQI: address register QI view */ { "Dst32AnPrefixedQI", M32C_OPERAND_DST32ANPREFIXEDQI, HW_H_AR_QI, 17, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Dst32AnPrefixedHI: address register HI view */ { "Dst32AnPrefixedHI", M32C_OPERAND_DST32ANPREFIXEDHI, HW_H_AR_HI, 17, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Dst32AnPrefixedSI: address register SI view */ { "Dst32AnPrefixedSI", M32C_OPERAND_DST32ANPREFIXEDSI, HW_H_AR, 17, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Bit16An: address register bit view */ { "Bit16An", M32C_OPERAND_BIT16AN, HW_H_AR, 15, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } }, - { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, /* Bit32AnPrefixed: address register bit */ { "Bit32AnPrefixed", M32C_OPERAND_BIT32ANPREFIXED, HW_H_AR, 17, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Bit32AnUnprefixed: address register bit */ { "Bit32AnUnprefixed", M32C_OPERAND_BIT32ANUNPREFIXED, HW_H_AR, 9, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* A0: a0 */ { "A0", M32C_OPERAND_A0, HW_H_A0, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* A1: a1 */ { "A1", M32C_OPERAND_A1, HW_H_A1, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* sb: SB register */ { "sb", M32C_OPERAND_SB, HW_H_SB, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* fb: FB register */ { "fb", M32C_OPERAND_FB, HW_H_FB, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* sp: SP register */ { "sp", M32C_OPERAND_SP, HW_H_SP, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* SrcDst16-r0l-r0h-S-normal: r0l/r0h pair */ { "SrcDst16-r0l-r0h-S-normal", M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL, HW_H_SINT, 5, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_5_1] } }, - { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, /* Regsetpop: popm regset */ { "Regsetpop", M32C_OPERAND_REGSETPOP, HW_H_UINT, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_8_8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Regsetpush: pushm regset */ { "Regsetpush", M32C_OPERAND_REGSETPUSH, HW_H_UINT, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_8_8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Rn16-push-S: r0[lh] */ { "Rn16-push-S", M32C_OPERAND_RN16_PUSH_S, HW_H_GR_QI, 4, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_4_1] } }, - { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, /* An16-push-S: a[01] */ { "An16-push-S", M32C_OPERAND_AN16_PUSH_S, HW_H_AR_HI, 4, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_4_1] } }, - { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } }, /* Dsp-8-u6: unsigned 6 bit displacement at offset 8 bits */ { "Dsp-8-u6", M32C_OPERAND_DSP_8_U6, HW_H_UINT, 8, 6, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U6] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-8-u8: unsigned 8 bit displacement at offset 8 bits */ { "Dsp-8-u8", M32C_OPERAND_DSP_8_U8, HW_H_UINT, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-8-u16: unsigned 16 bit displacement at offset 8 bits */ { "Dsp-8-u16", M32C_OPERAND_DSP_8_U16, HW_H_UINT, 8, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U16] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-8-s8: signed 8 bit displacement at offset 8 bits */ { "Dsp-8-s8", M32C_OPERAND_DSP_8_S8, HW_H_SINT, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-8-s24: signed 24 bit displacement at offset 8 bits */ { "Dsp-8-s24", M32C_OPERAND_DSP_8_S24, HW_H_SINT, 8, 24, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S24] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-8-u24: unsigned 24 bit displacement at offset 8 bits */ { "Dsp-8-u24", M32C_OPERAND_DSP_8_U24, HW_H_UINT, 8, 24, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U24] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-10-u6: unsigned 6 bit displacement at offset 10 bits */ { "Dsp-10-u6", M32C_OPERAND_DSP_10_U6, HW_H_UINT, 10, 6, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_10_U6] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-16-u8: unsigned 8 bit displacement at offset 16 bits */ { "Dsp-16-u8", M32C_OPERAND_DSP_16_U8, HW_H_UINT, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-16-u16: unsigned 16 bit displacement at offset 16 bits */ { "Dsp-16-u16", M32C_OPERAND_DSP_16_U16, HW_H_UINT, 16, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-16-u20: unsigned 20 bit displacement at offset 16 bits */ { "Dsp-16-u20", M32C_OPERAND_DSP_16_U20, HW_H_UINT, 0, 24, { 2, { (const PTR) &M32C_F_DSP_16_U24_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-16-u24: unsigned 24 bit displacement at offset 16 bits */ { "Dsp-16-u24", M32C_OPERAND_DSP_16_U24, HW_H_UINT, 0, 24, { 2, { (const PTR) &M32C_F_DSP_16_U24_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-16-s8: signed 8 bit displacement at offset 16 bits */ { "Dsp-16-s8", M32C_OPERAND_DSP_16_S8, HW_H_SINT, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-16-s16: signed 16 bit displacement at offset 16 bits */ { "Dsp-16-s16", M32C_OPERAND_DSP_16_S16, HW_H_SINT, 16, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-24-u8: unsigned 8 bit displacement at offset 24 bits */ { "Dsp-24-u8", M32C_OPERAND_DSP_24_U8, HW_H_UINT, 24, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-24-u16: unsigned 16 bit displacement at offset 24 bits */ { "Dsp-24-u16", M32C_OPERAND_DSP_24_U16, HW_H_UINT, 0, 16, { 2, { (const PTR) &M32C_F_DSP_24_U16_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-24-u20: unsigned 20 bit displacement at offset 24 bits */ { "Dsp-24-u20", M32C_OPERAND_DSP_24_U20, HW_H_UINT, 0, 24, { 2, { (const PTR) &M32C_F_DSP_24_U24_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-24-u24: unsigned 24 bit displacement at offset 24 bits */ { "Dsp-24-u24", M32C_OPERAND_DSP_24_U24, HW_H_UINT, 0, 24, { 2, { (const PTR) &M32C_F_DSP_24_U24_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-24-s8: signed 8 bit displacement at offset 24 bits */ { "Dsp-24-s8", M32C_OPERAND_DSP_24_S8, HW_H_SINT, 24, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-24-s16: signed 16 bit displacement at offset 24 bits */ { "Dsp-24-s16", M32C_OPERAND_DSP_24_S16, HW_H_SINT, 0, 16, { 2, { (const PTR) &M32C_F_DSP_24_S16_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-32-u8: unsigned 8 bit displacement at offset 32 bits */ { "Dsp-32-u8", M32C_OPERAND_DSP_32_U8, HW_H_UINT, 0, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-32-u16: unsigned 16 bit displacement at offset 32 bits */ { "Dsp-32-u16", M32C_OPERAND_DSP_32_U16, HW_H_UINT, 0, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-32-u24: unsigned 24 bit displacement at offset 32 bits */ { "Dsp-32-u24", M32C_OPERAND_DSP_32_U24, HW_H_UINT, 0, 24, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-32-u20: unsigned 20 bit displacement at offset 32 bits */ { "Dsp-32-u20", M32C_OPERAND_DSP_32_U20, HW_H_UINT, 0, 24, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-32-s8: signed 8 bit displacement at offset 32 bits */ { "Dsp-32-s8", M32C_OPERAND_DSP_32_S8, HW_H_SINT, 0, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-32-s16: signed 16 bit displacement at offset 32 bits */ { "Dsp-32-s16", M32C_OPERAND_DSP_32_S16, HW_H_SINT, 0, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S16] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-40-u8: unsigned 8 bit displacement at offset 40 bits */ { "Dsp-40-u8", M32C_OPERAND_DSP_40_U8, HW_H_UINT, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-40-s8: signed 8 bit displacement at offset 40 bits */ { "Dsp-40-s8", M32C_OPERAND_DSP_40_S8, HW_H_SINT, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-40-u16: unsigned 16 bit displacement at offset 40 bits */ { "Dsp-40-u16", M32C_OPERAND_DSP_40_U16, HW_H_UINT, 8, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U16] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-40-s16: signed 16 bit displacement at offset 40 bits */ { "Dsp-40-s16", M32C_OPERAND_DSP_40_S16, HW_H_SINT, 8, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-40-u24: unsigned 24 bit displacement at offset 40 bits */ { "Dsp-40-u24", M32C_OPERAND_DSP_40_U24, HW_H_UINT, 8, 24, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U24] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-48-u8: unsigned 8 bit displacement at offset 48 bits */ { "Dsp-48-u8", M32C_OPERAND_DSP_48_U8, HW_H_UINT, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-48-s8: signed 8 bit displacement at offset 48 bits */ { "Dsp-48-s8", M32C_OPERAND_DSP_48_S8, HW_H_SINT, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-48-u16: unsigned 16 bit displacement at offset 48 bits */ { "Dsp-48-u16", M32C_OPERAND_DSP_48_U16, HW_H_UINT, 16, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-48-s16: signed 16 bit displacement at offset 48 bits */ { "Dsp-48-s16", M32C_OPERAND_DSP_48_S16, HW_H_SINT, 16, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Dsp-48-u24: unsigned 24 bit displacement at offset 48 bits */ { "Dsp-48-u24", M32C_OPERAND_DSP_48_U24, HW_H_UINT, 0, 24, { 2, { (const PTR) &M32C_F_DSP_48_U24_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-8-s4: signed 4 bit immediate at offset 8 bits */ { "Imm-8-s4", M32C_OPERAND_IMM_8_S4, HW_H_SINT, 8, 4, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-8-s4n: negated 4 bit immediate at offset 8 bits */ { "Imm-8-s4n", M32C_OPERAND_IMM_8_S4N, HW_H_SINT, 8, 4, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-sh-8-s4: signed 4 bit shift immediate at offset 8 bits */ { "Imm-sh-8-s4", M32C_OPERAND_IMM_SH_8_S4, HW_H_SHIMM, 8, 4, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-8-QI: signed 8 bit immediate at offset 8 bits */ { "Imm-8-QI", M32C_OPERAND_IMM_8_QI, HW_H_SINT, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-8-HI: signed 16 bit immediate at offset 8 bits */ { "Imm-8-HI", M32C_OPERAND_IMM_8_HI, HW_H_SINT, 8, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S16] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-12-s4: signed 4 bit immediate at offset 12 bits */ { "Imm-12-s4", M32C_OPERAND_IMM_12_S4, HW_H_SINT, 12, 4, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-12-s4n: negated 4 bit immediate at offset 12 bits */ { "Imm-12-s4n", M32C_OPERAND_IMM_12_S4N, HW_H_SINT, 12, 4, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-sh-12-s4: signed 4 bit shift immediate at offset 12 bits */ { "Imm-sh-12-s4", M32C_OPERAND_IMM_SH_12_S4, HW_H_SHIMM, 12, 4, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-13-u3: signed 3 bit immediate at offset 13 bits */ { "Imm-13-u3", M32C_OPERAND_IMM_13_U3, HW_H_SINT, 13, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_13_U3] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-20-s4: signed 4 bit immediate at offset 20 bits */ { "Imm-20-s4", M32C_OPERAND_IMM_20_S4, HW_H_SINT, 20, 4, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_20_S4] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-sh-20-s4: signed 4 bit shift immediate at offset 12 bits */ { "Imm-sh-20-s4", M32C_OPERAND_IMM_SH_20_S4, HW_H_SHIMM, 20, 4, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_20_S4] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-16-QI: signed 8 bit immediate at offset 16 bits */ { "Imm-16-QI", M32C_OPERAND_IMM_16_QI, HW_H_SINT, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-16-HI: signed 16 bit immediate at offset 16 bits */ { "Imm-16-HI", M32C_OPERAND_IMM_16_HI, HW_H_SINT, 16, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-16-SI: signed 32 bit immediate at offset 16 bits */ { "Imm-16-SI", M32C_OPERAND_IMM_16_SI, HW_H_SINT, 0, 32, { 2, { (const PTR) &M32C_F_DSP_16_S32_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-24-QI: signed 8 bit immediate at offset 24 bits */ { "Imm-24-QI", M32C_OPERAND_IMM_24_QI, HW_H_SINT, 24, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-24-HI: signed 16 bit immediate at offset 24 bits */ { "Imm-24-HI", M32C_OPERAND_IMM_24_HI, HW_H_SINT, 0, 16, { 2, { (const PTR) &M32C_F_DSP_24_S16_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-24-SI: signed 32 bit immediate at offset 24 bits */ { "Imm-24-SI", M32C_OPERAND_IMM_24_SI, HW_H_SINT, 0, 32, { 2, { (const PTR) &M32C_F_DSP_24_S32_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-32-QI: signed 8 bit immediate at offset 32 bits */ { "Imm-32-QI", M32C_OPERAND_IMM_32_QI, HW_H_SINT, 0, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-32-SI: signed 32 bit immediate at offset 32 bits */ { "Imm-32-SI", M32C_OPERAND_IMM_32_SI, HW_H_SINT, 0, 32, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S32] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-32-HI: signed 16 bit immediate at offset 32 bits */ { "Imm-32-HI", M32C_OPERAND_IMM_32_HI, HW_H_SINT, 0, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S16] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-40-QI: signed 8 bit immediate at offset 40 bits */ { "Imm-40-QI", M32C_OPERAND_IMM_40_QI, HW_H_SINT, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-40-HI: signed 16 bit immediate at offset 40 bits */ { "Imm-40-HI", M32C_OPERAND_IMM_40_HI, HW_H_SINT, 8, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-40-SI: signed 32 bit immediate at offset 40 bits */ { "Imm-40-SI", M32C_OPERAND_IMM_40_SI, HW_H_SINT, 0, 32, { 2, { (const PTR) &M32C_F_DSP_40_S32_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-48-QI: signed 8 bit immediate at offset 48 bits */ { "Imm-48-QI", M32C_OPERAND_IMM_48_QI, HW_H_SINT, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-48-HI: signed 16 bit immediate at offset 48 bits */ { "Imm-48-HI", M32C_OPERAND_IMM_48_HI, HW_H_SINT, 16, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-48-SI: signed 32 bit immediate at offset 48 bits */ { "Imm-48-SI", M32C_OPERAND_IMM_48_SI, HW_H_SINT, 0, 32, { 2, { (const PTR) &M32C_F_DSP_48_S32_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-56-QI: signed 8 bit immediate at offset 56 bits */ { "Imm-56-QI", M32C_OPERAND_IMM_56_QI, HW_H_SINT, 24, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_56_S8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-56-HI: signed 16 bit immediate at offset 56 bits */ { "Imm-56-HI", M32C_OPERAND_IMM_56_HI, HW_H_SINT, 0, 16, { 2, { (const PTR) &M32C_F_DSP_56_S16_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm-64-HI: signed 16 bit immediate at offset 64 bits */ { "Imm-64-HI", M32C_OPERAND_IMM_64_HI, HW_H_SINT, 0, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_S16] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Imm1-S: signed 1 bit immediate for short format binary insns */ { "Imm1-S", M32C_OPERAND_IMM1_S, HW_H_SINT, 2, 1, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM1_S] } }, - { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* Imm3-S: signed 3 bit immediate for short format binary insns */ { "Imm3-S", M32C_OPERAND_IMM3_S, HW_H_SINT, 2, 3, { 2, { (const PTR) &M32C_F_IMM3_S_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* Bitno16R: bit number for indexing registers */ { "Bitno16R", M32C_OPERAND_BITNO16R, HW_H_UINT, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* Bitno32Prefixed: bit number for indexing objects */ { "Bitno32Prefixed", M32C_OPERAND_BITNO32PREFIXED, HW_H_UINT, 21, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* Bitno32Unprefixed: bit number for indexing objects */ { "Bitno32Unprefixed", M32C_OPERAND_BITNO32UNPREFIXED, HW_H_UINT, 13, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* BitBase16-16-u8: unsigned bit,base:8 at offset 16for m16c */ { "BitBase16-16-u8", M32C_OPERAND_BITBASE16_16_U8, HW_H_UINT, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* BitBase16-16-s8: signed bit,base:8 at offset 16for m16c */ { "BitBase16-16-s8", M32C_OPERAND_BITBASE16_16_S8, HW_H_SINT, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* BitBase16-16-u16: unsigned bit,base:16 at offset 16 for m16c */ { "BitBase16-16-u16", M32C_OPERAND_BITBASE16_16_U16, HW_H_UINT, 16, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* BitBase16-8-u11-S: signed bit,base:11 at offset 16 for m16c */ { "BitBase16-8-u11-S", M32C_OPERAND_BITBASE16_8_U11_S, HW_H_UINT, 5, 11, { 2, { (const PTR) &M32C_F_BITBASE16_U11_S_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* BitBase32-16-u11-Unprefixed: unsigned bit,base:11 at offset 16 for m32c */ { "BitBase32-16-u11-Unprefixed", M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, HW_H_UINT, 13, 11, { 2, { (const PTR) &M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* BitBase32-16-s11-Unprefixed: signed bit,base:11 at offset 16 for m32c */ { "BitBase32-16-s11-Unprefixed", M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, HW_H_SINT, 13, 11, { 2, { (const PTR) &M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* BitBase32-16-u19-Unprefixed: unsigned bit,base:19 at offset 16 for m32c */ { "BitBase32-16-u19-Unprefixed", M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, HW_H_UINT, 13, 19, { 2, { (const PTR) &M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* BitBase32-16-s19-Unprefixed: signed bit,base:19 at offset 16 for m32c */ { "BitBase32-16-s19-Unprefixed", M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, HW_H_SINT, 13, 19, { 2, { (const PTR) &M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* BitBase32-16-u27-Unprefixed: unsigned bit,base:27 at offset 16 for m32c */ { "BitBase32-16-u27-Unprefixed", M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, HW_H_UINT, 0, 27, { 3, { (const PTR) &M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* BitBase32-24-u11-Prefixed: unsigned bit,base:11 at offset 24 for m32c */ { "BitBase32-24-u11-Prefixed", M32C_OPERAND_BITBASE32_24_U11_PREFIXED, HW_H_UINT, 21, 11, { 2, { (const PTR) &M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* BitBase32-24-s11-Prefixed: signed bit,base:11 at offset 24 for m32c */ { "BitBase32-24-s11-Prefixed", M32C_OPERAND_BITBASE32_24_S11_PREFIXED, HW_H_SINT, 21, 11, { 2, { (const PTR) &M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* BitBase32-24-u19-Prefixed: unsigned bit,base:19 at offset 24 for m32c */ { "BitBase32-24-u19-Prefixed", M32C_OPERAND_BITBASE32_24_U19_PREFIXED, HW_H_UINT, 0, 19, { 3, { (const PTR) &M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* BitBase32-24-s19-Prefixed: signed bit,base:19 at offset 24 for m32c */ { "BitBase32-24-s19-Prefixed", M32C_OPERAND_BITBASE32_24_S19_PREFIXED, HW_H_SINT, 0, 19, { 3, { (const PTR) &M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* BitBase32-24-u27-Prefixed: unsigned bit,base:27 at offset 24 for m32c */ { "BitBase32-24-u27-Prefixed", M32C_OPERAND_BITBASE32_24_U27_PREFIXED, HW_H_UINT, 0, 27, { 3, { (const PTR) &M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* Lab-5-3: 3 bit label */ { "Lab-5-3", M32C_OPERAND_LAB_5_3, HW_H_IADDR, 5, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_5_3] } }, - { 0|A(RELAX)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Lab32-jmp-s: 3 bit label */ { "Lab32-jmp-s", M32C_OPERAND_LAB32_JMP_S, HW_H_IADDR, 2, 3, { 2, { (const PTR) &M32C_F_LAB32_JMP_S_MULTI_IFIELD[0] } }, - { 0|A(RELAX)|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(RELAX)|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Lab-8-8: 8 bit label */ { "Lab-8-8", M32C_OPERAND_LAB_8_8, HW_H_IADDR, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_8] } }, - { 0|A(RELAX)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Lab-8-16: 16 bit label */ { "Lab-8-16", M32C_OPERAND_LAB_8_16, HW_H_IADDR, 8, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_16] } }, - { 0|A(RELAX)|A(SIGN_OPT)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(RELAX)|A(SIGN_OPT)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Lab-8-24: 24 bit label */ { "Lab-8-24", M32C_OPERAND_LAB_8_24, HW_H_IADDR, 8, 24, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_24] } }, - { 0|A(ABS_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Lab-16-8: 8 bit label */ { "Lab-16-8", M32C_OPERAND_LAB_16_8, HW_H_IADDR, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_16_8] } }, - { 0|A(RELAX)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Lab-24-8: 8 bit label */ { "Lab-24-8", M32C_OPERAND_LAB_24_8, HW_H_IADDR, 24, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_24_8] } }, - { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Lab-32-8: 8 bit label */ { "Lab-32-8", M32C_OPERAND_LAB_32_8, HW_H_IADDR, 0, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_32_8] } }, - { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Lab-40-8: 8 bit label */ { "Lab-40-8", M32C_OPERAND_LAB_40_8, HW_H_IADDR, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_40_8] } }, - { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* sbit: negative bit */ { "sbit", M32C_OPERAND_SBIT, HW_H_SBIT, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* obit: overflow bit */ { "obit", M32C_OPERAND_OBIT, HW_H_OBIT, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* zbit: zero bit */ { "zbit", M32C_OPERAND_ZBIT, HW_H_ZBIT, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* cbit: carry bit */ { "cbit", M32C_OPERAND_CBIT, HW_H_CBIT, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* ubit: stack ptr select bit */ { "ubit", M32C_OPERAND_UBIT, HW_H_UBIT, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* ibit: interrupt enable bit */ { "ibit", M32C_OPERAND_IBIT, HW_H_IBIT, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* bbit: reg bank select bit */ { "bbit", M32C_OPERAND_BBIT, HW_H_BBIT, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* dbit: debug bit */ { "dbit", M32C_OPERAND_DBIT, HW_H_DBIT, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* cond16-16: condition */ { "cond16-16", M32C_OPERAND_COND16_16, HW_H_COND16, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cond16-24: condition */ { "cond16-24", M32C_OPERAND_COND16_24, HW_H_COND16, 24, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cond16-32: condition */ { "cond16-32", M32C_OPERAND_COND16_32, HW_H_COND16, 0, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cond32-16: condition */ { "cond32-16", M32C_OPERAND_COND32_16, HW_H_COND32, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cond32-24: condition */ { "cond32-24", M32C_OPERAND_COND32_24, HW_H_COND32, 24, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cond32-32: condition */ { "cond32-32", M32C_OPERAND_COND32_32, HW_H_COND32, 0, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cond32-40: condition */ { "cond32-40", M32C_OPERAND_COND32_40, HW_H_COND32, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U8] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cond16c: condition */ { "cond16c", M32C_OPERAND_COND16C, HW_H_COND16C, 12, 4, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cond16j: condition */ { "cond16j", M32C_OPERAND_COND16J, HW_H_COND16J, 12, 4, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cond16j5: condition */ { "cond16j5", M32C_OPERAND_COND16J5, HW_H_COND16J_5, 5, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16J_5] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cond32: condition */ { "cond32", M32C_OPERAND_COND32, HW_H_COND32, 9, 4, { 2, { (const PTR) &M32C_F_COND32_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cond32j: condition */ { "cond32j", M32C_OPERAND_COND32J, HW_H_COND32, 1, 4, { 2, { (const PTR) &M32C_F_COND32J_MULTI_IFIELD[0] } }, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sccond32: scCND condition */ { "sccond32", M32C_OPERAND_SCCOND32, HW_H_COND32, 12, 4, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* flags16: flags */ { "flags16", M32C_OPERAND_FLAGS16, HW_H_FLAGS, 9, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_3] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* flags32: flags */ { "flags32", M32C_OPERAND_FLAGS32, HW_H_FLAGS, 13, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cr16: control */ { "cr16", M32C_OPERAND_CR16, HW_H_CR_16, 9, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_3] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cr1-Unprefixed-32: control */ { "cr1-Unprefixed-32", M32C_OPERAND_CR1_UNPREFIXED_32, HW_H_CR1_32, 13, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cr1-Prefixed-32: control */ { "cr1-Prefixed-32", M32C_OPERAND_CR1_PREFIXED_32, HW_H_CR1_32, 21, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_21_3] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cr2-32: control */ { "cr2-32", M32C_OPERAND_CR2_32, HW_H_CR2_32, 13, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cr3-Unprefixed-32: control */ { "cr3-Unprefixed-32", M32C_OPERAND_CR3_UNPREFIXED_32, HW_H_CR3_32, 13, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cr3-Prefixed-32: control */ { "cr3-Prefixed-32", M32C_OPERAND_CR3_PREFIXED_32, HW_H_CR3_32, 21, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_21_3] } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* Z: Suffix for zero format insns */ { "Z", M32C_OPERAND_Z, HW_H_SINT, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* S: Suffix for short format insns */ { "S", M32C_OPERAND_S, HW_H_SINT, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* Q: Suffix for quick format insns */ { "Q", M32C_OPERAND_Q, HW_H_SINT, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* G: Suffix for general format insns */ { "G", M32C_OPERAND_G, HW_H_SINT, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* X: Empty suffix */ { "X", M32C_OPERAND_X, HW_H_SINT, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* size: any size specifier */ { "size", M32C_OPERAND_SIZE, HW_H_SINT, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* BitIndex: Bit Index for the next insn */ { "BitIndex", M32C_OPERAND_BITINDEX, HW_H_BIT_INDEX, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* SrcIndex: Source Index for the next insn */ { "SrcIndex", M32C_OPERAND_SRCINDEX, HW_H_SRC_INDEX, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* DstIndex: Destination Index for the next insn */ { "DstIndex", M32C_OPERAND_DSTINDEX, HW_H_DST_INDEX, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* NoRemainder: Place holder for when the remainder is not kept */ { "NoRemainder", M32C_OPERAND_NOREMAINDER, HW_H_NONE, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_M32C), (1<<ISA_M32C) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } }, /* src16-Rn-direct-QI: m16c Rn direct source QI */ /* src16-Rn-direct-HI: m16c Rn direct source HI */ /* src32-Rn-direct-Unprefixed-QI: m32c Rn direct source QI */ @@ -2649,7 +2649,7 @@ const CGEN_OPERAND m32c_cgen_operand_table[] = /* sentinel */ { 0, 0, 0, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { 0 } } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } } }; #undef A @@ -2669,16596 +2669,16596 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] = /* Special null first entry. A `num' value of zero is thus invalid. Also, the special `invalid' insn resides here. */ - { 0, 0, 0, 0, {0, {0}} }, + { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16},$Dst32RnPrefixedHI */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16},$Dst32AnPrefixedHI */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u24},$Dst32RnPrefixedHI */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u24},$Dst32AnPrefixedHI */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "extz", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "extz", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "extz", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "extz", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "extz", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "extz", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "extz", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "extz", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "extz", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "extz", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "extz", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "extz", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "extz", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz $Src32RnPrefixedQI,$Dst32RnPrefixedHI */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz [$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz $Src32RnPrefixedQI,$Dst32AnPrefixedHI */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz [$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "extz", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "extz", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "extz", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "extz", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "extz", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "extz", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz $Src32RnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "extz", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz $Src32RnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* extz [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "extz", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16},$Dst32RnPrefixedHI */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16},$Dst32AnPrefixedHI */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u24},$Dst32RnPrefixedHI */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u24},$Dst32AnPrefixedHI */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "exts.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "exts.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "exts.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "exts.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "exts.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "exts.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "exts.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "exts.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "exts.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "exts.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "exts.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "exts.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "exts.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b $Src32RnPrefixedQI,$Dst32RnPrefixedHI */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b [$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b $Src32RnPrefixedQI,$Dst32AnPrefixedHI */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b [$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "exts.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "exts.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "exts.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "exts.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "exts.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "exts.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b $Src32RnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b $Src32RnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "exts.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.w $Dst32RnExtUnprefixedHI */ { M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_RN_DIRECT_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-Rn-direct-ExtUnprefixed-HI", "exts.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.w $Dst32AnUnprefixedSI */ { M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "exts32.w-16-ExtUnprefixed-dst32-An-direct-Unprefixed-SI", "exts.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.w [$Dst32AnExtUnprefixed] */ { M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_AN_INDIRECT_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-An-indirect-ExtUnprefixed-HI", "exts.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.w ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */ { M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-An-relative-ExtUnprefixed-HI", "exts.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.w ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */ { M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-An-relative-ExtUnprefixed-HI", "exts.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.w ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */ { M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-24-An-relative-ExtUnprefixed-HI", "exts.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.w ${Dsp-16-u8}[sb] */ { M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-SB-relative-ExtUnprefixed-HI", "exts.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.w ${Dsp-16-u16}[sb] */ { M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-SB-relative-ExtUnprefixed-HI", "exts.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.w ${Dsp-16-s8}[fb] */ { M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-FB-relative-ExtUnprefixed-HI", "exts.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.w ${Dsp-16-s16}[fb] */ { M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-FB-relative-ExtUnprefixed-HI", "exts.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.w ${Dsp-16-u16} */ { M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-absolute-ExtUnprefixed-HI", "exts.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.w ${Dsp-16-u24} */ { M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-24-absolute-ExtUnprefixed-HI", "exts.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b $Dst32RnExtUnprefixedQI */ { M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_RN_DIRECT_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-Rn-direct-ExtUnprefixed-QI", "exts.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b $Dst32AnUnprefixedHI */ { M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "exts32.b-16-ExtUnprefixed-dst32-An-direct-Unprefixed-HI", "exts.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b [$Dst32AnExtUnprefixed] */ { M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_AN_INDIRECT_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-An-indirect-ExtUnprefixed-QI", "exts.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */ { M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-An-relative-ExtUnprefixed-QI", "exts.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */ { M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-An-relative-ExtUnprefixed-QI", "exts.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */ { M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-24-An-relative-ExtUnprefixed-QI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-16-u8}[sb] */ { M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-SB-relative-ExtUnprefixed-QI", "exts.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-16-u16}[sb] */ { M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-SB-relative-ExtUnprefixed-QI", "exts.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-16-s8}[fb] */ { M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-FB-relative-ExtUnprefixed-QI", "exts.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-16-s16}[fb] */ { M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-FB-relative-ExtUnprefixed-QI", "exts.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-16-u16} */ { M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-absolute-ExtUnprefixed-QI", "exts.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b ${Dsp-16-u24} */ { M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-24-absolute-ExtUnprefixed-QI", "exts.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.b $Dst16RnExtQI */ { M32C_INSN_EXTS16_B_16_EXT_DST16_RN_DIRECT_EXT_QI, "exts16.b-16-Ext-dst16-Rn-direct-Ext-QI", "exts.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* exts.b [$Dst16An] */ { M32C_INSN_EXTS16_B_16_EXT_DST16_AN_INDIRECT_EXT_QI, "exts16.b-16-Ext-dst16-An-indirect-Ext-QI", "exts.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* exts.b ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_AN_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-An-relative-Ext-QI", "exts.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* exts.b ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_AN_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-An-relative-Ext-QI", "exts.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* exts.b ${Dsp-16-u8}[sb] */ { M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_SB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-SB-relative-Ext-QI", "exts.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* exts.b ${Dsp-16-u16}[sb] */ { M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_SB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-SB-relative-Ext-QI", "exts.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* exts.b ${Dsp-16-s8}[fb] */ { M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_FB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-FB-relative-Ext-QI", "exts.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* exts.b ${Dsp-16-u16} */ { M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_ABSOLUTE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-absolute-Ext-QI", "exts.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "xor.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "xor.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "xor.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "xor.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "xor.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "xor.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "xor.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "xor.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "xor.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "xor.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "xor.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "xor.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "xor.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "xor.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "xor.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "xor.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "xor.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "xor.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "xor.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "xor.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "xor.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "xor.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "xor.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "xor.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16},$Dst16RnHI */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16},$Dst16AnHI */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} $Src16RnHI,$Dst16RnHI */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "xor.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} $Src16AnHI,$Dst16RnHI */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "xor.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} [$Src16An],$Dst16RnHI */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "xor.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} $Src16RnHI,$Dst16AnHI */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "xor.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} $Src16AnHI,$Dst16AnHI */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "xor.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} [$Src16An],$Dst16AnHI */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "xor.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} $Src16RnHI,[$Dst16An] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "xor.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} $Src16AnHI,[$Dst16An] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "xor.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} [$Src16An],[$Dst16An] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "xor.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "xor.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} $Src16RnHI,${Dsp-16-u16} */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} $Src16AnHI,${Dsp-16-u16} */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16},$Dst16RnQI */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16},$Dst16AnQI */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} $Src16RnQI,$Dst16RnQI */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "xor.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} $Src16AnQI,$Dst16RnQI */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "xor.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} [$Src16An],$Dst16RnQI */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "xor.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} $Src16RnQI,$Dst16AnQI */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "xor.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} $Src16AnQI,$Dst16AnQI */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "xor.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} [$Src16An],$Dst16AnQI */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "xor.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} $Src16RnQI,[$Dst16An] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "xor.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} $Src16AnQI,[$Dst16An] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "xor.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} [$Src16An],[$Dst16An] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "xor.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} $Src16RnQI,${Dsp-16-u16} */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} $Src16AnQI,${Dsp-16-u16} */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ { M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ { M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ { M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} #${Imm-40-HI},${Dsp-16-u24} */ { M32C_INSN_XOR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ { M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ { M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XOR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.b${G} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_XOR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xor.w${G} #${Imm-16-HI},$Dst16RnHI */ { M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "xor16.w-imm-G-basic-dst16-Rn-direct-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} #${Imm-16-HI},$Dst16AnHI */ { M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "xor16.w-imm-G-basic-dst16-An-direct-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} #${Imm-16-HI},[$Dst16An] */ { M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "xor16.w-imm-G-basic-dst16-An-indirect-HI", "xor.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "xor.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "xor16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "xor16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "xor16.w-imm-G-16-16-dst16-16-16-absolute-HI", "xor.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} #${Imm-16-QI},$Dst16RnQI */ { M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "xor16.b-imm-G-basic-dst16-Rn-direct-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} #${Imm-16-QI},$Dst16AnQI */ { M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "xor16.b-imm-G-basic-dst16-An-direct-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} #${Imm-16-QI},[$Dst16An] */ { M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "xor16.b-imm-G-basic-dst16-An-indirect-QI", "xor.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "xor.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "xor16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "xor16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "xor16.b-imm-G-16-16-dst16-16-16-absolute-QI", "xor.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r3,$Dst32RnUnprefixedHI */ { M32C_INSN_XCHG32W_R3_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r3,$Dst32AnUnprefixedHI */ { M32C_INSN_XCHG32W_R3_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-An-direct-Unprefixed-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r3,[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R3_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r3,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R3_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r3,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R3_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r3,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R3_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r3,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG32W_R3_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r3,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG32W_R3_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r3,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG32W_R3_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r3,${Dsp-16-s16}[fb] */ { M32C_INSN_XCHG32W_R3_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r3,${Dsp-16-u16} */ { M32C_INSN_XCHG32W_R3_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r3,${Dsp-16-u24} */ { M32C_INSN_XCHG32W_R3_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r2,$Dst32RnUnprefixedHI */ { M32C_INSN_XCHG32W_R2_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r2,$Dst32AnUnprefixedHI */ { M32C_INSN_XCHG32W_R2_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-An-direct-Unprefixed-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r2,[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R2_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r2,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R2_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r2,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R2_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r2,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R2_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r2,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG32W_R2_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r2,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG32W_R2_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r2,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG32W_R2_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r2,${Dsp-16-s16}[fb] */ { M32C_INSN_XCHG32W_R2_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r2,${Dsp-16-u16} */ { M32C_INSN_XCHG32W_R2_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r2,${Dsp-16-u24} */ { M32C_INSN_XCHG32W_R2_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w a1,$Dst32RnUnprefixedHI */ { M32C_INSN_XCHG32W_A1_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w a1,$Dst32AnUnprefixedHI */ { M32C_INSN_XCHG32W_A1_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-An-direct-Unprefixed-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w a1,[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_A1_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w a1,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG32W_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w a1,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG32W_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w a1,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG32W_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w a1,${Dsp-16-s16}[fb] */ { M32C_INSN_XCHG32W_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w a1,${Dsp-16-u16} */ { M32C_INSN_XCHG32W_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w a1,${Dsp-16-u24} */ { M32C_INSN_XCHG32W_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w a0,$Dst32RnUnprefixedHI */ { M32C_INSN_XCHG32W_A0_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w a0,$Dst32AnUnprefixedHI */ { M32C_INSN_XCHG32W_A0_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-An-direct-Unprefixed-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w a0,[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_A0_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w a0,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG32W_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w a0,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG32W_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w a0,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG32W_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w a0,${Dsp-16-s16}[fb] */ { M32C_INSN_XCHG32W_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w a0,${Dsp-16-u16} */ { M32C_INSN_XCHG32W_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w a0,${Dsp-16-u24} */ { M32C_INSN_XCHG32W_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r1,$Dst32RnUnprefixedHI */ { M32C_INSN_XCHG32W_R1_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r1,$Dst32AnUnprefixedHI */ { M32C_INSN_XCHG32W_R1_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-An-direct-Unprefixed-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r1,[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R1_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r1,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R1_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r1,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R1_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r1,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R1_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r1,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG32W_R1_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r1,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG32W_R1_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r1,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG32W_R1_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r1,${Dsp-16-s16}[fb] */ { M32C_INSN_XCHG32W_R1_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r1,${Dsp-16-u16} */ { M32C_INSN_XCHG32W_R1_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r1,${Dsp-16-u24} */ { M32C_INSN_XCHG32W_R1_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r0,$Dst32RnUnprefixedHI */ { M32C_INSN_XCHG32W_R0_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r0,$Dst32AnUnprefixedHI */ { M32C_INSN_XCHG32W_R0_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-An-direct-Unprefixed-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r0,[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R0_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r0,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R0_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r0,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R0_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r0,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32W_R0_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r0,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG32W_R0_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r0,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG32W_R0_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r0,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG32W_R0_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r0,${Dsp-16-s16}[fb] */ { M32C_INSN_XCHG32W_R0_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r0,${Dsp-16-u16} */ { M32C_INSN_XCHG32W_R0_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r0,${Dsp-16-u24} */ { M32C_INSN_XCHG32W_R0_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r1h,$Dst32RnUnprefixedQI */ { M32C_INSN_XCHG32B_R1H_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r1h,$Dst32AnUnprefixedQI */ { M32C_INSN_XCHG32B_R1H_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-An-direct-Unprefixed-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r1h,[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R1H_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R1H_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R1H_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R1H_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG32B_R1H_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG32B_R1H_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG32B_R1H_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r1h,${Dsp-16-s16}[fb] */ { M32C_INSN_XCHG32B_R1H_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r1h,${Dsp-16-u16} */ { M32C_INSN_XCHG32B_R1H_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r1h,${Dsp-16-u24} */ { M32C_INSN_XCHG32B_R1H_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r0h,$Dst32RnUnprefixedQI */ { M32C_INSN_XCHG32B_R0H_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r0h,$Dst32AnUnprefixedQI */ { M32C_INSN_XCHG32B_R0H_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-An-direct-Unprefixed-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r0h,[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R0H_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r0h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R0H_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r0h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R0H_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r0h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R0H_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r0h,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG32B_R0H_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r0h,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG32B_R0H_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r0h,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG32B_R0H_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r0h,${Dsp-16-s16}[fb] */ { M32C_INSN_XCHG32B_R0H_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r0h,${Dsp-16-u16} */ { M32C_INSN_XCHG32B_R0H_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r0h,${Dsp-16-u24} */ { M32C_INSN_XCHG32B_R0H_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b a1,$Dst32RnUnprefixedQI */ { M32C_INSN_XCHG32B_A1_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b a1,$Dst32AnUnprefixedQI */ { M32C_INSN_XCHG32B_A1_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-An-direct-Unprefixed-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b a1,[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_A1_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b a1,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG32B_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b a1,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG32B_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b a1,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG32B_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b a1,${Dsp-16-s16}[fb] */ { M32C_INSN_XCHG32B_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b a1,${Dsp-16-u16} */ { M32C_INSN_XCHG32B_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b a1,${Dsp-16-u24} */ { M32C_INSN_XCHG32B_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b a0,$Dst32RnUnprefixedQI */ { M32C_INSN_XCHG32B_A0_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b a0,$Dst32AnUnprefixedQI */ { M32C_INSN_XCHG32B_A0_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-An-direct-Unprefixed-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b a0,[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_A0_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b a0,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG32B_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b a0,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG32B_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b a0,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG32B_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b a0,${Dsp-16-s16}[fb] */ { M32C_INSN_XCHG32B_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b a0,${Dsp-16-u16} */ { M32C_INSN_XCHG32B_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b a0,${Dsp-16-u24} */ { M32C_INSN_XCHG32B_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r1l,$Dst32RnUnprefixedQI */ { M32C_INSN_XCHG32B_R1L_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r1l,$Dst32AnUnprefixedQI */ { M32C_INSN_XCHG32B_R1L_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-An-direct-Unprefixed-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r1l,[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R1L_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r1l,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R1L_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r1l,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R1L_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r1l,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R1L_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r1l,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG32B_R1L_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r1l,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG32B_R1L_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r1l,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG32B_R1L_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r1l,${Dsp-16-s16}[fb] */ { M32C_INSN_XCHG32B_R1L_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r1l,${Dsp-16-u16} */ { M32C_INSN_XCHG32B_R1L_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r1l,${Dsp-16-u24} */ { M32C_INSN_XCHG32B_R1L_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r0l,$Dst32RnUnprefixedQI */ { M32C_INSN_XCHG32B_R0L_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r0l,$Dst32AnUnprefixedQI */ { M32C_INSN_XCHG32B_R0L_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-An-direct-Unprefixed-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r0l,[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R0L_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r0l,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R0L_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r0l,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R0L_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r0l,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_XCHG32B_R0L_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r0l,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG32B_R0L_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r0l,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG32B_R0L_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r0l,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG32B_R0L_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r0l,${Dsp-16-s16}[fb] */ { M32C_INSN_XCHG32B_R0L_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r0l,${Dsp-16-u16} */ { M32C_INSN_XCHG32B_R0L_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.b r0l,${Dsp-16-u24} */ { M32C_INSN_XCHG32B_R0L_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* xchg.w r3,$Dst16RnHI */ { M32C_INSN_XCHG16W_R3_DST16_RN_DIRECT_HI, "xchg16w-r3-dst16-Rn-direct-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r3,$Dst16AnHI */ { M32C_INSN_XCHG16W_R3_DST16_AN_DIRECT_HI, "xchg16w-r3-dst16-An-direct-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r3,[$Dst16An] */ { M32C_INSN_XCHG16W_R3_DST16_AN_INDIRECT_HI, "xchg16w-r3-dst16-An-indirect-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r3,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XCHG16W_R3_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r3-dst16-16-8-An-relative-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r3,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XCHG16W_R3_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r3-dst16-16-16-An-relative-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r3,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG16W_R3_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r3-dst16-16-8-SB-relative-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r3,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG16W_R3_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r3-dst16-16-16-SB-relative-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r3,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG16W_R3_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r3-dst16-16-8-FB-relative-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r3,${Dsp-16-u16} */ { M32C_INSN_XCHG16W_R3_DST16_16_16_ABSOLUTE_HI, "xchg16w-r3-dst16-16-16-absolute-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r2,$Dst16RnHI */ { M32C_INSN_XCHG16W_R2_DST16_RN_DIRECT_HI, "xchg16w-r2-dst16-Rn-direct-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r2,$Dst16AnHI */ { M32C_INSN_XCHG16W_R2_DST16_AN_DIRECT_HI, "xchg16w-r2-dst16-An-direct-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r2,[$Dst16An] */ { M32C_INSN_XCHG16W_R2_DST16_AN_INDIRECT_HI, "xchg16w-r2-dst16-An-indirect-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r2,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XCHG16W_R2_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r2-dst16-16-8-An-relative-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r2,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XCHG16W_R2_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r2-dst16-16-16-An-relative-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r2,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG16W_R2_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r2-dst16-16-8-SB-relative-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r2,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG16W_R2_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r2-dst16-16-16-SB-relative-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r2,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG16W_R2_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r2-dst16-16-8-FB-relative-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r2,${Dsp-16-u16} */ { M32C_INSN_XCHG16W_R2_DST16_16_16_ABSOLUTE_HI, "xchg16w-r2-dst16-16-16-absolute-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r1,$Dst16RnHI */ { M32C_INSN_XCHG16W_R1_DST16_RN_DIRECT_HI, "xchg16w-r1-dst16-Rn-direct-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r1,$Dst16AnHI */ { M32C_INSN_XCHG16W_R1_DST16_AN_DIRECT_HI, "xchg16w-r1-dst16-An-direct-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r1,[$Dst16An] */ { M32C_INSN_XCHG16W_R1_DST16_AN_INDIRECT_HI, "xchg16w-r1-dst16-An-indirect-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r1,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XCHG16W_R1_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r1-dst16-16-8-An-relative-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r1,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XCHG16W_R1_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r1-dst16-16-16-An-relative-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r1,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG16W_R1_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r1-dst16-16-8-SB-relative-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r1,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG16W_R1_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r1-dst16-16-16-SB-relative-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r1,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG16W_R1_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r1-dst16-16-8-FB-relative-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r1,${Dsp-16-u16} */ { M32C_INSN_XCHG16W_R1_DST16_16_16_ABSOLUTE_HI, "xchg16w-r1-dst16-16-16-absolute-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r0,$Dst16RnHI */ { M32C_INSN_XCHG16W_R0_DST16_RN_DIRECT_HI, "xchg16w-r0-dst16-Rn-direct-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r0,$Dst16AnHI */ { M32C_INSN_XCHG16W_R0_DST16_AN_DIRECT_HI, "xchg16w-r0-dst16-An-direct-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r0,[$Dst16An] */ { M32C_INSN_XCHG16W_R0_DST16_AN_INDIRECT_HI, "xchg16w-r0-dst16-An-indirect-HI", "xchg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r0,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XCHG16W_R0_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r0-dst16-16-8-An-relative-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r0,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XCHG16W_R0_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r0-dst16-16-16-An-relative-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r0,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG16W_R0_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r0-dst16-16-8-SB-relative-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r0,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG16W_R0_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r0-dst16-16-16-SB-relative-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r0,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG16W_R0_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r0-dst16-16-8-FB-relative-HI", "xchg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.w r0,${Dsp-16-u16} */ { M32C_INSN_XCHG16W_R0_DST16_16_16_ABSOLUTE_HI, "xchg16w-r0-dst16-16-16-absolute-HI", "xchg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r1h,$Dst16RnQI */ { M32C_INSN_XCHG16B_R1H_DST16_RN_DIRECT_QI, "xchg16b-r1h-dst16-Rn-direct-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r1h,$Dst16AnQI */ { M32C_INSN_XCHG16B_R1H_DST16_AN_DIRECT_QI, "xchg16b-r1h-dst16-An-direct-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r1h,[$Dst16An] */ { M32C_INSN_XCHG16B_R1H_DST16_AN_INDIRECT_QI, "xchg16b-r1h-dst16-An-indirect-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r1h,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XCHG16B_R1H_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-An-relative-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r1h,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XCHG16B_R1H_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r1h-dst16-16-16-An-relative-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG16B_R1H_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-SB-relative-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG16B_R1H_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r1h-dst16-16-16-SB-relative-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG16B_R1H_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-FB-relative-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r1h,${Dsp-16-u16} */ { M32C_INSN_XCHG16B_R1H_DST16_16_16_ABSOLUTE_QI, "xchg16b-r1h-dst16-16-16-absolute-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r1l,$Dst16RnQI */ { M32C_INSN_XCHG16B_R1L_DST16_RN_DIRECT_QI, "xchg16b-r1l-dst16-Rn-direct-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r1l,$Dst16AnQI */ { M32C_INSN_XCHG16B_R1L_DST16_AN_DIRECT_QI, "xchg16b-r1l-dst16-An-direct-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r1l,[$Dst16An] */ { M32C_INSN_XCHG16B_R1L_DST16_AN_INDIRECT_QI, "xchg16b-r1l-dst16-An-indirect-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r1l,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XCHG16B_R1L_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-An-relative-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r1l,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XCHG16B_R1L_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r1l-dst16-16-16-An-relative-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r1l,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG16B_R1L_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-SB-relative-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r1l,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG16B_R1L_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r1l-dst16-16-16-SB-relative-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r1l,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG16B_R1L_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-FB-relative-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r1l,${Dsp-16-u16} */ { M32C_INSN_XCHG16B_R1L_DST16_16_16_ABSOLUTE_QI, "xchg16b-r1l-dst16-16-16-absolute-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r0h,$Dst16RnQI */ { M32C_INSN_XCHG16B_R0H_DST16_RN_DIRECT_QI, "xchg16b-r0h-dst16-Rn-direct-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r0h,$Dst16AnQI */ { M32C_INSN_XCHG16B_R0H_DST16_AN_DIRECT_QI, "xchg16b-r0h-dst16-An-direct-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r0h,[$Dst16An] */ { M32C_INSN_XCHG16B_R0H_DST16_AN_INDIRECT_QI, "xchg16b-r0h-dst16-An-indirect-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r0h,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XCHG16B_R0H_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-An-relative-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r0h,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XCHG16B_R0H_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r0h-dst16-16-16-An-relative-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r0h,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG16B_R0H_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-SB-relative-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r0h,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG16B_R0H_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r0h-dst16-16-16-SB-relative-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r0h,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG16B_R0H_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-FB-relative-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r0h,${Dsp-16-u16} */ { M32C_INSN_XCHG16B_R0H_DST16_16_16_ABSOLUTE_QI, "xchg16b-r0h-dst16-16-16-absolute-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r0l,$Dst16RnQI */ { M32C_INSN_XCHG16B_R0L_DST16_RN_DIRECT_QI, "xchg16b-r0l-dst16-Rn-direct-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r0l,$Dst16AnQI */ { M32C_INSN_XCHG16B_R0L_DST16_AN_DIRECT_QI, "xchg16b-r0l-dst16-An-direct-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r0l,[$Dst16An] */ { M32C_INSN_XCHG16B_R0L_DST16_AN_INDIRECT_QI, "xchg16b-r0l-dst16-An-indirect-QI", "xchg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r0l,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_XCHG16B_R0L_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-An-relative-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r0l,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_XCHG16B_R0L_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r0l-dst16-16-16-An-relative-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r0l,${Dsp-16-u8}[sb] */ { M32C_INSN_XCHG16B_R0L_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-SB-relative-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r0l,${Dsp-16-u16}[sb] */ { M32C_INSN_XCHG16B_R0L_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r0l-dst16-16-16-SB-relative-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r0l,${Dsp-16-s8}[fb] */ { M32C_INSN_XCHG16B_R0L_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-FB-relative-QI", "xchg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* xchg.b r0l,${Dsp-16-u16} */ { M32C_INSN_XCHG16B_R0L_DST16_16_16_ABSOLUTE_QI, "xchg16b-r0l-dst16-16-16-absolute-QI", "xchg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ { M32C_INSN_TST32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "tst32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ { M32C_INSN_TST32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "tst32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${S} #${Imm-24-HI},${Dsp-8-u16} */ { M32C_INSN_TST32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "tst32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${S} #${Imm-8-HI},r0 */ { M32C_INSN_TST32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "tst32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ { M32C_INSN_TST32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "tst32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ { M32C_INSN_TST32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "tst32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${S} #${Imm-24-QI},${Dsp-8-u16} */ { M32C_INSN_TST32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "tst32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${S} #${Imm-8-QI},r0l */ { M32C_INSN_TST32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "tst32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "tst.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16},$Dst32RnPrefixedHI */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16},$Dst32AnPrefixedHI */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u24},$Dst32RnPrefixedHI */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u24},$Dst32AnPrefixedHI */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "tst.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "tst.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "tst.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "tst.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "tst.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "tst.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "tst.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "tst.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "tst.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "tst.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "tst.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "tst.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16} */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16} */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u24} */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u24} */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16},$Dst32RnPrefixedQI */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16},$Dst32AnPrefixedQI */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u24},$Dst32RnPrefixedQI */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u24},$Dst32AnPrefixedQI */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "tst.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "tst.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "tst.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "tst.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "tst.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "tst.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "tst.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "tst.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "tst.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "tst.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "tst.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "tst.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "tst.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16},$Dst16RnHI */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16},$Dst16AnHI */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} $Src16RnHI,$Dst16RnHI */ { M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "tst.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} $Src16AnHI,$Dst16RnHI */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "tst.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} [$Src16An],$Dst16RnHI */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "tst.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} $Src16RnHI,$Dst16AnHI */ { M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "tst.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} $Src16AnHI,$Dst16AnHI */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "tst.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} [$Src16An],$Dst16AnHI */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "tst.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} $Src16RnHI,[$Dst16An] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "tst.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} $Src16AnHI,[$Dst16An] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "tst.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} [$Src16An],[$Dst16An] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "tst.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "tst.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} $Src16RnHI,${Dsp-16-u16} */ { M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} $Src16AnHI,${Dsp-16-u16} */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${X} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16},$Dst16RnQI */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16},$Dst16AnQI */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} $Src16RnQI,$Dst16RnQI */ { M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "tst.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} $Src16AnQI,$Dst16RnQI */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "tst.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} [$Src16An],$Dst16RnQI */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "tst.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} $Src16RnQI,$Dst16AnQI */ { M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "tst.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} $Src16AnQI,$Dst16AnQI */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "tst.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} [$Src16An],$Dst16AnQI */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "tst.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} $Src16RnQI,[$Dst16An] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "tst.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} $Src16AnQI,[$Dst16An] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "tst.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} [$Src16An],[$Dst16An] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "tst.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} $Src16RnQI,${Dsp-16-u16} */ { M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} $Src16AnQI,${Dsp-16-u16} */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${X} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ { M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ { M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ { M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ { M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_TST32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} #${Imm-40-HI},${Dsp-16-u24} */ { M32C_INSN_TST32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "tst32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "tst.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ { M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ { M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_TST32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.b${G} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_TST32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "tst32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "tst.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tst.w${G} #${Imm-16-HI},$Dst16RnHI */ { M32C_INSN_TST16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "tst16.w-imm-G-basic-dst16-Rn-direct-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${G} #${Imm-16-HI},$Dst16AnHI */ { M32C_INSN_TST16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "tst16.w-imm-G-basic-dst16-An-direct-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${G} #${Imm-16-HI},[$Dst16An] */ { M32C_INSN_TST16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "tst16.w-imm-G-basic-dst16-An-indirect-HI", "tst.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "tst.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "tst16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "tst16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "tst16.w-imm-G-16-16-dst16-16-16-absolute-HI", "tst.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${G} #${Imm-16-QI},$Dst16RnQI */ { M32C_INSN_TST16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "tst16.b-imm-G-basic-dst16-Rn-direct-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${G} #${Imm-16-QI},$Dst16AnQI */ { M32C_INSN_TST16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "tst16.b-imm-G-basic-dst16-An-direct-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${G} #${Imm-16-QI},[$Dst16An] */ { M32C_INSN_TST16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "tst16.b-imm-G-basic-dst16-An-indirect-QI", "tst.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "tst.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "tst16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "tst16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tst.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "tst16.b-imm-G-16-16-dst16-16-16-absolute-QI", "tst.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "subx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "subx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "subx", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "subx", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "subx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "subx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "subx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "subx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "subx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "subx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "subx", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "subx", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} #${Imm-16-QI},$Dst32RnUnprefixedSI */ { M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "subx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} #${Imm-16-QI},$Dst32AnUnprefixedSI */ { M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "subx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "subx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "subx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUBX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* subx${G} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_SUBX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "subx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32RnUnprefixedHI */ { M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stzx.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32AnUnprefixedHI */ { M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stzx.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx.w #${Imm-16-HI},#${Imm-32-HI},[$Dst32AnUnprefixed] */ { M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stzx.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stzx.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stzx.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stzx.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stzx.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stzx.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-s16}[fb] */ { M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stzx.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16} */ { M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stzx.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_STZX32_W_IMM_40_HI_IMM_56_HI_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-40-HI-Imm-56-HI-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stzx.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24} */ { M32C_INSN_STZX32_W_IMM_40_HI_IMM_56_HI_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stzx32.w-Imm-40-HI-Imm-56-HI-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stzx.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32RnUnprefixedQI */ { M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stzx.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32AnUnprefixedQI */ { M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stzx.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx.b #${Imm-16-QI},#${Imm-24-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stzx.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stzx.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stzx.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stzx.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stzx.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stzx.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stzx.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16} */ { M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stzx.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_STZX32_B_IMM_40_QI_IMM_48_QI_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-40-QI-Imm-48-QI-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stzx.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24} */ { M32C_INSN_STZX32_B_IMM_40_QI_IMM_48_QI_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stzx32.b-Imm-40-QI-Imm-48-QI-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stzx.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */ { M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stz.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */ { M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stz.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */ { M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stz.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stz.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stz.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stz.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stz.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stz.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */ { M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stz.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz.w${X} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stz.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_STZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stz.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz.w${X} #${Imm-40-HI},${Dsp-16-u24} */ { M32C_INSN_STZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stz32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stz.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */ { M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stz.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */ { M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stz.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stz.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stz.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stz.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stz.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stz.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stz.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stz.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz.b${X} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stz.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_STZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stz.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz.b${X} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_STZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stz32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stz.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stz${S} #${Imm-8-QI},r0l */ { M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "stz16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "stz", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stz${S} #${Imm-8-QI},r0h */ { M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "stz16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "stz", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "stz", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "stz", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stz${S} #${Imm-8-QI},${Dsp-16-u16} */ { M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "stz", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stnz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */ { M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stnz.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stnz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */ { M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stnz.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stnz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */ { M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stnz.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stnz.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stnz.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stnz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stnz.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stnz.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stnz.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stnz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */ { M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stnz.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stnz.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_STNZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stnz.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24} */ { M32C_INSN_STNZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stnz32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stnz.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stnz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */ { M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stnz.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stnz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */ { M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stnz.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stnz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stnz.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stnz.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stnz.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stnz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stnz.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stnz.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stnz.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stnz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stnz.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stnz.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_STNZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stnz.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_STNZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stnz32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stnz.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stnz${S} #${Imm-8-QI},r0l */ { M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "stnz", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stnz${S} #${Imm-8-QI},r0h */ { M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "stnz", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stnz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "stnz", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stnz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "stnz", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stnz${S} #${Imm-8-QI},${Dsp-16-u16} */ { M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "stnz", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shlnc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ { M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shlnc.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shlnc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ { M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shlnc.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shlnc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shlnc.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shlnc.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shlnc.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shlnc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shlnc.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shlnc.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shlnc.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shlnc.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shlnc.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHLNC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shlnc.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_SHLNC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shlnc.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.l r1h,$Dst32RnUnprefixedSI */ { M32C_INSN_SHL32_L_DST_DST32_RN_DIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-Rn-direct-Unprefixed-SI", "shl.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.l r1h,$Dst32AnUnprefixedSI */ { M32C_INSN_SHL32_L_DST_DST32_AN_DIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-An-direct-Unprefixed-SI", "shl.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.l r1h,[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_L_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-An-indirect-Unprefixed-SI", "shl.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_L_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-An-relative-Unprefixed-SI", "shl.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_L_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-An-relative-Unprefixed-SI", "shl.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_L_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-24-An-relative-Unprefixed-SI", "shl.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.l r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_SHL32_L_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-SB-relative-Unprefixed-SI", "shl.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.l r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_SHL32_L_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-SB-relative-Unprefixed-SI", "shl.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.l r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_SHL32_L_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-FB-relative-Unprefixed-SI", "shl.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.l r1h,${Dsp-16-s16}[fb] */ { M32C_INSN_SHL32_L_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-FB-relative-Unprefixed-SI", "shl.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.l r1h,${Dsp-16-u16} */ { M32C_INSN_SHL32_L_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-absolute-Unprefixed-SI", "shl.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.l r1h,${Dsp-16-u24} */ { M32C_INSN_SHL32_L_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-24-absolute-Unprefixed-SI", "shl.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ { M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shl.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ { M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shl.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shl.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shl.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shl.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shl.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shl.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shl.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shl.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.l${X} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shl.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shl.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.l${X} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_SHL32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shl32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shl.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w r1h,$Dst32RnUnprefixedHI */ { M32C_INSN_SHL32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-Rn-direct-Unprefixed-HI", "shl.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w r1h,$Dst32AnUnprefixedHI */ { M32C_INSN_SHL32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-An-direct-Unprefixed-HI", "shl.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w r1h,[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-An-indirect-Unprefixed-HI", "shl.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "shl.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "shl.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "shl.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_SHL32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "shl.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_SHL32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "shl.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_SHL32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "shl.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w r1h,${Dsp-16-s16}[fb] */ { M32C_INSN_SHL32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "shl.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w r1h,${Dsp-16-u16} */ { M32C_INSN_SHL32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "shl.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w r1h,${Dsp-16-u24} */ { M32C_INSN_SHL32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "shl.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.b r1h,$Dst32RnUnprefixedQI */ { M32C_INSN_SHL32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-Rn-direct-Unprefixed-QI", "shl.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.b r1h,$Dst32AnUnprefixedQI */ { M32C_INSN_SHL32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-An-direct-Unprefixed-QI", "shl.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.b r1h,[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-An-indirect-Unprefixed-QI", "shl.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "shl.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "shl.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "shl.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.b r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_SHL32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "shl.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.b r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_SHL32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "shl.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.b r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_SHL32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "shl.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.b r1h,${Dsp-16-s16}[fb] */ { M32C_INSN_SHL32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "shl.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.b r1h,${Dsp-16-u16} */ { M32C_INSN_SHL32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "shl.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.b r1h,${Dsp-16-u24} */ { M32C_INSN_SHL32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "shl.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w r1h,$Dst16RnHI */ { M32C_INSN_SHL16_W_DST_DST16_RN_DIRECT_HI, "shl16.w-dst-dst16-Rn-direct-HI", "shl.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.w r1h,$Dst16AnHI */ { M32C_INSN_SHL16_W_DST_DST16_AN_DIRECT_HI, "shl16.w-dst-dst16-An-direct-HI", "shl.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.w r1h,[$Dst16An] */ { M32C_INSN_SHL16_W_DST_DST16_AN_INDIRECT_HI, "shl16.w-dst-dst16-An-indirect-HI", "shl.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.w r1h,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SHL16_W_DST_DST16_16_8_AN_RELATIVE_HI, "shl16.w-dst-dst16-16-8-An-relative-HI", "shl.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.w r1h,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SHL16_W_DST_DST16_16_16_AN_RELATIVE_HI, "shl16.w-dst-dst16-16-16-An-relative-HI", "shl.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.w r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_SHL16_W_DST_DST16_16_8_SB_RELATIVE_HI, "shl16.w-dst-dst16-16-8-SB-relative-HI", "shl.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.w r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_SHL16_W_DST_DST16_16_16_SB_RELATIVE_HI, "shl16.w-dst-dst16-16-16-SB-relative-HI", "shl.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.w r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_SHL16_W_DST_DST16_16_8_FB_RELATIVE_HI, "shl16.w-dst-dst16-16-8-FB-relative-HI", "shl.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.w r1h,${Dsp-16-u16} */ { M32C_INSN_SHL16_W_DST_DST16_16_16_ABSOLUTE_HI, "shl16.w-dst-dst16-16-16-absolute-HI", "shl.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.b r1h,$Dst16RnQI */ { M32C_INSN_SHL16_B_DST_DST16_RN_DIRECT_QI, "shl16.b-dst-dst16-Rn-direct-QI", "shl.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.b r1h,$Dst16AnQI */ { M32C_INSN_SHL16_B_DST_DST16_AN_DIRECT_QI, "shl16.b-dst-dst16-An-direct-QI", "shl.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.b r1h,[$Dst16An] */ { M32C_INSN_SHL16_B_DST_DST16_AN_INDIRECT_QI, "shl16.b-dst-dst16-An-indirect-QI", "shl.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.b r1h,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SHL16_B_DST_DST16_16_8_AN_RELATIVE_QI, "shl16.b-dst-dst16-16-8-An-relative-QI", "shl.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.b r1h,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SHL16_B_DST_DST16_16_16_AN_RELATIVE_QI, "shl16.b-dst-dst16-16-16-An-relative-QI", "shl.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.b r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_SHL16_B_DST_DST16_16_8_SB_RELATIVE_QI, "shl16.b-dst-dst16-16-8-SB-relative-QI", "shl.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.b r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_SHL16_B_DST_DST16_16_16_SB_RELATIVE_QI, "shl16.b-dst-dst16-16-16-SB-relative-QI", "shl.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.b r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_SHL16_B_DST_DST16_16_8_FB_RELATIVE_QI, "shl16.b-dst-dst16-16-8-FB-relative-QI", "shl.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.b r1h,${Dsp-16-u16} */ { M32C_INSN_SHL16_B_DST_DST16_16_16_ABSOLUTE_QI, "shl16.b-dst-dst16-16-16-absolute-QI", "shl.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */ { M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "shl.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */ { M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "shl.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "shl.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "shl.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "shl.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "shl.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "shl.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "shl.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "shl.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */ { M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "shl.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */ { M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "shl.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */ { M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "shl.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */ { M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "shl.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */ { M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "shl.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "shl.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "shl.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "shl.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "shl.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "shl.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "shl.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "shl.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */ { M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "shl.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */ { M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "shl.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */ { M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "shl.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shl.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */ { M32C_INSN_SHL16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "shl16.w-imm4-Q-16-dst16-Rn-direct-HI", "shl.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */ { M32C_INSN_SHL16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "shl16.w-imm4-Q-16-dst16-An-direct-HI", "shl.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.w${Q} #${Imm-sh-8-s4},[$Dst16An] */ { M32C_INSN_SHL16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "shl16.w-imm4-Q-16-dst16-An-indirect-HI", "shl.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "shl.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "shl.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "shl.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "shl.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "shl.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */ { M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "shl16.w-imm4-Q-16-dst16-16-16-absolute-HI", "shl.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */ { M32C_INSN_SHL16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "shl16.b-imm4-Q-16-dst16-Rn-direct-QI", "shl.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */ { M32C_INSN_SHL16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "shl16.b-imm4-Q-16-dst16-An-direct-QI", "shl.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.b${Q} #${Imm-sh-8-s4},[$Dst16An] */ { M32C_INSN_SHL16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "shl16.b-imm4-Q-16-dst16-An-indirect-QI", "shl.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "shl.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "shl.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "shl.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "shl.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "shl.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */ { M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "shl16.b-imm4-Q-16-dst16-16-16-absolute-QI", "shl.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shanc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ { M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shanc.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shanc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ { M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shanc.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shanc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shanc.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shanc.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shanc.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shanc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shanc.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shanc.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shanc.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shanc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shanc.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shanc.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHANC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shanc.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_SHANC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shanc32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shanc.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l r1h,$Dst32RnUnprefixedSI */ { M32C_INSN_SHA32_L_DST_DST32_RN_DIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-Rn-direct-Unprefixed-SI", "sha.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l r1h,$Dst32AnUnprefixedSI */ { M32C_INSN_SHA32_L_DST_DST32_AN_DIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-An-direct-Unprefixed-SI", "sha.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l r1h,[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_L_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-An-indirect-Unprefixed-SI", "sha.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_L_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-An-relative-Unprefixed-SI", "sha.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_L_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-An-relative-Unprefixed-SI", "sha.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_L_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-24-An-relative-Unprefixed-SI", "sha.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_SHA32_L_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-SB-relative-Unprefixed-SI", "sha.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_SHA32_L_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-SB-relative-Unprefixed-SI", "sha.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_SHA32_L_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-FB-relative-Unprefixed-SI", "sha.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l r1h,${Dsp-16-s16}[fb] */ { M32C_INSN_SHA32_L_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-FB-relative-Unprefixed-SI", "sha.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l r1h,${Dsp-16-u16} */ { M32C_INSN_SHA32_L_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-absolute-Unprefixed-SI", "sha.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l r1h,${Dsp-16-u24} */ { M32C_INSN_SHA32_L_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-24-absolute-Unprefixed-SI", "sha.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ { M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "sha.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ { M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "sha.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "sha.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "sha.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "sha.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "sha.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "sha.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "sha.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "sha.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l${X} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "sha.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "sha.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l${X} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_SHA32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sha32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "sha.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w r1h,$Dst32RnUnprefixedHI */ { M32C_INSN_SHA32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-Rn-direct-Unprefixed-HI", "sha.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w r1h,$Dst32AnUnprefixedHI */ { M32C_INSN_SHA32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-An-direct-Unprefixed-HI", "sha.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w r1h,[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-An-indirect-Unprefixed-HI", "sha.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "sha.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "sha.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "sha.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_SHA32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "sha.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_SHA32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "sha.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_SHA32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "sha.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w r1h,${Dsp-16-s16}[fb] */ { M32C_INSN_SHA32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "sha.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w r1h,${Dsp-16-u16} */ { M32C_INSN_SHA32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "sha.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w r1h,${Dsp-16-u24} */ { M32C_INSN_SHA32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "sha.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.b r1h,$Dst32RnUnprefixedQI */ { M32C_INSN_SHA32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-Rn-direct-Unprefixed-QI", "sha.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.b r1h,$Dst32AnUnprefixedQI */ { M32C_INSN_SHA32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-An-direct-Unprefixed-QI", "sha.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.b r1h,[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-An-indirect-Unprefixed-QI", "sha.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "sha.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "sha.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "sha.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.b r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_SHA32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "sha.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.b r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_SHA32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "sha.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.b r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_SHA32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "sha.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.b r1h,${Dsp-16-s16}[fb] */ { M32C_INSN_SHA32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "sha.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.b r1h,${Dsp-16-u16} */ { M32C_INSN_SHA32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "sha.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.b r1h,${Dsp-16-u24} */ { M32C_INSN_SHA32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "sha.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w r1h,$Dst16RnHI */ { M32C_INSN_SHA16_W_DST_DST16_RN_DIRECT_HI, "sha16.w-dst-dst16-Rn-direct-HI", "sha.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.w r1h,$Dst16AnHI */ { M32C_INSN_SHA16_W_DST_DST16_AN_DIRECT_HI, "sha16.w-dst-dst16-An-direct-HI", "sha.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.w r1h,[$Dst16An] */ { M32C_INSN_SHA16_W_DST_DST16_AN_INDIRECT_HI, "sha16.w-dst-dst16-An-indirect-HI", "sha.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.w r1h,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SHA16_W_DST_DST16_16_8_AN_RELATIVE_HI, "sha16.w-dst-dst16-16-8-An-relative-HI", "sha.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.w r1h,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SHA16_W_DST_DST16_16_16_AN_RELATIVE_HI, "sha16.w-dst-dst16-16-16-An-relative-HI", "sha.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.w r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_SHA16_W_DST_DST16_16_8_SB_RELATIVE_HI, "sha16.w-dst-dst16-16-8-SB-relative-HI", "sha.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.w r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_SHA16_W_DST_DST16_16_16_SB_RELATIVE_HI, "sha16.w-dst-dst16-16-16-SB-relative-HI", "sha.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.w r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_SHA16_W_DST_DST16_16_8_FB_RELATIVE_HI, "sha16.w-dst-dst16-16-8-FB-relative-HI", "sha.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.w r1h,${Dsp-16-u16} */ { M32C_INSN_SHA16_W_DST_DST16_16_16_ABSOLUTE_HI, "sha16.w-dst-dst16-16-16-absolute-HI", "sha.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.b r1h,$Dst16RnQI */ { M32C_INSN_SHA16_B_DST_DST16_RN_DIRECT_QI, "sha16.b-dst-dst16-Rn-direct-QI", "sha.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.b r1h,$Dst16AnQI */ { M32C_INSN_SHA16_B_DST_DST16_AN_DIRECT_QI, "sha16.b-dst-dst16-An-direct-QI", "sha.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.b r1h,[$Dst16An] */ { M32C_INSN_SHA16_B_DST_DST16_AN_INDIRECT_QI, "sha16.b-dst-dst16-An-indirect-QI", "sha.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.b r1h,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SHA16_B_DST_DST16_16_8_AN_RELATIVE_QI, "sha16.b-dst-dst16-16-8-An-relative-QI", "sha.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.b r1h,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SHA16_B_DST_DST16_16_16_AN_RELATIVE_QI, "sha16.b-dst-dst16-16-16-An-relative-QI", "sha.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.b r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_SHA16_B_DST_DST16_16_8_SB_RELATIVE_QI, "sha16.b-dst-dst16-16-8-SB-relative-QI", "sha.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.b r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_SHA16_B_DST_DST16_16_16_SB_RELATIVE_QI, "sha16.b-dst-dst16-16-16-SB-relative-QI", "sha.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.b r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_SHA16_B_DST_DST16_16_8_FB_RELATIVE_QI, "sha16.b-dst-dst16-16-8-FB-relative-QI", "sha.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.b r1h,${Dsp-16-u16} */ { M32C_INSN_SHA16_B_DST_DST16_16_16_ABSOLUTE_QI, "sha16.b-dst-dst16-16-16-absolute-QI", "sha.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */ { M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sha.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */ { M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "sha.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sha.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sha.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sha.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sha.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sha.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sha.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sha.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */ { M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sha.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */ { M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sha.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */ { M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sha.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */ { M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sha.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */ { M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "sha.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sha.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sha.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sha.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sha.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sha.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sha.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sha.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */ { M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sha.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */ { M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sha.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */ { M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sha.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */ { M32C_INSN_SHA16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "sha16.w-imm4-Q-16-dst16-Rn-direct-HI", "sha.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */ { M32C_INSN_SHA16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "sha16.w-imm4-Q-16-dst16-An-direct-HI", "sha.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.w${Q} #${Imm-sh-8-s4},[$Dst16An] */ { M32C_INSN_SHA16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "sha16.w-imm4-Q-16-dst16-An-indirect-HI", "sha.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "sha.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "sha.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "sha.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "sha.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "sha.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */ { M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "sha16.w-imm4-Q-16-dst16-16-16-absolute-HI", "sha.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */ { M32C_INSN_SHA16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "sha16.b-imm4-Q-16-dst16-Rn-direct-QI", "sha.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */ { M32C_INSN_SHA16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "sha16.b-imm4-Q-16-dst16-An-direct-QI", "sha.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.b${Q} #${Imm-sh-8-s4},[$Dst16An] */ { M32C_INSN_SHA16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "sha16.b-imm4-Q-16-dst16-An-indirect-QI", "sha.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "sha.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "sha.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "sha.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "sha.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "sha.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */ { M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "sha16.b-imm4-Q-16-dst16-16-16-absolute-QI", "sha.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sc${sccond32} $Dst32RnUnprefixedHI */ { M32C_INSN_SCCND_DST32_RN_DIRECT_UNPREFIXED_HI, "sccnd-dst32-Rn-direct-Unprefixed-HI", "sc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sc${sccond32} $Dst32AnUnprefixedHI */ { M32C_INSN_SCCND_DST32_AN_DIRECT_UNPREFIXED_HI, "sccnd-dst32-An-direct-Unprefixed-HI", "sc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sc${sccond32} [$Dst32AnUnprefixed] */ { M32C_INSN_SCCND_DST32_AN_INDIRECT_UNPREFIXED_HI, "sccnd-dst32-An-indirect-Unprefixed-HI", "sc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sc${sccond32} ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SCCND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-An-relative-Unprefixed-HI", "sc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sc${sccond32} ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SCCND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-An-relative-Unprefixed-HI", "sc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sc${sccond32} ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SCCND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-24-An-relative-Unprefixed-HI", "sc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sc${sccond32} ${Dsp-16-u8}[sb] */ { M32C_INSN_SCCND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-SB-relative-Unprefixed-HI", "sc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sc${sccond32} ${Dsp-16-u16}[sb] */ { M32C_INSN_SCCND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-SB-relative-Unprefixed-HI", "sc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sc${sccond32} ${Dsp-16-s8}[fb] */ { M32C_INSN_SCCND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-FB-relative-Unprefixed-HI", "sc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sc${sccond32} ${Dsp-16-s16}[fb] */ { M32C_INSN_SCCND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-FB-relative-Unprefixed-HI", "sc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sc${sccond32} ${Dsp-16-u16} */ { M32C_INSN_SCCND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sccnd-dst32-16-16-absolute-Unprefixed-HI", "sc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sc${sccond32} ${Dsp-16-u24} */ { M32C_INSN_SCCND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sccnd-dst32-16-24-absolute-Unprefixed-HI", "sc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.w #${Imm-12-s4n},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */ { M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sbjnz.w", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.w #${Imm-12-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */ { M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sbjnz.w", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.w #${Imm-12-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */ { M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sbjnz.w", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */ { M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sbjnz.w", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */ { M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sbjnz.w", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.w #${Imm-12-s4n},${Dsp-16-s16}[fb],${Lab-32-8} */ { M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sbjnz.w", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16},${Lab-32-8} */ { M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sbjnz.w", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.w #${Imm-12-s4n},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */ { M32C_INSN_SBJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sbjnz.w", 48, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.w #${Imm-12-s4n},${Dsp-16-u24},${Lab-40-8} */ { M32C_INSN_SBJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sbjnz.w", 48, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.w #${Imm-12-s4n},$Dst32RnUnprefixedHI,${Lab-16-8} */ { M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sbjnz.w", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.w #${Imm-12-s4n},$Dst32AnUnprefixedHI,${Lab-16-8} */ { M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "sbjnz.w", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.w #${Imm-12-s4n},[$Dst32AnUnprefixed],${Lab-16-8} */ { M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sbjnz.w", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.b #${Imm-12-s4n},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */ { M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sbjnz.b", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.b #${Imm-12-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */ { M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sbjnz.b", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.b #${Imm-12-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */ { M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sbjnz.b", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */ { M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sbjnz.b", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */ { M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sbjnz.b", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.b #${Imm-12-s4n},${Dsp-16-s16}[fb],${Lab-32-8} */ { M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sbjnz.b", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16},${Lab-32-8} */ { M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sbjnz.b", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.b #${Imm-12-s4n},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */ { M32C_INSN_SBJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sbjnz.b", 48, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.b #${Imm-12-s4n},${Dsp-16-u24},${Lab-40-8} */ { M32C_INSN_SBJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sbjnz.b", 48, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.b #${Imm-12-s4n},$Dst32RnUnprefixedQI,${Lab-16-8} */ { M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sbjnz.b", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.b #${Imm-12-s4n},$Dst32AnUnprefixedQI,${Lab-16-8} */ { M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "sbjnz.b", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.b #${Imm-12-s4n},[$Dst32AnUnprefixed],${Lab-16-8} */ { M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sbjnz.b", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbjnz.w #${Imm-8-s4n},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */ { M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_AN_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-An-relative-HI", "sbjnz.w", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbjnz.w #${Imm-8-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */ { M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_SB_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-SB-relative-HI", "sbjnz.w", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbjnz.w #${Imm-8-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */ { M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_FB_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-FB-relative-HI", "sbjnz.w", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */ { M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_AN_RELATIVE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-An-relative-HI", "sbjnz.w", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */ { M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_SB_RELATIVE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-SB-relative-HI", "sbjnz.w", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16},${Lab-32-8} */ { M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_ABSOLUTE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-absolute-HI", "sbjnz.w", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbjnz.w #${Imm-8-s4n},$Dst16RnHI,${Lab-16-8} */ { M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_RN_DIRECT_HI, "sbjnz16.w-imm4-basic-dst16-Rn-direct-HI", "sbjnz.w", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbjnz.w #${Imm-8-s4n},$Dst16AnHI,${Lab-16-8} */ { M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_AN_DIRECT_HI, "sbjnz16.w-imm4-basic-dst16-An-direct-HI", "sbjnz.w", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbjnz.w #${Imm-8-s4n},[$Dst16An],${Lab-16-8} */ { M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_AN_INDIRECT_HI, "sbjnz16.w-imm4-basic-dst16-An-indirect-HI", "sbjnz.w", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbjnz.b #${Imm-8-s4n},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */ { M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_AN_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-An-relative-QI", "sbjnz.b", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbjnz.b #${Imm-8-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */ { M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_SB_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-SB-relative-QI", "sbjnz.b", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbjnz.b #${Imm-8-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */ { M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_FB_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-FB-relative-QI", "sbjnz.b", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */ { M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_AN_RELATIVE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-An-relative-QI", "sbjnz.b", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */ { M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_SB_RELATIVE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-SB-relative-QI", "sbjnz.b", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16},${Lab-32-8} */ { M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_ABSOLUTE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-absolute-QI", "sbjnz.b", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbjnz.b #${Imm-8-s4n},$Dst16RnQI,${Lab-16-8} */ { M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_RN_DIRECT_QI, "sbjnz16.b-imm4-basic-dst16-Rn-direct-QI", "sbjnz.b", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbjnz.b #${Imm-8-s4n},$Dst16AnQI,${Lab-16-8} */ { M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_AN_DIRECT_QI, "sbjnz16.b-imm4-basic-dst16-An-direct-QI", "sbjnz.b", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbjnz.b #${Imm-8-s4n},[$Dst16An],${Lab-16-8} */ { M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_AN_INDIRECT_QI, "sbjnz16.b-imm4-basic-dst16-An-indirect-QI", "sbjnz.b", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "sbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "sbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "sbb.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "sbb.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "sbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "sbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "sbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "sbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "sbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "sbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "sbb.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "sbb.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "sbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "sbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "sbb.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "sbb.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "sbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "sbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "sbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "sbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "sbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "sbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "sbb.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "sbb.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16},$Dst16RnHI */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16},$Dst16AnHI */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} $Src16RnHI,$Dst16RnHI */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "sbb.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} $Src16AnHI,$Dst16RnHI */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "sbb.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} [$Src16An],$Dst16RnHI */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "sbb.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} $Src16RnHI,$Dst16AnHI */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "sbb.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} $Src16AnHI,$Dst16AnHI */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "sbb.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} [$Src16An],$Dst16AnHI */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "sbb.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} $Src16RnHI,[$Dst16An] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "sbb.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} $Src16AnHI,[$Dst16An] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "sbb.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} [$Src16An],[$Dst16An] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "sbb.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} $Src16RnHI,${Dsp-16-u16} */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} $Src16AnHI,${Dsp-16-u16} */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16},$Dst16RnQI */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16},$Dst16AnQI */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} $Src16RnQI,$Dst16RnQI */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "sbb.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} $Src16AnQI,$Dst16RnQI */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "sbb.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} [$Src16An],$Dst16RnQI */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "sbb.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} $Src16RnQI,$Dst16AnQI */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "sbb.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} $Src16AnQI,$Dst16AnQI */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "sbb.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} [$Src16An],$Dst16AnQI */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "sbb.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} $Src16RnQI,[$Dst16An] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "sbb.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} $Src16AnQI,[$Dst16An] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "sbb.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} [$Src16An],[$Dst16An] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "sbb.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} $Src16RnQI,${Dsp-16-u16} */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} $Src16AnQI,${Dsp-16-u16} */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ { M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ { M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ { M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ { M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ { M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ { M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */ { M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */ { M32C_INSN_SBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ { M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ { M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ { M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ { M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ { M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ { M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */ { M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_SBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */ { M32C_INSN_SBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sbb.w${X} #${Imm-16-HI},$Dst16RnHI */ { M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "sbb16.w-imm-G-basic-dst16-Rn-direct-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} #${Imm-16-HI},$Dst16AnHI */ { M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "sbb16.w-imm-G-basic-dst16-An-direct-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} #${Imm-16-HI},[$Dst16An] */ { M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "sbb16.w-imm-G-basic-dst16-An-indirect-HI", "sbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "sbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-absolute-HI", "sbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} #${Imm-16-QI},$Dst16RnQI */ { M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "sbb16.b-imm-G-basic-dst16-Rn-direct-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} #${Imm-16-QI},$Dst16AnQI */ { M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "sbb16.b-imm-G-basic-dst16-An-direct-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} #${Imm-16-QI},[$Dst16An] */ { M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "sbb16.b-imm-G-basic-dst16-An-indirect-QI", "sbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "sbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-absolute-QI", "sbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.w r1h,$Dst32RnUnprefixedHI */ { M32C_INSN_ROT32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-Rn-direct-Unprefixed-HI", "rot.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.w r1h,$Dst32AnUnprefixedHI */ { M32C_INSN_ROT32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-An-direct-Unprefixed-HI", "rot.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.w r1h,[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-An-indirect-Unprefixed-HI", "rot.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "rot.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "rot.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "rot.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.w r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_ROT32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "rot.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.w r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_ROT32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "rot.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.w r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_ROT32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "rot.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.w r1h,${Dsp-16-s16}[fb] */ { M32C_INSN_ROT32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "rot.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.w r1h,${Dsp-16-u16} */ { M32C_INSN_ROT32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "rot.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.w r1h,${Dsp-16-u24} */ { M32C_INSN_ROT32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "rot.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.b r1h,$Dst32RnUnprefixedQI */ { M32C_INSN_ROT32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-Rn-direct-Unprefixed-QI", "rot.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.b r1h,$Dst32AnUnprefixedQI */ { M32C_INSN_ROT32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-An-direct-Unprefixed-QI", "rot.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.b r1h,[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-An-indirect-Unprefixed-QI", "rot.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "rot.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "rot.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "rot.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.b r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_ROT32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "rot.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.b r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_ROT32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "rot.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.b r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_ROT32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "rot.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.b r1h,${Dsp-16-s16}[fb] */ { M32C_INSN_ROT32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "rot.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.b r1h,${Dsp-16-u16} */ { M32C_INSN_ROT32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "rot.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.b r1h,${Dsp-16-u24} */ { M32C_INSN_ROT32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "rot.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.w r1h,$Dst16RnHI */ { M32C_INSN_ROT16_W_DST_DST16_RN_DIRECT_HI, "rot16.w-dst-dst16-Rn-direct-HI", "rot.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.w r1h,$Dst16AnHI */ { M32C_INSN_ROT16_W_DST_DST16_AN_DIRECT_HI, "rot16.w-dst-dst16-An-direct-HI", "rot.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.w r1h,[$Dst16An] */ { M32C_INSN_ROT16_W_DST_DST16_AN_INDIRECT_HI, "rot16.w-dst-dst16-An-indirect-HI", "rot.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.w r1h,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ROT16_W_DST_DST16_16_8_AN_RELATIVE_HI, "rot16.w-dst-dst16-16-8-An-relative-HI", "rot.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.w r1h,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ROT16_W_DST_DST16_16_16_AN_RELATIVE_HI, "rot16.w-dst-dst16-16-16-An-relative-HI", "rot.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.w r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_ROT16_W_DST_DST16_16_8_SB_RELATIVE_HI, "rot16.w-dst-dst16-16-8-SB-relative-HI", "rot.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.w r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_ROT16_W_DST_DST16_16_16_SB_RELATIVE_HI, "rot16.w-dst-dst16-16-16-SB-relative-HI", "rot.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.w r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_ROT16_W_DST_DST16_16_8_FB_RELATIVE_HI, "rot16.w-dst-dst16-16-8-FB-relative-HI", "rot.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.w r1h,${Dsp-16-u16} */ { M32C_INSN_ROT16_W_DST_DST16_16_16_ABSOLUTE_HI, "rot16.w-dst-dst16-16-16-absolute-HI", "rot.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.b r1h,$Dst16RnQI */ { M32C_INSN_ROT16_B_DST_DST16_RN_DIRECT_QI, "rot16.b-dst-dst16-Rn-direct-QI", "rot.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.b r1h,$Dst16AnQI */ { M32C_INSN_ROT16_B_DST_DST16_AN_DIRECT_QI, "rot16.b-dst-dst16-An-direct-QI", "rot.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.b r1h,[$Dst16An] */ { M32C_INSN_ROT16_B_DST_DST16_AN_INDIRECT_QI, "rot16.b-dst-dst16-An-indirect-QI", "rot.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.b r1h,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ROT16_B_DST_DST16_16_8_AN_RELATIVE_QI, "rot16.b-dst-dst16-16-8-An-relative-QI", "rot.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.b r1h,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ROT16_B_DST_DST16_16_16_AN_RELATIVE_QI, "rot16.b-dst-dst16-16-16-An-relative-QI", "rot.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.b r1h,${Dsp-16-u8}[sb] */ { M32C_INSN_ROT16_B_DST_DST16_16_8_SB_RELATIVE_QI, "rot16.b-dst-dst16-16-8-SB-relative-QI", "rot.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.b r1h,${Dsp-16-u16}[sb] */ { M32C_INSN_ROT16_B_DST_DST16_16_16_SB_RELATIVE_QI, "rot16.b-dst-dst16-16-16-SB-relative-QI", "rot.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.b r1h,${Dsp-16-s8}[fb] */ { M32C_INSN_ROT16_B_DST_DST16_16_8_FB_RELATIVE_QI, "rot16.b-dst-dst16-16-8-FB-relative-QI", "rot.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.b r1h,${Dsp-16-u16} */ { M32C_INSN_ROT16_B_DST_DST16_16_16_ABSOLUTE_QI, "rot16.b-dst-dst16-16-16-absolute-QI", "rot.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */ { M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rot.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */ { M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rot.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rot.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rot.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rot.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rot.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rot.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rot.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rot.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */ { M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rot.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */ { M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rot.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */ { M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rot.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */ { M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rot.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */ { M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rot.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rot.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rot.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rot.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rot.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rot.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rot.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rot.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */ { M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rot.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */ { M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rot.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */ { M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rot.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rot.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */ { M32C_INSN_ROT16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "rot16.w-imm4-Q-16-dst16-Rn-direct-HI", "rot.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */ { M32C_INSN_ROT16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "rot16.w-imm4-Q-16-dst16-An-direct-HI", "rot.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.w${Q} #${Imm-sh-8-s4},[$Dst16An] */ { M32C_INSN_ROT16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "rot16.w-imm4-Q-16-dst16-An-indirect-HI", "rot.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "rot.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "rot.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "rot.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "rot.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "rot.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */ { M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "rot16.w-imm4-Q-16-dst16-16-16-absolute-HI", "rot.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */ { M32C_INSN_ROT16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "rot16.b-imm4-Q-16-dst16-Rn-direct-QI", "rot.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */ { M32C_INSN_ROT16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "rot16.b-imm4-Q-16-dst16-An-direct-QI", "rot.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.b${Q} #${Imm-sh-8-s4},[$Dst16An] */ { M32C_INSN_ROT16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "rot16.b-imm4-Q-16-dst16-An-indirect-QI", "rot.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "rot.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "rot.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "rot.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "rot.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "rot.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */ { M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "rot16.b-imm4-Q-16-dst16-16-16-absolute-QI", "rot.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rorc.w $Dst32RnUnprefixedHI */ { M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rorc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rorc.w $Dst32AnUnprefixedHI */ { M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rorc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rorc.w [$Dst32AnUnprefixed] */ { M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rorc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rorc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rorc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rorc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rorc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rorc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rorc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rorc.w ${Dsp-16-u8}[sb] */ { M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rorc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rorc.w ${Dsp-16-u16}[sb] */ { M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rorc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rorc.w ${Dsp-16-s8}[fb] */ { M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rorc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rorc.w ${Dsp-16-s16}[fb] */ { M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rorc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rorc.w ${Dsp-16-u16} */ { M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rorc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rorc.w ${Dsp-16-u24} */ { M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rorc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rorc.b $Dst32RnUnprefixedQI */ { M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rorc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rorc.b $Dst32AnUnprefixedQI */ { M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rorc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rorc.b [$Dst32AnUnprefixed] */ { M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rorc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rorc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rorc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rorc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rorc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rorc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rorc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rorc.b ${Dsp-16-u8}[sb] */ { M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rorc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rorc.b ${Dsp-16-u16}[sb] */ { M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rorc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rorc.b ${Dsp-16-s8}[fb] */ { M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rorc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rorc.b ${Dsp-16-s16}[fb] */ { M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rorc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rorc.b ${Dsp-16-u16} */ { M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rorc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rorc.b ${Dsp-16-u24} */ { M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rorc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rorc.w $Dst16RnHI */ { M32C_INSN_RORC16_W_16_DST16_RN_DIRECT_HI, "rorc16.w-16-dst16-Rn-direct-HI", "rorc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rorc.w $Dst16AnHI */ { M32C_INSN_RORC16_W_16_DST16_AN_DIRECT_HI, "rorc16.w-16-dst16-An-direct-HI", "rorc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rorc.w [$Dst16An] */ { M32C_INSN_RORC16_W_16_DST16_AN_INDIRECT_HI, "rorc16.w-16-dst16-An-indirect-HI", "rorc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rorc.w ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_RORC16_W_16_DST16_16_8_AN_RELATIVE_HI, "rorc16.w-16-dst16-16-8-An-relative-HI", "rorc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rorc.w ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_RORC16_W_16_DST16_16_16_AN_RELATIVE_HI, "rorc16.w-16-dst16-16-16-An-relative-HI", "rorc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rorc.w ${Dsp-16-u8}[sb] */ { M32C_INSN_RORC16_W_16_DST16_16_8_SB_RELATIVE_HI, "rorc16.w-16-dst16-16-8-SB-relative-HI", "rorc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rorc.w ${Dsp-16-u16}[sb] */ { M32C_INSN_RORC16_W_16_DST16_16_16_SB_RELATIVE_HI, "rorc16.w-16-dst16-16-16-SB-relative-HI", "rorc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rorc.w ${Dsp-16-s8}[fb] */ { M32C_INSN_RORC16_W_16_DST16_16_8_FB_RELATIVE_HI, "rorc16.w-16-dst16-16-8-FB-relative-HI", "rorc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rorc.w ${Dsp-16-u16} */ { M32C_INSN_RORC16_W_16_DST16_16_16_ABSOLUTE_HI, "rorc16.w-16-dst16-16-16-absolute-HI", "rorc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rorc.b $Dst16RnQI */ { M32C_INSN_RORC16_B_16_DST16_RN_DIRECT_QI, "rorc16.b-16-dst16-Rn-direct-QI", "rorc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rorc.b $Dst16AnQI */ { M32C_INSN_RORC16_B_16_DST16_AN_DIRECT_QI, "rorc16.b-16-dst16-An-direct-QI", "rorc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rorc.b [$Dst16An] */ { M32C_INSN_RORC16_B_16_DST16_AN_INDIRECT_QI, "rorc16.b-16-dst16-An-indirect-QI", "rorc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rorc.b ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_RORC16_B_16_DST16_16_8_AN_RELATIVE_QI, "rorc16.b-16-dst16-16-8-An-relative-QI", "rorc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rorc.b ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_RORC16_B_16_DST16_16_16_AN_RELATIVE_QI, "rorc16.b-16-dst16-16-16-An-relative-QI", "rorc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rorc.b ${Dsp-16-u8}[sb] */ { M32C_INSN_RORC16_B_16_DST16_16_8_SB_RELATIVE_QI, "rorc16.b-16-dst16-16-8-SB-relative-QI", "rorc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rorc.b ${Dsp-16-u16}[sb] */ { M32C_INSN_RORC16_B_16_DST16_16_16_SB_RELATIVE_QI, "rorc16.b-16-dst16-16-16-SB-relative-QI", "rorc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rorc.b ${Dsp-16-s8}[fb] */ { M32C_INSN_RORC16_B_16_DST16_16_8_FB_RELATIVE_QI, "rorc16.b-16-dst16-16-8-FB-relative-QI", "rorc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rorc.b ${Dsp-16-u16} */ { M32C_INSN_RORC16_B_16_DST16_16_16_ABSOLUTE_QI, "rorc16.b-16-dst16-16-16-absolute-QI", "rorc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rolc.w $Dst32RnUnprefixedHI */ { M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rolc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rolc.w $Dst32AnUnprefixedHI */ { M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rolc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rolc.w [$Dst32AnUnprefixed] */ { M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rolc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rolc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rolc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rolc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rolc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rolc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rolc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rolc.w ${Dsp-16-u8}[sb] */ { M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rolc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rolc.w ${Dsp-16-u16}[sb] */ { M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rolc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rolc.w ${Dsp-16-s8}[fb] */ { M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rolc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rolc.w ${Dsp-16-s16}[fb] */ { M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rolc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rolc.w ${Dsp-16-u16} */ { M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rolc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rolc.w ${Dsp-16-u24} */ { M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rolc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rolc.b $Dst32RnUnprefixedQI */ { M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rolc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rolc.b $Dst32AnUnprefixedQI */ { M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rolc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rolc.b [$Dst32AnUnprefixed] */ { M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rolc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rolc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rolc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rolc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rolc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rolc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rolc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rolc.b ${Dsp-16-u8}[sb] */ { M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rolc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rolc.b ${Dsp-16-u16}[sb] */ { M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rolc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rolc.b ${Dsp-16-s8}[fb] */ { M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rolc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rolc.b ${Dsp-16-s16}[fb] */ { M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rolc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rolc.b ${Dsp-16-u16} */ { M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rolc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rolc.b ${Dsp-16-u24} */ { M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rolc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rolc.w $Dst16RnHI */ { M32C_INSN_ROLC16_W_16_DST16_RN_DIRECT_HI, "rolc16.w-16-dst16-Rn-direct-HI", "rolc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rolc.w $Dst16AnHI */ { M32C_INSN_ROLC16_W_16_DST16_AN_DIRECT_HI, "rolc16.w-16-dst16-An-direct-HI", "rolc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rolc.w [$Dst16An] */ { M32C_INSN_ROLC16_W_16_DST16_AN_INDIRECT_HI, "rolc16.w-16-dst16-An-indirect-HI", "rolc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rolc.w ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ROLC16_W_16_DST16_16_8_AN_RELATIVE_HI, "rolc16.w-16-dst16-16-8-An-relative-HI", "rolc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rolc.w ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ROLC16_W_16_DST16_16_16_AN_RELATIVE_HI, "rolc16.w-16-dst16-16-16-An-relative-HI", "rolc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rolc.w ${Dsp-16-u8}[sb] */ { M32C_INSN_ROLC16_W_16_DST16_16_8_SB_RELATIVE_HI, "rolc16.w-16-dst16-16-8-SB-relative-HI", "rolc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rolc.w ${Dsp-16-u16}[sb] */ { M32C_INSN_ROLC16_W_16_DST16_16_16_SB_RELATIVE_HI, "rolc16.w-16-dst16-16-16-SB-relative-HI", "rolc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rolc.w ${Dsp-16-s8}[fb] */ { M32C_INSN_ROLC16_W_16_DST16_16_8_FB_RELATIVE_HI, "rolc16.w-16-dst16-16-8-FB-relative-HI", "rolc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rolc.w ${Dsp-16-u16} */ { M32C_INSN_ROLC16_W_16_DST16_16_16_ABSOLUTE_HI, "rolc16.w-16-dst16-16-16-absolute-HI", "rolc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rolc.b $Dst16RnQI */ { M32C_INSN_ROLC16_B_16_DST16_RN_DIRECT_QI, "rolc16.b-16-dst16-Rn-direct-QI", "rolc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rolc.b $Dst16AnQI */ { M32C_INSN_ROLC16_B_16_DST16_AN_DIRECT_QI, "rolc16.b-16-dst16-An-direct-QI", "rolc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rolc.b [$Dst16An] */ { M32C_INSN_ROLC16_B_16_DST16_AN_INDIRECT_QI, "rolc16.b-16-dst16-An-indirect-QI", "rolc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rolc.b ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ROLC16_B_16_DST16_16_8_AN_RELATIVE_QI, "rolc16.b-16-dst16-16-8-An-relative-QI", "rolc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rolc.b ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ROLC16_B_16_DST16_16_16_AN_RELATIVE_QI, "rolc16.b-16-dst16-16-16-An-relative-QI", "rolc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rolc.b ${Dsp-16-u8}[sb] */ { M32C_INSN_ROLC16_B_16_DST16_16_8_SB_RELATIVE_QI, "rolc16.b-16-dst16-16-8-SB-relative-QI", "rolc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rolc.b ${Dsp-16-u16}[sb] */ { M32C_INSN_ROLC16_B_16_DST16_16_16_SB_RELATIVE_QI, "rolc16.b-16-dst16-16-16-SB-relative-QI", "rolc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rolc.b ${Dsp-16-s8}[fb] */ { M32C_INSN_ROLC16_B_16_DST16_16_8_FB_RELATIVE_QI, "rolc16.b-16-dst16-16-8-FB-relative-QI", "rolc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rolc.b ${Dsp-16-u16} */ { M32C_INSN_ROLC16_B_16_DST16_16_16_ABSOLUTE_QI, "rolc16.b-16-dst16-16-16-absolute-QI", "rolc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pusha [$Dst32AnUnprefixed] */ { M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-An-indirect-Unprefixed-Mova-SI", "pusha", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pusha ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-An-relative-Unprefixed-Mova-SI", "pusha", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pusha ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-An-relative-Unprefixed-Mova-SI", "pusha", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pusha ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-24-An-relative-Unprefixed-Mova-SI", "pusha", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pusha ${Dsp-16-u8}[sb] */ { M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "pusha", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pusha ${Dsp-16-u16}[sb] */ { M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "pusha", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pusha ${Dsp-16-s8}[fb] */ { M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "pusha", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pusha ${Dsp-16-s16}[fb] */ { M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "pusha", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pusha ${Dsp-16-u16} */ { M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-absolute-Unprefixed-Mova-SI", "pusha", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pusha ${Dsp-16-u24} */ { M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-24-absolute-Unprefixed-Mova-SI", "pusha", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pusha [$Dst16An] */ { M32C_INSN_PUSHA16_16_MOVA_DST16_AN_INDIRECT_MOVA_HI, "pusha16-16-Mova-dst16-An-indirect-Mova-HI", "pusha", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pusha ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_AN_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-An-relative-Mova-HI", "pusha", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pusha ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_AN_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-An-relative-Mova-HI", "pusha", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pusha ${Dsp-16-u8}[sb] */ { M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_SB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-SB-relative-Mova-HI", "pusha", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pusha ${Dsp-16-u16}[sb] */ { M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_SB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-SB-relative-Mova-HI", "pusha", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pusha ${Dsp-16-s8}[fb] */ { M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_FB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-FB-relative-Mova-HI", "pusha", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pusha ${Dsp-16-u16} */ { M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_ABSOLUTE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-absolute-Mova-HI", "pusha", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* push.l $Dst32RnUnprefixedSI */ { M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "push.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.l $Dst32AnUnprefixedSI */ { M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "push.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.l [$Dst32AnUnprefixed] */ { M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "push.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.l ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "push.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.l ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "push.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.l ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "push.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.l ${Dsp-16-u8}[sb] */ { M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "push.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.l ${Dsp-16-u16}[sb] */ { M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "push.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.l ${Dsp-16-s8}[fb] */ { M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "push.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.l ${Dsp-16-s16}[fb] */ { M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "push.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.l ${Dsp-16-u16} */ { M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "push.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.l ${Dsp-16-u24} */ { M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "push.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.w${S} ${An16-push-S} */ { M32C_INSN_PUSH16_B_S_AN_AN16_PUSH_S_DERIVED, "push16.b-s-an-An16-push-S-derived", "push.w", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* push.b${S} ${Rn16-push-S} */ { M32C_INSN_PUSH16_B_S_RN_RN16_PUSH_S_DERIVED, "push16.b-s-rn-Rn16-push-S-derived", "push.b", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* push.w $Dst32RnUnprefixedHI */ { M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "push.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.w $Dst32AnUnprefixedHI */ { M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "push.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.w [$Dst32AnUnprefixed] */ { M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "push.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "push.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "push.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "push.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.w ${Dsp-16-u8}[sb] */ { M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "push.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.w ${Dsp-16-u16}[sb] */ { M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "push.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.w ${Dsp-16-s8}[fb] */ { M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "push.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.w ${Dsp-16-s16}[fb] */ { M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "push.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.w ${Dsp-16-u16} */ { M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "push.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.w ${Dsp-16-u24} */ { M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "push.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.b $Dst32RnUnprefixedQI */ { M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "push.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.b $Dst32AnUnprefixedQI */ { M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "push.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.b [$Dst32AnUnprefixed] */ { M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "push.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "push.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "push.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "push.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.b ${Dsp-16-u8}[sb] */ { M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "push.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.b ${Dsp-16-u16}[sb] */ { M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "push.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.b ${Dsp-16-s8}[fb] */ { M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "push.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.b ${Dsp-16-s16}[fb] */ { M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "push.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.b ${Dsp-16-u16} */ { M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "push.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.b ${Dsp-16-u24} */ { M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "push.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.w${G} $Dst16RnHI */ { M32C_INSN_PUSH16_W_16_DST16_RN_DIRECT_HI, "push16.w-16-dst16-Rn-direct-HI", "push.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* push.w${G} $Dst16AnHI */ { M32C_INSN_PUSH16_W_16_DST16_AN_DIRECT_HI, "push16.w-16-dst16-An-direct-HI", "push.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* push.w${G} [$Dst16An] */ { M32C_INSN_PUSH16_W_16_DST16_AN_INDIRECT_HI, "push16.w-16-dst16-An-indirect-HI", "push.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* push.w${G} ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_PUSH16_W_16_DST16_16_8_AN_RELATIVE_HI, "push16.w-16-dst16-16-8-An-relative-HI", "push.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* push.w${G} ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_PUSH16_W_16_DST16_16_16_AN_RELATIVE_HI, "push16.w-16-dst16-16-16-An-relative-HI", "push.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* push.w${G} ${Dsp-16-u8}[sb] */ { M32C_INSN_PUSH16_W_16_DST16_16_8_SB_RELATIVE_HI, "push16.w-16-dst16-16-8-SB-relative-HI", "push.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* push.w${G} ${Dsp-16-u16}[sb] */ { M32C_INSN_PUSH16_W_16_DST16_16_16_SB_RELATIVE_HI, "push16.w-16-dst16-16-16-SB-relative-HI", "push.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* push.w${G} ${Dsp-16-s8}[fb] */ { M32C_INSN_PUSH16_W_16_DST16_16_8_FB_RELATIVE_HI, "push16.w-16-dst16-16-8-FB-relative-HI", "push.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* push.w${G} ${Dsp-16-u16} */ { M32C_INSN_PUSH16_W_16_DST16_16_16_ABSOLUTE_HI, "push16.w-16-dst16-16-16-absolute-HI", "push.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* push.b${G} $Dst16RnQI */ { M32C_INSN_PUSH16_B_16_DST16_RN_DIRECT_QI, "push16.b-16-dst16-Rn-direct-QI", "push.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* push.b${G} $Dst16AnQI */ { M32C_INSN_PUSH16_B_16_DST16_AN_DIRECT_QI, "push16.b-16-dst16-An-direct-QI", "push.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* push.b${G} [$Dst16An] */ { M32C_INSN_PUSH16_B_16_DST16_AN_INDIRECT_QI, "push16.b-16-dst16-An-indirect-QI", "push.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* push.b${G} ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_PUSH16_B_16_DST16_16_8_AN_RELATIVE_QI, "push16.b-16-dst16-16-8-An-relative-QI", "push.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* push.b${G} ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_PUSH16_B_16_DST16_16_16_AN_RELATIVE_QI, "push16.b-16-dst16-16-16-An-relative-QI", "push.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* push.b${G} ${Dsp-16-u8}[sb] */ { M32C_INSN_PUSH16_B_16_DST16_16_8_SB_RELATIVE_QI, "push16.b-16-dst16-16-8-SB-relative-QI", "push.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* push.b${G} ${Dsp-16-u16}[sb] */ { M32C_INSN_PUSH16_B_16_DST16_16_16_SB_RELATIVE_QI, "push16.b-16-dst16-16-16-SB-relative-QI", "push.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* push.b${G} ${Dsp-16-s8}[fb] */ { M32C_INSN_PUSH16_B_16_DST16_16_8_FB_RELATIVE_QI, "push16.b-16-dst16-16-8-FB-relative-QI", "push.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* push.b${G} ${Dsp-16-u16} */ { M32C_INSN_PUSH16_B_16_DST16_16_16_ABSOLUTE_QI, "push16.b-16-dst16-16-16-absolute-QI", "push.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pop.w${S} ${An16-push-S} */ { M32C_INSN_POP16_B_S_AN_AN16_PUSH_S_DERIVED, "pop16.b-s-an-An16-push-S-derived", "pop.w", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pop.b${S} ${Rn16-push-S} */ { M32C_INSN_POP16_B_S_RN_RN16_PUSH_S_DERIVED, "pop16.b-s-rn-Rn16-push-S-derived", "pop.b", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pop.w $Dst32RnUnprefixedHI */ { M32C_INSN_POP32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "pop.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pop.w $Dst32AnUnprefixedHI */ { M32C_INSN_POP32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "pop.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pop.w [$Dst32AnUnprefixed] */ { M32C_INSN_POP32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "pop.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pop.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "pop.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pop.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "pop.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pop.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "pop.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pop.w ${Dsp-16-u8}[sb] */ { M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "pop.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pop.w ${Dsp-16-u16}[sb] */ { M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "pop.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pop.w ${Dsp-16-s8}[fb] */ { M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "pop.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pop.w ${Dsp-16-s16}[fb] */ { M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "pop.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pop.w ${Dsp-16-u16} */ { M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "pop.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pop.w ${Dsp-16-u24} */ { M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "pop.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pop.b $Dst32RnUnprefixedQI */ { M32C_INSN_POP32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "pop.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pop.b $Dst32AnUnprefixedQI */ { M32C_INSN_POP32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "pop.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pop.b [$Dst32AnUnprefixed] */ { M32C_INSN_POP32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "pop.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pop.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "pop.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pop.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "pop.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pop.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "pop.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pop.b ${Dsp-16-u8}[sb] */ { M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "pop.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pop.b ${Dsp-16-u16}[sb] */ { M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "pop.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pop.b ${Dsp-16-s8}[fb] */ { M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "pop.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pop.b ${Dsp-16-s16}[fb] */ { M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "pop.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pop.b ${Dsp-16-u16} */ { M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "pop.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pop.b ${Dsp-16-u24} */ { M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "pop.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pop.w $Dst16RnHI */ { M32C_INSN_POP16_W_16_DST16_RN_DIRECT_HI, "pop16.w-16-dst16-Rn-direct-HI", "pop.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pop.w $Dst16AnHI */ { M32C_INSN_POP16_W_16_DST16_AN_DIRECT_HI, "pop16.w-16-dst16-An-direct-HI", "pop.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pop.w [$Dst16An] */ { M32C_INSN_POP16_W_16_DST16_AN_INDIRECT_HI, "pop16.w-16-dst16-An-indirect-HI", "pop.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pop.w ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_POP16_W_16_DST16_16_8_AN_RELATIVE_HI, "pop16.w-16-dst16-16-8-An-relative-HI", "pop.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pop.w ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_POP16_W_16_DST16_16_16_AN_RELATIVE_HI, "pop16.w-16-dst16-16-16-An-relative-HI", "pop.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pop.w ${Dsp-16-u8}[sb] */ { M32C_INSN_POP16_W_16_DST16_16_8_SB_RELATIVE_HI, "pop16.w-16-dst16-16-8-SB-relative-HI", "pop.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pop.w ${Dsp-16-u16}[sb] */ { M32C_INSN_POP16_W_16_DST16_16_16_SB_RELATIVE_HI, "pop16.w-16-dst16-16-16-SB-relative-HI", "pop.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pop.w ${Dsp-16-s8}[fb] */ { M32C_INSN_POP16_W_16_DST16_16_8_FB_RELATIVE_HI, "pop16.w-16-dst16-16-8-FB-relative-HI", "pop.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pop.w ${Dsp-16-u16} */ { M32C_INSN_POP16_W_16_DST16_16_16_ABSOLUTE_HI, "pop16.w-16-dst16-16-16-absolute-HI", "pop.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pop.b $Dst16RnQI */ { M32C_INSN_POP16_B_16_DST16_RN_DIRECT_QI, "pop16.b-16-dst16-Rn-direct-QI", "pop.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pop.b $Dst16AnQI */ { M32C_INSN_POP16_B_16_DST16_AN_DIRECT_QI, "pop16.b-16-dst16-An-direct-QI", "pop.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pop.b [$Dst16An] */ { M32C_INSN_POP16_B_16_DST16_AN_INDIRECT_QI, "pop16.b-16-dst16-An-indirect-QI", "pop.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pop.b ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_POP16_B_16_DST16_16_8_AN_RELATIVE_QI, "pop16.b-16-dst16-16-8-An-relative-QI", "pop.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pop.b ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_POP16_B_16_DST16_16_16_AN_RELATIVE_QI, "pop16.b-16-dst16-16-16-An-relative-QI", "pop.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pop.b ${Dsp-16-u8}[sb] */ { M32C_INSN_POP16_B_16_DST16_16_8_SB_RELATIVE_QI, "pop16.b-16-dst16-16-8-SB-relative-QI", "pop.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pop.b ${Dsp-16-u16}[sb] */ { M32C_INSN_POP16_B_16_DST16_16_16_SB_RELATIVE_QI, "pop16.b-16-dst16-16-16-SB-relative-QI", "pop.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pop.b ${Dsp-16-s8}[fb] */ { M32C_INSN_POP16_B_16_DST16_16_8_FB_RELATIVE_QI, "pop16.b-16-dst16-16-8-FB-relative-QI", "pop.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pop.b ${Dsp-16-u16} */ { M32C_INSN_POP16_B_16_DST16_16_16_ABSOLUTE_QI, "pop16.b-16-dst16-16-16-absolute-QI", "pop.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "or.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "or.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "or.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "or.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "or.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "or.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "or.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "or.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "or.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "or.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "or.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "or.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "or.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "or.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "or.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "or.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "or.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "or.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "or.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "or.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "or.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "or.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "or.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "or.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16},$Dst16RnHI */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16},$Dst16AnHI */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} $Src16RnHI,$Dst16RnHI */ { M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "or.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} $Src16AnHI,$Dst16RnHI */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "or.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} [$Src16An],$Dst16RnHI */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "or.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} $Src16RnHI,$Dst16AnHI */ { M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "or.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} $Src16AnHI,$Dst16AnHI */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "or.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} [$Src16An],$Dst16AnHI */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "or.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} $Src16RnHI,[$Dst16An] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "or.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} $Src16AnHI,[$Dst16An] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "or.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} [$Src16An],[$Dst16An] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "or.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} $Src16RnHI,${Dsp-16-u16} */ { M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} $Src16AnHI,${Dsp-16-u16} */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16},$Dst16RnQI */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16},$Dst16AnQI */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} $Src16RnQI,$Dst16RnQI */ { M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "or.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} $Src16AnQI,$Dst16RnQI */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "or.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} [$Src16An],$Dst16RnQI */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "or.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} $Src16RnQI,$Dst16AnQI */ { M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "or.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} $Src16AnQI,$Dst16AnQI */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "or.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} [$Src16An],$Dst16AnQI */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "or.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} $Src16RnQI,[$Dst16An] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "or.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} $Src16AnQI,[$Dst16An] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "or.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} [$Src16An],[$Dst16An] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "or.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} $Src16RnQI,${Dsp-16-u16} */ { M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} $Src16AnQI,${Dsp-16-u16} */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ { M32C_INSN_OR32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "or32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ { M32C_INSN_OR32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "or32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${S} #${Imm-24-HI},${Dsp-8-u16} */ { M32C_INSN_OR32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "or32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${S} #${Imm-8-HI},r0 */ { M32C_INSN_OR32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "or32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "or.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ { M32C_INSN_OR32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "or32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ { M32C_INSN_OR32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "or32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${S} #${Imm-24-QI},${Dsp-8-u16} */ { M32C_INSN_OR32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "or32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${S} #${Imm-8-QI},r0l */ { M32C_INSN_OR32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "or32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "or.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${S} #${Imm-8-QI},r0l */ { M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "or16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "or.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${S} #${Imm-8-QI},r0h */ { M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "or16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "or.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${S} #${Imm-8-QI},${Dsp-16-u16} */ { M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ { M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ { M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ { M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} #${Imm-40-HI},${Dsp-16-u24} */ { M32C_INSN_OR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "or.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ { M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ { M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_OR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.b${G} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_OR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "or.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* or.w${G} #${Imm-16-HI},$Dst16RnHI */ { M32C_INSN_OR16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "or16.w-imm-G-basic-dst16-Rn-direct-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} #${Imm-16-HI},$Dst16AnHI */ { M32C_INSN_OR16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "or16.w-imm-G-basic-dst16-An-direct-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} #${Imm-16-HI},[$Dst16An] */ { M32C_INSN_OR16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "or16.w-imm-G-basic-dst16-An-indirect-HI", "or.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "or.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "or16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "or16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "or16.w-imm-G-16-16-dst16-16-16-absolute-HI", "or.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} #${Imm-16-QI},$Dst16RnQI */ { M32C_INSN_OR16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "or16.b-imm-G-basic-dst16-Rn-direct-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} #${Imm-16-QI},$Dst16AnQI */ { M32C_INSN_OR16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "or16.b-imm-G-basic-dst16-An-direct-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} #${Imm-16-QI},[$Dst16An] */ { M32C_INSN_OR16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "or16.b-imm-G-basic-dst16-An-indirect-QI", "or.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "or.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "or16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "or16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "or16.b-imm-G-16-16-dst16-16-16-absolute-QI", "or.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* not.b:s r0l */ { @@ -19288,43382 +19288,43382 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] = /* not.w${G} $Dst32RnUnprefixedHI */ { M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "not.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* not.w${G} $Dst32AnUnprefixedHI */ { M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "not.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* not.w${G} [$Dst32AnUnprefixed] */ { M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "not.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* not.w${G} ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "not.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* not.w${G} ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "not.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* not.w${G} ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "not.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* not.w${G} ${Dsp-16-u8}[sb] */ { M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "not.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* not.w${G} ${Dsp-16-u16}[sb] */ { M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "not.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* not.w${G} ${Dsp-16-s8}[fb] */ { M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "not.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* not.w${G} ${Dsp-16-s16}[fb] */ { M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "not.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* not.w${G} ${Dsp-16-u16} */ { M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "not.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* not.w${G} ${Dsp-16-u24} */ { M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "not.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* not.b${G} $Dst32RnUnprefixedQI */ { M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "not.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* not.b${G} $Dst32AnUnprefixedQI */ { M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "not.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* not.b${G} [$Dst32AnUnprefixed] */ { M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "not.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* not.b${G} ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "not.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* not.b${G} ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "not.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* not.b${G} ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "not.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* not.b${G} ${Dsp-16-u8}[sb] */ { M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "not.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* not.b${G} ${Dsp-16-u16}[sb] */ { M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "not.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* not.b${G} ${Dsp-16-s8}[fb] */ { M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "not.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* not.b${G} ${Dsp-16-s16}[fb] */ { M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "not.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* not.b${G} ${Dsp-16-u16} */ { M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "not.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* not.b${G} ${Dsp-16-u24} */ { M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "not.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* not.w${G} $Dst16RnHI */ { M32C_INSN_NOT16_W_16_DST16_RN_DIRECT_HI, "not16.w-16-dst16-Rn-direct-HI", "not.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* not.w${G} $Dst16AnHI */ { M32C_INSN_NOT16_W_16_DST16_AN_DIRECT_HI, "not16.w-16-dst16-An-direct-HI", "not.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* not.w${G} [$Dst16An] */ { M32C_INSN_NOT16_W_16_DST16_AN_INDIRECT_HI, "not16.w-16-dst16-An-indirect-HI", "not.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* not.w${G} ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_NOT16_W_16_DST16_16_8_AN_RELATIVE_HI, "not16.w-16-dst16-16-8-An-relative-HI", "not.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* not.w${G} ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_NOT16_W_16_DST16_16_16_AN_RELATIVE_HI, "not16.w-16-dst16-16-16-An-relative-HI", "not.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* not.w${G} ${Dsp-16-u8}[sb] */ { M32C_INSN_NOT16_W_16_DST16_16_8_SB_RELATIVE_HI, "not16.w-16-dst16-16-8-SB-relative-HI", "not.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* not.w${G} ${Dsp-16-u16}[sb] */ { M32C_INSN_NOT16_W_16_DST16_16_16_SB_RELATIVE_HI, "not16.w-16-dst16-16-16-SB-relative-HI", "not.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* not.w${G} ${Dsp-16-s8}[fb] */ { M32C_INSN_NOT16_W_16_DST16_16_8_FB_RELATIVE_HI, "not16.w-16-dst16-16-8-FB-relative-HI", "not.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* not.w${G} ${Dsp-16-u16} */ { M32C_INSN_NOT16_W_16_DST16_16_16_ABSOLUTE_HI, "not16.w-16-dst16-16-16-absolute-HI", "not.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* not.b${G} $Dst16RnQI */ { M32C_INSN_NOT16_B_16_DST16_RN_DIRECT_QI, "not16.b-16-dst16-Rn-direct-QI", "not.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* not.b${G} $Dst16AnQI */ { M32C_INSN_NOT16_B_16_DST16_AN_DIRECT_QI, "not16.b-16-dst16-An-direct-QI", "not.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* not.b${G} [$Dst16An] */ { M32C_INSN_NOT16_B_16_DST16_AN_INDIRECT_QI, "not16.b-16-dst16-An-indirect-QI", "not.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* not.b${G} ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_NOT16_B_16_DST16_16_8_AN_RELATIVE_QI, "not16.b-16-dst16-16-8-An-relative-QI", "not.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* not.b${G} ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_NOT16_B_16_DST16_16_16_AN_RELATIVE_QI, "not16.b-16-dst16-16-16-An-relative-QI", "not.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* not.b${G} ${Dsp-16-u8}[sb] */ { M32C_INSN_NOT16_B_16_DST16_16_8_SB_RELATIVE_QI, "not16.b-16-dst16-16-8-SB-relative-QI", "not.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* not.b${G} ${Dsp-16-u16}[sb] */ { M32C_INSN_NOT16_B_16_DST16_16_16_SB_RELATIVE_QI, "not16.b-16-dst16-16-16-SB-relative-QI", "not.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* not.b${G} ${Dsp-16-s8}[fb] */ { M32C_INSN_NOT16_B_16_DST16_16_8_FB_RELATIVE_QI, "not16.b-16-dst16-16-8-FB-relative-QI", "not.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* not.b${G} ${Dsp-16-u16} */ { M32C_INSN_NOT16_B_16_DST16_16_16_ABSOLUTE_QI, "not16.b-16-dst16-16-16-absolute-QI", "not.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* neg.w $Dst32RnUnprefixedHI */ { M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "neg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* neg.w $Dst32AnUnprefixedHI */ { M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "neg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* neg.w [$Dst32AnUnprefixed] */ { M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "neg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* neg.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "neg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* neg.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "neg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* neg.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "neg.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* neg.w ${Dsp-16-u8}[sb] */ { M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "neg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* neg.w ${Dsp-16-u16}[sb] */ { M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "neg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* neg.w ${Dsp-16-s8}[fb] */ { M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "neg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* neg.w ${Dsp-16-s16}[fb] */ { M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "neg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* neg.w ${Dsp-16-u16} */ { M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "neg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* neg.w ${Dsp-16-u24} */ { M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "neg.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* neg.b $Dst32RnUnprefixedQI */ { M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "neg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* neg.b $Dst32AnUnprefixedQI */ { M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "neg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* neg.b [$Dst32AnUnprefixed] */ { M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "neg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* neg.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "neg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* neg.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "neg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* neg.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "neg.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* neg.b ${Dsp-16-u8}[sb] */ { M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "neg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* neg.b ${Dsp-16-u16}[sb] */ { M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "neg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* neg.b ${Dsp-16-s8}[fb] */ { M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "neg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* neg.b ${Dsp-16-s16}[fb] */ { M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "neg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* neg.b ${Dsp-16-u16} */ { M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "neg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* neg.b ${Dsp-16-u24} */ { M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "neg.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* neg.w $Dst16RnHI */ { M32C_INSN_NEG16_W_16_DST16_RN_DIRECT_HI, "neg16.w-16-dst16-Rn-direct-HI", "neg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* neg.w $Dst16AnHI */ { M32C_INSN_NEG16_W_16_DST16_AN_DIRECT_HI, "neg16.w-16-dst16-An-direct-HI", "neg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* neg.w [$Dst16An] */ { M32C_INSN_NEG16_W_16_DST16_AN_INDIRECT_HI, "neg16.w-16-dst16-An-indirect-HI", "neg.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* neg.w ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_NEG16_W_16_DST16_16_8_AN_RELATIVE_HI, "neg16.w-16-dst16-16-8-An-relative-HI", "neg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* neg.w ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_NEG16_W_16_DST16_16_16_AN_RELATIVE_HI, "neg16.w-16-dst16-16-16-An-relative-HI", "neg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* neg.w ${Dsp-16-u8}[sb] */ { M32C_INSN_NEG16_W_16_DST16_16_8_SB_RELATIVE_HI, "neg16.w-16-dst16-16-8-SB-relative-HI", "neg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* neg.w ${Dsp-16-u16}[sb] */ { M32C_INSN_NEG16_W_16_DST16_16_16_SB_RELATIVE_HI, "neg16.w-16-dst16-16-16-SB-relative-HI", "neg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* neg.w ${Dsp-16-s8}[fb] */ { M32C_INSN_NEG16_W_16_DST16_16_8_FB_RELATIVE_HI, "neg16.w-16-dst16-16-8-FB-relative-HI", "neg.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* neg.w ${Dsp-16-u16} */ { M32C_INSN_NEG16_W_16_DST16_16_16_ABSOLUTE_HI, "neg16.w-16-dst16-16-16-absolute-HI", "neg.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* neg.b $Dst16RnQI */ { M32C_INSN_NEG16_B_16_DST16_RN_DIRECT_QI, "neg16.b-16-dst16-Rn-direct-QI", "neg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* neg.b $Dst16AnQI */ { M32C_INSN_NEG16_B_16_DST16_AN_DIRECT_QI, "neg16.b-16-dst16-An-direct-QI", "neg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* neg.b [$Dst16An] */ { M32C_INSN_NEG16_B_16_DST16_AN_INDIRECT_QI, "neg16.b-16-dst16-An-indirect-QI", "neg.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* neg.b ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_NEG16_B_16_DST16_16_8_AN_RELATIVE_QI, "neg16.b-16-dst16-16-8-An-relative-QI", "neg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* neg.b ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_NEG16_B_16_DST16_16_16_AN_RELATIVE_QI, "neg16.b-16-dst16-16-16-An-relative-QI", "neg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* neg.b ${Dsp-16-u8}[sb] */ { M32C_INSN_NEG16_B_16_DST16_16_8_SB_RELATIVE_QI, "neg16.b-16-dst16-16-8-SB-relative-QI", "neg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* neg.b ${Dsp-16-u16}[sb] */ { M32C_INSN_NEG16_B_16_DST16_16_16_SB_RELATIVE_QI, "neg16.b-16-dst16-16-16-SB-relative-QI", "neg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* neg.b ${Dsp-16-s8}[fb] */ { M32C_INSN_NEG16_B_16_DST16_16_8_FB_RELATIVE_QI, "neg16.b-16-dst16-16-8-FB-relative-QI", "neg.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* neg.b ${Dsp-16-u16} */ { M32C_INSN_NEG16_B_16_DST16_16_16_ABSOLUTE_QI, "neg16.b-16-dst16-16-16-absolute-QI", "neg.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mulu.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mulu.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mulu.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mulu.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mulu.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mulu.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mulu.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mulu.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mulu.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mulu.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mulu.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mulu.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mulu.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mulu.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mulu.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mulu.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mulu.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mulu.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mulu.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mulu.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mulu.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mulu.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mulu.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mulu.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16},$Dst16RnHI */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16},$Dst16AnHI */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} $Src16RnHI,$Dst16RnHI */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mulu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} $Src16AnHI,$Dst16RnHI */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mulu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} [$Src16An],$Dst16RnHI */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mulu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} $Src16RnHI,$Dst16AnHI */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mulu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} $Src16AnHI,$Dst16AnHI */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mulu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} [$Src16An],$Dst16AnHI */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mulu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} $Src16RnHI,[$Dst16An] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mulu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} $Src16AnHI,[$Dst16An] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mulu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} [$Src16An],[$Dst16An] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mulu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} $Src16RnHI,${Dsp-16-u16} */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} $Src16AnHI,${Dsp-16-u16} */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16},$Dst16RnQI */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16},$Dst16AnQI */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} $Src16RnQI,$Dst16RnQI */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mulu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} $Src16AnQI,$Dst16RnQI */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mulu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} [$Src16An],$Dst16RnQI */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mulu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} $Src16RnQI,$Dst16AnQI */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mulu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} $Src16AnQI,$Dst16AnQI */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mulu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} [$Src16An],$Dst16AnQI */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mulu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} $Src16RnQI,[$Dst16An] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mulu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} $Src16AnQI,[$Dst16An] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mulu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} [$Src16An],[$Dst16An] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mulu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} $Src16RnQI,${Dsp-16-u16} */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} $Src16AnQI,${Dsp-16-u16} */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ { M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ { M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ { M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24} */ { M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ { M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ { M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulu.w${G} #${Imm-16-HI},$Dst16RnHI */ { M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mulu16.w-imm-G-basic-dst16-Rn-direct-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} #${Imm-16-HI},$Dst16AnHI */ { M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mulu16.w-imm-G-basic-dst16-An-direct-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} #${Imm-16-HI},[$Dst16An] */ { M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mulu16.w-imm-G-basic-dst16-An-indirect-HI", "mulu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mulu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mulu.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} #${Imm-16-QI},$Dst16RnQI */ { M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mulu16.b-imm-G-basic-dst16-Rn-direct-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} #${Imm-16-QI},$Dst16AnQI */ { M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mulu16.b-imm-G-basic-dst16-An-direct-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} #${Imm-16-QI},[$Dst16An] */ { M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mulu16.b-imm-G-basic-dst16-An-indirect-QI", "mulu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mulu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mulu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mulex $R3 */ { M32C_INSN_MULEX_DST32_R3_DIRECT_UNPREFIXED_HI, "mulex-dst32-R3-direct-Unprefixed-HI", "mulex", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulex $Dst32AnUnprefixedHI */ { M32C_INSN_MULEX_DST32_AN_DIRECT_UNPREFIXED_HI, "mulex-dst32-An-direct-Unprefixed-HI", "mulex", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulex [$Dst32AnUnprefixed] */ { M32C_INSN_MULEX_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulex-dst32-An-indirect-Unprefixed-HI", "mulex", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulex ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MULEX_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-An-relative-Unprefixed-HI", "mulex", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulex ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MULEX_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-An-relative-Unprefixed-HI", "mulex", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulex ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MULEX_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-24-An-relative-Unprefixed-HI", "mulex", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulex ${Dsp-16-u8}[sb] */ { M32C_INSN_MULEX_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-SB-relative-Unprefixed-HI", "mulex", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulex ${Dsp-16-u16}[sb] */ { M32C_INSN_MULEX_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-SB-relative-Unprefixed-HI", "mulex", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulex ${Dsp-16-s8}[fb] */ { M32C_INSN_MULEX_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-FB-relative-Unprefixed-HI", "mulex", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulex ${Dsp-16-s16}[fb] */ { M32C_INSN_MULEX_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-FB-relative-Unprefixed-HI", "mulex", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulex ${Dsp-16-u16} */ { M32C_INSN_MULEX_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulex-dst32-16-16-absolute-Unprefixed-HI", "mulex", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mulex ${Dsp-16-u24} */ { M32C_INSN_MULEX_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulex-dst32-16-24-absolute-Unprefixed-HI", "mulex", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mul.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mul.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mul.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mul.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mul.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mul.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mul.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mul.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mul.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mul.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mul.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mul.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mul.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mul.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mul.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mul.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mul.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mul.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mul.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mul.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mul.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mul.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mul.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mul.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16},$Dst16RnHI */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16},$Dst16AnHI */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} $Src16RnHI,$Dst16RnHI */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mul.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} $Src16AnHI,$Dst16RnHI */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mul.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} [$Src16An],$Dst16RnHI */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mul.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} $Src16RnHI,$Dst16AnHI */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mul.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} $Src16AnHI,$Dst16AnHI */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mul.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} [$Src16An],$Dst16AnHI */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mul.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} $Src16RnHI,[$Dst16An] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mul.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} $Src16AnHI,[$Dst16An] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mul.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} [$Src16An],[$Dst16An] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mul.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mul.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} $Src16RnHI,${Dsp-16-u16} */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} $Src16AnHI,${Dsp-16-u16} */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16},$Dst16RnQI */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16},$Dst16AnQI */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} $Src16RnQI,$Dst16RnQI */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mul.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} $Src16AnQI,$Dst16RnQI */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mul.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} [$Src16An],$Dst16RnQI */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mul.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} $Src16RnQI,$Dst16AnQI */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mul.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} $Src16AnQI,$Dst16AnQI */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mul.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} [$Src16An],$Dst16AnQI */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mul.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} $Src16RnQI,[$Dst16An] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mul.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} $Src16AnQI,[$Dst16An] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mul.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} [$Src16An],[$Dst16An] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mul.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} $Src16RnQI,${Dsp-16-u16} */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} $Src16AnQI,${Dsp-16-u16} */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ { M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ { M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ { M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} #${Imm-40-HI},${Dsp-16-u24} */ { M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ { M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ { M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.b${G} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mul.w${G} #${Imm-16-HI},$Dst16RnHI */ { M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mul16.w-imm-G-basic-dst16-Rn-direct-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} #${Imm-16-HI},$Dst16AnHI */ { M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mul16.w-imm-G-basic-dst16-An-direct-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} #${Imm-16-HI},[$Dst16An] */ { M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mul16.w-imm-G-basic-dst16-An-indirect-HI", "mul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mul.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mul16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mul16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mul16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mul.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} #${Imm-16-QI},$Dst16RnQI */ { M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mul16.b-imm-G-basic-dst16-Rn-direct-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} #${Imm-16-QI},$Dst16AnQI */ { M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mul16.b-imm-G-basic-dst16-An-direct-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} #${Imm-16-QI},[$Dst16An] */ { M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mul16.b-imm-G-basic-dst16-An-indirect-QI", "mul.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mul.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mul16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mul16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mul16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mul.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ { M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "movx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ { M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "movx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "movx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "movx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "movx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "movx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "movx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "movx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "movx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movx${X} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "movx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "movx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movx${X} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "movx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "movx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh $Dst32RnPrefixedQI,r0l */ { M32C_INSN_MOVHH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movhh", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh $Dst32AnPrefixedQI,r0l */ { M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-An-direct-Prefixed-QI", "movhh", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh [$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-An-indirect-Prefixed-QI", "movhh", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movhh", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movhh", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movhh", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh ${Dsp-24-u8}[sb],r0l */ { M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movhh", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh ${Dsp-24-u16}[sb],r0l */ { M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movhh", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh ${Dsp-24-s8}[fb],r0l */ { M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movhh", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh ${Dsp-24-s16}[fb],r0l */ { M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movhh", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh ${Dsp-24-u16},r0l */ { M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movhh", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh ${Dsp-24-u24},r0l */ { M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movhh", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhl $Dst32RnPrefixedQI,r0l */ { M32C_INSN_MOVHL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movhl", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhl $Dst32AnPrefixedQI,r0l */ { M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-An-direct-Prefixed-QI", "movhl", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhl [$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-An-indirect-Prefixed-QI", "movhl", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhl ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movhl", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhl ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movhl", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhl ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movhl", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhl ${Dsp-24-u8}[sb],r0l */ { M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movhl", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhl ${Dsp-24-u16}[sb],r0l */ { M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movhl", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhl ${Dsp-24-s8}[fb],r0l */ { M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movhl", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhl ${Dsp-24-s16}[fb],r0l */ { M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movhl", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhl ${Dsp-24-u16},r0l */ { M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movhl", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhl ${Dsp-24-u24},r0l */ { M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movhl", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movlh $Dst32RnPrefixedQI,r0l */ { M32C_INSN_MOVLH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movlh", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movlh $Dst32AnPrefixedQI,r0l */ { M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-An-direct-Prefixed-QI", "movlh", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movlh [$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-An-indirect-Prefixed-QI", "movlh", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movlh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movlh", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movlh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movlh", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movlh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movlh", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movlh ${Dsp-24-u8}[sb],r0l */ { M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movlh", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movlh ${Dsp-24-u16}[sb],r0l */ { M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movlh", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movlh ${Dsp-24-s8}[fb],r0l */ { M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movlh", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movlh ${Dsp-24-s16}[fb],r0l */ { M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movlh", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movlh ${Dsp-24-u16},r0l */ { M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movlh", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movlh ${Dsp-24-u24},r0l */ { M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movlh", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movll $Dst32RnPrefixedQI,r0l */ { M32C_INSN_MOVLL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movll", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movll $Dst32AnPrefixedQI,r0l */ { M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-An-direct-Prefixed-QI", "movll", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movll [$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-An-indirect-Prefixed-QI", "movll", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movll ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movll", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movll ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movll", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movll ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */ { M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movll", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movll ${Dsp-24-u8}[sb],r0l */ { M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movll", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movll ${Dsp-24-u16}[sb],r0l */ { M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movll", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movll ${Dsp-24-s8}[fb],r0l */ { M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movll", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movll ${Dsp-24-s16}[fb],r0l */ { M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movll", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movll ${Dsp-24-u16},r0l */ { M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movll", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movll ${Dsp-24-u24},r0l */ { M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movll32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movll", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh r0l,$Dst32RnPrefixedQI */ { M32C_INSN_MOVHH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movhh", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh r0l,$Dst32AnPrefixedQI */ { M32C_INSN_MOVHH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-An-direct-Prefixed-QI", "movhh", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh r0l,[$Dst32AnPrefixed] */ { M32C_INSN_MOVHH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movhh", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movhh", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movhh", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movhh", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh r0l,${Dsp-24-u8}[sb] */ { M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movhh", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh r0l,${Dsp-24-u16}[sb] */ { M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movhh", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh r0l,${Dsp-24-s8}[fb] */ { M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movhh", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh r0l,${Dsp-24-s16}[fb] */ { M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movhh", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh r0l,${Dsp-24-u16} */ { M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movhh", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh r0l,${Dsp-24-u24} */ { M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movhh", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhl r0l,$Dst32RnPrefixedQI */ { M32C_INSN_MOVHL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movhl", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhl r0l,$Dst32AnPrefixedQI */ { M32C_INSN_MOVHL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-An-direct-Prefixed-QI", "movhl", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhl r0l,[$Dst32AnPrefixed] */ { M32C_INSN_MOVHL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movhl", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhl r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movhl", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhl r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movhl", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhl r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movhl", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhl r0l,${Dsp-24-u8}[sb] */ { M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movhl", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhl r0l,${Dsp-24-u16}[sb] */ { M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movhl", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhl r0l,${Dsp-24-s8}[fb] */ { M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movhl", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhl r0l,${Dsp-24-s16}[fb] */ { M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movhl", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhl r0l,${Dsp-24-u16} */ { M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movhl", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhl r0l,${Dsp-24-u24} */ { M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movhl", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movlh r0l,$Dst32RnPrefixedQI */ { M32C_INSN_MOVLH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movlh", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movlh r0l,$Dst32AnPrefixedQI */ { M32C_INSN_MOVLH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-An-direct-Prefixed-QI", "movlh", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movlh r0l,[$Dst32AnPrefixed] */ { M32C_INSN_MOVLH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movlh", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movlh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movlh", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movlh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movlh", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movlh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movlh", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movlh r0l,${Dsp-24-u8}[sb] */ { M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movlh", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movlh r0l,${Dsp-24-u16}[sb] */ { M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movlh", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movlh r0l,${Dsp-24-s8}[fb] */ { M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movlh", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movlh r0l,${Dsp-24-s16}[fb] */ { M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movlh", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movlh r0l,${Dsp-24-u16} */ { M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movlh", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movlh r0l,${Dsp-24-u24} */ { M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movlh", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movll r0l,$Dst32RnPrefixedQI */ { M32C_INSN_MOVLL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movll", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movll r0l,$Dst32AnPrefixedQI */ { M32C_INSN_MOVLL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-An-direct-Prefixed-QI", "movll", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movll r0l,[$Dst32AnPrefixed] */ { M32C_INSN_MOVLL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movll", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movll r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movll", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movll r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movll", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movll r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movll", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movll r0l,${Dsp-24-u8}[sb] */ { M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movll", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movll r0l,${Dsp-24-u16}[sb] */ { M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movll", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movll r0l,${Dsp-24-s8}[fb] */ { M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movll", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movll r0l,${Dsp-24-s16}[fb] */ { M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movll", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movll r0l,${Dsp-24-u16} */ { M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movll", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movll r0l,${Dsp-24-u24} */ { M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movll", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* movhh $Dst16RnQI,r0l */ { M32C_INSN_MOVHH16_SRC_R0L_DST16_RN_DIRECT_QI, "movhh16.src-r0l-dst16-Rn-direct-QI", "movhh", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhh $Dst16AnQI,r0l */ { M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_DIRECT_QI, "movhh16.src-r0l-dst16-An-direct-QI", "movhh", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhh [$Dst16An],r0l */ { M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_INDIRECT_QI, "movhh16.src-r0l-dst16-An-indirect-QI", "movhh", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhh ${Dsp-16-u8}[$Dst16An],r0l */ { M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-An-relative-QI", "movhh", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhh ${Dsp-16-u16}[$Dst16An],r0l */ { M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movhh16.src-r0l-dst16-16-16-An-relative-QI", "movhh", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhh ${Dsp-16-u8}[sb],r0l */ { M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-SB-relative-QI", "movhh", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhh ${Dsp-16-u16}[sb],r0l */ { M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-16-SB-relative-QI", "movhh", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhh ${Dsp-16-s8}[fb],r0l */ { M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-FB-relative-QI", "movhh", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhh ${Dsp-16-u16},r0l */ { M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movhh16.src-r0l-dst16-16-16-absolute-QI", "movhh", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhl $Dst16RnQI,r0l */ { M32C_INSN_MOVHL16_SRC_R0L_DST16_RN_DIRECT_QI, "movhl16.src-r0l-dst16-Rn-direct-QI", "movhl", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhl $Dst16AnQI,r0l */ { M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_DIRECT_QI, "movhl16.src-r0l-dst16-An-direct-QI", "movhl", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhl [$Dst16An],r0l */ { M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_INDIRECT_QI, "movhl16.src-r0l-dst16-An-indirect-QI", "movhl", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhl ${Dsp-16-u8}[$Dst16An],r0l */ { M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-An-relative-QI", "movhl", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhl ${Dsp-16-u16}[$Dst16An],r0l */ { M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movhl16.src-r0l-dst16-16-16-An-relative-QI", "movhl", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhl ${Dsp-16-u8}[sb],r0l */ { M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-SB-relative-QI", "movhl", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhl ${Dsp-16-u16}[sb],r0l */ { M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-16-SB-relative-QI", "movhl", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhl ${Dsp-16-s8}[fb],r0l */ { M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-FB-relative-QI", "movhl", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhl ${Dsp-16-u16},r0l */ { M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movhl16.src-r0l-dst16-16-16-absolute-QI", "movhl", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movlh $Dst16RnQI,r0l */ { M32C_INSN_MOVLH16_SRC_R0L_DST16_RN_DIRECT_QI, "movlh16.src-r0l-dst16-Rn-direct-QI", "movlh", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movlh $Dst16AnQI,r0l */ { M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_DIRECT_QI, "movlh16.src-r0l-dst16-An-direct-QI", "movlh", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movlh [$Dst16An],r0l */ { M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_INDIRECT_QI, "movlh16.src-r0l-dst16-An-indirect-QI", "movlh", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movlh ${Dsp-16-u8}[$Dst16An],r0l */ { M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-An-relative-QI", "movlh", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movlh ${Dsp-16-u16}[$Dst16An],r0l */ { M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movlh16.src-r0l-dst16-16-16-An-relative-QI", "movlh", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movlh ${Dsp-16-u8}[sb],r0l */ { M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-SB-relative-QI", "movlh", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movlh ${Dsp-16-u16}[sb],r0l */ { M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-16-SB-relative-QI", "movlh", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movlh ${Dsp-16-s8}[fb],r0l */ { M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-FB-relative-QI", "movlh", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movlh ${Dsp-16-u16},r0l */ { M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movlh16.src-r0l-dst16-16-16-absolute-QI", "movlh", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movll $Dst16RnQI,r0l */ { M32C_INSN_MOVLL16_SRC_R0L_DST16_RN_DIRECT_QI, "movll16.src-r0l-dst16-Rn-direct-QI", "movll", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movll $Dst16AnQI,r0l */ { M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_DIRECT_QI, "movll16.src-r0l-dst16-An-direct-QI", "movll", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movll [$Dst16An],r0l */ { M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_INDIRECT_QI, "movll16.src-r0l-dst16-An-indirect-QI", "movll", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movll ${Dsp-16-u8}[$Dst16An],r0l */ { M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-An-relative-QI", "movll", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movll ${Dsp-16-u16}[$Dst16An],r0l */ { M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movll16.src-r0l-dst16-16-16-An-relative-QI", "movll", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movll ${Dsp-16-u8}[sb],r0l */ { M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-SB-relative-QI", "movll", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movll ${Dsp-16-u16}[sb],r0l */ { M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movll16.src-r0l-dst16-16-16-SB-relative-QI", "movll", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movll ${Dsp-16-s8}[fb],r0l */ { M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-FB-relative-QI", "movll", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movll ${Dsp-16-u16},r0l */ { M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movll16.src-r0l-dst16-16-16-absolute-QI", "movll", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhh r0l,$Dst16RnQI */ { M32C_INSN_MOVHH16_R0L_DST_DST16_RN_DIRECT_QI, "movhh16.r0l-dst-dst16-Rn-direct-QI", "movhh", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhh r0l,$Dst16AnQI */ { M32C_INSN_MOVHH16_R0L_DST_DST16_AN_DIRECT_QI, "movhh16.r0l-dst-dst16-An-direct-QI", "movhh", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhh r0l,[$Dst16An] */ { M32C_INSN_MOVHH16_R0L_DST_DST16_AN_INDIRECT_QI, "movhh16.r0l-dst-dst16-An-indirect-QI", "movhh", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhh r0l,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-An-relative-QI", "movhh", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhh r0l,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-16-An-relative-QI", "movhh", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhh r0l,${Dsp-16-u8}[sb] */ { M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-SB-relative-QI", "movhh", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhh r0l,${Dsp-16-u16}[sb] */ { M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-16-SB-relative-QI", "movhh", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhh r0l,${Dsp-16-s8}[fb] */ { M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-FB-relative-QI", "movhh", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhh r0l,${Dsp-16-u16} */ { M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movhh16.r0l-dst-dst16-16-16-absolute-QI", "movhh", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhl r0l,$Dst16RnQI */ { M32C_INSN_MOVHL16_R0L_DST_DST16_RN_DIRECT_QI, "movhl16.r0l-dst-dst16-Rn-direct-QI", "movhl", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhl r0l,$Dst16AnQI */ { M32C_INSN_MOVHL16_R0L_DST_DST16_AN_DIRECT_QI, "movhl16.r0l-dst-dst16-An-direct-QI", "movhl", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhl r0l,[$Dst16An] */ { M32C_INSN_MOVHL16_R0L_DST_DST16_AN_INDIRECT_QI, "movhl16.r0l-dst-dst16-An-indirect-QI", "movhl", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhl r0l,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-An-relative-QI", "movhl", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhl r0l,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-16-An-relative-QI", "movhl", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhl r0l,${Dsp-16-u8}[sb] */ { M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-SB-relative-QI", "movhl", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhl r0l,${Dsp-16-u16}[sb] */ { M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-16-SB-relative-QI", "movhl", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhl r0l,${Dsp-16-s8}[fb] */ { M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-FB-relative-QI", "movhl", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movhl r0l,${Dsp-16-u16} */ { M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movhl16.r0l-dst-dst16-16-16-absolute-QI", "movhl", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movlh r0l,$Dst16RnQI */ { M32C_INSN_MOVLH16_R0L_DST_DST16_RN_DIRECT_QI, "movlh16.r0l-dst-dst16-Rn-direct-QI", "movlh", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movlh r0l,$Dst16AnQI */ { M32C_INSN_MOVLH16_R0L_DST_DST16_AN_DIRECT_QI, "movlh16.r0l-dst-dst16-An-direct-QI", "movlh", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movlh r0l,[$Dst16An] */ { M32C_INSN_MOVLH16_R0L_DST_DST16_AN_INDIRECT_QI, "movlh16.r0l-dst-dst16-An-indirect-QI", "movlh", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movlh r0l,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-An-relative-QI", "movlh", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movlh r0l,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-16-An-relative-QI", "movlh", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movlh r0l,${Dsp-16-u8}[sb] */ { M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-SB-relative-QI", "movlh", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movlh r0l,${Dsp-16-u16}[sb] */ { M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-16-SB-relative-QI", "movlh", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movlh r0l,${Dsp-16-s8}[fb] */ { M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-FB-relative-QI", "movlh", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movlh r0l,${Dsp-16-u16} */ { M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movlh16.r0l-dst-dst16-16-16-absolute-QI", "movlh", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movll r0l,$Dst16RnQI */ { M32C_INSN_MOVLL16_R0L_DST_DST16_RN_DIRECT_QI, "movll16.r0l-dst-dst16-Rn-direct-QI", "movll", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movll r0l,$Dst16AnQI */ { M32C_INSN_MOVLL16_R0L_DST_DST16_AN_DIRECT_QI, "movll16.r0l-dst-dst16-An-direct-QI", "movll", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movll r0l,[$Dst16An] */ { M32C_INSN_MOVLL16_R0L_DST_DST16_AN_INDIRECT_QI, "movll16.r0l-dst-dst16-An-indirect-QI", "movll", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movll r0l,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-An-relative-QI", "movll", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movll r0l,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movll16.r0l-dst-dst16-16-16-An-relative-QI", "movll", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movll r0l,${Dsp-16-u8}[sb] */ { M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-SB-relative-QI", "movll", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movll r0l,${Dsp-16-u16}[sb] */ { M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-16-SB-relative-QI", "movll", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movll r0l,${Dsp-16-s8}[fb] */ { M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-FB-relative-QI", "movll", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* movll r0l,${Dsp-16-u16} */ { M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movll16.r0l-dst-dst16-16-16-absolute-QI", "movll", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova [$Dst32AnUnprefixed],a1 */ { M32C_INSN_MOVA32_SRC_A1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a1 */ { M32C_INSN_MOVA32_SRC_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a1 */ { M32C_INSN_MOVA32_SRC_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a1 */ { M32C_INSN_MOVA32_SRC_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u8}[sb],a1 */ { M32C_INSN_MOVA32_SRC_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u16}[sb],a1 */ { M32C_INSN_MOVA32_SRC_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-s8}[fb],a1 */ { M32C_INSN_MOVA32_SRC_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-s16}[fb],a1 */ { M32C_INSN_MOVA32_SRC_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u16},a1 */ { M32C_INSN_MOVA32_SRC_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u24},a1 */ { M32C_INSN_MOVA32_SRC_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova [$Dst32AnUnprefixed],a0 */ { M32C_INSN_MOVA32_SRC_A0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a0 */ { M32C_INSN_MOVA32_SRC_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a0 */ { M32C_INSN_MOVA32_SRC_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a0 */ { M32C_INSN_MOVA32_SRC_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u8}[sb],a0 */ { M32C_INSN_MOVA32_SRC_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u16}[sb],a0 */ { M32C_INSN_MOVA32_SRC_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-s8}[fb],a0 */ { M32C_INSN_MOVA32_SRC_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-s16}[fb],a0 */ { M32C_INSN_MOVA32_SRC_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u16},a0 */ { M32C_INSN_MOVA32_SRC_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u24},a0 */ { M32C_INSN_MOVA32_SRC_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova [$Dst32AnUnprefixed],r3r1 */ { M32C_INSN_MOVA32_SRC_R3R1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r3r1 */ { M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r3r1 */ { M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r3r1 */ { M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u8}[sb],r3r1 */ { M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u16}[sb],r3r1 */ { M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-s8}[fb],r3r1 */ { M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-s16}[fb],r3r1 */ { M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u16},r3r1 */ { M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u24},r3r1 */ { M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova [$Dst32AnUnprefixed],r2r0 */ { M32C_INSN_MOVA32_SRC_R2R0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r2r0 */ { M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r2r0 */ { M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r2r0 */ { M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u8}[sb],r2r0 */ { M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u16}[sb],r2r0 */ { M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-s8}[fb],r2r0 */ { M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-s16}[fb],r2r0 */ { M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u16},r2r0 */ { M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova ${Dsp-16-u24},r2r0 */ { M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mova [$Dst16An],a1 */ { M32C_INSN_MOVA16_SRC_A1_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-a1-dst16-An-indirect-Mova-HI", "mova", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u8}[$Dst16An],a1 */ { M32C_INSN_MOVA16_SRC_A1_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-An-relative-Mova-HI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u16}[$Dst16An],a1 */ { M32C_INSN_MOVA16_SRC_A1_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-16-An-relative-Mova-HI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u8}[sb],a1 */ { M32C_INSN_MOVA16_SRC_A1_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-SB-relative-Mova-HI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u16}[sb],a1 */ { M32C_INSN_MOVA16_SRC_A1_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-16-SB-relative-Mova-HI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-s8}[fb],a1 */ { M32C_INSN_MOVA16_SRC_A1_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-FB-relative-Mova-HI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u16},a1 */ { M32C_INSN_MOVA16_SRC_A1_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-a1-dst16-16-16-absolute-Mova-HI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova [$Dst16An],a0 */ { M32C_INSN_MOVA16_SRC_A0_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-a0-dst16-An-indirect-Mova-HI", "mova", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u8}[$Dst16An],a0 */ { M32C_INSN_MOVA16_SRC_A0_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-An-relative-Mova-HI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u16}[$Dst16An],a0 */ { M32C_INSN_MOVA16_SRC_A0_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-16-An-relative-Mova-HI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u8}[sb],a0 */ { M32C_INSN_MOVA16_SRC_A0_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-SB-relative-Mova-HI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u16}[sb],a0 */ { M32C_INSN_MOVA16_SRC_A0_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-16-SB-relative-Mova-HI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-s8}[fb],a0 */ { M32C_INSN_MOVA16_SRC_A0_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-FB-relative-Mova-HI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u16},a0 */ { M32C_INSN_MOVA16_SRC_A0_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-a0-dst16-16-16-absolute-Mova-HI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova [$Dst16An],r3 */ { M32C_INSN_MOVA16_SRC_R3_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r3-dst16-An-indirect-Mova-HI", "mova", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u8}[$Dst16An],r3 */ { M32C_INSN_MOVA16_SRC_R3_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-An-relative-Mova-HI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u16}[$Dst16An],r3 */ { M32C_INSN_MOVA16_SRC_R3_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-16-An-relative-Mova-HI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u8}[sb],r3 */ { M32C_INSN_MOVA16_SRC_R3_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-SB-relative-Mova-HI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u16}[sb],r3 */ { M32C_INSN_MOVA16_SRC_R3_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-16-SB-relative-Mova-HI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-s8}[fb],r3 */ { M32C_INSN_MOVA16_SRC_R3_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-FB-relative-Mova-HI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u16},r3 */ { M32C_INSN_MOVA16_SRC_R3_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r3-dst16-16-16-absolute-Mova-HI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova [$Dst16An],r2 */ { M32C_INSN_MOVA16_SRC_R2_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r2-dst16-An-indirect-Mova-HI", "mova", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u8}[$Dst16An],r2 */ { M32C_INSN_MOVA16_SRC_R2_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-An-relative-Mova-HI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u16}[$Dst16An],r2 */ { M32C_INSN_MOVA16_SRC_R2_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-16-An-relative-Mova-HI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u8}[sb],r2 */ { M32C_INSN_MOVA16_SRC_R2_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-SB-relative-Mova-HI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u16}[sb],r2 */ { M32C_INSN_MOVA16_SRC_R2_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-16-SB-relative-Mova-HI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-s8}[fb],r2 */ { M32C_INSN_MOVA16_SRC_R2_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-FB-relative-Mova-HI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u16},r2 */ { M32C_INSN_MOVA16_SRC_R2_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r2-dst16-16-16-absolute-Mova-HI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova [$Dst16An],r1 */ { M32C_INSN_MOVA16_SRC_R1_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r1-dst16-An-indirect-Mova-HI", "mova", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u8}[$Dst16An],r1 */ { M32C_INSN_MOVA16_SRC_R1_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-An-relative-Mova-HI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u16}[$Dst16An],r1 */ { M32C_INSN_MOVA16_SRC_R1_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-16-An-relative-Mova-HI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u8}[sb],r1 */ { M32C_INSN_MOVA16_SRC_R1_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-SB-relative-Mova-HI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u16}[sb],r1 */ { M32C_INSN_MOVA16_SRC_R1_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-16-SB-relative-Mova-HI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-s8}[fb],r1 */ { M32C_INSN_MOVA16_SRC_R1_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-FB-relative-Mova-HI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u16},r1 */ { M32C_INSN_MOVA16_SRC_R1_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r1-dst16-16-16-absolute-Mova-HI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova [$Dst16An],r0 */ { M32C_INSN_MOVA16_SRC_R0_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r0-dst16-An-indirect-Mova-HI", "mova", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u8}[$Dst16An],r0 */ { M32C_INSN_MOVA16_SRC_R0_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-An-relative-Mova-HI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u16}[$Dst16An],r0 */ { M32C_INSN_MOVA16_SRC_R0_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-16-An-relative-Mova-HI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u8}[sb],r0 */ { M32C_INSN_MOVA16_SRC_R0_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-SB-relative-Mova-HI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u16}[sb],r0 */ { M32C_INSN_MOVA16_SRC_R0_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-16-SB-relative-Mova-HI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-s8}[fb],r0 */ { M32C_INSN_MOVA16_SRC_R0_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-FB-relative-Mova-HI", "mova", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mova ${Dsp-16-u16},r0 */ { M32C_INSN_MOVA16_SRC_R0_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r0-dst16-16-16-absolute-Mova-HI", "mova", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-s8}[sp] */ { M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */ { M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */ { M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-s8}[sp] */ { M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */ { M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[sp] */ { M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */ { M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-s8}[sp] */ { M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[sp] */ { M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Dst32RnUnprefixedHI,${Dsp-16-s8}[sp] */ { M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Dst32AnUnprefixedHI,${Dsp-16-s8}[sp] */ { M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} [$Dst32AnUnprefixed],${Dsp-16-s8}[sp] */ { M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-s8}[sp] */ { M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */ { M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */ { M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-s8}[sp] */ { M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */ { M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[sp] */ { M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */ { M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-s8}[sp] */ { M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[sp] */ { M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Dst32RnUnprefixedQI,${Dsp-16-s8}[sp] */ { M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Dst32AnUnprefixedQI,${Dsp-16-s8}[sp] */ { M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} [$Dst32AnUnprefixed],${Dsp-16-s8}[sp] */ { M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[$Dst16An],${Dsp-24-s8}[sp] */ { M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-An-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */ { M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-SB-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */ { M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-FB-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16}[$Dst16An],${Dsp-32-s8}[sp] */ { M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-An-relative-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */ { M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-SB-relative-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */ { M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-absolute-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} $Dst16RnHI,${Dsp-16-s8}[sp] */ { M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-Rn-direct-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} $Dst16AnHI,${Dsp-16-s8}[sp] */ { M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-An-direct-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} [$Dst16An],${Dsp-16-s8}[sp] */ { M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-An-indirect-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u8}[$Dst16An],${Dsp-24-s8}[sp] */ { M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-An-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */ { M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */ { M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16}[$Dst16An],${Dsp-32-s8}[sp] */ { M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-An-relative-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */ { M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */ { M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-absolute-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} $Dst16RnQI,${Dsp-16-s8}[sp] */ { M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-Rn-direct-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} $Dst16AnQI,${Dsp-16-s8}[sp] */ { M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-An-direct-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} [$Dst16An],${Dsp-16-s8}[sp] */ { M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-An-indirect-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */ { M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-40-s8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-40-s8}[sp],${Dsp-16-u24} */ { M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s8}[sp],$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s8}[sp],$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s8}[sp],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */ { M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-40-s8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-40-s8}[sp],${Dsp-16-u24} */ { M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s8}[sp],$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s8}[sp],$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s8}[sp],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-An-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-SB-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-FB-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-An-relative-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */ { M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-SB-relative-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */ { M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-absolute-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-s8}[sp],$Dst16RnHI */ { M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_RN_DIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-Rn-direct-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-s8}[sp],$Dst16AnHI */ { M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_DIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-An-direct-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-s8}[sp],[$Dst16An] */ { M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-An-indirect-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-An-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-An-relative-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */ { M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */ { M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-absolute-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-s8}[sp],$Dst16RnQI */ { M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_RN_DIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-Rn-direct-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-s8}[sp],$Dst16AnQI */ { M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_DIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-An-direct-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-s8}[sp],[$Dst16An] */ { M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-An-indirect-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.l${S} ${Dsp-8-u8}[sb],a1 */ { M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_SB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a1-dst32-2-S-8-SB-relative-SI", "mov.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${S} ${Dsp-8-s8}[fb],a1 */ { M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_FB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a1-dst32-2-S-8-FB-relative-SI", "mov.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${S} ${Dsp-8-u8}[sb],a0 */ { M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_SB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a0-dst32-2-S-8-SB-relative-SI", "mov.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${S} ${Dsp-8-s8}[fb],a0 */ { M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_FB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a0-dst32-2-S-8-FB-relative-SI", "mov.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${S} ${Dsp-8-u16},a1 */ { M32C_INSN_MOV32_SZ_DST32_2_S_16_A1_DST32_2_S_16_ABSOLUTE_SI, "mov32.sz-dst32-2-S-16-a1-dst32-2-S-16-absolute-SI", "mov.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${S} ${Dsp-8-u16},a0 */ { M32C_INSN_MOV32_SZ_DST32_2_S_16_A0_DST32_2_S_16_ABSOLUTE_SI, "mov32.sz-dst32-2-S-16-a0-dst32-2-S-16-absolute-SI", "mov.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${S} r0,${Dsp-8-u8}[sb] */ { M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-r0-dst32-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${S} r0,${Dsp-8-s8}[fb] */ { M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-r0-dst32-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${S} r0l,${Dsp-8-u8}[sb] */ { M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-r0l-dst32-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${S} r0l,${Dsp-8-s8}[fb] */ { M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-r0l-dst32-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${S} r0,${Dsp-8-u16} */ { M32C_INSN_MOV32_W_R0_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-r0-dst32-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${S} r0l,${Dsp-8-u16} */ { M32C_INSN_MOV32_B_R0L_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-r0l-dst32-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${S} ${Dsp-8-u8}[sb],r1 */ { M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r1-dst32-2-S-8-SB-relative-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${S} ${Dsp-8-s8}[fb],r1 */ { M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r1-dst32-2-S-8-FB-relative-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${S} ${Dsp-8-u8}[sb],r1l */ { M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r1l-dst32-2-S-8-SB-relative-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${S} ${Dsp-8-s8}[fb],r1l */ { M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r1l-dst32-2-S-8-FB-relative-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${S} ${Dsp-8-u16},r1 */ { M32C_INSN_MOV32_W_DST32_2_S_16_R1_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-dst32-2-S-16-r1-dst32-2-S-16-absolute-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${S} ${Dsp-8-u16},r1l */ { M32C_INSN_MOV32_B_DST32_2_S_16_R1L_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-dst32-2-S-16-r1l-dst32-2-S-16-absolute-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${S} r0,r1 */ { M32C_INSN_MOV32_W_DST32_2_S_BASIC_R1_DST32_2_S_R0_DIRECT_HI, "mov32.w-dst32-2-S-basic-r1-dst32-2-S-R0-direct-HI", "mov.w", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${S} r0l,r1l */ { M32C_INSN_MOV32_B_DST32_2_S_BASIC_R1L_DST32_2_S_R0L_DIRECT_QI, "mov32.b-dst32-2-S-basic-r1l-dst32-2-S-R0l-direct-QI", "mov.b", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${S} ${Dsp-8-u8}[sb],r0 */ { M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r0-dst32-2-S-8-SB-relative-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${S} ${Dsp-8-s8}[fb],r0 */ { M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r0-dst32-2-S-8-FB-relative-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${S} ${Dsp-8-u8}[sb],r0l */ { M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r0l-dst32-2-S-8-SB-relative-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${S} ${Dsp-8-s8}[fb],r0l */ { M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r0l-dst32-2-S-8-FB-relative-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${S} ${Dsp-8-u16},r0 */ { M32C_INSN_MOV32_W_DST32_2_S_16_R0_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-dst32-2-S-16-r0-dst32-2-S-16-absolute-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${S} ${Dsp-8-u16},r0l */ { M32C_INSN_MOV32_B_DST32_2_S_16_R0L_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-dst32-2-S-16-r0l-dst32-2-S-16-absolute-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${S} ${SrcDst16-r0l-r0h-S-normal} */ { M32C_INSN_MOV16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "mov16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "mov.b", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */ { M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-src2-src16-2-S-8-SB-relative-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */ { M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-src2-src16-2-S-8-FB-relative-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */ { M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-src2-src16-2-S-16-absolute-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u8}[sb] */ { M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-Rn-An-src16-2-S-8-SB-relative-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${S} ${Dst16RnQI-S},${Dsp-8-s8}[fb] */ { M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-Rn-An-src16-2-S-8-FB-relative-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u16} */ { M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-Rn-An-src16-2-S-16-absolute-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "mov.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "mov.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "mov.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "mov.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "mov.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "mov.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "mov.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "mov.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "mov.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "mov.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "mov.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "mov.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${S} ${Dsp-8-u8}[sb],${Dst16AnQI-S} */ { M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-An-src16-2-S-8-SB-relative-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${S} ${Dsp-8-s8}[fb],${Dst16AnQI-S} */ { M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-An-src16-2-S-8-FB-relative-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${S} ${Dsp-8-u16},${Dst16AnQI-S} */ { M32C_INSN_MOV16_B_S_AN_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-An-src16-2-S-16-absolute-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mov.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mov.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mov.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mov.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mov.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mov.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mov.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mov.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mov.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mov.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mov.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mov.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mov.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mov.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mov.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mov.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mov.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mov.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mov.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mov.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mov.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mov.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mov.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mov.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16},$Dst16RnHI */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16},$Dst16AnHI */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} $Src16RnHI,$Dst16RnHI */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} $Src16AnHI,$Dst16RnHI */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} [$Src16An],$Dst16RnHI */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} $Src16RnHI,$Dst16AnHI */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} $Src16AnHI,$Dst16AnHI */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} [$Src16An],$Dst16AnHI */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} $Src16RnHI,[$Dst16An] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} $Src16AnHI,[$Dst16An] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} [$Src16An],[$Dst16An] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} $Src16RnHI,${Dsp-16-u16} */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} $Src16AnHI,${Dsp-16-u16} */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16},$Dst16RnQI */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16},$Dst16AnQI */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} $Src16RnQI,$Dst16RnQI */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} $Src16AnQI,$Dst16RnQI */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} [$Src16An],$Dst16RnQI */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} $Src16RnQI,$Dst16AnQI */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} $Src16AnQI,$Dst16AnQI */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} [$Src16An],$Dst16AnQI */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} $Src16RnQI,[$Dst16An] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} $Src16AnQI,[$Dst16An] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} [$Src16An],[$Dst16An] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} $Src16RnQI,${Dsp-16-u16} */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} $Src16AnQI,${Dsp-16-u16} */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${Z} #0,${Dsp-8-u8}[sb] */ { M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-imm-Z-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${Z} #0,${Dsp-8-s8}[fb] */ { M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-imm-Z-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${Z} #0,${Dsp-8-u16} */ { M32C_INSN_MOV32_W_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-imm-Z-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${Z} #0,r0 */ { M32C_INSN_MOV32_W_IMM_Z_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "mov32.w-imm-Z-2-S-basic-dst32-2-S-R0-direct-HI", "mov.w", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${Z} #0,${Dsp-8-u8}[sb] */ { M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-imm-Z-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${Z} #0,${Dsp-8-s8}[fb] */ { M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-imm-Z-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${Z} #0,${Dsp-8-u16} */ { M32C_INSN_MOV32_B_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-imm-Z-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${Z} #0,r0l */ { M32C_INSN_MOV32_B_IMM_Z_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "mov32.b-imm-Z-2-S-basic-dst32-2-S-R0l-direct-QI", "mov.b", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${Z} #0,r0l */ { M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-R0l-direct-QI", "mov.b", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${Z} #0,r0h */ { M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-R0h-direct-QI", "mov.b", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${Z} #0,${Dsp-8-u8}[sb] */ { M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_SB_RELATIVE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-8-SB-relative-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${Z} #0,${Dsp-8-s8}[fb] */ { M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_FB_RELATIVE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-8-FB-relative-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${Z} #0,${Dsp-8-u16} */ { M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_16_ABSOLUTE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-16-absolute-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16} */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24} */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16} */ { M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24} */ { M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${Q} #${Imm-8-s4},$Dst16RnQI */ { M32C_INSN_MOV16_W_IMM4_Q_16_DST16_RN_DIRECT_QI, "mov16.w-imm4-Q-16-dst16-Rn-direct-QI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${Q} #${Imm-8-s4},$Dst16AnQI */ { M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_DIRECT_QI, "mov16.w-imm4-Q-16-dst16-An-direct-QI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${Q} #${Imm-8-s4},[$Dst16An] */ { M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_INDIRECT_QI, "mov16.w-imm4-Q-16-dst16-An-indirect-QI", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-8-An-relative-QI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-16-An-relative-QI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-8-SB-relative-QI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-16-SB-relative-QI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-8-FB-relative-QI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16} */ { M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "mov16.w-imm4-Q-16-dst16-16-16-absolute-QI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${Q} #${Imm-8-s4},$Dst16RnQI */ { M32C_INSN_MOV16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "mov16.b-imm4-Q-16-dst16-Rn-direct-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${Q} #${Imm-8-s4},$Dst16AnQI */ { M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "mov16.b-imm4-Q-16-dst16-An-direct-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${Q} #${Imm-8-s4},[$Dst16An] */ { M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "mov16.b-imm4-Q-16-dst16-An-indirect-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16} */ { M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-imm4-Q-16-dst16-16-16-absolute-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${S} #${Imm-8-QI},r0l */ { M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${S} #${Imm-8-QI},r0h */ { M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${S} #${Imm-8-QI},${Dsp-16-u16} */ { M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ { M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ { M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${S} #${Imm-24-HI},${Dsp-8-u16} */ { M32C_INSN_MOV32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${S} #${Imm-8-HI},r0 */ { M32C_INSN_MOV32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "mov32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ { M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ { M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${S} #${Imm-24-QI},${Dsp-8-u16} */ { M32C_INSN_MOV32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${S} #${Imm-8-QI},r0l */ { M32C_INSN_MOV32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "mov32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */ { M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "mov.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} #${Imm-32-SI},${Dsp-16-u16} */ { M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l${G} #${Imm-40-SI},${Dsp-16-u24} */ { M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ { M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} #${Imm-40-HI},${Dsp-16-u24} */ { M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ { M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ { M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b${G} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w${G} #${Imm-16-HI},$Dst16RnHI */ { M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mov16.w-imm-G-basic-dst16-Rn-direct-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} #${Imm-16-HI},$Dst16AnHI */ { M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mov16.w-imm-G-basic-dst16-An-direct-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} #${Imm-16-HI},[$Dst16An] */ { M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-imm-G-basic-dst16-An-indirect-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mov.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} #${Imm-16-QI},$Dst16RnQI */ { M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mov16.b-imm-G-basic-dst16-Rn-direct-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} #${Imm-16-QI},$Dst16AnQI */ { M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mov16.b-imm-G-basic-dst16-An-direct-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} #${Imm-16-QI},[$Dst16An] */ { M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-imm-G-basic-dst16-An-indirect-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mov.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "min.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "min.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "min.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "min.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "min.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "min.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "min.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "min.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "min.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "min.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "min.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "min.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "min.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "min.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "min.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "min.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "min.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "min.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "min.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "min.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "min.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "min.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "min.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "min.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ { M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ { M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "min.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ { M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ { M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ { M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ { M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} #${Imm-40-HI},${Dsp-24-u16} */ { M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "min.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "min.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.w${X} #${Imm-48-HI},${Dsp-24-u24} */ { M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "min.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ { M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "min.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ { M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "min.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "min.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ { M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ { M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ { M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ { M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} #${Imm-40-QI},${Dsp-24-u16} */ { M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "min.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* min.b${X} #${Imm-48-QI},${Dsp-24-u24} */ { M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "min.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ { M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ { M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "max.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "max.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "max.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "max.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "max.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "max.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "max.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "max.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "max.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "max.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "max.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "max.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "max.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "max.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "max.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ { M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ { M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "max.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "max.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "max.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "max.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "max.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "max.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "max.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "max.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "max.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "max.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "max.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "max.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "max.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "max.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "max.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ { M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ { M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "max.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ { M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ { M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ { M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ { M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} #${Imm-40-HI},${Dsp-24-u16} */ { M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "max.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "max.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.w${X} #${Imm-48-HI},${Dsp-24-u24} */ { M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "max.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ { M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "max.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ { M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "max.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "max.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ { M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ { M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ { M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ { M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} #${Imm-40-QI},${Dsp-24-u16} */ { M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "max.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* max.b${X} #${Imm-48-QI},${Dsp-24-u24} */ { M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "max.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ste.w ${Dsp-16-u16}[$Dst16An],[a1a0] */ { M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI, "ste.w-16-16-a1a0-dst16-16-16-An-relative-HI", "ste.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w ${Dsp-16-u16}[sb],[a1a0] */ { M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, "ste.w-16-16-a1a0-dst16-16-16-SB-relative-HI", "ste.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w ${Dsp-16-u16},[a1a0] */ { M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI, "ste.w-16-16-a1a0-dst16-16-16-absolute-HI", "ste.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */ { M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, "ste.w-16-16-u20a0-dst16-16-16-An-relative-HI", "ste.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */ { M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI, "ste.w-16-16-u20a0-dst16-16-16-SB-relative-HI", "ste.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w ${Dsp-16-u16},${Dsp-32-u20}[a0] */ { M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, "ste.w-16-16-u20a0-dst16-16-16-absolute-HI", "ste.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */ { M32C_INSN_STE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI, "ste.w-16-16-u20-dst16-16-16-An-relative-HI", "ste.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20} */ { M32C_INSN_STE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, "ste.w-16-16-u20-dst16-16-16-SB-relative-HI", "ste.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w ${Dsp-16-u16},${Dsp-32-u20} */ { M32C_INSN_STE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI, "ste.w-16-16-u20-dst16-16-16-absolute-HI", "ste.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w ${Dsp-16-u8}[$Dst16An],[a1a0] */ { M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, "ste.w-16-8-a1a0-dst16-16-8-An-relative-HI", "ste.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w ${Dsp-16-u8}[sb],[a1a0] */ { M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI, "ste.w-16-8-a1a0-dst16-16-8-SB-relative-HI", "ste.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w ${Dsp-16-s8}[fb],[a1a0] */ { M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, "ste.w-16-8-a1a0-dst16-16-8-FB-relative-HI", "ste.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */ { M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI, "ste.w-16-8-u20a0-dst16-16-8-An-relative-HI", "ste.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */ { M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, "ste.w-16-8-u20a0-dst16-16-8-SB-relative-HI", "ste.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */ { M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI, "ste.w-16-8-u20a0-dst16-16-8-FB-relative-HI", "ste.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */ { M32C_INSN_STE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, "ste.w-16-8-u20-dst16-16-8-An-relative-HI", "ste.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20} */ { M32C_INSN_STE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI, "ste.w-16-8-u20-dst16-16-8-SB-relative-HI", "ste.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20} */ { M32C_INSN_STE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, "ste.w-16-8-u20-dst16-16-8-FB-relative-HI", "ste.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w $Dst16RnHI,[a1a0] */ { M32C_INSN_STE_W_BASIC_A1A0_DST16_RN_DIRECT_HI, "ste.w-basic-a1a0-dst16-Rn-direct-HI", "ste.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w $Dst16AnHI,[a1a0] */ { M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, "ste.w-basic-a1a0-dst16-An-direct-HI", "ste.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w [$Dst16An],[a1a0] */ { M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI, "ste.w-basic-a1a0-dst16-An-indirect-HI", "ste.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w $Dst16RnHI,${Dsp-16-u20}[a0] */ { M32C_INSN_STE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, "ste.w-basic-u20a0-dst16-Rn-direct-HI", "ste.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w $Dst16AnHI,${Dsp-16-u20}[a0] */ { M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_DIRECT_HI, "ste.w-basic-u20a0-dst16-An-direct-HI", "ste.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w [$Dst16An],${Dsp-16-u20}[a0] */ { M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, "ste.w-basic-u20a0-dst16-An-indirect-HI", "ste.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w $Dst16RnHI,${Dsp-16-u20} */ { M32C_INSN_STE_W_BASIC_U20_DST16_RN_DIRECT_HI, "ste.w-basic-u20-dst16-Rn-direct-HI", "ste.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w $Dst16AnHI,${Dsp-16-u20} */ { M32C_INSN_STE_W_BASIC_U20_DST16_AN_DIRECT_HI, "ste.w-basic-u20-dst16-An-direct-HI", "ste.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.w [$Dst16An],${Dsp-16-u20} */ { M32C_INSN_STE_W_BASIC_U20_DST16_AN_INDIRECT_HI, "ste.w-basic-u20-dst16-An-indirect-HI", "ste.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b ${Dsp-16-u16}[$Dst16An],[a1a0] */ { M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, "ste.b-16-16-a1a0-dst16-16-16-An-relative-QI", "ste.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b ${Dsp-16-u16}[sb],[a1a0] */ { M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI, "ste.b-16-16-a1a0-dst16-16-16-SB-relative-QI", "ste.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b ${Dsp-16-u16},[a1a0] */ { M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, "ste.b-16-16-a1a0-dst16-16-16-absolute-QI", "ste.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */ { M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI, "ste.b-16-16-u20a0-dst16-16-16-An-relative-QI", "ste.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */ { M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, "ste.b-16-16-u20a0-dst16-16-16-SB-relative-QI", "ste.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b ${Dsp-16-u16},${Dsp-32-u20}[a0] */ { M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI, "ste.b-16-16-u20a0-dst16-16-16-absolute-QI", "ste.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */ { M32C_INSN_STE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, "ste.b-16-16-u20-dst16-16-16-An-relative-QI", "ste.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20} */ { M32C_INSN_STE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI, "ste.b-16-16-u20-dst16-16-16-SB-relative-QI", "ste.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b ${Dsp-16-u16},${Dsp-32-u20} */ { M32C_INSN_STE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, "ste.b-16-16-u20-dst16-16-16-absolute-QI", "ste.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b ${Dsp-16-u8}[$Dst16An],[a1a0] */ { M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI, "ste.b-16-8-a1a0-dst16-16-8-An-relative-QI", "ste.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b ${Dsp-16-u8}[sb],[a1a0] */ { M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, "ste.b-16-8-a1a0-dst16-16-8-SB-relative-QI", "ste.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b ${Dsp-16-s8}[fb],[a1a0] */ { M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI, "ste.b-16-8-a1a0-dst16-16-8-FB-relative-QI", "ste.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */ { M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, "ste.b-16-8-u20a0-dst16-16-8-An-relative-QI", "ste.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */ { M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI, "ste.b-16-8-u20a0-dst16-16-8-SB-relative-QI", "ste.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */ { M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, "ste.b-16-8-u20a0-dst16-16-8-FB-relative-QI", "ste.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */ { M32C_INSN_STE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI, "ste.b-16-8-u20-dst16-16-8-An-relative-QI", "ste.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20} */ { M32C_INSN_STE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, "ste.b-16-8-u20-dst16-16-8-SB-relative-QI", "ste.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20} */ { M32C_INSN_STE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI, "ste.b-16-8-u20-dst16-16-8-FB-relative-QI", "ste.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b $Dst16RnQI,[a1a0] */ { M32C_INSN_STE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, "ste.b-basic-a1a0-dst16-Rn-direct-QI", "ste.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b $Dst16AnQI,[a1a0] */ { M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_DIRECT_QI, "ste.b-basic-a1a0-dst16-An-direct-QI", "ste.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b [$Dst16An],[a1a0] */ { M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, "ste.b-basic-a1a0-dst16-An-indirect-QI", "ste.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b $Dst16RnQI,${Dsp-16-u20}[a0] */ { M32C_INSN_STE_B_BASIC_U20A0_DST16_RN_DIRECT_QI, "ste.b-basic-u20a0-dst16-Rn-direct-QI", "ste.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b $Dst16AnQI,${Dsp-16-u20}[a0] */ { M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, "ste.b-basic-u20a0-dst16-An-direct-QI", "ste.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b [$Dst16An],${Dsp-16-u20}[a0] */ { M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI, "ste.b-basic-u20a0-dst16-An-indirect-QI", "ste.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b $Dst16RnQI,${Dsp-16-u20} */ { M32C_INSN_STE_B_BASIC_U20_DST16_RN_DIRECT_QI, "ste.b-basic-u20-dst16-Rn-direct-QI", "ste.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b $Dst16AnQI,${Dsp-16-u20} */ { M32C_INSN_STE_B_BASIC_U20_DST16_AN_DIRECT_QI, "ste.b-basic-u20-dst16-An-direct-QI", "ste.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ste.b [$Dst16An],${Dsp-16-u20} */ { M32C_INSN_STE_B_BASIC_U20_DST16_AN_INDIRECT_QI, "ste.b-basic-u20-dst16-An-indirect-QI", "ste.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w [a1a0],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI, "lde.w-16-16-a1a0-dst16-16-16-An-relative-HI", "lde.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w [a1a0],${Dsp-16-u16}[sb] */ { M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, "lde.w-16-16-a1a0-dst16-16-16-SB-relative-HI", "lde.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w [a1a0],${Dsp-16-u16} */ { M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI, "lde.w-16-16-a1a0-dst16-16-16-absolute-HI", "lde.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, "lde.w-16-16-u20a0-dst16-16-16-An-relative-HI", "lde.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */ { M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI, "lde.w-16-16-u20a0-dst16-16-16-SB-relative-HI", "lde.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16} */ { M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, "lde.w-16-16-u20a0-dst16-16-16-absolute-HI", "lde.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_LDE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI, "lde.w-16-16-u20-dst16-16-16-An-relative-HI", "lde.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w ${Dsp-32-u20},${Dsp-16-u16}[sb] */ { M32C_INSN_LDE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, "lde.w-16-16-u20-dst16-16-16-SB-relative-HI", "lde.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w ${Dsp-32-u20},${Dsp-16-u16} */ { M32C_INSN_LDE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI, "lde.w-16-16-u20-dst16-16-16-absolute-HI", "lde.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w [a1a0],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, "lde.w-16-8-a1a0-dst16-16-8-An-relative-HI", "lde.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w [a1a0],${Dsp-16-u8}[sb] */ { M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI, "lde.w-16-8-a1a0-dst16-16-8-SB-relative-HI", "lde.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w [a1a0],${Dsp-16-s8}[fb] */ { M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, "lde.w-16-8-a1a0-dst16-16-8-FB-relative-HI", "lde.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI, "lde.w-16-8-u20a0-dst16-16-8-An-relative-HI", "lde.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */ { M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, "lde.w-16-8-u20a0-dst16-16-8-SB-relative-HI", "lde.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */ { M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI, "lde.w-16-8-u20a0-dst16-16-8-FB-relative-HI", "lde.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_LDE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, "lde.w-16-8-u20-dst16-16-8-An-relative-HI", "lde.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w ${Dsp-24-u20},${Dsp-16-u8}[sb] */ { M32C_INSN_LDE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI, "lde.w-16-8-u20-dst16-16-8-SB-relative-HI", "lde.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w ${Dsp-24-u20},${Dsp-16-s8}[fb] */ { M32C_INSN_LDE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, "lde.w-16-8-u20-dst16-16-8-FB-relative-HI", "lde.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w [a1a0],$Dst16RnHI */ { M32C_INSN_LDE_W_BASIC_A1A0_DST16_RN_DIRECT_HI, "lde.w-basic-a1a0-dst16-Rn-direct-HI", "lde.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w [a1a0],$Dst16AnHI */ { M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, "lde.w-basic-a1a0-dst16-An-direct-HI", "lde.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w [a1a0],[$Dst16An] */ { M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI, "lde.w-basic-a1a0-dst16-An-indirect-HI", "lde.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w ${Dsp-16-u20}[a0],$Dst16RnHI */ { M32C_INSN_LDE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, "lde.w-basic-u20a0-dst16-Rn-direct-HI", "lde.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w ${Dsp-16-u20}[a0],$Dst16AnHI */ { M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_DIRECT_HI, "lde.w-basic-u20a0-dst16-An-direct-HI", "lde.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w ${Dsp-16-u20}[a0],[$Dst16An] */ { M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, "lde.w-basic-u20a0-dst16-An-indirect-HI", "lde.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w ${Dsp-16-u20},$Dst16RnHI */ { M32C_INSN_LDE_W_BASIC_U20_DST16_RN_DIRECT_HI, "lde.w-basic-u20-dst16-Rn-direct-HI", "lde.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w ${Dsp-16-u20},$Dst16AnHI */ { M32C_INSN_LDE_W_BASIC_U20_DST16_AN_DIRECT_HI, "lde.w-basic-u20-dst16-An-direct-HI", "lde.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.w ${Dsp-16-u20},[$Dst16An] */ { M32C_INSN_LDE_W_BASIC_U20_DST16_AN_INDIRECT_HI, "lde.w-basic-u20-dst16-An-indirect-HI", "lde.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b [a1a0],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, "lde.b-16-16-a1a0-dst16-16-16-An-relative-QI", "lde.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b [a1a0],${Dsp-16-u16}[sb] */ { M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI, "lde.b-16-16-a1a0-dst16-16-16-SB-relative-QI", "lde.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b [a1a0],${Dsp-16-u16} */ { M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, "lde.b-16-16-a1a0-dst16-16-16-absolute-QI", "lde.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI, "lde.b-16-16-u20a0-dst16-16-16-An-relative-QI", "lde.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */ { M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, "lde.b-16-16-u20a0-dst16-16-16-SB-relative-QI", "lde.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16} */ { M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI, "lde.b-16-16-u20a0-dst16-16-16-absolute-QI", "lde.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_LDE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, "lde.b-16-16-u20-dst16-16-16-An-relative-QI", "lde.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b ${Dsp-32-u20},${Dsp-16-u16}[sb] */ { M32C_INSN_LDE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI, "lde.b-16-16-u20-dst16-16-16-SB-relative-QI", "lde.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b ${Dsp-32-u20},${Dsp-16-u16} */ { M32C_INSN_LDE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, "lde.b-16-16-u20-dst16-16-16-absolute-QI", "lde.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b [a1a0],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI, "lde.b-16-8-a1a0-dst16-16-8-An-relative-QI", "lde.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b [a1a0],${Dsp-16-u8}[sb] */ { M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, "lde.b-16-8-a1a0-dst16-16-8-SB-relative-QI", "lde.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b [a1a0],${Dsp-16-s8}[fb] */ { M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI, "lde.b-16-8-a1a0-dst16-16-8-FB-relative-QI", "lde.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, "lde.b-16-8-u20a0-dst16-16-8-An-relative-QI", "lde.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */ { M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI, "lde.b-16-8-u20a0-dst16-16-8-SB-relative-QI", "lde.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */ { M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, "lde.b-16-8-u20a0-dst16-16-8-FB-relative-QI", "lde.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_LDE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI, "lde.b-16-8-u20-dst16-16-8-An-relative-QI", "lde.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b ${Dsp-24-u20},${Dsp-16-u8}[sb] */ { M32C_INSN_LDE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, "lde.b-16-8-u20-dst16-16-8-SB-relative-QI", "lde.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b ${Dsp-24-u20},${Dsp-16-s8}[fb] */ { M32C_INSN_LDE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI, "lde.b-16-8-u20-dst16-16-8-FB-relative-QI", "lde.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b [a1a0],$Dst16RnQI */ { M32C_INSN_LDE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, "lde.b-basic-a1a0-dst16-Rn-direct-QI", "lde.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b [a1a0],$Dst16AnQI */ { M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_DIRECT_QI, "lde.b-basic-a1a0-dst16-An-direct-QI", "lde.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b [a1a0],[$Dst16An] */ { M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, "lde.b-basic-a1a0-dst16-An-indirect-QI", "lde.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b ${Dsp-16-u20}[a0],$Dst16RnQI */ { M32C_INSN_LDE_B_BASIC_U20A0_DST16_RN_DIRECT_QI, "lde.b-basic-u20a0-dst16-Rn-direct-QI", "lde.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b ${Dsp-16-u20}[a0],$Dst16AnQI */ { M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, "lde.b-basic-u20a0-dst16-An-direct-QI", "lde.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b ${Dsp-16-u20}[a0],[$Dst16An] */ { M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI, "lde.b-basic-u20a0-dst16-An-indirect-QI", "lde.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b ${Dsp-16-u20},$Dst16RnQI */ { M32C_INSN_LDE_B_BASIC_U20_DST16_RN_DIRECT_QI, "lde.b-basic-u20-dst16-Rn-direct-QI", "lde.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b ${Dsp-16-u20},$Dst16AnQI */ { M32C_INSN_LDE_B_BASIC_U20_DST16_AN_DIRECT_QI, "lde.b-basic-u20-dst16-An-direct-QI", "lde.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* lde.b ${Dsp-16-u20},[$Dst16An] */ { M32C_INSN_LDE_B_BASIC_U20_DST16_AN_INDIRECT_QI, "lde.b-basic-u20-dst16-An-indirect-QI", "lde.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stc ${cr3-Prefixed-32},$Dst32RnPrefixedSI */ { M32C_INSN_STC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, "stc32.src-cr3-dst32-Rn-direct-Prefixed-SI", "stc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr3-Prefixed-32},$Dst32AnPrefixedSI */ { M32C_INSN_STC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, "stc32.src-cr3-dst32-An-direct-Prefixed-SI", "stc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr3-Prefixed-32},[$Dst32AnPrefixed] */ { M32C_INSN_STC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI, "stc32.src-cr3-dst32-An-indirect-Prefixed-SI", "stc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr3-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_STC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-8-An-relative-Prefixed-SI", "stc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr3-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_STC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-An-relative-Prefixed-SI", "stc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr3-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_STC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-24-An-relative-Prefixed-SI", "stc", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr3-Prefixed-32},${Dsp-24-u8}[sb] */ { M32C_INSN_STC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-8-SB-relative-Prefixed-SI", "stc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr3-Prefixed-32},${Dsp-24-u16}[sb] */ { M32C_INSN_STC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-SB-relative-Prefixed-SI", "stc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr3-Prefixed-32},${Dsp-24-s8}[fb] */ { M32C_INSN_STC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-8-FB-relative-Prefixed-SI", "stc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr3-Prefixed-32},${Dsp-24-s16}[fb] */ { M32C_INSN_STC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-FB-relative-Prefixed-SI", "stc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr3-Prefixed-32},${Dsp-24-u16} */ { M32C_INSN_STC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-absolute-Prefixed-SI", "stc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr3-Prefixed-32},${Dsp-24-u24} */ { M32C_INSN_STC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, "stc32.src-cr3-dst32-24-24-absolute-Prefixed-SI", "stc", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr2-32},$Dst32RnUnprefixedSI */ { M32C_INSN_STC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, "stc32.src-cr2-dst32-Rn-direct-Unprefixed-SI", "stc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr2-32},$Dst32AnUnprefixedSI */ { M32C_INSN_STC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, "stc32.src-cr2-dst32-An-direct-Unprefixed-SI", "stc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr2-32},[$Dst32AnUnprefixed] */ { M32C_INSN_STC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI, "stc32.src-cr2-dst32-An-indirect-Unprefixed-SI", "stc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr2-32},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_STC32_SRC_CR2_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-8-An-relative-Unprefixed-SI", "stc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr2-32},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_STC32_SRC_CR2_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-An-relative-Unprefixed-SI", "stc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr2-32},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_STC32_SRC_CR2_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-24-An-relative-Unprefixed-SI", "stc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr2-32},${Dsp-16-u8}[sb] */ { M32C_INSN_STC32_SRC_CR2_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-8-SB-relative-Unprefixed-SI", "stc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr2-32},${Dsp-16-u16}[sb] */ { M32C_INSN_STC32_SRC_CR2_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-SB-relative-Unprefixed-SI", "stc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr2-32},${Dsp-16-s8}[fb] */ { M32C_INSN_STC32_SRC_CR2_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-8-FB-relative-Unprefixed-SI", "stc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr2-32},${Dsp-16-s16}[fb] */ { M32C_INSN_STC32_SRC_CR2_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-FB-relative-Unprefixed-SI", "stc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr2-32},${Dsp-16-u16} */ { M32C_INSN_STC32_SRC_CR2_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-absolute-Unprefixed-SI", "stc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr2-32},${Dsp-16-u24} */ { M32C_INSN_STC32_SRC_CR2_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-24-absolute-Unprefixed-SI", "stc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr1-Prefixed-32},$Dst32RnPrefixedHI */ { M32C_INSN_STC32_SRC_CR1_DST32_RN_DIRECT_PREFIXED_HI, "stc32.src-cr1-dst32-Rn-direct-Prefixed-HI", "stc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr1-Prefixed-32},$Dst32AnPrefixedHI */ { M32C_INSN_STC32_SRC_CR1_DST32_AN_DIRECT_PREFIXED_HI, "stc32.src-cr1-dst32-An-direct-Prefixed-HI", "stc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr1-Prefixed-32},[$Dst32AnPrefixed] */ { M32C_INSN_STC32_SRC_CR1_DST32_AN_INDIRECT_PREFIXED_HI, "stc32.src-cr1-dst32-An-indirect-Prefixed-HI", "stc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr1-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_STC32_SRC_CR1_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-8-An-relative-Prefixed-HI", "stc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr1-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_STC32_SRC_CR1_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-An-relative-Prefixed-HI", "stc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr1-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_STC32_SRC_CR1_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-24-An-relative-Prefixed-HI", "stc", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr1-Prefixed-32},${Dsp-24-u8}[sb] */ { M32C_INSN_STC32_SRC_CR1_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-8-SB-relative-Prefixed-HI", "stc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr1-Prefixed-32},${Dsp-24-u16}[sb] */ { M32C_INSN_STC32_SRC_CR1_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-SB-relative-Prefixed-HI", "stc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr1-Prefixed-32},${Dsp-24-s8}[fb] */ { M32C_INSN_STC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-8-FB-relative-Prefixed-HI", "stc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr1-Prefixed-32},${Dsp-24-s16}[fb] */ { M32C_INSN_STC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-FB-relative-Prefixed-HI", "stc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr1-Prefixed-32},${Dsp-24-u16} */ { M32C_INSN_STC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-absolute-Prefixed-HI", "stc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc ${cr1-Prefixed-32},${Dsp-24-u24} */ { M32C_INSN_STC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI, "stc32.src-cr1-dst32-24-24-absolute-Prefixed-HI", "stc", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stc pc,$Dst16RnHI */ { M32C_INSN_STC16_PC_DST16_RN_DIRECT_HI, "stc16.pc-dst16-Rn-direct-HI", "stc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stc pc,$Dst16AnHI */ { M32C_INSN_STC16_PC_DST16_AN_DIRECT_HI, "stc16.pc-dst16-An-direct-HI", "stc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stc pc,[$Dst16An] */ { M32C_INSN_STC16_PC_DST16_AN_INDIRECT_HI, "stc16.pc-dst16-An-indirect-HI", "stc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stc pc,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_STC16_PC_DST16_16_8_AN_RELATIVE_HI, "stc16.pc-dst16-16-8-An-relative-HI", "stc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stc pc,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_STC16_PC_DST16_16_16_AN_RELATIVE_HI, "stc16.pc-dst16-16-16-An-relative-HI", "stc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stc pc,${Dsp-16-u8}[sb] */ { M32C_INSN_STC16_PC_DST16_16_8_SB_RELATIVE_HI, "stc16.pc-dst16-16-8-SB-relative-HI", "stc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stc pc,${Dsp-16-u16}[sb] */ { M32C_INSN_STC16_PC_DST16_16_16_SB_RELATIVE_HI, "stc16.pc-dst16-16-16-SB-relative-HI", "stc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stc pc,${Dsp-16-s8}[fb] */ { M32C_INSN_STC16_PC_DST16_16_8_FB_RELATIVE_HI, "stc16.pc-dst16-16-8-FB-relative-HI", "stc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stc pc,${Dsp-16-u16} */ { M32C_INSN_STC16_PC_DST16_16_16_ABSOLUTE_HI, "stc16.pc-dst16-16-16-absolute-HI", "stc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stc ${cr16},$Dst16RnHI */ { M32C_INSN_STC16_SRC_DST16_RN_DIRECT_HI, "stc16.src-dst16-Rn-direct-HI", "stc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stc ${cr16},$Dst16AnHI */ { M32C_INSN_STC16_SRC_DST16_AN_DIRECT_HI, "stc16.src-dst16-An-direct-HI", "stc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stc ${cr16},[$Dst16An] */ { M32C_INSN_STC16_SRC_DST16_AN_INDIRECT_HI, "stc16.src-dst16-An-indirect-HI", "stc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stc ${cr16},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_STC16_SRC_DST16_16_8_AN_RELATIVE_HI, "stc16.src-dst16-16-8-An-relative-HI", "stc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stc ${cr16},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_STC16_SRC_DST16_16_16_AN_RELATIVE_HI, "stc16.src-dst16-16-16-An-relative-HI", "stc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stc ${cr16},${Dsp-16-u8}[sb] */ { M32C_INSN_STC16_SRC_DST16_16_8_SB_RELATIVE_HI, "stc16.src-dst16-16-8-SB-relative-HI", "stc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stc ${cr16},${Dsp-16-u16}[sb] */ { M32C_INSN_STC16_SRC_DST16_16_16_SB_RELATIVE_HI, "stc16.src-dst16-16-16-SB-relative-HI", "stc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stc ${cr16},${Dsp-16-s8}[fb] */ { M32C_INSN_STC16_SRC_DST16_16_8_FB_RELATIVE_HI, "stc16.src-dst16-16-8-FB-relative-HI", "stc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stc ${cr16},${Dsp-16-u16} */ { M32C_INSN_STC16_SRC_DST16_16_16_ABSOLUTE_HI, "stc16.src-dst16-16-16-absolute-HI", "stc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ldc $Dst32RnPrefixedSI,${cr3-Prefixed-32} */ { M32C_INSN_LDC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, "ldc32.src-cr3-dst32-Rn-direct-Prefixed-SI", "ldc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc $Dst32AnPrefixedSI,${cr3-Prefixed-32} */ { M32C_INSN_LDC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, "ldc32.src-cr3-dst32-An-direct-Prefixed-SI", "ldc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc [$Dst32AnPrefixed],${cr3-Prefixed-32} */ { M32C_INSN_LDC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI, "ldc32.src-cr3-dst32-An-indirect-Prefixed-SI", "ldc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr3-Prefixed-32} */ { M32C_INSN_LDC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-8-An-relative-Prefixed-SI", "ldc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr3-Prefixed-32} */ { M32C_INSN_LDC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-An-relative-Prefixed-SI", "ldc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr3-Prefixed-32} */ { M32C_INSN_LDC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-24-An-relative-Prefixed-SI", "ldc", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-24-u8}[sb],${cr3-Prefixed-32} */ { M32C_INSN_LDC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-8-SB-relative-Prefixed-SI", "ldc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-24-u16}[sb],${cr3-Prefixed-32} */ { M32C_INSN_LDC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-SB-relative-Prefixed-SI", "ldc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-24-s8}[fb],${cr3-Prefixed-32} */ { M32C_INSN_LDC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-8-FB-relative-Prefixed-SI", "ldc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-24-s16}[fb],${cr3-Prefixed-32} */ { M32C_INSN_LDC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-FB-relative-Prefixed-SI", "ldc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-24-u16},${cr3-Prefixed-32} */ { M32C_INSN_LDC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-absolute-Prefixed-SI", "ldc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-24-u24},${cr3-Prefixed-32} */ { M32C_INSN_LDC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-24-absolute-Prefixed-SI", "ldc", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc $Dst32RnUnprefixedSI,${cr2-32} */ { M32C_INSN_LDC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, "ldc32.src-cr2-dst32-Rn-direct-Unprefixed-SI", "ldc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc $Dst32AnUnprefixedSI,${cr2-32} */ { M32C_INSN_LDC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, "ldc32.src-cr2-dst32-An-direct-Unprefixed-SI", "ldc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc [$Dst32AnUnprefixed],${cr2-32} */ { M32C_INSN_LDC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI, "ldc32.src-cr2-dst32-An-indirect-Unprefixed-SI", "ldc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-16-u8}[$Dst32AnUnprefixed],${cr2-32} */ { M32C_INSN_LDC32_SRC_CR2_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-8-An-relative-Unprefixed-SI", "ldc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-16-u16}[$Dst32AnUnprefixed],${cr2-32} */ { M32C_INSN_LDC32_SRC_CR2_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-An-relative-Unprefixed-SI", "ldc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-16-u24}[$Dst32AnUnprefixed],${cr2-32} */ { M32C_INSN_LDC32_SRC_CR2_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-24-An-relative-Unprefixed-SI", "ldc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-16-u8}[sb],${cr2-32} */ { M32C_INSN_LDC32_SRC_CR2_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-8-SB-relative-Unprefixed-SI", "ldc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-16-u16}[sb],${cr2-32} */ { M32C_INSN_LDC32_SRC_CR2_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-SB-relative-Unprefixed-SI", "ldc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-16-s8}[fb],${cr2-32} */ { M32C_INSN_LDC32_SRC_CR2_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-8-FB-relative-Unprefixed-SI", "ldc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-16-s16}[fb],${cr2-32} */ { M32C_INSN_LDC32_SRC_CR2_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-FB-relative-Unprefixed-SI", "ldc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-16-u16},${cr2-32} */ { M32C_INSN_LDC32_SRC_CR2_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-absolute-Unprefixed-SI", "ldc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-16-u24},${cr2-32} */ { M32C_INSN_LDC32_SRC_CR2_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-24-absolute-Unprefixed-SI", "ldc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc $Dst32RnPrefixedHI,${cr1-Prefixed-32} */ { M32C_INSN_LDC32_SRC_CR1_DST32_RN_DIRECT_PREFIXED_HI, "ldc32.src-cr1-dst32-Rn-direct-Prefixed-HI", "ldc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc $Dst32AnPrefixedHI,${cr1-Prefixed-32} */ { M32C_INSN_LDC32_SRC_CR1_DST32_AN_DIRECT_PREFIXED_HI, "ldc32.src-cr1-dst32-An-direct-Prefixed-HI", "ldc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc [$Dst32AnPrefixed],${cr1-Prefixed-32} */ { M32C_INSN_LDC32_SRC_CR1_DST32_AN_INDIRECT_PREFIXED_HI, "ldc32.src-cr1-dst32-An-indirect-Prefixed-HI", "ldc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr1-Prefixed-32} */ { M32C_INSN_LDC32_SRC_CR1_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-8-An-relative-Prefixed-HI", "ldc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr1-Prefixed-32} */ { M32C_INSN_LDC32_SRC_CR1_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-An-relative-Prefixed-HI", "ldc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr1-Prefixed-32} */ { M32C_INSN_LDC32_SRC_CR1_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-24-An-relative-Prefixed-HI", "ldc", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-24-u8}[sb],${cr1-Prefixed-32} */ { M32C_INSN_LDC32_SRC_CR1_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-8-SB-relative-Prefixed-HI", "ldc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-24-u16}[sb],${cr1-Prefixed-32} */ { M32C_INSN_LDC32_SRC_CR1_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-SB-relative-Prefixed-HI", "ldc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-24-s8}[fb],${cr1-Prefixed-32} */ { M32C_INSN_LDC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-8-FB-relative-Prefixed-HI", "ldc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-24-s16}[fb],${cr1-Prefixed-32} */ { M32C_INSN_LDC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-FB-relative-Prefixed-HI", "ldc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-24-u16},${cr1-Prefixed-32} */ { M32C_INSN_LDC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-absolute-Prefixed-HI", "ldc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc ${Dsp-24-u24},${cr1-Prefixed-32} */ { M32C_INSN_LDC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-24-absolute-Prefixed-HI", "ldc", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc $Dst16RnHI,${cr16} */ { M32C_INSN_LDC16_DST_DST16_RN_DIRECT_HI, "ldc16.dst-dst16-Rn-direct-HI", "ldc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ldc $Dst16AnHI,${cr16} */ { M32C_INSN_LDC16_DST_DST16_AN_DIRECT_HI, "ldc16.dst-dst16-An-direct-HI", "ldc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ldc [$Dst16An],${cr16} */ { M32C_INSN_LDC16_DST_DST16_AN_INDIRECT_HI, "ldc16.dst-dst16-An-indirect-HI", "ldc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ldc ${Dsp-16-u8}[$Dst16An],${cr16} */ { M32C_INSN_LDC16_DST_DST16_16_8_AN_RELATIVE_HI, "ldc16.dst-dst16-16-8-An-relative-HI", "ldc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ldc ${Dsp-16-u16}[$Dst16An],${cr16} */ { M32C_INSN_LDC16_DST_DST16_16_16_AN_RELATIVE_HI, "ldc16.dst-dst16-16-16-An-relative-HI", "ldc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ldc ${Dsp-16-u8}[sb],${cr16} */ { M32C_INSN_LDC16_DST_DST16_16_8_SB_RELATIVE_HI, "ldc16.dst-dst16-16-8-SB-relative-HI", "ldc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ldc ${Dsp-16-u16}[sb],${cr16} */ { M32C_INSN_LDC16_DST_DST16_16_16_SB_RELATIVE_HI, "ldc16.dst-dst16-16-16-SB-relative-HI", "ldc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ldc ${Dsp-16-s8}[fb],${cr16} */ { M32C_INSN_LDC16_DST_DST16_16_8_FB_RELATIVE_HI, "ldc16.dst-dst16-16-8-FB-relative-HI", "ldc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ldc ${Dsp-16-u16},${cr16} */ { M32C_INSN_LDC16_DST_DST16_16_16_ABSOLUTE_HI, "ldc16.dst-dst16-16-16-absolute-HI", "ldc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_JSRI32_A_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "jsri32.a-dst32-16-24-An-relative-Unprefixed-SI", "jsri.w", 40, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsri.w ${Dsp-16-u24} */ { M32C_INSN_JSRI32_A_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "jsri32.a-dst32-16-24-absolute-Unprefixed-SI", "jsri.w", 40, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsri.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "jsri.a", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsri.a ${Dsp-16-u16}[sb] */ { M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "jsri.a", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsri.a ${Dsp-16-s16}[fb] */ { M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "jsri.a", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsri.a ${Dsp-16-u16} */ { M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "jsri.a", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsri.a ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_AN_RELATIVE_SI, "jsri16a-dst16-16-16-SI-dst16-16-16-An-relative-SI", "jsri.a", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jsri.a ${Dsp-16-u16}[sb] */ { M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_SB_RELATIVE_SI, "jsri16a-dst16-16-16-SI-dst16-16-16-SB-relative-SI", "jsri.a", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jsri.a ${Dsp-16-u16} */ { M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_ABSOLUTE_SI, "jsri16a-dst16-16-16-SI-dst16-16-16-absolute-SI", "jsri.a", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jsri.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-8-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "jsri.a", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsri.a ${Dsp-16-u8}[sb] */ { M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-8-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "jsri.a", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsri.a ${Dsp-16-s8}[fb] */ { M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-8-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "jsri.a", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsri.a ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_AN_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-An-relative-SI", "jsri.a", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jsri.a ${Dsp-16-u8}[sb] */ { M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_SB_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-SB-relative-SI", "jsri.a", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jsri.a ${Dsp-16-s8}[fb] */ { M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_FB_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-FB-relative-SI", "jsri.a", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jsri.a $Dst32RnUnprefixedSI */ { M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "jsri.a", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsri.a $Dst32AnUnprefixedSI */ { M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "jsri.a", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsri.a [$Dst32AnUnprefixed] */ { M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "jsri.a", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsri.a $Dst16RnSI */ { M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_RN_DIRECT_SI, "jsri16a-dst16-basic-SI-dst16-Rn-direct-SI", "jsri.a", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jsri.a $Dst16AnSI */ { M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_DIRECT_SI, "jsri16a-dst16-basic-SI-dst16-An-direct-SI", "jsri.a", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jsri.a [$Dst16An] */ { M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_INDIRECT_SI, "jsri16a-dst16-basic-SI-dst16-An-indirect-SI", "jsri.a", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_JSRI32_W_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "jsri32.w-dst32-16-24-An-relative-Unprefixed-HI", "jsri.w", 40, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsri.w ${Dsp-16-u24} */ { M32C_INSN_JSRI32_W_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "jsri32.w-dst32-16-24-absolute-Unprefixed-HI", "jsri.w", 40, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsri.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "jsri.w", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsri.w ${Dsp-16-u16}[sb] */ { M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "jsri.w", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsri.w ${Dsp-16-s16}[fb] */ { M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "jsri.w", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsri.w ${Dsp-16-u16} */ { M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "jsri.w", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsri.w ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_AN_RELATIVE_HI, "jsri16w-dst16-16-16-HI-dst16-16-16-An-relative-HI", "jsri.w", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jsri.w ${Dsp-16-u16}[sb] */ { M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_SB_RELATIVE_HI, "jsri16w-dst16-16-16-HI-dst16-16-16-SB-relative-HI", "jsri.w", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jsri.w ${Dsp-16-u16} */ { M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_ABSOLUTE_HI, "jsri16w-dst16-16-16-HI-dst16-16-16-absolute-HI", "jsri.w", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jsri.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "jsri.w", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsri.w ${Dsp-16-u8}[sb] */ { M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "jsri.w", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsri.w ${Dsp-16-s8}[fb] */ { M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "jsri.w", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsri.w ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_AN_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-An-relative-HI", "jsri.w", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jsri.w ${Dsp-16-u8}[sb] */ { M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_SB_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-SB-relative-HI", "jsri.w", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jsri.w ${Dsp-16-s8}[fb] */ { M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_FB_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-FB-relative-HI", "jsri.w", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jsri.w $Dst32RnUnprefixedHI */ { M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "jsri.w", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsri.w $Dst32AnUnprefixedHI */ { M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "jsri.w", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsri.w [$Dst32AnUnprefixed] */ { M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "jsri.w", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsri.w $Dst16RnHI */ { M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_RN_DIRECT_HI, "jsri16w-dst16-basic-HI-dst16-Rn-direct-HI", "jsri.w", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jsri.w $Dst16AnHI */ { M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_DIRECT_HI, "jsri16w-dst16-basic-HI-dst16-An-direct-HI", "jsri.w", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jsri.w [$Dst16An] */ { M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_INDIRECT_HI, "jsri16w-dst16-basic-HI-dst16-An-indirect-HI", "jsri.w", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jmpi.a $Dst32RnUnprefixedSI */ { M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "jmpi.a", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmpi.a $Dst32AnUnprefixedSI */ { M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "jmpi.a", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmpi.a [$Dst32AnUnprefixed] */ { M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "jmpi.a", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmpi.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "jmpi.a", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmpi.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "jmpi.a", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmpi.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "jmpi.a", 40, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmpi.a ${Dsp-16-u8}[sb] */ { M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "jmpi.a", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmpi.a ${Dsp-16-u16}[sb] */ { M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "jmpi.a", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmpi.a ${Dsp-16-s8}[fb] */ { M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "jmpi.a", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmpi.a ${Dsp-16-s16}[fb] */ { M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "jmpi.a", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmpi.a ${Dsp-16-u16} */ { M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "jmpi.a", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmpi.a ${Dsp-16-u24} */ { M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "jmpi.a", 40, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmpi.a $Dst16RnSI */ { M32C_INSN_JMPI16_A_16_DST16_RN_DIRECT_SI, "jmpi16.a-16-dst16-Rn-direct-SI", "jmpi.a", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jmpi.a $Dst16AnSI */ { M32C_INSN_JMPI16_A_16_DST16_AN_DIRECT_SI, "jmpi16.a-16-dst16-An-direct-SI", "jmpi.a", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jmpi.a [$Dst16An] */ { M32C_INSN_JMPI16_A_16_DST16_AN_INDIRECT_SI, "jmpi16.a-16-dst16-An-indirect-SI", "jmpi.a", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jmpi.a ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_JMPI16_A_16_DST16_16_8_AN_RELATIVE_SI, "jmpi16.a-16-dst16-16-8-An-relative-SI", "jmpi.a", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jmpi.a ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_JMPI16_A_16_DST16_16_16_AN_RELATIVE_SI, "jmpi16.a-16-dst16-16-16-An-relative-SI", "jmpi.a", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jmpi.a ${Dsp-16-u8}[sb] */ { M32C_INSN_JMPI16_A_16_DST16_16_8_SB_RELATIVE_SI, "jmpi16.a-16-dst16-16-8-SB-relative-SI", "jmpi.a", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jmpi.a ${Dsp-16-u16}[sb] */ { M32C_INSN_JMPI16_A_16_DST16_16_16_SB_RELATIVE_SI, "jmpi16.a-16-dst16-16-16-SB-relative-SI", "jmpi.a", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jmpi.a ${Dsp-16-s8}[fb] */ { M32C_INSN_JMPI16_A_16_DST16_16_8_FB_RELATIVE_SI, "jmpi16.a-16-dst16-16-8-FB-relative-SI", "jmpi.a", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jmpi.a ${Dsp-16-u16} */ { M32C_INSN_JMPI16_A_16_DST16_16_16_ABSOLUTE_SI, "jmpi16.a-16-dst16-16-16-absolute-SI", "jmpi.a", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jmpi.w $Dst32RnUnprefixedHI */ { M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "jmpi.w", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmpi.w $Dst32AnUnprefixedHI */ { M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "jmpi.w", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmpi.w [$Dst32AnUnprefixed] */ { M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "jmpi.w", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmpi.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "jmpi.w", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmpi.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "jmpi.w", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmpi.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "jmpi.w", 40, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmpi.w ${Dsp-16-u8}[sb] */ { M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "jmpi.w", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmpi.w ${Dsp-16-u16}[sb] */ { M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "jmpi.w", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmpi.w ${Dsp-16-s8}[fb] */ { M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "jmpi.w", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmpi.w ${Dsp-16-s16}[fb] */ { M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "jmpi.w", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmpi.w ${Dsp-16-u16} */ { M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "jmpi.w", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmpi.w ${Dsp-16-u24} */ { M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "jmpi.w", 40, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmpi.w $Dst16RnHI */ { M32C_INSN_JMPI16_W_16_DST16_RN_DIRECT_HI, "jmpi16.w-16-dst16-Rn-direct-HI", "jmpi.w", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jmpi.w $Dst16AnHI */ { M32C_INSN_JMPI16_W_16_DST16_AN_DIRECT_HI, "jmpi16.w-16-dst16-An-direct-HI", "jmpi.w", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jmpi.w [$Dst16An] */ { M32C_INSN_JMPI16_W_16_DST16_AN_INDIRECT_HI, "jmpi16.w-16-dst16-An-indirect-HI", "jmpi.w", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jmpi.w ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_JMPI16_W_16_DST16_16_8_AN_RELATIVE_HI, "jmpi16.w-16-dst16-16-8-An-relative-HI", "jmpi.w", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jmpi.w ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_JMPI16_W_16_DST16_16_16_AN_RELATIVE_HI, "jmpi16.w-16-dst16-16-16-An-relative-HI", "jmpi.w", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jmpi.w ${Dsp-16-u8}[sb] */ { M32C_INSN_JMPI16_W_16_DST16_16_8_SB_RELATIVE_HI, "jmpi16.w-16-dst16-16-8-SB-relative-HI", "jmpi.w", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jmpi.w ${Dsp-16-u16}[sb] */ { M32C_INSN_JMPI16_W_16_DST16_16_16_SB_RELATIVE_HI, "jmpi16.w-16-dst16-16-16-SB-relative-HI", "jmpi.w", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jmpi.w ${Dsp-16-s8}[fb] */ { M32C_INSN_JMPI16_W_16_DST16_16_8_FB_RELATIVE_HI, "jmpi16.w-16-dst16-16-8-FB-relative-HI", "jmpi.w", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jmpi.w ${Dsp-16-u16} */ { M32C_INSN_JMPI16_W_16_DST16_16_16_ABSOLUTE_HI, "jmpi16.w-16-dst16-16-16-absolute-HI", "jmpi.w", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* indexws.w $Dst32RnUnprefixedHI */ { M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexws.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexws.w $Dst32AnUnprefixedHI */ { M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexws.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexws.w [$Dst32AnUnprefixed] */ { M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexws.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexws.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexws.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexws.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexws.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexws.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexws.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexws.w ${Dsp-16-u8}[sb] */ { M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexws.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexws.w ${Dsp-16-u16}[sb] */ { M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexws.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexws.w ${Dsp-16-s8}[fb] */ { M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexws.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexws.w ${Dsp-16-s16}[fb] */ { M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexws.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexws.w ${Dsp-16-u16} */ { M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexws.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexws.w ${Dsp-16-u24} */ { M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexws.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexws.b $Dst32RnUnprefixedQI */ { M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexws.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexws.b $Dst32AnUnprefixedQI */ { M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexws.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexws.b [$Dst32AnUnprefixed] */ { M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexws.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexws.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexws.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexws.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexws.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexws.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexws.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexws.b ${Dsp-16-u8}[sb] */ { M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexws.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexws.b ${Dsp-16-u16}[sb] */ { M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexws.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexws.b ${Dsp-16-s8}[fb] */ { M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexws.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexws.b ${Dsp-16-s16}[fb] */ { M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexws.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexws.b ${Dsp-16-u16} */ { M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexws.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexws.b ${Dsp-16-u24} */ { M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexws.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexwd.w $Dst32RnUnprefixedHI */ { M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexwd.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexwd.w $Dst32AnUnprefixedHI */ { M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexwd.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexwd.w [$Dst32AnUnprefixed] */ { M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexwd.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexwd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexwd.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexwd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexwd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexwd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexwd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexwd.w ${Dsp-16-u8}[sb] */ { M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexwd.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexwd.w ${Dsp-16-u16}[sb] */ { M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexwd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexwd.w ${Dsp-16-s8}[fb] */ { M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexwd.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexwd.w ${Dsp-16-s16}[fb] */ { M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexwd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexwd.w ${Dsp-16-u16} */ { M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexwd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexwd.w ${Dsp-16-u24} */ { M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexwd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexwd.b $Dst32RnUnprefixedQI */ { M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexwd.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexwd.b $Dst32AnUnprefixedQI */ { M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexwd.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexwd.b [$Dst32AnUnprefixed] */ { M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexwd.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexwd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexwd.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexwd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexwd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexwd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexwd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexwd.b ${Dsp-16-u8}[sb] */ { M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexwd.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexwd.b ${Dsp-16-u16}[sb] */ { M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexwd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexwd.b ${Dsp-16-s8}[fb] */ { M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexwd.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexwd.b ${Dsp-16-s16}[fb] */ { M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexwd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexwd.b ${Dsp-16-u16} */ { M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexwd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexwd.b ${Dsp-16-u24} */ { M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexwd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexw.w $Dst32RnUnprefixedHI */ { M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexw.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexw.w $Dst32AnUnprefixedHI */ { M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexw.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexw.w [$Dst32AnUnprefixed] */ { M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexw.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexw.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexw.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexw.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexw.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexw.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexw.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexw.w ${Dsp-16-u8}[sb] */ { M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexw.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexw.w ${Dsp-16-u16}[sb] */ { M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexw.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexw.w ${Dsp-16-s8}[fb] */ { M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexw.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexw.w ${Dsp-16-s16}[fb] */ { M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexw.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexw.w ${Dsp-16-u16} */ { M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexw.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexw.w ${Dsp-16-u24} */ { M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexw.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexw.b $Dst32RnUnprefixedQI */ { M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexw.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexw.b $Dst32AnUnprefixedQI */ { M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexw.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexw.b [$Dst32AnUnprefixed] */ { M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexw.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexw.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexw.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexw.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexw.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexw.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexw.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexw.b ${Dsp-16-u8}[sb] */ { M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexw.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexw.b ${Dsp-16-u16}[sb] */ { M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexw.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexw.b ${Dsp-16-s8}[fb] */ { M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexw.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexw.b ${Dsp-16-s16}[fb] */ { M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexw.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexw.b ${Dsp-16-u16} */ { M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexw.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexw.b ${Dsp-16-u24} */ { M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexw.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexls.w $Dst32RnUnprefixedHI */ { M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexls.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexls.w $Dst32AnUnprefixedHI */ { M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexls.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexls.w [$Dst32AnUnprefixed] */ { M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexls.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexls.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexls.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexls.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexls.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexls.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexls.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexls.w ${Dsp-16-u8}[sb] */ { M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexls.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexls.w ${Dsp-16-u16}[sb] */ { M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexls.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexls.w ${Dsp-16-s8}[fb] */ { M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexls.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexls.w ${Dsp-16-s16}[fb] */ { M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexls.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexls.w ${Dsp-16-u16} */ { M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexls.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexls.w ${Dsp-16-u24} */ { M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexls.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexls.b $Dst32RnUnprefixedQI */ { M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexls.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexls.b $Dst32AnUnprefixedQI */ { M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexls.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexls.b [$Dst32AnUnprefixed] */ { M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexls.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexls.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexls.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexls.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexls.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexls.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexls.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexls.b ${Dsp-16-u8}[sb] */ { M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexls.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexls.b ${Dsp-16-u16}[sb] */ { M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexls.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexls.b ${Dsp-16-s8}[fb] */ { M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexls.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexls.b ${Dsp-16-s16}[fb] */ { M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexls.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexls.b ${Dsp-16-u16} */ { M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexls.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexls.b ${Dsp-16-u24} */ { M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexls.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexld.w $Dst32RnUnprefixedHI */ { M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexld.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexld.w $Dst32AnUnprefixedHI */ { M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexld.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexld.w [$Dst32AnUnprefixed] */ { M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexld.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexld.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexld.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexld.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexld.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexld.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexld.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexld.w ${Dsp-16-u8}[sb] */ { M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexld.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexld.w ${Dsp-16-u16}[sb] */ { M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexld.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexld.w ${Dsp-16-s8}[fb] */ { M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexld.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexld.w ${Dsp-16-s16}[fb] */ { M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexld.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexld.w ${Dsp-16-u16} */ { M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexld.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexld.w ${Dsp-16-u24} */ { M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexld.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexld.b $Dst32RnUnprefixedQI */ { M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexld.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexld.b $Dst32AnUnprefixedQI */ { M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexld.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexld.b [$Dst32AnUnprefixed] */ { M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexld.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexld.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexld.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexld.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexld.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexld.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexld.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexld.b ${Dsp-16-u8}[sb] */ { M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexld.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexld.b ${Dsp-16-u16}[sb] */ { M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexld.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexld.b ${Dsp-16-s8}[fb] */ { M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexld.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexld.b ${Dsp-16-s16}[fb] */ { M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexld.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexld.b ${Dsp-16-u16} */ { M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexld.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexld.b ${Dsp-16-u24} */ { M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexld.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexl.w $Dst32RnUnprefixedHI */ { M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexl.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexl.w $Dst32AnUnprefixedHI */ { M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexl.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexl.w [$Dst32AnUnprefixed] */ { M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexl.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexl.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexl.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexl.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexl.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexl.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexl.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexl.w ${Dsp-16-u8}[sb] */ { M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexl.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexl.w ${Dsp-16-u16}[sb] */ { M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexl.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexl.w ${Dsp-16-s8}[fb] */ { M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexl.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexl.w ${Dsp-16-s16}[fb] */ { M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexl.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexl.w ${Dsp-16-u16} */ { M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexl.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexl.w ${Dsp-16-u24} */ { M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexl.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexl.b $Dst32RnUnprefixedQI */ { M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexl.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexl.b $Dst32AnUnprefixedQI */ { M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexl.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexl.b [$Dst32AnUnprefixed] */ { M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexl.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexl.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexl.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexl.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexl.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexl.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexl.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexl.b ${Dsp-16-u8}[sb] */ { M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexl.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexl.b ${Dsp-16-u16}[sb] */ { M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexl.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexl.b ${Dsp-16-s8}[fb] */ { M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexl.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexl.b ${Dsp-16-s16}[fb] */ { M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexl.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexl.b ${Dsp-16-u16} */ { M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexl.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexl.b ${Dsp-16-u24} */ { M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexl.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbs.w $Dst32RnUnprefixedHI */ { M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexbs.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbs.w $Dst32AnUnprefixedHI */ { M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexbs.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbs.w [$Dst32AnUnprefixed] */ { M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexbs.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexbs.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexbs.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexbs.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbs.w ${Dsp-16-u8}[sb] */ { M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexbs.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbs.w ${Dsp-16-u16}[sb] */ { M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexbs.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbs.w ${Dsp-16-s8}[fb] */ { M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexbs.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbs.w ${Dsp-16-s16}[fb] */ { M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexbs.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbs.w ${Dsp-16-u16} */ { M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexbs.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbs.w ${Dsp-16-u24} */ { M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexbs.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbs.b $Dst32RnUnprefixedQI */ { M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexbs.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbs.b $Dst32AnUnprefixedQI */ { M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexbs.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbs.b [$Dst32AnUnprefixed] */ { M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexbs.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexbs.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexbs.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexbs.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbs.b ${Dsp-16-u8}[sb] */ { M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexbs.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbs.b ${Dsp-16-u16}[sb] */ { M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexbs.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbs.b ${Dsp-16-s8}[fb] */ { M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexbs.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbs.b ${Dsp-16-s16}[fb] */ { M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexbs.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbs.b ${Dsp-16-u16} */ { M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexbs.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbs.b ${Dsp-16-u24} */ { M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexbs.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbd.w $Dst32RnUnprefixedHI */ { M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexbd.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbd.w $Dst32AnUnprefixedHI */ { M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexbd.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbd.w [$Dst32AnUnprefixed] */ { M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexbd.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexbd.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexbd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexbd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbd.w ${Dsp-16-u8}[sb] */ { M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexbd.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbd.w ${Dsp-16-u16}[sb] */ { M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexbd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbd.w ${Dsp-16-s8}[fb] */ { M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexbd.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbd.w ${Dsp-16-s16}[fb] */ { M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexbd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbd.w ${Dsp-16-u16} */ { M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexbd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbd.w ${Dsp-16-u24} */ { M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexbd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbd.b $Dst32RnUnprefixedQI */ { M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexbd.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbd.b $Dst32AnUnprefixedQI */ { M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexbd.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbd.b [$Dst32AnUnprefixed] */ { M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexbd.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexbd.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexbd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexbd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbd.b ${Dsp-16-u8}[sb] */ { M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexbd.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbd.b ${Dsp-16-u16}[sb] */ { M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexbd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbd.b ${Dsp-16-s8}[fb] */ { M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexbd.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbd.b ${Dsp-16-s16}[fb] */ { M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexbd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbd.b ${Dsp-16-u16} */ { M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexbd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexbd.b ${Dsp-16-u24} */ { M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexbd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexb.w $Dst32RnUnprefixedHI */ { M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexb.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexb.w $Dst32AnUnprefixedHI */ { M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexb.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexb.w [$Dst32AnUnprefixed] */ { M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexb.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexb.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexb.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexb.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexb.w ${Dsp-16-u8}[sb] */ { M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexb.w ${Dsp-16-u16}[sb] */ { M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexb.w ${Dsp-16-s8}[fb] */ { M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexb.w ${Dsp-16-s16}[fb] */ { M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexb.w ${Dsp-16-u16} */ { M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexb.w ${Dsp-16-u24} */ { M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexb.b $Dst32RnUnprefixedQI */ { M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexb.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexb.b $Dst32AnUnprefixedQI */ { M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexb.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexb.b [$Dst32AnUnprefixed] */ { M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexb.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexb.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexb.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexb.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexb.b ${Dsp-16-u8}[sb] */ { M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexb.b ${Dsp-16-u16}[sb] */ { M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexb.b ${Dsp-16-s8}[fb] */ { M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexb.b ${Dsp-16-s16}[fb] */ { M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexb.b ${Dsp-16-u16} */ { M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* indexb.b ${Dsp-16-u24} */ { M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.w $Dst32RnUnprefixedHI */ { M32C_INSN_INC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "inc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.w $Dst32AnUnprefixedHI */ { M32C_INSN_INC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "inc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.w [$Dst32AnUnprefixed] */ { M32C_INSN_INC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "inc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "inc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "inc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "inc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.w ${Dsp-16-u8}[sb] */ { M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "inc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.w ${Dsp-16-u16}[sb] */ { M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "inc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.w ${Dsp-16-s8}[fb] */ { M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "inc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.w ${Dsp-16-s16}[fb] */ { M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "inc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.w ${Dsp-16-u16} */ { M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "inc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.w ${Dsp-16-u24} */ { M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "inc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.b $Dst32RnUnprefixedQI */ { M32C_INSN_INC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "inc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.b $Dst32AnUnprefixedQI */ { M32C_INSN_INC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "inc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.b [$Dst32AnUnprefixed] */ { M32C_INSN_INC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "inc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "inc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "inc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "inc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.b ${Dsp-16-u8}[sb] */ { M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "inc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.b ${Dsp-16-u16}[sb] */ { M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "inc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.b ${Dsp-16-s8}[fb] */ { M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "inc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.b ${Dsp-16-s16}[fb] */ { M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "inc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.b ${Dsp-16-u16} */ { M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "inc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.b ${Dsp-16-u24} */ { M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "inc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.b r0l */ { M32C_INSN_INC16_B_DST16_3_S_R0L_DIRECT_QI, "inc16.b-dst16-3-S-R0l-direct-QI", "inc.b", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* inc.b r0h */ { M32C_INSN_INC16_B_DST16_3_S_R0H_DIRECT_QI, "inc16.b-dst16-3-S-R0h-direct-QI", "inc.b", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* inc.b ${Dsp-8-u8}[sb] */ { M32C_INSN_INC16_B_DST16_3_S_8_8_SB_RELATIVE_QI, "inc16.b-dst16-3-S-8-8-SB-relative-QI", "inc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* inc.b ${Dsp-8-s8}[fb] */ { M32C_INSN_INC16_B_DST16_3_S_8_8_FB_RELATIVE_QI, "inc16.b-dst16-3-S-8-8-FB-relative-QI", "inc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* inc.b ${Dsp-8-u16} */ { M32C_INSN_INC16_B_DST16_3_S_8_16_ABSOLUTE_QI, "inc16.b-dst16-3-S-8-16-absolute-QI", "inc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */ { M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */ { M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "sub.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "sub.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "sub.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "sub.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "sub.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "sub.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "sub.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "sub.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "sub.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "sub.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "sub.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "sub.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ { M32C_INSN_SUB32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "sub32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ { M32C_INSN_SUB32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "sub32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${S} #${Imm-24-HI},${Dsp-8-u16} */ { M32C_INSN_SUB32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "sub32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${S} #${Imm-8-HI},r0 */ { M32C_INSN_SUB32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "sub32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ { M32C_INSN_SUB32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "sub32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ { M32C_INSN_SUB32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "sub32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${S} #${Imm-24-QI},${Dsp-8-u16} */ { M32C_INSN_SUB32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "sub32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${S} #${Imm-8-QI},r0l */ { M32C_INSN_SUB32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "sub32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "sub.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */ { M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */ { M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "sub.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */ { M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */ { M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */ { M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */ { M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} #${Imm-32-SI},${Dsp-16-u16} */ { M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.l${G} #${Imm-40-SI},${Dsp-16-u24} */ { M32C_INSN_SUB32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${S} ${SrcDst16-r0l-r0h-S-normal} */ { M32C_INSN_SUB16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "sub16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "sub.b", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */ { M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "sub16.b.S-src2-src16-2-S-8-SB-relative-QI", "sub.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */ { M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "sub16.b.S-src2-src16-2-S-8-FB-relative-QI", "sub.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */ { M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "sub16.b.S-src2-src16-2-S-16-absolute-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ { M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ { M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "sub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "sub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "sub.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "sub.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "sub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "sub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "sub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "sub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "sub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "sub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "sub.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "sub.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ { M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ { M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "sub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "sub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "sub.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "sub.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "sub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "sub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "sub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "sub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "sub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "sub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "sub.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "sub.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16},$Dst16RnHI */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16},$Dst16AnHI */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} $Src16RnHI,$Dst16RnHI */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "sub.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} $Src16AnHI,$Dst16RnHI */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "sub.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} [$Src16An],$Dst16RnHI */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "sub.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} $Src16RnHI,$Dst16AnHI */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "sub.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} $Src16AnHI,$Dst16AnHI */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "sub.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} [$Src16An],$Dst16AnHI */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "sub.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} $Src16RnHI,[$Dst16An] */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "sub.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} $Src16AnHI,[$Dst16An] */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "sub.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} [$Src16An],[$Dst16An] */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "sub.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "sub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} $Src16RnHI,${Dsp-16-u16} */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} $Src16AnHI,${Dsp-16-u16} */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16},$Dst16RnQI */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16},$Dst16AnQI */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} $Src16RnQI,$Dst16RnQI */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "sub.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} $Src16AnQI,$Dst16RnQI */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "sub.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} [$Src16An],$Dst16RnQI */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "sub.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} $Src16RnQI,$Dst16AnQI */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "sub.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} $Src16AnQI,$Dst16AnQI */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "sub.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} [$Src16An],$Dst16AnQI */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "sub.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} $Src16RnQI,[$Dst16An] */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "sub.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} $Src16AnQI,[$Dst16An] */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "sub.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} [$Src16An],[$Dst16An] */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "sub.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} $Src16RnQI,${Dsp-16-u16} */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} $Src16AnQI,${Dsp-16-u16} */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${S} #${Imm-8-QI},r0l */ { M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "sub16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "sub.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${S} #${Imm-8-QI},r0h */ { M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "sub16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "sub.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "sub16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "sub16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${S} #${Imm-8-QI},${Dsp-16-u16} */ { M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "sub16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ { M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ { M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ { M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} #${Imm-40-HI},${Dsp-16-u24} */ { M32C_INSN_SUB32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ { M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ { M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_SUB32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.b${G} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_SUB32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sub.w${G} #${Imm-16-HI},$Dst16RnHI */ { M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "sub16.w-imm-G-basic-dst16-Rn-direct-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} #${Imm-16-HI},$Dst16AnHI */ { M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "sub16.w-imm-G-basic-dst16-An-direct-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} #${Imm-16-HI},[$Dst16An] */ { M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "sub16.w-imm-G-basic-dst16-An-indirect-HI", "sub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "sub16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "sub16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "sub16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "sub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "sub16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "sub16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "sub16.w-imm-G-16-16-dst16-16-16-absolute-HI", "sub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} #${Imm-16-QI},$Dst16RnQI */ { M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "sub16.b-imm-G-basic-dst16-Rn-direct-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} #${Imm-16-QI},$Dst16AnQI */ { M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "sub16.b-imm-G-basic-dst16-An-direct-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} #${Imm-16-QI},[$Dst16An] */ { M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "sub16.b-imm-G-basic-dst16-An-indirect-QI", "sub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "sub16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "sub16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "sub16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "sub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "sub16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "sub16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "sub16.b-imm-G-16-16-dst16-16-16-absolute-QI", "sub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ { M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ { M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsub.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsub.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsub.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsub.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsub.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsub.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsub.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsub.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsub.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsub.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsub.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsub.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ { M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ { M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsub.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsub.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsub.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsub.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsub.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsub.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsub.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsub.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsub.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsub.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsub.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsub.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ { M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ { M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dsub.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ { M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ { M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ { M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ { M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16} */ { M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24} */ { M32C_INSN_DSUB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ { M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ { M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dsub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dsub.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ { M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ { M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ { M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ { M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16} */ { M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSUB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24} */ { M32C_INSN_DSUB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ { M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ { M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsbb.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsbb.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsbb.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsbb.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ { M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ { M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsbb.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsbb.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsbb.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsbb.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsbb.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ { M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ { M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ { M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ { M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ { M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ { M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */ { M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */ { M32C_INSN_DSBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ { M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ { M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dsbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ { M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ { M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ { M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ { M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */ { M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DSBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */ { M32C_INSN_DSBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.l $Dst32RnPrefixedSI */ { M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-Rn-direct-Prefixed-SI", "divx.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.l $Dst32AnPrefixedSI */ { M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-An-direct-Prefixed-SI", "divx.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.l [$Dst32AnPrefixed] */ { M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-An-indirect-Prefixed-SI", "divx.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.l ${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-8-An-relative-Prefixed-SI", "divx.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.l ${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-An-relative-Prefixed-SI", "divx.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.l ${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-24-An-relative-Prefixed-SI", "divx.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.l ${Dsp-24-u8}[sb] */ { M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-8-SB-relative-Prefixed-SI", "divx.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.l ${Dsp-24-u16}[sb] */ { M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-SB-relative-Prefixed-SI", "divx.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.l ${Dsp-24-s8}[fb] */ { M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-8-FB-relative-Prefixed-SI", "divx.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.l ${Dsp-24-s16}[fb] */ { M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-FB-relative-Prefixed-SI", "divx.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.l ${Dsp-24-u16} */ { M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-absolute-Prefixed-SI", "divx.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.l ${Dsp-24-u24} */ { M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-24-absolute-Prefixed-SI", "divx.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.l $Dst32RnPrefixedSI */ { M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-Rn-direct-Prefixed-SI", "divu.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.l $Dst32AnPrefixedSI */ { M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-An-direct-Prefixed-SI", "divu.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.l [$Dst32AnPrefixed] */ { M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-An-indirect-Prefixed-SI", "divu.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.l ${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-8-An-relative-Prefixed-SI", "divu.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.l ${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-An-relative-Prefixed-SI", "divu.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.l ${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-24-An-relative-Prefixed-SI", "divu.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.l ${Dsp-24-u8}[sb] */ { M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-8-SB-relative-Prefixed-SI", "divu.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.l ${Dsp-24-u16}[sb] */ { M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-SB-relative-Prefixed-SI", "divu.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.l ${Dsp-24-s8}[fb] */ { M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-8-FB-relative-Prefixed-SI", "divu.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.l ${Dsp-24-s16}[fb] */ { M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-FB-relative-Prefixed-SI", "divu.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.l ${Dsp-24-u16} */ { M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-absolute-Prefixed-SI", "divu.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.l ${Dsp-24-u24} */ { M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-24-absolute-Prefixed-SI", "divu.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.l $Dst32RnPrefixedSI */ { M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-Rn-direct-Prefixed-SI", "div.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.l $Dst32AnPrefixedSI */ { M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-An-direct-Prefixed-SI", "div.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.l [$Dst32AnPrefixed] */ { M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-An-indirect-Prefixed-SI", "div.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.l ${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-8-An-relative-Prefixed-SI", "div.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.l ${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-An-relative-Prefixed-SI", "div.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.l ${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-24-An-relative-Prefixed-SI", "div.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.l ${Dsp-24-u8}[sb] */ { M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-8-SB-relative-Prefixed-SI", "div.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.l ${Dsp-24-u16}[sb] */ { M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-SB-relative-Prefixed-SI", "div.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.l ${Dsp-24-s8}[fb] */ { M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-8-FB-relative-Prefixed-SI", "div.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.l ${Dsp-24-s16}[fb] */ { M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-FB-relative-Prefixed-SI", "div.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.l ${Dsp-24-u16} */ { M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-absolute-Prefixed-SI", "div.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.l ${Dsp-24-u24} */ { M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-24-absolute-Prefixed-SI", "div.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.w $Dst32RnUnprefixedHI */ { M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "divx.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.w $Dst32AnUnprefixedHI */ { M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "divx.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.w [$Dst32AnUnprefixed] */ { M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "divx.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "divx.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "divx.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "divx.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.w ${Dsp-16-u8}[sb] */ { M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "divx.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.w ${Dsp-16-u16}[sb] */ { M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "divx.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.w ${Dsp-16-s8}[fb] */ { M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "divx.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.w ${Dsp-16-s16}[fb] */ { M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "divx.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.w ${Dsp-16-u16} */ { M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "divx.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.w ${Dsp-16-u24} */ { M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "divx.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.b $Dst32RnUnprefixedQI */ { M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "divx.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.b $Dst32AnUnprefixedQI */ { M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "divx.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.b [$Dst32AnUnprefixed] */ { M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "divx.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "divx.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "divx.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "divx.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.b ${Dsp-16-u8}[sb] */ { M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "divx.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.b ${Dsp-16-u16}[sb] */ { M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "divx.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.b ${Dsp-16-s8}[fb] */ { M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "divx.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.b ${Dsp-16-s16}[fb] */ { M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "divx.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.b ${Dsp-16-u16} */ { M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "divx.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.b ${Dsp-16-u24} */ { M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "divx.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.w $Dst16RnHI */ { M32C_INSN_DIVX16_W_DST16_16_HI_DST16_RN_DIRECT_HI, "divx16.w-dst16-16-HI-dst16-Rn-direct-HI", "divx.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divx.w $Dst16AnHI */ { M32C_INSN_DIVX16_W_DST16_16_HI_DST16_AN_DIRECT_HI, "divx16.w-dst16-16-HI-dst16-An-direct-HI", "divx.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divx.w [$Dst16An] */ { M32C_INSN_DIVX16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, "divx16.w-dst16-16-HI-dst16-An-indirect-HI", "divx.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divx.w ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-8-An-relative-HI", "divx.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divx.w ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-16-An-relative-HI", "divx.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divx.w ${Dsp-16-u8}[sb] */ { M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-8-SB-relative-HI", "divx.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divx.w ${Dsp-16-u16}[sb] */ { M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-16-SB-relative-HI", "divx.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divx.w ${Dsp-16-s8}[fb] */ { M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-8-FB-relative-HI", "divx.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divx.w ${Dsp-16-u16} */ { M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, "divx16.w-dst16-16-HI-dst16-16-16-absolute-HI", "divx.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divx.b $Dst16RnQI */ { M32C_INSN_DIVX16_B_DST16_16_QI_DST16_RN_DIRECT_QI, "divx16.b-dst16-16-QI-dst16-Rn-direct-QI", "divx.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divx.b $Dst16AnQI */ { M32C_INSN_DIVX16_B_DST16_16_QI_DST16_AN_DIRECT_QI, "divx16.b-dst16-16-QI-dst16-An-direct-QI", "divx.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divx.b [$Dst16An] */ { M32C_INSN_DIVX16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, "divx16.b-dst16-16-QI-dst16-An-indirect-QI", "divx.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divx.b ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-8-An-relative-QI", "divx.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divx.b ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-16-An-relative-QI", "divx.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divx.b ${Dsp-16-u8}[sb] */ { M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-8-SB-relative-QI", "divx.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divx.b ${Dsp-16-u16}[sb] */ { M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-16-SB-relative-QI", "divx.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divx.b ${Dsp-16-s8}[fb] */ { M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-8-FB-relative-QI", "divx.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divx.b ${Dsp-16-u16} */ { M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, "divx16.b-dst16-16-QI-dst16-16-16-absolute-QI", "divx.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divu.w $Dst32RnUnprefixedHI */ { M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "divu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.w $Dst32AnUnprefixedHI */ { M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "divu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.w [$Dst32AnUnprefixed] */ { M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "divu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "divu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "divu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "divu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.w ${Dsp-16-u8}[sb] */ { M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "divu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.w ${Dsp-16-u16}[sb] */ { M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "divu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.w ${Dsp-16-s8}[fb] */ { M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "divu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.w ${Dsp-16-s16}[fb] */ { M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "divu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.w ${Dsp-16-u16} */ { M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "divu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.w ${Dsp-16-u24} */ { M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "divu.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.b $Dst32RnUnprefixedQI */ { M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "divu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.b $Dst32AnUnprefixedQI */ { M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "divu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.b [$Dst32AnUnprefixed] */ { M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "divu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "divu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "divu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "divu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.b ${Dsp-16-u8}[sb] */ { M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "divu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.b ${Dsp-16-u16}[sb] */ { M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "divu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.b ${Dsp-16-s8}[fb] */ { M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "divu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.b ${Dsp-16-s16}[fb] */ { M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "divu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.b ${Dsp-16-u16} */ { M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "divu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.b ${Dsp-16-u24} */ { M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "divu.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.w $Dst16RnHI */ { M32C_INSN_DIVU16_W_DST16_16_HI_DST16_RN_DIRECT_HI, "divu16.w-dst16-16-HI-dst16-Rn-direct-HI", "divu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divu.w $Dst16AnHI */ { M32C_INSN_DIVU16_W_DST16_16_HI_DST16_AN_DIRECT_HI, "divu16.w-dst16-16-HI-dst16-An-direct-HI", "divu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divu.w [$Dst16An] */ { M32C_INSN_DIVU16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, "divu16.w-dst16-16-HI-dst16-An-indirect-HI", "divu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divu.w ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-8-An-relative-HI", "divu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divu.w ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-16-An-relative-HI", "divu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divu.w ${Dsp-16-u8}[sb] */ { M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-8-SB-relative-HI", "divu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divu.w ${Dsp-16-u16}[sb] */ { M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-16-SB-relative-HI", "divu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divu.w ${Dsp-16-s8}[fb] */ { M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-8-FB-relative-HI", "divu.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divu.w ${Dsp-16-u16} */ { M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, "divu16.w-dst16-16-HI-dst16-16-16-absolute-HI", "divu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divu.b $Dst16RnQI */ { M32C_INSN_DIVU16_B_DST16_16_QI_DST16_RN_DIRECT_QI, "divu16.b-dst16-16-QI-dst16-Rn-direct-QI", "divu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divu.b $Dst16AnQI */ { M32C_INSN_DIVU16_B_DST16_16_QI_DST16_AN_DIRECT_QI, "divu16.b-dst16-16-QI-dst16-An-direct-QI", "divu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divu.b [$Dst16An] */ { M32C_INSN_DIVU16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, "divu16.b-dst16-16-QI-dst16-An-indirect-QI", "divu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divu.b ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-8-An-relative-QI", "divu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divu.b ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-16-An-relative-QI", "divu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divu.b ${Dsp-16-u8}[sb] */ { M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-8-SB-relative-QI", "divu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divu.b ${Dsp-16-u16}[sb] */ { M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-16-SB-relative-QI", "divu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divu.b ${Dsp-16-s8}[fb] */ { M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-8-FB-relative-QI", "divu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divu.b ${Dsp-16-u16} */ { M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, "divu16.b-dst16-16-QI-dst16-16-16-absolute-QI", "divu.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* div.w $Dst32RnUnprefixedHI */ { M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "div.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.w $Dst32AnUnprefixedHI */ { M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "div.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.w [$Dst32AnUnprefixed] */ { M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "div.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "div.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "div.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "div.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.w ${Dsp-16-u8}[sb] */ { M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "div.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.w ${Dsp-16-u16}[sb] */ { M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "div.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.w ${Dsp-16-s8}[fb] */ { M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "div.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.w ${Dsp-16-s16}[fb] */ { M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "div.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.w ${Dsp-16-u16} */ { M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "div.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.w ${Dsp-16-u24} */ { M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "div.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.b $Dst32RnUnprefixedQI */ { M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "div.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.b $Dst32AnUnprefixedQI */ { M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "div.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.b [$Dst32AnUnprefixed] */ { M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "div.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "div.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "div.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "div.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.b ${Dsp-16-u8}[sb] */ { M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "div.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.b ${Dsp-16-u16}[sb] */ { M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "div.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.b ${Dsp-16-s8}[fb] */ { M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "div.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.b ${Dsp-16-s16}[fb] */ { M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "div.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.b ${Dsp-16-u16} */ { M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "div.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.b ${Dsp-16-u24} */ { M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "div.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.w $Dst16RnHI */ { M32C_INSN_DIV16_W_DST16_16_HI_DST16_RN_DIRECT_HI, "div16.w-dst16-16-HI-dst16-Rn-direct-HI", "div.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* div.w $Dst16AnHI */ { M32C_INSN_DIV16_W_DST16_16_HI_DST16_AN_DIRECT_HI, "div16.w-dst16-16-HI-dst16-An-direct-HI", "div.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* div.w [$Dst16An] */ { M32C_INSN_DIV16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, "div16.w-dst16-16-HI-dst16-An-indirect-HI", "div.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* div.w ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-8-An-relative-HI", "div.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* div.w ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-16-An-relative-HI", "div.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* div.w ${Dsp-16-u8}[sb] */ { M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-8-SB-relative-HI", "div.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* div.w ${Dsp-16-u16}[sb] */ { M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-16-SB-relative-HI", "div.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* div.w ${Dsp-16-s8}[fb] */ { M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-8-FB-relative-HI", "div.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* div.w ${Dsp-16-u16} */ { M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, "div16.w-dst16-16-HI-dst16-16-16-absolute-HI", "div.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* div.b $Dst16RnQI */ { M32C_INSN_DIV16_B_DST16_16_QI_DST16_RN_DIRECT_QI, "div16.b-dst16-16-QI-dst16-Rn-direct-QI", "div.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* div.b $Dst16AnQI */ { M32C_INSN_DIV16_B_DST16_16_QI_DST16_AN_DIRECT_QI, "div16.b-dst16-16-QI-dst16-An-direct-QI", "div.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* div.b [$Dst16An] */ { M32C_INSN_DIV16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, "div16.b-dst16-16-QI-dst16-An-indirect-QI", "div.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* div.b ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-8-An-relative-QI", "div.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* div.b ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-16-An-relative-QI", "div.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* div.b ${Dsp-16-u8}[sb] */ { M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-8-SB-relative-QI", "div.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* div.b ${Dsp-16-u16}[sb] */ { M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-16-SB-relative-QI", "div.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* div.b ${Dsp-16-s8}[fb] */ { M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-8-FB-relative-QI", "div.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* div.b ${Dsp-16-u16} */ { M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, "div16.b-dst16-16-QI-dst16-16-16-absolute-QI", "div.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* dec.w $Dst32RnUnprefixedHI */ { M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "dec.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.w $Dst32AnUnprefixedHI */ { M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "dec.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.w [$Dst32AnUnprefixed] */ { M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "dec.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "dec.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "dec.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "dec.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.w ${Dsp-16-u8}[sb] */ { M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "dec.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.w ${Dsp-16-u16}[sb] */ { M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "dec.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.w ${Dsp-16-s8}[fb] */ { M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "dec.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.w ${Dsp-16-s16}[fb] */ { M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "dec.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.w ${Dsp-16-u16} */ { M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "dec.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.w ${Dsp-16-u24} */ { M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "dec.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.b $Dst32RnUnprefixedQI */ { M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "dec.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.b $Dst32AnUnprefixedQI */ { M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "dec.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.b [$Dst32AnUnprefixed] */ { M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "dec.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "dec.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "dec.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "dec.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.b ${Dsp-16-u8}[sb] */ { M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "dec.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.b ${Dsp-16-u16}[sb] */ { M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "dec.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.b ${Dsp-16-s8}[fb] */ { M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "dec.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.b ${Dsp-16-s16}[fb] */ { M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "dec.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.b ${Dsp-16-u16} */ { M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "dec.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.b ${Dsp-16-u24} */ { M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "dec.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.b r0l */ { M32C_INSN_DEC16_B_DST16_3_S_R0L_DIRECT_QI, "dec16.b-dst16-3-S-R0l-direct-QI", "dec.b", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* dec.b r0h */ { M32C_INSN_DEC16_B_DST16_3_S_R0H_DIRECT_QI, "dec16.b-dst16-3-S-R0h-direct-QI", "dec.b", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* dec.b ${Dsp-8-u8}[sb] */ { M32C_INSN_DEC16_B_DST16_3_S_8_8_SB_RELATIVE_QI, "dec16.b-dst16-3-S-8-8-SB-relative-QI", "dec.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* dec.b ${Dsp-8-s8}[fb] */ { M32C_INSN_DEC16_B_DST16_3_S_8_8_FB_RELATIVE_QI, "dec16.b-dst16-3-S-8-8-FB-relative-QI", "dec.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* dec.b ${Dsp-8-u16} */ { M32C_INSN_DEC16_B_DST16_3_S_8_16_ABSOLUTE_QI, "dec16.b-dst16-3-S-8-16-absolute-QI", "dec.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmpx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ { M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "cmpx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "cmpx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmpx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ { M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "cmpx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "cmpx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmpx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmpx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "cmpx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "cmpx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "cmpx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmpx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "cmpx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "cmpx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "cmpx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmpx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "cmpx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmpx${X} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "cmpx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmpx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMPX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "cmpx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmpx${X} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_CMPX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmpx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "cmpx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${S} ${Dsp-8-u8}[sb],${Dst32R0HI-S} */ { M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_8_SB_RELATIVE_HI, "cmp32.w.S-src2-r0-HI-src32-2-S-8-SB-relative-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${S} ${Dsp-8-s8}[fb],${Dst32R0HI-S} */ { M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_8_FB_RELATIVE_HI, "cmp32.w.S-src2-r0-HI-src32-2-S-8-FB-relative-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${S} ${Dsp-8-u16},${Dst32R0HI-S} */ { M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_16_ABSOLUTE_HI, "cmp32.w.S-src2-r0-HI-src32-2-S-16-absolute-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${S} ${Dsp-8-u8}[sb],${Dst32R0QI-S} */ { M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_8_SB_RELATIVE_QI, "cmp32.b.S-src2-r0-QI-src32-2-S-8-SB-relative-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${S} ${Dsp-8-s8}[fb],${Dst32R0QI-S} */ { M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_8_FB_RELATIVE_QI, "cmp32.b.S-src2-r0-QI-src32-2-S-8-FB-relative-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${S} ${Dsp-8-u16},${Dst32R0QI-S} */ { M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_16_ABSOLUTE_QI, "cmp32.b.S-src2-r0-QI-src32-2-S-16-absolute-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ { M32C_INSN_CMP32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "cmp32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ { M32C_INSN_CMP32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "cmp32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${S} #${Imm-24-HI},${Dsp-8-u16} */ { M32C_INSN_CMP32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "cmp32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${S} #${Imm-8-HI},r0 */ { M32C_INSN_CMP32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "cmp32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ { M32C_INSN_CMP32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "cmp32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ { M32C_INSN_CMP32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "cmp32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${S} #${Imm-24-QI},${Dsp-8-u16} */ { M32C_INSN_CMP32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "cmp32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${S} #${Imm-8-QI},r0l */ { M32C_INSN_CMP32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "cmp32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */ { M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */ { M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "cmp.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "cmp.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "cmp.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "cmp.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "cmp.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "cmp.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "cmp.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "cmp.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "cmp.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "cmp.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "cmp.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "cmp.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${S} ${SrcDst16-r0l-r0h-S-normal} */ { M32C_INSN_CMP16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "cmp16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "cmp.b", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */ { M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "cmp16.b.S-src2-src16-2-S-8-SB-relative-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */ { M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "cmp16.b.S-src2-src16-2-S-8-FB-relative-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */ { M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "cmp16.b.S-src2-src16-2-S-16-absolute-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ { M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ { M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "cmp.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "cmp.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "cmp.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "cmp.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "cmp.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "cmp.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "cmp.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "cmp.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "cmp.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "cmp.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "cmp.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "cmp.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ { M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ { M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "cmp.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "cmp.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "cmp.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "cmp.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "cmp.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "cmp.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "cmp.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "cmp.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "cmp.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "cmp.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "cmp.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "cmp.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16},$Dst16RnHI */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16},$Dst16AnHI */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} $Src16RnHI,$Dst16RnHI */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} $Src16AnHI,$Dst16RnHI */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} [$Src16An],$Dst16RnHI */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} $Src16RnHI,$Dst16AnHI */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} $Src16AnHI,$Dst16AnHI */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} [$Src16An],$Dst16AnHI */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} $Src16RnHI,[$Dst16An] */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} $Src16AnHI,[$Dst16An] */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} [$Src16An],[$Dst16An] */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} $Src16RnHI,${Dsp-16-u16} */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} $Src16AnHI,${Dsp-16-u16} */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16},$Dst16RnQI */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16},$Dst16AnQI */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} $Src16RnQI,$Dst16RnQI */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} $Src16AnQI,$Dst16RnQI */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} [$Src16An],$Dst16RnQI */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} $Src16RnQI,$Dst16AnQI */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} $Src16AnQI,$Dst16AnQI */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} [$Src16An],$Dst16AnQI */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} $Src16RnQI,[$Dst16An] */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} $Src16AnQI,[$Dst16An] */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} [$Src16An],[$Dst16An] */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} $Src16RnQI,${Dsp-16-u16} */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} $Src16AnQI,${Dsp-16-u16} */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${S} #${Imm-8-QI},r0l */ { M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${S} #${Imm-8-QI},r0h */ { M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${S} #${Imm-8-QI},${Dsp-16-u16} */ { M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */ { M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */ { M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */ { M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16} */ { M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24} */ { M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */ { M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */ { M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */ { M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16} */ { M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24} */ { M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${Q} #${Imm-8-s4},$Dst16RnHI */ { M32C_INSN_CMP16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "cmp16.w-imm4-Q-16-dst16-Rn-direct-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${Q} #${Imm-8-s4},$Dst16AnHI */ { M32C_INSN_CMP16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "cmp16.w-imm4-Q-16-dst16-An-direct-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${Q} #${Imm-8-s4},[$Dst16An] */ { M32C_INSN_CMP16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "cmp16.w-imm4-Q-16-dst16-An-indirect-HI", "cmp.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "cmp.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16} */ { M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "cmp16.w-imm4-Q-16-dst16-16-16-absolute-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${Q} #${Imm-8-s4},$Dst16RnQI */ { M32C_INSN_CMP16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "cmp16.b-imm4-Q-16-dst16-Rn-direct-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${Q} #${Imm-8-s4},$Dst16AnQI */ { M32C_INSN_CMP16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "cmp16.b-imm4-Q-16-dst16-An-direct-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${Q} #${Imm-8-s4},[$Dst16An] */ { M32C_INSN_CMP16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "cmp16.b-imm4-Q-16-dst16-An-indirect-QI", "cmp.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16} */ { M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "cmp16.b-imm4-Q-16-dst16-16-16-absolute-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ { M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ { M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ { M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24} */ { M32C_INSN_CMP32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ { M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ { M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_CMP32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.w${G} #${Imm-16-HI},$Dst16RnHI */ { M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "cmp16.w-imm-G-basic-dst16-Rn-direct-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} #${Imm-16-HI},$Dst16AnHI */ { M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "cmp16.w-imm-G-basic-dst16-An-direct-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} #${Imm-16-HI},[$Dst16An] */ { M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "cmp16.w-imm-G-basic-dst16-An-indirect-HI", "cmp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "cmp.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "cmp16.w-imm-G-16-16-dst16-16-16-absolute-HI", "cmp.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} #${Imm-16-QI},$Dst16RnQI */ { M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "cmp16.b-imm-G-basic-dst16-Rn-direct-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} #${Imm-16-QI},$Dst16AnQI */ { M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "cmp16.b-imm-G-basic-dst16-An-direct-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} #${Imm-16-QI},[$Dst16An] */ { M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "cmp16.b-imm-G-basic-dst16-An-indirect-QI", "cmp.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "cmp.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "cmp16.b-imm-G-16-16-dst16-16-16-absolute-QI", "cmp.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* cmp.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */ { M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */ { M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "cmp.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */ { M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */ { M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */ { M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */ { M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16} */ { M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_CMP32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24} */ { M32C_INSN_CMP32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32RnPrefixedHI */ { M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "clip32.w-Imm-24-HI-Imm-40-HI-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "clip.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32AnPrefixedHI */ { M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "clip32.w-Imm-24-HI-Imm-40-HI-basic-Prefixed-dst32-An-direct-Prefixed-HI", "clip.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* clip.w #${Imm-24-HI},#${Imm-40-HI},[$Dst32AnPrefixed] */ { M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "clip32.w-Imm-24-HI-Imm-40-HI-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "clip.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "clip32.w-Imm-32-HI-Imm-48-HI-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "clip.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[sb] */ { M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-32-HI-Imm-48-HI-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "clip.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-s8}[fb] */ { M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-32-HI-Imm-48-HI-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "clip.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "clip.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[sb] */ { M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "clip.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-s16}[fb] */ { M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "clip.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16} */ { M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "clip.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_CLIP32_W_IMM_48_HI_IMM_64_HI_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "clip32.w-Imm-48-HI-Imm-64-HI-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "clip.w", 80, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24} */ { M32C_INSN_CLIP32_W_IMM_48_HI_IMM_64_HI_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "clip32.w-Imm-48-HI-Imm-64-HI-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "clip.w", 80, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32RnPrefixedQI */ { M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "clip32.b-Imm-24-QI-Imm-32-QI-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "clip.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32AnPrefixedQI */ { M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "clip32.b-Imm-24-QI-Imm-32-QI-basic-Prefixed-dst32-An-direct-Prefixed-QI", "clip.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* clip.b #${Imm-24-QI},#${Imm-32-QI},[$Dst32AnPrefixed] */ { M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "clip32.b-Imm-24-QI-Imm-32-QI-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "clip.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "clip32.b-Imm-32-QI-Imm-40-QI-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "clip.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[sb] */ { M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-32-QI-Imm-40-QI-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "clip.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-s8}[fb] */ { M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-32-QI-Imm-40-QI-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "clip.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "clip.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[sb] */ { M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "clip.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-s16}[fb] */ { M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "clip.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16} */ { M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "clip.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_CLIP32_B_IMM_48_QI_IMM_56_QI_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "clip32.b-Imm-48-QI-Imm-56-QI-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "clip.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24} */ { M32C_INSN_CLIP32_B_IMM_48_QI_IMM_56_QI_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "clip32.b-Imm-48-QI-Imm-56-QI-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "clip.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */ { M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bxor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */ { M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bxor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */ { M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bxor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */ { M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bxor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */ { M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bxor", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */ { M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bxor", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bxor${X} ${BitBase32-24-u11-Prefixed}[sb] */ { M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bxor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bxor${X} ${BitBase32-24-u19-Prefixed}[sb] */ { M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bxor", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bxor${X} ${BitBase32-24-s11-Prefixed}[fb] */ { M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bxor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bxor${X} ${BitBase32-24-s19-Prefixed}[fb] */ { M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bxor", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bxor${X} ${BitBase32-24-u19-Prefixed} */ { M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bxor", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bxor${X} ${BitBase32-24-u27-Prefixed} */ { M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bxor", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bxor${X} $Bitno16R,$Bit16Rn */ { M32C_INSN_BXOR16_X_BIT16_16_BIT16_RN_DIRECT, "bxor16-X-bit16-16-bit16-Rn-direct", "bxor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bxor${X} $Bitno16R,$Bit16An */ { M32C_INSN_BXOR16_X_BIT16_16_BIT16_AN_DIRECT, "bxor16-X-bit16-16-bit16-An-direct", "bxor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bxor${X} [$Bit16An] */ { M32C_INSN_BXOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bxor16-X-bit16-16-bit16-An-indirect", "bxor", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bxor${X} ${Dsp-16-u8}[$Bit16An] */ { M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bxor16-X-bit16-16-bit16-16-8-An-relative", "bxor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bxor${X} ${Dsp-16-u16}[$Bit16An] */ { M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bxor16-X-bit16-16-bit16-16-16-An-relative", "bxor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bxor${X} ${BitBase16-16-u8}[sb] */ { M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bxor16-X-bit16-16-bit16-16-8-SB-relative", "bxor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bxor${X} ${BitBase16-16-u16}[sb] */ { M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bxor16-X-bit16-16-bit16-16-16-SB-relative", "bxor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bxor${X} ${BitBase16-16-s8}[fb] */ { M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bxor16-X-bit16-16-bit16-16-8-FB-relative", "bxor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bxor${X} ${BitBase16-16-u16} */ { M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bxor16-X-bit16-16-bit16-16-16-absolute", "bxor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btsts${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */ { M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "btsts", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btsts${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */ { M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "btsts", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btsts${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */ { M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "btsts", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btsts${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */ { M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "btsts", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btsts${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */ { M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "btsts", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btsts${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */ { M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "btsts", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btsts${X} ${BitBase32-16-u11-Unprefixed}[sb] */ { M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "btsts", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btsts${X} ${BitBase32-16-u19-Unprefixed}[sb] */ { M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "btsts", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btsts${X} ${BitBase32-16-s11-Unprefixed}[fb] */ { M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "btsts", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btsts${X} ${BitBase32-16-s19-Unprefixed}[fb] */ { M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "btsts", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btsts${X} ${BitBase32-16-u19-Unprefixed} */ { M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "btsts", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btsts${X} ${BitBase32-16-u27-Unprefixed} */ { M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "btsts", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btsts${X} $Bitno16R,$Bit16Rn */ { M32C_INSN_BTSTS16_X_BIT16_16_BIT16_RN_DIRECT, "btsts16-X-bit16-16-bit16-Rn-direct", "btsts", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btsts${X} $Bitno16R,$Bit16An */ { M32C_INSN_BTSTS16_X_BIT16_16_BIT16_AN_DIRECT, "btsts16-X-bit16-16-bit16-An-direct", "btsts", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btsts${X} [$Bit16An] */ { M32C_INSN_BTSTS16_X_BIT16_16_BIT16_AN_INDIRECT, "btsts16-X-bit16-16-bit16-An-indirect", "btsts", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btsts${X} ${Dsp-16-u8}[$Bit16An] */ { M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "btsts16-X-bit16-16-bit16-16-8-An-relative", "btsts", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btsts${X} ${Dsp-16-u16}[$Bit16An] */ { M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "btsts16-X-bit16-16-bit16-16-16-An-relative", "btsts", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btsts${X} ${BitBase16-16-u8}[sb] */ { M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "btsts16-X-bit16-16-bit16-16-8-SB-relative", "btsts", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btsts${X} ${BitBase16-16-u16}[sb] */ { M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "btsts16-X-bit16-16-bit16-16-16-SB-relative", "btsts", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btsts${X} ${BitBase16-16-s8}[fb] */ { M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "btsts16-X-bit16-16-bit16-16-8-FB-relative", "btsts", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btsts${X} ${BitBase16-16-u16} */ { M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "btsts16-X-bit16-16-bit16-16-16-absolute", "btsts", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btstc${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */ { M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "btstc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btstc${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */ { M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "btstc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btstc${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */ { M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "btstc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btstc${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */ { M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "btstc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btstc${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */ { M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "btstc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btstc${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */ { M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "btstc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btstc${X} ${BitBase32-16-u11-Unprefixed}[sb] */ { M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "btstc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btstc${X} ${BitBase32-16-u19-Unprefixed}[sb] */ { M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "btstc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btstc${X} ${BitBase32-16-s11-Unprefixed}[fb] */ { M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "btstc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btstc${X} ${BitBase32-16-s19-Unprefixed}[fb] */ { M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "btstc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btstc${X} ${BitBase32-16-u19-Unprefixed} */ { M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "btstc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btstc${X} ${BitBase32-16-u27-Unprefixed} */ { M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "btstc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btstc${X} $Bitno16R,$Bit16Rn */ { M32C_INSN_BTSTC16_X_BIT16_16_BIT16_RN_DIRECT, "btstc16-X-bit16-16-bit16-Rn-direct", "btstc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btstc${X} $Bitno16R,$Bit16An */ { M32C_INSN_BTSTC16_X_BIT16_16_BIT16_AN_DIRECT, "btstc16-X-bit16-16-bit16-An-direct", "btstc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btstc${X} [$Bit16An] */ { M32C_INSN_BTSTC16_X_BIT16_16_BIT16_AN_INDIRECT, "btstc16-X-bit16-16-bit16-An-indirect", "btstc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btstc${X} ${Dsp-16-u8}[$Bit16An] */ { M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "btstc16-X-bit16-16-bit16-16-8-An-relative", "btstc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btstc${X} ${Dsp-16-u16}[$Bit16An] */ { M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "btstc16-X-bit16-16-bit16-16-16-An-relative", "btstc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btstc${X} ${BitBase16-16-u8}[sb] */ { M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "btstc16-X-bit16-16-bit16-16-8-SB-relative", "btstc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btstc${X} ${BitBase16-16-u16}[sb] */ { M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "btstc16-X-bit16-16-bit16-16-16-SB-relative", "btstc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btstc${X} ${BitBase16-16-s8}[fb] */ { M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "btstc16-X-bit16-16-bit16-16-8-FB-relative", "btstc", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btstc${X} ${BitBase16-16-u16} */ { M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "btstc16-X-bit16-16-bit16-16-16-absolute", "btstc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btst${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */ { M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "btst", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btst${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */ { M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "btst", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btst${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */ { M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "btst", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btst${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */ { M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "btst", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btst${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */ { M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "btst", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btst${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */ { M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "btst", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btst${X} ${BitBase32-16-u11-Unprefixed}[sb] */ { M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "btst", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btst${X} ${BitBase32-16-u19-Unprefixed}[sb] */ { M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "btst", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btst${X} ${BitBase32-16-s11-Unprefixed}[fb] */ { M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "btst", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btst${X} ${BitBase32-16-s19-Unprefixed}[fb] */ { M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "btst", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btst${X} ${BitBase32-16-u19-Unprefixed} */ { M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "btst", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btst${X} ${BitBase32-16-u27-Unprefixed} */ { M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "btst", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* btst${G} $Bitno16R,$Bit16Rn */ { M32C_INSN_BTST16_G_BIT16_16_8_BIT16_RN_DIRECT, "btst16-G-bit16-16-8-bit16-Rn-direct", "btst", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btst${G} $Bitno16R,$Bit16An */ { M32C_INSN_BTST16_G_BIT16_16_8_BIT16_AN_DIRECT, "btst16-G-bit16-16-8-bit16-An-direct", "btst", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btst${G} ${Dsp-16-u8}[$Bit16An] */ { M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "btst16-G-bit16-16-8-bit16-16-8-An-relative", "btst", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btst${G} ${BitBase16-16-u8}[sb] */ { M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "btst16-G-bit16-16-8-bit16-16-8-SB-relative", "btst", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btst${G} ${BitBase16-16-s8}[fb] */ { M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "btst16-G-bit16-16-8-bit16-16-8-FB-relative", "btst", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btst${S} ${BitBase16-8-u11-S}[sb] */ { M32C_INSN_BTST16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "btst16-S-bit16-11-S-bit16-11-SB-relative-S", "btst", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btst${G} ${Dsp-16-u16}[$Bit16An] */ { M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "btst16-G-bit16-16-16-bit16-16-16-An-relative", "btst", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btst${G} ${BitBase16-16-u16}[sb] */ { M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "btst16-G-bit16-16-16-bit16-16-16-SB-relative", "btst", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btst${G} ${BitBase16-16-u16} */ { M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "btst16-G-bit16-16-16-bit16-16-16-absolute", "btst", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* btst${G} [$Bit16An] */ { M32C_INSN_BTST16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "btst16-G-bit16-16-basic-bit16-An-indirect", "btst", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bset${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */ { M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "bset", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bset${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */ { M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "bset", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bset${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */ { M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "bset", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bset${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */ { M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "bset", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bset${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */ { M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "bset", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bset${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */ { M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "bset", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bset${X} ${BitBase32-16-u11-Unprefixed}[sb] */ { M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "bset", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bset${X} ${BitBase32-16-u19-Unprefixed}[sb] */ { M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "bset", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bset${X} ${BitBase32-16-s11-Unprefixed}[fb] */ { M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "bset", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bset${X} ${BitBase32-16-s19-Unprefixed}[fb] */ { M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "bset", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bset${X} ${BitBase32-16-u19-Unprefixed} */ { M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "bset", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bset${X} ${BitBase32-16-u27-Unprefixed} */ { M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "bset", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bset${G} $Bitno16R,$Bit16Rn */ { M32C_INSN_BSET16_G_BIT16_16_8_BIT16_RN_DIRECT, "bset16-G-bit16-16-8-bit16-Rn-direct", "bset", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bset${G} $Bitno16R,$Bit16An */ { M32C_INSN_BSET16_G_BIT16_16_8_BIT16_AN_DIRECT, "bset16-G-bit16-16-8-bit16-An-direct", "bset", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bset${G} ${Dsp-16-u8}[$Bit16An] */ { M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "bset16-G-bit16-16-8-bit16-16-8-An-relative", "bset", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bset${G} ${BitBase16-16-u8}[sb] */ { M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "bset16-G-bit16-16-8-bit16-16-8-SB-relative", "bset", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bset${G} ${BitBase16-16-s8}[fb] */ { M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "bset16-G-bit16-16-8-bit16-16-8-FB-relative", "bset", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bset${S} ${BitBase16-8-u11-S}[sb] */ { M32C_INSN_BSET16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "bset16-S-bit16-11-S-bit16-11-SB-relative-S", "bset", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bset${G} ${Dsp-16-u16}[$Bit16An] */ { M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "bset16-G-bit16-16-16-bit16-16-16-An-relative", "bset", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bset${G} ${BitBase16-16-u16}[sb] */ { M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "bset16-G-bit16-16-16-bit16-16-16-SB-relative", "bset", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bset${G} ${BitBase16-16-u16} */ { M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "bset16-G-bit16-16-16-bit16-16-16-absolute", "bset", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bset${G} [$Bit16An] */ { M32C_INSN_BSET16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "bset16-G-bit16-16-basic-bit16-An-indirect", "bset", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bor${X} $Bitno32Prefixed,$Bit32RnPrefixed */ { M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bor${X} $Bitno32Prefixed,$Bit32AnPrefixed */ { M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */ { M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */ { M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */ { M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bor", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */ { M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bor", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bor${X} ${BitBase32-24-u11-Prefixed}[sb] */ { M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bor${X} ${BitBase32-24-u19-Prefixed}[sb] */ { M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bor", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bor${X} ${BitBase32-24-s11-Prefixed}[fb] */ { M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bor${X} ${BitBase32-24-s19-Prefixed}[fb] */ { M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bor", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bor${X} ${BitBase32-24-u19-Prefixed} */ { M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bor", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bor${X} ${BitBase32-24-u27-Prefixed} */ { M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bor", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bor${X} $Bitno16R,$Bit16Rn */ { M32C_INSN_BOR16_X_BIT16_16_BIT16_RN_DIRECT, "bor16-X-bit16-16-bit16-Rn-direct", "bor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bor${X} $Bitno16R,$Bit16An */ { M32C_INSN_BOR16_X_BIT16_16_BIT16_AN_DIRECT, "bor16-X-bit16-16-bit16-An-direct", "bor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bor${X} [$Bit16An] */ { M32C_INSN_BOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bor16-X-bit16-16-bit16-An-indirect", "bor", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bor${X} ${Dsp-16-u8}[$Bit16An] */ { M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bor16-X-bit16-16-bit16-16-8-An-relative", "bor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bor${X} ${Dsp-16-u16}[$Bit16An] */ { M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bor16-X-bit16-16-bit16-16-16-An-relative", "bor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bor${X} ${BitBase16-16-u8}[sb] */ { M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bor16-X-bit16-16-bit16-16-8-SB-relative", "bor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bor${X} ${BitBase16-16-u16}[sb] */ { M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bor16-X-bit16-16-bit16-16-16-SB-relative", "bor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bor${X} ${BitBase16-16-s8}[fb] */ { M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bor16-X-bit16-16-bit16-16-8-FB-relative", "bor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bor${X} ${BitBase16-16-u16} */ { M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bor16-X-bit16-16-bit16-16-16-absolute", "bor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */ { M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bnxor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */ { M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bnxor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */ { M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bnxor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */ { M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bnxor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */ { M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bnxor", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */ { M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bnxor", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnxor${X} ${BitBase32-24-u11-Prefixed}[sb] */ { M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bnxor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnxor${X} ${BitBase32-24-u19-Prefixed}[sb] */ { M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bnxor", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnxor${X} ${BitBase32-24-s11-Prefixed}[fb] */ { M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bnxor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnxor${X} ${BitBase32-24-s19-Prefixed}[fb] */ { M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bnxor", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnxor${X} ${BitBase32-24-u19-Prefixed} */ { M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bnxor", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnxor${X} ${BitBase32-24-u27-Prefixed} */ { M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bnxor", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnxor${X} $Bitno16R,$Bit16Rn */ { M32C_INSN_BNXOR16_X_BIT16_16_BIT16_RN_DIRECT, "bnxor16-X-bit16-16-bit16-Rn-direct", "bnxor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnxor${X} $Bitno16R,$Bit16An */ { M32C_INSN_BNXOR16_X_BIT16_16_BIT16_AN_DIRECT, "bnxor16-X-bit16-16-bit16-An-direct", "bnxor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnxor${X} [$Bit16An] */ { M32C_INSN_BNXOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bnxor16-X-bit16-16-bit16-An-indirect", "bnxor", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnxor${X} ${Dsp-16-u8}[$Bit16An] */ { M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bnxor16-X-bit16-16-bit16-16-8-An-relative", "bnxor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnxor${X} ${Dsp-16-u16}[$Bit16An] */ { M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bnxor16-X-bit16-16-bit16-16-16-An-relative", "bnxor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnxor${X} ${BitBase16-16-u8}[sb] */ { M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bnxor16-X-bit16-16-bit16-16-8-SB-relative", "bnxor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnxor${X} ${BitBase16-16-u16}[sb] */ { M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bnxor16-X-bit16-16-bit16-16-16-SB-relative", "bnxor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnxor${X} ${BitBase16-16-s8}[fb] */ { M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bnxor16-X-bit16-16-bit16-16-8-FB-relative", "bnxor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnxor${X} ${BitBase16-16-u16} */ { M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bnxor16-X-bit16-16-bit16-16-16-absolute", "bnxor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bntst${X} $Bitno32Prefixed,$Bit32RnPrefixed */ { M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bntst", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bntst${X} $Bitno32Prefixed,$Bit32AnPrefixed */ { M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bntst", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bntst${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */ { M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bntst", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bntst${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */ { M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bntst", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bntst${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */ { M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bntst", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bntst${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */ { M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bntst", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bntst${X} ${BitBase32-24-u11-Prefixed}[sb] */ { M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bntst", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bntst${X} ${BitBase32-24-u19-Prefixed}[sb] */ { M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bntst", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bntst${X} ${BitBase32-24-s11-Prefixed}[fb] */ { M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bntst", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bntst${X} ${BitBase32-24-s19-Prefixed}[fb] */ { M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bntst", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bntst${X} ${BitBase32-24-u19-Prefixed} */ { M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bntst", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bntst${X} ${BitBase32-24-u27-Prefixed} */ { M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bntst", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bntst${X} $Bitno16R,$Bit16Rn */ { M32C_INSN_BNTST16_X_BIT16_16_BIT16_RN_DIRECT, "bntst16-X-bit16-16-bit16-Rn-direct", "bntst", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bntst${X} $Bitno16R,$Bit16An */ { M32C_INSN_BNTST16_X_BIT16_16_BIT16_AN_DIRECT, "bntst16-X-bit16-16-bit16-An-direct", "bntst", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bntst${X} [$Bit16An] */ { M32C_INSN_BNTST16_X_BIT16_16_BIT16_AN_INDIRECT, "bntst16-X-bit16-16-bit16-An-indirect", "bntst", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bntst${X} ${Dsp-16-u8}[$Bit16An] */ { M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bntst16-X-bit16-16-bit16-16-8-An-relative", "bntst", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bntst${X} ${Dsp-16-u16}[$Bit16An] */ { M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bntst16-X-bit16-16-bit16-16-16-An-relative", "bntst", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bntst${X} ${BitBase16-16-u8}[sb] */ { M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bntst16-X-bit16-16-bit16-16-8-SB-relative", "bntst", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bntst${X} ${BitBase16-16-u16}[sb] */ { M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bntst16-X-bit16-16-bit16-16-16-SB-relative", "bntst", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bntst${X} ${BitBase16-16-s8}[fb] */ { M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bntst16-X-bit16-16-bit16-16-8-FB-relative", "bntst", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bntst${X} ${BitBase16-16-u16} */ { M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bntst16-X-bit16-16-bit16-16-16-absolute", "bntst", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnot${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */ { M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "bnot", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnot${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */ { M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "bnot", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnot${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */ { M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "bnot", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnot${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */ { M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "bnot", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnot${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */ { M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "bnot", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnot${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */ { M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "bnot", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnot${X} ${BitBase32-16-u11-Unprefixed}[sb] */ { M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "bnot", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnot${X} ${BitBase32-16-u19-Unprefixed}[sb] */ { M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "bnot", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnot${X} ${BitBase32-16-s11-Unprefixed}[fb] */ { M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "bnot", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnot${X} ${BitBase32-16-s19-Unprefixed}[fb] */ { M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "bnot", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnot${X} ${BitBase32-16-u19-Unprefixed} */ { M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "bnot", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnot${X} ${BitBase32-16-u27-Unprefixed} */ { M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "bnot", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnot${G} $Bitno16R,$Bit16Rn */ { M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_RN_DIRECT, "bnot16-G-bit16-16-8-bit16-Rn-direct", "bnot", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnot${G} $Bitno16R,$Bit16An */ { M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_AN_DIRECT, "bnot16-G-bit16-16-8-bit16-An-direct", "bnot", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnot${G} ${Dsp-16-u8}[$Bit16An] */ { M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "bnot16-G-bit16-16-8-bit16-16-8-An-relative", "bnot", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnot${G} ${BitBase16-16-u8}[sb] */ { M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "bnot16-G-bit16-16-8-bit16-16-8-SB-relative", "bnot", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnot${G} ${BitBase16-16-s8}[fb] */ { M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "bnot16-G-bit16-16-8-bit16-16-8-FB-relative", "bnot", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnot${S} ${BitBase16-8-u11-S}[sb] */ { M32C_INSN_BNOT16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "bnot16-S-bit16-11-S-bit16-11-SB-relative-S", "bnot", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnot${G} ${Dsp-16-u16}[$Bit16An] */ { M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "bnot16-G-bit16-16-16-bit16-16-16-An-relative", "bnot", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnot${G} ${BitBase16-16-u16}[sb] */ { M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "bnot16-G-bit16-16-16-bit16-16-16-SB-relative", "bnot", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnot${G} ${BitBase16-16-u16} */ { M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "bnot16-G-bit16-16-16-bit16-16-16-absolute", "bnot", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnot${G} [$Bit16An] */ { M32C_INSN_BNOT16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "bnot16-G-bit16-16-basic-bit16-An-indirect", "bnot", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnor${X} $Bitno32Prefixed,$Bit32RnPrefixed */ { M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bnor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnor${X} $Bitno32Prefixed,$Bit32AnPrefixed */ { M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bnor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */ { M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bnor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */ { M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bnor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */ { M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bnor", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */ { M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bnor", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnor${X} ${BitBase32-24-u11-Prefixed}[sb] */ { M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bnor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnor${X} ${BitBase32-24-u19-Prefixed}[sb] */ { M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bnor", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnor${X} ${BitBase32-24-s11-Prefixed}[fb] */ { M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bnor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnor${X} ${BitBase32-24-s19-Prefixed}[fb] */ { M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bnor", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnor${X} ${BitBase32-24-u19-Prefixed} */ { M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bnor", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnor${X} ${BitBase32-24-u27-Prefixed} */ { M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bnor", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnor${X} $Bitno16R,$Bit16Rn */ { M32C_INSN_BNOR16_X_BIT16_16_BIT16_RN_DIRECT, "bnor16-X-bit16-16-bit16-Rn-direct", "bnor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnor${X} $Bitno16R,$Bit16An */ { M32C_INSN_BNOR16_X_BIT16_16_BIT16_AN_DIRECT, "bnor16-X-bit16-16-bit16-An-direct", "bnor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnor${X} [$Bit16An] */ { M32C_INSN_BNOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bnor16-X-bit16-16-bit16-An-indirect", "bnor", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnor${X} ${Dsp-16-u8}[$Bit16An] */ { M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bnor16-X-bit16-16-bit16-16-8-An-relative", "bnor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnor${X} ${Dsp-16-u16}[$Bit16An] */ { M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bnor16-X-bit16-16-bit16-16-16-An-relative", "bnor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnor${X} ${BitBase16-16-u8}[sb] */ { M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bnor16-X-bit16-16-bit16-16-8-SB-relative", "bnor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnor${X} ${BitBase16-16-u16}[sb] */ { M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bnor16-X-bit16-16-bit16-16-16-SB-relative", "bnor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnor${X} ${BitBase16-16-s8}[fb] */ { M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bnor16-X-bit16-16-bit16-16-8-FB-relative", "bnor", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnor${X} ${BitBase16-16-u16} */ { M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bnor16-X-bit16-16-bit16-16-16-absolute", "bnor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnand${X} $Bitno32Prefixed,$Bit32RnPrefixed */ { M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bnand", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnand${X} $Bitno32Prefixed,$Bit32AnPrefixed */ { M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bnand", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnand${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */ { M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bnand", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnand${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */ { M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bnand", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnand${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */ { M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bnand", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnand${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */ { M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bnand", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnand${X} ${BitBase32-24-u11-Prefixed}[sb] */ { M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bnand", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnand${X} ${BitBase32-24-u19-Prefixed}[sb] */ { M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bnand", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnand${X} ${BitBase32-24-s11-Prefixed}[fb] */ { M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bnand", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnand${X} ${BitBase32-24-s19-Prefixed}[fb] */ { M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bnand", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnand${X} ${BitBase32-24-u19-Prefixed} */ { M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bnand", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnand${X} ${BitBase32-24-u27-Prefixed} */ { M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bnand", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bnand${X} $Bitno16R,$Bit16Rn */ { M32C_INSN_BNAND16_X_BIT16_16_BIT16_RN_DIRECT, "bnand16-X-bit16-16-bit16-Rn-direct", "bnand", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnand${X} $Bitno16R,$Bit16An */ { M32C_INSN_BNAND16_X_BIT16_16_BIT16_AN_DIRECT, "bnand16-X-bit16-16-bit16-An-direct", "bnand", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnand${X} [$Bit16An] */ { M32C_INSN_BNAND16_X_BIT16_16_BIT16_AN_INDIRECT, "bnand16-X-bit16-16-bit16-An-indirect", "bnand", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnand${X} ${Dsp-16-u8}[$Bit16An] */ { M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bnand16-X-bit16-16-bit16-16-8-An-relative", "bnand", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnand${X} ${Dsp-16-u16}[$Bit16An] */ { M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bnand16-X-bit16-16-bit16-16-16-An-relative", "bnand", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnand${X} ${BitBase16-16-u8}[sb] */ { M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bnand16-X-bit16-16-bit16-16-8-SB-relative", "bnand", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnand${X} ${BitBase16-16-u16}[sb] */ { M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bnand16-X-bit16-16-bit16-16-16-SB-relative", "bnand", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnand${X} ${BitBase16-16-s8}[fb] */ { M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bnand16-X-bit16-16-bit16-16-8-FB-relative", "bnand", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bnand${X} ${BitBase16-16-u16} */ { M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bnand16-X-bit16-16-bit16-16-16-absolute", "bnand", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bm${cond32-16} $Bitno32Unprefixed,$Bit32RnUnprefixed */ { M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_RN_DIRECT_UNPREFIXED, "bm32-bit32-basic-Unprefixed-cond32-16-bit32-Rn-direct-Unprefixed", "bm", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bm${cond32-16} $Bitno32Unprefixed,$Bit32AnUnprefixed */ { M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_AN_DIRECT_UNPREFIXED, "bm32-bit32-basic-Unprefixed-cond32-16-bit32-An-direct-Unprefixed", "bm", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bm${cond32-16} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */ { M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_AN_INDIRECT_UNPREFIXED, "bm32-bit32-basic-Unprefixed-cond32-16-bit32-An-indirect-Unprefixed", "bm", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */ { M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bm32-bit32-16-8-Unprefixed-cond32-24-bit32-16-11-An-relative-Unprefixed", "bm", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[sb] */ { M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bm32-bit32-16-8-Unprefixed-cond32-24-bit32-16-11-SB-relative-Unprefixed", "bm", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bm${cond32-24} ${BitBase32-16-s11-Unprefixed}[fb] */ { M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bm32-bit32-16-8-Unprefixed-cond32-24-bit32-16-11-FB-relative-Unprefixed", "bm", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */ { M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-An-relative-Unprefixed", "bm", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[sb] */ { M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-SB-relative-Unprefixed", "bm", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bm${cond32-32} ${BitBase32-16-s19-Unprefixed}[fb] */ { M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-FB-relative-Unprefixed", "bm", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bm${cond32-32} ${BitBase32-16-u19-Unprefixed} */ { M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-absolute-Unprefixed", "bm", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bm${cond32-40} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */ { M32C_INSN_BM32_BIT32_16_24_UNPREFIXED_COND32_40_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bm32-bit32-16-24-Unprefixed-cond32-40-bit32-16-27-An-relative-Unprefixed", "bm", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bm${cond32-40} ${BitBase32-16-u27-Unprefixed} */ { M32C_INSN_BM32_BIT32_16_24_UNPREFIXED_COND32_40_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bm32-bit32-16-24-Unprefixed-cond32-40-bit32-16-27-absolute-Unprefixed", "bm", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bm${cond16-24} $Bitno16R,$Bit16Rn */ { M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_RN_DIRECT, "bm16-bit16-16-8-cond16-24-bit16-Rn-direct", "bm", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bm${cond16-24} $Bitno16R,$Bit16An */ { M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_AN_DIRECT, "bm16-bit16-16-8-cond16-24-bit16-An-direct", "bm", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bm${cond16-24} ${Dsp-16-u8}[$Bit16An] */ { M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_AN_RELATIVE, "bm16-bit16-16-8-cond16-24-bit16-16-8-An-relative", "bm", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bm${cond16-24} ${BitBase16-16-u8}[sb] */ { M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_SB_RELATIVE, "bm16-bit16-16-8-cond16-24-bit16-16-8-SB-relative", "bm", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bm${cond16-24} ${BitBase16-16-s8}[fb] */ { M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_FB_RELATIVE, "bm16-bit16-16-8-cond16-24-bit16-16-8-FB-relative", "bm", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bm${cond16-32} ${Dsp-16-u16}[$Bit16An] */ { M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_AN_RELATIVE, "bm16-bit16-16-16-cond16-32-bit16-16-16-An-relative", "bm", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bm${cond16-32} ${BitBase16-16-u16}[sb] */ { M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_SB_RELATIVE, "bm16-bit16-16-16-cond16-32-bit16-16-16-SB-relative", "bm", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bm${cond16-32} ${BitBase16-16-u16} */ { M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_ABSOLUTE, "bm16-bit16-16-16-cond16-32-bit16-16-16-absolute", "bm", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bm${cond16-16} [$Bit16An] */ { M32C_INSN_BM16_BIT16_16_BASIC_COND16_16_BIT16_AN_INDIRECT, "bm16-bit16-16-basic-cond16-16-bit16-An-indirect", "bm", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bitindex.w $Dst32RnUnprefixedHI */ { M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "bitindex.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bitindex.w $Dst32AnUnprefixedHI */ { M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "bitindex.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bitindex.w [$Dst32AnUnprefixed] */ { M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "bitindex.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bitindex.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "bitindex.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bitindex.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "bitindex.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bitindex.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "bitindex.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bitindex.w ${Dsp-16-u8}[sb] */ { M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "bitindex.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bitindex.w ${Dsp-16-u16}[sb] */ { M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "bitindex.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bitindex.w ${Dsp-16-s8}[fb] */ { M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "bitindex.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bitindex.w ${Dsp-16-s16}[fb] */ { M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "bitindex.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bitindex.w ${Dsp-16-u16} */ { M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "bitindex.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bitindex.w ${Dsp-16-u24} */ { M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "bitindex.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bitindex.b $Dst32RnUnprefixedQI */ { M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "bitindex.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bitindex.b $Dst32AnUnprefixedQI */ { M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "bitindex.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bitindex.b [$Dst32AnUnprefixed] */ { M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "bitindex.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bitindex.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "bitindex.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bitindex.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "bitindex.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bitindex.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "bitindex.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bitindex.b ${Dsp-16-u8}[sb] */ { M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "bitindex.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bitindex.b ${Dsp-16-u16}[sb] */ { M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "bitindex.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bitindex.b ${Dsp-16-s8}[fb] */ { M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "bitindex.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bitindex.b ${Dsp-16-s16}[fb] */ { M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "bitindex.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bitindex.b ${Dsp-16-u16} */ { M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "bitindex.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bitindex.b ${Dsp-16-u24} */ { M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "bitindex.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bclr${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */ { M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "bclr", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bclr${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */ { M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "bclr", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bclr${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */ { M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "bclr", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bclr${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */ { M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "bclr", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bclr${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */ { M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "bclr", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bclr${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */ { M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "bclr", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bclr${X} ${BitBase32-16-u11-Unprefixed}[sb] */ { M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "bclr", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bclr${X} ${BitBase32-16-u19-Unprefixed}[sb] */ { M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "bclr", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bclr${X} ${BitBase32-16-s11-Unprefixed}[fb] */ { M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "bclr", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bclr${X} ${BitBase32-16-s19-Unprefixed}[fb] */ { M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "bclr", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bclr${X} ${BitBase32-16-u19-Unprefixed} */ { M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "bclr", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bclr${X} ${BitBase32-16-u27-Unprefixed} */ { M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "bclr", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* bclr${G} $Bitno16R,$Bit16Rn */ { M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_RN_DIRECT, "bclr16-G-bit16-16-8-bit16-Rn-direct", "bclr", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bclr${G} $Bitno16R,$Bit16An */ { M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_AN_DIRECT, "bclr16-G-bit16-16-8-bit16-An-direct", "bclr", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bclr${G} ${Dsp-16-u8}[$Bit16An] */ { M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "bclr16-G-bit16-16-8-bit16-16-8-An-relative", "bclr", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bclr${G} ${BitBase16-16-u8}[sb] */ { M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "bclr16-G-bit16-16-8-bit16-16-8-SB-relative", "bclr", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bclr${G} ${BitBase16-16-s8}[fb] */ { M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "bclr16-G-bit16-16-8-bit16-16-8-FB-relative", "bclr", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bclr${S} ${BitBase16-8-u11-S}[sb] */ { M32C_INSN_BCLR16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "bclr16-S-bit16-11-S-bit16-11-SB-relative-S", "bclr", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bclr${G} ${Dsp-16-u16}[$Bit16An] */ { M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "bclr16-G-bit16-16-16-bit16-16-16-An-relative", "bclr", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bclr${G} ${BitBase16-16-u16}[sb] */ { M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "bclr16-G-bit16-16-16-bit16-16-16-SB-relative", "bclr", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bclr${G} ${BitBase16-16-u16} */ { M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "bclr16-G-bit16-16-16-bit16-16-16-absolute", "bclr", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bclr${G} [$Bit16An] */ { M32C_INSN_BCLR16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "bclr16-G-bit16-16-basic-bit16-An-indirect", "bclr", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* band${X} $Bitno32Prefixed,$Bit32RnPrefixed */ { M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "band", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* band${X} $Bitno32Prefixed,$Bit32AnPrefixed */ { M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "band", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* band${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */ { M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "band", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* band${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */ { M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "band", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* band${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */ { M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "band", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* band${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */ { M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "band", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* band${X} ${BitBase32-24-u11-Prefixed}[sb] */ { M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "band", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* band${X} ${BitBase32-24-u19-Prefixed}[sb] */ { M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "band", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* band${X} ${BitBase32-24-s11-Prefixed}[fb] */ { M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "band", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* band${X} ${BitBase32-24-s19-Prefixed}[fb] */ { M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "band", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* band${X} ${BitBase32-24-u19-Prefixed} */ { M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "band", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* band${X} ${BitBase32-24-u27-Prefixed} */ { M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "band", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* band${X} $Bitno16R,$Bit16Rn */ { M32C_INSN_BAND16_X_BIT16_16_BIT16_RN_DIRECT, "band16-X-bit16-16-bit16-Rn-direct", "band", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* band${X} $Bitno16R,$Bit16An */ { M32C_INSN_BAND16_X_BIT16_16_BIT16_AN_DIRECT, "band16-X-bit16-16-bit16-An-direct", "band", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* band${X} [$Bit16An] */ { M32C_INSN_BAND16_X_BIT16_16_BIT16_AN_INDIRECT, "band16-X-bit16-16-bit16-An-indirect", "band", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* band${X} ${Dsp-16-u8}[$Bit16An] */ { M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "band16-X-bit16-16-bit16-16-8-An-relative", "band", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* band${X} ${Dsp-16-u16}[$Bit16An] */ { M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "band16-X-bit16-16-bit16-16-16-An-relative", "band", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* band${X} ${BitBase16-16-u8}[sb] */ { M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "band16-X-bit16-16-bit16-16-8-SB-relative", "band", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* band${X} ${BitBase16-16-u16}[sb] */ { M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "band16-X-bit16-16-bit16-16-16-SB-relative", "band", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* band${X} ${BitBase16-16-s8}[fb] */ { M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "band16-X-bit16-16-bit16-16-8-FB-relative", "band", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* band${X} ${BitBase16-16-u16} */ { M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "band16-X-bit16-16-bit16-16-16-absolute", "band", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ { M32C_INSN_AND32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "and32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ { M32C_INSN_AND32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "and32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${S} #${Imm-24-HI},${Dsp-8-u16} */ { M32C_INSN_AND32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "and32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${S} #${Imm-8-HI},r0 */ { M32C_INSN_AND32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "and32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ { M32C_INSN_AND32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "and32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ { M32C_INSN_AND32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "and32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${S} #${Imm-24-QI},${Dsp-8-u16} */ { M32C_INSN_AND32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "and32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${S} #${Imm-8-QI},r0l */ { M32C_INSN_AND32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "and32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "and.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${S} ${SrcDst16-r0l-r0h-S-normal} */ { M32C_INSN_AND16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "and16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "and.b", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */ { M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "and16.b.S-src2-src16-2-S-8-SB-relative-QI", "and.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */ { M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "and16.b.S-src2-src16-2-S-8-FB-relative-QI", "and.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */ { M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "and16.b.S-src2-src16-2-S-16-absolute-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ { M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ { M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "and.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "and.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "and.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "and.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "and.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "and.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "and.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "and.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "and.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "and.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "and.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "and.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ { M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ { M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "and.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "and.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "and.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "and.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "and.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "and.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "and.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "and.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "and.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "and.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "and.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "and.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16},$Dst16RnHI */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16},$Dst16AnHI */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} $Src16RnHI,$Dst16RnHI */ { M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "and.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} $Src16AnHI,$Dst16RnHI */ { M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "and.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} [$Src16An],$Dst16RnHI */ { M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "and.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} $Src16RnHI,$Dst16AnHI */ { M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "and.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} $Src16AnHI,$Dst16AnHI */ { M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "and.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} [$Src16An],$Dst16AnHI */ { M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "and.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} $Src16RnHI,[$Dst16An] */ { M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "and.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} $Src16AnHI,[$Dst16An] */ { M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "and.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} [$Src16An],[$Dst16An] */ { M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "and.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "and.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} $Src16RnHI,${Dsp-16-u16} */ { M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} $Src16AnHI,${Dsp-16-u16} */ { M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16},$Dst16RnQI */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16},$Dst16AnQI */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} $Src16RnQI,$Dst16RnQI */ { M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "and.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} $Src16AnQI,$Dst16RnQI */ { M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "and.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} [$Src16An],$Dst16RnQI */ { M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "and.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} $Src16RnQI,$Dst16AnQI */ { M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "and.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} $Src16AnQI,$Dst16AnQI */ { M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "and.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} [$Src16An],$Dst16AnQI */ { M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "and.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} $Src16RnQI,[$Dst16An] */ { M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "and.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} $Src16AnQI,[$Dst16An] */ { M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "and.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} [$Src16An],[$Dst16An] */ { M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "and.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} $Src16RnQI,${Dsp-16-u16} */ { M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} $Src16AnQI,${Dsp-16-u16} */ { M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${S} #${Imm-8-QI},r0l */ { M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "and16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "and.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${S} #${Imm-8-QI},r0h */ { M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "and16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "and.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "and16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "and16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${S} #${Imm-8-QI},${Dsp-16-u16} */ { M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "and16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ { M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ { M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ { M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} #${Imm-40-HI},${Dsp-16-u24} */ { M32C_INSN_AND32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "and.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ { M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ { M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_AND32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.b${G} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_AND32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "and.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* and.w${G} #${Imm-16-HI},$Dst16RnHI */ { M32C_INSN_AND16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "and16.w-imm-G-basic-dst16-Rn-direct-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} #${Imm-16-HI},$Dst16AnHI */ { M32C_INSN_AND16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "and16.w-imm-G-basic-dst16-An-direct-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} #${Imm-16-HI},[$Dst16An] */ { M32C_INSN_AND16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "and16.w-imm-G-basic-dst16-An-indirect-HI", "and.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "and16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "and16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "and16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "and.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "and16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "and16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "and16.w-imm-G-16-16-dst16-16-16-absolute-HI", "and.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} #${Imm-16-QI},$Dst16RnQI */ { M32C_INSN_AND16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "and16.b-imm-G-basic-dst16-Rn-direct-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} #${Imm-16-QI},$Dst16AnQI */ { M32C_INSN_AND16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "and16.b-imm-G-basic-dst16-An-direct-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} #${Imm-16-QI},[$Dst16An] */ { M32C_INSN_AND16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "and16.b-imm-G-basic-dst16-An-indirect-QI", "and.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "and16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "and16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "and16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "and.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "and16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "and16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "and16.b-imm-G-16-16-dst16-16-16-absolute-QI", "and.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */ { M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "adjnz.w", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */ { M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "adjnz.w", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adjnz.w #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */ { M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "adjnz.w", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */ { M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "adjnz.w", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */ { M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "adjnz.w", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adjnz.w #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */ { M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "adjnz.w", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adjnz.w #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */ { M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "adjnz.w", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adjnz.w #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */ { M32C_INSN_ADJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "adjnz.w", 48, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adjnz.w #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */ { M32C_INSN_ADJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "adjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "adjnz.w", 48, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adjnz.w #${Imm-12-s4},$Dst32RnUnprefixedHI,${Lab-16-8} */ { M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "adjnz32.w-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "adjnz.w", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adjnz.w #${Imm-12-s4},$Dst32AnUnprefixedHI,${Lab-16-8} */ { M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "adjnz32.w-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "adjnz.w", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adjnz.w #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */ { M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "adjnz32.w-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "adjnz.w", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */ { M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "adjnz.b", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */ { M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "adjnz.b", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adjnz.b #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */ { M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "adjnz.b", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */ { M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "adjnz.b", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */ { M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "adjnz.b", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adjnz.b #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */ { M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "adjnz.b", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adjnz.b #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */ { M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "adjnz.b", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adjnz.b #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */ { M32C_INSN_ADJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "adjnz.b", 48, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adjnz.b #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */ { M32C_INSN_ADJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "adjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "adjnz.b", 48, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adjnz.b #${Imm-12-s4},$Dst32RnUnprefixedQI,${Lab-16-8} */ { M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "adjnz32.b-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "adjnz.b", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adjnz.b #${Imm-12-s4},$Dst32AnUnprefixedQI,${Lab-16-8} */ { M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "adjnz32.b-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "adjnz.b", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adjnz.b #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */ { M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "adjnz32.b-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "adjnz.b", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */ { M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_AN_RELATIVE_HI, "adjnz16.w-imm4-16-8-dst16-16-8-An-relative-HI", "adjnz.w", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */ { M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_SB_RELATIVE_HI, "adjnz16.w-imm4-16-8-dst16-16-8-SB-relative-HI", "adjnz.w", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adjnz.w #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */ { M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_FB_RELATIVE_HI, "adjnz16.w-imm4-16-8-dst16-16-8-FB-relative-HI", "adjnz.w", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */ { M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_AN_RELATIVE_HI, "adjnz16.w-imm4-16-16-dst16-16-16-An-relative-HI", "adjnz.w", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */ { M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_SB_RELATIVE_HI, "adjnz16.w-imm4-16-16-dst16-16-16-SB-relative-HI", "adjnz.w", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adjnz.w #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */ { M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_ABSOLUTE_HI, "adjnz16.w-imm4-16-16-dst16-16-16-absolute-HI", "adjnz.w", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adjnz.w #${Imm-8-s4},$Dst16RnHI,${Lab-16-8} */ { M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_RN_DIRECT_HI, "adjnz16.w-imm4-basic-dst16-Rn-direct-HI", "adjnz.w", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adjnz.w #${Imm-8-s4},$Dst16AnHI,${Lab-16-8} */ { M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_AN_DIRECT_HI, "adjnz16.w-imm4-basic-dst16-An-direct-HI", "adjnz.w", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adjnz.w #${Imm-8-s4},[$Dst16An],${Lab-16-8} */ { M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_AN_INDIRECT_HI, "adjnz16.w-imm4-basic-dst16-An-indirect-HI", "adjnz.w", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */ { M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_AN_RELATIVE_QI, "adjnz16.b-imm4-16-8-dst16-16-8-An-relative-QI", "adjnz.b", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */ { M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_SB_RELATIVE_QI, "adjnz16.b-imm4-16-8-dst16-16-8-SB-relative-QI", "adjnz.b", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adjnz.b #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */ { M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_FB_RELATIVE_QI, "adjnz16.b-imm4-16-8-dst16-16-8-FB-relative-QI", "adjnz.b", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */ { M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_AN_RELATIVE_QI, "adjnz16.b-imm4-16-16-dst16-16-16-An-relative-QI", "adjnz.b", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */ { M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_SB_RELATIVE_QI, "adjnz16.b-imm4-16-16-dst16-16-16-SB-relative-QI", "adjnz.b", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adjnz.b #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */ { M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_ABSOLUTE_QI, "adjnz16.b-imm4-16-16-dst16-16-16-absolute-QI", "adjnz.b", 40, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adjnz.b #${Imm-8-s4},$Dst16RnQI,${Lab-16-8} */ { M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_RN_DIRECT_QI, "adjnz16.b-imm4-basic-dst16-Rn-direct-QI", "adjnz.b", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adjnz.b #${Imm-8-s4},$Dst16AnQI,${Lab-16-8} */ { M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_AN_DIRECT_QI, "adjnz16.b-imm4-basic-dst16-An-direct-QI", "adjnz.b", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adjnz.b #${Imm-8-s4},[$Dst16An],${Lab-16-8} */ { M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_AN_INDIRECT_QI, "adjnz16.b-imm4-basic-dst16-An-indirect-QI", "adjnz.b", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16},$Dst32RnUnprefixedSI */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16},$Dst32AnUnprefixedSI */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u24},$Dst32RnUnprefixedSI */ { M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u24},$Dst32AnUnprefixedSI */ { M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "addx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "addx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "addx", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "addx", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "addx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "addx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "addx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "addx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "addx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "addx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "addx", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "addx", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "addx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "addx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "addx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ { M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "addx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ { M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "addx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "addx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "addx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADDX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* addx${X} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_ADDX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "addx", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ { M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ { M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadd.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadd.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadd.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadd.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadd.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadd.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadd.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadd.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadd.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadd.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadd.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadd.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ { M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ { M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadd.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadd.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadd.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadd.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadd.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadd.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadd.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadd.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadd.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadd.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadd.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadd.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ { M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ { M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dadd.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ { M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ { M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ { M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ { M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16} */ { M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24} */ { M32C_INSN_DADD32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ { M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ { M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dadd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dadd.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ { M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ { M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ { M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ { M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16} */ { M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADD32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24} */ { M32C_INSN_DADD32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ { M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ { M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadc.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadc.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadc.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadc.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ { M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ { M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadc.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadc.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadc.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadc.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ { M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ { M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dadc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ { M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ { M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ { M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ { M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16} */ { M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24} */ { M32C_INSN_DADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ { M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ { M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dadc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dadc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ { M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ { M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ { M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ { M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16} */ { M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_DADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24} */ { M32C_INSN_DADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ { M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ { M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "adc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "adc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "adc.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "adc.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "adc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "adc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "adc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "adc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "adc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "adc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "adc.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "adc.w", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ { M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ { M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ { M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ { M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "adc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "adc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "adc.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "adc.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ { M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ { M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ { M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "adc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ { M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "adc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ { M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ { M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ { M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "adc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ { M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "adc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ { M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "adc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ { M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "adc.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ { M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "adc.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ { M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "adc.b", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ { M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16},$Dst16RnHI */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16},$Dst16AnHI */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} $Src16RnHI,$Dst16RnHI */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "adc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} $Src16AnHI,$Dst16RnHI */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "adc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} [$Src16An],$Dst16RnHI */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "adc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} $Src16RnHI,$Dst16AnHI */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "adc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} $Src16AnHI,$Dst16AnHI */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "adc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} [$Src16An],$Dst16AnHI */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "adc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} $Src16RnHI,[$Dst16An] */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "adc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} $Src16AnHI,[$Dst16An] */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "adc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} [$Src16An],[$Dst16An] */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "adc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "adc.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} $Src16RnHI,${Dsp-16-u16} */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} $Src16AnHI,${Dsp-16-u16} */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16},$Dst16RnQI */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16},$Dst16AnQI */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} $Src16RnQI,$Dst16RnQI */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "adc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} $Src16AnQI,$Dst16RnQI */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "adc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} [$Src16An],$Dst16RnQI */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "adc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} $Src16RnQI,$Dst16AnQI */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "adc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} $Src16AnQI,$Dst16AnQI */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "adc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} [$Src16An],$Dst16AnQI */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "adc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} $Src16RnQI,[$Dst16An] */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "adc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} $Src16AnQI,[$Dst16An] */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "adc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} [$Src16An],[$Dst16An] */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "adc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} $Src16RnQI,${Dsp-16-u16} */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} $Src16AnQI,${Dsp-16-u16} */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ { M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ { M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ { M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ { M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ { M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ { M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} #${Imm-40-HI},${Dsp-24-u16} */ { M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "adc.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} #${Imm-48-HI},${Dsp-24-u24} */ { M32C_INSN_ADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "adc.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ { M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ { M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ { M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ { M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ { M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ { M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} #${Imm-40-QI},${Dsp-24-u16} */ { M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "adc.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ { M32C_INSN_ADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.b${X} #${Imm-48-QI},${Dsp-24-u24} */ { M32C_INSN_ADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "adc.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adc.w${X} #${Imm-16-HI},$Dst16RnHI */ { M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "adc16.w-imm-G-basic-dst16-Rn-direct-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} #${Imm-16-HI},$Dst16AnHI */ { M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "adc16.w-imm-G-basic-dst16-An-direct-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} #${Imm-16-HI},[$Dst16An] */ { M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "adc16.w-imm-G-basic-dst16-An-indirect-HI", "adc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "adc16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "adc16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "adc16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "adc.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "adc16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "adc16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.w${X} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "adc16.w-imm-G-16-16-dst16-16-16-absolute-HI", "adc.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} #${Imm-16-QI},$Dst16RnQI */ { M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "adc16.b-imm-G-basic-dst16-Rn-direct-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} #${Imm-16-QI},$Dst16AnQI */ { M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "adc16.b-imm-G-basic-dst16-An-direct-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} #${Imm-16-QI},[$Dst16An] */ { M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "adc16.b-imm-G-basic-dst16-An-indirect-QI", "adc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "adc16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "adc16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "adc16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "adc.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "adc16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "adc16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adc.b${X} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "adc16.b-imm-G-16-16-dst16-16-16-absolute-QI", "adc.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ { M32C_INSN_ADD32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "add32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ { M32C_INSN_ADD32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "add32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${S} #${Imm-24-HI},${Dsp-8-u16} */ { M32C_INSN_ADD32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "add32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${S} #${Imm-8-HI},r0 */ { M32C_INSN_ADD32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "add32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ { M32C_INSN_ADD32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "add32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ { M32C_INSN_ADD32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "add32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${S} #${Imm-24-QI},${Dsp-8-u16} */ { M32C_INSN_ADD32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "add32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${S} #${Imm-8-QI},r0l */ { M32C_INSN_ADD32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "add32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${S} #${Imm1-S},a0 */ { M32C_INSN_ADD32_L_S_IMM1_S_AN_DST32_1_S_A0_DIRECT_HI, "add32.l-s-imm1-S-an-dst32-1-S-A0-direct-HI", "add.l", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${S} #${Imm1-S},a1 */ { M32C_INSN_ADD32_L_S_IMM1_S_AN_DST32_1_S_A1_DIRECT_HI, "add32.l-s-imm1-S-an-dst32-1-S-A1-direct-HI", "add.l", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */ { M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */ { M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "add.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "add.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "add.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "add.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "add.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "add.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "add.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "add.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "add.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "add.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "add.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "add.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${S} ${SrcDst16-r0l-r0h-S-normal} */ { M32C_INSN_ADD16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "add16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "add.b", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */ { M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "add16.b.S-src2-src16-2-S-8-SB-relative-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */ { M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "add16.b.S-src2-src16-2-S-8-FB-relative-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */ { M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "add16.b.S-src2-src16-2-S-16-absolute-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ { M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ { M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "add.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "add.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "add.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "add.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "add.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "add.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "add.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "add.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "add.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "add.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "add.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "add.w", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ { M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ { M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ { M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "add.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "add.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "add.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "add.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ { M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ { M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ { M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "add.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ { M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "add.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ { M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ { M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ { M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "add.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ { M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "add.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ { M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "add.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ { M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "add.b", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ { M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "add.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ { M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "add.b", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ { M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16},$Dst16RnHI */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16},$Dst16AnHI */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} $Src16RnHI,$Dst16RnHI */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} $Src16AnHI,$Dst16RnHI */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} [$Src16An],$Dst16RnHI */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} $Src16RnHI,$Dst16AnHI */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} $Src16AnHI,$Dst16AnHI */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} [$Src16An],$Dst16AnHI */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} $Src16RnHI,[$Dst16An] */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} $Src16AnHI,[$Dst16An] */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} [$Src16An],[$Dst16An] */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} $Src16RnHI,${Dsp-16-u16} */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} $Src16AnHI,${Dsp-16-u16} */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ { M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16},$Dst16RnQI */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16},$Dst16AnQI */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16},[$Dst16An] */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ { M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} $Src16RnQI,$Dst16RnQI */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} $Src16AnQI,$Dst16RnQI */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} [$Src16An],$Dst16RnQI */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} $Src16RnQI,$Dst16AnQI */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} $Src16AnQI,$Dst16AnQI */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} [$Src16An],$Dst16AnQI */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} $Src16RnQI,[$Dst16An] */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} $Src16AnQI,[$Dst16An] */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} [$Src16An],[$Dst16An] */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} [$Src16An],${Dsp-16-u8}[sb] */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} [$Src16An],${Dsp-16-u16}[sb] */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} [$Src16An],${Dsp-16-s8}[fb] */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} $Src16RnQI,${Dsp-16-u16} */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} $Src16AnQI,${Dsp-16-u16} */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} [$Src16An],${Dsp-16-u16} */ { M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${S} #${Imm-8-QI},r0l */ { M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "add16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${S} #${Imm-8-QI},r0h */ { M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "add16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "add16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "add16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${S} #${Imm-8-QI},${Dsp-16-u16} */ { M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "add16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.l${Q} #${Imm-12-s4},$Dst32RnUnprefixedSI */ { M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "add.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${Q} #${Imm-12-s4},$Dst32AnUnprefixedSI */ { M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "add.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "add.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */ { M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${Q} #${Imm-12-s4},${Dsp-16-u16} */ { M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${Q} #${Imm-12-s4},${Dsp-16-u24} */ { M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */ { M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */ { M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */ { M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${Q} #${Imm-12-s4},${Dsp-16-u16} */ { M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${Q} #${Imm-12-s4},${Dsp-16-u24} */ { M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */ { M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */ { M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */ { M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${Q} #${Imm-12-s4},${Dsp-16-u16} */ { M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${Q} #${Imm-12-s4},${Dsp-16-u24} */ { M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${Q} #${Imm-8-s4},$Dst16RnHI */ { M32C_INSN_ADD16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "add16.w-imm4-Q-16-dst16-Rn-direct-HI", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${Q} #${Imm-8-s4},$Dst16AnHI */ { M32C_INSN_ADD16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "add16.w-imm4-Q-16-dst16-An-direct-HI", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${Q} #${Imm-8-s4},[$Dst16An] */ { M32C_INSN_ADD16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "add16.w-imm4-Q-16-dst16-An-indirect-HI", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "add.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${Q} #${Imm-8-s4},${Dsp-16-u16} */ { M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "add16.w-imm4-Q-16-dst16-16-16-absolute-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${Q} #${Imm-8-s4},$Dst16RnQI */ { M32C_INSN_ADD16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "add16.b-imm4-Q-16-dst16-Rn-direct-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${Q} #${Imm-8-s4},$Dst16AnQI */ { M32C_INSN_ADD16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "add16.b-imm4-Q-16-dst16-An-direct-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${Q} #${Imm-8-s4},[$Dst16An] */ { M32C_INSN_ADD16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "add16.b-imm4-Q-16-dst16-An-indirect-QI", "add.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */ { M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */ { M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */ { M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${Q} #${Imm-8-s4},${Dsp-16-u16} */ { M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "add16.b-imm4-Q-16-dst16-16-16-absolute-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ { M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ { M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ { M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} #${Imm-40-HI},${Dsp-16-u24} */ { M32C_INSN_ADD32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "add.w", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ { M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ { M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ { M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.b${G} #${Imm-40-QI},${Dsp-16-u24} */ { M32C_INSN_ADD32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "add.b", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.w${G} #${Imm-16-HI},$Dst16RnHI */ { M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "add16.w-imm-G-basic-dst16-Rn-direct-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} #${Imm-16-HI},$Dst16AnHI */ { M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "add16.w-imm-G-basic-dst16-An-direct-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} #${Imm-16-HI},[$Dst16An] */ { M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "add16.w-imm-G-basic-dst16-An-indirect-HI", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "add16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ { M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "add16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ { M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "add16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "add.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "add16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ { M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "add16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */ { M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "add16.w-imm-G-16-16-dst16-16-16-absolute-HI", "add.w", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} #${Imm-16-QI},$Dst16RnQI */ { M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "add16.b-imm-G-basic-dst16-Rn-direct-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} #${Imm-16-QI},$Dst16AnQI */ { M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "add16.b-imm-G-basic-dst16-An-direct-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} #${Imm-16-QI},[$Dst16An] */ { M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "add16.b-imm-G-basic-dst16-An-indirect-QI", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "add16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "add16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "add16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "add.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "add16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ { M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "add16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "add16.b-imm-G-16-16-dst16-16-16-absolute-QI", "add.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */ { M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */ { M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "add.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */ { M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */ { M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */ { M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */ { M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} #${Imm-32-SI},${Dsp-16-u16} */ { M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "add.l", 64, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADD32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l${G} #${Imm-40-SI},${Dsp-16-u24} */ { M32C_INSN_ADD32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "add.l", 72, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.w $Dst32RnUnprefixedHI */ { M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "adcf.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.w $Dst32AnUnprefixedHI */ { M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "adcf.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.w [$Dst32AnUnprefixed] */ { M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "adcf.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "adcf.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "adcf.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "adcf.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.w ${Dsp-16-u8}[sb] */ { M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "adcf.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.w ${Dsp-16-u16}[sb] */ { M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "adcf.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.w ${Dsp-16-s8}[fb] */ { M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "adcf.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.w ${Dsp-16-s16}[fb] */ { M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "adcf.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.w ${Dsp-16-u16} */ { M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "adcf.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.w ${Dsp-16-u24} */ { M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "adcf.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.b $Dst32RnUnprefixedQI */ { M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "adcf.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.b $Dst32AnUnprefixedQI */ { M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "adcf.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.b [$Dst32AnUnprefixed] */ { M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "adcf.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "adcf.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "adcf.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "adcf.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.b ${Dsp-16-u8}[sb] */ { M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "adcf.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.b ${Dsp-16-u16}[sb] */ { M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "adcf.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.b ${Dsp-16-s8}[fb] */ { M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "adcf.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.b ${Dsp-16-s16}[fb] */ { M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "adcf.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.b ${Dsp-16-u16} */ { M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "adcf.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.b ${Dsp-16-u24} */ { M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "adcf.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* adcf.w $Dst16RnHI */ { M32C_INSN_ADCF16_W_16_DST16_RN_DIRECT_HI, "adcf16.w-16-dst16-Rn-direct-HI", "adcf.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adcf.w $Dst16AnHI */ { M32C_INSN_ADCF16_W_16_DST16_AN_DIRECT_HI, "adcf16.w-16-dst16-An-direct-HI", "adcf.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adcf.w [$Dst16An] */ { M32C_INSN_ADCF16_W_16_DST16_AN_INDIRECT_HI, "adcf16.w-16-dst16-An-indirect-HI", "adcf.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adcf.w ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ADCF16_W_16_DST16_16_8_AN_RELATIVE_HI, "adcf16.w-16-dst16-16-8-An-relative-HI", "adcf.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adcf.w ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ADCF16_W_16_DST16_16_16_AN_RELATIVE_HI, "adcf16.w-16-dst16-16-16-An-relative-HI", "adcf.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adcf.w ${Dsp-16-u8}[sb] */ { M32C_INSN_ADCF16_W_16_DST16_16_8_SB_RELATIVE_HI, "adcf16.w-16-dst16-16-8-SB-relative-HI", "adcf.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adcf.w ${Dsp-16-u16}[sb] */ { M32C_INSN_ADCF16_W_16_DST16_16_16_SB_RELATIVE_HI, "adcf16.w-16-dst16-16-16-SB-relative-HI", "adcf.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adcf.w ${Dsp-16-s8}[fb] */ { M32C_INSN_ADCF16_W_16_DST16_16_8_FB_RELATIVE_HI, "adcf16.w-16-dst16-16-8-FB-relative-HI", "adcf.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adcf.w ${Dsp-16-u16} */ { M32C_INSN_ADCF16_W_16_DST16_16_16_ABSOLUTE_HI, "adcf16.w-16-dst16-16-16-absolute-HI", "adcf.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adcf.b $Dst16RnQI */ { M32C_INSN_ADCF16_B_16_DST16_RN_DIRECT_QI, "adcf16.b-16-dst16-Rn-direct-QI", "adcf.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adcf.b $Dst16AnQI */ { M32C_INSN_ADCF16_B_16_DST16_AN_DIRECT_QI, "adcf16.b-16-dst16-An-direct-QI", "adcf.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adcf.b [$Dst16An] */ { M32C_INSN_ADCF16_B_16_DST16_AN_INDIRECT_QI, "adcf16.b-16-dst16-An-indirect-QI", "adcf.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adcf.b ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ADCF16_B_16_DST16_16_8_AN_RELATIVE_QI, "adcf16.b-16-dst16-16-8-An-relative-QI", "adcf.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adcf.b ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ADCF16_B_16_DST16_16_16_AN_RELATIVE_QI, "adcf16.b-16-dst16-16-16-An-relative-QI", "adcf.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adcf.b ${Dsp-16-u8}[sb] */ { M32C_INSN_ADCF16_B_16_DST16_16_8_SB_RELATIVE_QI, "adcf16.b-16-dst16-16-8-SB-relative-QI", "adcf.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adcf.b ${Dsp-16-u16}[sb] */ { M32C_INSN_ADCF16_B_16_DST16_16_16_SB_RELATIVE_QI, "adcf16.b-16-dst16-16-16-SB-relative-QI", "adcf.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adcf.b ${Dsp-16-s8}[fb] */ { M32C_INSN_ADCF16_B_16_DST16_16_8_FB_RELATIVE_QI, "adcf16.b-16-dst16-16-8-FB-relative-QI", "adcf.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* adcf.b ${Dsp-16-u16} */ { M32C_INSN_ADCF16_B_16_DST16_16_16_ABSOLUTE_QI, "adcf16.b-16-dst16-16-16-absolute-QI", "adcf.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* abs.w $Dst32RnUnprefixedHI */ { M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "abs.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* abs.w $Dst32AnUnprefixedHI */ { M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "abs.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* abs.w [$Dst32AnUnprefixed] */ { M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "abs.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* abs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "abs.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* abs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "abs.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* abs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "abs.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* abs.w ${Dsp-16-u8}[sb] */ { M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "abs.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* abs.w ${Dsp-16-u16}[sb] */ { M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "abs.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* abs.w ${Dsp-16-s8}[fb] */ { M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "abs.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* abs.w ${Dsp-16-s16}[fb] */ { M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "abs.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* abs.w ${Dsp-16-u16} */ { M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "abs.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* abs.w ${Dsp-16-u24} */ { M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "abs.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* abs.b $Dst32RnUnprefixedQI */ { M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "abs.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* abs.b $Dst32AnUnprefixedQI */ { M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "abs.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* abs.b [$Dst32AnUnprefixed] */ { M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "abs.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* abs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "abs.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* abs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ { M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "abs.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* abs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "abs.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* abs.b ${Dsp-16-u8}[sb] */ { M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "abs.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* abs.b ${Dsp-16-u16}[sb] */ { M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "abs.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* abs.b ${Dsp-16-s8}[fb] */ { M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "abs.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* abs.b ${Dsp-16-s16}[fb] */ { M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "abs.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* abs.b ${Dsp-16-u16} */ { M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "abs.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* abs.b ${Dsp-16-u24} */ { M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "abs.b", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* abs.w $Dst16RnHI */ { M32C_INSN_ABS16_W_16_DST16_RN_DIRECT_HI, "abs16.w-16-dst16-Rn-direct-HI", "abs.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* abs.w $Dst16AnHI */ { M32C_INSN_ABS16_W_16_DST16_AN_DIRECT_HI, "abs16.w-16-dst16-An-direct-HI", "abs.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* abs.w [$Dst16An] */ { M32C_INSN_ABS16_W_16_DST16_AN_INDIRECT_HI, "abs16.w-16-dst16-An-indirect-HI", "abs.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* abs.w ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ABS16_W_16_DST16_16_8_AN_RELATIVE_HI, "abs16.w-16-dst16-16-8-An-relative-HI", "abs.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* abs.w ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ABS16_W_16_DST16_16_16_AN_RELATIVE_HI, "abs16.w-16-dst16-16-16-An-relative-HI", "abs.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* abs.w ${Dsp-16-u8}[sb] */ { M32C_INSN_ABS16_W_16_DST16_16_8_SB_RELATIVE_HI, "abs16.w-16-dst16-16-8-SB-relative-HI", "abs.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* abs.w ${Dsp-16-u16}[sb] */ { M32C_INSN_ABS16_W_16_DST16_16_16_SB_RELATIVE_HI, "abs16.w-16-dst16-16-16-SB-relative-HI", "abs.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* abs.w ${Dsp-16-s8}[fb] */ { M32C_INSN_ABS16_W_16_DST16_16_8_FB_RELATIVE_HI, "abs16.w-16-dst16-16-8-FB-relative-HI", "abs.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* abs.w ${Dsp-16-u16} */ { M32C_INSN_ABS16_W_16_DST16_16_16_ABSOLUTE_HI, "abs16.w-16-dst16-16-16-absolute-HI", "abs.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* abs.b $Dst16RnQI */ { M32C_INSN_ABS16_B_16_DST16_RN_DIRECT_QI, "abs16.b-16-dst16-Rn-direct-QI", "abs.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* abs.b $Dst16AnQI */ { M32C_INSN_ABS16_B_16_DST16_AN_DIRECT_QI, "abs16.b-16-dst16-An-direct-QI", "abs.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* abs.b [$Dst16An] */ { M32C_INSN_ABS16_B_16_DST16_AN_INDIRECT_QI, "abs16.b-16-dst16-An-indirect-QI", "abs.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* abs.b ${Dsp-16-u8}[$Dst16An] */ { M32C_INSN_ABS16_B_16_DST16_16_8_AN_RELATIVE_QI, "abs16.b-16-dst16-16-8-An-relative-QI", "abs.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* abs.b ${Dsp-16-u16}[$Dst16An] */ { M32C_INSN_ABS16_B_16_DST16_16_16_AN_RELATIVE_QI, "abs16.b-16-dst16-16-16-An-relative-QI", "abs.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* abs.b ${Dsp-16-u8}[sb] */ { M32C_INSN_ABS16_B_16_DST16_16_8_SB_RELATIVE_QI, "abs16.b-16-dst16-16-8-SB-relative-QI", "abs.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* abs.b ${Dsp-16-u16}[sb] */ { M32C_INSN_ABS16_B_16_DST16_16_16_SB_RELATIVE_QI, "abs16.b-16-dst16-16-16-SB-relative-QI", "abs.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* abs.b ${Dsp-16-s8}[fb] */ { M32C_INSN_ABS16_B_16_DST16_16_8_FB_RELATIVE_QI, "abs16.b-16-dst16-16-8-FB-relative-QI", "abs.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* abs.b ${Dsp-16-u16} */ { M32C_INSN_ABS16_B_16_DST16_16_16_ABSOLUTE_QI, "abs16.b-16-dst16-16-16-absolute-QI", "abs.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w$Q #${Imm-12-s4},sp */ { M32C_INSN_ADD16_WQ_SP, "add16-wQ-sp", "add.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.b$G #${Imm-16-QI},sp */ { M32C_INSN_ADD16_B_G_SP, "add16.b-G-sp", "add.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.w$G #${Imm-16-HI},sp */ { M32C_INSN_ADD16_W_G_SP, "add16.w-G-sp", "add.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* add.l$Q #${Imm3-S},sp */ { M32C_INSN_ADD32_L_IMM3_Q, "add32.l-imm3-Q", "add.l", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l$S #${Imm-16-QI},sp */ { M32C_INSN_ADD32_L_IMM8_S, "add32.l-imm8-S", "add.l", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* add.l$G #${Imm-16-HI},sp */ { M32C_INSN_ADD32_L_IMM16_G, "add32.l-imm16-G", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dadc.b #${Imm-16-QI} */ { M32C_INSN_DADC16_B_IMM8, "dadc16.b-imm8", "dadc.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* dadc.w #${Imm-16-HI} */ { M32C_INSN_DADC16_W_IMM16, "dadc16.w-imm16", "dadc.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* dadc.b r0h,r0l */ { M32C_INSN_DADC16_B_R0H_R0L, "dadc16.b-r0h-r0l", "dadc.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* dadc.w r1,r0 */ { M32C_INSN_DADC16_W_R1_R0, "dadc16.w-r1-r0", "dadc.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* dadd.b #${Imm-16-QI} */ { M32C_INSN_DADD16_B_IMM8, "dadd16.b-imm8", "dadd.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* dadd.w #${Imm-16-HI} */ { M32C_INSN_DADD16_W_IMM16, "dadd16.w-imm16", "dadd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* dadd.b r0h,r0l */ { M32C_INSN_DADD16_B_R0H_R0L, "dadd16.b-r0h-r0l", "dadd.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* dadd.w r1,r0 */ { M32C_INSN_DADD16_W_R1_R0, "dadd16.w-r1-r0", "dadd.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bm$cond16c c */ { M32C_INSN_BM16_C, "bm16-c", "bm", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* bm$cond32 c */ { M32C_INSN_BM32_C, "bm32-c", "bm", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* brk */ { M32C_INSN_BRK16, "brk16", "brk", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* brk */ { M32C_INSN_BRK32, "brk32", "brk", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* brk2 */ { M32C_INSN_BRK232, "brk232", "brk2", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dec.w ${Dst16An-S} */ { M32C_INSN_DEC16_W, "dec16.w", "dec.w", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* div.b #${Imm-16-QI} */ { M32C_INSN_DIV16_B_IMM_16_QI, "div16.b-Imm-16-QI", "div.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* div.w #${Imm-16-HI} */ { M32C_INSN_DIV16_W_IMM_16_HI, "div16.w-Imm-16-HI", "div.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* div.b #${Imm-16-QI} */ { M32C_INSN_DIV32_B_IMM_16_QI, "div32.b-Imm-16-QI", "div.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* div.w #${Imm-16-HI} */ { M32C_INSN_DIV32_W_IMM_16_HI, "div32.w-Imm-16-HI", "div.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.b #${Imm-16-QI} */ { M32C_INSN_DIVU16_B_IMM_16_QI, "divu16.b-Imm-16-QI", "divu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divu.w #${Imm-16-HI} */ { M32C_INSN_DIVU16_W_IMM_16_HI, "divu16.w-Imm-16-HI", "divu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divu.b #${Imm-16-QI} */ { M32C_INSN_DIVU32_B_IMM_16_QI, "divu32.b-Imm-16-QI", "divu.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divu.w #${Imm-16-HI} */ { M32C_INSN_DIVU32_W_IMM_16_HI, "divu32.w-Imm-16-HI", "divu.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.b #${Imm-16-QI} */ { M32C_INSN_DIVX16_B_IMM_16_QI, "divx16.b-Imm-16-QI", "divx.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divx.w #${Imm-16-HI} */ { M32C_INSN_DIVX16_W_IMM_16_HI, "divx16.w-Imm-16-HI", "divx.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* divx.b #${Imm-16-QI} */ { M32C_INSN_DIVX32_B_IMM_16_QI, "divx32.b-Imm-16-QI", "divx.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* divx.w #${Imm-16-HI} */ { M32C_INSN_DIVX32_W_IMM_16_HI, "divx32.w-Imm-16-HI", "divx.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dsbb.b #${Imm-16-QI} */ { M32C_INSN_DSBB16_B_IMM8, "dsbb16.b-imm8", "dsbb.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* dsbb.w #${Imm-16-HI} */ { M32C_INSN_DSBB16_W_IMM16, "dsbb16.w-imm16", "dsbb.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* dsbb.b r0h,r0l */ { M32C_INSN_DSBB16_B_R0H_R0L, "dsbb16.b-r0h-r0l", "dsbb.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* dsbb.w r1,r0 */ { M32C_INSN_DSBB16_W_R1_R0, "dsbb16.w-r1-r0", "dsbb.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* dsub.b #${Imm-16-QI} */ { M32C_INSN_DSUB16_B_IMM8, "dsub16.b-imm8", "dsub.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* dsub.w #${Imm-16-HI} */ { M32C_INSN_DSUB16_W_IMM16, "dsub16.w-imm16", "dsub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* dsub.b r0h,r0l */ { M32C_INSN_DSUB16_B_R0H_R0L, "dsub16.b-r0h-r0l", "dsub.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* dsub.w r1,r0 */ { M32C_INSN_DSUB16_W_R1_R0, "dsub16.w-r1-r0", "dsub.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* enter #${Dsp-16-u8} */ { M32C_INSN_ENTER16, "enter16", "enter", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* exitd */ { M32C_INSN_EXITD16, "exitd16", "exitd", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* enter #${Dsp-8-u8} */ { M32C_INSN_ENTER32, "enter32", "enter", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exitd */ { M32C_INSN_EXITD32, "exitd32", "exitd", 8, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* fclr ${flags16} */ { M32C_INSN_FCLR16, "fclr16", "fclr", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* fset ${flags16} */ { M32C_INSN_FSET16, "fset16", "fset", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* fclr ${flags32} */ { M32C_INSN_FCLR, "fclr", "fclr", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* fset ${flags32} */ { M32C_INSN_FSET, "fset", "fset", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* inc.w ${Dst16An-S} */ { M32C_INSN_INC16_W, "inc16.w", "inc.w", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* freit */ { M32C_INSN_FREIT32, "freit32", "freit", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* int #${Dsp-10-u6} */ { M32C_INSN_INT16, "int16", "int", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* into */ { M32C_INSN_INTO16, "into16", "into", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* int #${Dsp-8-u6} */ { M32C_INSN_INT32, "int32", "int", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* into */ { M32C_INSN_INTO32, "into32", "into", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* j$cond16j5 ${Lab-8-8} */ { M32C_INSN_JCND16_5, "jcnd16-5", "j", 16, - { 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* j$cond16j ${Lab-16-8} */ { M32C_INSN_JCND16, "jcnd16", "j", 24, - { 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* j$cond32j ${Lab-8-8} */ { M32C_INSN_JCND32, "jcnd32", "j", 16, - { 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmp.s ${Lab-5-3} */ { M32C_INSN_JMP16_S, "jmp16.s", "jmp.s", 8, - { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jmp.b ${Lab-8-8} */ { M32C_INSN_JMP16_B, "jmp16.b", "jmp.b", 16, - { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jmp.w ${Lab-8-16} */ { M32C_INSN_JMP16_W, "jmp16.w", "jmp.w", 24, - { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jmp.a ${Lab-8-24} */ { M32C_INSN_JMP16_A, "jmp16.a", "jmp.a", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jmps #${Imm-8-QI} */ { M32C_INSN_JMPS16, "jmps16", "jmps", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jmp.s ${Lab32-jmp-s} */ { M32C_INSN_JMP32_S, "jmp32.s", "jmp.s", 8, - { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmp.b ${Lab-8-8} */ { M32C_INSN_JMP32_B, "jmp32.b", "jmp.b", 16, - { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmp.w ${Lab-8-16} */ { M32C_INSN_JMP32_W, "jmp32.w", "jmp.w", 24, - { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmp.a ${Lab-8-24} */ { M32C_INSN_JMP32_A, "jmp32.a", "jmp.a", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jmps #${Imm-8-QI} */ { M32C_INSN_JMPS32, "jmps32", "jmps", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsr.w ${Lab-8-16} */ { M32C_INSN_JSR16_W, "jsr16.w", "jsr.w", 24, - { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jsr.a ${Lab-8-24} */ { M32C_INSN_JSR16_A, "jsr16.a", "jsr.a", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jsr.w ${Lab-8-16} */ { M32C_INSN_JSR32_W, "jsr32.w", "jsr.w", 24, - { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsr.a ${Lab-8-24} */ { M32C_INSN_JSR32_A, "jsr32.a", "jsr.a", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* jsrs #${Imm-8-QI} */ { M32C_INSN_JSRS16, "jsrs16", "jsrs", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* jsrs #${Imm-8-QI} */ { M32C_INSN_JSRS, "jsrs", "jsrs", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc #${Imm-16-HI},${cr16} */ { M32C_INSN_LDC16_IMM16, "ldc16.imm16", "ldc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ldc #${Imm-16-HI},${cr1-Unprefixed-32} */ { M32C_INSN_LDC32_IMM16_CR1, "ldc32.imm16-cr1", "ldc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc #${Dsp-16-u24},${cr2-32} */ { M32C_INSN_LDC32_IMM16_CR2, "ldc32.imm16-cr2", "ldc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldc #${Dsp-16-u24},${cr3-Unprefixed-32} */ { M32C_INSN_LDC32_IMM16_CR3, "ldc32.imm16-cr3", "ldc", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldctx ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_LDCTX16, "ldctx16", "ldctx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ldctx ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_LDCTX32, "ldctx32", "ldctx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stctx ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_STCTX16, "stctx16", "stctx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stctx ${Dsp-16-u16},${Dsp-32-u24} */ { M32C_INSN_STCTX32, "stctx32", "stctx", 56, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* ldipl #${Imm-13-u3} */ { M32C_INSN_LDIPL16_IMM, "ldipl16.imm", "ldipl", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* ldipl #${Imm-13-u3} */ { M32C_INSN_LDIPL32_IMM, "ldipl32.imm", "ldipl", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b$S #${Imm-8-QI},a0 */ { M32C_INSN_MOV16_B_S_IMM_A0, "mov16.b.S-imm-a0", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b$S #${Imm-8-QI},a1 */ { M32C_INSN_MOV16_B_S_IMM_A1, "mov16.b.S-imm-a1", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w$S #${Imm-8-HI},a0 */ { M32C_INSN_MOV16_W_S_IMM_A0, "mov16.w.S-imm-a0", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w$S #${Imm-8-HI},a1 */ { M32C_INSN_MOV16_W_S_IMM_A1, "mov16.w.S-imm-a1", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.w$S #${Imm-8-HI},a0 */ { M32C_INSN_MOV32_W_A0, "mov32-w-a0", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.w$S #${Imm-8-HI},a1 */ { M32C_INSN_MOV32_W_A1, "mov32-w-a1", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l$S #${Dsp-8-s24},a0 */ { M32C_INSN_MOV32_L_A0, "mov32-l-a0", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.l$S #${Dsp-8-s24},a1 */ { M32C_INSN_MOV32_L_A1, "mov32-l-a1", "mov.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mov.b$S r0l,a1 */ { M32C_INSN_MOV16_B_S_R0L_A1, "mov16.b.S-r0l-a1", "mov.b", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mov.b$S r0h,a0 */ { M32C_INSN_MOV16_B_S_R0H_A0, "mov16.b.S-r0h-a0", "mov.b", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* nop */ { M32C_INSN_NOP16, "nop16", "nop", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* nop */ { M32C_INSN_NOP32, "nop32", "nop", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* popc ${cr16} */ { M32C_INSN_POPC16_IMM16, "popc16.imm16", "popc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* popc ${cr1-Unprefixed-32} */ { M32C_INSN_POPC32_IMM16_CR1, "popc32.imm16-cr1", "popc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* popc ${cr2-32} */ { M32C_INSN_POPC32_IMM16_CR2, "popc32.imm16-cr2", "popc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pushc ${cr16} */ { M32C_INSN_PUSHC16_IMM16, "pushc16.imm16", "pushc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pushc ${cr1-Unprefixed-32} */ { M32C_INSN_PUSHC32_IMM16_CR1, "pushc32.imm16-cr1", "pushc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pushc ${cr2-32} */ { M32C_INSN_PUSHC32_IMM16_CR2, "pushc32.imm16-cr2", "pushc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* popm ${Regsetpop} */ { M32C_INSN_POPM16, "popm16", "popm", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pushm ${Regsetpush} */ { M32C_INSN_PUSHM16, "pushm16", "pushm", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* popm ${Regsetpop} */ { M32C_INSN_POPM, "popm", "popm", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* pushm ${Regsetpush} */ { M32C_INSN_PUSHM, "pushm", "pushm", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.b$G #${Imm-16-QI} */ { M32C_INSN_PUSH16_B_G_IMM, "push16.b.G-imm", "push.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* push.w$G #${Imm-16-HI} */ { M32C_INSN_PUSH16_W_G_IMM, "push16.w.G-imm", "push.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* push.b #Imm-8-QI */ { M32C_INSN_PUSH32_B_IMM, "push32.b.imm", "push.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.w #${Imm-8-HI} */ { M32C_INSN_PUSH32_W_IMM, "push32.w.imm", "push.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* push.l #${Imm-16-SI} */ { M32C_INSN_PUSH32_L_IMM, "push32.l.imm", "push.l", 48, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* reit */ { M32C_INSN_REIT16, "reit16", "reit", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* reit */ { M32C_INSN_REIT32, "reit32", "reit", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rmpa.b */ { M32C_INSN_RMPA16_B, "rmpa16.b", "rmpa.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rmpa.w */ { M32C_INSN_RMPA16_W, "rmpa16.w", "rmpa.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rmpa.b */ { M32C_INSN_RMPA32_B, "rmpa32.b", "rmpa.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rmpa.w */ { M32C_INSN_RMPA32_W, "rmpa32.w", "rmpa.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rts */ { M32C_INSN_RTS16, "rts16", "rts", 8, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rts */ { M32C_INSN_RTS32, "rts32", "rts", 8, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* scmpu.b */ { M32C_INSN_SCMPU_B, "scmpu.b", "scmpu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* scmpu.w */ { M32C_INSN_SCMPU_W, "scmpu.w", "scmpu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sha.l #${Imm-sh-12-s4},r2r0 */ { M32C_INSN_SHA16_L_IMM_R2R0, "sha16-L-imm-r2r0", "sha.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.l #${Imm-sh-12-s4},r3r1 */ { M32C_INSN_SHA16_L_IMM_R3R1, "sha16-L-imm-r3r1", "sha.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.l r1h,r2r0 */ { M32C_INSN_SHA16_L_R1H_R2R0, "sha16-L-r1h-r2r0", "sha.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sha.l r1h,r3r1 */ { M32C_INSN_SHA16_L_R1H_R3R1, "sha16-L-r1h-r3r1", "sha.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.l #${Imm-sh-12-s4},r2r0 */ { M32C_INSN_SHL16_L_IMM_R2R0, "shl16-L-imm-r2r0", "shl.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.l #${Imm-sh-12-s4},r3r1 */ { M32C_INSN_SHL16_L_IMM_R3R1, "shl16-L-imm-r3r1", "shl.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.l r1h,r2r0 */ { M32C_INSN_SHL16_L_R1H_R2R0, "shl16-L-r1h-r2r0", "shl.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* shl.l r1h,r3r1 */ { M32C_INSN_SHL16_L_R1H_R3R1, "shl16-L-r1h-r3r1", "shl.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sin.b */ { M32C_INSN_SIN32_B, "sin32.b", "sin.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sin.w */ { M32C_INSN_SIN32_W, "sin32.w", "sin.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* smovb.b */ { M32C_INSN_SMOVB16_B, "smovb16.b", "smovb.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* smovb.w */ { M32C_INSN_SMOVB16_W, "smovb16.w", "smovb.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* smovb.b */ { M32C_INSN_SMOVB32_B, "smovb32.b", "smovb.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* smovb.w */ { M32C_INSN_SMOVB32_W, "smovb32.w", "smovb.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* smovf.b */ { M32C_INSN_SMOVF16_B, "smovf16.b", "smovf.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* smovf.w */ { M32C_INSN_SMOVF16_W, "smovf16.w", "smovf.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* smovf.b */ { M32C_INSN_SMOVF32_B, "smovf32.b", "smovf.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* smovf.w */ { M32C_INSN_SMOVF32_W, "smovf32.w", "smovf.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* smovu.b */ { M32C_INSN_SMOVU_B, "smovu.b", "smovu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* smovu.w */ { M32C_INSN_SMOVU_W, "smovu.w", "smovu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sout.b */ { M32C_INSN_SOUT_B, "sout.b", "sout.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sout.w */ { M32C_INSN_SOUT_W, "sout.w", "sout.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sstr.b */ { M32C_INSN_SSTR16_B, "sstr16.b", "sstr.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sstr.w */ { M32C_INSN_SSTR16_W, "sstr16.w", "sstr.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sstr.b */ { M32C_INSN_SSTR_B, "sstr.b", "sstr.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* sstr.w */ { M32C_INSN_SSTR_W, "sstr.w", "sstr.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* stzx #${Imm-8-QI},#${Imm-16-QI},r0h */ { M32C_INSN_STZX16_IMM8_IMM8_R0H, "stzx16-imm8-imm8-r0h", "stzx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stzx #${Imm-8-QI},#${Imm-16-QI},r0l */ { M32C_INSN_STZX16_IMM8_IMM8_R0L, "stzx16-imm8-imm8-r0l", "stzx", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-u8}[sb] */ { M32C_INSN_STZX16_IMM8_IMM8_DSP8SB, "stzx16-imm8-imm8-dsp8sb", "stzx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-s8}[fb] */ { M32C_INSN_STZX16_IMM8_IMM8_DSP8FB, "stzx16-imm8-imm8-dsp8fb", "stzx", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* stzx #${Imm-8-QI},#${Imm-32-QI},${Dsp-16-u16} */ { M32C_INSN_STZX16_IMM8_IMM8_ABS16, "stzx16-imm8-imm8-abs16", "stzx", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* und */ { M32C_INSN_UND16, "und16", "und", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* und */ { M32C_INSN_UND32, "und32", "und", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* wait */ { M32C_INSN_WAIT16, "wait16", "wait", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* wait */ { M32C_INSN_WAIT, "wait", "wait", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* exts.w r0 */ { M32C_INSN_EXTS16_W_R0, "exts16.w-r0", "exts.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* src-indirect */ { M32C_INSN_SRCIND, "srcind", "src-indirect", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* dest-indirect */ { M32C_INSN_DESTIND, "destind", "dest-indirect", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* src-dest-indirect */ { M32C_INSN_SRCDESTIND, "srcdestind", "src-dest-indirect", 8, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, }; @@ -62786,7 +62786,7 @@ static void m32c_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) { int i; - unsigned int isas = cd->isas; + CGEN_BITSET *isas = cd->isas; unsigned int machs = cd->machs; cd->int_insn_p = CGEN_INT_INSN_P; @@ -62798,7 +62798,7 @@ m32c_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) - if (((1 << i) & isas) != 0) + if (cgen_bitset_contains (isas, i)) { const CGEN_ISA *isa = & m32c_cgen_isa_table[i]; @@ -62883,7 +62883,7 @@ m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) { CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); static int init_p; - unsigned int isas = 0; /* 0 = "unspecified" */ + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ unsigned int machs = 0; /* 0 = "unspecified" */ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; va_list ap; @@ -62902,7 +62902,7 @@ m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) switch (arg_type) { case CGEN_CPU_OPEN_ISAS : - isas = va_arg (ap, unsigned int); + isas = va_arg (ap, CGEN_BITSET *); break; case CGEN_CPU_OPEN_MACHS : machs = va_arg (ap, unsigned int); @@ -62933,9 +62933,6 @@ m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) machs = (1 << MAX_MACHS) - 1; /* Base mach is always selected. */ machs |= 1; - /* ISA unspecified means "all". */ - if (isas == 0) - isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) { /* ??? If target has only one, could have a default. */ @@ -62943,7 +62940,7 @@ m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) abort (); } - cd->isas = isas; + cd->isas = cgen_bitset_copy (isas); cd->machs = machs; cd->endian = endian; /* FIXME: for the sparc case we can determine insn-endianness statically. diff --git a/opcodes/m32c-desc.h b/opcodes/m32c-desc.h index b969707ebd2..3fa1db9e435 100644 --- a/opcodes/m32c-desc.h +++ b/opcodes/m32c-desc.h @@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc., #ifndef M32C_CPU_H #define M32C_CPU_H +#include "opcode/cgen-bitset.h" + #define CGEN_ARCH m32c /* Given symbol S, return m32c_cgen_<S>. */ @@ -92,6 +94,16 @@ typedef enum cgen_ifld_attr { /* Number of non-boolean elements in cgen_ifld_attr. */ #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) + /* Enum declaration for m32c ifield types. */ typedef enum ifield_type { M32C_F_NIL, M32C_F_ANYOF, M32C_F_0_1, M32C_F_0_2 @@ -150,6 +162,14 @@ typedef enum cgen_hw_attr { /* Number of non-boolean elements in cgen_hw_attr. */ #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) + /* Enum declaration for m32c hardware types. */ typedef enum cgen_hw_type { HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR @@ -188,6 +208,18 @@ typedef enum cgen_operand_attr { /* Number of non-boolean elements in cgen_operand_attr. */ #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) + /* Enum declaration for m32c operand types. */ typedef enum cgen_operand_type { M32C_OPERAND_PC, M32C_OPERAND_SRC16RNQI, M32C_OPERAND_SRC16RNHI, M32C_OPERAND_SRC32RNUNPREFIXEDQI @@ -430,6 +462,20 @@ typedef enum cgen_insn_attr { /* Number of non-boolean elements in cgen_insn_attr. */ #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) + /* cgen.h uses things we just defined. */ #include "opcode/cgen.h" diff --git a/opcodes/m32c-dis.c b/opcodes/m32c-dis.c index cfa3517cb1b..43f93e2b2b8 100644 --- a/opcodes/m32c-dis.c +++ b/opcodes/m32c-dis.c @@ -4,7 +4,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-dis.in isn't - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -1190,7 +1190,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) typedef struct cpu_desc_list { struct cpu_desc_list *next; - int isa; + CGEN_BITSET *isa; int mach; int endian; CGEN_CPU_DESC cd; @@ -1202,11 +1202,12 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info) static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; static CGEN_CPU_DESC cd = 0; - static int prev_isa; + static CGEN_BITSET *prev_isa; static int prev_mach; static int prev_endian; int length; - int isa,mach; + CGEN_BITSET *isa; + int mach; int endian = (info->endian == BFD_ENDIAN_BIG ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); @@ -1229,25 +1230,34 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info) #endif #ifdef CGEN_COMPUTE_ISA - isa = CGEN_COMPUTE_ISA (info); + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } #else isa = info->insn_sets; #endif /* If we've switched cpu's, try to find a handle we've used before */ if (cd - && (isa != prev_isa + && (cgen_bitset_compare (isa, prev_isa) != 0 || mach != prev_mach || endian != prev_endian)) { cd = 0; for (cl = cd_list; cl; cl = cl->next) { - if (cl->isa == isa && + if (cgen_bitset_compare (cl->isa, isa) == 0 && cl->mach == mach && cl->endian == endian) { cd = cl->cd; + prev_isa = cd->isas; break; } } @@ -1263,7 +1273,7 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info) abort (); mach_name = arch_type->printable_name; - prev_isa = isa; + prev_isa = cgen_bitset_copy (isa); prev_mach = mach; prev_endian = endian; cd = m32c_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, @@ -1276,7 +1286,7 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info) /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; - cl->isa = isa; + cl->isa = prev_isa; cl->mach = mach; cl->endian = endian; cl->next = cd_list; diff --git a/opcodes/m32c-opc.c b/opcodes/m32c-opc.c index 185abad1f1d..0913c2cb22b 100644 --- a/opcodes/m32c-opc.c +++ b/opcodes/m32c-opc.c @@ -79916,7 +79916,7 @@ static const CGEN_IBASE m32c_cgen_macro_insn_table[] = /* add.b:q #${Imm-12-s4},sp */ { -1, "add16-bQ-sp", "add.b:q", 16, - { 0|A(ALIAS), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, }; diff --git a/opcodes/m32r-desc.c b/opcodes/m32r-desc.c index 3b8cb56c7c9..c9cd3bb5163 100644 --- a/opcodes/m32r-desc.c +++ b/opcodes/m32r-desc.c @@ -148,25 +148,25 @@ static const CGEN_MACH m32r_cgen_mach_table[] = { static CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] = { - { "fp", 13, {0, {0}}, 0, 0 }, - { "lr", 14, {0, {0}}, 0, 0 }, - { "sp", 15, {0, {0}}, 0, 0 }, - { "r0", 0, {0, {0}}, 0, 0 }, - { "r1", 1, {0, {0}}, 0, 0 }, - { "r2", 2, {0, {0}}, 0, 0 }, - { "r3", 3, {0, {0}}, 0, 0 }, - { "r4", 4, {0, {0}}, 0, 0 }, - { "r5", 5, {0, {0}}, 0, 0 }, - { "r6", 6, {0, {0}}, 0, 0 }, - { "r7", 7, {0, {0}}, 0, 0 }, - { "r8", 8, {0, {0}}, 0, 0 }, - { "r9", 9, {0, {0}}, 0, 0 }, - { "r10", 10, {0, {0}}, 0, 0 }, - { "r11", 11, {0, {0}}, 0, 0 }, - { "r12", 12, {0, {0}}, 0, 0 }, - { "r13", 13, {0, {0}}, 0, 0 }, - { "r14", 14, {0, {0}}, 0, 0 }, - { "r15", 15, {0, {0}}, 0, 0 } + { "fp", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "lr", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "r15", 15, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32r_cgen_opval_gr_names = @@ -178,30 +178,30 @@ CGEN_KEYWORD m32r_cgen_opval_gr_names = static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] = { - { "psw", 0, {0, {0}}, 0, 0 }, - { "cbr", 1, {0, {0}}, 0, 0 }, - { "spi", 2, {0, {0}}, 0, 0 }, - { "spu", 3, {0, {0}}, 0, 0 }, - { "bpc", 6, {0, {0}}, 0, 0 }, - { "bbpsw", 8, {0, {0}}, 0, 0 }, - { "bbpc", 14, {0, {0}}, 0, 0 }, - { "evb", 5, {0, {0}}, 0, 0 }, - { "cr0", 0, {0, {0}}, 0, 0 }, - { "cr1", 1, {0, {0}}, 0, 0 }, - { "cr2", 2, {0, {0}}, 0, 0 }, - { "cr3", 3, {0, {0}}, 0, 0 }, - { "cr4", 4, {0, {0}}, 0, 0 }, - { "cr5", 5, {0, {0}}, 0, 0 }, - { "cr6", 6, {0, {0}}, 0, 0 }, - { "cr7", 7, {0, {0}}, 0, 0 }, - { "cr8", 8, {0, {0}}, 0, 0 }, - { "cr9", 9, {0, {0}}, 0, 0 }, - { "cr10", 10, {0, {0}}, 0, 0 }, - { "cr11", 11, {0, {0}}, 0, 0 }, - { "cr12", 12, {0, {0}}, 0, 0 }, - { "cr13", 13, {0, {0}}, 0, 0 }, - { "cr14", 14, {0, {0}}, 0, 0 }, - { "cr15", 15, {0, {0}}, 0, 0 } + { "psw", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "cbr", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "spi", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "spu", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "bpc", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "bbpsw", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "bbpc", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "evb", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "cr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "cr1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "cr2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "cr3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "cr4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "cr5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "cr6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "cr7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "cr8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "cr9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "cr10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "cr11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "cr12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "cr13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "cr14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "cr15", 15, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32r_cgen_opval_cr_names = @@ -213,8 +213,8 @@ CGEN_KEYWORD m32r_cgen_opval_cr_names = static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] = { - { "a0", 0, {0, {0}}, 0, 0 }, - { "a1", 1, {0, {0}}, 0, 0 } + { "a0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "a1", 1, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD m32r_cgen_opval_h_accums = @@ -235,25 +235,25 @@ CGEN_KEYWORD m32r_cgen_opval_h_accums = const CGEN_HW_ENTRY m32r_cgen_hw_table[] = { - { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } }, - { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } }, - { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } }, - { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } } }, - { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} } + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } }, + { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } }; #undef A @@ -269,36 +269,36 @@ const CGEN_HW_ENTRY m32r_cgen_hw_table[] = const CGEN_IFLD m32r_cgen_ifld_table[] = { - { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, - { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, - { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } } }, - { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } }, - { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } }, - { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } }, - { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } }, - { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } }, - { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } }, - { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } } }, - { M32R_F_UIMM3, "f-uimm3", 0, 32, 5, 3, { 0, { (1<<MACH_BASE) } } }, - { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } }, - { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { (1<<MACH_BASE) } } }, - { M32R_F_UIMM8, "f-uimm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } }, - { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } }, - { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } } }, - { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } }, - { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, - { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, - { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, - { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } } }, - { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { (1<<MACH_BASE) } } }, - { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } } }, - { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { (1<<MACH_BASE) } } }, - { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { (1<<MACH_BASE) } } }, - { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { (1<<MACH_BASE) } } }, - { M32R_F_BIT4, "f-bit4", 0, 32, 4, 1, { 0, { (1<<MACH_BASE) } } }, - { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } } }, - { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } }, - { 0, 0, 0, 0, 0, 0, {0, {0}} } + { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_UIMM3, "f-uimm3", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_UIMM8, "f-uimm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_BIT4, "f-bit4", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } }; #undef A @@ -330,119 +330,119 @@ const CGEN_OPERAND m32r_cgen_operand_table[] = /* pc: program counter */ { "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_NIL] } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* sr: source register */ { "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* dr: destination register */ { "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* src1: source register 1 */ { "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* src2: source register 2 */ { "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* scr: source control register */ { "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* dcr: destination control register */ { "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* simm8: 8 bit signed immediate */ { "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM8] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* simm16: 16 bit signed immediate */ { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* uimm3: 3 bit unsigned number */ { "uimm3", M32R_OPERAND_UIMM3, HW_H_UINT, 5, 3, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM3] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* uimm4: 4 bit trap number */ { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM4] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* uimm5: 5 bit shift count */ { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM5] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* uimm8: 8 bit unsigned immediate */ { "uimm8", M32R_OPERAND_UIMM8, HW_H_UINT, 8, 8, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM8] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* uimm16: 16 bit unsigned immediate */ { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* imm1: 1 bit immediate */ { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_IMM1] } }, - { 0|A(HASH_PREFIX), { (1<<MACH_M32RX)|(1<<MACH_M32R2) } } }, + { 0|A(HASH_PREFIX), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } }, /* accd: accumulator destination register */ { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCD] } }, - { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } } }, + { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } }, /* accs: accumulator source register */ { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCS] } }, - { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } } }, + { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } }, /* acc: accumulator reg (d) */ { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACC] } }, - { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } } }, + { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } }, /* hash: # prefix */ { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* hi16: high 16 bit immediate, sign optional */ { "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_HI16] } }, - { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } }, + { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, /* slo16: 16 bit signed immediate, for low() */ { "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ulo16: 16 bit unsigned immediate, for low() */ { "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* uimm24: 24 bit address */ { "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM24] } }, - { 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } } }, + { 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, /* disp8: 8 bit displacement */ { "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP8] } }, - { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, + { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, /* disp16: 16 bit displacement */ { "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP16] } }, - { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, + { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, /* disp24: 24 bit displacement */ { "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24, { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP24] } }, - { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, + { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, /* condbit: condition bit */ { "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* accum: accumulator */ { "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* sentinel */ { 0, 0, 0, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { 0 } } } + { 0, { { { (1<<MACH_BASE), 0 } } } } } }; #undef A @@ -462,746 +462,746 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] = /* Special null first entry. A `num' value of zero is thus invalid. Also, the special `invalid' insn resides here. */ - { 0, 0, 0, 0, {0, {0}} }, + { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* add $dr,$sr */ { M32R_INSN_ADD, "add", "add", 16, - { 0, { (1<<MACH_BASE), PIPE_OS } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } }, /* add3 $dr,$sr,$hash$slo16 */ { M32R_INSN_ADD3, "add3", "add3", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* and $dr,$sr */ { M32R_INSN_AND, "and", "and", 16, - { 0, { (1<<MACH_BASE), PIPE_OS } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } }, /* and3 $dr,$sr,$uimm16 */ { M32R_INSN_AND3, "and3", "and3", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* or $dr,$sr */ { M32R_INSN_OR, "or", "or", 16, - { 0, { (1<<MACH_BASE), PIPE_OS } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } }, /* or3 $dr,$sr,$hash$ulo16 */ { M32R_INSN_OR3, "or3", "or3", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* xor $dr,$sr */ { M32R_INSN_XOR, "xor", "xor", 16, - { 0, { (1<<MACH_BASE), PIPE_OS } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } }, /* xor3 $dr,$sr,$uimm16 */ { M32R_INSN_XOR3, "xor3", "xor3", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* addi $dr,$simm8 */ { M32R_INSN_ADDI, "addi", "addi", 16, - { 0, { (1<<MACH_BASE), PIPE_OS } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } }, /* addv $dr,$sr */ { M32R_INSN_ADDV, "addv", "addv", 16, - { 0, { (1<<MACH_BASE), PIPE_OS } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } }, /* addv3 $dr,$sr,$simm16 */ { M32R_INSN_ADDV3, "addv3", "addv3", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* addx $dr,$sr */ { M32R_INSN_ADDX, "addx", "addx", 16, - { 0, { (1<<MACH_BASE), PIPE_OS } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } }, /* bc.s $disp8 */ { M32R_INSN_BC8, "bc8", "bc.s", 16, - { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* bc.l $disp24 */ { M32R_INSN_BC24, "bc24", "bc.l", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* beq $src1,$src2,$disp16 */ { M32R_INSN_BEQ, "beq", "beq", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* beqz $src2,$disp16 */ { M32R_INSN_BEQZ, "beqz", "beqz", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* bgez $src2,$disp16 */ { M32R_INSN_BGEZ, "bgez", "bgez", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* bgtz $src2,$disp16 */ { M32R_INSN_BGTZ, "bgtz", "bgtz", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* blez $src2,$disp16 */ { M32R_INSN_BLEZ, "blez", "blez", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* bltz $src2,$disp16 */ { M32R_INSN_BLTZ, "bltz", "bltz", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* bnez $src2,$disp16 */ { M32R_INSN_BNEZ, "bnez", "bnez", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* bl.s $disp8 */ { M32R_INSN_BL8, "bl8", "bl.s", 16, - { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } } + { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* bl.l $disp24 */ { M32R_INSN_BL24, "bl24", "bl.l", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* bcl.s $disp8 */ { M32R_INSN_BCL8, "bcl8", "bcl.s", 16, - { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } } + { 0|A(FILL_SLOT)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } } }, /* bcl.l $disp24 */ { M32R_INSN_BCL24, "bcl24", "bcl.l", 32, - { 0|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } } + { 0|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } }, /* bnc.s $disp8 */ { M32R_INSN_BNC8, "bnc8", "bnc.s", 16, - { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* bnc.l $disp24 */ { M32R_INSN_BNC24, "bnc24", "bnc.l", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* bne $src1,$src2,$disp16 */ { M32R_INSN_BNE, "bne", "bne", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* bra.s $disp8 */ { M32R_INSN_BRA8, "bra8", "bra.s", 16, - { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } } + { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* bra.l $disp24 */ { M32R_INSN_BRA24, "bra24", "bra.l", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* bncl.s $disp8 */ { M32R_INSN_BNCL8, "bncl8", "bncl.s", 16, - { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } } + { 0|A(FILL_SLOT)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } } }, /* bncl.l $disp24 */ { M32R_INSN_BNCL24, "bncl24", "bncl.l", 32, - { 0|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } } + { 0|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } }, /* cmp $src1,$src2 */ { M32R_INSN_CMP, "cmp", "cmp", 16, - { 0, { (1<<MACH_BASE), PIPE_OS } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } }, /* cmpi $src2,$simm16 */ { M32R_INSN_CMPI, "cmpi", "cmpi", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* cmpu $src1,$src2 */ { M32R_INSN_CMPU, "cmpu", "cmpu", 16, - { 0, { (1<<MACH_BASE), PIPE_OS } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } }, /* cmpui $src2,$simm16 */ { M32R_INSN_CMPUI, "cmpui", "cmpui", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* cmpeq $src1,$src2 */ { M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16, - { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_OS } } + { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } } }, /* cmpz $src2 */ { M32R_INSN_CMPZ, "cmpz", "cmpz", 16, - { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_OS } } + { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } } }, /* div $dr,$sr */ { M32R_INSN_DIV, "div", "div", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* divu $dr,$sr */ { M32R_INSN_DIVU, "divu", "divu", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* rem $dr,$sr */ { M32R_INSN_REM, "rem", "rem", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* remu $dr,$sr */ { M32R_INSN_REMU, "remu", "remu", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* remh $dr,$sr */ { M32R_INSN_REMH, "remh", "remh", 32, - { 0, { (1<<MACH_M32R2), PIPE_NONE } } + { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } }, /* remuh $dr,$sr */ { M32R_INSN_REMUH, "remuh", "remuh", 32, - { 0, { (1<<MACH_M32R2), PIPE_NONE } } + { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } }, /* remb $dr,$sr */ { M32R_INSN_REMB, "remb", "remb", 32, - { 0, { (1<<MACH_M32R2), PIPE_NONE } } + { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } }, /* remub $dr,$sr */ { M32R_INSN_REMUB, "remub", "remub", 32, - { 0, { (1<<MACH_M32R2), PIPE_NONE } } + { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } }, /* divuh $dr,$sr */ { M32R_INSN_DIVUH, "divuh", "divuh", 32, - { 0, { (1<<MACH_M32R2), PIPE_NONE } } + { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } }, /* divb $dr,$sr */ { M32R_INSN_DIVB, "divb", "divb", 32, - { 0, { (1<<MACH_M32R2), PIPE_NONE } } + { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } }, /* divub $dr,$sr */ { M32R_INSN_DIVUB, "divub", "divub", 32, - { 0, { (1<<MACH_M32R2), PIPE_NONE } } + { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } }, /* divh $dr,$sr */ { M32R_INSN_DIVH, "divh", "divh", 32, - { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } } + { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } }, /* jc $sr */ { M32R_INSN_JC, "jc", "jc", 16, - { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } } + { 0|A(SPECIAL)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } } }, /* jnc $sr */ { M32R_INSN_JNC, "jnc", "jnc", 16, - { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } } + { 0|A(SPECIAL)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } } }, /* jl $sr */ { M32R_INSN_JL, "jl", "jl", 16, - { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } } + { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* jmp $sr */ { M32R_INSN_JMP, "jmp", "jmp", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* ld $dr,@$sr */ { M32R_INSN_LD, "ld", "ld", 16, - { 0, { (1<<MACH_BASE), PIPE_O } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* ld $dr,@($slo16,$sr) */ { M32R_INSN_LD_D, "ld-d", "ld", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* ldb $dr,@$sr */ { M32R_INSN_LDB, "ldb", "ldb", 16, - { 0, { (1<<MACH_BASE), PIPE_O } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* ldb $dr,@($slo16,$sr) */ { M32R_INSN_LDB_D, "ldb-d", "ldb", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* ldh $dr,@$sr */ { M32R_INSN_LDH, "ldh", "ldh", 16, - { 0, { (1<<MACH_BASE), PIPE_O } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* ldh $dr,@($slo16,$sr) */ { M32R_INSN_LDH_D, "ldh-d", "ldh", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* ldub $dr,@$sr */ { M32R_INSN_LDUB, "ldub", "ldub", 16, - { 0, { (1<<MACH_BASE), PIPE_O } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* ldub $dr,@($slo16,$sr) */ { M32R_INSN_LDUB_D, "ldub-d", "ldub", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* lduh $dr,@$sr */ { M32R_INSN_LDUH, "lduh", "lduh", 16, - { 0, { (1<<MACH_BASE), PIPE_O } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* lduh $dr,@($slo16,$sr) */ { M32R_INSN_LDUH_D, "lduh-d", "lduh", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* ld $dr,@$sr+ */ { M32R_INSN_LD_PLUS, "ld-plus", "ld", 16, - { 0, { (1<<MACH_BASE), PIPE_O } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* ld24 $dr,$uimm24 */ { M32R_INSN_LD24, "ld24", "ld24", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* ldi8 $dr,$simm8 */ { M32R_INSN_LDI8, "ldi8", "ldi8", 16, - { 0, { (1<<MACH_BASE), PIPE_OS } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } }, /* ldi16 $dr,$hash$slo16 */ { M32R_INSN_LDI16, "ldi16", "ldi16", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* lock $dr,@$sr */ { M32R_INSN_LOCK, "lock", "lock", 16, - { 0, { (1<<MACH_BASE), PIPE_O } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* machi $src1,$src2 */ { M32R_INSN_MACHI, "machi", "machi", 16, - { 0, { (1<<MACH_M32R), PIPE_S } } + { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } }, /* machi $src1,$src2,$acc */ { M32R_INSN_MACHI_A, "machi-a", "machi", 16, - { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } } + { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } }, /* maclo $src1,$src2 */ { M32R_INSN_MACLO, "maclo", "maclo", 16, - { 0, { (1<<MACH_M32R), PIPE_S } } + { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } }, /* maclo $src1,$src2,$acc */ { M32R_INSN_MACLO_A, "maclo-a", "maclo", 16, - { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } } + { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } }, /* macwhi $src1,$src2 */ { M32R_INSN_MACWHI, "macwhi", "macwhi", 16, - { 0, { (1<<MACH_M32R), PIPE_S } } + { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } }, /* macwhi $src1,$src2,$acc */ { M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16, - { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } } + { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } }, /* macwlo $src1,$src2 */ { M32R_INSN_MACWLO, "macwlo", "macwlo", 16, - { 0, { (1<<MACH_M32R), PIPE_S } } + { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } }, /* macwlo $src1,$src2,$acc */ { M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16, - { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } } + { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } }, /* mul $dr,$sr */ { M32R_INSN_MUL, "mul", "mul", 16, - { 0, { (1<<MACH_BASE), PIPE_S } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_S, 0 } } } } }, /* mulhi $src1,$src2 */ { M32R_INSN_MULHI, "mulhi", "mulhi", 16, - { 0, { (1<<MACH_M32R), PIPE_S } } + { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } }, /* mulhi $src1,$src2,$acc */ { M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16, - { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } } + { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } }, /* mullo $src1,$src2 */ { M32R_INSN_MULLO, "mullo", "mullo", 16, - { 0, { (1<<MACH_M32R), PIPE_S } } + { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } }, /* mullo $src1,$src2,$acc */ { M32R_INSN_MULLO_A, "mullo-a", "mullo", 16, - { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } } + { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } }, /* mulwhi $src1,$src2 */ { M32R_INSN_MULWHI, "mulwhi", "mulwhi", 16, - { 0, { (1<<MACH_M32R), PIPE_S } } + { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } }, /* mulwhi $src1,$src2,$acc */ { M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16, - { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } } + { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } }, /* mulwlo $src1,$src2 */ { M32R_INSN_MULWLO, "mulwlo", "mulwlo", 16, - { 0, { (1<<MACH_M32R), PIPE_S } } + { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } }, /* mulwlo $src1,$src2,$acc */ { M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16, - { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } } + { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } }, /* mv $dr,$sr */ { M32R_INSN_MV, "mv", "mv", 16, - { 0, { (1<<MACH_BASE), PIPE_OS } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } }, /* mvfachi $dr */ { M32R_INSN_MVFACHI, "mvfachi", "mvfachi", 16, - { 0, { (1<<MACH_M32R), PIPE_S } } + { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } }, /* mvfachi $dr,$accs */ { M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16, - { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } } + { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } }, /* mvfaclo $dr */ { M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo", 16, - { 0, { (1<<MACH_M32R), PIPE_S } } + { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } }, /* mvfaclo $dr,$accs */ { M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16, - { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } } + { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } }, /* mvfacmi $dr */ { M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi", 16, - { 0, { (1<<MACH_M32R), PIPE_S } } + { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } }, /* mvfacmi $dr,$accs */ { M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16, - { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } } + { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } }, /* mvfc $dr,$scr */ { M32R_INSN_MVFC, "mvfc", "mvfc", 16, - { 0, { (1<<MACH_BASE), PIPE_O } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* mvtachi $src1 */ { M32R_INSN_MVTACHI, "mvtachi", "mvtachi", 16, - { 0, { (1<<MACH_M32R), PIPE_S } } + { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } }, /* mvtachi $src1,$accs */ { M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16, - { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } } + { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } }, /* mvtaclo $src1 */ { M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo", 16, - { 0, { (1<<MACH_M32R), PIPE_S } } + { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } }, /* mvtaclo $src1,$accs */ { M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16, - { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } } + { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } }, /* mvtc $sr,$dcr */ { M32R_INSN_MVTC, "mvtc", "mvtc", 16, - { 0, { (1<<MACH_BASE), PIPE_O } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* neg $dr,$sr */ { M32R_INSN_NEG, "neg", "neg", 16, - { 0, { (1<<MACH_BASE), PIPE_OS } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } }, /* nop */ { M32R_INSN_NOP, "nop", "nop", 16, - { 0, { (1<<MACH_BASE), PIPE_OS } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } }, /* not $dr,$sr */ { M32R_INSN_NOT, "not", "not", 16, - { 0, { (1<<MACH_BASE), PIPE_OS } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } }, /* rac */ { M32R_INSN_RAC, "rac", "rac", 16, - { 0, { (1<<MACH_M32R), PIPE_S } } + { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } }, /* rac $accd,$accs,$imm1 */ { M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16, - { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } } + { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } }, /* rach */ { M32R_INSN_RACH, "rach", "rach", 16, - { 0, { (1<<MACH_M32R), PIPE_S } } + { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } }, /* rach $accd,$accs,$imm1 */ { M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16, - { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } } + { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } }, /* rte */ { M32R_INSN_RTE, "rte", "rte", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* seth $dr,$hash$hi16 */ { M32R_INSN_SETH, "seth", "seth", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* sll $dr,$sr */ { M32R_INSN_SLL, "sll", "sll", 16, - { 0, { (1<<MACH_BASE), PIPE_O_OS } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } } }, /* sll3 $dr,$sr,$simm16 */ { M32R_INSN_SLL3, "sll3", "sll3", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* slli $dr,$uimm5 */ { M32R_INSN_SLLI, "slli", "slli", 16, - { 0, { (1<<MACH_BASE), PIPE_O_OS } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } } }, /* sra $dr,$sr */ { M32R_INSN_SRA, "sra", "sra", 16, - { 0, { (1<<MACH_BASE), PIPE_O_OS } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } } }, /* sra3 $dr,$sr,$simm16 */ { M32R_INSN_SRA3, "sra3", "sra3", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* srai $dr,$uimm5 */ { M32R_INSN_SRAI, "srai", "srai", 16, - { 0, { (1<<MACH_BASE), PIPE_O_OS } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } } }, /* srl $dr,$sr */ { M32R_INSN_SRL, "srl", "srl", 16, - { 0, { (1<<MACH_BASE), PIPE_O_OS } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } } }, /* srl3 $dr,$sr,$simm16 */ { M32R_INSN_SRL3, "srl3", "srl3", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* srli $dr,$uimm5 */ { M32R_INSN_SRLI, "srli", "srli", 16, - { 0, { (1<<MACH_BASE), PIPE_O_OS } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } } }, /* st $src1,@$src2 */ { M32R_INSN_ST, "st", "st", 16, - { 0, { (1<<MACH_BASE), PIPE_O } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* st $src1,@($slo16,$src2) */ { M32R_INSN_ST_D, "st-d", "st", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* stb $src1,@$src2 */ { M32R_INSN_STB, "stb", "stb", 16, - { 0, { (1<<MACH_BASE), PIPE_O } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* stb $src1,@($slo16,$src2) */ { M32R_INSN_STB_D, "stb-d", "stb", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* sth $src1,@$src2 */ { M32R_INSN_STH, "sth", "sth", 16, - { 0, { (1<<MACH_BASE), PIPE_O } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* sth $src1,@($slo16,$src2) */ { M32R_INSN_STH_D, "sth-d", "sth", 32, - { 0, { (1<<MACH_BASE), PIPE_NONE } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* st $src1,@+$src2 */ { M32R_INSN_ST_PLUS, "st-plus", "st", 16, - { 0, { (1<<MACH_BASE), PIPE_O } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* sth $src1,@$src2+ */ { M32R_INSN_STH_PLUS, "sth-plus", "sth", 16, - { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } } + { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } } }, /* stb $src1,@$src2+ */ { M32R_INSN_STB_PLUS, "stb-plus", "stb", 16, - { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } } + { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } } }, /* st $src1,@-$src2 */ { M32R_INSN_ST_MINUS, "st-minus", "st", 16, - { 0, { (1<<MACH_BASE), PIPE_O } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* sub $dr,$sr */ { M32R_INSN_SUB, "sub", "sub", 16, - { 0, { (1<<MACH_BASE), PIPE_OS } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } }, /* subv $dr,$sr */ { M32R_INSN_SUBV, "subv", "subv", 16, - { 0, { (1<<MACH_BASE), PIPE_OS } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } }, /* subx $dr,$sr */ { M32R_INSN_SUBX, "subx", "subx", 16, - { 0, { (1<<MACH_BASE), PIPE_OS } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } }, /* trap $uimm4 */ { M32R_INSN_TRAP, "trap", "trap", 16, - { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } } + { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* unlock $src1,@$src2 */ { M32R_INSN_UNLOCK, "unlock", "unlock", 16, - { 0, { (1<<MACH_BASE), PIPE_O } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* satb $dr,$sr */ { M32R_INSN_SATB, "satb", "satb", 32, - { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } } + { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } }, /* sath $dr,$sr */ { M32R_INSN_SATH, "sath", "sath", 32, - { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } } + { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } }, /* sat $dr,$sr */ { M32R_INSN_SAT, "sat", "sat", 32, - { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } } + { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } }, /* pcmpbz $src2 */ { M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16, - { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_OS } } + { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } } }, /* sadd */ { M32R_INSN_SADD, "sadd", "sadd", 16, - { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } } + { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } }, /* macwu1 $src1,$src2 */ { M32R_INSN_MACWU1, "macwu1", "macwu1", 16, - { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } } + { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } }, /* msblo $src1,$src2 */ { M32R_INSN_MSBLO, "msblo", "msblo", 16, - { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } } + { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } }, /* mulwu1 $src1,$src2 */ { M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16, - { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } } + { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } }, /* maclh1 $src1,$src2 */ { M32R_INSN_MACLH1, "maclh1", "maclh1", 16, - { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } } + { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } }, /* sc */ { M32R_INSN_SC, "sc", "sc", 16, - { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } } + { 0|A(SPECIAL)|A(SKIP_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } } }, /* snc */ { M32R_INSN_SNC, "snc", "snc", 16, - { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } } + { 0|A(SPECIAL)|A(SKIP_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } } }, /* clrpsw $uimm8 */ { M32R_INSN_CLRPSW, "clrpsw", "clrpsw", 16, - { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_O } } + { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* setpsw $uimm8 */ { M32R_INSN_SETPSW, "setpsw", "setpsw", 16, - { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_O } } + { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* bset $uimm3,@($slo16,$sr) */ { M32R_INSN_BSET, "bset", "bset", 32, - { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* bclr $uimm3,@($slo16,$sr) */ { M32R_INSN_BCLR, "bclr", "bclr", 32, - { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* btst $uimm3,$sr */ { M32R_INSN_BTST, "btst", "btst", 16, - { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_O } } + { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, }; @@ -1324,7 +1324,7 @@ static void m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) { int i; - unsigned int isas = cd->isas; + CGEN_BITSET *isas = cd->isas; unsigned int machs = cd->machs; cd->int_insn_p = CGEN_INT_INSN_P; @@ -1336,7 +1336,7 @@ m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) - if (((1 << i) & isas) != 0) + if (cgen_bitset_contains (isas, i)) { const CGEN_ISA *isa = & m32r_cgen_isa_table[i]; @@ -1421,7 +1421,7 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) { CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); static int init_p; - unsigned int isas = 0; /* 0 = "unspecified" */ + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ unsigned int machs = 0; /* 0 = "unspecified" */ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; va_list ap; @@ -1440,7 +1440,7 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) switch (arg_type) { case CGEN_CPU_OPEN_ISAS : - isas = va_arg (ap, unsigned int); + isas = va_arg (ap, CGEN_BITSET *); break; case CGEN_CPU_OPEN_MACHS : machs = va_arg (ap, unsigned int); @@ -1471,9 +1471,6 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) machs = (1 << MAX_MACHS) - 1; /* Base mach is always selected. */ machs |= 1; - /* ISA unspecified means "all". */ - if (isas == 0) - isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) { /* ??? If target has only one, could have a default. */ @@ -1481,7 +1478,7 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) abort (); } - cd->isas = isas; + cd->isas = cgen_bitset_copy (isas); cd->machs = machs; cd->endian = endian; /* FIXME: for the sparc case we can determine insn-endianness statically. diff --git a/opcodes/m32r-desc.h b/opcodes/m32r-desc.h index 2080b5cdc0f..9624852bea9 100644 --- a/opcodes/m32r-desc.h +++ b/opcodes/m32r-desc.h @@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc., #ifndef M32R_CPU_H #define M32R_CPU_H +#include "opcode/cgen-bitset.h" + #define CGEN_ARCH m32r /* Given symbol S, return m32r_cgen_<S>. */ @@ -135,6 +137,16 @@ typedef enum cgen_ifld_attr { /* Number of non-boolean elements in cgen_ifld_attr. */ #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RELOC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RELOC)) != 0) + /* Enum declaration for m32r ifield types. */ typedef enum ifield_type { M32R_F_NIL, M32R_F_ANYOF, M32R_F_OP1, M32R_F_OP2 @@ -160,6 +172,13 @@ typedef enum cgen_hw_attr { /* Number of non-boolean elements in cgen_hw_attr. */ #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) + /* Enum declaration for m32r hardware types. */ typedef enum cgen_hw_type { HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR @@ -184,6 +203,19 @@ typedef enum cgen_operand_attr { /* Number of non-boolean elements in cgen_operand_attr. */ #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELOC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELOC)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0) + /* Enum declaration for m32r operand types. */ typedef enum cgen_operand_type { M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1 @@ -216,6 +248,24 @@ typedef enum cgen_insn_attr { /* Number of non-boolean elements in cgen_insn_attr. */ #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_PIPE_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_PIPE-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) +#define CGEN_ATTR_CGEN_INSN_FILL_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_FILL_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_SPECIAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SPECIAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_SPECIAL_M32R_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SPECIAL_M32R)) != 0) +#define CGEN_ATTR_CGEN_INSN_SPECIAL_FLOAT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SPECIAL_FLOAT)) != 0) + /* cgen.h uses things we just defined. */ #include "opcode/cgen.h" diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c index fb65bfee728..e381c919d75 100644 --- a/opcodes/m32r-dis.c +++ b/opcodes/m32r-dis.c @@ -4,7 +4,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-dis.in isn't - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -564,7 +564,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) typedef struct cpu_desc_list { struct cpu_desc_list *next; - int isa; + CGEN_BITSET *isa; int mach; int endian; CGEN_CPU_DESC cd; @@ -576,11 +576,12 @@ print_insn_m32r (bfd_vma pc, disassemble_info *info) static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; static CGEN_CPU_DESC cd = 0; - static int prev_isa; + static CGEN_BITSET *prev_isa; static int prev_mach; static int prev_endian; int length; - int isa,mach; + CGEN_BITSET *isa; + int mach; int endian = (info->endian == BFD_ENDIAN_BIG ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); @@ -603,25 +604,34 @@ print_insn_m32r (bfd_vma pc, disassemble_info *info) #endif #ifdef CGEN_COMPUTE_ISA - isa = CGEN_COMPUTE_ISA (info); + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } #else isa = info->insn_sets; #endif /* If we've switched cpu's, try to find a handle we've used before */ if (cd - && (isa != prev_isa + && (cgen_bitset_compare (isa, prev_isa) != 0 || mach != prev_mach || endian != prev_endian)) { cd = 0; for (cl = cd_list; cl; cl = cl->next) { - if (cl->isa == isa && + if (cgen_bitset_compare (cl->isa, isa) == 0 && cl->mach == mach && cl->endian == endian) { cd = cl->cd; + prev_isa = cd->isas; break; } } @@ -637,7 +647,7 @@ print_insn_m32r (bfd_vma pc, disassemble_info *info) abort (); mach_name = arch_type->printable_name; - prev_isa = isa; + prev_isa = cgen_bitset_copy (isa); prev_mach = mach; prev_endian = endian; cd = m32r_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, @@ -650,7 +660,7 @@ print_insn_m32r (bfd_vma pc, disassemble_info *info) /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; - cl->isa = isa; + cl->isa = prev_isa; cl->mach = mach; cl->endian = endian; cl->next = cd_list; diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c index 29b7a21c290..7669eb6187c 100644 --- a/opcodes/m32r-opc.c +++ b/opcodes/m32r-opc.c @@ -1301,182 +1301,182 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] = /* bc $disp8 */ { -1, "bc8r", "bc", 16, - { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } + { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* bc $disp24 */ { -1, "bc24r", "bc", 32, - { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* bl $disp8 */ { -1, "bl8r", "bl", 16, - { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } + { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* bl $disp24 */ { -1, "bl24r", "bl", 32, - { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* bcl $disp8 */ { -1, "bcl8r", "bcl", 16, - { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } } + { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } } }, /* bcl $disp24 */ { -1, "bcl24r", "bcl", 32, - { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } } + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } }, /* bnc $disp8 */ { -1, "bnc8r", "bnc", 16, - { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } + { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* bnc $disp24 */ { -1, "bnc24r", "bnc", 32, - { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* bra $disp8 */ { -1, "bra8r", "bra", 16, - { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } + { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* bra $disp24 */ { -1, "bra24r", "bra", 32, - { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* bncl $disp8 */ { -1, "bncl8r", "bncl", 16, - { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } } + { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } } }, /* bncl $disp24 */ { -1, "bncl24r", "bncl", 32, - { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } } + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } }, /* ld $dr,@($sr) */ { -1, "ld-2", "ld", 16, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* ld $dr,@($sr,$slo16) */ { -1, "ld-d2", "ld", 32, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* ldb $dr,@($sr) */ { -1, "ldb-2", "ldb", 16, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* ldb $dr,@($sr,$slo16) */ { -1, "ldb-d2", "ldb", 32, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* ldh $dr,@($sr) */ { -1, "ldh-2", "ldh", 16, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* ldh $dr,@($sr,$slo16) */ { -1, "ldh-d2", "ldh", 32, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* ldub $dr,@($sr) */ { -1, "ldub-2", "ldub", 16, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* ldub $dr,@($sr,$slo16) */ { -1, "ldub-d2", "ldub", 32, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* lduh $dr,@($sr) */ { -1, "lduh-2", "lduh", 16, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* lduh $dr,@($sr,$slo16) */ { -1, "lduh-d2", "lduh", 32, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* pop $dr */ { -1, "pop", "pop", 16, - { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* ldi $dr,$simm8 */ { -1, "ldi8a", "ldi", 16, - { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_OS } } + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } }, /* ldi $dr,$hash$slo16 */ { -1, "ldi16a", "ldi", 32, - { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* rac $accd */ { -1, "rac-d", "rac", 16, - { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } } + { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } }, /* rac $accd,$accs */ { -1, "rac-ds", "rac", 16, - { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } } + { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } }, /* rach $accd */ { -1, "rach-d", "rach", 16, - { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } } + { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } }, /* rach $accd,$accs */ { -1, "rach-ds", "rach", 16, - { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } } + { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } }, /* st $src1,@($src2) */ { -1, "st-2", "st", 16, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* st $src1,@($src2,$slo16) */ { -1, "st-d2", "st", 32, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* stb $src1,@($src2) */ { -1, "stb-2", "stb", 16, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* stb $src1,@($src2,$slo16) */ { -1, "stb-d2", "stb", 32, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* sth $src1,@($src2) */ { -1, "sth-2", "sth", 16, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, /* sth $src1,@($src2,$slo16) */ { -1, "sth-d2", "sth", 32, - { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, /* push $src1 */ { -1, "push", "push", 16, - { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } }, }; diff --git a/opcodes/ms1-desc.c b/opcodes/ms1-desc.c index 8428c6c0125..c48a8a89c85 100644 --- a/opcodes/ms1-desc.c +++ b/opcodes/ms1-desc.c @@ -138,8 +138,8 @@ static const CGEN_MACH ms1_cgen_mach_table[] = { static CGEN_KEYWORD_ENTRY ms1_cgen_opval_msys_syms_entries[] = { - { "DUP", 1, {0, {0}}, 0, 0 }, - { "XX", 0, {0, {0}}, 0, 0 } + { "DUP", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "XX", 0, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD ms1_cgen_opval_msys_syms = @@ -151,26 +151,26 @@ CGEN_KEYWORD ms1_cgen_opval_msys_syms = static CGEN_KEYWORD_ENTRY ms1_cgen_opval_h_spr_entries[] = { - { "R0", 0, {0, {0}}, 0, 0 }, - { "R1", 1, {0, {0}}, 0, 0 }, - { "R2", 2, {0, {0}}, 0, 0 }, - { "R3", 3, {0, {0}}, 0, 0 }, - { "R4", 4, {0, {0}}, 0, 0 }, - { "R5", 5, {0, {0}}, 0, 0 }, - { "R6", 6, {0, {0}}, 0, 0 }, - { "R7", 7, {0, {0}}, 0, 0 }, - { "R8", 8, {0, {0}}, 0, 0 }, - { "R9", 9, {0, {0}}, 0, 0 }, - { "R10", 10, {0, {0}}, 0, 0 }, - { "R11", 11, {0, {0}}, 0, 0 }, - { "R12", 12, {0, {0}}, 0, 0 }, - { "fp", 12, {0, {0}}, 0, 0 }, - { "R13", 13, {0, {0}}, 0, 0 }, - { "sp", 13, {0, {0}}, 0, 0 }, - { "R14", 14, {0, {0}}, 0, 0 }, - { "ra", 14, {0, {0}}, 0, 0 }, - { "R15", 15, {0, {0}}, 0, 0 }, - { "ira", 15, {0, {0}}, 0, 0 } + { "R0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "R1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "R2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "R3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "R4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "R5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "R6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "R7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "R8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "R9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "R10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "R11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "R12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "fp", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "R13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "R14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "ra", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "R15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "ira", 15, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD ms1_cgen_opval_h_spr = @@ -191,14 +191,14 @@ CGEN_KEYWORD ms1_cgen_opval_h_spr = const CGEN_HW_ENTRY ms1_cgen_hw_table[] = { - { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & ms1_cgen_opval_h_spr, { 0, { (1<<MACH_BASE) } } }, - { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } }, - { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} } + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & ms1_cgen_opval_h_spr, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } }, + { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } }; #undef A @@ -214,76 +214,76 @@ const CGEN_HW_ENTRY ms1_cgen_hw_table[] = const CGEN_IFLD ms1_cgen_ifld_table[] = { - { MS1_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_MSYS, "f-msys", 0, 32, 31, 1, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_OPC, "f-opc", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_IMM, "f-imm", 0, 32, 24, 1, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_UU24, "f-uu24", 0, 32, 23, 24, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_SR1, "f-sr1", 0, 32, 23, 4, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, - { MS1_F_SR2, "f-sr2", 0, 32, 19, 4, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, - { MS1_F_DR, "f-dr", 0, 32, 19, 4, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, - { MS1_F_DRRR, "f-drrr", 0, 32, 15, 4, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, - { MS1_F_IMM16U, "f-imm16u", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_IMM16S, "f-imm16s", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_IMM16A, "f-imm16a", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, - { MS1_F_UU4A, "f-uu4a", 0, 32, 19, 4, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_UU4B, "f-uu4b", 0, 32, 23, 4, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_UU12, "f-uu12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_UU16, "f-uu16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_MSOPC, "f-msopc", 0, 32, 30, 5, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_UU_26_25, "f-uu-26-25", 0, 32, 25, 26, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_MASK, "f-mask", 0, 32, 25, 16, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_BANKADDR, "f-bankaddr", 0, 32, 25, 13, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_RDA, "f-rda", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_UU_2_25, "f-uu-2-25", 0, 32, 25, 2, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_RBBC, "f-rbbc", 0, 32, 25, 2, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_PERM, "f-perm", 0, 32, 25, 2, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_MODE, "f-mode", 0, 32, 25, 2, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_UU_1_24, "f-uu-1-24", 0, 32, 24, 1, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_WR, "f-wr", 0, 32, 24, 1, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_FBINCR, "f-fbincr", 0, 32, 23, 4, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_UU_2_23, "f-uu-2-23", 0, 32, 23, 2, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_XMODE, "f-xmode", 0, 32, 23, 1, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_A23, "f-a23", 0, 32, 23, 1, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_MASK1, "f-mask1", 0, 32, 22, 3, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_CR, "f-cr", 0, 32, 22, 3, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_TYPE, "f-type", 0, 32, 21, 2, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_INCAMT, "f-incamt", 0, 32, 19, 8, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_CBS, "f-cbs", 0, 32, 19, 2, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_UU_1_19, "f-uu-1-19", 0, 32, 19, 1, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_BALL, "f-ball", 0, 32, 19, 1, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_COLNUM, "f-colnum", 0, 32, 18, 3, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_BRC, "f-brc", 0, 32, 18, 3, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_INCR, "f-incr", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_FBDISP, "f-fbdisp", 0, 32, 15, 6, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_UU_4_15, "f-uu-4-15", 0, 32, 15, 4, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_LENGTH, "f-length", 0, 32, 15, 3, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_UU_1_15, "f-uu-1-15", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_RC, "f-rc", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_RCNUM, "f-rcnum", 0, 32, 14, 3, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_ROWNUM, "f-rownum", 0, 32, 14, 3, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_CBX, "f-cbx", 0, 32, 14, 3, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_ID, "f-id", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_SIZE, "f-size", 0, 32, 13, 14, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_ROWNUM1, "f-rownum1", 0, 32, 12, 3, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_UU_3_11, "f-uu-3-11", 0, 32, 11, 3, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_RC1, "f-rc1", 0, 32, 11, 1, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_CCB, "f-ccb", 0, 32, 11, 1, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_CBRB, "f-cbrb", 0, 32, 10, 1, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_CDB, "f-cdb", 0, 32, 10, 1, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_ROWNUM2, "f-rownum2", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_CELL, "f-cell", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_UU_3_9, "f-uu-3-9", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_CONTNUM, "f-contnum", 0, 32, 8, 9, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_UU_1_6, "f-uu-1-6", 0, 32, 6, 1, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_DUP, "f-dup", 0, 32, 6, 1, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_RC2, "f-rc2", 0, 32, 6, 1, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_CTXDISP, "f-ctxdisp", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_MSYSFRSR2, "f-msysfrsr2", 0, 32, 19, 4, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_BRC2, "f-brc2", 0, 32, 14, 3, { 0, { (1<<MACH_BASE) } } }, - { MS1_F_BALL2, "f-ball2", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } }, - { 0, 0, 0, 0, 0, 0, {0, {0}} } + { MS1_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_MSYS, "f-msys", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_OPC, "f-opc", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_IMM, "f-imm", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_UU24, "f-uu24", 0, 32, 23, 24, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_SR1, "f-sr1", 0, 32, 23, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_SR2, "f-sr2", 0, 32, 19, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_DR, "f-dr", 0, 32, 19, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_DRRR, "f-drrr", 0, 32, 15, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_IMM16U, "f-imm16u", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_IMM16S, "f-imm16s", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_IMM16A, "f-imm16a", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_UU4A, "f-uu4a", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_UU4B, "f-uu4b", 0, 32, 23, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_UU12, "f-uu12", 0, 32, 11, 12, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_UU16, "f-uu16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_MSOPC, "f-msopc", 0, 32, 30, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_UU_26_25, "f-uu-26-25", 0, 32, 25, 26, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_MASK, "f-mask", 0, 32, 25, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_BANKADDR, "f-bankaddr", 0, 32, 25, 13, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_RDA, "f-rda", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_UU_2_25, "f-uu-2-25", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_RBBC, "f-rbbc", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_PERM, "f-perm", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_MODE, "f-mode", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_UU_1_24, "f-uu-1-24", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_WR, "f-wr", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_FBINCR, "f-fbincr", 0, 32, 23, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_UU_2_23, "f-uu-2-23", 0, 32, 23, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_XMODE, "f-xmode", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_A23, "f-a23", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_MASK1, "f-mask1", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_CR, "f-cr", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_TYPE, "f-type", 0, 32, 21, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_INCAMT, "f-incamt", 0, 32, 19, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_CBS, "f-cbs", 0, 32, 19, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_UU_1_19, "f-uu-1-19", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_BALL, "f-ball", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_COLNUM, "f-colnum", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_BRC, "f-brc", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_INCR, "f-incr", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_FBDISP, "f-fbdisp", 0, 32, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_UU_4_15, "f-uu-4-15", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_LENGTH, "f-length", 0, 32, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_UU_1_15, "f-uu-1-15", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_RC, "f-rc", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_RCNUM, "f-rcnum", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_ROWNUM, "f-rownum", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_CBX, "f-cbx", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_ID, "f-id", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_SIZE, "f-size", 0, 32, 13, 14, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_ROWNUM1, "f-rownum1", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_UU_3_11, "f-uu-3-11", 0, 32, 11, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_RC1, "f-rc1", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_CCB, "f-ccb", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_CBRB, "f-cbrb", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_CDB, "f-cdb", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_ROWNUM2, "f-rownum2", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_CELL, "f-cell", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_UU_3_9, "f-uu-3-9", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_CONTNUM, "f-contnum", 0, 32, 8, 9, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_UU_1_6, "f-uu-1-6", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_DUP, "f-dup", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_RC2, "f-rc2", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_CTXDISP, "f-ctxdisp", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_MSYSFRSR2, "f-msysfrsr2", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_BRC2, "f-brc2", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { MS1_F_BALL2, "f-ball2", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } }; #undef A @@ -315,199 +315,199 @@ const CGEN_OPERAND ms1_cgen_operand_table[] = /* pc: program counter */ { "pc", MS1_OPERAND_PC, HW_H_PC, 0, 0, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_NIL] } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* frsr1: register */ { "frsr1", MS1_OPERAND_FRSR1, HW_H_SPR, 23, 4, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_SR1] } }, - { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, + { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, /* frsr2: register */ { "frsr2", MS1_OPERAND_FRSR2, HW_H_SPR, 19, 4, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_SR2] } }, - { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, + { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, /* frdr: register */ { "frdr", MS1_OPERAND_FRDR, HW_H_SPR, 19, 4, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_DR] } }, - { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, + { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, /* frdrrr: register */ { "frdrrr", MS1_OPERAND_FRDRRR, HW_H_SPR, 15, 4, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_DRRR] } }, - { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, + { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, /* imm16: immediate value - sign extd */ { "imm16", MS1_OPERAND_IMM16, HW_H_SINT, 15, 16, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_IMM16S] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* imm16z: immediate value - zero extd */ { "imm16z", MS1_OPERAND_IMM16Z, HW_H_UINT, 15, 16, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_IMM16U] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* imm16o: immediate value */ { "imm16o", MS1_OPERAND_IMM16O, HW_H_UINT, 15, 16, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_IMM16S] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* rc: rc */ { "rc", MS1_OPERAND_RC, HW_H_UINT, 15, 1, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RC] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* rcnum: rcnum */ { "rcnum", MS1_OPERAND_RCNUM, HW_H_UINT, 14, 3, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RCNUM] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* contnum: context number */ { "contnum", MS1_OPERAND_CONTNUM, HW_H_UINT, 8, 9, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CONTNUM] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* rbbc: omega network configuration */ { "rbbc", MS1_OPERAND_RBBC, HW_H_UINT, 25, 2, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RBBC] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* colnum: column number */ { "colnum", MS1_OPERAND_COLNUM, HW_H_UINT, 18, 3, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_COLNUM] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* rownum: row number */ { "rownum", MS1_OPERAND_ROWNUM, HW_H_UINT, 14, 3, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_ROWNUM] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* rownum1: row number */ { "rownum1", MS1_OPERAND_ROWNUM1, HW_H_UINT, 12, 3, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_ROWNUM1] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* rownum2: row number */ { "rownum2", MS1_OPERAND_ROWNUM2, HW_H_UINT, 9, 3, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_ROWNUM2] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* rc1: rc1 */ { "rc1", MS1_OPERAND_RC1, HW_H_UINT, 11, 1, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RC1] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* rc2: rc2 */ { "rc2", MS1_OPERAND_RC2, HW_H_UINT, 6, 1, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RC2] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* cbrb: data-bus orientation */ { "cbrb", MS1_OPERAND_CBRB, HW_H_UINT, 10, 1, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CBRB] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* cell: cell */ { "cell", MS1_OPERAND_CELL, HW_H_UINT, 9, 3, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CELL] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* dup: dup */ { "dup", MS1_OPERAND_DUP, HW_H_UINT, 6, 1, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_DUP] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ctxdisp: context displacement */ { "ctxdisp", MS1_OPERAND_CTXDISP, HW_H_UINT, 5, 6, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CTXDISP] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* fbdisp: frame buffer displacement */ { "fbdisp", MS1_OPERAND_FBDISP, HW_H_UINT, 15, 6, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_FBDISP] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* type: type */ { "type", MS1_OPERAND_TYPE, HW_H_UINT, 21, 2, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_TYPE] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mask: mask */ { "mask", MS1_OPERAND_MASK, HW_H_UINT, 25, 16, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_MASK] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* bankaddr: bank address */ { "bankaddr", MS1_OPERAND_BANKADDR, HW_H_UINT, 25, 13, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_BANKADDR] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* incamt: increment amount */ { "incamt", MS1_OPERAND_INCAMT, HW_H_UINT, 19, 8, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_INCAMT] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* xmode: xmode */ { "xmode", MS1_OPERAND_XMODE, HW_H_UINT, 23, 1, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_XMODE] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mask1: mask1 */ { "mask1", MS1_OPERAND_MASK1, HW_H_UINT, 22, 3, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_MASK1] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ball: b_all */ { "ball", MS1_OPERAND_BALL, HW_H_UINT, 19, 1, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_BALL] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* brc: b_r_c */ { "brc", MS1_OPERAND_BRC, HW_H_UINT, 18, 3, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_BRC] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* rda: rd */ { "rda", MS1_OPERAND_RDA, HW_H_UINT, 25, 1, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RDA] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* wr: wr */ { "wr", MS1_OPERAND_WR, HW_H_UINT, 24, 1, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_WR] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ball2: b_all2 */ { "ball2", MS1_OPERAND_BALL2, HW_H_UINT, 15, 1, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_BALL2] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* brc2: b_r_c2 */ { "brc2", MS1_OPERAND_BRC2, HW_H_UINT, 14, 3, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_BRC2] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* perm: perm */ { "perm", MS1_OPERAND_PERM, HW_H_UINT, 25, 2, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_PERM] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* a23: a23 */ { "a23", MS1_OPERAND_A23, HW_H_UINT, 23, 1, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_A23] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* cr: c-r */ { "cr", MS1_OPERAND_CR, HW_H_UINT, 22, 3, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CR] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* cbs: cbs */ { "cbs", MS1_OPERAND_CBS, HW_H_UINT, 19, 2, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CBS] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* incr: incr */ { "incr", MS1_OPERAND_INCR, HW_H_UINT, 17, 6, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_INCR] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* length: length */ { "length", MS1_OPERAND_LENGTH, HW_H_UINT, 15, 3, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_LENGTH] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* cbx: cbx */ { "cbx", MS1_OPERAND_CBX, HW_H_UINT, 14, 3, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CBX] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ccb: ccb */ { "ccb", MS1_OPERAND_CCB, HW_H_UINT, 11, 1, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CCB] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* cdb: cdb */ { "cdb", MS1_OPERAND_CDB, HW_H_UINT, 10, 1, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CDB] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mode: mode */ { "mode", MS1_OPERAND_MODE, HW_H_UINT, 25, 2, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_MODE] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* id: i/d */ { "id", MS1_OPERAND_ID, HW_H_UINT, 14, 1, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_ID] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* size: size */ { "size", MS1_OPERAND_SIZE, HW_H_UINT, 13, 14, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_SIZE] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* fbincr: fb incr */ { "fbincr", MS1_OPERAND_FBINCR, HW_H_UINT, 23, 4, { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_FBINCR] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* sentinel */ { 0, 0, 0, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { 0 } } } + { 0, { { { (1<<MACH_BASE), 0 } } } } } }; #undef A @@ -527,391 +527,391 @@ static const CGEN_IBASE ms1_cgen_insn_table[MAX_INSNS] = /* Special null first entry. A `num' value of zero is thus invalid. Also, the special `invalid' insn resides here. */ - { 0, 0, 0, 0, {0, {0}} }, + { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* add $frdrrr,$frsr1,$frsr2 */ { MS1_INSN_ADD, "add", "add", 32, - { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* addu $frdrrr,$frsr1,$frsr2 */ { MS1_INSN_ADDU, "addu", "addu", 32, - { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* addi $frdr,$frsr1,#$imm16 */ { MS1_INSN_ADDI, "addi", "addi", 32, - { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* addui $frdr,$frsr1,#$imm16z */ { MS1_INSN_ADDUI, "addui", "addui", 32, - { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* sub $frdrrr,$frsr1,$frsr2 */ { MS1_INSN_SUB, "sub", "sub", 32, - { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* subu $frdrrr,$frsr1,$frsr2 */ { MS1_INSN_SUBU, "subu", "subu", 32, - { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* subi $frdr,$frsr1,#$imm16 */ { MS1_INSN_SUBI, "subi", "subi", 32, - { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* subui $frdr,$frsr1,#$imm16z */ { MS1_INSN_SUBUI, "subui", "subui", 32, - { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* mul $frdrrr,$frsr1,$frsr2 */ { MS1_INSN_MUL, "mul", "mul", 32, - { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_MS1_003) } } + { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_MS1_003), 0 } } } } }, /* muli $frdr,$frsr1,#$imm16 */ { MS1_INSN_MULI, "muli", "muli", 32, - { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_MS1_003) } } + { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_MS1_003), 0 } } } } }, /* and $frdrrr,$frsr1,$frsr2 */ { MS1_INSN_AND, "and", "and", 32, - { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* andi $frdr,$frsr1,#$imm16z */ { MS1_INSN_ANDI, "andi", "andi", 32, - { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* or $frdrrr,$frsr1,$frsr2 */ { MS1_INSN_OR, "or", "or", 32, - { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* nop */ { MS1_INSN_NOP, "nop", "nop", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ori $frdr,$frsr1,#$imm16z */ { MS1_INSN_ORI, "ori", "ori", 32, - { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* xor $frdrrr,$frsr1,$frsr2 */ { MS1_INSN_XOR, "xor", "xor", 32, - { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* xori $frdr,$frsr1,#$imm16z */ { MS1_INSN_XORI, "xori", "xori", 32, - { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* nand $frdrrr,$frsr1,$frsr2 */ { MS1_INSN_NAND, "nand", "nand", 32, - { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* nandi $frdr,$frsr1,#$imm16z */ { MS1_INSN_NANDI, "nandi", "nandi", 32, - { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* nor $frdrrr,$frsr1,$frsr2 */ { MS1_INSN_NOR, "nor", "nor", 32, - { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* nori $frdr,$frsr1,#$imm16z */ { MS1_INSN_NORI, "nori", "nori", 32, - { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* xnor $frdrrr,$frsr1,$frsr2 */ { MS1_INSN_XNOR, "xnor", "xnor", 32, - { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* xnori $frdr,$frsr1,#$imm16z */ { MS1_INSN_XNORI, "xnori", "xnori", 32, - { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* ldui $frdr,#$imm16z */ { MS1_INSN_LDUI, "ldui", "ldui", 32, - { 0|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* lsl $frdrrr,$frsr1,$frsr2 */ { MS1_INSN_LSL, "lsl", "lsl", 32, - { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } } }, /* lsli $frdr,$frsr1,#$imm16 */ { MS1_INSN_LSLI, "lsli", "lsli", 32, - { 0|A(USES_FRSR1)|A(USES_FRDR), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } } }, /* lsr $frdrrr,$frsr1,$frsr2 */ { MS1_INSN_LSR, "lsr", "lsr", 32, - { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } } }, /* lsri $frdr,$frsr1,#$imm16 */ { MS1_INSN_LSRI, "lsri", "lsri", 32, - { 0|A(USES_FRSR1)|A(USES_FRDR), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } } }, /* asr $frdrrr,$frsr1,$frsr2 */ { MS1_INSN_ASR, "asr", "asr", 32, - { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } } }, /* asri $frdr,$frsr1,#$imm16 */ { MS1_INSN_ASRI, "asri", "asri", 32, - { 0|A(USES_FRSR1)|A(USES_FRDR), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } } }, /* brlt $frsr1,$frsr2,$imm16o */ { MS1_INSN_BRLT, "brlt", "brlt", 32, - { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(DELAY_SLOT)|A(BR_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* brle $frsr1,$frsr2,$imm16o */ { MS1_INSN_BRLE, "brle", "brle", 32, - { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* breq $frsr1,$frsr2,$imm16o */ { MS1_INSN_BREQ, "breq", "breq", 32, - { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* brne $frsr1,$frsr2,$imm16o */ { MS1_INSN_BRNE, "brne", "brne", 32, - { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } } }, /* jmp $imm16o */ { MS1_INSN_JMP, "jmp", "jmp", 32, - { 0|A(BR_INSN)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* jal $frdrrr,$frsr1 */ { MS1_INSN_JAL, "jal", "jal", 32, - { 0|A(USES_FRSR1)|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR1)|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* dbnz $frsr1,$imm16o */ { MS1_INSN_DBNZ, "dbnz", "dbnz", 32, - { 0|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { (1<<MACH_MS1_003) } } + { 0|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_MS1_003), 0 } } } } }, /* ei */ { MS1_INSN_EI, "ei", "ei", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* di */ { MS1_INSN_DI, "di", "di", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* si $frdrrr */ { MS1_INSN_SI, "si", "si", 32, - { 0|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* reti $frsr1 */ { MS1_INSN_RETI, "reti", "reti", 32, - { 0|A(USES_FRSR1)|A(BR_INSN)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR1)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* ldw $frdr,$frsr1,#$imm16 */ { MS1_INSN_LDW, "ldw", "ldw", 32, - { 0|A(USES_FRSR1)|A(USES_FRDR)|A(MEMORY_ACCESS)|A(LOAD_DELAY), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR1)|A(USES_FRDR)|A(MEMORY_ACCESS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } } }, /* stw $frsr2,$frsr1,#$imm16 */ { MS1_INSN_STW, "stw", "stw", 32, - { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(MEMORY_ACCESS), { (1<<MACH_BASE) } } + { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(MEMORY_ACCESS), { { { (1<<MACH_BASE), 0 } } } } }, /* break */ { MS1_INSN_BREAK, "break", "break", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* iflush */ { MS1_INSN_IFLUSH, "iflush", "iflush", 32, - { 0, { (1<<MACH_MS1_003) } } + { 0, { { { (1<<MACH_MS1_003), 0 } } } } }, /* ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum */ { MS1_INSN_LDCTXT, "ldctxt", "ldctxt", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ldfb $frsr1,$frsr2,#$imm16z */ { MS1_INSN_LDFB, "ldfb", "ldfb", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* stfb $frsr1,$frsr2,#$imm16z */ { MS1_INSN_STFB, "stfb", "stfb", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ { MS1_INSN_FBCB, "fbcb", "fbcb", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mfbcb $frsr1,#$rbbc,$frsr2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ { MS1_INSN_MFBCB, "mfbcb", "mfbcb", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* fbcci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ { MS1_INSN_FBCCI, "fbcci", "fbcci", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* fbrci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ { MS1_INSN_FBRCI, "fbrci", "fbrci", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* fbcri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ { MS1_INSN_FBCRI, "fbcri", "fbcri", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* fbrri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ { MS1_INSN_FBRRI, "fbrri", "fbrri", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mfbcci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ { MS1_INSN_MFBCCI, "mfbcci", "mfbcci", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mfbrci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ { MS1_INSN_MFBRCI, "mfbrci", "mfbrci", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mfbcri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ { MS1_INSN_MFBCRI, "mfbcri", "mfbcri", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mfbrri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ { MS1_INSN_MFBRRI, "mfbrri", "mfbrri", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* fbcbdr $frsr1,#$rbbc,$frsr2,#$ball2,#$brc2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ { MS1_INSN_FBCBDR, "fbcbdr", "fbcbdr", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* rcfbcb #$rbbc,#$type,#$ball,#$brc,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ { MS1_INSN_RCFBCB, "rcfbcb", "rcfbcb", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mrcfbcb $frsr2,#$rbbc,#$type,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ { MS1_INSN_MRCFBCB, "mrcfbcb", "mrcfbcb", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* cbcast #$mask,#$rc2,#$ctxdisp */ { MS1_INSN_CBCAST, "cbcast", "cbcast", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* dupcbcast #$mask,#$cell,#$rc2,#$ctxdisp */ { MS1_INSN_DUPCBCAST, "dupcbcast", "dupcbcast", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* wfbi #$bankaddr,#$rownum1,#$cell,#$dup,#$ctxdisp */ { MS1_INSN_WFBI, "wfbi", "wfbi", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* wfb $frsr1,$frsr2,#$fbdisp,#$rownum2,#$ctxdisp */ { MS1_INSN_WFB, "wfb", "wfb", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* rcrisc $frdrrr,#$rbbc,$frsr1,#$colnum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ { MS1_INSN_RCRISC, "rcrisc", "rcrisc", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* fbcbinc $frsr1,#$rbbc,#$incamt,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ { MS1_INSN_FBCBINC, "fbcbinc", "fbcbinc", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* rcxmode $frsr2,#$rda,#$wr,#$xmode,#$mask1,#$fbdisp,#$rownum2,#$rc2,#$ctxdisp */ { MS1_INSN_RCXMODE, "rcxmode", "rcxmode", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* intlvr $frsr1,#$mode,$frsr2,#$id,#$size */ { MS1_INSN_INTERLEAVER, "interleaver", "intlvr", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ { MS1_INSN_WFBINC, "wfbinc", "wfbinc", 32, - { 0, { (1<<MACH_MS1_003) } } + { 0, { { { (1<<MACH_MS1_003), 0 } } } } }, /* mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ { MS1_INSN_MWFBINC, "mwfbinc", "mwfbinc", 32, - { 0, { (1<<MACH_MS1_003) } } + { 0, { { { (1<<MACH_MS1_003), 0 } } } } }, /* wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ { MS1_INSN_WFBINCR, "wfbincr", "wfbincr", 32, - { 0, { (1<<MACH_MS1_003) } } + { 0, { { { (1<<MACH_MS1_003), 0 } } } } }, /* mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ { MS1_INSN_MWFBINCR, "mwfbincr", "mwfbincr", 32, - { 0, { (1<<MACH_MS1_003) } } + { 0, { { { (1<<MACH_MS1_003), 0 } } } } }, /* fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ { MS1_INSN_FBCBINCS, "fbcbincs", "fbcbincs", 32, - { 0, { (1<<MACH_MS1_003) } } + { 0, { { { (1<<MACH_MS1_003), 0 } } } } }, /* mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ { MS1_INSN_MFBCBINCS, "mfbcbincs", "mfbcbincs", 32, - { 0, { (1<<MACH_MS1_003) } } + { 0, { { { (1<<MACH_MS1_003), 0 } } } } }, /* fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ { MS1_INSN_FBCBINCRS, "fbcbincrs", "fbcbincrs", 32, - { 0, { (1<<MACH_MS1_003) } } + { 0, { { { (1<<MACH_MS1_003), 0 } } } } }, /* mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ { MS1_INSN_MFBCBINCRS, "mfbcbincrs", "mfbcbincrs", 32, - { 0, { (1<<MACH_MS1_003) } } + { 0, { { { (1<<MACH_MS1_003), 0 } } } } }, }; @@ -1034,7 +1034,7 @@ static void ms1_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) { int i; - unsigned int isas = cd->isas; + CGEN_BITSET *isas = cd->isas; unsigned int machs = cd->machs; cd->int_insn_p = CGEN_INT_INSN_P; @@ -1046,7 +1046,7 @@ ms1_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) - if (((1 << i) & isas) != 0) + if (cgen_bitset_contains (isas, i)) { const CGEN_ISA *isa = & ms1_cgen_isa_table[i]; @@ -1131,7 +1131,7 @@ ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) { CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); static int init_p; - unsigned int isas = 0; /* 0 = "unspecified" */ + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ unsigned int machs = 0; /* 0 = "unspecified" */ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; va_list ap; @@ -1150,7 +1150,7 @@ ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) switch (arg_type) { case CGEN_CPU_OPEN_ISAS : - isas = va_arg (ap, unsigned int); + isas = va_arg (ap, CGEN_BITSET *); break; case CGEN_CPU_OPEN_MACHS : machs = va_arg (ap, unsigned int); @@ -1181,9 +1181,6 @@ ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) machs = (1 << MAX_MACHS) - 1; /* Base mach is always selected. */ machs |= 1; - /* ISA unspecified means "all". */ - if (isas == 0) - isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) { /* ??? If target has only one, could have a default. */ @@ -1191,7 +1188,7 @@ ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) abort (); } - cd->isas = isas; + cd->isas = cgen_bitset_copy (isas); cd->machs = machs; cd->endian = endian; /* FIXME: for the sparc case we can determine insn-endianness statically. diff --git a/opcodes/ms1-desc.h b/opcodes/ms1-desc.h index 9dfd4da44d2..4a3dd2f5e21 100644 --- a/opcodes/ms1-desc.h +++ b/opcodes/ms1-desc.h @@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc., #ifndef MS1_CPU_H #define MS1_CPU_H +#include "opcode/cgen-bitset.h" + #define CGEN_ARCH ms1 /* Given symbol S, return ms1_cgen_<S>. */ @@ -131,6 +133,15 @@ typedef enum cgen_ifld_attr { /* Number of non-boolean elements in cgen_ifld_attr. */ #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) + /* Enum declaration for ms1 ifield types. */ typedef enum ifield_type { MS1_F_NIL, MS1_F_ANYOF, MS1_F_MSYS, MS1_F_OPC @@ -166,6 +177,13 @@ typedef enum cgen_hw_attr { /* Number of non-boolean elements in cgen_hw_attr. */ #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) + /* Enum declaration for ms1 hardware types. */ typedef enum cgen_hw_type { HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR @@ -186,6 +204,17 @@ typedef enum cgen_operand_attr { /* Number of non-boolean elements in cgen_operand_attr. */ #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) + /* Enum declaration for ms1 operand types. */ typedef enum cgen_operand_type { MS1_OPERAND_PC, MS1_OPERAND_FRSR1, MS1_OPERAND_FRSR2, MS1_OPERAND_FRDR @@ -224,6 +253,29 @@ typedef enum cgen_insn_attr { /* Number of non-boolean elements in cgen_insn_attr. */ #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) +#define CGEN_ATTR_CGEN_INSN_LOAD_DELAY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_LOAD_DELAY)) != 0) +#define CGEN_ATTR_CGEN_INSN_MEMORY_ACCESS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_MEMORY_ACCESS)) != 0) +#define CGEN_ATTR_CGEN_INSN_AL_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_AL_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_IO_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_IO_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_BR_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_BR_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_USES_FRDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRDR)) != 0) +#define CGEN_ATTR_CGEN_INSN_USES_FRDRRR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRDRRR)) != 0) +#define CGEN_ATTR_CGEN_INSN_USES_FRSR1_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRSR1)) != 0) +#define CGEN_ATTR_CGEN_INSN_USES_FRSR2_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRSR2)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIPA_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIPA)) != 0) + /* cgen.h uses things we just defined. */ #include "opcode/cgen.h" diff --git a/opcodes/ms1-dis.c b/opcodes/ms1-dis.c index 980e8e09632..0026124f7db 100644 --- a/opcodes/ms1-dis.c +++ b/opcodes/ms1-dis.c @@ -4,7 +4,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-dis.in isn't - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -566,7 +566,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) typedef struct cpu_desc_list { struct cpu_desc_list *next; - int isa; + CGEN_BITSET *isa; int mach; int endian; CGEN_CPU_DESC cd; @@ -578,11 +578,12 @@ print_insn_ms1 (bfd_vma pc, disassemble_info *info) static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; static CGEN_CPU_DESC cd = 0; - static int prev_isa; + static CGEN_BITSET *prev_isa; static int prev_mach; static int prev_endian; int length; - int isa,mach; + CGEN_BITSET *isa; + int mach; int endian = (info->endian == BFD_ENDIAN_BIG ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); @@ -605,25 +606,34 @@ print_insn_ms1 (bfd_vma pc, disassemble_info *info) #endif #ifdef CGEN_COMPUTE_ISA - isa = CGEN_COMPUTE_ISA (info); + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } #else isa = info->insn_sets; #endif /* If we've switched cpu's, try to find a handle we've used before */ if (cd - && (isa != prev_isa + && (cgen_bitset_compare (isa, prev_isa) != 0 || mach != prev_mach || endian != prev_endian)) { cd = 0; for (cl = cd_list; cl; cl = cl->next) { - if (cl->isa == isa && + if (cgen_bitset_compare (cl->isa, isa) == 0 && cl->mach == mach && cl->endian == endian) { cd = cl->cd; + prev_isa = cd->isas; break; } } @@ -639,7 +649,7 @@ print_insn_ms1 (bfd_vma pc, disassemble_info *info) abort (); mach_name = arch_type->printable_name; - prev_isa = isa; + prev_isa = cgen_bitset_copy (isa); prev_mach = mach; prev_endian = endian; cd = ms1_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, @@ -652,7 +662,7 @@ print_insn_ms1 (bfd_vma pc, disassemble_info *info) /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; - cl->isa = isa; + cl->isa = prev_isa; cl->mach = mach; cl->endian = endian; cl->next = cd_list; diff --git a/opcodes/openrisc-desc.c b/opcodes/openrisc-desc.c index c469694cf59..5bdbeca536b 100644 --- a/opcodes/openrisc-desc.c +++ b/opcodes/openrisc-desc.c @@ -136,41 +136,41 @@ static const CGEN_MACH openrisc_cgen_mach_table[] = { static CGEN_KEYWORD_ENTRY openrisc_cgen_opval_h_gr_entries[] = { - { "r0", 0, {0, {0}}, 0, 0 }, - { "r1", 1, {0, {0}}, 0, 0 }, - { "r2", 2, {0, {0}}, 0, 0 }, - { "r3", 3, {0, {0}}, 0, 0 }, - { "r4", 4, {0, {0}}, 0, 0 }, - { "r5", 5, {0, {0}}, 0, 0 }, - { "r6", 6, {0, {0}}, 0, 0 }, - { "r7", 7, {0, {0}}, 0, 0 }, - { "r8", 8, {0, {0}}, 0, 0 }, - { "r9", 9, {0, {0}}, 0, 0 }, - { "r10", 10, {0, {0}}, 0, 0 }, - { "r11", 11, {0, {0}}, 0, 0 }, - { "r12", 12, {0, {0}}, 0, 0 }, - { "r13", 13, {0, {0}}, 0, 0 }, - { "r14", 14, {0, {0}}, 0, 0 }, - { "r15", 15, {0, {0}}, 0, 0 }, - { "r16", 16, {0, {0}}, 0, 0 }, - { "r17", 17, {0, {0}}, 0, 0 }, - { "r18", 18, {0, {0}}, 0, 0 }, - { "r19", 19, {0, {0}}, 0, 0 }, - { "r20", 20, {0, {0}}, 0, 0 }, - { "r21", 21, {0, {0}}, 0, 0 }, - { "r22", 22, {0, {0}}, 0, 0 }, - { "r23", 23, {0, {0}}, 0, 0 }, - { "r24", 24, {0, {0}}, 0, 0 }, - { "r25", 25, {0, {0}}, 0, 0 }, - { "r26", 26, {0, {0}}, 0, 0 }, - { "r27", 27, {0, {0}}, 0, 0 }, - { "r28", 28, {0, {0}}, 0, 0 }, - { "r29", 29, {0, {0}}, 0, 0 }, - { "r30", 30, {0, {0}}, 0, 0 }, - { "r31", 31, {0, {0}}, 0, 0 }, - { "lr", 11, {0, {0}}, 0, 0 }, - { "sp", 1, {0, {0}}, 0, 0 }, - { "fp", 2, {0, {0}}, 0, 0 } + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "r16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "r17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "r18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "r19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "r20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "r21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "r22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "r23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "r24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "r25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "r26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "r27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "r28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "r29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "r30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "r31", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "lr", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "fp", 2, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD openrisc_cgen_opval_h_gr = @@ -191,19 +191,19 @@ CGEN_KEYWORD openrisc_cgen_opval_h_gr = const CGEN_HW_ENTRY openrisc_cgen_hw_table[] = { - { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } }, - { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & openrisc_cgen_opval_h_gr, { 0|A(PROFILE), { (1<<MACH_BASE) } } }, - { "h-sr", HW_H_SR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-lo16", HW_H_LO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-delay-insn", HW_H_DELAY_INSN, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} } + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & openrisc_cgen_opval_h_gr, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-sr", HW_H_SR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-lo16", HW_H_LO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-delay-insn", HW_H_DELAY_INSN, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } }; #undef A @@ -219,37 +219,37 @@ const CGEN_HW_ENTRY openrisc_cgen_hw_table[] = const CGEN_IFLD openrisc_cgen_ifld_table[] = { - { OPENRISC_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, - { OPENRISC_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, - { OPENRISC_F_CLASS, "f-class", 0, 32, 31, 2, { 0, { (1<<MACH_BASE) } } }, - { OPENRISC_F_SUB, "f-sub", 0, 32, 29, 4, { 0, { (1<<MACH_BASE) } } }, - { OPENRISC_F_R1, "f-r1", 0, 32, 25, 5, { 0, { (1<<MACH_BASE) } } }, - { OPENRISC_F_R2, "f-r2", 0, 32, 20, 5, { 0, { (1<<MACH_BASE) } } }, - { OPENRISC_F_R3, "f-r3", 0, 32, 15, 5, { 0, { (1<<MACH_BASE) } } }, - { OPENRISC_F_SIMM16, "f-simm16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } } }, - { OPENRISC_F_UIMM16, "f-uimm16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } } }, - { OPENRISC_F_UIMM5, "f-uimm5", 0, 32, 4, 5, { 0, { (1<<MACH_BASE) } } }, - { OPENRISC_F_HI16, "f-hi16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } } }, - { OPENRISC_F_LO16, "f-lo16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } } }, - { OPENRISC_F_OP1, "f-op1", 0, 32, 31, 2, { 0, { (1<<MACH_BASE) } } }, - { OPENRISC_F_OP2, "f-op2", 0, 32, 29, 4, { 0, { (1<<MACH_BASE) } } }, - { OPENRISC_F_OP3, "f-op3", 0, 32, 25, 2, { 0, { (1<<MACH_BASE) } } }, - { OPENRISC_F_OP4, "f-op4", 0, 32, 23, 3, { 0, { (1<<MACH_BASE) } } }, - { OPENRISC_F_OP5, "f-op5", 0, 32, 25, 5, { 0, { (1<<MACH_BASE) } } }, - { OPENRISC_F_OP6, "f-op6", 0, 32, 7, 3, { 0, { (1<<MACH_BASE) } } }, - { OPENRISC_F_OP7, "f-op7", 0, 32, 3, 4, { 0, { (1<<MACH_BASE) } } }, - { OPENRISC_F_I16_1, "f-i16-1", 0, 32, 10, 11, { 0, { (1<<MACH_BASE) } } }, - { OPENRISC_F_I16_2, "f-i16-2", 0, 32, 25, 5, { 0, { (1<<MACH_BASE) } } }, - { OPENRISC_F_DISP26, "f-disp26", 0, 32, 25, 26, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, - { OPENRISC_F_ABS26, "f-abs26", 0, 32, 25, 26, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, - { OPENRISC_F_I16NC, "f-i16nc", 0, 0, 0, 0,{ 0|A(SIGN_OPT)|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { OPENRISC_F_F_15_8, "f-f-15-8", 0, 32, 15, 8, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { OPENRISC_F_F_10_3, "f-f-10-3", 0, 32, 10, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { OPENRISC_F_F_4_1, "f-f-4-1", 0, 32, 4, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { OPENRISC_F_F_7_3, "f-f-7-3", 0, 32, 7, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { OPENRISC_F_F_10_7, "f-f-10-7", 0, 32, 10, 7, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { OPENRISC_F_F_10_11, "f-f-10-11", 0, 32, 10, 11, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, - { 0, 0, 0, 0, 0, 0, {0, {0}} } + { OPENRISC_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_CLASS, "f-class", 0, 32, 31, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_SUB, "f-sub", 0, 32, 29, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_R1, "f-r1", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_R2, "f-r2", 0, 32, 20, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_R3, "f-r3", 0, 32, 15, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_SIMM16, "f-simm16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_UIMM16, "f-uimm16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_UIMM5, "f-uimm5", 0, 32, 4, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_HI16, "f-hi16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_LO16, "f-lo16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_OP1, "f-op1", 0, 32, 31, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_OP2, "f-op2", 0, 32, 29, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_OP3, "f-op3", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_OP4, "f-op4", 0, 32, 23, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_OP5, "f-op5", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_OP6, "f-op6", 0, 32, 7, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_OP7, "f-op7", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_I16_1, "f-i16-1", 0, 32, 10, 11, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_I16_2, "f-i16-2", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_DISP26, "f-disp26", 0, 32, 25, 26, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_ABS26, "f-abs26", 0, 32, 25, 26, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_I16NC, "f-i16nc", 0, 0, 0, 0,{ 0|A(SIGN_OPT)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_F_15_8, "f-f-15-8", 0, 32, 15, 8, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_F_10_3, "f-f-10-3", 0, 32, 10, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_F_4_1, "f-f-4-1", 0, 32, 4, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_F_7_3, "f-f-7-3", 0, 32, 7, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_F_10_7, "f-f-10-7", 0, 32, 10, 7, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { OPENRISC_F_F_10_11, "f-f-10-11", 0, 32, 10, 11, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } }; #undef A @@ -288,71 +288,71 @@ const CGEN_OPERAND openrisc_cgen_operand_table[] = /* pc: program counter */ { "pc", OPENRISC_OPERAND_PC, HW_H_PC, 0, 0, { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_NIL] } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* sr: special register */ { "sr", OPENRISC_OPERAND_SR, HW_H_SR, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* cbit: condition bit */ { "cbit", OPENRISC_OPERAND_CBIT, HW_H_CBIT, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* simm-16: 16 bit signed immediate */ { "simm-16", OPENRISC_OPERAND_SIMM_16, HW_H_SINT, 15, 16, { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_SIMM16] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* uimm-16: 16 bit unsigned immediate */ { "uimm-16", OPENRISC_OPERAND_UIMM_16, HW_H_UINT, 15, 16, { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_UIMM16] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* disp-26: pc-rel 26 bit */ { "disp-26", OPENRISC_OPERAND_DISP_26, HW_H_IADDR, 25, 26, { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_DISP26] } }, - { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, + { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, /* abs-26: abs 26 bit */ { "abs-26", OPENRISC_OPERAND_ABS_26, HW_H_IADDR, 25, 26, { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_ABS26] } }, - { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, + { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, /* uimm-5: imm5 */ { "uimm-5", OPENRISC_OPERAND_UIMM_5, HW_H_UINT, 4, 5, { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_UIMM5] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* rD: destination register */ { "rD", OPENRISC_OPERAND_RD, HW_H_GR, 25, 5, { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_R1] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* rA: source register A */ { "rA", OPENRISC_OPERAND_RA, HW_H_GR, 20, 5, { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_R2] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* rB: source register B */ { "rB", OPENRISC_OPERAND_RB, HW_H_GR, 15, 5, { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_R3] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* op-f-23: f-op23 */ { "op-f-23", OPENRISC_OPERAND_OP_F_23, HW_H_UINT, 23, 3, { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_OP4] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* op-f-3: f-op3 */ { "op-f-3", OPENRISC_OPERAND_OP_F_3, HW_H_UINT, 25, 5, { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_OP5] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* hi16: high 16 bit immediate, sign optional */ { "hi16", OPENRISC_OPERAND_HI16, HW_H_HI16, 15, 16, { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_SIMM16] } }, - { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } }, + { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, /* lo16: low 16 bit immediate, sign optional */ { "lo16", OPENRISC_OPERAND_LO16, HW_H_LO16, 15, 16, { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_LO16] } }, - { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } }, + { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, /* ui16nc: 16 bit immediate, sign optional */ { "ui16nc", OPENRISC_OPERAND_UI16NC, HW_H_LO16, 10, 16, { 2, { (const PTR) &OPENRISC_F_I16NC_MULTI_IFIELD[0] } }, - { 0|A(SIGN_OPT)|A(VIRTUAL), { (1<<MACH_BASE) } } }, + { 0|A(SIGN_OPT)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, /* sentinel */ { 0, 0, 0, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { 0 } } } + { 0, { { { (1<<MACH_BASE), 0 } } } } } }; #undef A @@ -372,326 +372,326 @@ static const CGEN_IBASE openrisc_cgen_insn_table[MAX_INSNS] = /* Special null first entry. A `num' value of zero is thus invalid. Also, the special `invalid' insn resides here. */ - { 0, 0, 0, 0, {0, {0}} }, + { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* l.j ${abs-26} */ { OPENRISC_INSN_L_J, "l-j", "l.j", 32, - { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.jal ${abs-26} */ { OPENRISC_INSN_L_JAL, "l-jal", "l.jal", 32, - { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.jr $rA */ { OPENRISC_INSN_L_JR, "l-jr", "l.jr", 32, - { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.jalr $rA */ { OPENRISC_INSN_L_JALR, "l-jalr", "l.jalr", 32, - { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.bal ${disp-26} */ { OPENRISC_INSN_L_BAL, "l-bal", "l.bal", 32, - { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.bnf ${disp-26} */ { OPENRISC_INSN_L_BNF, "l-bnf", "l.bnf", 32, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.bf ${disp-26} */ { OPENRISC_INSN_L_BF, "l-bf", "l.bf", 32, - { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.brk ${uimm-16} */ { OPENRISC_INSN_L_BRK, "l-brk", "l.brk", 32, - { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.rfe $rA */ { OPENRISC_INSN_L_RFE, "l-rfe", "l.rfe", 32, - { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sys ${uimm-16} */ { OPENRISC_INSN_L_SYS, "l-sys", "l.sys", 32, - { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.nop */ { OPENRISC_INSN_L_NOP, "l-nop", "l.nop", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* l.movhi $rD,$hi16 */ { OPENRISC_INSN_L_MOVHI, "l-movhi", "l.movhi", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.mfsr $rD,$rA */ { OPENRISC_INSN_L_MFSR, "l-mfsr", "l.mfsr", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.mtsr $rA,$rB */ { OPENRISC_INSN_L_MTSR, "l-mtsr", "l.mtsr", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.lw $rD,${simm-16}($rA) */ { OPENRISC_INSN_L_LW, "l-lw", "l.lw", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.lbz $rD,${simm-16}($rA) */ { OPENRISC_INSN_L_LBZ, "l-lbz", "l.lbz", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.lbs $rD,${simm-16}($rA) */ { OPENRISC_INSN_L_LBS, "l-lbs", "l.lbs", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.lhz $rD,${simm-16}($rA) */ { OPENRISC_INSN_L_LHZ, "l-lhz", "l.lhz", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.lhs $rD,${simm-16}($rA) */ { OPENRISC_INSN_L_LHS, "l-lhs", "l.lhs", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sw ${ui16nc}($rA),$rB */ { OPENRISC_INSN_L_SW, "l-sw", "l.sw", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sb ${ui16nc}($rA),$rB */ { OPENRISC_INSN_L_SB, "l-sb", "l.sb", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sh ${ui16nc}($rA),$rB */ { OPENRISC_INSN_L_SH, "l-sh", "l.sh", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sll $rD,$rA,$rB */ { OPENRISC_INSN_L_SLL, "l-sll", "l.sll", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* l.slli $rD,$rA,${uimm-5} */ { OPENRISC_INSN_L_SLLI, "l-slli", "l.slli", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* l.srl $rD,$rA,$rB */ { OPENRISC_INSN_L_SRL, "l-srl", "l.srl", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* l.srli $rD,$rA,${uimm-5} */ { OPENRISC_INSN_L_SRLI, "l-srli", "l.srli", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* l.sra $rD,$rA,$rB */ { OPENRISC_INSN_L_SRA, "l-sra", "l.sra", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* l.srai $rD,$rA,${uimm-5} */ { OPENRISC_INSN_L_SRAI, "l-srai", "l.srai", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* l.ror $rD,$rA,$rB */ { OPENRISC_INSN_L_ROR, "l-ror", "l.ror", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* l.rori $rD,$rA,${uimm-5} */ { OPENRISC_INSN_L_RORI, "l-rori", "l.rori", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* l.add $rD,$rA,$rB */ { OPENRISC_INSN_L_ADD, "l-add", "l.add", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* l.addi $rD,$rA,$lo16 */ { OPENRISC_INSN_L_ADDI, "l-addi", "l.addi", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* l.sub $rD,$rA,$rB */ { OPENRISC_INSN_L_SUB, "l-sub", "l.sub", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* l.subi $rD,$rA,$lo16 */ { OPENRISC_INSN_L_SUBI, "l-subi", "l.subi", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* l.and $rD,$rA,$rB */ { OPENRISC_INSN_L_AND, "l-and", "l.and", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* l.andi $rD,$rA,$lo16 */ { OPENRISC_INSN_L_ANDI, "l-andi", "l.andi", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* l.or $rD,$rA,$rB */ { OPENRISC_INSN_L_OR, "l-or", "l.or", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* l.ori $rD,$rA,$lo16 */ { OPENRISC_INSN_L_ORI, "l-ori", "l.ori", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* l.xor $rD,$rA,$rB */ { OPENRISC_INSN_L_XOR, "l-xor", "l.xor", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* l.xori $rD,$rA,$lo16 */ { OPENRISC_INSN_L_XORI, "l-xori", "l.xori", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* l.mul $rD,$rA,$rB */ { OPENRISC_INSN_L_MUL, "l-mul", "l.mul", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* l.muli $rD,$rA,$lo16 */ { OPENRISC_INSN_L_MULI, "l-muli", "l.muli", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* l.div $rD,$rA,$rB */ { OPENRISC_INSN_L_DIV, "l-div", "l.div", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.divu $rD,$rA,$rB */ { OPENRISC_INSN_L_DIVU, "l-divu", "l.divu", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sfgts $rA,$rB */ { OPENRISC_INSN_L_SFGTS, "l-sfgts", "l.sfgts", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sfgtu $rA,$rB */ { OPENRISC_INSN_L_SFGTU, "l-sfgtu", "l.sfgtu", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sfges $rA,$rB */ { OPENRISC_INSN_L_SFGES, "l-sfges", "l.sfges", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sfgeu $rA,$rB */ { OPENRISC_INSN_L_SFGEU, "l-sfgeu", "l.sfgeu", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sflts $rA,$rB */ { OPENRISC_INSN_L_SFLTS, "l-sflts", "l.sflts", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sfltu $rA,$rB */ { OPENRISC_INSN_L_SFLTU, "l-sfltu", "l.sfltu", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sfles $rA,$rB */ { OPENRISC_INSN_L_SFLES, "l-sfles", "l.sfles", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sfleu $rA,$rB */ { OPENRISC_INSN_L_SFLEU, "l-sfleu", "l.sfleu", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sfgtsi $rA,${simm-16} */ { OPENRISC_INSN_L_SFGTSI, "l-sfgtsi", "l.sfgtsi", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sfgtui $rA,${uimm-16} */ { OPENRISC_INSN_L_SFGTUI, "l-sfgtui", "l.sfgtui", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sfgesi $rA,${simm-16} */ { OPENRISC_INSN_L_SFGESI, "l-sfgesi", "l.sfgesi", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sfgeui $rA,${uimm-16} */ { OPENRISC_INSN_L_SFGEUI, "l-sfgeui", "l.sfgeui", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sfltsi $rA,${simm-16} */ { OPENRISC_INSN_L_SFLTSI, "l-sfltsi", "l.sfltsi", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sfltui $rA,${uimm-16} */ { OPENRISC_INSN_L_SFLTUI, "l-sfltui", "l.sfltui", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sflesi $rA,${simm-16} */ { OPENRISC_INSN_L_SFLESI, "l-sflesi", "l.sflesi", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sfleui $rA,${uimm-16} */ { OPENRISC_INSN_L_SFLEUI, "l-sfleui", "l.sfleui", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sfeq $rA,$rB */ { OPENRISC_INSN_L_SFEQ, "l-sfeq", "l.sfeq", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sfeqi $rA,${simm-16} */ { OPENRISC_INSN_L_SFEQI, "l-sfeqi", "l.sfeqi", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sfne $rA,$rB */ { OPENRISC_INSN_L_SFNE, "l-sfne", "l.sfne", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, /* l.sfnei $rA,${simm-16} */ { OPENRISC_INSN_L_SFNEI, "l-sfnei", "l.sfnei", 32, - { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } } + { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } }, }; @@ -814,7 +814,7 @@ static void openrisc_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) { int i; - unsigned int isas = cd->isas; + CGEN_BITSET *isas = cd->isas; unsigned int machs = cd->machs; cd->int_insn_p = CGEN_INT_INSN_P; @@ -826,7 +826,7 @@ openrisc_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) - if (((1 << i) & isas) != 0) + if (cgen_bitset_contains (isas, i)) { const CGEN_ISA *isa = & openrisc_cgen_isa_table[i]; @@ -911,7 +911,7 @@ openrisc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) { CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); static int init_p; - unsigned int isas = 0; /* 0 = "unspecified" */ + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ unsigned int machs = 0; /* 0 = "unspecified" */ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; va_list ap; @@ -930,7 +930,7 @@ openrisc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) switch (arg_type) { case CGEN_CPU_OPEN_ISAS : - isas = va_arg (ap, unsigned int); + isas = va_arg (ap, CGEN_BITSET *); break; case CGEN_CPU_OPEN_MACHS : machs = va_arg (ap, unsigned int); @@ -961,9 +961,6 @@ openrisc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) machs = (1 << MAX_MACHS) - 1; /* Base mach is always selected. */ machs |= 1; - /* ISA unspecified means "all". */ - if (isas == 0) - isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) { /* ??? If target has only one, could have a default. */ @@ -971,7 +968,7 @@ openrisc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) abort (); } - cd->isas = isas; + cd->isas = cgen_bitset_copy (isas); cd->machs = machs; cd->endian = endian; /* FIXME: for the sparc case we can determine insn-endianness statically. diff --git a/opcodes/openrisc-desc.h b/opcodes/openrisc-desc.h index b47da960eae..dd0ccf8b2a7 100644 --- a/opcodes/openrisc-desc.h +++ b/opcodes/openrisc-desc.h @@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc., #ifndef OPENRISC_CPU_H #define OPENRISC_CPU_H +#include "opcode/cgen-bitset.h" + #define CGEN_ARCH openrisc /* Given symbol S, return openrisc_cgen_<S>. */ @@ -154,6 +156,15 @@ typedef enum cgen_ifld_attr { /* Number of non-boolean elements in cgen_ifld_attr. */ #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) + /* Enum declaration for openrisc ifield types. */ typedef enum ifield_type { OPENRISC_F_NIL, OPENRISC_F_ANYOF, OPENRISC_F_CLASS, OPENRISC_F_SUB @@ -179,6 +190,13 @@ typedef enum cgen_hw_attr { /* Number of non-boolean elements in cgen_hw_attr. */ #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) + /* Enum declaration for openrisc hardware types. */ typedef enum cgen_hw_type { HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR @@ -201,6 +219,17 @@ typedef enum cgen_operand_attr { /* Number of non-boolean elements in cgen_operand_attr. */ #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) + /* Enum declaration for openrisc operand types. */ typedef enum cgen_operand_type { OPENRISC_OPERAND_PC, OPENRISC_OPERAND_SR, OPENRISC_OPERAND_CBIT, OPENRISC_OPERAND_SIMM_16 @@ -229,6 +258,20 @@ typedef enum cgen_insn_attr { /* Number of non-boolean elements in cgen_insn_attr. */ #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) +#define CGEN_ATTR_CGEN_INSN_NOT_IN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NOT_IN_DELAY_SLOT)) != 0) + /* cgen.h uses things we just defined. */ #include "opcode/cgen.h" diff --git a/opcodes/openrisc-dis.c b/opcodes/openrisc-dis.c index cb3f99b82e0..d3c4f681d95 100644 --- a/opcodes/openrisc-dis.c +++ b/opcodes/openrisc-dis.c @@ -4,7 +4,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-dis.in isn't - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -443,7 +443,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) typedef struct cpu_desc_list { struct cpu_desc_list *next; - int isa; + CGEN_BITSET *isa; int mach; int endian; CGEN_CPU_DESC cd; @@ -455,11 +455,12 @@ print_insn_openrisc (bfd_vma pc, disassemble_info *info) static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; static CGEN_CPU_DESC cd = 0; - static int prev_isa; + static CGEN_BITSET *prev_isa; static int prev_mach; static int prev_endian; int length; - int isa,mach; + CGEN_BITSET *isa; + int mach; int endian = (info->endian == BFD_ENDIAN_BIG ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); @@ -482,25 +483,34 @@ print_insn_openrisc (bfd_vma pc, disassemble_info *info) #endif #ifdef CGEN_COMPUTE_ISA - isa = CGEN_COMPUTE_ISA (info); + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } #else isa = info->insn_sets; #endif /* If we've switched cpu's, try to find a handle we've used before */ if (cd - && (isa != prev_isa + && (cgen_bitset_compare (isa, prev_isa) != 0 || mach != prev_mach || endian != prev_endian)) { cd = 0; for (cl = cd_list; cl; cl = cl->next) { - if (cl->isa == isa && + if (cgen_bitset_compare (cl->isa, isa) == 0 && cl->mach == mach && cl->endian == endian) { cd = cl->cd; + prev_isa = cd->isas; break; } } @@ -516,7 +526,7 @@ print_insn_openrisc (bfd_vma pc, disassemble_info *info) abort (); mach_name = arch_type->printable_name; - prev_isa = isa; + prev_isa = cgen_bitset_copy (isa); prev_mach = mach; prev_endian = endian; cd = openrisc_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, @@ -529,7 +539,7 @@ print_insn_openrisc (bfd_vma pc, disassemble_info *info) /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; - cl->isa = isa; + cl->isa = prev_isa; cl->mach = mach; cl->endian = endian; cl->next = cd_list; diff --git a/opcodes/openrisc-opc.c b/opcodes/openrisc-opc.c index 58aed98c667..ff9d52c37d8 100644 --- a/opcodes/openrisc-opc.c +++ b/opcodes/openrisc-opc.c @@ -560,7 +560,7 @@ static const CGEN_IBASE openrisc_cgen_macro_insn_table[] = /* l.ret */ { -1, "l-ret", "l.ret", 32, - { 0|A(ALIAS), { (1<<MACH_BASE) } } + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } }, }; diff --git a/opcodes/xstormy16-desc.c b/opcodes/xstormy16-desc.c index a63a4518499..80c7bf92984 100644 --- a/opcodes/xstormy16-desc.c +++ b/opcodes/xstormy16-desc.c @@ -126,24 +126,24 @@ static const CGEN_MACH xstormy16_cgen_mach_table[] = { static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_names_entries[] = { - { "r0", 0, {0, {0}}, 0, 0 }, - { "r1", 1, {0, {0}}, 0, 0 }, - { "r2", 2, {0, {0}}, 0, 0 }, - { "r3", 3, {0, {0}}, 0, 0 }, - { "r4", 4, {0, {0}}, 0, 0 }, - { "r5", 5, {0, {0}}, 0, 0 }, - { "r6", 6, {0, {0}}, 0, 0 }, - { "r7", 7, {0, {0}}, 0, 0 }, - { "r8", 8, {0, {0}}, 0, 0 }, - { "r9", 9, {0, {0}}, 0, 0 }, - { "r10", 10, {0, {0}}, 0, 0 }, - { "r11", 11, {0, {0}}, 0, 0 }, - { "r12", 12, {0, {0}}, 0, 0 }, - { "r13", 13, {0, {0}}, 0, 0 }, - { "r14", 14, {0, {0}}, 0, 0 }, - { "r15", 15, {0, {0}}, 0, 0 }, - { "psw", 14, {0, {0}}, 0, 0 }, - { "sp", 15, {0, {0}}, 0, 0 } + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "psw", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 15, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD xstormy16_cgen_opval_gr_names = @@ -155,16 +155,16 @@ CGEN_KEYWORD xstormy16_cgen_opval_gr_names = static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_Rb_names_entries[] = { - { "r8", 0, {0, {0}}, 0, 0 }, - { "r9", 1, {0, {0}}, 0, 0 }, - { "r10", 2, {0, {0}}, 0, 0 }, - { "r11", 3, {0, {0}}, 0, 0 }, - { "r12", 4, {0, {0}}, 0, 0 }, - { "r13", 5, {0, {0}}, 0, 0 }, - { "r14", 6, {0, {0}}, 0, 0 }, - { "r15", 7, {0, {0}}, 0, 0 }, - { "psw", 6, {0, {0}}, 0, 0 }, - { "sp", 7, {0, {0}}, 0, 0 } + { "r8", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r9", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r10", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r11", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "r12", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "r13", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "r14", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "r15", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "psw", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 7, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names = @@ -176,22 +176,22 @@ CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names = static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_branchcond_entries[] = { - { "ge", 0, {0, {0}}, 0, 0 }, - { "nc", 1, {0, {0}}, 0, 0 }, - { "lt", 2, {0, {0}}, 0, 0 }, - { "c", 3, {0, {0}}, 0, 0 }, - { "gt", 4, {0, {0}}, 0, 0 }, - { "hi", 5, {0, {0}}, 0, 0 }, - { "le", 6, {0, {0}}, 0, 0 }, - { "ls", 7, {0, {0}}, 0, 0 }, - { "pl", 8, {0, {0}}, 0, 0 }, - { "nv", 9, {0, {0}}, 0, 0 }, - { "mi", 10, {0, {0}}, 0, 0 }, - { "v", 11, {0, {0}}, 0, 0 }, - { "nz.b", 12, {0, {0}}, 0, 0 }, - { "nz", 13, {0, {0}}, 0, 0 }, - { "z.b", 14, {0, {0}}, 0, 0 }, - { "z", 15, {0, {0}}, 0, 0 } + { "ge", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "nc", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "lt", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "c", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "gt", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "hi", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "le", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "ls", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "pl", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "nv", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "mi", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "v", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "nz.b", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "nz", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "z.b", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "z", 15, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD xstormy16_cgen_opval_h_branchcond = @@ -203,9 +203,9 @@ CGEN_KEYWORD xstormy16_cgen_opval_h_branchcond = static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_wordsize_entries[] = { - { ".b", 0, {0, {0}}, 0, 0 }, - { ".w", 1, {0, {0}}, 0, 0 }, - { "", 1, {0, {0}}, 0, 0 } + { ".b", 0, {0, {{{0, 0}}}}, 0, 0 }, + { ".w", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "", 1, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD xstormy16_cgen_opval_h_wordsize = @@ -226,26 +226,26 @@ CGEN_KEYWORD xstormy16_cgen_opval_h_wordsize = const CGEN_HW_ENTRY xstormy16_cgen_hw_table[] = { - { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { (1<<MACH_BASE) } } }, - { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_names, { 0, { (1<<MACH_BASE) } } }, - { "h-Rb", HW_H_RB, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-Rbj", HW_H_RBJ, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-Rpsw", HW_H_RPSW, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-z8", HW_H_Z8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-z16", HW_H_Z16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-cy", HW_H_CY, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-hc", HW_H_HC, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-ov", HW_H_OV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-pt", HW_H_PT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-s", HW_H_S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-branchcond", HW_H_BRANCHCOND, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_branchcond, { 0, { (1<<MACH_BASE) } } }, - { "h-wordsize", HW_H_WORDSIZE, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_wordsize, { 0, { (1<<MACH_BASE) } } }, - { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} } + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-Rb", HW_H_RB, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-Rbj", HW_H_RBJ, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-Rpsw", HW_H_RPSW, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-z8", HW_H_Z8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-z16", HW_H_Z16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-cy", HW_H_CY, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-hc", HW_H_HC, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-ov", HW_H_OV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-pt", HW_H_PT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-s", HW_H_S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-branchcond", HW_H_BRANCHCOND, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_branchcond, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-wordsize", HW_H_WORDSIZE, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_wordsize, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } }; #undef A @@ -261,44 +261,44 @@ const CGEN_HW_ENTRY xstormy16_cgen_hw_table[] = const CGEN_IFLD xstormy16_cgen_ifld_table[] = { - { XSTORMY16_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_RD, "f-Rd", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_RDM, "f-Rdm", 0, 32, 13, 3, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_RM, "f-Rm", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_RS, "f-Rs", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_RB, "f-Rb", 0, 32, 17, 3, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_RBJ, "f-Rbj", 0, 32, 11, 1, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_OP2, "f-op2", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_OP2A, "f-op2a", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_OP2M, "f-op2m", 0, 32, 7, 1, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_OP3, "f-op3", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_OP3A, "f-op3a", 0, 32, 8, 2, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_OP3B, "f-op3b", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_OP4, "f-op4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_OP4M, "f-op4m", 0, 32, 12, 1, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_OP4B, "f-op4b", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_OP5, "f-op5", 0, 32, 16, 4, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_OP5A, "f-op5a", 0, 32, 16, 1, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_OP, "f-op", 0, 32, 0, 16, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_IMM2, "f-imm2", 0, 32, 10, 2, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_IMM3, "f-imm3", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_IMM3B, "f-imm3b", 0, 32, 17, 3, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_IMM4, "f-imm4", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_IMM8, "f-imm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_IMM12, "f-imm12", 0, 32, 20, 12, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_IMM16, "f-imm16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } }, - { XSTORMY16_F_LMEM8, "f-lmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, - { XSTORMY16_F_HMEM8, "f-hmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, - { XSTORMY16_F_REL8_2, "f-rel8-2", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, - { XSTORMY16_F_REL8_4, "f-rel8-4", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, - { XSTORMY16_F_REL12, "f-rel12", 0, 32, 20, 12, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, - { XSTORMY16_F_REL12A, "f-rel12a", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, - { XSTORMY16_F_ABS24_1, "f-abs24-1", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_ABS24_2, "f-abs24-2", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } }, - { XSTORMY16_F_ABS24, "f-abs24", 0, 0, 0, 0,{ 0|A(ABS_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { 0, 0, 0, 0, 0, 0, {0, {0}} } + { XSTORMY16_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_RD, "f-Rd", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_RDM, "f-Rdm", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_RM, "f-Rm", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_RS, "f-Rs", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_RB, "f-Rb", 0, 32, 17, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_RBJ, "f-Rbj", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_OP2, "f-op2", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_OP2A, "f-op2a", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_OP2M, "f-op2m", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_OP3, "f-op3", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_OP3A, "f-op3a", 0, 32, 8, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_OP3B, "f-op3b", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_OP4, "f-op4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_OP4M, "f-op4m", 0, 32, 12, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_OP4B, "f-op4b", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_OP5, "f-op5", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_OP5A, "f-op5a", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_OP, "f-op", 0, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_IMM2, "f-imm2", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_IMM3, "f-imm3", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_IMM3B, "f-imm3b", 0, 32, 17, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_IMM4, "f-imm4", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_IMM8, "f-imm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_IMM12, "f-imm12", 0, 32, 20, 12, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_IMM16, "f-imm16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_LMEM8, "f-lmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_HMEM8, "f-hmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_REL8_2, "f-rel8-2", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_REL8_4, "f-rel8-4", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_REL12, "f-rel12", 0, 32, 20, 12, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_REL12A, "f-rel12a", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_ABS24_1, "f-abs24-1", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_ABS24_2, "f-abs24-2", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { XSTORMY16_F_ABS24, "f-abs24", 0, 0, 0, 0,{ 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } }; #undef A @@ -337,163 +337,163 @@ const CGEN_OPERAND xstormy16_cgen_operand_table[] = /* pc: program counter */ { "pc", XSTORMY16_OPERAND_PC, HW_H_PC, 0, 0, { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_NIL] } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* psw-z8: */ { "psw-z8", XSTORMY16_OPERAND_PSW_Z8, HW_H_Z8, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* psw-z16: */ { "psw-z16", XSTORMY16_OPERAND_PSW_Z16, HW_H_Z16, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* psw-cy: */ { "psw-cy", XSTORMY16_OPERAND_PSW_CY, HW_H_CY, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* psw-hc: */ { "psw-hc", XSTORMY16_OPERAND_PSW_HC, HW_H_HC, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* psw-ov: */ { "psw-ov", XSTORMY16_OPERAND_PSW_OV, HW_H_OV, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* psw-pt: */ { "psw-pt", XSTORMY16_OPERAND_PSW_PT, HW_H_PT, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* psw-s: */ { "psw-s", XSTORMY16_OPERAND_PSW_S, HW_H_S, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* Rd: general register destination */ { "Rd", XSTORMY16_OPERAND_RD, HW_H_GR, 12, 4, { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RD] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* Rdm: general register destination */ { "Rdm", XSTORMY16_OPERAND_RDM, HW_H_GR, 13, 3, { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RDM] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* Rm: general register for memory */ { "Rm", XSTORMY16_OPERAND_RM, HW_H_GR, 4, 3, { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RM] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* Rs: general register source */ { "Rs", XSTORMY16_OPERAND_RS, HW_H_GR, 8, 4, { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RS] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* Rb: base register */ { "Rb", XSTORMY16_OPERAND_RB, HW_H_RB, 17, 3, { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RB] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* Rbj: base register for jump */ { "Rbj", XSTORMY16_OPERAND_RBJ, HW_H_RBJ, 11, 1, { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RBJ] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* bcond2: branch condition opcode */ { "bcond2", XSTORMY16_OPERAND_BCOND2, HW_H_BRANCHCOND, 4, 4, { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ws2: word size opcode */ { "ws2", XSTORMY16_OPERAND_WS2, HW_H_WORDSIZE, 7, 1, { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2M] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* bcond5: branch condition opcode */ { "bcond5", XSTORMY16_OPERAND_BCOND5, HW_H_BRANCHCOND, 16, 4, { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP5] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* imm2: 2 bit unsigned immediate */ { "imm2", XSTORMY16_OPERAND_IMM2, HW_H_UINT, 10, 2, { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM2] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* imm3: 3 bit unsigned immediate */ { "imm3", XSTORMY16_OPERAND_IMM3, HW_H_UINT, 4, 3, { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* imm3b: 3 bit unsigned immediate for bit tests */ { "imm3b", XSTORMY16_OPERAND_IMM3B, HW_H_UINT, 17, 3, { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3B] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* imm4: 4 bit unsigned immediate */ { "imm4", XSTORMY16_OPERAND_IMM4, HW_H_UINT, 8, 4, { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM4] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* imm8: 8 bit unsigned immediate */ { "imm8", XSTORMY16_OPERAND_IMM8, HW_H_UINT, 8, 8, { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* imm8small: 8 bit unsigned immediate */ { "imm8small", XSTORMY16_OPERAND_IMM8SMALL, HW_H_UINT, 8, 8, { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* imm12: 12 bit signed immediate */ { "imm12", XSTORMY16_OPERAND_IMM12, HW_H_SINT, 20, 12, { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM12] } }, - { 0, { (1<<MACH_BASE) } } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* imm16: 16 bit immediate */ { "imm16", XSTORMY16_OPERAND_IMM16, HW_H_UINT, 16, 16, { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM16] } }, - { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } }, + { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, /* lmem8: 8 bit unsigned immediate low memory */ { "lmem8", XSTORMY16_OPERAND_LMEM8, HW_H_UINT, 8, 8, { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_LMEM8] } }, - { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, + { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, /* hmem8: 8 bit unsigned immediate high memory */ { "hmem8", XSTORMY16_OPERAND_HMEM8, HW_H_UINT, 8, 8, { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_HMEM8] } }, - { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, + { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, /* rel8-2: 8 bit relative address */ { "rel8-2", XSTORMY16_OPERAND_REL8_2, HW_H_UINT, 8, 8, { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_2] } }, - { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, + { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, /* rel8-4: 8 bit relative address */ { "rel8-4", XSTORMY16_OPERAND_REL8_4, HW_H_UINT, 8, 8, { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_4] } }, - { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, + { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, /* rel12: 12 bit relative address */ { "rel12", XSTORMY16_OPERAND_REL12, HW_H_UINT, 20, 12, { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12] } }, - { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, + { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, /* rel12a: 12 bit relative address */ { "rel12a", XSTORMY16_OPERAND_REL12A, HW_H_UINT, 4, 11, { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12A] } }, - { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, + { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, /* abs24: 24 bit absolute address */ { "abs24", XSTORMY16_OPERAND_ABS24, HW_H_UINT, 8, 24, { 2, { (const PTR) &XSTORMY16_F_ABS24_MULTI_IFIELD[0] } }, - { 0|A(ABS_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } }, + { 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, /* psw: program status word */ { "psw", XSTORMY16_OPERAND_PSW, HW_H_GR, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* Rpsw: N0-N3 of the program status word */ { "Rpsw", XSTORMY16_OPERAND_RPSW, HW_H_RPSW, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* sp: stack pointer */ { "sp", XSTORMY16_OPERAND_SP, HW_H_GR, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* R0: R0 */ { "R0", XSTORMY16_OPERAND_R0, HW_H_GR, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* R1: R1 */ { "R1", XSTORMY16_OPERAND_R1, HW_H_GR, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* R2: R2 */ { "R2", XSTORMY16_OPERAND_R2, HW_H_GR, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* R8: R8 */ { "R8", XSTORMY16_OPERAND_R8, HW_H_GR, 0, 0, { 0, { (const PTR) 0 } }, - { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* sentinel */ { 0, 0, 0, 0, 0, { 0, { (const PTR) 0 } }, - { 0, { 0 } } } + { 0, { { { (1<<MACH_BASE), 0 } } } } } }; #undef A @@ -513,646 +513,646 @@ static const CGEN_IBASE xstormy16_cgen_insn_table[MAX_INSNS] = /* Special null first entry. A `num' value of zero is thus invalid. Also, the special `invalid' insn resides here. */ - { 0, 0, 0, 0, {0, {0}} }, + { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov$ws2 $lmem8,#$imm16 */ { XSTORMY16_INSN_MOVLMEMIMM, "movlmemimm", "mov", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov$ws2 $hmem8,#$imm16 */ { XSTORMY16_INSN_MOVHMEMIMM, "movhmemimm", "mov", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov$ws2 $Rm,$lmem8 */ { XSTORMY16_INSN_MOVLGRMEM, "movlgrmem", "mov", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov$ws2 $Rm,$hmem8 */ { XSTORMY16_INSN_MOVHGRMEM, "movhgrmem", "mov", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov$ws2 $lmem8,$Rm */ { XSTORMY16_INSN_MOVLMEMGR, "movlmemgr", "mov", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov$ws2 $hmem8,$Rm */ { XSTORMY16_INSN_MOVHMEMGR, "movhmemgr", "mov", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov$ws2 $Rdm,($Rs) */ { XSTORMY16_INSN_MOVGRGRI, "movgrgri", "mov", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov$ws2 $Rdm,($Rs++) */ { XSTORMY16_INSN_MOVGRGRIPOSTINC, "movgrgripostinc", "mov", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov$ws2 $Rdm,(--$Rs) */ { XSTORMY16_INSN_MOVGRGRIPREDEC, "movgrgripredec", "mov", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov$ws2 ($Rs),$Rdm */ { XSTORMY16_INSN_MOVGRIGR, "movgrigr", "mov", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov$ws2 ($Rs++),$Rdm */ { XSTORMY16_INSN_MOVGRIPOSTINCGR, "movgripostincgr", "mov", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov$ws2 (--$Rs),$Rdm */ { XSTORMY16_INSN_MOVGRIPREDECGR, "movgripredecgr", "mov", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov$ws2 $Rdm,($Rs,$imm12) */ { XSTORMY16_INSN_MOVGRGRII, "movgrgrii", "mov", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov$ws2 $Rdm,($Rs++,$imm12) */ { XSTORMY16_INSN_MOVGRGRIIPOSTINC, "movgrgriipostinc", "mov", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov$ws2 $Rdm,(--$Rs,$imm12) */ { XSTORMY16_INSN_MOVGRGRIIPREDEC, "movgrgriipredec", "mov", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov$ws2 ($Rs,$imm12),$Rdm */ { XSTORMY16_INSN_MOVGRIIGR, "movgriigr", "mov", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov$ws2 ($Rs++,$imm12),$Rdm */ { XSTORMY16_INSN_MOVGRIIPOSTINCGR, "movgriipostincgr", "mov", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov$ws2 (--$Rs,$imm12),$Rdm */ { XSTORMY16_INSN_MOVGRIIPREDECGR, "movgriipredecgr", "mov", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov $Rd,$Rs */ { XSTORMY16_INSN_MOVGRGR, "movgrgr", "mov", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov.w Rx,#$imm8 */ { XSTORMY16_INSN_MOVWIMM8, "movwimm8", "mov.w", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov.w $Rm,#$imm8small */ { XSTORMY16_INSN_MOVWGRIMM8, "movwgrimm8", "mov.w", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov.w $Rd,#$imm16 */ { XSTORMY16_INSN_MOVWGRIMM16, "movwgrimm16", "mov.w", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov.b $Rd,RxL */ { XSTORMY16_INSN_MOVLOWGR, "movlowgr", "mov.b", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mov.b $Rd,RxH */ { XSTORMY16_INSN_MOVHIGHGR, "movhighgr", "mov.b", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* movf$ws2 $Rdm,($Rs) */ { XSTORMY16_INSN_MOVFGRGRI, "movfgrgri", "movf", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* movf$ws2 $Rdm,($Rs++) */ { XSTORMY16_INSN_MOVFGRGRIPOSTINC, "movfgrgripostinc", "movf", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* movf$ws2 $Rdm,(--$Rs) */ { XSTORMY16_INSN_MOVFGRGRIPREDEC, "movfgrgripredec", "movf", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* movf$ws2 ($Rs),$Rdm */ { XSTORMY16_INSN_MOVFGRIGR, "movfgrigr", "movf", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* movf$ws2 ($Rs++),$Rdm */ { XSTORMY16_INSN_MOVFGRIPOSTINCGR, "movfgripostincgr", "movf", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* movf$ws2 (--$Rs),$Rdm */ { XSTORMY16_INSN_MOVFGRIPREDECGR, "movfgripredecgr", "movf", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* movf$ws2 $Rdm,($Rb,$Rs,$imm12) */ { XSTORMY16_INSN_MOVFGRGRII, "movfgrgrii", "movf", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* movf$ws2 $Rdm,($Rb,$Rs++,$imm12) */ { XSTORMY16_INSN_MOVFGRGRIIPOSTINC, "movfgrgriipostinc", "movf", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* movf$ws2 $Rdm,($Rb,--$Rs,$imm12) */ { XSTORMY16_INSN_MOVFGRGRIIPREDEC, "movfgrgriipredec", "movf", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* movf$ws2 ($Rb,$Rs,$imm12),$Rdm */ { XSTORMY16_INSN_MOVFGRIIGR, "movfgriigr", "movf", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* movf$ws2 ($Rb,$Rs++,$imm12),$Rdm */ { XSTORMY16_INSN_MOVFGRIIPOSTINCGR, "movfgriipostincgr", "movf", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* movf$ws2 ($Rb,--$Rs,$imm12),$Rdm */ { XSTORMY16_INSN_MOVFGRIIPREDECGR, "movfgriipredecgr", "movf", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mask $Rd,$Rs */ { XSTORMY16_INSN_MASKGRGR, "maskgrgr", "mask", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* mask $Rd,#$imm16 */ { XSTORMY16_INSN_MASKGRIMM16, "maskgrimm16", "mask", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* push $Rd */ { XSTORMY16_INSN_PUSHGR, "pushgr", "push", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* pop $Rd */ { XSTORMY16_INSN_POPGR, "popgr", "pop", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* swpn $Rd */ { XSTORMY16_INSN_SWPN, "swpn", "swpn", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* swpb $Rd */ { XSTORMY16_INSN_SWPB, "swpb", "swpb", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* swpw $Rd,$Rs */ { XSTORMY16_INSN_SWPW, "swpw", "swpw", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* and $Rd,$Rs */ { XSTORMY16_INSN_ANDGRGR, "andgrgr", "and", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* and Rx,#$imm8 */ { XSTORMY16_INSN_ANDIMM8, "andimm8", "and", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* and $Rd,#$imm16 */ { XSTORMY16_INSN_ANDGRIMM16, "andgrimm16", "and", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* or $Rd,$Rs */ { XSTORMY16_INSN_ORGRGR, "orgrgr", "or", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* or Rx,#$imm8 */ { XSTORMY16_INSN_ORIMM8, "orimm8", "or", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* or $Rd,#$imm16 */ { XSTORMY16_INSN_ORGRIMM16, "orgrimm16", "or", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* xor $Rd,$Rs */ { XSTORMY16_INSN_XORGRGR, "xorgrgr", "xor", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* xor Rx,#$imm8 */ { XSTORMY16_INSN_XORIMM8, "xorimm8", "xor", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* xor $Rd,#$imm16 */ { XSTORMY16_INSN_XORGRIMM16, "xorgrimm16", "xor", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* not $Rd */ { XSTORMY16_INSN_NOTGR, "notgr", "not", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* add $Rd,$Rs */ { XSTORMY16_INSN_ADDGRGR, "addgrgr", "add", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* add $Rd,#$imm4 */ { XSTORMY16_INSN_ADDGRIMM4, "addgrimm4", "add", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* add Rx,#$imm8 */ { XSTORMY16_INSN_ADDIMM8, "addimm8", "add", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* add $Rd,#$imm16 */ { XSTORMY16_INSN_ADDGRIMM16, "addgrimm16", "add", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* adc $Rd,$Rs */ { XSTORMY16_INSN_ADCGRGR, "adcgrgr", "adc", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* adc $Rd,#$imm4 */ { XSTORMY16_INSN_ADCGRIMM4, "adcgrimm4", "adc", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* adc Rx,#$imm8 */ { XSTORMY16_INSN_ADCIMM8, "adcimm8", "adc", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* adc $Rd,#$imm16 */ { XSTORMY16_INSN_ADCGRIMM16, "adcgrimm16", "adc", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* sub $Rd,$Rs */ { XSTORMY16_INSN_SUBGRGR, "subgrgr", "sub", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* sub $Rd,#$imm4 */ { XSTORMY16_INSN_SUBGRIMM4, "subgrimm4", "sub", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* sub Rx,#$imm8 */ { XSTORMY16_INSN_SUBIMM8, "subimm8", "sub", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* sub $Rd,#$imm16 */ { XSTORMY16_INSN_SUBGRIMM16, "subgrimm16", "sub", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* sbc $Rd,$Rs */ { XSTORMY16_INSN_SBCGRGR, "sbcgrgr", "sbc", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* sbc $Rd,#$imm4 */ { XSTORMY16_INSN_SBCGRIMM4, "sbcgrimm4", "sbc", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* sbc Rx,#$imm8 */ { XSTORMY16_INSN_SBCGRIMM8, "sbcgrimm8", "sbc", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* sbc $Rd,#$imm16 */ { XSTORMY16_INSN_SBCGRIMM16, "sbcgrimm16", "sbc", 32, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* inc $Rd,#$imm2 */ { XSTORMY16_INSN_INCGRIMM2, "incgrimm2", "inc", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* dec $Rd,#$imm2 */ { XSTORMY16_INSN_DECGRIMM2, "decgrimm2", "dec", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* rrc $Rd,$Rs */ { XSTORMY16_INSN_RRCGRGR, "rrcgrgr", "rrc", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* rrc $Rd,#$imm4 */ { XSTORMY16_INSN_RRCGRIMM4, "rrcgrimm4", "rrc", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* rlc $Rd,$Rs */ { XSTORMY16_INSN_RLCGRGR, "rlcgrgr", "rlc", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* rlc $Rd,#$imm4 */ { XSTORMY16_INSN_RLCGRIMM4, "rlcgrimm4", "rlc", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* shr $Rd,$Rs */ { XSTORMY16_INSN_SHRGRGR, "shrgrgr", "shr", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* shr $Rd,#$imm4 */ { XSTORMY16_INSN_SHRGRIMM, "shrgrimm", "shr", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* shl $Rd,$Rs */ { XSTORMY16_INSN_SHLGRGR, "shlgrgr", "shl", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* shl $Rd,#$imm4 */ { XSTORMY16_INSN_SHLGRIMM, "shlgrimm", "shl", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* asr $Rd,$Rs */ { XSTORMY16_INSN_ASRGRGR, "asrgrgr", "asr", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* asr $Rd,#$imm4 */ { XSTORMY16_INSN_ASRGRIMM, "asrgrimm", "asr", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* set1 $Rd,#$imm4 */ { XSTORMY16_INSN_SET1GRIMM, "set1grimm", "set1", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* set1 $Rd,$Rs */ { XSTORMY16_INSN_SET1GRGR, "set1grgr", "set1", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* set1 $lmem8,#$imm3 */ { XSTORMY16_INSN_SET1LMEMIMM, "set1lmemimm", "set1", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* set1 $hmem8,#$imm3 */ { XSTORMY16_INSN_SET1HMEMIMM, "set1hmemimm", "set1", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* clr1 $Rd,#$imm4 */ { XSTORMY16_INSN_CLR1GRIMM, "clr1grimm", "clr1", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* clr1 $Rd,$Rs */ { XSTORMY16_INSN_CLR1GRGR, "clr1grgr", "clr1", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* clr1 $lmem8,#$imm3 */ { XSTORMY16_INSN_CLR1LMEMIMM, "clr1lmemimm", "clr1", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* clr1 $hmem8,#$imm3 */ { XSTORMY16_INSN_CLR1HMEMIMM, "clr1hmemimm", "clr1", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* cbw $Rd */ { XSTORMY16_INSN_CBWGR, "cbwgr", "cbw", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* rev $Rd */ { XSTORMY16_INSN_REVGR, "revgr", "rev", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* b$bcond5 $Rd,$Rs,$rel12 */ { XSTORMY16_INSN_BCCGRGR, "bccgrgr", "b", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* b$bcond5 $Rm,#$imm8,$rel12 */ { XSTORMY16_INSN_BCCGRIMM8, "bccgrimm8", "b", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* b$bcond2 Rx,#$imm16,${rel8-4} */ { XSTORMY16_INSN_BCCIMM16, "bccimm16", "b", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* bn $Rd,#$imm4,$rel12 */ { XSTORMY16_INSN_BNGRIMM4, "bngrimm4", "bn", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* bn $Rd,$Rs,$rel12 */ { XSTORMY16_INSN_BNGRGR, "bngrgr", "bn", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* bn $lmem8,#$imm3b,$rel12 */ { XSTORMY16_INSN_BNLMEMIMM, "bnlmemimm", "bn", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* bn $hmem8,#$imm3b,$rel12 */ { XSTORMY16_INSN_BNHMEMIMM, "bnhmemimm", "bn", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* bp $Rd,#$imm4,$rel12 */ { XSTORMY16_INSN_BPGRIMM4, "bpgrimm4", "bp", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* bp $Rd,$Rs,$rel12 */ { XSTORMY16_INSN_BPGRGR, "bpgrgr", "bp", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* bp $lmem8,#$imm3b,$rel12 */ { XSTORMY16_INSN_BPLMEMIMM, "bplmemimm", "bp", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* bp $hmem8,#$imm3b,$rel12 */ { XSTORMY16_INSN_BPHMEMIMM, "bphmemimm", "bp", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* b$bcond2 ${rel8-2} */ { XSTORMY16_INSN_BCC, "bcc", "b", 16, - { 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* br $Rd */ { XSTORMY16_INSN_BGR, "bgr", "br", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* br $rel12a */ { XSTORMY16_INSN_BR, "br", "br", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* jmp $Rbj,$Rd */ { XSTORMY16_INSN_JMP, "jmp", "jmp", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* jmpf $abs24 */ { XSTORMY16_INSN_JMPF, "jmpf", "jmpf", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* callr $Rd */ { XSTORMY16_INSN_CALLRGR, "callrgr", "callr", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* callr $rel12a */ { XSTORMY16_INSN_CALLRIMM, "callrimm", "callr", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* call $Rbj,$Rd */ { XSTORMY16_INSN_CALLGR, "callgr", "call", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* callf $abs24 */ { XSTORMY16_INSN_CALLFIMM, "callfimm", "callf", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* icallr $Rd */ { XSTORMY16_INSN_ICALLRGR, "icallrgr", "icallr", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* icall $Rbj,$Rd */ { XSTORMY16_INSN_ICALLGR, "icallgr", "icall", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* icallf $abs24 */ { XSTORMY16_INSN_ICALLFIMM, "icallfimm", "icallf", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* iret */ { XSTORMY16_INSN_IRET, "iret", "iret", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* ret */ { XSTORMY16_INSN_RET, "ret", "ret", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } }, /* mul */ { XSTORMY16_INSN_MUL, "mul", "mul", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* div */ { XSTORMY16_INSN_DIV, "div", "div", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* sdiv */ { XSTORMY16_INSN_SDIV, "sdiv", "sdiv", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* sdivlh */ { XSTORMY16_INSN_SDIVLH, "sdivlh", "sdivlh", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* divlh */ { XSTORMY16_INSN_DIVLH, "divlh", "divlh", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* reset */ { XSTORMY16_INSN_RESET, "reset", "reset", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* nop */ { XSTORMY16_INSN_NOP, "nop", "nop", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* halt */ { XSTORMY16_INSN_HALT, "halt", "halt", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* hold */ { XSTORMY16_INSN_HOLD, "hold", "hold", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* holdx */ { XSTORMY16_INSN_HOLDX, "holdx", "holdx", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* brk */ { XSTORMY16_INSN_BRK, "brk", "brk", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* --unused-- */ { XSTORMY16_INSN_SYSCALL, "syscall", "--unused--", 16, - { 0, { (1<<MACH_BASE) } } + { 0, { { { (1<<MACH_BASE), 0 } } } } }, }; @@ -1275,7 +1275,7 @@ static void xstormy16_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) { int i; - unsigned int isas = cd->isas; + CGEN_BITSET *isas = cd->isas; unsigned int machs = cd->machs; cd->int_insn_p = CGEN_INT_INSN_P; @@ -1287,7 +1287,7 @@ xstormy16_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) - if (((1 << i) & isas) != 0) + if (cgen_bitset_contains (isas, i)) { const CGEN_ISA *isa = & xstormy16_cgen_isa_table[i]; @@ -1372,7 +1372,7 @@ xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) { CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); static int init_p; - unsigned int isas = 0; /* 0 = "unspecified" */ + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ unsigned int machs = 0; /* 0 = "unspecified" */ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; va_list ap; @@ -1391,7 +1391,7 @@ xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) switch (arg_type) { case CGEN_CPU_OPEN_ISAS : - isas = va_arg (ap, unsigned int); + isas = va_arg (ap, CGEN_BITSET *); break; case CGEN_CPU_OPEN_MACHS : machs = va_arg (ap, unsigned int); @@ -1422,9 +1422,6 @@ xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) machs = (1 << MAX_MACHS) - 1; /* Base mach is always selected. */ machs |= 1; - /* ISA unspecified means "all". */ - if (isas == 0) - isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) { /* ??? If target has only one, could have a default. */ @@ -1432,7 +1429,7 @@ xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) abort (); } - cd->isas = isas; + cd->isas = cgen_bitset_copy (isas); cd->machs = machs; cd->endian = endian; /* FIXME: for the sparc case we can determine insn-endianness statically. diff --git a/opcodes/xstormy16-desc.h b/opcodes/xstormy16-desc.h index 823a03ba3c1..4614fa5eb52 100644 --- a/opcodes/xstormy16-desc.h +++ b/opcodes/xstormy16-desc.h @@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc., #ifndef XSTORMY16_CPU_H #define XSTORMY16_CPU_H +#include "opcode/cgen-bitset.h" + #define CGEN_ARCH xstormy16 /* Given symbol S, return xstormy16_cgen_<S>. */ @@ -184,6 +186,15 @@ typedef enum cgen_ifld_attr { /* Number of non-boolean elements in cgen_ifld_attr. */ #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) + /* Enum declaration for xstormy16 ifield types. */ typedef enum ifield_type { XSTORMY16_F_NIL, XSTORMY16_F_ANYOF, XSTORMY16_F_RD, XSTORMY16_F_RDM @@ -211,6 +222,13 @@ typedef enum cgen_hw_attr { /* Number of non-boolean elements in cgen_hw_attr. */ #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) + /* Enum declaration for xstormy16 hardware types. */ typedef enum cgen_hw_type { HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR @@ -234,6 +252,17 @@ typedef enum cgen_operand_attr { /* Number of non-boolean elements in cgen_operand_attr. */ #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) + /* Enum declaration for xstormy16 operand types. */ typedef enum cgen_operand_type { XSTORMY16_OPERAND_PC, XSTORMY16_OPERAND_PSW_Z8, XSTORMY16_OPERAND_PSW_Z16, XSTORMY16_OPERAND_PSW_CY @@ -267,6 +296,19 @@ typedef enum cgen_insn_attr { /* Number of non-boolean elements in cgen_insn_attr. */ #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) + /* cgen.h uses things we just defined. */ #include "opcode/cgen.h" diff --git a/opcodes/xstormy16-dis.c b/opcodes/xstormy16-dis.c index 91cde6be6a9..aaff53f863d 100644 --- a/opcodes/xstormy16-dis.c +++ b/opcodes/xstormy16-dis.c @@ -4,7 +4,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-dis.in isn't - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -476,7 +476,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) typedef struct cpu_desc_list { struct cpu_desc_list *next; - int isa; + CGEN_BITSET *isa; int mach; int endian; CGEN_CPU_DESC cd; @@ -488,11 +488,12 @@ print_insn_xstormy16 (bfd_vma pc, disassemble_info *info) static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; static CGEN_CPU_DESC cd = 0; - static int prev_isa; + static CGEN_BITSET *prev_isa; static int prev_mach; static int prev_endian; int length; - int isa,mach; + CGEN_BITSET *isa; + int mach; int endian = (info->endian == BFD_ENDIAN_BIG ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); @@ -515,25 +516,34 @@ print_insn_xstormy16 (bfd_vma pc, disassemble_info *info) #endif #ifdef CGEN_COMPUTE_ISA - isa = CGEN_COMPUTE_ISA (info); + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } #else isa = info->insn_sets; #endif /* If we've switched cpu's, try to find a handle we've used before */ if (cd - && (isa != prev_isa + && (cgen_bitset_compare (isa, prev_isa) != 0 || mach != prev_mach || endian != prev_endian)) { cd = 0; for (cl = cd_list; cl; cl = cl->next) { - if (cl->isa == isa && + if (cgen_bitset_compare (cl->isa, isa) == 0 && cl->mach == mach && cl->endian == endian) { cd = cl->cd; + prev_isa = cd->isas; break; } } @@ -549,7 +559,7 @@ print_insn_xstormy16 (bfd_vma pc, disassemble_info *info) abort (); mach_name = arch_type->printable_name; - prev_isa = isa; + prev_isa = cgen_bitset_copy (isa); prev_mach = mach; prev_endian = endian; cd = xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, @@ -562,7 +572,7 @@ print_insn_xstormy16 (bfd_vma pc, disassemble_info *info) /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; - cl->isa = isa; + cl->isa = prev_isa; cl->mach = mach; cl->endian = endian; cl->next = cd_list; diff --git a/opcodes/xstormy16-opc.c b/opcodes/xstormy16-opc.c index 8237472f3aa..14823ee7ca1 100644 --- a/opcodes/xstormy16-opc.c +++ b/opcodes/xstormy16-opc.c @@ -1010,27 +1010,27 @@ static const CGEN_IBASE xstormy16_cgen_macro_insn_table[] = /* mov Rx,#$imm8 */ { -1, "movimm8", "mov", 16, - { 0|A(ALIAS), { (1<<MACH_BASE) } } + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } }, /* mov $Rm,#$imm8small */ { -1, "movgrimm8", "mov", 16, - { 0|A(ALIAS), { (1<<MACH_BASE) } } + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } }, /* mov $Rd,#$imm16 */ { -1, "movgrimm16", "mov", 32, - { 0|A(ALIAS), { (1<<MACH_BASE) } } + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } }, /* inc $Rd */ { -1, "incgr", "inc", 16, - { 0|A(ALIAS), { (1<<MACH_BASE) } } + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } }, /* dec $Rd */ { -1, "decgr", "dec", 16, - { 0|A(ALIAS), { (1<<MACH_BASE) } } + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } }, }; |