diff options
| -rw-r--r-- | gas/testsuite/gas/ppc/ppc.exp | 1 | ||||
| -rw-r--r-- | gas/testsuite/gas/ppc/svindex.d | 16 | ||||
| -rw-r--r-- | gas/testsuite/gas/ppc/svindex.s | 8 | ||||
| -rw-r--r-- | opcodes/ppc-opc.c | 15 |
4 files changed, 40 insertions, 0 deletions
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp index 9f02fa75c21..53c2d0dc328 100644 --- a/gas/testsuite/gas/ppc/ppc.exp +++ b/gas/testsuite/gas/ppc/ppc.exp @@ -159,3 +159,4 @@ run_dump_test "setvl" run_dump_test "svstep" run_dump_test "svshape" run_dump_test "svremap" +run_dump_test "svindex" diff --git a/gas/testsuite/gas/ppc/svindex.d b/gas/testsuite/gas/ppc/svindex.d new file mode 100644 index 00000000000..f573b854d89 --- /dev/null +++ b/gas/testsuite/gas/ppc/svindex.d @@ -0,0 +1,16 @@ +#as: -mlibresoc +#objdump: -dr -Mlibresoc + +.*: file format .* + + +Disassembly of section \.text: +0+ <\.text>: +.*: (29 00 00 58|58 00 00 29) svindex 0,0,1,0,0,0,0 +.*: (29 00 e0 5b|5b e0 00 29) svindex 31,0,1,0,0,0,0 +.*: (29 00 1f 58|58 1f 00 29) svindex 0,31,1,0,0,0,0 +.*: (29 f8 00 58|58 00 f8 29) svindex 0,0,32,0,0,0,0 +.*: (29 06 00 58|58 00 06 29) svindex 0,0,1,3,0,0,0 +.*: (29 01 00 58|58 00 01 29) svindex 0,0,1,0,1,0,0 +.*: (a9 00 00 58|58 00 00 a9) svindex 0,0,1,0,0,1,0 +.*: (69 00 00 58|58 00 00 69) svindex 0,0,1,0,0,0,1 diff --git a/gas/testsuite/gas/ppc/svindex.s b/gas/testsuite/gas/ppc/svindex.s new file mode 100644 index 00000000000..ab256c433b2 --- /dev/null +++ b/gas/testsuite/gas/ppc/svindex.s @@ -0,0 +1,8 @@ +svindex 0,0,1,0,0,0,0 +svindex 31,0,1,0,0,0,0 +svindex 0,31,1,0,0,0,0 +svindex 0,0,32,0,0,0,0 +svindex 0,0,1,3,0,0,0 +svindex 0,0,1,0,1,0,0 +svindex 0,0,1,0,0,1,0 +svindex 0,0,1,0,0,0,1 diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index af67d6dce82..934b1bf4e85 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -3509,6 +3509,7 @@ const struct powerpc_operand powerpc_operands[] = #define TO TBR + 1 #define DUI TO #define SVme TO +#define SVG TO #define TO_MASK (0x1f << 21) { 0x1f, 21, NULL, NULL, 0 }, @@ -3556,6 +3557,7 @@ const struct powerpc_operand powerpc_operands[] = /* The UIMM field in a VX form instruction. */ #define UIMM SIMM + 1 #define DCTL UIMM +#define rmm UIMM { 0x1f, 16, NULL, NULL, 0 }, /* The 3-bit UIMM field in a VX form instruction. */ @@ -3648,6 +3650,7 @@ const struct powerpc_operand powerpc_operands[] = /* The RMC or CY field in a Z23 form instruction. */ #define RMC A_L + 1 #define CY RMC +#define ew RMC { 0x3, 9, NULL, NULL, 0 }, #define R RMC + 1 @@ -3836,12 +3839,15 @@ const struct powerpc_operand powerpc_operands[] = { 0x3f, 9, NULL, NULL, PPC_OPERAND_NONZERO }, #define vf SVi + 1 +#define sk vf { 0x1, 6, NULL, NULL, 0 }, #define vs vf + 1 +#define mm vs { 0x1, 7, NULL, NULL, 0 }, #define ms vs + 1 +#define yx ms { 0x1, 8, NULL, NULL, 0 }, #define SVLcr ms + 1 @@ -3854,6 +3860,7 @@ const struct powerpc_operand powerpc_operands[] = { 0x1f, 16, NULL, NULL, PPC_OPERAND_NONZERO }, #define SVzd SVyd + 1 +#define SVd SVzd { 0x1f, 11, NULL, NULL, PPC_OPERAND_NONZERO }, #define SVrm SVzd + 1 @@ -4758,6 +4765,12 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) | (((uint64_t)(xop)) & 0x3f)) #define SVRM_MASK SVRM (0x3f, 0x3f) +/* An SVI form instruction. */ +#define SVI(op, xop) \ + (OP (op) \ + | (((uint64_t)(xop)) & 0x3f)) +#define SVI_MASK SVI (0x3f, 0x3f) + /* The BO encodings used in extended conditional branch mnemonics. */ #define BODNZF (0x0) #define BODNZFP (0x1) @@ -6835,6 +6848,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}}, {"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}}, +{"svindex", SVI(22,41), SVI_MASK, SVP64, PPCVLE, {SVG, rmm, SVd, ew, yx, mm, sk}}, + {"svremap", SVRM(22,57), SVRM_MASK, SVP64, PPCVLE, {SVme, mi0, mi1, mi2, mo0, mo1, pst}}, {"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RB}}, |