diff options
| -rw-r--r-- | bfd/elfxx-riscv.c | 4 | ||||
| -rw-r--r-- | gas/doc/c-riscv.texi | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/x-ventana-condops.d | 12 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/x-ventana-condops.s | 4 | ||||
| -rw-r--r-- | include/opcode/riscv-opc.h | 8 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 1 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 4 |
7 files changed, 39 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 19391d94e30..bd0c7c81329 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1255,6 +1255,8 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadmemidx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadmempair", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + /* XVentanaCondOps: https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf */ + {"xventanacondops", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -2383,6 +2385,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xtheadmempair"); case INSN_CLASS_XTHEADSYNC: return riscv_subset_supports (rps, "xtheadsync"); + case INSN_CLASS_XVENTANACONDOPS: + return riscv_subset_supports (rps, "xventanacondops"); default: rps->error_handler (_("internal: unreachable INSN_CLASS_*")); diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index 64fff6a7973..98d5d1bed44 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -763,5 +763,11 @@ It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/rel The XTheadSync extension provides instructions for multi-processor synchronization. It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. +@item XVentanaCondOps +XVentanaCondOps extension provides instructions for branchless +sequences that perform conditional arithmetic, conditional +bitwise-logic, and conditional select operations. + +It is documented at @url{https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf}. @end table diff --git a/gas/testsuite/gas/riscv/x-ventana-condops.d b/gas/testsuite/gas/riscv/x-ventana-condops.d new file mode 100644 index 00000000000..cab0cc8dc12 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-ventana-condops.d @@ -0,0 +1,12 @@ +#as: -march=rv64i_xventanacondops1p0 +#source: x-ventana-condops.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+0:[ ]+00c5e57b[ ]+vt.maskc[ ]+a0,a1,a2 +[ ]+4:[ ]+00e6f57b[ ]+vt.maskcn[ ]+a0,a3,a4 diff --git a/gas/testsuite/gas/riscv/x-ventana-condops.s b/gas/testsuite/gas/riscv/x-ventana-condops.s new file mode 100644 index 00000000000..562cf7384f7 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-ventana-condops.s @@ -0,0 +1,4 @@ +target: + vt.maskc a0, a1, a2 + vt.maskcn a0, a3, a4 + diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 85d35c1efc9..91e56c03191 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2342,6 +2342,11 @@ #define MASK_TH_SYNC_IS 0xffffffff #define MATCH_TH_SYNC_S 0x0190000b #define MASK_TH_SYNC_S 0xffffffff +/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ +#define MATCH_VT_MASKC 0x607b +#define MASK_VT_MASKC 0xfe00707f +#define MATCH_VT_MASKCN 0x707b +#define MASK_VT_MASKCN 0xfe00707f /* Unprivileged Counter/Timers CSR addresses. */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 @@ -3236,6 +3241,9 @@ DECLARE_INSN(th_sync, MATCH_TH_SYNC, MASK_TH_SYNC) DECLARE_INSN(th_sync_i, MATCH_TH_SYNC_I, MASK_TH_SYNC_I) DECLARE_INSN(th_sync_is, MATCH_TH_SYNC_IS, MASK_TH_SYNC_IS) DECLARE_INSN(th_sync_s, MATCH_TH_SYNC_S, MASK_TH_SYNC_S) +/* XVentanaCondOps instructions. */ +DECLARE_INSN(vt_maskc, MATCH_VT_MASKC, MASK_VT_MASKC) +DECLARE_INSN(vt_maskcn, MATCH_VT_MASKCN, MASK_VT_MASKCN) #endif /* DECLARE_INSN */ #ifdef DECLARE_CSR /* Unprivileged Counter/Timers CSRs. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index b4ae55249bb..e86a1bd0824 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -422,6 +422,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADMEMIDX, INSN_CLASS_XTHEADMEMPAIR, INSN_CLASS_XTHEADSYNC, + INSN_CLASS_XVENTANACONDOPS, }; /* This structure holds information for a particular instruction. */ diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index d9d69cda548..1c3d9b0903e 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2009,6 +2009,10 @@ const struct riscv_opcode riscv_opcodes[] = {"th.sync.is", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_IS, MASK_TH_SYNC_IS, match_opcode, 0}, {"th.sync.s", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_S, MASK_TH_SYNC_S, match_opcode, 0}, +/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ +{"vt.maskc", 0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 }, +{"vt.maskcn", 0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 }, + /* Terminate the list. */ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0} }; |