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| author | Alexandre Oliva <aoliva@redhat.com> | 2004-06-28 19:26:37 +0000 |
|---|---|---|
| committer | Alexandre Oliva <aoliva@redhat.com> | 2004-06-28 19:26:37 +0000 |
| commit | e073c4747aebd9b65de341f6201fa479e57ea275 (patch) | |
| tree | ba3aba60d3e4be6b3323c884c4c2143668fb1c24 /sim/testsuite | |
| parent | e4d3c499f58baf4d71323d262f0e122c8a1baf9c (diff) | |
| download | binutils-gdb-e073c4747aebd9b65de341f6201fa479e57ea275.tar.gz | |
sim/h8300/ChangeLog:
2003-07-23 Richard Sandiford <rsandifo@redhat.com>
* compile.c (sim_resume): Make sure that dst.reg refers to the
right register byte in mova/sz.l @(dd,RnL),ERn.
2003-07-21 Richard Sandiford <rsandifo@redhat.com>
* compile.c (sim_resume): Zero-extend immediate to muls, mulsu,
mulxs, divs and divxs.
sim/testsuite/sim/h8300/ChangeLog:
2003-07-22 Michael Snyder <msnyder@redhat.com>
* mul.s: Don't try to use negative immediate (it's always
unsigned).
* div.s: Ditto.
Diffstat (limited to 'sim/testsuite')
| -rw-r--r-- | sim/testsuite/sim/h8300/ChangeLog | 7 | ||||
| -rw-r--r-- | sim/testsuite/sim/h8300/div.s | 12 | ||||
| -rw-r--r-- | sim/testsuite/sim/h8300/mul.s | 16 |
3 files changed, 21 insertions, 14 deletions
diff --git a/sim/testsuite/sim/h8300/ChangeLog b/sim/testsuite/sim/h8300/ChangeLog index a90793a9ee2..21c02663820 100644 --- a/sim/testsuite/sim/h8300/ChangeLog +++ b/sim/testsuite/sim/h8300/ChangeLog @@ -1,3 +1,10 @@ +2004-06-28 Alexandre Oliva <aoliva@redhat.com> + + 2003-07-22 Michael Snyder <msnyder@redhat.com> + * mul.s: Don't try to use negative immediate (it's always + unsigned). + * div.s: Ditto. + 2004-06-24 Alexandre Oliva <aoliva@redhat.com> 2004-06-17 Alexandre Oliva <aoliva@redhat.com> diff --git a/sim/testsuite/sim/h8300/div.s b/sim/testsuite/sim/h8300/div.s index 518b62f9523..fd53bafa62c 100644 --- a/sim/testsuite/sim/h8300/div.s +++ b/sim/testsuite/sim/h8300/div.s @@ -41,9 +41,9 @@ divs_w_imm4_reg: set_grs_a5a5 ;; divs.w xx:4, rd - mov.w #32, r1 + mov.w #-32, r1 set_ccr_zero - divs.w #-2:4, r1 + divs.w #2:4, r1 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 test_neg_set @@ -88,9 +88,9 @@ divs_l_imm4_reg: set_grs_a5a5 ;; divs.l xx:4, rd - mov.l #320000, er1 + mov.l #-320000, er1 set_ccr_zero - divs.l #-2:4, er1 + divs.l #2:4, er1 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 test_neg_set @@ -221,9 +221,9 @@ divxs_b_imm4_reg: set_grs_a5a5 ;; divxs.b xx:4, rd - mov.w #32, r1 + mov.w #-32, r1 set_ccr_zero - divxs.b #-2:4, r1 + divxs.b #2:4, r1 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 test_neg_set diff --git a/sim/testsuite/sim/h8300/mul.s b/sim/testsuite/sim/h8300/mul.s index 70ab7ec1208..02b9e9f846d 100644 --- a/sim/testsuite/sim/h8300/mul.s +++ b/sim/testsuite/sim/h8300/mul.s @@ -41,9 +41,9 @@ muls_w_imm4_reg: set_grs_a5a5 ;; muls.w xx:4, rd - mov.w #32, r1 + mov.w #-32, r1 set_ccr_zero - muls.w #-2:4, r1 + muls.w #2:4, r1 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 test_neg_set @@ -88,9 +88,9 @@ muls_l_imm4_reg: set_grs_a5a5 ;; muls.l xx:4, rd - mov.l #320000, er1 + mov.l #-320000, er1 set_ccr_zero - muls.l #-2:4, er1 + muls.l #2:4, er1 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 test_neg_set @@ -308,9 +308,9 @@ mulxs_b_imm4_reg: set_grs_a5a5 ;; mulxs.b xx:4, rd - mov.w #32, r1 + mov.w #-32, r1 set_ccr_zero - mulxs.b #-2:4, r1 + mulxs.b #2:4, r1 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 test_neg_set @@ -408,9 +408,9 @@ mulxu_b_imm4_reg: set_grs_a5a5 ;; mulxu.b xx:4, rd - mov.b #32, r1l + mov.b #-32, r1l set_ccr_zero - mulxu.b #-2:4, r1 + mulxu.b #2:4, r1 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 test_cc_clear |