diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2022-12-10 06:33:58 -0500 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2022-12-20 21:06:32 -0500 |
| commit | d026e67ed41a249ec758847008d8a19257bf45fc (patch) | |
| tree | cc49e25810d2453ed8ed389f9e79eff4be34eb59 /sim/riscv | |
| parent | 897903a2104878d541a6370b12644ec34afb389b (diff) | |
| download | binutils-gdb-d026e67ed41a249ec758847008d8a19257bf45fc.tar.gz | |
sim: move register headers into sim/ namespace [PR sim/29869]
These headers define the register numbers for each port to implement
the sim_fetch_register & sim_store_register interfaces. While gdb
uses these, the APIs are part of the sim, not gdb. Move the headers
out of the gdb/ include namespace and into sim/ instead.
Diffstat (limited to 'sim/riscv')
| -rw-r--r-- | sim/riscv/sim-main.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index 6f253d58beb..b8771e66e67 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -33,7 +33,7 @@ #include "opcode/riscv.h" -#include "gdb/sim-riscv.h" +#include "sim/sim-riscv.h" #define TRACE_REG(cpu, reg) \ TRACE_REGISTER (cpu, "wrote %s = %#" PRIxTW, riscv_gpr_names_abi[reg], \ |