* arch.c: Regenerate.

	* arch.h: Regenerate.
	* cpu.c: Regenerate.
	* cpu.h: Regenerate.
	* cpu2.c: Regenerate.
	* cpu2.h: Regenerate.
	* cpuall.h: Regenerate.
	* cpux.c: Regenerate.
	* cpux.h: Regenerate.
	* decode.c: Regenerate.
	* decode.h: Regenerate.
	* decode2.c: Regenerate.
	* decode2.h: Regenerate.
	* decodex.c: Regenerate.
	* decodex.h: Regenerate.
	* model.c: Regenerate.
	* model2.c: Regenerate.
	* modelx.c: Regenerate.
	* sem-switch.c: Regenerate.
	* sem.c: Regenerate.
	* sem2-switch.c: Regenerate.
	* semx-switch.c: Regenerate.

23 files changed, 866 insertions, 443 deletions

diff --git a/sim/m32r/ChangeLog b/sim/m32r/ChangeLog
index 3dd0c583b3b..7211f8e35e3 100644
--- a/sim/m32r/ChangeLog
+++ b/sim/m32r/ChangeLog
@@ -1,5 +1,28 @@
 2009-11-03  Doug Evans  <dje@sebabeach.org>
 
+	* arch.c: Regenerate.
+	* arch.h: Regenerate.
+	* cpu.c: Regenerate.
+	* cpu.h: Regenerate.
+	* cpu2.c: Regenerate.
+	* cpu2.h: Regenerate.
+	* cpuall.h: Regenerate.
+	* cpux.c: Regenerate.
+	* cpux.h: Regenerate.
+	* decode.c: Regenerate.
+	* decode.h: Regenerate.
+	* decode2.c: Regenerate.
+	* decode2.h: Regenerate.
+	* decodex.c: Regenerate.
+	* decodex.h: Regenerate.
+	* model.c: Regenerate.
+	* model2.c: Regenerate.
+	* modelx.c: Regenerate.
+	* sem-switch.c: Regenerate.
+	* sem.c: Regenerate.
+	* sem2-switch.c: Regenerate.
+	* semx-switch.c: Regenerate.
+
 	* Makefile.in (mloop.c): Add @true to rule.
 	(mloopx.c, mloop2.c): Ditto.
 	(stamp-*): Add Makefile dependency.
diff --git a/sim/m32r/arch.c b/sim/m32r/arch.c
index 383507e2c41..8ac835cf10d 100644
--- a/sim/m32r/arch.c
+++ b/sim/m32r/arch.c
@@ -2,22 +2,23 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
diff --git a/sim/m32r/arch.h b/sim/m32r/arch.h
index 6e427723430..96498ecb21c 100644
--- a/sim/m32r/arch.h
+++ b/sim/m32r/arch.h
@@ -2,22 +2,23 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
diff --git a/sim/m32r/cpu.c b/sim/m32r/cpu.c
index 966b96b0540..2c34793c869 100644
--- a/sim/m32r/cpu.c
+++ b/sim/m32r/cpu.c
@@ -2,22 +2,23 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
diff --git a/sim/m32r/cpu.h b/sim/m32r/cpu.h
index de7575bee6d..7f112d4d046 100644
--- a/sim/m32r/cpu.h
+++ b/sim/m32r/cpu.h
@@ -2,22 +2,23 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
diff --git a/sim/m32r/cpu2.c b/sim/m32r/cpu2.c
index 358a01b080e..7176e97efcf 100644
--- a/sim/m32r/cpu2.c
+++ b/sim/m32r/cpu2.c
@@ -2,22 +2,23 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
diff --git a/sim/m32r/cpu2.h b/sim/m32r/cpu2.h
index 10f06fc8bfa..58334e5ae3c 100644
--- a/sim/m32r/cpu2.h
+++ b/sim/m32r/cpu2.h
@@ -2,22 +2,23 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
@@ -949,24 +950,24 @@ struct parexec {
       USI h_memory_SI_src2_idx;
     } sfmt_st;
     struct { /* e.g. st $src1,@($slo16,$src2) */
-      SI h_memory_SI_add__DFLT_src2_slo16;
-      USI h_memory_SI_add__DFLT_src2_slo16_idx;
+      SI h_memory_SI_add__SI_src2_slo16;
+      USI h_memory_SI_add__SI_src2_slo16_idx;
     } sfmt_st_d;
     struct { /* e.g. stb $src1,@$src2 */
       QI h_memory_QI_src2;
       USI h_memory_QI_src2_idx;
     } sfmt_stb;
     struct { /* e.g. stb $src1,@($slo16,$src2) */
-      QI h_memory_QI_add__DFLT_src2_slo16;
-      USI h_memory_QI_add__DFLT_src2_slo16_idx;
+      QI h_memory_QI_add__SI_src2_slo16;
+      USI h_memory_QI_add__SI_src2_slo16_idx;
     } sfmt_stb_d;
     struct { /* e.g. sth $src1,@$src2 */
       HI h_memory_HI_src2;
       USI h_memory_HI_src2_idx;
     } sfmt_sth;
     struct { /* e.g. sth $src1,@($slo16,$src2) */
-      HI h_memory_HI_add__DFLT_src2_slo16;
-      USI h_memory_HI_add__DFLT_src2_slo16_idx;
+      HI h_memory_HI_add__SI_src2_slo16;
+      USI h_memory_HI_add__SI_src2_slo16_idx;
     } sfmt_sth_d;
     struct { /* e.g. st $src1,@+$src2 */
       SI h_memory_SI_new_src2;
@@ -989,7 +990,7 @@ struct parexec {
       USI h_cr_USI_14;
       USI h_cr_USI_6;
       UQI h_psw_UQI;
-      SI pc;
+      USI pc;
     } sfmt_trap;
     struct { /* e.g. unlock $src1,@$src2 */
       BI h_lock_BI;
@@ -1024,8 +1025,8 @@ struct parexec {
       USI h_cr_USI_0;
     } sfmt_setpsw;
     struct { /* e.g. bset $uimm3,@($slo16,$sr) */
-      QI h_memory_QI_add__DFLT_sr_slo16;
-      USI h_memory_QI_add__DFLT_sr_slo16_idx;
+      QI h_memory_QI_add__SI_sr_slo16;
+      USI h_memory_QI_add__SI_sr_slo16_idx;
     } sfmt_bset;
     struct { /* e.g. btst $uimm3,$sr */
       BI condbit;
diff --git a/sim/m32r/cpuall.h b/sim/m32r/cpuall.h
index 5ba3374ad9e..36e128beb7a 100644
--- a/sim/m32r/cpuall.h
+++ b/sim/m32r/cpuall.h
@@ -2,22 +2,23 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
diff --git a/sim/m32r/cpux.c b/sim/m32r/cpux.c
index a6326a03c7e..73f29af4c42 100644
--- a/sim/m32r/cpux.c
+++ b/sim/m32r/cpux.c
@@ -2,22 +2,23 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
diff --git a/sim/m32r/cpux.h b/sim/m32r/cpux.h
index 70dc20d92e9..784536efd17 100644
--- a/sim/m32r/cpux.h
+++ b/sim/m32r/cpux.h
@@ -2,22 +2,23 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
@@ -949,24 +950,24 @@ struct parexec {
       USI h_memory_SI_src2_idx;
     } sfmt_st;
     struct { /* e.g. st $src1,@($slo16,$src2) */
-      SI h_memory_SI_add__DFLT_src2_slo16;
-      USI h_memory_SI_add__DFLT_src2_slo16_idx;
+      SI h_memory_SI_add__SI_src2_slo16;
+      USI h_memory_SI_add__SI_src2_slo16_idx;
     } sfmt_st_d;
     struct { /* e.g. stb $src1,@$src2 */
       QI h_memory_QI_src2;
       USI h_memory_QI_src2_idx;
     } sfmt_stb;
     struct { /* e.g. stb $src1,@($slo16,$src2) */
-      QI h_memory_QI_add__DFLT_src2_slo16;
-      USI h_memory_QI_add__DFLT_src2_slo16_idx;
+      QI h_memory_QI_add__SI_src2_slo16;
+      USI h_memory_QI_add__SI_src2_slo16_idx;
     } sfmt_stb_d;
     struct { /* e.g. sth $src1,@$src2 */
       HI h_memory_HI_src2;
       USI h_memory_HI_src2_idx;
     } sfmt_sth;
     struct { /* e.g. sth $src1,@($slo16,$src2) */
-      HI h_memory_HI_add__DFLT_src2_slo16;
-      USI h_memory_HI_add__DFLT_src2_slo16_idx;
+      HI h_memory_HI_add__SI_src2_slo16;
+      USI h_memory_HI_add__SI_src2_slo16_idx;
     } sfmt_sth_d;
     struct { /* e.g. st $src1,@+$src2 */
       SI h_memory_SI_new_src2;
@@ -989,7 +990,7 @@ struct parexec {
       USI h_cr_USI_14;
       USI h_cr_USI_6;
       UQI h_psw_UQI;
-      SI pc;
+      USI pc;
     } sfmt_trap;
     struct { /* e.g. unlock $src1,@$src2 */
       BI h_lock_BI;
@@ -1024,8 +1025,8 @@ struct parexec {
       USI h_cr_USI_0;
     } sfmt_setpsw;
     struct { /* e.g. bset $uimm3,@($slo16,$sr) */
-      QI h_memory_QI_add__DFLT_sr_slo16;
-      USI h_memory_QI_add__DFLT_sr_slo16_idx;
+      QI h_memory_QI_add__SI_sr_slo16;
+      USI h_memory_QI_add__SI_sr_slo16_idx;
     } sfmt_bset;
     struct { /* e.g. btst $uimm3,$sr */
       BI condbit;
diff --git a/sim/m32r/decode.c b/sim/m32r/decode.c
index 3fdea46518f..e94ff361ee1 100644
--- a/sim/m32r/decode.c
+++ b/sim/m32r/decode.c
@@ -2,22 +2,23 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
@@ -241,7 +242,10 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 12 : itype = M32RBF_INSN_AND; goto extract_sfmt_add;
       case 13 : itype = M32RBF_INSN_XOR; goto extract_sfmt_add;
       case 14 : itype = M32RBF_INSN_OR; goto extract_sfmt_add;
-      case 15 : itype = M32RBF_INSN_BTST; goto extract_sfmt_btst;
+      case 15 :
+        if ((entire_insn & 0xf8f0) == 0xf0)
+          { itype = M32RBF_INSN_BTST; goto extract_sfmt_btst; }
+        itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 16 : itype = M32RBF_INSN_SRL; goto extract_sfmt_add;
       case 18 : itype = M32RBF_INSN_SRA; goto extract_sfmt_add;
       case 20 : itype = M32RBF_INSN_SLL; goto extract_sfmt_add;
@@ -254,13 +258,25 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 8) & (1 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RBF_INSN_JL; goto extract_sfmt_jl;
-          case 1 : itype = M32RBF_INSN_JMP; goto extract_sfmt_jmp;
+          case 0 :
+            if ((entire_insn & 0xfff0) == 0x1ec0)
+              { itype = M32RBF_INSN_JL; goto extract_sfmt_jl; }
+            itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0xfff0) == 0x1fc0)
+              { itype = M32RBF_INSN_JMP; goto extract_sfmt_jmp; }
+            itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 29 : itype = M32RBF_INSN_RTE; goto extract_sfmt_rte;
-      case 31 : itype = M32RBF_INSN_TRAP; goto extract_sfmt_trap;
+      case 29 :
+        if ((entire_insn & 0xffff) == 0x10d6)
+          { itype = M32RBF_INSN_RTE; goto extract_sfmt_rte; }
+        itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 31 :
+        if ((entire_insn & 0xfff0) == 0x10f0)
+          { itype = M32RBF_INSN_TRAP; goto extract_sfmt_trap; }
+        itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 32 : itype = M32RBF_INSN_STB; goto extract_sfmt_stb;
       case 34 : itype = M32RBF_INSN_STH; goto extract_sfmt_sth;
       case 36 : itype = M32RBF_INSN_ST; goto extract_sfmt_st;
@@ -309,21 +325,42 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 0) & (1 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RBF_INSN_MVTACHI; goto extract_sfmt_mvtachi;
-          case 1 : itype = M32RBF_INSN_MVTACLO; goto extract_sfmt_mvtachi;
+          case 0 :
+            if ((entire_insn & 0xf0ff) == 0x5070)
+              { itype = M32RBF_INSN_MVTACHI; goto extract_sfmt_mvtachi; }
+            itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0xf0ff) == 0x5071)
+              { itype = M32RBF_INSN_MVTACLO; goto extract_sfmt_mvtachi; }
+            itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 88 : itype = M32RBF_INSN_RACH; goto extract_sfmt_rac;
-      case 89 : itype = M32RBF_INSN_RAC; goto extract_sfmt_rac;
+      case 88 :
+        if ((entire_insn & 0xffff) == 0x5080)
+          { itype = M32RBF_INSN_RACH; goto extract_sfmt_rac; }
+        itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 89 :
+        if ((entire_insn & 0xffff) == 0x5090)
+          { itype = M32RBF_INSN_RAC; goto extract_sfmt_rac; }
+        itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 95 :
         {
           unsigned int val = (((insn >> 0) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RBF_INSN_MVFACHI; goto extract_sfmt_mvfachi;
-          case 1 : itype = M32RBF_INSN_MVFACLO; goto extract_sfmt_mvfachi;
-          case 2 : itype = M32RBF_INSN_MVFACMI; goto extract_sfmt_mvfachi;
+          case 0 :
+            if ((entire_insn & 0xf0ff) == 0x50f0)
+              { itype = M32RBF_INSN_MVFACHI; goto extract_sfmt_mvfachi; }
+            itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0xf0ff) == 0x50f1)
+              { itype = M32RBF_INSN_MVFACLO; goto extract_sfmt_mvfachi; }
+            itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0xf0ff) == 0x50f2)
+              { itype = M32RBF_INSN_MVFACMI; goto extract_sfmt_mvfachi; }
+            itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -348,7 +385,10 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 8) & (15 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RBF_INSN_NOP; goto extract_sfmt_nop;
+          case 0 :
+            if ((entire_insn & 0xffff) == 0x7000)
+              { itype = M32RBF_INSN_NOP; goto extract_sfmt_nop; }
+            itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
           case 1 : itype = M32RBF_INSN_SETPSW; goto extract_sfmt_setpsw;
           case 2 : itype = M32RBF_INSN_CLRPSW; goto extract_sfmt_clrpsw;
           case 12 : itype = M32RBF_INSN_BC8; goto extract_sfmt_bc8;
@@ -386,26 +426,53 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
           default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 132 : itype = M32RBF_INSN_CMPI; goto extract_sfmt_cmpi;
-      case 133 : itype = M32RBF_INSN_CMPUI; goto extract_sfmt_cmpi;
+      case 132 :
+        if ((entire_insn & 0xfff00000) == 0x80400000)
+          { itype = M32RBF_INSN_CMPI; goto extract_sfmt_cmpi; }
+        itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 133 :
+        if ((entire_insn & 0xfff00000) == 0x80500000)
+          { itype = M32RBF_INSN_CMPUI; goto extract_sfmt_cmpi; }
+        itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 136 : itype = M32RBF_INSN_ADDV3; goto extract_sfmt_addv3;
       case 138 : itype = M32RBF_INSN_ADD3; goto extract_sfmt_add3;
       case 140 : itype = M32RBF_INSN_AND3; goto extract_sfmt_and3;
       case 141 : itype = M32RBF_INSN_XOR3; goto extract_sfmt_and3;
       case 142 : itype = M32RBF_INSN_OR3; goto extract_sfmt_or3;
-      case 144 : itype = M32RBF_INSN_DIV; goto extract_sfmt_div;
-      case 145 : itype = M32RBF_INSN_DIVU; goto extract_sfmt_div;
-      case 146 : itype = M32RBF_INSN_REM; goto extract_sfmt_div;
-      case 147 : itype = M32RBF_INSN_REMU; goto extract_sfmt_div;
+      case 144 :
+        if ((entire_insn & 0xf0f0ffff) == 0x90000000)
+          { itype = M32RBF_INSN_DIV; goto extract_sfmt_div; }
+        itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 145 :
+        if ((entire_insn & 0xf0f0ffff) == 0x90100000)
+          { itype = M32RBF_INSN_DIVU; goto extract_sfmt_div; }
+        itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 146 :
+        if ((entire_insn & 0xf0f0ffff) == 0x90200000)
+          { itype = M32RBF_INSN_REM; goto extract_sfmt_div; }
+        itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 147 :
+        if ((entire_insn & 0xf0f0ffff) == 0x90300000)
+          { itype = M32RBF_INSN_REMU; goto extract_sfmt_div; }
+        itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 152 : itype = M32RBF_INSN_SRL3; goto extract_sfmt_sll3;
       case 154 : itype = M32RBF_INSN_SRA3; goto extract_sfmt_sll3;
       case 156 : itype = M32RBF_INSN_SLL3; goto extract_sfmt_sll3;
-      case 159 : itype = M32RBF_INSN_LDI16; goto extract_sfmt_ldi16;
+      case 159 :
+        if ((entire_insn & 0xf0ff0000) == 0x90f00000)
+          { itype = M32RBF_INSN_LDI16; goto extract_sfmt_ldi16; }
+        itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 160 : itype = M32RBF_INSN_STB_D; goto extract_sfmt_stb_d;
       case 162 : itype = M32RBF_INSN_STH_D; goto extract_sfmt_sth_d;
       case 164 : itype = M32RBF_INSN_ST_D; goto extract_sfmt_st_d;
-      case 166 : itype = M32RBF_INSN_BSET; goto extract_sfmt_bset;
-      case 167 : itype = M32RBF_INSN_BCLR; goto extract_sfmt_bset;
+      case 166 :
+        if ((entire_insn & 0xf8f00000) == 0xa0600000)
+          { itype = M32RBF_INSN_BSET; goto extract_sfmt_bset; }
+        itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 167 :
+        if ((entire_insn & 0xf8f00000) == 0xa0700000)
+          { itype = M32RBF_INSN_BCLR; goto extract_sfmt_bset; }
+        itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 168 : itype = M32RBF_INSN_LDB_D; goto extract_sfmt_ldb_d;
       case 169 : itype = M32RBF_INSN_LDUB_D; goto extract_sfmt_ldb_d;
       case 170 : itype = M32RBF_INSN_LDH_D; goto extract_sfmt_ldh_d;
@@ -413,13 +480,34 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 172 : itype = M32RBF_INSN_LD_D; goto extract_sfmt_ld_d;
       case 176 : itype = M32RBF_INSN_BEQ; goto extract_sfmt_beq;
       case 177 : itype = M32RBF_INSN_BNE; goto extract_sfmt_beq;
-      case 184 : itype = M32RBF_INSN_BEQZ; goto extract_sfmt_beqz;
-      case 185 : itype = M32RBF_INSN_BNEZ; goto extract_sfmt_beqz;
-      case 186 : itype = M32RBF_INSN_BLTZ; goto extract_sfmt_beqz;
-      case 187 : itype = M32RBF_INSN_BGEZ; goto extract_sfmt_beqz;
-      case 188 : itype = M32RBF_INSN_BLEZ; goto extract_sfmt_beqz;
-      case 189 : itype = M32RBF_INSN_BGTZ; goto extract_sfmt_beqz;
-      case 220 : itype = M32RBF_INSN_SETH; goto extract_sfmt_seth;
+      case 184 :
+        if ((entire_insn & 0xfff00000) == 0xb0800000)
+          { itype = M32RBF_INSN_BEQZ; goto extract_sfmt_beqz; }
+        itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 185 :
+        if ((entire_insn & 0xfff00000) == 0xb0900000)
+          { itype = M32RBF_INSN_BNEZ; goto extract_sfmt_beqz; }
+        itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 186 :
+        if ((entire_insn & 0xfff00000) == 0xb0a00000)
+          { itype = M32RBF_INSN_BLTZ; goto extract_sfmt_beqz; }
+        itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 187 :
+        if ((entire_insn & 0xfff00000) == 0xb0b00000)
+          { itype = M32RBF_INSN_BGEZ; goto extract_sfmt_beqz; }
+        itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 188 :
+        if ((entire_insn & 0xfff00000) == 0xb0c00000)
+          { itype = M32RBF_INSN_BLEZ; goto extract_sfmt_beqz; }
+        itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 189 :
+        if ((entire_insn & 0xfff00000) == 0xb0d00000)
+          { itype = M32RBF_INSN_BGTZ; goto extract_sfmt_beqz; }
+        itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 220 :
+        if ((entire_insn & 0xf0ff0000) == 0xd0c00000)
+          { itype = M32RBF_INSN_SETH; goto extract_sfmt_seth; }
+        itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 224 : /* fall through */
       case 225 : /* fall through */
       case 226 : /* fall through */
@@ -456,10 +544,22 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 8) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RBF_INSN_BC24; goto extract_sfmt_bc24;
-          case 1 : itype = M32RBF_INSN_BNC24; goto extract_sfmt_bc24;
-          case 2 : itype = M32RBF_INSN_BL24; goto extract_sfmt_bl24;
-          case 3 : itype = M32RBF_INSN_BRA24; goto extract_sfmt_bra24;
+          case 0 :
+            if ((entire_insn & 0xff000000) == 0xfc000000)
+              { itype = M32RBF_INSN_BC24; goto extract_sfmt_bc24; }
+            itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0xff000000) == 0xfd000000)
+              { itype = M32RBF_INSN_BNC24; goto extract_sfmt_bc24; }
+            itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0xff000000) == 0xfe000000)
+              { itype = M32RBF_INSN_BL24; goto extract_sfmt_bl24; }
+            itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0xff000000) == 0xff000000)
+              { itype = M32RBF_INSN_BRA24; goto extract_sfmt_bra24; }
+            itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
diff --git a/sim/m32r/decode.h b/sim/m32r/decode.h
index 3b095a74808..4930f34b53f 100644
--- a/sim/m32r/decode.h
+++ b/sim/m32r/decode.h
@@ -2,22 +2,23 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
diff --git a/sim/m32r/decode2.c b/sim/m32r/decode2.c
index 53e929d84e6..66ffa11e855 100644
--- a/sim/m32r/decode2.c
+++ b/sim/m32r/decode2.c
@@ -2,22 +2,23 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
@@ -283,8 +284,14 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 8) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = M32R2F_INSN_CMPZ; goto extract_sfmt_cmpz;
-          case 3 : itype = M32R2F_INSN_PCMPBZ; goto extract_sfmt_cmpz;
+          case 0 :
+            if ((entire_insn & 0xfff0) == 0x70)
+              { itype = M32R2F_INSN_CMPZ; goto extract_sfmt_cmpz; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0xfff0) == 0x370)
+              { itype = M32R2F_INSN_PCMPBZ; goto extract_sfmt_cmpz; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -295,7 +302,10 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
       case 12 : itype = M32R2F_INSN_AND; goto extract_sfmt_add;
       case 13 : itype = M32R2F_INSN_XOR; goto extract_sfmt_add;
       case 14 : itype = M32R2F_INSN_OR; goto extract_sfmt_add;
-      case 15 : itype = M32R2F_INSN_BTST; goto extract_sfmt_btst;
+      case 15 :
+        if ((entire_insn & 0xf8f0) == 0xf0)
+          { itype = M32R2F_INSN_BTST; goto extract_sfmt_btst; }
+        itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
       case 16 : itype = M32R2F_INSN_SRL; goto extract_sfmt_add;
       case 18 : itype = M32R2F_INSN_SRA; goto extract_sfmt_add;
       case 20 : itype = M32R2F_INSN_SLL; goto extract_sfmt_add;
@@ -308,15 +318,33 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 8) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = M32R2F_INSN_JC; goto extract_sfmt_jc;
-          case 1 : itype = M32R2F_INSN_JNC; goto extract_sfmt_jc;
-          case 2 : itype = M32R2F_INSN_JL; goto extract_sfmt_jl;
-          case 3 : itype = M32R2F_INSN_JMP; goto extract_sfmt_jmp;
+          case 0 :
+            if ((entire_insn & 0xfff0) == 0x1cc0)
+              { itype = M32R2F_INSN_JC; goto extract_sfmt_jc; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0xfff0) == 0x1dc0)
+              { itype = M32R2F_INSN_JNC; goto extract_sfmt_jc; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0xfff0) == 0x1ec0)
+              { itype = M32R2F_INSN_JL; goto extract_sfmt_jl; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0xfff0) == 0x1fc0)
+              { itype = M32R2F_INSN_JMP; goto extract_sfmt_jmp; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 29 : itype = M32R2F_INSN_RTE; goto extract_sfmt_rte;
-      case 31 : itype = M32R2F_INSN_TRAP; goto extract_sfmt_trap;
+      case 29 :
+        if ((entire_insn & 0xffff) == 0x10d6)
+          { itype = M32R2F_INSN_RTE; goto extract_sfmt_rte; }
+        itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 31 :
+        if ((entire_insn & 0xfff0) == 0x10f0)
+          { itype = M32R2F_INSN_TRAP; goto extract_sfmt_trap; }
+        itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
       case 32 : itype = M32R2F_INSN_STB; goto extract_sfmt_stb;
       case 33 : itype = M32R2F_INSN_STB_PLUS; goto extract_sfmt_stb_plus;
       case 34 : itype = M32R2F_INSN_STH; goto extract_sfmt_sth;
@@ -375,18 +403,33 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 0) & (1 << 0)));
           switch (val)
           {
-          case 0 : itype = M32R2F_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a;
-          case 1 : itype = M32R2F_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a;
+          case 0 :
+            if ((entire_insn & 0xf0f3) == 0x5070)
+              { itype = M32R2F_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0xf0f3) == 0x5071)
+              { itype = M32R2F_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 88 : itype = M32R2F_INSN_RACH_DSI; goto extract_sfmt_rac_dsi;
-      case 89 : itype = M32R2F_INSN_RAC_DSI; goto extract_sfmt_rac_dsi;
+      case 88 :
+        if ((entire_insn & 0xf3f2) == 0x5080)
+          { itype = M32R2F_INSN_RACH_DSI; goto extract_sfmt_rac_dsi; }
+        itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 89 :
+        if ((entire_insn & 0xf3f2) == 0x5090)
+          { itype = M32R2F_INSN_RAC_DSI; goto extract_sfmt_rac_dsi; }
+        itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
       case 90 : itype = M32R2F_INSN_MULWU1; goto extract_sfmt_mulwu1;
       case 91 : itype = M32R2F_INSN_MACWU1; goto extract_sfmt_macwu1;
       case 92 : itype = M32R2F_INSN_MACLH1; goto extract_sfmt_macwu1;
       case 93 : itype = M32R2F_INSN_MSBLO; goto extract_sfmt_msblo;
-      case 94 : itype = M32R2F_INSN_SADD; goto extract_sfmt_sadd;
+      case 94 :
+        if ((entire_insn & 0xffff) == 0x50e4)
+          { itype = M32R2F_INSN_SADD; goto extract_sfmt_sadd; }
+        itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
       case 95 :
         {
           unsigned int val = (((insn >> 0) & (3 << 0)));
@@ -419,13 +462,22 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0)));
           switch (val)
           {
-          case 0 : itype = M32R2F_INSN_NOP; goto extract_sfmt_nop;
+          case 0 :
+            if ((entire_insn & 0xffff) == 0x7000)
+              { itype = M32R2F_INSN_NOP; goto extract_sfmt_nop; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
           case 2 : /* fall through */
           case 3 : itype = M32R2F_INSN_SETPSW; goto extract_sfmt_setpsw;
           case 4 : /* fall through */
           case 5 : itype = M32R2F_INSN_CLRPSW; goto extract_sfmt_clrpsw;
-          case 9 : itype = M32R2F_INSN_SC; goto extract_sfmt_sc;
-          case 11 : itype = M32R2F_INSN_SNC; goto extract_sfmt_sc;
+          case 9 :
+            if ((entire_insn & 0xffff) == 0x7401)
+              { itype = M32R2F_INSN_SC; goto extract_sfmt_sc; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 11 :
+            if ((entire_insn & 0xffff) == 0x7501)
+              { itype = M32R2F_INSN_SNC; goto extract_sfmt_sc; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
           case 16 : /* fall through */
           case 17 : itype = M32R2F_INSN_BCL8; goto extract_sfmt_bcl8;
           case 18 : /* fall through */
@@ -471,16 +523,31 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
           default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 132 : itype = M32R2F_INSN_CMPI; goto extract_sfmt_cmpi;
-      case 133 : itype = M32R2F_INSN_CMPUI; goto extract_sfmt_cmpi;
+      case 132 :
+        if ((entire_insn & 0xfff00000) == 0x80400000)
+          { itype = M32R2F_INSN_CMPI; goto extract_sfmt_cmpi; }
+        itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 133 :
+        if ((entire_insn & 0xfff00000) == 0x80500000)
+          { itype = M32R2F_INSN_CMPUI; goto extract_sfmt_cmpi; }
+        itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
       case 134 :
         {
-          unsigned int val = (((insn >> -8) & (3 << 0)));
+          unsigned int val = (((entire_insn >> 8) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = M32R2F_INSN_SAT; goto extract_sfmt_sat;
-          case 2 : itype = M32R2F_INSN_SATH; goto extract_sfmt_satb;
-          case 3 : itype = M32R2F_INSN_SATB; goto extract_sfmt_satb;
+          case 0 :
+            if ((entire_insn & 0xf0f0ffff) == 0x80600000)
+              { itype = M32R2F_INSN_SAT; goto extract_sfmt_sat; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0xf0f0ffff) == 0x80600200)
+              { itype = M32R2F_INSN_SATH; goto extract_sfmt_satb; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0xf0f0ffff) == 0x80600300)
+              { itype = M32R2F_INSN_SATB; goto extract_sfmt_satb; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -491,57 +558,102 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
       case 142 : itype = M32R2F_INSN_OR3; goto extract_sfmt_or3;
       case 144 :
         {
-          unsigned int val = (((insn >> -13) & (3 << 0)));
+          unsigned int val = (((entire_insn >> 3) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = M32R2F_INSN_DIV; goto extract_sfmt_div;
-          case 2 : itype = M32R2F_INSN_DIVH; goto extract_sfmt_div;
-          case 3 : itype = M32R2F_INSN_DIVB; goto extract_sfmt_div;
+          case 0 :
+            if ((entire_insn & 0xf0f0ffff) == 0x90000000)
+              { itype = M32R2F_INSN_DIV; goto extract_sfmt_div; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0xf0f0ffff) == 0x90000010)
+              { itype = M32R2F_INSN_DIVH; goto extract_sfmt_div; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0xf0f0ffff) == 0x90000018)
+              { itype = M32R2F_INSN_DIVB; goto extract_sfmt_div; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
       case 145 :
         {
-          unsigned int val = (((insn >> -13) & (3 << 0)));
+          unsigned int val = (((entire_insn >> 3) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = M32R2F_INSN_DIVU; goto extract_sfmt_div;
-          case 2 : itype = M32R2F_INSN_DIVUH; goto extract_sfmt_div;
-          case 3 : itype = M32R2F_INSN_DIVUB; goto extract_sfmt_div;
+          case 0 :
+            if ((entire_insn & 0xf0f0ffff) == 0x90100000)
+              { itype = M32R2F_INSN_DIVU; goto extract_sfmt_div; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0xf0f0ffff) == 0x90100010)
+              { itype = M32R2F_INSN_DIVUH; goto extract_sfmt_div; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0xf0f0ffff) == 0x90100018)
+              { itype = M32R2F_INSN_DIVUB; goto extract_sfmt_div; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
       case 146 :
         {
-          unsigned int val = (((insn >> -13) & (3 << 0)));
+          unsigned int val = (((entire_insn >> 3) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = M32R2F_INSN_REM; goto extract_sfmt_div;
-          case 2 : itype = M32R2F_INSN_REMH; goto extract_sfmt_div;
-          case 3 : itype = M32R2F_INSN_REMB; goto extract_sfmt_div;
+          case 0 :
+            if ((entire_insn & 0xf0f0ffff) == 0x90200000)
+              { itype = M32R2F_INSN_REM; goto extract_sfmt_div; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0xf0f0ffff) == 0x90200010)
+              { itype = M32R2F_INSN_REMH; goto extract_sfmt_div; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0xf0f0ffff) == 0x90200018)
+              { itype = M32R2F_INSN_REMB; goto extract_sfmt_div; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
       case 147 :
         {
-          unsigned int val = (((insn >> -13) & (3 << 0)));
+          unsigned int val = (((entire_insn >> 3) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = M32R2F_INSN_REMU; goto extract_sfmt_div;
-          case 2 : itype = M32R2F_INSN_REMUH; goto extract_sfmt_div;
-          case 3 : itype = M32R2F_INSN_REMUB; goto extract_sfmt_div;
+          case 0 :
+            if ((entire_insn & 0xf0f0ffff) == 0x90300000)
+              { itype = M32R2F_INSN_REMU; goto extract_sfmt_div; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0xf0f0ffff) == 0x90300010)
+              { itype = M32R2F_INSN_REMUH; goto extract_sfmt_div; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0xf0f0ffff) == 0x90300018)
+              { itype = M32R2F_INSN_REMUB; goto extract_sfmt_div; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
       case 152 : itype = M32R2F_INSN_SRL3; goto extract_sfmt_sll3;
       case 154 : itype = M32R2F_INSN_SRA3; goto extract_sfmt_sll3;
       case 156 : itype = M32R2F_INSN_SLL3; goto extract_sfmt_sll3;
-      case 159 : itype = M32R2F_INSN_LDI16; goto extract_sfmt_ldi16;
+      case 159 :
+        if ((entire_insn & 0xf0ff0000) == 0x90f00000)
+          { itype = M32R2F_INSN_LDI16; goto extract_sfmt_ldi16; }
+        itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
       case 160 : itype = M32R2F_INSN_STB_D; goto extract_sfmt_stb_d;
       case 162 : itype = M32R2F_INSN_STH_D; goto extract_sfmt_sth_d;
       case 164 : itype = M32R2F_INSN_ST_D; goto extract_sfmt_st_d;
-      case 166 : itype = M32R2F_INSN_BSET; goto extract_sfmt_bset;
-      case 167 : itype = M32R2F_INSN_BCLR; goto extract_sfmt_bset;
+      case 166 :
+        if ((entire_insn & 0xf8f00000) == 0xa0600000)
+          { itype = M32R2F_INSN_BSET; goto extract_sfmt_bset; }
+        itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 167 :
+        if ((entire_insn & 0xf8f00000) == 0xa0700000)
+          { itype = M32R2F_INSN_BCLR; goto extract_sfmt_bset; }
+        itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
       case 168 : itype = M32R2F_INSN_LDB_D; goto extract_sfmt_ldb_d;
       case 169 : itype = M32R2F_INSN_LDUB_D; goto extract_sfmt_ldb_d;
       case 170 : itype = M32R2F_INSN_LDH_D; goto extract_sfmt_ldh_d;
@@ -549,13 +661,34 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
       case 172 : itype = M32R2F_INSN_LD_D; goto extract_sfmt_ld_d;
       case 176 : itype = M32R2F_INSN_BEQ; goto extract_sfmt_beq;
       case 177 : itype = M32R2F_INSN_BNE; goto extract_sfmt_beq;
-      case 184 : itype = M32R2F_INSN_BEQZ; goto extract_sfmt_beqz;
-      case 185 : itype = M32R2F_INSN_BNEZ; goto extract_sfmt_beqz;
-      case 186 : itype = M32R2F_INSN_BLTZ; goto extract_sfmt_beqz;
-      case 187 : itype = M32R2F_INSN_BGEZ; goto extract_sfmt_beqz;
-      case 188 : itype = M32R2F_INSN_BLEZ; goto extract_sfmt_beqz;
-      case 189 : itype = M32R2F_INSN_BGTZ; goto extract_sfmt_beqz;
-      case 220 : itype = M32R2F_INSN_SETH; goto extract_sfmt_seth;
+      case 184 :
+        if ((entire_insn & 0xfff00000) == 0xb0800000)
+          { itype = M32R2F_INSN_BEQZ; goto extract_sfmt_beqz; }
+        itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 185 :
+        if ((entire_insn & 0xfff00000) == 0xb0900000)
+          { itype = M32R2F_INSN_BNEZ; goto extract_sfmt_beqz; }
+        itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 186 :
+        if ((entire_insn & 0xfff00000) == 0xb0a00000)
+          { itype = M32R2F_INSN_BLTZ; goto extract_sfmt_beqz; }
+        itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 187 :
+        if ((entire_insn & 0xfff00000) == 0xb0b00000)
+          { itype = M32R2F_INSN_BGEZ; goto extract_sfmt_beqz; }
+        itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 188 :
+        if ((entire_insn & 0xfff00000) == 0xb0c00000)
+          { itype = M32R2F_INSN_BLEZ; goto extract_sfmt_beqz; }
+        itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 189 :
+        if ((entire_insn & 0xfff00000) == 0xb0d00000)
+          { itype = M32R2F_INSN_BGTZ; goto extract_sfmt_beqz; }
+        itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 220 :
+        if ((entire_insn & 0xf0ff0000) == 0xd0c00000)
+          { itype = M32R2F_INSN_SETH; goto extract_sfmt_seth; }
+        itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
       case 224 : /* fall through */
       case 225 : /* fall through */
       case 226 : /* fall through */
@@ -592,12 +725,30 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 8) & (7 << 0)));
           switch (val)
           {
-          case 0 : itype = M32R2F_INSN_BCL24; goto extract_sfmt_bcl24;
-          case 1 : itype = M32R2F_INSN_BNCL24; goto extract_sfmt_bcl24;
-          case 4 : itype = M32R2F_INSN_BC24; goto extract_sfmt_bc24;
-          case 5 : itype = M32R2F_INSN_BNC24; goto extract_sfmt_bc24;
-          case 6 : itype = M32R2F_INSN_BL24; goto extract_sfmt_bl24;
-          case 7 : itype = M32R2F_INSN_BRA24; goto extract_sfmt_bra24;
+          case 0 :
+            if ((entire_insn & 0xff000000) == 0xf8000000)
+              { itype = M32R2F_INSN_BCL24; goto extract_sfmt_bcl24; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0xff000000) == 0xf9000000)
+              { itype = M32R2F_INSN_BNCL24; goto extract_sfmt_bcl24; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 4 :
+            if ((entire_insn & 0xff000000) == 0xfc000000)
+              { itype = M32R2F_INSN_BC24; goto extract_sfmt_bc24; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 5 :
+            if ((entire_insn & 0xff000000) == 0xfd000000)
+              { itype = M32R2F_INSN_BNC24; goto extract_sfmt_bc24; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 6 :
+            if ((entire_insn & 0xff000000) == 0xfe000000)
+              { itype = M32R2F_INSN_BL24; goto extract_sfmt_bl24; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 7 :
+            if ((entire_insn & 0xff000000) == 0xff000000)
+              { itype = M32R2F_INSN_BRA24; goto extract_sfmt_bra24; }
+            itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
diff --git a/sim/m32r/decode2.h b/sim/m32r/decode2.h
index ef49292b15e..a04c469af4e 100644
--- a/sim/m32r/decode2.h
+++ b/sim/m32r/decode2.h
@@ -2,22 +2,23 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
diff --git a/sim/m32r/decodex.c b/sim/m32r/decodex.c
index 8f6ba67e5ef..f1644b97e3f 100644
--- a/sim/m32r/decodex.c
+++ b/sim/m32r/decodex.c
@@ -2,22 +2,23 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
@@ -276,8 +277,14 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 8) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RXF_INSN_CMPZ; goto extract_sfmt_cmpz;
-          case 3 : itype = M32RXF_INSN_PCMPBZ; goto extract_sfmt_cmpz;
+          case 0 :
+            if ((entire_insn & 0xfff0) == 0x70)
+              { itype = M32RXF_INSN_CMPZ; goto extract_sfmt_cmpz; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0xfff0) == 0x370)
+              { itype = M32RXF_INSN_PCMPBZ; goto extract_sfmt_cmpz; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -288,7 +295,10 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 12 : itype = M32RXF_INSN_AND; goto extract_sfmt_add;
       case 13 : itype = M32RXF_INSN_XOR; goto extract_sfmt_add;
       case 14 : itype = M32RXF_INSN_OR; goto extract_sfmt_add;
-      case 15 : itype = M32RXF_INSN_BTST; goto extract_sfmt_btst;
+      case 15 :
+        if ((entire_insn & 0xf8f0) == 0xf0)
+          { itype = M32RXF_INSN_BTST; goto extract_sfmt_btst; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 16 : itype = M32RXF_INSN_SRL; goto extract_sfmt_add;
       case 18 : itype = M32RXF_INSN_SRA; goto extract_sfmt_add;
       case 20 : itype = M32RXF_INSN_SLL; goto extract_sfmt_add;
@@ -301,15 +311,33 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 8) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RXF_INSN_JC; goto extract_sfmt_jc;
-          case 1 : itype = M32RXF_INSN_JNC; goto extract_sfmt_jc;
-          case 2 : itype = M32RXF_INSN_JL; goto extract_sfmt_jl;
-          case 3 : itype = M32RXF_INSN_JMP; goto extract_sfmt_jmp;
+          case 0 :
+            if ((entire_insn & 0xfff0) == 0x1cc0)
+              { itype = M32RXF_INSN_JC; goto extract_sfmt_jc; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0xfff0) == 0x1dc0)
+              { itype = M32RXF_INSN_JNC; goto extract_sfmt_jc; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0xfff0) == 0x1ec0)
+              { itype = M32RXF_INSN_JL; goto extract_sfmt_jl; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0xfff0) == 0x1fc0)
+              { itype = M32RXF_INSN_JMP; goto extract_sfmt_jmp; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 29 : itype = M32RXF_INSN_RTE; goto extract_sfmt_rte;
-      case 31 : itype = M32RXF_INSN_TRAP; goto extract_sfmt_trap;
+      case 29 :
+        if ((entire_insn & 0xffff) == 0x10d6)
+          { itype = M32RXF_INSN_RTE; goto extract_sfmt_rte; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 31 :
+        if ((entire_insn & 0xfff0) == 0x10f0)
+          { itype = M32RXF_INSN_TRAP; goto extract_sfmt_trap; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 32 : itype = M32RXF_INSN_STB; goto extract_sfmt_stb;
       case 33 : itype = M32RXF_INSN_STB_PLUS; goto extract_sfmt_stb_plus;
       case 34 : itype = M32RXF_INSN_STH; goto extract_sfmt_sth;
@@ -368,18 +396,33 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 0) & (1 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RXF_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a;
-          case 1 : itype = M32RXF_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a;
+          case 0 :
+            if ((entire_insn & 0xf0f3) == 0x5070)
+              { itype = M32RXF_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0xf0f3) == 0x5071)
+              { itype = M32RXF_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 88 : itype = M32RXF_INSN_RACH_DSI; goto extract_sfmt_rac_dsi;
-      case 89 : itype = M32RXF_INSN_RAC_DSI; goto extract_sfmt_rac_dsi;
+      case 88 :
+        if ((entire_insn & 0xf3f2) == 0x5080)
+          { itype = M32RXF_INSN_RACH_DSI; goto extract_sfmt_rac_dsi; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 89 :
+        if ((entire_insn & 0xf3f2) == 0x5090)
+          { itype = M32RXF_INSN_RAC_DSI; goto extract_sfmt_rac_dsi; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 90 : itype = M32RXF_INSN_MULWU1; goto extract_sfmt_mulwu1;
       case 91 : itype = M32RXF_INSN_MACWU1; goto extract_sfmt_macwu1;
       case 92 : itype = M32RXF_INSN_MACLH1; goto extract_sfmt_macwu1;
       case 93 : itype = M32RXF_INSN_MSBLO; goto extract_sfmt_msblo;
-      case 94 : itype = M32RXF_INSN_SADD; goto extract_sfmt_sadd;
+      case 94 :
+        if ((entire_insn & 0xffff) == 0x50e4)
+          { itype = M32RXF_INSN_SADD; goto extract_sfmt_sadd; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 95 :
         {
           unsigned int val = (((insn >> 0) & (3 << 0)));
@@ -412,13 +455,22 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RXF_INSN_NOP; goto extract_sfmt_nop;
+          case 0 :
+            if ((entire_insn & 0xffff) == 0x7000)
+              { itype = M32RXF_INSN_NOP; goto extract_sfmt_nop; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           case 2 : /* fall through */
           case 3 : itype = M32RXF_INSN_SETPSW; goto extract_sfmt_setpsw;
           case 4 : /* fall through */
           case 5 : itype = M32RXF_INSN_CLRPSW; goto extract_sfmt_clrpsw;
-          case 9 : itype = M32RXF_INSN_SC; goto extract_sfmt_sc;
-          case 11 : itype = M32RXF_INSN_SNC; goto extract_sfmt_sc;
+          case 9 :
+            if ((entire_insn & 0xffff) == 0x7401)
+              { itype = M32RXF_INSN_SC; goto extract_sfmt_sc; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 11 :
+            if ((entire_insn & 0xffff) == 0x7501)
+              { itype = M32RXF_INSN_SNC; goto extract_sfmt_sc; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           case 16 : /* fall through */
           case 17 : itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8;
           case 18 : /* fall through */
@@ -464,16 +516,31 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
           default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 132 : itype = M32RXF_INSN_CMPI; goto extract_sfmt_cmpi;
-      case 133 : itype = M32RXF_INSN_CMPUI; goto extract_sfmt_cmpi;
+      case 132 :
+        if ((entire_insn & 0xfff00000) == 0x80400000)
+          { itype = M32RXF_INSN_CMPI; goto extract_sfmt_cmpi; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 133 :
+        if ((entire_insn & 0xfff00000) == 0x80500000)
+          { itype = M32RXF_INSN_CMPUI; goto extract_sfmt_cmpi; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 134 :
         {
-          unsigned int val = (((insn >> -8) & (3 << 0)));
+          unsigned int val = (((entire_insn >> 8) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RXF_INSN_SAT; goto extract_sfmt_sat;
-          case 2 : itype = M32RXF_INSN_SATH; goto extract_sfmt_satb;
-          case 3 : itype = M32RXF_INSN_SATB; goto extract_sfmt_satb;
+          case 0 :
+            if ((entire_insn & 0xf0f0ffff) == 0x80600000)
+              { itype = M32RXF_INSN_SAT; goto extract_sfmt_sat; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0xf0f0ffff) == 0x80600200)
+              { itype = M32RXF_INSN_SATH; goto extract_sfmt_satb; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0xf0f0ffff) == 0x80600300)
+              { itype = M32RXF_INSN_SATB; goto extract_sfmt_satb; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -484,26 +551,50 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 142 : itype = M32RXF_INSN_OR3; goto extract_sfmt_or3;
       case 144 :
         {
-          unsigned int val = (((insn >> -12) & (1 << 0)));
+          unsigned int val = (((entire_insn >> 4) & (1 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RXF_INSN_DIV; goto extract_sfmt_div;
-          case 1 : itype = M32RXF_INSN_DIVH; goto extract_sfmt_div;
+          case 0 :
+            if ((entire_insn & 0xf0f0ffff) == 0x90000000)
+              { itype = M32RXF_INSN_DIV; goto extract_sfmt_div; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0xf0f0ffff) == 0x90000010)
+              { itype = M32RXF_INSN_DIVH; goto extract_sfmt_div; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 145 : itype = M32RXF_INSN_DIVU; goto extract_sfmt_div;
-      case 146 : itype = M32RXF_INSN_REM; goto extract_sfmt_div;
-      case 147 : itype = M32RXF_INSN_REMU; goto extract_sfmt_div;
+      case 145 :
+        if ((entire_insn & 0xf0f0ffff) == 0x90100000)
+          { itype = M32RXF_INSN_DIVU; goto extract_sfmt_div; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 146 :
+        if ((entire_insn & 0xf0f0ffff) == 0x90200000)
+          { itype = M32RXF_INSN_REM; goto extract_sfmt_div; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 147 :
+        if ((entire_insn & 0xf0f0ffff) == 0x90300000)
+          { itype = M32RXF_INSN_REMU; goto extract_sfmt_div; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 152 : itype = M32RXF_INSN_SRL3; goto extract_sfmt_sll3;
       case 154 : itype = M32RXF_INSN_SRA3; goto extract_sfmt_sll3;
       case 156 : itype = M32RXF_INSN_SLL3; goto extract_sfmt_sll3;
-      case 159 : itype = M32RXF_INSN_LDI16; goto extract_sfmt_ldi16;
+      case 159 :
+        if ((entire_insn & 0xf0ff0000) == 0x90f00000)
+          { itype = M32RXF_INSN_LDI16; goto extract_sfmt_ldi16; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 160 : itype = M32RXF_INSN_STB_D; goto extract_sfmt_stb_d;
       case 162 : itype = M32RXF_INSN_STH_D; goto extract_sfmt_sth_d;
       case 164 : itype = M32RXF_INSN_ST_D; goto extract_sfmt_st_d;
-      case 166 : itype = M32RXF_INSN_BSET; goto extract_sfmt_bset;
-      case 167 : itype = M32RXF_INSN_BCLR; goto extract_sfmt_bset;
+      case 166 :
+        if ((entire_insn & 0xf8f00000) == 0xa0600000)
+          { itype = M32RXF_INSN_BSET; goto extract_sfmt_bset; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 167 :
+        if ((entire_insn & 0xf8f00000) == 0xa0700000)
+          { itype = M32RXF_INSN_BCLR; goto extract_sfmt_bset; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 168 : itype = M32RXF_INSN_LDB_D; goto extract_sfmt_ldb_d;
       case 169 : itype = M32RXF_INSN_LDUB_D; goto extract_sfmt_ldb_d;
       case 170 : itype = M32RXF_INSN_LDH_D; goto extract_sfmt_ldh_d;
@@ -511,13 +602,34 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 172 : itype = M32RXF_INSN_LD_D; goto extract_sfmt_ld_d;
       case 176 : itype = M32RXF_INSN_BEQ; goto extract_sfmt_beq;
       case 177 : itype = M32RXF_INSN_BNE; goto extract_sfmt_beq;
-      case 184 : itype = M32RXF_INSN_BEQZ; goto extract_sfmt_beqz;
-      case 185 : itype = M32RXF_INSN_BNEZ; goto extract_sfmt_beqz;
-      case 186 : itype = M32RXF_INSN_BLTZ; goto extract_sfmt_beqz;
-      case 187 : itype = M32RXF_INSN_BGEZ; goto extract_sfmt_beqz;
-      case 188 : itype = M32RXF_INSN_BLEZ; goto extract_sfmt_beqz;
-      case 189 : itype = M32RXF_INSN_BGTZ; goto extract_sfmt_beqz;
-      case 220 : itype = M32RXF_INSN_SETH; goto extract_sfmt_seth;
+      case 184 :
+        if ((entire_insn & 0xfff00000) == 0xb0800000)
+          { itype = M32RXF_INSN_BEQZ; goto extract_sfmt_beqz; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 185 :
+        if ((entire_insn & 0xfff00000) == 0xb0900000)
+          { itype = M32RXF_INSN_BNEZ; goto extract_sfmt_beqz; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 186 :
+        if ((entire_insn & 0xfff00000) == 0xb0a00000)
+          { itype = M32RXF_INSN_BLTZ; goto extract_sfmt_beqz; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 187 :
+        if ((entire_insn & 0xfff00000) == 0xb0b00000)
+          { itype = M32RXF_INSN_BGEZ; goto extract_sfmt_beqz; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 188 :
+        if ((entire_insn & 0xfff00000) == 0xb0c00000)
+          { itype = M32RXF_INSN_BLEZ; goto extract_sfmt_beqz; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 189 :
+        if ((entire_insn & 0xfff00000) == 0xb0d00000)
+          { itype = M32RXF_INSN_BGTZ; goto extract_sfmt_beqz; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 220 :
+        if ((entire_insn & 0xf0ff0000) == 0xd0c00000)
+          { itype = M32RXF_INSN_SETH; goto extract_sfmt_seth; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 224 : /* fall through */
       case 225 : /* fall through */
       case 226 : /* fall through */
@@ -554,12 +666,30 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 8) & (7 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RXF_INSN_BCL24; goto extract_sfmt_bcl24;
-          case 1 : itype = M32RXF_INSN_BNCL24; goto extract_sfmt_bcl24;
-          case 4 : itype = M32RXF_INSN_BC24; goto extract_sfmt_bc24;
-          case 5 : itype = M32RXF_INSN_BNC24; goto extract_sfmt_bc24;
-          case 6 : itype = M32RXF_INSN_BL24; goto extract_sfmt_bl24;
-          case 7 : itype = M32RXF_INSN_BRA24; goto extract_sfmt_bra24;
+          case 0 :
+            if ((entire_insn & 0xff000000) == 0xf8000000)
+              { itype = M32RXF_INSN_BCL24; goto extract_sfmt_bcl24; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0xff000000) == 0xf9000000)
+              { itype = M32RXF_INSN_BNCL24; goto extract_sfmt_bcl24; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 4 :
+            if ((entire_insn & 0xff000000) == 0xfc000000)
+              { itype = M32RXF_INSN_BC24; goto extract_sfmt_bc24; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 5 :
+            if ((entire_insn & 0xff000000) == 0xfd000000)
+              { itype = M32RXF_INSN_BNC24; goto extract_sfmt_bc24; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 6 :
+            if ((entire_insn & 0xff000000) == 0xfe000000)
+              { itype = M32RXF_INSN_BL24; goto extract_sfmt_bl24; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 7 :
+            if ((entire_insn & 0xff000000) == 0xff000000)
+              { itype = M32RXF_INSN_BRA24; goto extract_sfmt_bra24; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
diff --git a/sim/m32r/decodex.h b/sim/m32r/decodex.h
index 646205cbd44..e6e2395095c 100644
--- a/sim/m32r/decodex.h
+++ b/sim/m32r/decodex.h
@@ -2,22 +2,23 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
diff --git a/sim/m32r/model.c b/sim/m32r/model.c
index 2e20191c20b..a61e92c339a 100644
--- a/sim/m32r/model.c
+++ b/sim/m32r/model.c
@@ -2,22 +2,23 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
diff --git a/sim/m32r/model2.c b/sim/m32r/model2.c
index 4408ed64926..91d7bba2259 100644
--- a/sim/m32r/model2.c
+++ b/sim/m32r/model2.c
@@ -2,22 +2,23 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
diff --git a/sim/m32r/modelx.c b/sim/m32r/modelx.c
index c0388b08920..674a27a8bb6 100644
--- a/sim/m32r/modelx.c
+++ b/sim/m32r/modelx.c
@@ -2,22 +2,23 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
diff --git a/sim/m32r/sem-switch.c b/sim/m32r/sem-switch.c
index 3ed38d1e7b5..6febf087248 100644
--- a/sim/m32r/sem-switch.c
+++ b/sim/m32r/sem-switch.c
@@ -2,22 +2,23 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
@@ -2518,7 +2519,7 @@ if (CPU (h_lock)) {
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)), 65280));
+    USI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (ZEXTQISI (INVQI (FLD (f_uimm8))), 65280));
     SET_H_CR (((UINT) 0), opval);
     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
   }
@@ -2537,7 +2538,7 @@ if (CPU (h_lock)) {
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = FLD (f_uimm8);
+    USI opval = FLD (f_uimm8);
     SET_H_CR (((UINT) 0), opval);
     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
   }
@@ -2556,7 +2557,7 @@ if (CPU (h_lock)) {
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    QI opval = ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), SLLSI (1, SUBSI (7, FLD (f_uimm3))));
+    QI opval = ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), SLLQI (1, SUBSI (7, FLD (f_uimm3))));
     SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
   }
@@ -2575,7 +2576,7 @@ if (CPU (h_lock)) {
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    QI opval = ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), INVQI (SLLSI (1, SUBSI (7, FLD (f_uimm3)))));
+    QI opval = ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), INVQI (SLLQI (1, SUBSI (7, FLD (f_uimm3)))));
     SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
   }
@@ -2594,7 +2595,7 @@ if (CPU (h_lock)) {
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    BI opval = ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
+    BI opval = ANDQI (SRLQI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
   }
diff --git a/sim/m32r/sem.c b/sim/m32r/sem.c
index a4d91108545..431298c5ed9 100644
--- a/sim/m32r/sem.c
+++ b/sim/m32r/sem.c
@@ -2,22 +2,23 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
@@ -2574,7 +2575,7 @@ SEM_FN_NAME (m32rbf,clrpsw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)), 65280));
+    USI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (ZEXTQISI (INVQI (FLD (f_uimm8))), 65280));
     SET_H_CR (((UINT) 0), opval);
     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
   }
@@ -2595,7 +2596,7 @@ SEM_FN_NAME (m32rbf,setpsw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = FLD (f_uimm8);
+    USI opval = FLD (f_uimm8);
     SET_H_CR (((UINT) 0), opval);
     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
   }
@@ -2616,7 +2617,7 @@ SEM_FN_NAME (m32rbf,bset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    QI opval = ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), SLLSI (1, SUBSI (7, FLD (f_uimm3))));
+    QI opval = ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), SLLQI (1, SUBSI (7, FLD (f_uimm3))));
     SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
   }
@@ -2637,7 +2638,7 @@ SEM_FN_NAME (m32rbf,bclr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    QI opval = ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), INVQI (SLLSI (1, SUBSI (7, FLD (f_uimm3)))));
+    QI opval = ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), INVQI (SLLQI (1, SUBSI (7, FLD (f_uimm3)))));
     SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
   }
@@ -2658,7 +2659,7 @@ SEM_FN_NAME (m32rbf,btst) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    BI opval = ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
+    BI opval = ANDQI (SRLQI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
   }
diff --git a/sim/m32r/sem2-switch.c b/sim/m32r/sem2-switch.c
index 090880ecee2..e84ccdddedf 100644
--- a/sim/m32r/sem2-switch.c
+++ b/sim/m32r/sem2-switch.c
@@ -2,22 +2,23 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
@@ -2921,15 +2922,15 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 {
-  HI tmp_new_src2;
+  SI tmp_new_src2;
+  tmp_new_src2 = * FLD (i_src2);
   {
     HI opval = * FLD (i_src1);
     SETMEMHI (current_cpu, pc, tmp_new_src2, opval);
     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
   }
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 2);
   {
-    SI opval = tmp_new_src2;
+    SI opval = ADDSI (tmp_new_src2, 2);
     * FLD (i_src2) = opval;
     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
   }
@@ -2949,15 +2950,15 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 {
-  QI tmp_new_src2;
+  SI tmp_new_src2;
+  tmp_new_src2 = * FLD (i_src2);
   {
     QI opval = * FLD (i_src1);
     SETMEMQI (current_cpu, pc, tmp_new_src2, opval);
     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
   }
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 1);
   {
-    SI opval = tmp_new_src2;
+    SI opval = ADDSI (tmp_new_src2, 1);
     * FLD (i_src2) = opval;
     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
   }
@@ -3363,7 +3364,7 @@ if (ZEXTBISI (NOTBI (CPU (h_cond))))
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)), 65280));
+    USI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (ZEXTQISI (INVQI (FLD (f_uimm8))), 65280));
     SET_H_CR (((UINT) 0), opval);
     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
   }
@@ -3382,7 +3383,7 @@ if (ZEXTBISI (NOTBI (CPU (h_cond))))
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = FLD (f_uimm8);
+    USI opval = FLD (f_uimm8);
     SET_H_CR (((UINT) 0), opval);
     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
   }
@@ -3401,7 +3402,7 @@ if (ZEXTBISI (NOTBI (CPU (h_cond))))
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    QI opval = ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), SLLSI (1, SUBSI (7, FLD (f_uimm3))));
+    QI opval = ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), SLLQI (1, SUBSI (7, FLD (f_uimm3))));
     SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
   }
@@ -3420,7 +3421,7 @@ if (ZEXTBISI (NOTBI (CPU (h_cond))))
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    QI opval = ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), INVQI (SLLSI (1, SUBSI (7, FLD (f_uimm3)))));
+    QI opval = ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), INVQI (SLLQI (1, SUBSI (7, FLD (f_uimm3)))));
     SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
   }
@@ -3439,7 +3440,7 @@ if (ZEXTBISI (NOTBI (CPU (h_cond))))
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    BI opval = ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
+    BI opval = ANDQI (SRLQI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
   }
@@ -6002,16 +6003,16 @@ CASE (sem, INSN_WRITE_ST_PLUS) : /* st $src1,@+$src2 */
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 {
-  HI tmp_new_src2;
+  SI tmp_new_src2;
+  tmp_new_src2 = * FLD (i_src2);
   {
     HI opval = * FLD (i_src1);
     OPRND (h_memory_HI_new_src2_idx) = tmp_new_src2;
     OPRND (h_memory_HI_new_src2) = opval;
     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
   }
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 2);
   {
-    SI opval = tmp_new_src2;
+    SI opval = ADDSI (tmp_new_src2, 2);
     OPRND (src2) = opval;
     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
   }
@@ -6051,16 +6052,16 @@ CASE (sem, INSN_WRITE_STH_PLUS) : /* sth $src1,@$src2+ */
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 {
-  QI tmp_new_src2;
+  SI tmp_new_src2;
+  tmp_new_src2 = * FLD (i_src2);
   {
     QI opval = * FLD (i_src1);
     OPRND (h_memory_QI_new_src2_idx) = tmp_new_src2;
     OPRND (h_memory_QI_new_src2) = opval;
     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
   }
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 1);
   {
-    SI opval = tmp_new_src2;
+    SI opval = ADDSI (tmp_new_src2, 1);
     OPRND (src2) = opval;
     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
   }
@@ -6707,7 +6708,7 @@ CASE (sem, INSN_WRITE_SNC) : /* snc */
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)), 65280));
+    USI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (ZEXTQISI (INVQI (FLD (f_uimm8))), 65280));
     OPRND (h_cr_USI_0) = opval;
     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
   }
@@ -6745,7 +6746,7 @@ CASE (sem, INSN_WRITE_CLRPSW) : /* clrpsw $uimm8 */
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = FLD (f_uimm8);
+    USI opval = FLD (f_uimm8);
     OPRND (h_cr_USI_0) = opval;
     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
   }
@@ -6783,7 +6784,7 @@ CASE (sem, INSN_WRITE_SETPSW) : /* setpsw $uimm8 */
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    BI opval = ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
+    BI opval = ANDQI (SRLQI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
     OPRND (condbit) = opval;
     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
   }
diff --git a/sim/m32r/semx-switch.c b/sim/m32r/semx-switch.c
index fa95074c8e1..3ad54c50179 100644
--- a/sim/m32r/semx-switch.c
+++ b/sim/m32r/semx-switch.c
@@ -2,22 +2,23 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
@@ -2753,15 +2754,15 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 {
-  HI tmp_new_src2;
+  SI tmp_new_src2;
+  tmp_new_src2 = * FLD (i_src2);
   {
     HI opval = * FLD (i_src1);
     SETMEMHI (current_cpu, pc, tmp_new_src2, opval);
     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
   }
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 2);
   {
-    SI opval = tmp_new_src2;
+    SI opval = ADDSI (tmp_new_src2, 2);
     * FLD (i_src2) = opval;
     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
   }
@@ -2781,15 +2782,15 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 {
-  QI tmp_new_src2;
+  SI tmp_new_src2;
+  tmp_new_src2 = * FLD (i_src2);
   {
     QI opval = * FLD (i_src1);
     SETMEMQI (current_cpu, pc, tmp_new_src2, opval);
     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
   }
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 1);
   {
-    SI opval = tmp_new_src2;
+    SI opval = ADDSI (tmp_new_src2, 1);
     * FLD (i_src2) = opval;
     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
   }
@@ -3195,7 +3196,7 @@ if (ZEXTBISI (NOTBI (CPU (h_cond))))
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)), 65280));
+    USI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (ZEXTQISI (INVQI (FLD (f_uimm8))), 65280));
     SET_H_CR (((UINT) 0), opval);
     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
   }
@@ -3214,7 +3215,7 @@ if (ZEXTBISI (NOTBI (CPU (h_cond))))
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = FLD (f_uimm8);
+    USI opval = FLD (f_uimm8);
     SET_H_CR (((UINT) 0), opval);
     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
   }
@@ -3233,7 +3234,7 @@ if (ZEXTBISI (NOTBI (CPU (h_cond))))
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    QI opval = ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), SLLSI (1, SUBSI (7, FLD (f_uimm3))));
+    QI opval = ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), SLLQI (1, SUBSI (7, FLD (f_uimm3))));
     SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
   }
@@ -3252,7 +3253,7 @@ if (ZEXTBISI (NOTBI (CPU (h_cond))))
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    QI opval = ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), INVQI (SLLSI (1, SUBSI (7, FLD (f_uimm3)))));
+    QI opval = ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), INVQI (SLLQI (1, SUBSI (7, FLD (f_uimm3)))));
     SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
   }
@@ -3271,7 +3272,7 @@ if (ZEXTBISI (NOTBI (CPU (h_cond))))
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    BI opval = ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
+    BI opval = ANDQI (SRLQI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
   }
@@ -5834,16 +5835,16 @@ CASE (sem, INSN_WRITE_ST_PLUS) : /* st $src1,@+$src2 */
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 {
-  HI tmp_new_src2;
+  SI tmp_new_src2;
+  tmp_new_src2 = * FLD (i_src2);
   {
     HI opval = * FLD (i_src1);
     OPRND (h_memory_HI_new_src2_idx) = tmp_new_src2;
     OPRND (h_memory_HI_new_src2) = opval;
     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
   }
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 2);
   {
-    SI opval = tmp_new_src2;
+    SI opval = ADDSI (tmp_new_src2, 2);
     OPRND (src2) = opval;
     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
   }
@@ -5883,16 +5884,16 @@ CASE (sem, INSN_WRITE_STH_PLUS) : /* sth $src1,@$src2+ */
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
 {
-  QI tmp_new_src2;
+  SI tmp_new_src2;
+  tmp_new_src2 = * FLD (i_src2);
   {
     QI opval = * FLD (i_src1);
     OPRND (h_memory_QI_new_src2_idx) = tmp_new_src2;
     OPRND (h_memory_QI_new_src2) = opval;
     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
   }
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 1);
   {
-    SI opval = tmp_new_src2;
+    SI opval = ADDSI (tmp_new_src2, 1);
     OPRND (src2) = opval;
     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
   }
@@ -6539,7 +6540,7 @@ CASE (sem, INSN_WRITE_SNC) : /* snc */
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)), 65280));
+    USI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (ZEXTQISI (INVQI (FLD (f_uimm8))), 65280));
     OPRND (h_cr_USI_0) = opval;
     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
   }
@@ -6577,7 +6578,7 @@ CASE (sem, INSN_WRITE_CLRPSW) : /* clrpsw $uimm8 */
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    SI opval = FLD (f_uimm8);
+    USI opval = FLD (f_uimm8);
     OPRND (h_cr_USI_0) = opval;
     TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
   }
@@ -6615,7 +6616,7 @@ CASE (sem, INSN_WRITE_SETPSW) : /* setpsw $uimm8 */
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
   {
-    BI opval = ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
+    BI opval = ANDQI (SRLQI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
     OPRND (condbit) = opval;
     TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
   }