sim: bfin: new PINT model

Newer BF54x parts feature an updated GPIO block where all the interrupt
handling is split off, so create a new model for the pin interrupts.

This is missing the port forwarding aspects, but at least the register
interface should be there.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

1 files changed, 50 insertions, 1 deletions

diff --git a/sim/bfin/machs.c b/sim/bfin/machs.c
index 5267cfa6452..9d0f26314e4 100644
--- a/sim/bfin/machs.c
+++ b/sim/bfin/machs.c
@@ -1,7 +1,7 @@
 /* Simulator for Analog Devices Blackfin processors.
 
    Copyright (C) 2005-2012 Free Software Foundation, Inc.
-   Contributed by Analog Devices, Inc.
+   Contributed by Analog Devices, Inc. and Mike Frysinger.
 
    This file is part of simulators.
 
@@ -914,6 +914,10 @@ static const struct bfin_dev_layout bf542_dev[] =
   DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
   DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
  _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE,      "bfin_eppi@1", 1),
+  DEVICE (0xFFC01400, BFIN_MMR_PINT_SIZE,      "bfin_pint@0"),
+  DEVICE (0xFFC01430, BFIN_MMR_PINT_SIZE,      "bfin_pint@1"),
+ _DEVICE (0xFFC01460, BFIN_MMR_PINT_SIZE,      "bfin_pint@2", 2),
+ _DEVICE (0xFFC01490, BFIN_MMR_PINT_SIZE,      "bfin_pint@3", 2),
   DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@0"),
   DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@1"),
   DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@2"),
@@ -954,6 +958,10 @@ static const struct bfin_dev_layout bf544_dev[] =
   DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
  _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE,      "bfin_eppi@0", 1),
  _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE,      "bfin_eppi@1", 1),
+  DEVICE (0xFFC01400, BFIN_MMR_PINT_SIZE,      "bfin_pint@0"),
+  DEVICE (0xFFC01430, BFIN_MMR_PINT_SIZE,      "bfin_pint@1"),
+ _DEVICE (0xFFC01460, BFIN_MMR_PINT_SIZE,      "bfin_pint@2", 2),
+ _DEVICE (0xFFC01490, BFIN_MMR_PINT_SIZE,      "bfin_pint@3", 2),
   DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@0"),
   DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@1"),
   DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@2"),
@@ -995,6 +1003,10 @@ static const struct bfin_dev_layout bf547_dev[] =
   DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
  _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE,      "bfin_eppi@0", 1),
  _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE,      "bfin_eppi@1", 1),
+  DEVICE (0xFFC01400, BFIN_MMR_PINT_SIZE,      "bfin_pint@0"),
+  DEVICE (0xFFC01430, BFIN_MMR_PINT_SIZE,      "bfin_pint@1"),
+ _DEVICE (0xFFC01460, BFIN_MMR_PINT_SIZE,      "bfin_pint@2", 2),
+ _DEVICE (0xFFC01490, BFIN_MMR_PINT_SIZE,      "bfin_pint@3", 2),
   DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@0"),
   DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@1"),
   DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@2"),
@@ -1034,6 +1046,23 @@ static const struct bfin_dmac_layout bf54x_dmac[] =
 #define bf547_dmac bf54x_dmac
 #define bf548_dmac bf54x_dmac
 #define bf549_dmac bf54x_dmac
+#define PINT_PIQS(p, b, g) \
+  PORT (p, "piq0@"#b,  g, "p0"), \
+  PORT (p, "piq1@"#b,  g, "p1"), \
+  PORT (p, "piq2@"#b,  g, "p2"), \
+  PORT (p, "piq3@"#b,  g, "p3"), \
+  PORT (p, "piq4@"#b,  g, "p4"), \
+  PORT (p, "piq5@"#b,  g, "p5"), \
+  PORT (p, "piq6@"#b,  g, "p6"), \
+  PORT (p, "piq7@"#b,  g, "p7"), \
+  PORT (p, "piq8@"#b,  g, "p8"), \
+  PORT (p, "piq9@"#b,  g, "p9"), \
+  PORT (p, "piq10@"#b, g, "p10"), \
+  PORT (p, "piq11@"#b, g, "p11"), \
+  PORT (p, "piq12@"#b, g, "p12"), \
+  PORT (p, "piq13@"#b, g, "p13"), \
+  PORT (p, "piq14@"#b, g, "p14"), \
+  PORT (p, "piq15@"#b, g, "p15")
 static const struct bfin_port_layout bf54x_port[] =
 {
   SIC (0,  0, "bfin_pll",          "pll"),
@@ -1056,7 +1085,11 @@ static const struct bfin_port_layout bf54x_port[] =
   SIC (0, 17, "bfin_gptimer@9",    "stat"),
   SIC (0, 18, "bfin_gptimer@10",   "stat"),
   SIC (0, 19, "bfin_pint@0",       "stat"),
+  PINT_PIQS ("bfin_pint@0", 0, "bfin_gpio2@0"),
+  PINT_PIQS ("bfin_pint@0", 1, "bfin_gpio2@1"),
   SIC (0, 20, "bfin_pint@1",       "stat"),
+  PINT_PIQS ("bfin_pint@1", 0, "bfin_gpio2@0"),
+  PINT_PIQS ("bfin_pint@1", 1, "bfin_gpio2@1"),
   SIC (0, 21, "bfin_dma@256",      "di"),	/* mdma0 */
   SIC (0, 21, "bfin_dma@257",      "di"),	/* mdma0 */
   SIC (0, 22, "bfin_dma@258",      "di"),	/* mdma1 */
@@ -1138,7 +1171,23 @@ static const struct bfin_port_layout bf54x_port[] =
   SIC (2, 28, "bfin_gptimer@6",    "stat"),
   SIC (2, 29, "bfin_gptimer@7",    "stat"),
   SIC (2, 30, "bfin_pint@2",       "stat"),
+  PINT_PIQS ("bfin_pint@2", 0, "bfin_gpio2@2"),
+  PINT_PIQS ("bfin_pint@2", 1, "bfin_gpio2@3"),
+  PINT_PIQS ("bfin_pint@2", 2, "bfin_gpio2@4"),
+  PINT_PIQS ("bfin_pint@2", 3, "bfin_gpio2@5"),
+  PINT_PIQS ("bfin_pint@2", 4, "bfin_gpio2@6"),
+  PINT_PIQS ("bfin_pint@2", 5, "bfin_gpio2@7"),
+  PINT_PIQS ("bfin_pint@2", 6, "bfin_gpio2@8"),
+  PINT_PIQS ("bfin_pint@2", 7, "bfin_gpio2@9"),
   SIC (2, 31, "bfin_pint@3",       "stat"),
+  PINT_PIQS ("bfin_pint@3", 0, "bfin_gpio2@2"),
+  PINT_PIQS ("bfin_pint@3", 1, "bfin_gpio2@3"),
+  PINT_PIQS ("bfin_pint@3", 2, "bfin_gpio2@4"),
+  PINT_PIQS ("bfin_pint@3", 3, "bfin_gpio2@5"),
+  PINT_PIQS ("bfin_pint@3", 4, "bfin_gpio2@6"),
+  PINT_PIQS ("bfin_pint@3", 5, "bfin_gpio2@7"),
+  PINT_PIQS ("bfin_pint@3", 6, "bfin_gpio2@8"),
+  PINT_PIQS ("bfin_pint@3", 7, "bfin_gpio2@9"),
 };
 #define bf542_port bf54x_port
 #define bf544_port bf54x_port