Add support for .extInstruction pseudo-op.

gas/
2016-04-04  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/textinsn-errors.d: New File.
	* testsuite/gas/arc/textinsn-errors.err: Likewise.
	* testsuite/gas/arc/textinsn-errors.s: Likewise.
	* testsuite/gas/arc/textinsn2op.d: Likewise.
	* testsuite/gas/arc/textinsn2op.s: Likewise.
	* testsuite/gas/arc/textinsn2op01.d: Likewise.
	* testsuite/gas/arc/textinsn2op01.s: Likewise.
	* testsuite/gas/arc/textinsn3op.d: Likewise.
	* testsuite/gas/arc/textinsn3op.s: Likewise.
	* doc/c-arc.texi (ARC Directives): Add .extInstruction
	documentation.
	* config/tc-arc.c (arcext_section): New variable.
	(arc_extinsn): New function.
	(md_pseudo_table): Add .extInstruction pseudo op.
	(attributes_t): New type.
	(suffixclass, syntaxclass, syntaxclassmod): New constant
	structures.
	(find_opcode_match): Remove arc_num_opcodes.
	(md_begin): Likewise.
	(tokenize_extinsn): New function.
	(arc_set_ext_seg): Likewise.
	(create_extinst_section): Likewise.

include/
2016-04-04  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (arc_num_opcodes): Remove.
	(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
	(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
	(ARC_SUFFIX_FLAG): Define.
	(flags_none, flags_f, flags_cc, flags_ccf): Declare.
	(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
	(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
	(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
	(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
	(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
	(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
	(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
	(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
	(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.

opcodes/
2016-04-04  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
	Initialize.
	(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
	(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
	(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
	(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
	(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
	(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
	(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
	(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
	(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
	(arc_opcode arc_opcodes): Null terminate the array.
	(arc_num_opcodes): Remove.
	* arc-ext.h (INSERT_XOP): Define.
	(extInstruction_t): Likewise.
	(arcExtMap_instName): Delete.
	(arcExtMap_insn): New function.
	(arcExtMap_genOpcode): Likewise.
	* arc-ext.c (ExtInstruction): Remove.
	(create_map): Zero initialize instruction fields.
	(arcExtMap_instName): Remove.
	(arcExtMap_insn): New function.
	(dump_ARC_extmap): More info while debuging.
	(arcExtMap_genOpcode): New function.
	* arc-dis.c (find_format): New function.
	(print_insn_arc): Use find_format.
	(arc_get_disassembler): Enable dump_ARC_extmap only when
	debugging.

Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>

5 files changed, 554 insertions, 142 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 4d23c24306f..4eec5ee9df5 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,34 @@
+2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
+	Initialize.
+	(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
+	(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
+	(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
+	(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
+	(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
+	(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
+	(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
+	(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
+	(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
+	(arc_opcode arc_opcodes): Null terminate the array.
+	(arc_num_opcodes): Remove.
+	* arc-ext.h (INSERT_XOP): Define.
+	(extInstruction_t): Likewise.
+	(arcExtMap_instName): Delete.
+	(arcExtMap_insn): New function.
+	(arcExtMap_genOpcode): Likewise.
+	* arc-ext.c (ExtInstruction): Remove.
+	(create_map): Zero initialize instruction fields.
+	(arcExtMap_instName): Remove.
+	(arcExtMap_insn): New function.
+	(dump_ARC_extmap): More info while debuging.
+	(arcExtMap_genOpcode): New function.
+	* arc-dis.c (find_format): New function.
+	(print_insn_arc): Use find_format.
+	(arc_get_disassembler): Enable dump_ARC_extmap only when
+	debugging.
+
 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 
 	* mips-dis.c (print_mips16_insn_arg): Mask unused extended
@@ -27,12 +58,12 @@
 
 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 
-        * arc-regs.h: Add a new subclass field.  Add double assist
-        accumulator register values.
-        * arc-tbl.h: Use DPA subclass to mark the double assist
-        instructions.  Use DPX/SPX subclas to mark the FPX instructions.
-        * arc-opc.c (RSP): Define instead of SP.
-        (arc_aux_regs): Add the subclass field.
+	* arc-regs.h: Add a new subclass field.  Add double assist
+	accumulator register values.
+	* arc-tbl.h: Use DPA subclass to mark the double assist
+	instructions.  Use DPX/SPX subclas to mark the FPX instructions.
+	* arc-opc.c (RSP): Define instead of SP.
+	(arc_aux_regs): Add the subclass field.
 
 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 
@@ -50,23 +81,23 @@
 
 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 
-        * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
-        (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
-        (RTT): Remove duplicate.
-        (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
-        (PCT_CONFIG*): Remove.
-        (D1L, D1H, D2H, D2L): Define.
+	* arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
+	(AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
+	(RTT): Remove duplicate.
+	(LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
+	(PCT_CONFIG*): Remove.
+	(D1L, D1H, D2H, D2L): Define.
 
 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 
-        * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
+	* arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 
 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 
-        * arc-tbl.h (invld07): Remove.
-        * arc-ext-tbl.h: New file.
-        * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
-        * arc-opc.c (arc_opcodes): Add ext-tbl include.
+	* arc-tbl.h (invld07): Remove.
+	* arc-ext-tbl.h: New file.
+	* arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
+	* arc-opc.c (arc_opcodes): Add ext-tbl include.
 
 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 
@@ -164,8 +195,8 @@
 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 	    Janek van Oirschot  <jvanoirs@synopsys.com>
 
-        * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
-        variable.
+	* arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
+	variable.
 
 2016-02-04  Nick Clifton  <nickc@redhat.com>
 
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index 5f8fa42d852..0a03a0f305a 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -102,6 +102,107 @@ special_flag_p (const char *opname,
   return 0;
 }
 
+/* Find proper format for the given opcode.  */
+static const struct arc_opcode *
+find_format (const struct arc_opcode *arc_table,
+	     unsigned *insn, int insnLen,
+	     unsigned isa_mask)
+{
+  unsigned int i = 0;
+  const struct arc_opcode *opcode = NULL;
+  const unsigned char *opidx;
+  const unsigned char *flgidx;
+
+  do {
+    bfd_boolean invalid = FALSE;
+
+    opcode = &arc_table[i++];
+
+    if (ARC_SHORT (opcode->mask) && (insnLen == 2))
+      {
+	if (OPCODE_AC (opcode->opcode) != OPCODE_AC (insn[0]))
+	  continue;
+      }
+    else if (!ARC_SHORT (opcode->mask) && (insnLen == 4))
+      {
+	if (OPCODE (opcode->opcode) != OPCODE (insn[0]))
+	  continue;
+      }
+    else
+      continue;
+
+    if ((insn[0] ^ opcode->opcode) & opcode->mask)
+      continue;
+
+    if (!(opcode->cpu & isa_mask))
+      continue;
+
+    /* Possible candidate, check the operands.  */
+    for (opidx = opcode->operands; *opidx; opidx++)
+      {
+	int value;
+	const struct arc_operand *operand = &arc_operands[*opidx];
+
+	if (operand->flags & ARC_OPERAND_FAKE)
+	  continue;
+
+	if (operand->extract)
+	  value = (*operand->extract) (insn[0], &invalid);
+	else
+	  value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
+
+	/* Check for LIMM indicator.  If it is there, then make sure
+	   we pick the right format.  */
+	if (operand->flags & ARC_OPERAND_IR
+	    && !(operand->flags & ARC_OPERAND_LIMM))
+	  {
+	    if ((value == 0x3E && insnLen == 4)
+		|| (value == 0x1E && insnLen == 2))
+	      {
+		invalid = TRUE;
+		break;
+	      }
+	  }
+      }
+
+    /* Check the flags.  */
+    for (flgidx = opcode->flags; *flgidx; flgidx++)
+      {
+	/* Get a valid flag class.  */
+	const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
+	const unsigned *flgopridx;
+	int foundA = 0, foundB = 0;
+
+	for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
+	  {
+	    const struct arc_flag_operand *flg_operand =
+	      &arc_flag_operands[*flgopridx];
+	    unsigned int value;
+
+	    value = (insn[0] >> flg_operand->shift)
+	      & ((1 << flg_operand->bits) - 1);
+	    if (value == flg_operand->code)
+	      foundA = 1;
+	    if (value)
+	      foundB = 1;
+	  }
+	if (!foundA && foundB)
+	  {
+	    invalid = TRUE;
+	    break;
+	  }
+      }
+
+    if (invalid)
+      continue;
+
+    /* The instruction is valid.  */
+    return opcode;
+  } while (opcode->mask);
+
+  return NULL;
+}
+
 /* Disassemble ARC instructions.  */
 
 static int
@@ -111,15 +212,13 @@ print_insn_arc (bfd_vma memaddr,
   bfd_byte buffer[4];
   unsigned int lowbyte, highbyte;
   int status;
-  unsigned int i;
   int insnLen = 0;
   unsigned insn[2] = { 0, 0 };
   unsigned isa_mask;
   const unsigned char *opidx;
   const unsigned char *flgidx;
   const struct arc_opcode *opcode;
-  const char *instrName;
-  int flags;
+  const extInstruction_t *einsn;
   bfd_boolean need_comma;
   bfd_boolean open_braket;
   int size;
@@ -218,7 +317,7 @@ print_insn_arc (bfd_vma memaddr,
       return size;
     }
 
-  if (   (((buffer[lowbyte] & 0xf8) > 0x38)
+  if ((((buffer[lowbyte] & 0xf8) > 0x38)
        && ((buffer[lowbyte] & 0xf8) != 0x48))
       || ((info->mach == bfd_mach_arc_arcv2)
 	  && ((buffer[lowbyte] & 0xF8) == 0x48)) /* FIXME! ugly.  */
@@ -254,110 +353,40 @@ print_insn_arc (bfd_vma memaddr,
   info->disassembler_needs_relocs = TRUE;
 
   /* Find the first match in the opcode table.  */
-  for (i = 0; i < arc_num_opcodes; i++)
-    {
-      bfd_boolean invalid = FALSE;
+  opcode = find_format (arc_opcodes, insn, insnLen, isa_mask);
 
-      opcode = &arc_opcodes[i];
-
-      if (ARC_SHORT (opcode->mask) && (insnLen == 2))
-	{
-	  if (OPCODE_AC (opcode->opcode) != OPCODE_AC (insn[0]))
-	    continue;
-	}
-      else if (!ARC_SHORT (opcode->mask) && (insnLen == 4))
-	{
-	  if (OPCODE (opcode->opcode) != OPCODE (insn[0]))
-	    continue;
-	}
-      else
-	continue;
-
-      if ((insn[0] ^ opcode->opcode) & opcode->mask)
-	continue;
-
-      if (!(opcode->cpu & isa_mask))
-	continue;
-
-      /* Possible candidate, check the operands.  */
-      for (opidx = opcode->operands; *opidx; opidx++)
+  if (!opcode)
+    {
+      /* No instruction found.  Try the extensions.  */
+      einsn = arcExtMap_insn (OPCODE (insn[0]), insn[0]);
+      if (einsn)
 	{
-	  int value;
-	  const struct arc_operand *operand = &arc_operands[*opidx];
-
-	  if (operand->flags & ARC_OPERAND_FAKE)
-	    continue;
-
-	  if (operand->extract)
-	    value = (*operand->extract) (insn[0], &invalid);
-	  else
-	    value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
-
-	  /* Check for LIMM indicator.  If it is there, then make sure
-	     we pick the right format.  */
-	  if (operand->flags & ARC_OPERAND_IR
-	      && !(operand->flags & ARC_OPERAND_LIMM))
+	  const char *errmsg = NULL;
+	  opcode = arcExtMap_genOpcode (einsn, isa_mask, &errmsg);
+	  if (opcode == NULL)
 	    {
-	      if ((value == 0x3E && insnLen == 4)
-		  || (value == 0x1E && insnLen == 2))
-		{
-		  invalid = TRUE;
-		  break;
-		}
+	      (*info->fprintf_func) (info->stream,
+				     "An error occured while "
+				     "generating the extension instruction "
+				     "operations");
+	      return -1;
 	    }
-	}
 
-      /* Check the flags.  */
-      for (flgidx = opcode->flags; *flgidx; flgidx++)
+	  opcode = find_format (opcode, insn, insnLen, isa_mask);
+	  assert (opcode != NULL);
+	}
+      else
 	{
-	  /* Get a valid flag class.  */
-	  const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
-	  const unsigned *flgopridx;
-	  int foundA = 0, foundB = 0;
+	  if (insnLen == 2)
+	    (*info->fprintf_func) (info->stream, ".long %#04x", insn[0]);
+	  else
+	    (*info->fprintf_func) (info->stream, ".long %#08x", insn[0]);
 
-	  for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
-	    {
-	      const struct arc_flag_operand *flg_operand = &arc_flag_operands[*flgopridx];
-	      unsigned int value;
-
-	      value = (insn[0] >> flg_operand->shift) & ((1 << flg_operand->bits) - 1);
-	      if (value == flg_operand->code)
-		foundA = 1;
-	      if (value)
-		foundB = 1;
-	    }
-	  if (!foundA && foundB)
-	    {
-	      invalid = TRUE;
-	      break;
-	    }
+	  info->insn_type = dis_noninsn;
+	  return insnLen;
 	}
-
-      if (invalid)
-	continue;
-
-      /* The instruction is valid.  */
-      goto found;
     }
 
-  /* No instruction found.  Try the extenssions.  */
-  instrName = arcExtMap_instName (OPCODE (insn[0]), insn[0], &flags);
-  if (instrName)
-    {
-      opcode = &arc_opcodes[0];
-      (*info->fprintf_func) (info->stream, "%s", instrName);
-      goto print_flags;
-    }
-
-  if (insnLen == 2)
-    (*info->fprintf_func) (info->stream, ".long %#04x", insn[0]);
-  else
-    (*info->fprintf_func) (info->stream, ".long %#08x", insn[0]);
-
-  info->insn_type = dis_noninsn;
-  return insnLen;
-
- found:
   /* Print the mnemonic.  */
   (*info->fprintf_func) (info->stream, "%s", opcode->name);
 
@@ -382,7 +411,6 @@ print_insn_arc (bfd_vma memaddr,
 
   pr_debug ("%s: 0x%08x\n", opcode->name, opcode->opcode);
 
- print_flags:
   /* Now extract and print the flags.  */
   for (flgidx = opcode->flags; *flgidx; flgidx++)
     {
@@ -557,7 +585,9 @@ arc_get_disassembler (bfd *abfd)
 {
   /* Read the extenssion insns and registers, if any.  */
   build_ARC_extmap (abfd);
+#ifdef DEBUG
   dump_ARC_extmap ();
+#endif
 
   return print_insn_arc;
 }
diff --git a/opcodes/arc-ext.c b/opcodes/arc-ext.c
index 52f455639e0..45734a08329 100644
--- a/opcodes/arc-ext.c
+++ b/opcodes/arc-ext.c
@@ -27,7 +27,6 @@
 #include "elf/arc.h"
 #include "libiberty.h"
 
-
 /* This module provides support for extensions to the ARC processor
    architecture.  */
 
@@ -52,15 +51,6 @@
 
 /* These types define the information stored in the table.  */
 
-struct ExtInstruction
-{
-  char			 major;
-  char			 minor;
-  char			 flags;
-  char*			 name;
-  struct ExtInstruction* next;
-};
-
 struct ExtAuxRegister
 {
   long			 address;
@@ -141,6 +131,9 @@ create_map (unsigned char *block,
 	    insn->minor = minor;
 	    insn->flags = p[4];
 	    insn->next  = *bucket;
+	    insn->suffix = 0;
+	    insn->syntax = 0;
+	    insn->modsyn = 0;
 	    *bucket = insn;
 	    break;
 	  }
@@ -285,10 +278,8 @@ ExtReadWrite_image (enum ExtReadWrite val)
 
 /* Get the name of an extension instruction.  */
 
-const char *
-arcExtMap_instName (int opcode,
-		    int insn,
-		    int *flags)
+const extInstruction_t *
+arcExtMap_insn (int opcode, int insn)
 {
   /* Here the following tasks need to be done.  First of all, the
      opcode stored in the Extension Map is the real opcode.  However,
@@ -306,7 +297,7 @@ arcExtMap_instName (int opcode,
      then un-mangle using iiiiiI else iiiiii.  */
 
   unsigned char minor;
-  struct ExtInstruction *temp;
+  extInstruction_t *temp;
 
   /* 16-bit instructions.  */
   if (0x08 <= opcode && opcode <= 0x0b)
@@ -367,8 +358,7 @@ arcExtMap_instName (int opcode,
     {
       if ((temp->major == opcode) && (temp->minor == minor))
 	{
-	  *flags = temp->flags;
-	  return temp->name;
+	  return temp;
 	}
       temp = temp->next;
     }
@@ -459,6 +449,8 @@ build_ARC_extmap (bfd *text_bfd)
       }
 }
 
+/* Debug function used to dump the ARC information fount in arcextmap
+   sections.  */
 
 void
 dump_ARC_extmap (void)
@@ -480,8 +472,20 @@ dump_ARC_extmap (void)
 
 	for (insn = arc_extension_map.instructions[i];
 	     insn != NULL; insn = insn->next)
-	    printf ("INST: %d %d %x %s\n", insn->major, insn->minor,
-		    insn->flags, insn->name);
+	  {
+	    printf ("INST: 0x%02x 0x%02x ", insn->major, insn->minor);
+	    if (insn->flags & ARC_SYNTAX_2OP)
+	      printf ("SYNTAX_2OP");
+	    else if (insn->flags & ARC_SYNTAX_3OP)
+	      printf ("SYNTAX_3OP");
+	    else
+	      printf ("SYNTAX_UNK");
+
+	    if (insn->flags & 0x10)
+	      printf ("|MODIFIER");
+
+	    printf (" %s\n", insn->name);
+	  }
     }
 
     for (i = 0; i < NUM_EXT_CORE; i++)
@@ -497,3 +501,267 @@ dump_ARC_extmap (void)
 	if (arc_extension_map.condCodes[i])
 	    printf ("COND: %s\n", arc_extension_map.condCodes[i]);
 }
+
+/* For a given extension instruction generate the equivalent arc
+   opcode structure.  */
+
+struct arc_opcode *
+arcExtMap_genOpcode (const extInstruction_t *einsn,
+		     unsigned arc_target,
+		     const char **errmsg)
+{
+  struct arc_opcode *q, *arc_ext_opcodes = NULL;
+  const unsigned char *lflags_f;
+  const unsigned char *lflags_ccf;
+  int count;
+
+  /* Check for the class to see how many instructions we generate.  */
+  switch (einsn->flags & (ARC_SYNTAX_3OP | ARC_SYNTAX_2OP))
+    {
+    case ARC_SYNTAX_3OP:
+      count = (einsn->modsyn & ARC_OP1_MUST_BE_IMM) ? 10 : 20;
+      break;
+    case ARC_SYNTAX_2OP:
+      count = (einsn->flags & 0x10) ? 7 : 6;
+      break;
+    default:
+      count = 0;
+      break;
+    }
+
+  /* Allocate memory.  */
+  arc_ext_opcodes = (struct arc_opcode *)
+    xmalloc ((count + 1) * sizeof (*arc_ext_opcodes));
+
+  if (arc_ext_opcodes == NULL)
+    {
+      *errmsg = "Virtual memory exhausted";
+      return NULL;
+    }
+
+  /* Generate the patterns.  */
+  q = arc_ext_opcodes;
+
+  if (einsn->suffix)
+    {
+      lflags_f   = flags_none;
+      lflags_ccf = flags_none;
+    }
+  else
+    {
+      lflags_f   = flags_f;
+      lflags_ccf = flags_ccf;
+    }
+
+  if (einsn->suffix & ARC_SUFFIX_COND)
+    lflags_ccf = flags_cc;
+  if (einsn->suffix & ARC_SUFFIX_FLAG)
+    {
+      lflags_f   = flags_f;
+      lflags_ccf = flags_f;
+    }
+  if (einsn->suffix & (ARC_SUFFIX_FLAG | ARC_SUFFIX_COND))
+    lflags_ccf = flags_ccf;
+
+  if (einsn->flags & ARC_SYNTAX_2OP
+      && !(einsn->flags & 0x10))
+    {
+      /* Regular 2OP instruction.  */
+      if (einsn->suffix & ARC_SUFFIX_COND)
+	*errmsg = "Suffix SUFFIX_COND ignored";
+
+      INSERT_XOP (q, einsn->name,
+		  INSN2OP_BC (einsn->major, einsn->minor), MINSN2OP_BC,
+		  arc_target, arg_32bit_rbrc, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN2OP_0C (einsn->major, einsn->minor), MINSN2OP_0C,
+		  arc_target, arg_32bit_zarc, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN2OP_BU (einsn->major, einsn->minor), MINSN2OP_BU,
+		  arc_target, arg_32bit_rbu6, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN2OP_0U (einsn->major, einsn->minor), MINSN2OP_0U,
+		  arc_target, arg_32bit_zau6, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN2OP_BL (einsn->major, einsn->minor), MINSN2OP_BL,
+		  arc_target, arg_32bit_rblimm, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN2OP_0L (einsn->major, einsn->minor), MINSN2OP_0L,
+		  arc_target, arg_32bit_zalimm, lflags_f);
+    }
+  else if (einsn->flags & (0x10 | ARC_SYNTAX_2OP))
+    {
+      /* This is actually a 3OP pattern.  The first operand is
+	 immplied and is set to zero.  */
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_0BC (einsn->major, einsn->minor),  MINSN3OP_0BC,
+		  arc_target, arg_32bit_rbrc, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_0BU (einsn->major, einsn->minor),  MINSN3OP_0BU,
+		  arc_target, arg_32bit_rbu6, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_0BL (einsn->major, einsn->minor),  MINSN3OP_0BL,
+		  arc_target, arg_32bit_rblimm, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_C0LC (einsn->major, einsn->minor), MINSN3OP_C0LC,
+		  arc_target, arg_32bit_limmrc, lflags_ccf);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_C0LU (einsn->major, einsn->minor), MINSN3OP_C0LU,
+		  arc_target, arg_32bit_limmu6, lflags_ccf);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_0LS (einsn->major, einsn->minor),  MINSN3OP_0LS,
+		  arc_target, arg_32bit_limms12, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_C0LL (einsn->major, einsn->minor), MINSN3OP_C0LL,
+		  arc_target, arg_32bit_limmlimm, lflags_ccf);
+    }
+  else if (einsn->flags & ARC_SYNTAX_3OP
+	   && !(einsn->modsyn & ARC_OP1_MUST_BE_IMM))
+    {
+      /* Regular 3OP instruction.  */
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_ABC (einsn->major, einsn->minor),  MINSN3OP_ABC,
+		  arc_target, arg_32bit_rarbrc, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_0BC (einsn->major, einsn->minor),  MINSN3OP_0BC,
+		  arc_target, arg_32bit_zarbrc, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_CBBC (einsn->major, einsn->minor), MINSN3OP_CBBC,
+		  arc_target, arg_32bit_rbrbrc, lflags_ccf);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_ABU (einsn->major, einsn->minor),  MINSN3OP_ABU,
+		  arc_target, arg_32bit_rarbu6, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_0BU (einsn->major, einsn->minor),  MINSN3OP_0BU,
+		  arc_target, arg_32bit_zarbu6, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_CBBU (einsn->major, einsn->minor), MINSN3OP_CBBU,
+		  arc_target, arg_32bit_rbrbu6, lflags_ccf);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_BBS (einsn->major, einsn->minor),  MINSN3OP_BBS,
+		  arc_target, arg_32bit_rbrbs12, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_ALC (einsn->major, einsn->minor),  MINSN3OP_ALC,
+		  arc_target, arg_32bit_ralimmrc, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_ABL (einsn->major, einsn->minor),  MINSN3OP_ABL,
+		  arc_target, arg_32bit_rarblimm, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_0LC (einsn->major, einsn->minor),  MINSN3OP_0LC,
+		  arc_target, arg_32bit_zalimmrc, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_0BL (einsn->major, einsn->minor),  MINSN3OP_0BL,
+		  arc_target, arg_32bit_zarblimm, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_C0LC (einsn->major, einsn->minor), MINSN3OP_C0LC,
+		  arc_target, arg_32bit_zalimmrc, lflags_ccf);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_CBBL (einsn->major, einsn->minor), MINSN3OP_CBBL,
+		  arc_target, arg_32bit_rbrblimm, lflags_ccf);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_ALU (einsn->major, einsn->minor),  MINSN3OP_ALU,
+		  arc_target, arg_32bit_ralimmu6, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_0LU (einsn->major, einsn->minor),  MINSN3OP_0LU,
+		  arc_target, arg_32bit_zalimmu6, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_C0LU (einsn->major, einsn->minor), MINSN3OP_C0LU,
+		  arc_target, arg_32bit_zalimmu6, lflags_ccf);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_0LS (einsn->major, einsn->minor),  MINSN3OP_0LS,
+		  arc_target, arg_32bit_zalimms12, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_ALL (einsn->major, einsn->minor),  MINSN3OP_ALL,
+		  arc_target, arg_32bit_ralimmlimm, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_0LL (einsn->major, einsn->minor),  MINSN3OP_0LL,
+		  arc_target, arg_32bit_zalimmlimm, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_C0LL (einsn->major, einsn->minor), MINSN3OP_C0LL,
+		  arc_target, arg_32bit_zalimmlimm, lflags_ccf);
+    }
+  else if (einsn->flags & ARC_SYNTAX_3OP)
+    {
+      /* 3OP instruction which accepts only zero as first
+	 argument.  */
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_0BC (einsn->major, einsn->minor),  MINSN3OP_0BC,
+		  arc_target, arg_32bit_zarbrc, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_0BU (einsn->major, einsn->minor),  MINSN3OP_0BU,
+		  arc_target, arg_32bit_zarbu6, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_0LC (einsn->major, einsn->minor),  MINSN3OP_0LC,
+		  arc_target, arg_32bit_zalimmrc, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_0BL (einsn->major, einsn->minor),  MINSN3OP_0BL,
+		  arc_target, arg_32bit_zarblimm, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_C0LC (einsn->major, einsn->minor), MINSN3OP_C0LC,
+		  arc_target, arg_32bit_zalimmrc, lflags_ccf);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_0LU (einsn->major, einsn->minor),  MINSN3OP_0LU,
+		  arc_target, arg_32bit_zalimmu6, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_C0LU (einsn->major, einsn->minor), MINSN3OP_C0LU,
+		  arc_target, arg_32bit_zalimmu6, lflags_ccf);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_0LS (einsn->major, einsn->minor),  MINSN3OP_0LS,
+		  arc_target, arg_32bit_zalimms12, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_0LL (einsn->major, einsn->minor),  MINSN3OP_0LL,
+		  arc_target, arg_32bit_zalimmlimm, lflags_f);
+
+      INSERT_XOP (q, einsn->name,
+		  INSN3OP_C0LL (einsn->major, einsn->minor), MINSN3OP_C0LL,
+		  arc_target, arg_32bit_zalimmlimm, lflags_ccf);
+    }
+  else
+    {
+      *errmsg = "Unknown syntax";
+      return NULL;
+    }
+
+  /* End marker.  */
+  memset (q, 0, sizeof (*arc_ext_opcodes));
+
+  return arc_ext_opcodes;
+}
diff --git a/opcodes/arc-ext.h b/opcodes/arc-ext.h
index 9c2f4b7374e..fcce7e2bd4e 100644
--- a/opcodes/arc-ext.h
+++ b/opcodes/arc-ext.h
@@ -39,13 +39,14 @@
 #ifndef ARC_EXTENSIONS_H
 #define ARC_EXTENSIONS_H
 
+#include "opcode/arc.h"
+
 #define IGNORE_FIRST_OPD 1
 
 /* Define this if we do not want to encode instructions based on the
    ARCompact Programmer's Reference.  */
 #define UNMANGLED
 
-
 /* This defines the kinds of extensions which may be read from the
    ections in the executable files.  */
 enum ExtOperType
@@ -63,7 +64,6 @@ enum ExtOperType
   EXT_CORE_REGISTER_CLASS    = 9
 };
 
-
 enum ExtReadWrite
 {
   REG_INVALID,
@@ -72,6 +72,48 @@ enum ExtReadWrite
   REG_READWRITE
 };
 
+/* Macro used when generating the patterns for an extension
+   instruction.  */
+#define INSERT_XOP(OP, NAME, CODE, MASK, CPU, ARG, FLG)	\
+  do {							\
+    (OP)->name   = NAME;				\
+    (OP)->opcode = CODE;				\
+    (OP)->mask   = MASK;				\
+    (OP)->cpu    = CPU;					\
+    (OP)->class  = ARITH;				\
+    (OP)->subclass = NONE;				\
+    memcpy ((OP)->operands, (ARG), MAX_INSN_ARGS);	\
+    memcpy ((OP)->flags, (FLG), MAX_INSN_FLGS);		\
+    (OP++);						\
+  } while (0)
+
+/* Typedef to hold the extension instruction definition.  */
+typedef struct ExtInstruction
+{
+  /* Name.  */
+  char *name;
+
+  /* Major opcode.  */
+  char major;
+
+  /* Minor(sub) opcode.  */
+  char minor;
+
+  /* Flags, holds the syntax class and modifiers.  */
+  char flags;
+
+  /* Syntax class.  Use by assembler.  */
+  unsigned char syntax;
+
+  /* Syntax class modifier.  Used by assembler.  */
+  unsigned char modsyn;
+
+  /* Suffix class.  Used by assembler.  */
+  unsigned char suffix;
+
+  /* Pointer to the next extension instruction.  */
+  struct ExtInstruction* next;
+} extInstruction_t;
 
 /* Constructor function.  */
 extern void build_ARC_extmap (bfd *);
@@ -81,7 +123,10 @@ extern enum ExtReadWrite arcExtMap_coreReadWrite (int);
 extern const char * arcExtMap_coreRegName (int);
 extern const char * arcExtMap_auxRegName (long);
 extern const char * arcExtMap_condCodeName (int);
-extern const char * arcExtMap_instName (int, int, int *);
+extern const extInstruction_t *arcExtMap_insn (int, int);
+extern struct arc_opcode *arcExtMap_genOpcode (const extInstruction_t *,
+					       unsigned arc_target,
+					       const char **errmsg);
 
 /* Dump function (for debugging).  */
 extern void dump_ARC_extmap (void);
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index d667a78d65b..028b80bfb5f 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -1136,6 +1136,11 @@ const struct arc_flag_class arc_flag_classes[] =
 
 };
 
+const unsigned char flags_none[] = { 0 };
+const unsigned char flags_f[]    = { C_F };
+const unsigned char flags_cc[]   = { C_CC };
+const unsigned char flags_ccf[]  = { C_CC, C_F };
+
 /* The operands table.
 
    The format of the operands table is:
@@ -1499,6 +1504,39 @@ const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
 const unsigned arc_Toperand = FKT_T;
 const unsigned arc_NToperand = FKT_NT;
 
+const unsigned char arg_none[]		 = { 0 };
+const unsigned char arg_32bit_rarbrc[]	 = { RA, RB, RC };
+const unsigned char arg_32bit_zarbrc[]	 = { ZA, RB, RC };
+const unsigned char arg_32bit_rbrbrc[]	 = { RB, RBdup, RC };
+const unsigned char arg_32bit_rarbu6[]	 = { RA, RB, UIMM6_20 };
+const unsigned char arg_32bit_zarbu6[]	 = { ZA, RB, UIMM6_20 };
+const unsigned char arg_32bit_rbrbu6[]	 = { RB, RBdup, UIMM6_20 };
+const unsigned char arg_32bit_rbrbs12[]	 = { RB, RBdup, SIMM12_20 };
+const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC };
+const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM };
+const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC };
+const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM };
+
+const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM };
+const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 };
+const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 };
+
+const unsigned char arg_32bit_zalimms12[]  = { ZA, LIMM, SIMM12_20 };
+const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup };
+const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup };
+
+const unsigned char arg_32bit_rbrc[]   = { RB, RC };
+const unsigned char arg_32bit_zarc[]   = { ZA, RC };
+const unsigned char arg_32bit_rbu6[]   = { RB, UIMM6_20 };
+const unsigned char arg_32bit_zau6[]   = { ZA, UIMM6_20 };
+const unsigned char arg_32bit_rblimm[] = { RB, LIMM };
+const unsigned char arg_32bit_zalimm[] = { ZA, LIMM };
+
+const unsigned char arg_32bit_limmrc[]   = { LIMM, RC };
+const unsigned char arg_32bit_limmu6[]   = { LIMM, UIMM6_20 };
+const unsigned char arg_32bit_limms12[]  = { LIMM, SIMM12_20 };
+const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup };
+
 /* The opcode table.
 
    The format of the opcode table is:
@@ -1539,9 +1577,9 @@ const struct arc_opcode arc_opcodes[] =
 #include "arc-tbl.h"
 #include "arc-nps400-tbl.h"
 #include "arc-ext-tbl.h"
-};
 
-const unsigned arc_num_opcodes = ARRAY_SIZE (arc_opcodes);
+  { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } }
+};
 
 /* List with special cases instructions and the applicable flags.  */
 const struct arc_flag_special arc_flag_special_cases[] =