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| author | Andreas Krebbel <Andreas.Krebbel@de.ibm.com> | 2010-10-11 11:56:53 +0000 |
|---|---|---|
| committer | Andreas Krebbel <Andreas.Krebbel@de.ibm.com> | 2010-10-11 11:56:53 +0000 |
| commit | a3ec2691d043b53f9e77cbfc854f8473c090d2e6 (patch) | |
| tree | f28b5163940d152efbd9dec3e59b901cee48f9b5 /opcodes | |
| parent | b8f9044ba97e588961252e48aa01348d5406c6e1 (diff) | |
| download | binutils-gdb-a3ec2691d043b53f9e77cbfc854f8473c090d2e6.tar.gz | |
2010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* s390-opc.c: Make the instruction masks for the load/store on
condition instructions to cover the condition code mask as well.
* s390-opc.txt: lgoc -> locg and stgoc -> stocg.
2010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* gas/s390/zarch-z196.d: Adjust the load/store on condition
instructions.
* gas/s390/zarch-z196.s: Likewise.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/s390-opc.c | 2 | ||||
| -rw-r--r-- | opcodes/s390-opc.txt | 8 |
3 files changed, 11 insertions, 5 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 5336e46a5d3..8581095b614 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> + + * s390-opc.c: Make the instruction masks for the load/store on + condition instructions to cover the condition code mask as well. + * s390-opc.txt: lgoc -> locg and stgoc -> stocg. + 2010-10-11 Jan Kratochvil <jan.kratochvil@redhat.com> Jiang Jilin <freephp@gmail.com> diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c index fea838e7395..2f1487d5696 100644 --- a/opcodes/s390-opc.c +++ b/opcodes/s390-opc.c @@ -426,7 +426,7 @@ const struct s390_operand s390_operands[] = #define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RSY_RDRM { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -#define MASK_RSY_RDR0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSY_RDR0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } #define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } #define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } #define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt index 9393ba41011..e9b6ffc4da5 100644 --- a/opcodes/s390-opc.txt +++ b/opcodes/s390-opc.txt @@ -1008,12 +1008,12 @@ b9e2 locgr RRF_U0RR "load on condition 64 bit" z196 zarch b9e200000000 locgr*16 RRF_00RR "load on condition 64 bit" z196 zarch eb00000000f2 loc RSY_RDRM "load on condition 32 bit" z196 zarch eb00000000f2 loc*12 RSY_RDR0 "load on condition 32 bit" z196 zarch -eb00000000e2 lgoc RSY_RDRM "load on condition 64 bit" z196 zarch -eb00000000e2 lgoc*12 RSY_RDR0 "load on condition 64 bit" z196 zarch +eb00000000e2 locg RSY_RDRM "load on condition 64 bit" z196 zarch +eb00000000e2 locg*12 RSY_RDR0 "load on condition 64 bit" z196 zarch eb00000000f3 stoc RSY_RDRM "store on condition 32 bit" z196 zarch eb00000000f3 stoc*12 RSY_RDR0 "store on condition 32 bit" z196 zarch -eb00000000e3 stgoc RSY_RDRM "store on condition 64 bit" z196 zarch -eb00000000e3 stgoc*12 RSY_RDR0 "store on condition 64 bit" z196 zarch +eb00000000e3 stocg RSY_RDRM "store on condition 64 bit" z196 zarch +eb00000000e3 stocg*12 RSY_RDR0 "store on condition 64 bit" z196 zarch b9f8 ark RRF_R0RR2 "add 3 operands 32 bit" z196 zarch b9e8 agrk RRF_R0RR2 "add 3 operands 64 bit" z196 zarch ec00000000d8 ahik RIE_RRI0 "add immediate 3 operands 32 bit" z196 zarch |