diff options
| author | Claudiu Zissulescu <claziss@synopsys.com> | 2017-04-25 17:07:00 +0200 |
|---|---|---|
| committer | claziss <claziss@synopsys.com> | 2017-04-25 17:07:00 +0200 |
| commit | 126124cc0f3f0417913bfd84d83e4e525b6facf9 (patch) | |
| tree | 3b25064e723e5cc5c9a7d5053333f31413570795 /opcodes | |
| parent | be6a24d8eabdbeef32a9d79e81307af4491fcf56 (diff) | |
| download | binutils-gdb-126124cc0f3f0417913bfd84d83e4e525b6facf9.tar.gz | |
[ARC] Enhance enter/leave mnemonics.
enter/leave mnemonics are enhanced to not only accept register ranges
but also single register (i.e., r13) or even no GPR register at all.
gas/
2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/leave_enter.d: Update test.
* testsuite/gas/arc/leave_enter.s: Likewise.
opcodes/
2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
* arc-opc.c (insert_r13el): New function.
(R13_EL): Define.
* arc-tbl.h: Add new enter/leave variants.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 7 | ||||
| -rw-r--r-- | opcodes/arc-dis.c | 19 | ||||
| -rw-r--r-- | opcodes/arc-opc.c | 20 | ||||
| -rw-r--r-- | opcodes/arc-tbl.h | 2 |
4 files changed, 44 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 7076de5ca25..b9d67d2745f 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,12 @@ 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> + * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics. + * arc-opc.c (insert_r13el): New function. + (R13_EL): Define. + * arc-tbl.h: Add new enter/leave variants. + +2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> + * arc-tbl.h: Reorder NOP entry to be before MOV instructions. 2017-04-25 Maciej W. Rozycki <macro@imgtec.com> diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c index 4beca689c39..6fb030e5dbe 100644 --- a/opcodes/arc-dis.c +++ b/opcodes/arc-dis.c @@ -1208,9 +1208,22 @@ print_insn_arc (bfd_vma memaddr, if (operand->flags & ARC_OPERAND_TRUNCATE && !(operand->flags & ARC_OPERAND_ALIGNED32) && !(operand->flags & ARC_OPERAND_ALIGNED16) - && value > 0 && value <= 14) - (*info->fprintf_func) (info->stream, "r13-%s", - regnames[13 + value - 1]); + && value >= 0 && value <= 14) + { + switch (value) + { + case 0: + need_comma = FALSE; + break; + case 1: + (*info->fprintf_func) (info->stream, "r13"); + break; + default: + (*info->fprintf_func) (info->stream, "r13-%s", + regnames[13 + value - 1]); + break; + } + } else { const char *rname = get_auxreg (opcode, value, isa_mask); diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c index 41cd0375d28..c266f4f1ac9 100644 --- a/opcodes/arc-opc.c +++ b/opcodes/arc-opc.c @@ -546,6 +546,21 @@ extract_rrange (unsigned long long insn, } static unsigned long long +insert_r13el (unsigned long long insn, + long long int value, + const char **errmsg) +{ + if (value != 13) + { + *errmsg = _("Invalid register number, should be fp"); + return insn; + } + + insn |= 0x02; + return insn; +} + +static unsigned long long insert_fpel (unsigned long long insn, long long value, const char ** errmsg) @@ -1876,7 +1891,10 @@ const struct arc_operand arc_operands[] = #define RRANGE_EL (ZA + 1) { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE, insert_rrange, extract_rrange}, -#define FP_EL (RRANGE_EL + 1) +#define R13_EL (RRANGE_EL + 1) + { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, + insert_r13el, extract_rrange }, +#define FP_EL (R13_EL + 1) { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, insert_fpel, extract_fpel }, #define BLINK_EL (FP_EL + 1) diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h index 6b8a589cfac..826b2ce97cc 100644 --- a/opcodes/arc-tbl.h +++ b/opcodes/arc-tbl.h @@ -6192,6 +6192,7 @@ /* enter_s u6 110000UU111uuuu0. */ { "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ENTER, CD1, { BRAKET, RRANGE_EL, FP_EL, BLINK_EL, BRAKETdup }, { 0 }}, +{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ENTER, CD1, { BRAKET, R13_EL, FP_EL, BLINK_EL, BRAKETdup }, { 0 }}, { "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ENTER, CD1, { UIMM6_11_S }, { 0 }}, /* ex<.di> b,c 00100bbb00101111DBBBCCCCCC001100. */ @@ -8230,6 +8231,7 @@ /* leave_s u7 11000UUU110uuuu0. */ { "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LEAVE, CD1, { BRAKET, RRANGE_EL, FP_EL, BLINK_EL, PCL_EL, BRAKETdup }, { 0 }}, +{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LEAVE, CD1, { BRAKET, R13_EL, FP_EL, BLINK_EL, PCL_EL, BRAKETdup }, { 0 }}, { "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LEAVE, CD1, { UIMM7_11_S }, { 0 }}, /* llock<.di> b,c 00100bbb00101111DBBBCCCCCC010000. */ |