diff options
| author | Stan Shebs <shebs@codesourcery.com> | 1999-04-16 01:34:07 +0000 |
|---|---|---|
| committer | Stan Shebs <shebs@codesourcery.com> | 1999-04-16 01:34:07 +0000 |
| commit | 071ea11e85eb9d529cc5eb3d35f6247466a21b99 (patch) | |
| tree | 5deda65b8d7b04d1f4cbc534c3206d328e1267ec /opcodes | |
| parent | 1730ec6b1848f0f32154277f788fb29f88d8475b (diff) | |
| download | binutils-gdb-071ea11e85eb9d529cc5eb3d35f6247466a21b99.tar.gz | |
Initial creation of sourceware repository
Diffstat (limited to 'opcodes')
80 files changed, 0 insertions, 66365 deletions
diff --git a/opcodes/.Sanitize b/opcodes/.Sanitize deleted file mode 100644 index 2a03cc199b7..00000000000 --- a/opcodes/.Sanitize +++ /dev/null @@ -1,537 +0,0 @@ -# .Sanitize for devo/opcodes. - -# Each directory to survive its way into a release will need a file -# like this one called "./.Sanitize". All keyword lines must exist, -# and must exist in the order specified by this file. Each directory -# in the tree will be processed, top down, in the following order. - -# Hash started lines like this one are comments and will be deleted -# before anything else is done. Blank lines will also be squashed -# out. - -# The lines between the "Do-first:" line and the "Things-to-keep:" -# line are executed as a /bin/sh shell script before anything else is -# done in this directory. - -Do-first: - -cygnus_files="cgen.sh cgen-asm.in cgen-dis.in cgen-ibld.in" - -if ( echo $* | grep keep\-cygnus > /dev/null ) ; then - keep_these_too="${cygnus_files} ${keep_these_too}" -else - lose_these_too="${cygnus_files} ${lose_these_too}" -fi - -tic80_files="tic80-opc.c tic80-dis.c" - -if ( echo $* | grep keep\-tic80 > /dev/null ) ; then - keep_these_too="${tic80_files} ${keep_these_too}" -else - lose_these_too="${tic80_files} ${lose_these_too}" -fi - -sky_files="dvp-opc.c dvp-dis.c" - -if ( echo $* | grep keep\-sky > /dev/null ) ; then - keep_these_too="${sky_files} ${keep_these_too}" -else - lose_these_too="${sky_files} ${lose_these_too}" -fi - -# All files listed between the "Things-to-keep:" line and the -# "Files-to-sed:" line will be kept. All other files will be removed. -# Directories listed in this section will have their own Sanitize -# called. Directories not listed will be removed in their entirety -# with rm -rf. - -Things-to-keep: - -ChangeLog -Makefile.am -Makefile.in -acinclude.m4 -aclocal.m4 -alpha-dis.c -alpha-opc.c -arc-dis.c -arc-opc.c -arm-dis.c -arm-opc.h -a29k-dis.c -cgen-asm.c -cgen-dis.c -cgen-opc.c -config.in -configure -configure.bat -configure.in -d10v-dis.c -d10v-opc.c -d30v-dis.c -d30v-opc.c -dep-in.sed -dis-buf.c -disassemble.c -fr30-asm.c -fr30-desc.c -fr30-desc.h -fr30-dis.c -fr30-ibld.c -fr30-opc.c -fr30-opc.h -h8300-dis.c -h8500-dis.c -h8500-opc.h -hppa-dis.c -i386-dis.c -i960-dis.c -m32r-asm.c -m32r-desc.c -m32r-desc.h -m32r-dis.c -m32r-ibld.c -m32r-opc.c -m32r-opc.h -m32r-opinst.c -m68k-dis.c -m68k-opc.c -m88k-dis.c -makefile.vms -mips-dis.c -mips-opc.c -mips16-opc.c -m10200-dis.c -m10200-opc.c -m10300-dis.c -m10300-opc.c -mpw-config.in -mpw-make.sed -ns32k-dis.c -opintl.h -po -ppc-dis.c -ppc-opc.c -sh-opc.h -sh-dis.c -sparc-dis.c -sparc-opc.c -stamp-h.in -sysdep.h -tic30-dis.c -vax-dis.c -w65-dis.c -w65-opc.h -v850-opc.c -v850-dis.c -z8k-dis.c -z8k-opc.h -z8kgen.c - -Things-to-lose: - -Do-last: -never_files="Makefile.am Makefile.in" -for i in $never_files ; do - if test ! -d $i && (grep sanitize-never $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Removing traces of \"never\" from $i... - fi - cp $i new - sed '/start\-sanitize\-never/,/end\-sanitize\-never/d' < $i > new - if [ -n "${safe}" -a ! -f .Recover/$i ] ; then - if [ -n "${verbose}" ] ; then - echo Caching $i in .Recover... - fi - mv $i .Recover - fi - mv new $i - fi -done - -cygnus_files="ChangeLog Makefile.am Makefile.in configure.in configure m10300-opc.c m10300-dis.c" -if ( echo $* | grep keep\-cygnus > /dev/null ) ; then - for i in $cygnus_files ; do - if test ! -d $i && (grep sanitize-cygnus $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Keeping cygnus stuff in $i - fi - fi - done -else - for i in $cygnus_files ; do - if test ! -d $i && (grep sanitize-cygnus $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Removing traces of \"cygnus\" from $i... - fi - cp $i new - sed '/start\-sanitize\-cygnus/,/end-\sanitize\-cygnus/d' < $i > new - if [ -n "${safe}" -a ! -f .Recover/$i ] ; then - if [ -n "${verbose}" ] ; then - echo Caching $i in .Recover... - fi - mv $i .Recover - fi - mv new $i - fi - done -fi - -r5900_files="ChangeLog mips-opc.c mips-dis.c Makefile.am Makefile.in" -if ( echo $* | grep keep\-r5900 > /dev/null ) ; then - for i in $r5900_files ; do - if test ! -d $i && (grep sanitize-r5900 $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Keeping r5900 stuff in $i - fi - fi - done -else - for i in $r5900_files ; do - if test ! -d $i && (grep sanitize-r5900 $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Removing traces of \"r5900\" from $i... - fi - cp $i new - sed '/start\-sanitize\-r5900/,/end-\sanitize\-r5900/d' < $i > new - if [ -n "${safe}" -a ! -f .Recover/$i ] ; then - if [ -n "${verbose}" ] ; then - echo Caching $i in .Recover... - fi - mv $i .Recover - fi - mv new $i - fi - done -fi - -vr4320_files="ChangeLog mips-opc.c mips-dis.c" -if ( echo $* | grep keep\-vr4320 > /dev/null ) ; then - for i in $vr4320_files ; do - if test ! -d $i && (grep sanitize-vr4320 $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Keeping vr4320 stuff in $i - fi - fi - done -else - for i in $vr4320_files ; do - if test ! -d $i && (grep sanitize-vr4320 $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Removing traces of \"vr4320\" from $i... - fi - cp $i new - sed '/start\-sanitize\-vr4320/,/end-\sanitize\-vr4320/d' < $i > new - if [ -n "${safe}" -a ! -f .Recover/$i ] ; then - if [ -n "${verbose}" ] ; then - echo Caching $i in .Recover... - fi - mv $i .Recover - fi - mv new $i - fi - done -fi - -vr4xxx_files="ChangeLog mips-opc.c mips-dis.c" -if ( echo $* | grep keep\-vr4xxx > /dev/null ) ; then - for i in $vr4xxx_files ; do - if test ! -d $i && (grep sanitize-vr4xxx $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Keeping vr4xxx stuff in $i - fi - fi - done -else - for i in $vr4xxx_files ; do - if test ! -d $i && (grep sanitize-vr4xxx $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Removing traces of \"vr4xxx\" from $i... - fi - cp $i new - sed '/start\-sanitize\-vr4xxx/,/end-\sanitize\-vr4xxx/d' < $i > new - if [ -n "${safe}" -a ! -f .Recover/$i ] ; then - if [ -n "${verbose}" ] ; then - echo Caching $i in .Recover... - fi - mv $i .Recover - fi - mv new $i - fi - done -fi - -cygnus_files="ChangeLog mips-opc.c mips-dis.c" -if ( echo $* | grep keep\-cygnus > /dev/null ) ; then - for i in $cygnus_files ; do - if test ! -d $i && (grep sanitize-cygnus $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Keeping cygnus stuff in $i - fi - fi - done -else - for i in $cygnus_files ; do - if test ! -d $i && (grep sanitize-cygnus $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Removing traces of \"cygnus\" from $i... - fi - cp $i new - sed '/start\-sanitize\-cygnus/,/end-\sanitize\-cygnus/d' < $i > new - if [ -n "${safe}" -a ! -f .Recover/$i ] ; then - if [ -n "${verbose}" ] ; then - echo Caching $i in .Recover... - fi - mv $i .Recover - fi - mv new $i - fi - done -fi - -tx19_files="ChangeLog mips16-opc.c mips-dis.c" -if ( echo $* | grep keep\-tx19 > /dev/null ) ; then - for i in $tx19_files ; do - if test ! -d $i && (grep sanitize-tx19 $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Keeping tx19 stuff in $i - fi - fi - done -else - for i in $tx19_files ; do - if test ! -d $i && (grep sanitize-tx19 $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Removing traces of \"tx19\" from $i... - fi - cp $i new - sed '/start\-sanitize\-tx19/,/end-\sanitize\-tx19/d' < $i > new - if [ -n "${safe}" -a ! -f .Recover/$i ] ; then - if [ -n "${verbose}" ] ; then - echo Caching $i in .Recover... - fi - mv $i .Recover - fi - mv new $i - fi - done -fi - -tx49_files="ChangeLog mips-opc.c mips-dis.c" -if ( echo $* | grep keep\-tx49 > /dev/null ) ; then - for i in $tx49_files ; do - if test ! -d $i && (grep sanitize-tx49 $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Keeping tx49 stuff in $i - fi - fi - done -else - for i in $tx49_files ; do - if test ! -d $i && (grep sanitize-tx49 $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Removing traces of \"tx49\" from $i... - fi - cp $i new - sed '/start\-sanitize\-tx49/,/end-\sanitize\-tx49/d' < $i > new - if [ -n "${safe}" -a ! -f .Recover/$i ] ; then - if [ -n "${verbose}" ] ; then - echo Caching $i in .Recover... - fi - mv $i .Recover - fi - mv new $i - fi - done -fi - -tic80_files="ChangeLog Makefile.in Makefile.am configure.in configure disassemble.c" -if ( echo $* | grep keep\-tic80 > /dev/null ) ; then - for i in $tic80_files ; do - if test ! -d $i && (grep sanitize-tic80 $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Keeping tic80 stuff in $i - fi - fi - done -else - for i in $tic80_files ; do - if test ! -d $i && (grep sanitize-tic80 $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Removing traces of \"tic80\" from $i... - fi - cp $i new - sed '/start\-sanitize\-tic80/,/end-\sanitize\-tic80/d' < $i > new - if [ -n "${safe}" -a ! -f .Recover/$i ] ; then - if [ -n "${verbose}" ] ; then - echo Caching $i in .Recover... - fi - mv $i .Recover - fi - mv new $i - fi - done -fi - -coldfire_files="ChangeLog m68k-opc.c" -if ( echo $* | grep keep\-coldfire > /dev/null ) ; then - for i in $coldfire_files ; do - if test ! -d $i && (grep sanitize-coldfire $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Keeping coldfire stuff in $i - fi - fi - done -else - for i in $coldfire_files ; do - if test ! -d $i && (grep sanitize-coldfire $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Removing traces of \"coldfire\" from $i... - fi - cp $i new - sed '/start\-sanitize\-coldfire/,/end-\sanitize\-coldfire/d' < $i > new - if [ -n "${safe}" -a ! -f .Recover/$i ] ; then - if [ -n "${verbose}" ] ; then - echo Caching $i in .Recover... - fi - mv $i .Recover - fi - mv new $i - fi - done -fi - -sky_files="ChangeLog Makefile.in Makefile.am configure.in configure disassemble.c mips-dis.c" -if ( echo $* | grep keep\-sky > /dev/null ) ; then - for i in $sky_files ; do - if test ! -d $i && (grep sanitize-sky $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Keeping sky stuff in $i - fi - fi - done -else - for i in $sky_files ; do - if test ! -d $i && (grep sanitize-sky $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Removing traces of \"sky\" from $i... - fi - cp $i new - sed '/start\-sanitize\-sky/,/end-\sanitize\-sky/d' < $i > new - if [ -n "${safe}" -a ! -f .Recover/$i ] ; then - if [ -n "${verbose}" ] ; then - echo Caching $i in .Recover... - fi - mv $i .Recover - fi - mv new $i - fi - done -fi - -# N.B. m32rx files are now sanitized with keep-cygnus. -# After 99r1, the sanitization will be removed. -# N.B. there is special sanitization going on here to remove PIPE_[A-Z]*. - -cygnus_files="ChangeLog m32r-desc.c m32r-desc.h m32r-opc.c m32r-opc.h m32r-dis.c m32r-asm.c m32r-ibld.c m32r-opinst.c" -if ( echo $* | grep keep\-cygnus > /dev/null ) ; then - for i in $cygnus_files ; do - if test -f $i && (grep sanitize-cygnus $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Keeping cygnus stuff in $i - fi - fi - done -else - for i in $cygnus_files ; do - if test -f $i && (grep sanitize-cygnus $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Removing traces of \"cygnus\" from $i... - fi - cp $i new - # The PIPE sanitization will be much cleaner with redact. - sed -e '/start\-sanitize\-cygnus/,/end\-sanitize\-cygnus/d' \ - -e 's/, PIPE_[A-Z]*//g' < $i > new - if [ -n "${safe}" -a ! -f .Recover/$i ] ; then - if [ -n "${verbose}" ] ; then - echo Caching $i in .Recover... - fi - mv $i .Recover - fi - mv new $i - fi - done -fi - -nortel_ppc750_files="ChangeLog ppc-opc.c" -if ( echo $* | grep keep\-nortel-ppc750 > /dev/null ) ; then - for i in $nortel_ppc750_files ; do - if test -f $i && (grep sanitize-nortel-ppc750 $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Keeping nortel-ppc750 stuff in $i - fi - fi - done -else - for i in $nortel_ppc750_files ; do - if test -f $i && (grep sanitize-nortel-ppc750 $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Removing traces of \"nortel-ppc750\" from $i... - fi - cp $i new - # The PIPE sanitization will be much cleaner with redact. - sed -e '/start\-sanitize\-nortel-ppc750/,/end\-sanitize\-nortel-ppc750/d' \ - -e 's/, PIPE_[A-Z]*//g' < $i > new - if [ -n "${safe}" -a ! -f .Recover/$i ] ; then - if [ -n "${verbose}" ] ; then - echo Caching $i in .Recover... - fi - mv $i .Recover - fi - mv new $i - fi - done -fi - -for i in *; do - if test ! -d $i && (grep sanitize $i > /dev/null) ; then - echo '***' Some mentions of Sanitize are still left in opcodes/$i! 1>&2 - fi -done - -for lost in .. $lose_these_too; do - if test $lost != ..; then - for i in Makefile.am Makefile.in configure.in configure; do - if fgrep $lost $i >/dev/null 2>&1; then - echo '***' File $lost was sanitized out but is still mentioned in opcodes/$i 1>&2 - fi - done - fi -done - -# This must come after all other sanitizations. Re-sanitize the .pot -# file. -if [ -n "${verbose}" ]; then - echo Re-computing files for gettext ... -fi - -if [ -n "${safe}" -a ! -f po/.Recover/POTFILES.in ]; then - if [ -n "${verbose}" ]; then - echo Caching po/POTFILES.in in .Recover... - fi - mv po/POTFILES.in po/.Recover -fi - -ls -1 *.[ch] cg*.in 2>/dev/null | sed -e 's,^\./,,' > po/POTFILES.in - -if [ -n "${safe}" -a ! -f po/.Recover/opcodes.pot ]; then - if [ -n "${verbose}" ]; then - echo Caching po/opcodes.pot in .Recover... - fi - mv po/opcodes.pot po/.Recover -fi - -# If this fails, Sanitization must fail. -xgettext -C -c -k_ -kN_ -f po/POTFILES.in -o po/opcodes.pot || exit 1 - -# End of file. diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog deleted file mode 100644 index 98a858d9d39..00000000000 --- a/opcodes/ChangeLog +++ /dev/null @@ -1,5950 +0,0 @@ -1999-02-10 Doug Evans <devans@casey.cygnus.com> - - * Makefile.in: Rebuild. - -1999-02-09 Doug Evans <devans@casey.cygnus.com> - - * i960c-asm.c,i960c-dis.c,i960c-opc.c,i960c-opc.h: Delete. - * i960-dis.c (print_insn_i960): Rename from print_insn_i960_orig. - * Makefile.am: Remove references to them. - (HFILES): Add fr30-desc.h,m32r-desc.h. - (CFILES): Add fr30-desc.c,fr30-ibld.c,m32r-desc.c,m32r-ibld.c, - m32r-opinst.c. - (ALL_MACHINES): Update. - * configure.in: Redo handling of cgen_files. - (bfd_i960_arch): Delete i960c-*.lo files. - * configure: Regenerate. - * cgen-asm.c (*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC. - (hash_insn_array): Rewrite. - * cgen-dis.c (*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC. - (hash_insn_array): Rewrite. - * cgen-opc.c (*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC. - (cgen_lookup_insn,cgen_get_insn_operands): Define here. - (cgen_lookup_get_insn_operands): Ditto. - * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerate. - * m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate. - * po/POTFILES.in: Rebuild. - * po/opcodes.pot: Rebuild. -start-sanitize-cygnus - * Makefile.am (fr30 cgen dependencies): Add new files. - (m32r cgen dependencies): Add new files. - (CGENFILES): Update for opcode table reorg. - (run-cgen): Pass $(extrafiles). - (stamp-m32r): Set extrafiles to "opinst". - * Makefile.in: Rebuild. - * cgen-opc.in: Delete. - * cgen-ibld.in: New file. - * cgen-asm.in: Include @prefix@-desc.h. - (insert_1,insert_normal,insert_insn_normal): Moved to cgen-ibld.in. - * cgen-dis.in: Include @prefix@-desc.h. - (fill_cache,extract_1,extract_normal,extract_insn_normal): Moved to - cgen-ibld.in. - * cgen.sh: Accept new arg to handle generation of opinst file. - Generate arch-desc.[ch],arch-opinst.c,arch-ibld.c files. -end-sanitize-cygnus - -Fri Feb 5 00:04:24 1999 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.am: Rebuild dependencies. - (HFILES): Add fr30-opc.h. - (CFILES): Add fr30-asm.c, fr30-dis.c, fr30-opc.c. - * Makefile.in: Rebuild. - - * configure.in: Change AC_PREREQ to 2.13. Remove AM_CYGWIN32. - Change AM_EXEEXT to AC_EXEEXT and AM_PROG_INSTALL to - AC_PROG_INSTALL. - * acconfig.h: Remove. - * configure: Rebuild with current autoconf/automake. - * aclocal.m4: Likewise. - * config.in: Likewise. - * Makefile.in: Likewise. - -Thu Feb 4 13:48:52 1999 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: Correct move (not movew) to status word on 5200. - -Mon Feb 1 20:54:36 1999 Catherine Moore <clm@cygnus.com> - - * disassemble.c (disassembler): Handle bfd_mach_i386_i386_intel_syntax. - * i386-dis.c (x_mode): Define. - (dis386): Remove. - (dis386_att): New. - (dis386_intel): New. - (dis386_twobyte): Remove. - (dis386_twobyte_att): New. - (dis386_twobyte_intel): New. - (print_insn_x86): Use new arrays. - (float_mem): Remove. - (float_mem_intel): New. - (float_mem_att): New. - (dofloat): Use new float_mem arrays. - (print_insn_i386_att): New. - (print_insn_i386_intel): New. - (print_insn_i386): Handle bfd_mach_i386_i386_intel_syntax. - (putop): Handle intel syntax. - (OP_indirE): Handle intel syntax. - (OP_E): Handle intel syntax. - (OP_I): Handle intel syntax. - (OP_sI): Handle intel syntax. - (OP_OFF): Handle intel syntax. - - - -1999-01-27 Doug Evans <devans@casey.cygnus.com> - - * fr30-opc.h,fr30-opc.c: Rebuild. - * i960c-opc.h,i960c-opc.c: Rebuild. - * m32r-opc.c: Rebuild. - -Tue Jan 19 18:01:54 1999 David Taylor <taylor@texas.cygnus.com> - - * hppa-dis.c: revert HP merge changes until HP gives us - an updated file. - -1999-01-19 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (print_insn_arm): Display ARM syntax for PC relative - offsets as well as symbloic address. - -Tue Jan 19 10:51:01 1999 David Taylor <taylor@texas.cygnus.com> - - * hppa-dis.c: fix comments and some indentation. - -1999-01-12 Doug Evans <devans@casey.cygnus.com> - -start-sanitize-cygnus - * Makefile.am (run-cgen): Pass options to cgen. - (stamp-m32r): Build operand instance table. - (stamp-fr30,stamp-i960c): Don't build the table. - * Makefile.in: Regenerate. - * cgen.sh: New arg `options'. Pass to cgen. -end-sanitize-cygnus - * fr30-opc.c,i960c-opc.c: Regenerate. - -1999-01-11 Doug Evans <devans@casey.cygnus.com> - - * fr30-opc.c: Regenerate. - -1999-01-06 Doug Evans <devans@casey.cygnus.com> - - * m32r-dis.c: Regenerate. - -start-sanitize-r5900 -1999-01-06 Frank Ch. Eigler <fche@cygnus.com> - - * mips-opc.c (div1): Add three-operand pattern, just like "div". - (divu1): Ditto for "divu". - -end-sanitize-r5900 -1999-01-05 Doug Evans <devans@casey.cygnus.com> - -start-sanitize-cygnus - * cgen-asm.in (insert_normal): Use CGEN_BOOL_ATTR. - * cgen-asm.in (extract_normal): Ditto. -end-sanitize-cygnus - * fr30-asm.c,fr30-dis.c,fr30-opc.h,fr30-opc.c: Regenerate. - * i960c-asm.c,i960c-dis.c,i960c-opc.h,i960c-opc.c: Regenerate. - * m32r-asm.c,m32r-dis.c,m32r-opc.h,m32r-opc.c: Regenerate. - -1999-01-04 Jason Molenda (jsm@bugshack.cygnus.com) - - * configure.in: Require autoconf 2.12.1 or higher. - -1998-12-30 Gavin Romig-Koch <gavin@cygnus.com> - - * mips16-opc.c: Mark branch insns with MIPS16_INSN_BRANCH. - -Wed Dec 16 16:17:49 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-opc.c: Regenerated. - -start-sanitize-vr4xxx -1998-12-16 Gavin Romig-Koch <gavin@cygnus.com> - - * mips-dis.c (set_mips_isa_type): Handle bfd_mach_mips4111. - -end-sanitize-vr4xxx -1998-12-15 Dave Brolley <brolley@cygnus.com> - - * fr30-opc.c,fr30-opc.h: Regenerated. - -1998-12-14 Dave Brolley <brolley@cygnus.com> - - * fr30-opc.c,fr30-opc.h: Regenerated. - -start-sanitize-vr4xxx -1998-12-13 Gavin Romig-Koch <gavin@cygnus.com> - - * mips-dis.c (set_mips_isa_type): Add bfd_mach_mips4121. - (_print_insn_mips): Same. - * mips-opc.c: Add vr4121. - -end-sanitize-vr4xxx -Thu Dec 10 18:39:46 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-opc.c,fr30-opc.h: Regenerated. - -Thu Dec 10 12:49:24 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.c: Regenerate. - -start-sanitize-sky -Wed Dec 9 14:57:23 1998 Doug Evans <devans@canuck.cygnus.com> - - * mips-opc.c (mips_builtin_opcodes): Update vmtir syntax. - * dvp-opc.c (vu_lower_opcodes): Update mtir entry. - (extract_ffstreg): Fix calculation of reg part of returned value. - - Thu Nov 19 16:38:16 EST 1998 Frank Ch. Eigler <fche@cygnus.com> - - * mips-opc.c (sync*): Flag these instructions with INSN_SYNC. - - Wed Jul 29 09:41:19 1998 Frank Ch. Eigler <fche@cygnus.com> - - * dvp-opc.c (vu_lower_opcodes): Allow ISW, ISWR, MFIR instructions - to take multiple destination (xyzw) flags. - - Thu Jul 23 18:26:49 1998 Frank Ch. Eigler <fche@cygnus.com> - - * dvp-opc.c (vu_operands): Add UW operand type to force ".w" suffix - on ft operand of CLIP. - (insert_w): New function for same. - (vu_opcodes): Use "broadcast" style argument list for two-operand - CLIP insn. Call UW constraint above. - - Mon Jun 22 15:48:29 1998 Ian Carmichael <iancarm@cygnus.com> - - * dvp-dis.c (print_insn): Disassemble DVP_OPERAND_RELOC_11_S4 as - base 10. - -end-sanitize-sky -Tue Dec 8 13:56:18 1998 David Taylor <taylor@texas.cygnus.com> - - * dis-buf.c (generic_strcat_address): reformat to GNU coding - conventions. change sprintf call to an sprintf_vma call. - -Tue Dec 8 13:12:44 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated. - -Tue Dec 8 10:50:46 1998 David Taylor <taylor@texas.cygnus.com> - - The following changes were made by - Elena Zannoni <ezannoni@kwikemart.cygnus.com>, - David Taylor <taylor@texas.cygnus.com>, and - Edith Epstein <eepstein@sophia.cygnus.com> as part of a project to - merge in changes by HP; HP did not create ChangeLog entries. - - * dis-buf.c (generic_strcat_address): new function. - - * hppa-dis.c: Changes to improve hppa disassembly. - Changed formatting in : reg_names, fp_reg_names,control_reg, - New variables : sign_extension_names, deposit_names, conversion_names - float_test_names, compare_cond_names_double, add_cond_names_double, - logical_cond_names_double, unit_cond_names_double, - branch_push_pop_names, saturation_names, shift_names, mix_names, - New Macros : GET_COMPL_O, GET_PUSH_POP,MERGED_REG - Move some definitions to libhppa.h: GET_FIELD, GET_BIT - (fput_const): renamed as fput_hex_const - (print_insn_hppa): - - use the macros fputs_filtered and - fput_decimal_const whenever possible; calls to sign_extend require - 2 params -- add a missing second param of 0. - - Some new code ifdefed for LOCAL_ONLY, all related to figuring out - architecture version number of current machine. HP folks are - trying to handle situation where the target program was compiled - for PA 1.x (32-bit), but is running on a PA 2.0 machine and - visa versa. - - added new cases : 'g', 'B', 'm' - - added cases specifically for PA 2.0 - - changed the following cases : '"', 'n', 'N', 'p', 'Z', - - calls to fput_const become calls to fput_hex_const - -1998-12-07 James E Wilson <wilson@wilson-pc.cygnus.com> - - * Makefile.am (CFILES): Add i960c-asm, i960c-dis.c, i960c-opc.c. - (ALL_MACHINES): Add i960c-asm.lo, i960c-dis.lo, i960-opc.lo. -start-sanitize-cygnus - (CLEANFILES): Add stamp-i960. - (I960_DEPS): Define. - (i960c-opc.h, i960c-opc.c, i960c-asm.c, i960c-dis.c, stamp-i960): - New makefile rules. -end-sanitize-cygnus - (i960-asm.lo, i960c-dis.lo, i960c-opc.lo): New Makefile rules. - * Makefile.in: Rebuilt. - * configure.in (bfd_i960_arch): Add i960c-opc.lo, i960-asm.o, - i960-dis.c to ta. - * i960-dis.c (print_insn_i960): Rename to print_insn_i960_orig. - * i960c-asm.c, i960c-dis.c, i960c-opc.c, i960c-opc.h: New files. - -Mon Dec 7 14:33:44 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated. - -Sun Dec 6 14:06:48 1998 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c (mips_builtin_opcodes): Add dmfc2 and dmtc2. - - * ppc-opc.c (powerpc_opcodes): Add PowerPC403 GC[X] instructions. - From Saitoh Masanobu <msaitoh@spa.is.uec.ac.jp>. - -Fri Dec 4 17:45:51 1998 Doug Evans <devans@canuck.cygnus.com> - - * fr30-opc.c: Regenerate. - -Fri Dec 4 17:08:08 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated. - -Thu Dec 3 14:26:20 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated. - -Thu Dec 3 00:09:17 1998 Doug Evans <devans@canuck.cygnus.com> - - * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerate. - -1998-11-30 Doug Evans <devans@casey.cygnus.com> - - * cgen-dis.c (hash_insn_array): CGEN_INSN_VALUE -> - CGEN_INSN_BASE_VALUE. -start-sanitize-cygnus - * cgen-asm.in (insert_normal): Change start,length to unsigned int. - New args word_offset, word_length. Rewrite. - (FLD): Define. - (insert_1): Fix lsb0 case. - * cgen-dis.in (extract_normal): Change start,length to unsigned int. - New args word_offset, word_length. Rewrite. - (FLD): Define. - (extract_1): Fix lsb0 case. - * cgen-opc.in (FLD): Define. -end-sanitize-cygnus - * m32r-opc.c,m32r-opc.h,m32r-asm.c,m32r-dis.c: Regenerate. - * fr30-opc.c,fr30-opc.h,fr30-asm.c,fr30-dis.c: Regenerate. - -start-sanitize-cygnus -Mon Nov 30 11:52:44 1998 Doug Evans <devans@canuck.cygnus.com> - - * Makefile.am (CGENFILES): Add rtx-funcs.scm. - * Makefile.in: Rebuild. - -end-sanitize-cygnus -Thu Nov 26 11:26:32 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-asm.c,fr30-dis.c,fr30-opc.c: Regenerated. - -Tue Nov 24 11:20:54 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-asm.c,fr30-dis.c: Regenerated. - -Mon Nov 23 18:28:48 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated. - -1998-11-20 Doug Evans <devans@tobor.to.cygnus.com> - - * fr30-opc.c: Regenerated. - -Thu Nov 19 16:02:46 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-opc.c: Regenerated. - * fr30-opc.h: Regenerated. - * fr30-dis.c: Regenerated. - * fr30-asm.c: Regenerated. - -Thu Nov 19 07:54:15 1998 Doug Evans <devans@charmed.cygnus.com> - - * mips-opc.c (sync.p,sync.l): Swap insn values. - -1998-11-19 Doug Evans <devans@tobor.to.cygnus.com> - - * fr30-opc.c: Regenerate. - -Wed Nov 18 21:36:37 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-opc.c: Regenerated. - * fr30-opc.h: Regenerated. - -1998-11-18 Doug Evans <devans@casey.cygnus.com> - -start-sanitize-cygnus - * cgen-asm.in (insert_1): Replace calls to bfd_getb8/putb8. - (insert_normal, !CGEN_INT_INSN_P case): Only fetch enough bytes - to hold value. - (insert_insn_normal): Fix typo. - * cgen-dis.c (cgen_dis_lookup_insn): Update type of `value' arg. - * cgen-dis.in (extract_normal): Ditto. New arg `pc'. - Rewrite ! CGEN_INT_INSN_P case. - (extract_insn_normal): Ditto. - (extract_1): New arg `pc'. All callers updated. - Replace calls to bfd_getb8. - (fill_cache): New fn. - * cgen-opc.c (cgen_{get,put}_insn_value): Move here ... - * cgen-opc.in: ... from here. - (@arch@_cgen_lookup_insn): Rewrite ! CGEN_INT_INSN_P case. -end-sanitize-cygnus - * m32r-asm.c,m32r-dis.c,m32r-opc.c: Rebuild. - * fr30-asm.c,fr30-dis.c,fr30-opc.c: Rebuild. - -Wed Nov 18 11:30:04 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-opc.c: Regenerated. - -Mon Nov 16 19:21:48 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-opc.c: Regenerated. - * fr30-opc.h: Regenerated. - * fr30-dis.c: Regenerated. - * fr30-asm.c: Regenerated. - -Thu Nov 12 19:24:18 1998 Dave Brolley <brolley@cygnus.com> - - * po/opcodes.pot: Regenerated. - * fr30-opc.c: Regenerated. - * fr30-opc.h: Regenerated. - * fr30-dis.c: Regenerated. - * fr30-asm.c: Regenerated. - -Tue Nov 10 15:26:27 1998 Nick Clifton <nickc@cygnus.com> - - * disassemble.c (disassembler): Add support for FR30 target. - -Tue Nov 10 11:00:04 1998 Doug Evans <devans@canuck.cygnus.com> - -start-sanitize-cygnus - * cgen-dis.in (print_normal): CGEN_OPERAND_FAKE renamed to - CGEN_OPERAND_SEM_ONLY. -end-sanitize-cygnus - * m32r-dis.c,m32r-opc.c,m32r-opc.h: Rebuild. - * fr30-dis.c,fr30-opc.c,fr30-opc.h: Rebuild. - -Mon Nov 9 18:22:55 1998 Dave Brolley <brolley@cygnus.com> - - * po/opcodes.pot: Regenerate. - * po/POTFILES.in: Regenerate. - * fr30-opc.c: Regenerate. - * fr30-opc.h: Regenerate. - -Fri Nov 6 17:21:38 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-asm.c: Regenerate. - -Wed Nov 4 18:46:47 1998 Dave Brolley <brolley@cygnus.com> - - * configure.in: Added case for bfd_fr30_arch. - * Makefile.am (CFILES): Added fr30-asm.c, fr30-dis.c, fr30-opc.c. - (ALL_MACHINES): Added fr30-asm.lo, fr30-dis.lo, fr30-opc.lo. - (CLEANFILES): Added stamp-fr30. - (FR30_DEPS): Added. - * fr30-asm.c: New file. - * fr30-dis.c: New file. - * fr30-opc.c: New file. - * fr30-opc.h: New file. - * po/POTFILES.in: Regenerated - * po/opcodes.pot: Regenerated - -start-sanitize-cygnus -Mon Nov 2 20:08:03 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.c (m32r_cgen_insn_table_entries): Add FILL_SLOT attribute - to bcl8,bncl8 entries. - (macro_insn_table_entries): Add FILL_SLOT attribute - to bcl8r,bncl8r entries. - -end-sanitize-cygnus -Mon Nov 2 15:05:33 1998 Geoffrey Noer <noer@cygnus.com> - - * configure.in: detect cygwin* instead of cygwin32* - * configure: regenerate - -Tue Oct 27 08:58:37 1998 Gavin Romig-Koch <gavin@cygnus.com> - - * mips-opc.c (IS_M): Added. - -start-sanitize-r5900 -Fri Oct 23 12:06:00 EDT 1998 Frank Ch. Eigler <fche@cygnus.com> - - * mips-opc.c (vrget, vclipw, vrnext): Correct COP2 opcodes - and masks. - -end-sanitize-r5900 -Mon Oct 19 13:03:19 1998 Doug Evans <devans@seba.cygnus.com> - -start-sanitize-cygnus - * cgen-asm.in (insert_1): New function. - (insert_normal): Progress on handling ! CGEN_INT_INSN_P. - (insert_insn_normal): Update handling of CGEN_INT_INSN_P. - (@arch@_cgen_assemble_insn): Update type of `buf' arg. - * cgen-dis.in (extract_1): New function. - (extract_normal): buf_ctrl renamed to ex_info, update type. - Progress on handling of CGEN_INT_INSN_P. - (extract_insn_normal): buf_ctrl renamed to ex_info, update type. - Update handling of CGEN_INT_INSN_P. Handle errors from - @arch@_cgen_extract_operand. - (print_insn): Renamed from print_int_insn. Handle ! CGEN_INT_INSN_P. - (default_print_insn): Renamed from print_insn. - Handle ! CGEN_INT_INSN_P. - (print_insn_@arch@): Handle error returns from print_insn. - * cgen-opc.in (cgen_get_insn_value, cgen_put_insn_value): New fns. - (@arch@_cgen_lookup_insn): Update handling of CGEN_INT_INSN_P. - (@arch@_cgen_lookup_get_insn_operands): Ditto. -end-sanitize-cygnus - * m32r-opc.c,m32r-opc.h,m32r-asm.c,m32r-dis.c: Regenerate. - -start-sanitize-cygnus -Wed Oct 14 12:12:25 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c: Allow autoincrement stores using the same register - for source and destination operands. - -Mon Oct 12 10:43:51 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c: DSP instrutions which only write to one general - register have no restrictions on matching operands. - - * m10300-opc.c (lsr_add): Fix typo for "lsr_add imm,reg,reg,reg" case. - -end-sanitize-cygnus -Fri Oct 9 14:01:56 1998 Doug Evans <devans@seba.cygnus.com> - - * m32r-opc.h,m32r-opc.c: Regenerate. - -start-sanitize-cygnus -Thu Oct 8 06:04:38 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c (asr, lsr, asl): Fix am33 single bit shift opcode. - -end-sanitize-cygnus -Sun Oct 4 21:01:44 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c (OP_3DNowSuffix): New static function. - (OPSUF): Define. - (GRP14): Define. - (dis386_twobyte): Add GRP14, femms, and 3DNow entries. - (twobyte_has_modrm): Set entries corresponding to GRP14, 3DNow. - (insn_codep): New static variable. - (print_insn_x86): Init insn_codep after prefixes. - (grps): Add GRP14 entries for prefetch, prefetchw. - (OP_REG): Reformat. - - From Jeff B Epler <jepler@usgs.gov> - * i386-dis.c (Suffix3DNow): New table. - -Wed Sep 30 10:17:50 1998 Nick Clifton <nickc@cygnus.com> - - * d10v-opc.c: Treat TRAP as if it were a branch type instruction. - -Mon Sep 28 14:35:43 1998 Martin M. Hunt <hunt@cygnus.com> - - * d10v-dis.c (print_operand): If num is nonzero, then - add OPERAND_ACC1, not OPERAND_ACC0. - -Thu Sep 24 09:20:03 1998 Nick Clifton <nickc@cygnus.com> - - * d30v-opc.c: Add FLAG_JSR attribute to DBT, REIT, RTD, and TRAP - insns. - -Tue Sep 22 17:55:14 1998 Nick Clifton <nickc@cygnus.com> - - * d30v-opc.c: Add use of EITHER_BUT_PREFER_MU execution unit - class. - -start-sanitize-sky -Fri Sep 18 16:23:32 1998 Doug Evans <devans@canuck.cygnus.com> - - * dvp-opc.c (gif_opcodes): Support EOP on gifimage. - -end-sanitize-sky -Tue Sep 15 15:14:45 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.h,m32r-opc.c: Add bbpc,bbpsw support. - -1998-09-09 Michael Meissner <meissner@cygnus.com> - - * ppc-opc.c (powerpc_opcodes): Add support for PowerPC 750 move - to/from SPRs. - -Fri Sep 4 19:42:59 1998 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (print_insn_big_arm): Detect Thumb symbols in elf - object files. - (print_insn_little_arm): Detect Thumb symbols in elf object - files. - -Sat Aug 29 22:24:09 1998 Richard Henderson <rth@cygnus.com> - - * alpha-dis.c (print_insn_alpha): Use the machine type to - decide which PALcode set to include. - -Sun Aug 23 02:16:18 1998 Richard Henderson <rth@cygnus.com> - - * sparc-opc.c (FBRX): Fix typo in ",a,pn %fcc3" case. - -Fri Aug 21 16:07:52 1998 Nick Clifton <nickc@cygnus.com> - - * d30v-opc.c (d30v_opcode_table): Add FLAG_MUL32 to MAC, MACS, - MSUB and MSUBS instructions. - -start-sanitize-r5900 -Tue Aug 18 16:48:52 1998 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c: Insert contents of vu0.h, rather than including it. - * vu0.h: Remove. - * Makefile.am: Rebuild dependencies. - * Makefile: Rebuild. - -end-sanitize-r5900 -Thu Aug 13 16:23:04 1998 Ian Lance Taylor <ian@cygnus.com> - - * ppc-opc.c (powerpc_operands): Omit parens around additions in - operand name macros. - -Wed Aug 12 14:00:38 1998 Ian Lance Taylor <ian@cygnus.com> - -start-sanitize-coldfire - * m68k-opc.c: Correct divsl, divul, remsl, and remul for - ColdFire, as below for mulsl and mulul. - -end-sanitize-coldfire - From Peter Jeremy <peter.jeremy@auss2.alcatel.com.au>: - * m68k-opc.c: Correct mulsl and mulul to use q rather than D, a, - +, -, and d for ColdFire. - - From Peter Thiemann <thiemann@informatik.uni-tuebingen.de>: - * ppc-opc.c (insert_mbe): Handle wrapping bitmasks. - (extract_mbe): Likewise. - -Wed Aug 12 11:11:34 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c: Fix typo in udf20 .. udf25 instruction opcodes. - - * m10300-opc.c: First cut at UDF instructions. - -Mon Aug 10 14:08:22 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.c: Regenerate (remove semantic descriptions). - -Mon Aug 10 12:51:12 1998 Catherine Moore <clm@cygnus.com> - - * arm-dis.c (print_insn_big_arm): Fix indentation. - (print_insn_little_arm): Likewise. - -Sun Aug 9 20:17:28 1998 Catherine Moore <clm@cygnus.com> - - * arm-dis.c (print_insn_big_arm): Check for thumb symbol - attributes. - (print_insn_little_arm): Likewise. - -Mon Aug 3 12:43:16 1998 Doug Evans <devans@seba.cygnus.com> - - Move all global state data into opcode table struct, and treat - opcode table as something that is "opened/closed". - * cgen-asm.c (all fns): New first arg of opcode table descriptor. - (cgen_asm_init): Delete. - (cgen_set_parse_operand_fn): New function. - * cgen-dis.c (all fns): New first arg of opcode table descriptor. - (cgen_dis_init): Delete. - * cgen-opc.c (all fns): New first arg of opcode table descriptor. - (cgen_current_{opcode_table_mach,endian}): Delete. -start-sanitize-cygnus - * cgen-asm.in (all fns): New first arg of opcode table descriptor. - * cgen-dis.in (all fns): Ditto. - * cgen-opc.in (all fns): Ditto. -end-sanitize-cygnus - * m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate. - -start-sanitize-cygnus - * cgen-asm.in (parse_insn_normal): Ignore case in mnemonics. - - * cgen-dis.in (print_normal): Split into two. - (print_address): New function. - (extract_insn_normal): Clarify insn_value arg. - (print_int_insn): Renamed from print_insn. - (print_insn): New arg. - (print_insn_@arch@): Open opcode table if not already done so. - Move reading of insn into print_insn. - -end-sanitize-cygnus -Thu Jul 30 21:41:10 1998 Frank Ch. Eigler <fche@cygnus.com> - - * d30v-opc.c (d30v_opcode_table): Add new "LKR" flag to some - instructions. - -start-sanitize-cygnus -Tue Jul 28 13:15:39 1998 Doug Evans <devans@canuck.cygnus.com> - - Add support for new versions of mulwhi,mulwlo,macwhi,macwlo that - accept an accumulator choice. - * m32r-opc.c,m32r-opc.h: Regenerate. - -end-sanitize-cygnus -Tue Jul 28 11:00:09 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c: Add entries for "no_match_operands" field in - the opcode table. - -start-sanitize-cygnus -Fri Jul 24 15:22:40 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-dis.c: Do not emit a comma before a PLUS (autoincrement) - operand. - -end-sanitize-cygnus -Fri Jul 24 11:41:37 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-asm.c,m32r-opc.c: Regenerate (-Wall cleanups). - -start-sanitize-cygnus -Thu Jul 23 09:21:03 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c: Add DSP autoincrement memory loads/stores. - - * m10300-opc.c: Add autoincrement memory loads/stores. - -end-sanitize-cygnus -start-sanitize-r5900 -Wed Jul 22 17:05:40 1998 Jeffrey A Law (law@cygnus.com) - - * mips-opc.c: Make phmadh and phmsbh synonyms for phmaddh and - phmsubh respectively. - -end-sanitize-r5900 -Tue Jul 21 13:41:07 1998 Doug Evans <devans@seba.cygnus.com> - -start-sanitize-cygnus - * cgen-opc.in (@arch@_cgen_lookup_insn): Update call to - CGEN_EXTRACT_FN. - (@arch@_cgen_get_insn_operands): @arch@_cgen_get_operand renamed to - @arch_cgen_get_int_operand. - * cgen-asm.in (insert_insn_normal): New arg `pc', callers updated. - Update call to @arch@_cgen_insert_operand. - (@arch@_cgen_assemble_insn): Update call to CGEN_INSERT_FN. - * cgen-dis.in (print_normal): Delete use of CGEN_PCREL_OFFSET. - (extract_insn_normal): New arg `pc', callers updated. - Update call to @arch@_cgen_extract_operand. - (print_insn): Update call to CGEN_EXTRACT_FN. -end-sanitize-cygnus - * m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate. - -start-sanitize-cygnus -Mon Jul 20 12:10:37 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c: Fix load to sp and store from sp for the am33. - Add more multimedia instructions. - -Thu Jul 16 18:04:46 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c (mn10300_opcodes): Fix opcode for 4 operand "mul" and - "mulu". - -end-sanitize-cygnus -start-sanitize-r5900 -Mon Jul 13 18:14:24 1998 Jeffrey A Law (law@cygnus.com) - - * mips-opc.c (pref): Enabled for the r5900. - -end-sanitize-r5900 -Mon Jul 13 14:53:59 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c (ckprefix): Handle fwait specially only when it isn't - the first prefix. - (dofloat): Correct test for fnstsw. Print `fnstsw %ax' rather - than `fnstsw %eax'. - (OP_J): Remove unnecessary subtraction when 16-bit displacement - will be masked later. - -start-sanitize-cygnus -Fri Jul 10 23:09:56 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c (mn10300_opcodes): Fix destination operand for 3 operand - instructions. - -Wed Jul 8 11:32:44 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-dis.c (disassemble): When printing RREGs and XRREGs, map - from raw register #s to symbolic names to make debugging easier. - -end-sanitize-cygnus -Thu Jul 2 17:11:27 1998 Doug Evans <devans@seba.cygnus.com> - - * m32r-opc.h (CGEN_MIN_INSN_SIZE): New #define. - -Wed Jul 1 16:11:16 1998 Doug Evans <devans@seba.cygnus.com> - - * m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate. -start-sanitize-cygnus - * Makefile.am (CGENDIR): Set via configure. - (CGEN): New variable. - (CGENFILES): object.scm renamed to cos.scm. - (run-cgen): Renamed from cgen. stamp file renamed to stamp-$prefix. - (stamp-m32r): Pass prefix to run-cgen. - * Makefile.in: Regenerate. - * cgen-asm.in: @arch@-opc.h renamed to @prefix@-opc.h. - * cgen-dis.in: Ditto. - * cgen-opc.in: Ditto. - * cgen.sh: New args cgen,prefix. Delete args scheme,schemeflags. - * configure.in: AC_SUBST cgen,cgendir. No longer look for guile. - * configure: Regenerate. -end-sanitize-cygnus - -start-sanitize-cygnus -Tue Jun 30 09:59:37 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c: Reorder "movbu" and "movhu" instructions too. - -Mon Jun 29 14:54:32 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c: Reorder more instructions so that we do not - accidentally match a mn10300 instruction when we really - wanted an am33 instruction. - -end-sanitize-cygnus -Fri Jun 26 11:08:55 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-dis.c: Only recognize instructions from the currently - selected machine. - * m10300-opc.c: Add field indicating the particular variant of - the mn10300 each instruction is available on. - -Fri Jun 26 12:04:21 1998 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: For bfd_vax_arch, build vax-dis.lo. - * Makefile.am: Rebuild dependencies. - (CFILES): Add vax-dis.c. - (ALL_MACHINES): Add vax-dis.lo. - * aclocal.m4: Rebuild with current libtool. - * configure, Makefile.in: Rebuild. - -Fri Jun 26 12:03:20 1998 Klaus Kaempf <kkaempf@progis.de> - - * vax-dis.c: New file, from work by Pauline Middelink - <middelin@polyware.iaf.nl>. - * disassemble.c (ARCH_vax): Define if ARCH_all. - (disassembler): Add case for ARCH_vax. - * makefile.vms: Support compilation on vms/vax. - -start-sanitize-sky -Wed Jun 24 17:14:01 1998 Ian Carmichael <iancarm@cygnus.com> - - * dvp-opc.c (DVP_OPERAND_RELOC_11_S4): Temporarily back out - the DVP_OPERAND_RELOC_11_S4 relocation. - -end-sanitize-sky -start-sanitize-cygnus -Wed Jun 24 09:53:06 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-dis.c (print_insn_mn10300): 0xf7 opcode prefix specifies - 4 byte instructions. - (disassemble): Correctly handle FMT_D10 instructions. - - * m10300-opc.c (mn10300_opcodes): Fix typo in IMM24 versions of the - am33 shift instructions. - - * m10300-dis.c (print_insn_mn10300): 0xf9 opcode prefix specifies - 3 byte instructions. - (disassemble): Handle new instruction formats FMT_D6, FMT_D7, FMT_D8 - FMT_D9 and FMT_D10. Handle various new opcode flags for the am33. - - * m10300-opc.c (IMM32_HIGH8_MEM): New operand type. - (mn10300_opcodes): Reorder so as to try and select opcodes from - the core chip when multiple alternatives exist. Change several - am33 instructions to use IMM32_HIGH8_MEM. Fix typos in "mac" and - "macbu" instructions. Fix typos in a couple DSP instructions too. - -end-sanitize-cygnus -Tue Jun 23 19:42:18 1998 Mark Alexander <marka@cygnus.com> - - * m10200-dis.c (print_insn_mn10200): Fix various non-portabilities - related to sign extension and the size of ints. - -Tue Jun 23 10:59:26 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c: Support one operand "asr", "lsr" and "asl" - instructions. Support (sp) addressing mode by expanding it into - (0,sp). - -start-sanitize-sky -Mon Jun 22 15:48:29 1998 Ian Carmichael <iancarm@cygnus.com> - - * dvp-opc.c (LIMM11, LUIMM15): New symbol types - DVP_OPERAND_RELOC_U15_S3 and DVP_OPERAND_RELOC_11_S4 to allow labels to - be used as immediate values. - -end-sanitize-sky -start-sanitize-cygnus -Mon Jun 22 13:36:27 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c: Support 4 byte DSP instructions. - -end-sanitize-cygnus -Sat Jun 20 14:46:20 1998 Frank Ch. Eigler <fche@cygnus.com> - - * mips-dis.c (_print_insn_mips): Fix argument interchange typo. - -start-sanitize-cygnus -Fri Jun 19 16:47:06 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c: Support 6 and 7 byte am33 instructions. - -end-sanitize-cygnus -Fri Jun 19 09:16:42 1998 Mark Alexander <marka@cygnus.com> - - * m10200-dis.c (print_insn_mn10200): Recognize 'break' pseudo-op. - -start-sanitize-cygnus -Fri Jun 19 09:42:51 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c: Support for 3 byte and 4 byte extended instructions - found on the mn10300. - -end-sanitize-cygnus -1998-06-18 Ulrich Drepper <drepper@cygnus.com> - - * i386-dis.c: Add support for fxsave, fxrstor, sysenter and - sysexit. - -Thu Jun 18 10:22:24 1998 John Metzler <jmetzler@cygnus.com> - - * mips-dis.c (print_insn_little_mips): Previously, instruction - printing references the symbol table to determine whether the - instruction resides in a block regular instructions or mips16 - instructions. However, when the disassembler gets used in other - environments where the symbol table is not present, we no longer - rely in the symbol table, rather, use the low bit of the - instructions address to guess. There should be no change for usage - of the disassembler in host based programs, gdb, objdump. - (print_insn_big_mips): ditto. - (print_insn_mips): ditto - -Wed Jun 17 21:19:01 1998 Mark Alexander <marka@cygnus.com> - - * m10200-dis.c (print_insn_mn10200): Don't bomb on unknown opcodes. - -Wed Jun 17 17:49:23 1998 Jeffrey A Law (law@cygnus.com) - -start-sanitize-cygnus - * m10300-opc.c (USP, SSP, MSP, PC, IMM4, EPSW, RN0, RM1): New - operands for the am33. - (mn10300_opcodes): Add new instructions from the am33. -end-sanitize-cygnus - * m10300-opc.c (mn10300_opcodes): Change opcode for "syscall". - -Tue Jun 16 13:10:51 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c (index16): Add '%' to register names. Use ',' - instead of '+'. - -Sat Jun 13 11:33:55 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c: Don't print opcode suffix when we can figure out the - size (and gas can!) by register operands, or from the default - size. - (putop): Handle 'A', 'B', 'L', 'P', 'Q', 'R' macros. Rename 'C' - macro to 'E'. - (dis386, dis386_twobyte, grps): Use new suffix macros. - (dis386): Correct imul Ib to imul sIb. Change jnl to jge to be - consistent. Add suffix for call, jmp, lcall, ljmp, iret. Reverse - order of cmps operands to agree with Intel docs. Correct operand - of aad and aam (Ib -> sIb). Change ud2b from 0fb8 to 0fb9 to - agree with Intel docs. - (print_insn_x86): Print orphan fwait before other prefixes. - Return correct byte count for orphan fwait with prefixes. Don't - print `bound' operands in reverse order. - (ckprefix): Stop accumulating prefixes if we get fwait. - (OP_DIR): Print `$' before Ap operands of ljmp, lcall. - -Fri Jun 12 13:40:38 1998 Tom Tromey <tromey@cygnus.com> - - * po/Make-in (all-yes): If maintainer mode, depend on .pot file. - ($(PACKAGE).pot): Unconditionally depend on POTFILES. - -Fri Jun 12 11:04:06 1998 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - Fix problems when bfd_vma is wider than long. - * i386-dis.c: Make op_address and start_pc unsigned. - (set_op): Make parameter unsigned. - (print_insn_x86): Cast to bfd_vma when passing a value to - print_address_func. - * ns32k-dis.c (CORE_ADDR): Don't define. - (print_insn_ns32k): Change type of addr to bfd_vma. Use - bfd_scan_vma to read back address. - (print_insn_arg): Change type of addr to bfd_vma. Use sprintf_vma - to format it. - * m68k-dis.c (COERCE32): Cast to bfd_signed_vma to avoid overflow. - (NEXTULONG): New definition. - (print_insn_m68k): Avoid overflow when computing third argument of - print_insn_arg. - (print_insn_arg): Use NEXTULONG to fetch 32 bit address values. - Use disp instead of val to store offset values. - (print_indexed): Use base_disp instead of word to store base - displacement, to avoid overflow. - * m10300-dis.c (disassemble): Cast value to long when computing - pc-relative address, to get correct sign extension. - -Wed Jun 10 15:58:37 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.c: Regenerate. - -Tue Jun 9 14:27:57 1998 Nick Clifton <nickc@cygnus.com> - - * arm-opc.h (thumb_opcodes): Display 'add rx, rY, #0' insns as - 'mov rX, rY'. Patch courtesy of Tony Thompson <Tony.Thompson@arm.com> - -Mon Jun 8 18:17:21 1998 Nick Clifton <nickc@cygnus.com> - - * d30v-opc.c: Remove FALG_MUL32 attribyte from MULX2H insn. - -Fri Jun 5 23:47:55 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c: Combine aflag and dflag into sizeflag. Change OP_* - functions to void. - (OP_DSreg): Rename from OP_DSSI. - (OP_ESreg): Rename from OP_ESDI. - (Xb, Xv, Yb, Yv): Use index reg code, not b_mode or v_mode. - (DSBX): Define. - (append_seg): Rename from append_prefix. - (ptr_reg): New function. - (dis386): Add S suffix to pushf, popf, ret, lret, enter, leave. - Add DSBX for xlat. - (PREFIX_ADDR): Rename from PREFIX_ADR. - (float_reg): Add non-broken opcodes for people who don't want - UNIXWARE_COMPAT. - -Fri Jun 5 19:15:04 1998 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-opc.c (tstb, tstw, tstl): Don't allow pcrel on - 68000/68008/68010. - -Wed Jun 3 18:56:22 1998 H.J. Lu <hjl@gnu.org> - - * i386-dis.c (dis386): Change 0x60 to "pushaS", 0x61 to "popaS". - -Tue Jun 2 15:06:46 1998 Geoff Keating <geoffk@ozemail.com.au> - - * ppc-opc.c (powerpc_macros): Support shifts and rotates of size - 0; produce error message for shifts of size 32 (or 64 for 64-bit - shifts), because the hardware doesn't support them. - -start-sanitize-r5900 -Mon Jun 1 10:27:26 1998 Jeffrey A Law (law@cygnus.com) - - * mips-opc.c (c.lt.s): Remove r5900 specific variant. - (c.le.s): Likewise. - - * vu0.h (sqc2): Fix opcode. - - * mips-opc.c (rsqrt.s): Update based on r5900 ISA manual version 2.1 - (sqrt.s): Likewise. - -end-sanitize-r5900 -start-sanitize-cygnus -Thu May 28 08:46:09 1998 Catherine Moore <clm@cygnus.com> - - * mips-opc.c (macc, maccu, macchi, macchiu, msac, msacu, msachi, msachiu): - Change pinfo to use WR_HILO. - -end-sanitize-cygnus -Wed May 27 15:29:13 1998 Nick Clifton <nickc@cygnus.com> - - * d30v-opc.c: Add new operand: Ra3. Change SHORT_B3, SHORT_B3b, - LONG_2, LONG_2b formats to use this new operand. - -Tue May 26 20:47:48 1998 Stan Cox <scox@cygnus.com> - - * sparc-dis.c (compute_arch_mask): Added bfd_mach_sparc_sparclite_le. - -Tue May 26 20:45:33 1998 Mark Alexander <marka@cygnus.com> - - * sparc-dis.c (print_insn_sparc): big endian instruction / little - endian data support. - -Tue May 26 16:14:39 1998 Nick Clifton <nickc@cygnus.com> - - * d30v-opc.c (d30v_format_table): Change definition of SHORT_B3 - and SHORT_B3b formats to use Rb instead of Ra. - - Add FLAG_MUL16 to MUL2XH opcode. - - Add FLAG_ADDSUBppp to SRC and SATHp opcodes to implement extension - to existing 1.1.1 parallelisation prohibition procedure. - -Fri May 22 16:00:00 1998 Doug Evans <devans@canuck.cygnus.com> - -start-sanitize-cygnus - * cgen-asm.in (insert_normal): Handle empty fields and 64 bit hosts. - * cgen-dis.in (extract_normal): Likewise. -end-sanitize-cygnus - * m32r-asm.c,m32r-dis.c: Regenerate. - -start-sanitize-sky -Fri May 22 11:44:10 1998 Doug Evans <devans@canuck.cygnus.com> - - * dvp-opc.c (parse_dotdest): Missing dest -> xyzw. - -end-sanitize-sky -start-sanitize-r5900 -Wed May 20 00:22:27 1998 Jeffrey A Law (law@cygnus.com) - - * mips-opc.c (multu1): Add two operand variant for the r5900. - -end-sanitize-r5900 -Tue May 19 17:36:08 1998 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (print_mips16_insn_arg): Handle type ']' correctly - with a shift count of 0. - -start-sanitize-r5900 -Mon May 18 14:27:06 1998 Frank Ch. Eigler <fche@cygnus.com> - - * mips-opc.c (mult1): Add two-operand variety of mult1 for R5900. - -Mon May 18 11:44:00 1998 Jeffrey A Law (law@cygnus.com) - - * mips-dis.c (print_insn_arg): Handle ';' opcode completer. - (_print_insn_mips): Likewise. - * vu0.h (vopmula, vopmsub): Correctly handle opcode/operand - completers. - -end-sanitize-r5900 -Fri May 15 14:58:31 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen-opc.c (cgen_hw_lookup_by_name): Renamed from cgen_hw_lookup. - (cgen_hw_lookup_by_num): New function. - -start-sanitize-cygnus - * m32r-opc.c, m32r-opc.h: Regenerate, delete h-abort. - -end-sanitize-cygnus -Wed May 13 17:03:59 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-asm.c: Regenerate (handle uppercase HIGH/SHIGH/LOW/SDA). - -Wed May 13 14:34:31 1998 Mark Alexander <marka@cygnus.com> - - * sparc-dis.c (print_insn_sparc): Always fetch instructions - as big-endian on SPARClite. - -start-sanitize-cygnus -Tue May 12 13:39:51 1998 Nick Clifton <nickc@cygnus.com> - - * m32r-opc.c: Regenerated - SPECIAL attribute added to some - insns. - * m32r-opc.h: Regenerated - SPECIAL attribute added to some - insns. - -end-sanitize-cygnus -Tue May 12 11:46:31 1998 Richard Henderson <rth@cygnus.com> - - * d30v-opc.c (pre_defined_register): Remove alias for r0. - -start-sanitize-r5900 -Mon May 11 13:12:15 1998 Frank Ch. Eigler <fche@cygnus.com> - - * mips-opc.c (break): Added 20-bit single-operand break - instruction for R5900 only. - -end-sanitize-r5900 -Sun May 10 22:37:22 1998 Jeffrey A Law (law@cygnus.com) - - * po/Make-in (install-info): New target. - -Thu May 7 17:15:59 1998 Ian Lance Taylor <ian@cygnus.com> - - * configure.in (WIN32LIBADD): Add -lintl on cygwin32. - * configure: Rebuild. - -Thu May 7 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com> - - * mips-opc.c (teq,tge,tgeu,tlt,tltu,tne): Added three-operand - variety of ISA2 instructions to set bottom ten bits of trap code. - -Thu May 7 11:54:25 1998 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.am (config.status): Add explicit target so that - config.status depends upon bfd/configure.in. - * Makefile.in: Rebuild. - -Thu May 7 09:33:02 1998 Frank Ch. Eigler <fche@cygnus.com> - - * mips-opc.c (break, sdbbp): Added two-operand variety of ISA1 - instructions to set bottom ten bits of break code. - * mips-dis.c (print_insn_arg): Implement 'q' operand format used - for above optional argument. - -start-sanitize-cygnus -Wed May 6 14:47:17 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.sh: s/@ARCH@/${ARCH}/ in opc.h generation. - * m32r-opc.h: Regenerate. - -end-sanitize-cygnus -Wed May 6 15:30:06 1998 Klaus Kaempf <kkaempf@progis.de> - - * makefile.vms: Run dec c with /nodebug. - -Mon May 4 10:19:57 1998 Tom Tromey <tromey@cygnus.com> - - * Makefile.in: Rebuilt. - * Makefile.am: Regenerated dependencies with mkdep. - - * opintl.h (_): Define as dgettext. - -start-sanitize-cygnus -Fri May 1 13:47:42 1998 Doug Evans <devans@canuck.cygnus.com> - - * configure.in: Add support for --enable-cgen-maint. - * Makefile.am (M32R_DEPS): New variable. - (m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c): Update dependencies. - * aclocal.m4: Regenerate. - * Makefile.in: Regenerate. - * configure: Regenerate. - - * Makefile.am (CGENFILES): Add minsn.scm. - -end-sanitize-cygnus -Tue Apr 28 14:12:12 1998 Nick Clifton <nickc@cygnus.com> - - * cgen-asm.c: Internationalised. -start-sanitize-cygnus - * cgen-asm.in: Internationalised. - * cgen-opc.in: Internationalised. -end-sanitize-cygnus - * m32r-asm.c: Internationalised. - * m32r-dis.c: Internationalised. - * m32r-opc.c: Internationalised. - - * aclocal.m4: Regenerated. - * configure: Regenerated. - * Makefile.am (POTFILES): Remove inclusion of BFD_H. - * Makefile.in: Rebuild. - * po/POTFILES.in: Rebuilt using rule in Makefile.in. - * po/opcodes.pot: Rebuilt after changing POTFILES.in. - -Tue Apr 28 13:13:13 1998 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Call AC_ISC_POSIX near start. Move CY_GNU_GETTEXT - after AC_PROG_CC. - * aclocal.m4, configure: Rebuild with current tools. - -Mon Apr 27 14:31:00 1998 Nick Clifton <nickc@cygnus.com> - - * opintl.h: New file - contains internationalisation macros used - by source files in this directory. - * po/: New subdirectory - contains internationalisation files. - * po/Make-in: New file - Makefile constructor. - * po/POTFILES.in: New file - list of files in opcodes directory - that should be scan for internationalisation macros. - * po/opcodes.pot: New file - list of internationisation strings - found in files mentioned in po/POTFILES.in. - * Makefile.am: Add rule to build po/POTFILES.in. Add SUBDIRS - entry. Add intl directory to include paths. - * acconfig.h: Add ENABLE_NLS, HAVE_CATGETS, HAVE_GETEXT, - HAVE_STRCPY, HAVE_LC_MESSAGES - * configure.in: Add rule to build Makefile in po subdirectory. - * Makefile.in: Rebuilt. - * aclocal.m4: Rebuilt. - * config.in: Rebuilt. - * configure: Rebuilt. - * alpha-opc.c: Internationalised. - * arc-dis.c: Internationalised. - * arc-opc.c: Internationalised. - * arm-dis.c: Internationalised. - * cgen-asm.c: Internationalised. - * d30v-dis.c: Internationalised. - * dis-buf.c: Internationalised. -start-sanitize-sky - * dvp-dis.c: Internationalised. - * dvp-opc.c: Internationalised. -end-sanitize-sky - * h8300-dis.c: Internationalised. - * h8500-dis.c: Internationalised. - * i386-dis.c: Internationalised. - * m10200-dis.c: Internationalised. - * m10300-dis.c: Internationalised. - * m68k-dis.c: Internationalised. - * m88k-dis.c: Internationalised. - * mips-dis.c: Internationalised. - * ns32k-dis.c: Internationalised. - * opintl.h: Internationalised. - * ppc-opc.c: Internationalised. - * sparc-dis.c: Internationalised. - * v850-dis.c: Internationalised. - * v850-opc.c: Internationalised. - -Mon Apr 27 10:33:56 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen-asm.c (cgen_current_opcode_table): Renamed from ..._data. - (asm_hash_table_entries): New variable. - (cgen_asm_init): Free asm_hash_table_entries. - (hash_insn_array,hash_insn_list): New functions. - (build_asm_hash_table): Use them. Hash macro insns as well. - (cgen_asm_lookup_insn): Update. - * cgen_dis.c (cgen_current_opcode_table): Renamed from ..._data. - (dis_hash_table_entries): New variable. - (cgen_dis_init): Free dis_hash_table_entries. - (hash_insn_array,hash_insn_list): New functions. - (build_dis_hash_table): Use them. Hash macro insns as well. - (cgen_dis_lookup_insn): Update. - * cgen-opc.c (cgen_current_opcode_table): Renamed from ..._data. - (cgen_set_cpu,cgen_hw_lookup,cgen_insn_count): Update. - (cgen_macro_insn_count): New function. -start-sanitize-cygnus - * cgen-opc.in (@arch@_cgen_lookup_insn): New arg alias_p. - All callers updated. Sanity check result of extract fn. - (@arch@_cgen_get_insn_operands): Change result type to void. - Delete args insn_value, length. New arg fields. All callers updated. - (@arch@_cgen_lookup_get_insn_operands): New function. -end-sanitize-cygnus - * m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate. - -Fri Apr 24 16:07:57 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c (OP_DSSI): Print segment override. - -start-sanitize-r5900 -Thu Apr 23 12:32:07 1998 Frank Ch. Eigler <fche@cygnus.com> - - * mips-opc.c (msub.s): Correct mask pattern for disassembly. - -end-sanitize-r5900 -start-sanitize-r5900 -Mon Apr 20 19:11:55 1998 Frank Ch. Eigler <fche@cygnus.com> - - * mips-opc.c (madd.s): Correct mask pattern for disassembly. - -end-sanitize-r5900 -start-sanitize-r5900 -Sat Apr 18 00:29:18 1998 Jeffrey A Law (law@cygnus.com) - - * vu0.h (vlqd, vlqi): Update per revised specs. - -end-sanitize-r5900 -start-sanitize-sky -Thu Apr 16 11:44:59 1998 Doug Evans <devans@canuck.cygnus.com> - - * dvp-opc.c (parse_vif_unpackloc,insert_vif_unpackloc): Delete. - (vif_operands): Update. - (vif_get_unpackloc): Delete. - (state_vif_unpackloc{,_star_p}): Delete. - (dvp_opcode_init_parse): Update. - (vif_unpack_len_value): Avoid divide by zero. - -end-sanitize-sky -start-sanitize-r5900 -Wed Apr 15 10:30:07 1998 Frank Ch. Eigler <fche@cygnus.com> - - * vu0.h: Specs changed for VCALLMSR bit pattern. - * mips-dis.c: (print_insn_arg) Matching change. - -end-sanitize-r5900 -Mon Apr 13 16:59:39 1998 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (print_insn_arm): Add "_all" extension to 'C' - operator. - -Mon Apr 13 16:50:27 1998 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.am (libopcodes_la_LIBADD): Add @WIN32LIBADD@. - (libopcodes_la_LDFLAGS): Add @WIN32LDFLAGS@. - * configure.in: Define and substitute WIN32LDFLAGS and - WIN32LIBADD. - * aclocal.m4: Rebuild with new libtool. - * configure, Makefile.in: Rebuild. - -start-sanitize-r5900 -Mon Apr 13 16:02:02 1998 Frank Ch. Eigler <fche@cygnus.com> - - * vu0.h: Corrected bit pattern for VMAXI opcode. - -end-sanitize-r5900 -Fri Apr 10 18:14:31 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.c: Regenerate. - -start-sanitize-sky -Mon Apr 6 17:16:48 1998 Doug Evans <devans@canuck.cygnus.com> - - * dvp-opc.c (vif_macros): Tweak unpackloc operand. - (dvp_expand_macro): Implement. - (insert_vif_datalen): Record value with max+1 -> 0 conversion. - (vif_unpack_len): Perform 0 -> max+1 conversion on `wl' value. - -end-sanitize-sky -Sun Apr 5 16:04:39 1998 H.J. Lu <hjl@gnu.org> - - * Makefile.am (stamp-lib): Check that .libs/libopcodes.a exists - before trying to copy it. - * Makefile.in: Rebuild. - -Thu Apr 2 17:25:49 1998 Nick Clifton <nickc@cygnus.com> - - * m32r-opc.c: Use signed immediate values for CMPUI instruction. - -start-sanitize-cygnus -Thu Apr 2 16:44:23 1998 Nick Clifton <nickc@cygnus.com> - - * m32r-opc.c: Fix bit patterns for SAT and SATB. - -end-sanitize-cygnus -Wed Apr 1 16:20:27 1998 Ian Dall <Ian.Dall@dsto.defence.gov.au> - - * ns32k-dis.c (bit_extract_simple): New function to extract bits - from an arbitrary valid buffer instead of fetching them on demand - using fetch_data(). - (invalid_float): use bit_extract_simple() instead of bit_extract(). - -start-sanitize-cygnus -Wed Apr 1 14:57:54 1998 Nick Clifton <nickc@cygnus.com> - - * m32r-opc.c: Fix SATB bit pattern. Add extra control registers. - * m32r-opc.h: Add extra control registers. - -end-sanitize-cygnus -Tue Mar 31 11:09:08 1998 Ian Lance Taylor <ian@cygnus.com> - - From H.J. Lu <hjl@gnu.org>: - * i386-dis.c (dis386): Change 0x8c and 0x8e to movS, and change Ew - to Ev for both. - -Mon Mar 30 17:32:03 1998 Ian Lance Taylor <ian@cygnus.com> - - * Branched binutils 2.9. - -Mon Mar 30 15:18:00 1998 Ken Raeburn <raeburn@cygnus.com> - - * d30v-dis.c (print_insn_d30v): Don't use uninitialized "num" when - disassembling last 4 bytes of a section. - -Fri Mar 27 18:08:13 1998 Ian Lance Taylor <ian@cygnus.com> - - Fix some gcc -Wall warnings: - * arc-dis.c (print_insn): Add casts to avoid warnings. - * cgen-opc.c (cgen_keyword_lookup_name): Likewise. - * d10v-dis.c (dis_long, dis_2_short): Likewise. -start-sanitize-sky - * dvp-opc.c (issymchar, SKIP_BLANKS): Likewise. - (parse_dotdest, parse_dotdest1, u_parse_sdest): Likewise. - (parse_bc, parse_vfreg, parse_accdest): Likewise. - (parse_ffstreg, parse_vif_mode): Likewise. -end-sanitize-sky - * m10200-dis.c (disassemble): Likewise. - * m10300-dis.c (disassemble): Likewise. - * ns32k-dis.c (print_insn_ns32k): Likewise. - * ppc-opc.c (insert_ral, insert_ram): Likewise. - * cgen-dis.c (build_dis_hash_table): Remove used local variables. - * cgen-opc.c (cgen_keyword_search_next): Likewise. - * d10v-dis.c (dis_long, dis_2_short): Likewise. - * d30v-dis.c (print_insn_d30v, lookup_opcode): Likewise. -start-sanitize-sky - * dvp-dis.c (print_dma, print_vif, print_gif): Likewise. - * dvp-opc.c (parse_dest1, print_uflags): Likewise. - (parse_gif_nloop, dvp_opcode_init_tables): Likewise. -end-sanitize-sky - * ns32k-dis.c (bit_extract, print_insn_ns32k): Likewise. -start-sanitize-tic80 - * tic80-dis.c (print_one_instruction): Likewise. -end-sanitize-tic80 - * w65-dis.c (print_operand): Likewise. - * z8k-dis.c (fetch_data): Likewise. - * a29k-dis.c: Add return type for find_byte_func_type. - * arc-opc.c: Include <stdio.h>. Remove declarations of - insert_multshift and extract_multshift. - * d30v-dis.c (lookup_opcode): Parenthesize assignments in - conditionals. - (extract_value): Fully parenthesize expression. -start-sanitize-sky - * dvp-opc.c: Include <ctype.h>. - (print_sdest): Add default case to switch. -end-sanitize-sky - * h8500-dis.c (print_insn_h8500): Initialize local variables. - * h8500-opc.h (h8500_table): Fully bracket initializer. - * w65-opc.h (optable): Likewise. - * i386-dis.c (print_insn_x86): Declare aflag and flag parameters. - * i386-dis.c (OP_E): Initialize local variables. - * m10200-dis.c (print_insn_mn10200): Likewise. - * mips-dis.c (print_insn_mips16): Likewise. - * sh-dis.c (print_insn_shx): Likewise. - * v850-dis.c (print_insn_v850): Likewise. - * ns32k-dis.c (print_insn_arg): Declare. - (get_displacement, invalid_float): Declare. - (list_search, sign_extend, flip_bytes): Declare return type. - (get_displacement): Likewise. - (print_insn_arg): Likewise. Make d int. Fix sprintf format - string. - (print_insn_ns32k): Make i unsigned. - (invalid_float): Make static. Declare type of val. - * tic30-dis.c (print_par_insn): Make i size_t. Don't check strlen - on each for iteration. - * tic30-dis.c (get_indirect_operand): Likewise. - * z8k-dis.c (print_insn_z8001): Declare return type. - (print_insn_z8002): Likewise. - (unparse_instr): Fix sprintf format strings. - -Fri Mar 27 00:05:23 1998 Jeffrey A Law (law@cygnus.com) - - * mips-opc.c: Add "sync.l" and "sync.p". - -start-sanitize-sky -Thu Mar 26 13:27:37 1998 Doug Evans <devans@canuck.cygnus.com> - - * dvp-opc.c (extract_vif_datalen): Rewrite. - (vif_insn_len): Perform 0->max+1 conversion for direct length. - -Wed Mar 25 13:32:36 1998 Doug Evans <devans@canuck.cygnus.com> - - * dvp-dis.c (print_insn): Print unpack address in hex. - * dvp-opc.c (parse_vif_mpgloc): Renamed from parse_vif_mpgloc_star. - Don't skip over '*', just record it. - (insert_vif_mpgloc): Don't update state_vif_mpgloc if '*' value. - (parse_vif_unpackloc): Renamed from parse_vif_unpackloc_star. - Don't skip over '*', just record it. - (insert_vif_unpackloc): Don't update state_vif_unpackloc if '*' value. - (vif_operands): Delete VIF_MPGLOC_STAR,VIF_UNPACKLOC_STAR entries. - (vif_opcodes): Likewise. - (state_vif_{mpg,unpack}loc_star_p): New static locals. - (vif_macros,vif_macro_count): New globals. - (vif_unpack_len_value): New arguments wl,cl. All callers updated. - (vif_set_{mpg,unpack}loc): Delete. All callers updated. - (vif_get_wl_cl): New function. - (dvp_opcode_init_parse): Init mpgloc,unpackloc state. - -end-sanitize-sky -Wed Mar 25 14:32:48 1998 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-dis.c (print_insn_m68k): Use info->mach to select the - default m68k variant to recognize. - - * i960-dis.c (pinsn): Change type of first argument to bfd_vma. - (ctrl, cobr, mem, ea): Likewise. - (print_addr): Likewise. Remove cast. - (ea): Cast argument of print_addr to bfd_vma. - - * cgen-asm.c (cgen_parse_signed_integer): Fix type of local - variable value. - (cgen_parse_unsigned_integer): Likewise. - (cgen_parse_address): Likewise. - -Wed Mar 25 14:31:31 1998 Ian Lance Taylor <ian@cygnus.com> - - * i960-dis.c (ctrl): Add full braces to structure initialization. - (cobr, mem, reg): Likewise. - (ea): Correct parenthesization in expression. - - * cgen-asm.c: Include <ctype.h>. - (build_asm_hash_table): Remove unused local variable i. - (cgen_parse_keyword): Add casts to avoid warnings. - - * arm-dis.c (print_insn_big_arm): Only call coffsymbol for a COFF - symbol. Fix indentation. - (print_insn_little_arm): Likewise. - -start-sanitize-r5900 -Tue Mar 24 18:11:13 1998 Jeffrey A Law (law@cygnus.com) - - * vu0.h (cfc2, ctc2): Add variants with ".i" and ".ni" - opcode extensions. - -end-sanitize-r5900 -start-sanitize-cygnus -Mon Mar 23 11:32:11 1998 Nick Clifton <nickc@cygnus.com> - - * m32r-opc.c (m32r_cgen_insn_table_entries): Fix SATH bit pattern - (PR15418). - -end-sanitize-cygnus -start-sanitize-sky -Mon Mar 23 09:45:04 1998 Doug Evans <devans@canuck.cygnus.com> - - * dvp-opc.c (vif_operand_datalen_special): New global. - -end-sanitize-sky -start-sanitize-r5900 -Sun Mar 22 13:00:14 1998 Jeffrey A Law (law@cygnus.com) - - * vu0.h (vcallms): Use 'O' for call target operand. - * mips-dis.c (print_insn_arg): Handle 'O'. - -end-sanitize-r5900 -Fri Mar 20 18:55:18 1998 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Use AM_DISABLE_SHARED. - * aclocal.m4, configure: Rebuild with libtool 1.2. - -start-sanitize-r5900 -Fri Mar 20 09:01:31 1998 Jeffrey A Law (law@cygnus.com) - - * mips-dis.c: Change '%' to '#' in r5900 support. - * vu0.h: Likewise. - -end-sanitize-r5900 -Thu Mar 19 15:46:53 1998 Nick Clifton <nickc@cygnus.com> - - These patches are courtesy of Jonathan Walton and Tony Thompson - (athompso@cambridge.arm.com). - - * arm-dis.c (print_insn_thumb): Ignore bottom two bits of PC - relative addresses. - - * arm-opc.h (thumb_opcodes): Annotate PC relative addresses with - both the offset and the label closest to the destination. - -start-sanitize-r5900 -Thu Mar 19 13:53:25 1998 Jeffrey A Law (law@cygnus.com) - - * vu0.h: New file with cop2/vu0 instructions. - * mips-opc.c: Include vu0.h. - * mips-dis.c (print_insn_arg): Handle new args 0-9, +, -, %, K, &, - J, Q, X, and U. - (print_insn_mips): Do not emit a tab after an instruction if the - first arg is an instruction completer (&). If the next arg is an - escape character (%), then print the next arg verbatim. - * Makefile.am (mips-opc.lo): Depend on vu0.h - -end-sanitize-r5900 -start-sanitize-sky -Thu Mar 19 10:42:51 1998 Doug Evans <devans@canuck.cygnus.com> - - * dvp-opc.c (vif_opcodes): Add stcycl. - -Tue Mar 17 10:53:58 1998 Doug Evans <devans@canuck.cygnus.com> - - * dvp-dis.c (print_dma): Change length from 16 to 8. - -end-sanitize-sky -Sat Mar 14 23:47:14 1998 Doug Evans <devans@seba.cygnus.com> - - * m32r-opc.h: Regenerate. - -start-sanitize-sky -Thu Mar 12 09:18:54 1998 Doug Evans <devans@canuck.cygnus.com> - - * dvp-opc.c (print_dest1): Print dest spec again. - (print_vfreg,print_accdest): Likewise. - (vif_unpack_len): Round result up to word boundary. - -end-sanitize-sky -start-sanitize-vr4320 -Tue Mar 10 15:57:23 1998 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c ("clz","dclz"): Added the 4320 versions. - -Mon Mar 9 15:22:06 1998 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c ("macc*","mul*"): Added the 4320 versions - of these. - -end-sanitize-vr4320 -start-sanitize-sky -Fri Mar 6 11:27:53 1998 Doug Evans <devans@canuck.cygnus.com> - - * dvp-dis.c (print_gif): Fix length calcs for gifimage. - (print_insn): Do mask comparison on proper opcode word. - Print unsigned values in hex. - * dvp-opc.c (u_parse_sdest): Return -1 if dest missing. - (parse_bc): Catch missing dest. - (parse_vfreg): Replace atoi call with strtol. - (parse_{bcftreg,ffstreg,freg,ireg,vi01,gif_prim,gif_nloop}): Likewise. - (parse_bcftreg,parse_ffstreg): Handle missing dest. - (extract_gif_eop): New function. - (gif_operands): Update eop entry. - (VGIFOP,VGIFNREGS): Fix calcs. - (extract_gif_prim): Set *pinvalid to 1 if prim not used. - (gif_regs): Add entry for unused 11 case. - (print_gif_regs): Print empty list instead of nothing. - (extract_gif_nloop): Fix value calc. - (print_gif_nloop): Always print value, even if 0. - (insert_vif_wlcl,extract_vif_wlcl): New functions. - (vif_operands): Use them for wl,cl fields. - (state_vif_wl,state_vif_cl): New static locals. - (parse_vif_mode): Handle numeric args. - (vif_unpack_len_value,vif_unpack_len): New functions. - (vif_insn_len): Call vif_unpack_len. - -end-sanitize-sky -Wed Mar 4 12:08:14 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate. - -start-sanitize-cygnus -Tue Mar 3 18:51:22 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen-asm.in: Move insertion of generated routines to top of file. - (insert_normal): Add prototype. Delete `shift' arg. - * cgen-dis.in: Move insertion of generated routines to top of file. - (extract_normal): Add prototype. Delete `shift' arg. - (print_normal): Add prototype. Call CGEN_PRINT_NORMAL if defined. - (print_keyword): Add prototype. Fix type of `attrs' arg. - -end-sanitize-cygnus -start-sanitize-vr4320 -Tue Mar 3 11:47:58 1998 Gavin Koch <gavin@cygnus.com> - - * mips-dis.c (_print_insn_mips) : Handle bfd_mach_mips4320. - * mips-opc.c ("mac","dmac") : Added 4320 insns. - -end-sanitize-vr4320 -Sat Feb 28 16:02:34 1998 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (print_insn_big_arm, print_insn_little_arm): Do not - assume that info->symbols is non-empty. - -Sat Feb 28 12:19:05 1998 Richard Henderson <rth@cygnus.com> - - * alpha-opc.c (cvtqs) There is no such thing. - (cvttq): Missing most of the /*d variants. - -start-sanitize-r5900 -Fri Feb 27 13:16:42 1998 Andrew Cagney <cagney@b1.cygnus.com> - - * mips-opc.c (r5900/madd.s): Takes three operands, not four. Fix - opcode. - (r5900/min.s): Incorrect opcode ....,101001 not ...110000. - (r5900/msub.s): Takes three operands, not four. Fix opcode. - -end-sanitize-r5900 -Thu Feb 26 15:53:09 1998 Michael Meissner <meissner@cygnus.com> - - * d30v-opc.c (d30v_opcode_table): Indicate which instructions are - delayed branches or jumps. - -start-sanitize-sky -Fri Feb 27 10:04:19 1998 Doug Evans <devans@canuck.cygnus.com> - - * dvp-opc.c (vif_operands): Add unpack[u] support. - (vif_opcodes): Ditto. - (*_vif_imrubits): Renamed from *_vif_imrbits. - -Wed Feb 25 00:27:44 1998 Doug Evans <devans@canuck.cygnus.com> - - * dvp-dis.c (print_insn): Handle word number. - Handle mips address vs vu address. - * dvp-opc.c (vif_operands): Use DVP_OPERAND_VU_ADDRESS. - (dma_operands): Use DVP_OPERAND_MIPS_ADDRESS. - ({insert,extract}_dma_addr): Fix word ofset. - ({insert,print}_gif_regs): Fix encode/decode. - -end-sanitize-sky -Tue Feb 24 10:46:44 1998 Doug Evans <devans@canuck.cygnus.com> - - * arm-dis.c (print_insn_{big,little}_arm): info->symbol changed - to *info->symbols. - * mips-dis.c (print_insn_{big,little}_mips): Likewise. - * tic30-dis.c (print_branch): Likewise. -start-sanitize-sky - * mips-dis.c (print_insn_little_mips): Call dvp_info_mach_type. - * dvp-dis.c (dvp_info_mach_type): New function. - (print_insn_dvp): Call it. - (print_vif): Return length of 4 if mpg or direct insn so following - insns get properly disabled. - (print_gif): Fix word order. - * dvp-opc.c (vif_insn_len): New argument `pcpu'. All callers updated. - (gif_operands): Fix word order. - (gif_opcodes): Likewise. - ({insert,extract,print}_gif_regs): Likewise. - (gif_regs): Add new register number/name changes. - (dma_opcodes): Add dmarefe insn. -end-sanitize-sky - -Tue Feb 24 11:06:18 1998 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (print_insn_big_arm, print_insn_little_arm): Remove - saved_symbol code as it is no longer needed. - -Mon Feb 23 13:16:17 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen-asm.c: Include symcat.h. - * cgen-dis.c,cgen-opc.c: Ditto. -start-sanitize-cygnus - * cgen-asm.in,cgen-dis.in: Ditto. -end-sanitize-cygnus - * m32r-asm.c,m32r-dis.c,m32r-opc.h,m32r-opc.c: Regenerate. - -start-sanitize-sky -Mon Feb 23 09:51:39 1998 Doug Evans <devans@canuck.cygnus.com> - - * dvp-opc.c (extra_dma_flags): Fix typos. - (dma_operands): Fix word numbers. - (dma_opcodes): Likewise. - ({insert,extract}_dma_flags): Likewise. - -end-sanitize-sky -Mon Feb 23 10:34:58 1998 Jeffrey A Law (law@cygnus.com) - - * mips-dis.c (print_insn_arg): Do not prefix 'P' arguments with '$'. - -start-sanitize-sky -Fri Feb 20 18:02:20 1998 Doug Evans <devans@canuck.cygnus.com> - - * dvp-dis.c (print_gif): Complete. - * dvp-opc.c (gif_operands,gif_opcodes): Complete. - (state_gif_{nregs,regs,nloop}): New static locals. - (*_gif_*): Complete. - (dvp_opcode_init_{parse,print}): Init gif state locals. - (extract_vif_datalen,{insert,extract}_vif_imrbits): New functions. - (vif_insn_len): Handle `unpack'. - ({insert,extract}_dma_flags): Complete. - -end-sanitize-sky -start-sanitize-r5900 -Fri Feb 20 01:23:16 1998 Jeffrey A Law (law@cygnus.com) - - * mips-opc.c (mula.s): Renamed from multa.s. - -end-sanitize-r5900 -Thu Feb 19 16:51:13 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.[ch]: Regenerate. - -start-sanitize-sky -Thu Feb 19 02:11:39 1998 Doug Evans <devans@charmed.cygnus.com> - - * dvp-opc.c (dma_operands): Rewrite. - (dma_operand_{count,addr}): New globals. - (dma_opcodes): Rewrite. Add "dmaend" with no operands. - (insert_dma_addr): Insert value into insn. - (extract_dma_addr): Extract value from insn. - -Wed Feb 18 15:46:46 1998 Doug Evans <devans@canuck.cygnus.com> - - * dvp-dis.c (print_vu): Handle loi insns. - (print_insn): Likewise. - * dvp-opc.c (vu_lower_opcodes): Add "loi". - (vu_operands): Make LDEST1 a FAKE operand. - (parse_dest1): Allow elided argument. - (print_dest1): Don't print the argument. - -Tue Feb 17 18:48:25 1998 Doug Evans <devans@canuck.cygnus.com> - - * dvp-opc.c (parse_vfreg): Dest spec is optional. - (print_vfreg): Don't print dest spec. - (parse_accdest): Dest spec is optional. - (print_accdest): Don't print dest spec. - -end-sanitize-sky -Tue Feb 17 17:14:50 1998 Doug Evans <devans@seba.cygnus.com> - -start-sanitize-cygnus - * Makefile.am (CGENFILES): Update. - * Makefile.in: Regenerate. - * cgen-asm.in (insert_normal): Result is error message now. - Validate value to be inserted. - (insert_insn_normal): Result is error message now. - (@arch@_cgen_assemble_insn): Update. -end-sanitize-cygnus - * cgen-asm.c (cgen_parse_{signed,unsigned}_integer): Delete min,max - arguments. Don't perform validation here. - * m32r-asm.c,m32r-dis.c,m32r-opc.c: Regenerate. - -Fri Feb 13 14:26:06 1998 Doug Evans <devans@canuck.cygnus.com> - -start-sanitize-cygnus - * cgen-opc.in (@arch@_cgen_get_insn_operands): Handle empty - operand instance list. -end-sanitize-cygnus - * m32r-opc.c: Regenerate. - -Fri Feb 13 14:53:02 1998 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.am (AUTOMAKE_OPTIONS): Define. - * configure, Makefile.in, aclocal.m4: Rebuild with automake 1.2e. - -Fri Feb 13 10:21:09 1998 Mark Alexander <marka@cygnus.com> - - * m10300-dis.c (print_insn_mn10300): Recognize break instruction. - -Fri Feb 13 13:12:14 1998 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Get the version number from BFD. - * configure: Rebuild. - - From H.J. Lu <hjl@gnu.org>: - * Makefile.am (libopcodes_la_LDFLAGS): Define. - * Makefile.in: Rebuild. - -Fri Feb 13 09:50:32 1998 Nick Clifton <nickc@cygnus.com> - - * m32r-opc.c: Regenerate. - * m32r-opc.h: Regenerate. - -Thu Feb 12 11:01:40 1998 Doug Evans <devans@canuck.cygnus.com> - -start-sanitize-cygnus - * cgen-opc.in (@arch@_cgen_lookup_insn): New argument alias_p. - Ignore ALIAS insns if asked to. - (@arch@_cgen_get_insn_operands): Pass 0 for alias_p, NULL for insn. -end-sanitize-cygnus - * m32r-opc.c: Regenerate. - -start-sanitize-sky - * dvp.opc.c: Nicely format opcode tables. - (vu_operands): New element UFLAGS. - (parse_uflags,print_uflags): New functions. - (vu_upper_opcodes): Add UFLAGS to all insns. - -end-sanitize-sky -Thu Feb 12 03:41:00 1998 J"orn Rennecke <amylaar@cygnus.co.uk> - - Fix rac to accept only a0: - * d10v-opc.c (d10v_predefined_registers, d10v_operands, d10v_opcodes): - Split OPERAND_ACC into OPERAND_ACC0 and OPERAND_ACC1. - Introduce OPERAND_GPR. - * d10v-dis.c (print_operand): Likewise. - -Wed Feb 11 18:58:34 1998 Doug Evans <devans@seba.cygnus.com> - -start-sanitize-cygnus - * cgen-opc.in: New file. - * cgen.sh: Translate @ARCH@. Cat cgen-opc.in into @arch@-opc.c. - * Makefile.am (CGENFILES): Add cgen-opc.in. - * Makefile.in: Regenerate. - * cgen-dis.in (*): Use PTR instead of void *. - (print_insn): Delete unused vars `i', `syntax'. -end-sanitize-cygnus - * cgen-opc.c (cgen_set_cpu): Delete init of hw list `next' chain. - (cgen_hw_lookup): Make result const. - * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate. - -start-sanitize-sky -Tue Feb 10 14:56:24 1998 Doug Evans <devans@canuck.cygnus.com> - - * dvp-opc.c (*): pke,gpuif renamed to vif,gif. - (vif_opcodes): Update renamed insns. - * dvp-dis.c (*): Likewise. - -end-sanitize-sky -Sat Feb 7 15:30:27 1998 Ian Lance Taylor <ian@cygnus.com> - - * configure, aclocal.m4: Rebuild with new libtool. - -Thu Feb 5 17:56:10 1998 Michael Meissner <meissner@cygnus.com> - - * d30v-opc.c (repeat{,i} instructions): Repeat/repeati - instructions use a PC relative branch, not absolute. - -Wed Feb 4 19:17:37 1998 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Set libtool_enable_shared rather than - libtool_shared. Remove diversion hack. - * configure, Makefile.in, aclocal.m4: Rebuild with new libtool. - -Tue Feb 3 17:19:40 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen-opc.c (cgen_set_cpu): Initialize hardware table. - * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate. - -Mon Feb 2 19:22:15 1998 Steve Haworth <steve@pm.cse.rmit.EDU.AU> - - * tic30-dis.c: New file. - * disassemble.c (disassembler): Add bfd_arch_tic30 case. - * configure.in: Handle bfd_tic30_arch. - * Makefile.am: Rebuild dependencies. - (CFILES): Add tic30-dis.c - (ALL_MACHINES): Add tic30-dis.lo. - * configure, Makefile.in: Rebuild. - -start-sanitize-cygnus -Mon Feb 2 11:04:08 1998 Nick Clifton <nickc@cygnus.com> - - * m32r-opc.c, m32r-opc.h, m32r-asm.c m32r-dis.c: Newly generated - versions after updates to m32r.cpu to remove mulwhi-a, mulwlo-a, - macwhi-a and macwlo-a instructions. - -end-sanitize-cygnus -start-sanitize-sky -Fri Jan 30 17:39:21 1998 Ian Carmichael <iancarm@cygnus.com> - - * dvp-opc.c, fixed encoding of a bunch of instructions to - be consistent with the asmvu assembler (and inconsistent - with the specification). - -Thu Jan 29 18:14:56 1998 Ian Carmichael <iancarm@cygnus.com> - - * dvp-opc.c, fixed order of pkemscal/pkemscalf instructions - in the opcode table. The pkemscalf instruction must come first. - -Thu Jan 29 16:47:24 1998 Ian Carmichael <iancarm@cygnus.com> - - * dvp-opc.c, MAXIi should be VUOP6(0x1d) instead of 0x2d. - -end-sanitize-sky -Thu Jan 29 13:02:56 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.h (HAVE_CPU_M32R): Define. - -start-sanitize-sky -Wed Jan 28 13:46:19 1998 Doug Evans <devans@canuck.cygnus.com> - - * dvp-dis.c, dvp-opc.c: New files. - * configure.in: Compile them if bfd_dvp_arch, as well as mips. - * configure: Regenerate. - * Makefile.am (ALL_MACHINES): Add dvp-{dis,opc}.lo. - (dvp-dis.lo,dvp-opc.lo): Add rules for. - (mips-dis.lo): Compile with @archdefs@. - * Makefile.in: Regenerate. - * disassemble.c: Define ARCH_mips ifdef ARCH_dvp. - * mips-dis.c (print_insn_little_mips): Check for DVP insns. - -end-sanitize-sky -Wed Jan 28 09:55:03 1998 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c (insertion routines): If both alignment and size is - wrong then report this. - -Tue Jan 27 21:52:59 1998 Jeffrey A Law (law@cygnus.com) - - * mips-dis.c (_print_insn_mips): Set target_processor as appropriate. - Only recognize instructions for the current target_processor. - -Thu Jan 22 16:20:17 1998 Fred Fish <fnf@cygnus.com> - - * d10v-dis.c (PC_MASK): Correct value. - (print_operand): If there's a reloc, don't calculate the - address because they could be in different sections. - -start-sanitize-cygnus -Thu Jan 22 16:10:32 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.sh: Rewrite to be like simulator's version. - * Makefile.am (cgen): Update call to cgen.sh. - * Makefile.in: Regenerate - -end-sanitize-cygnus -Fri Jan 16 15:29:11 1998 Jim Blandy <jimb@zwingli.cygnus.com> - - * mips-opc.c (mips_builtin_opcodes): Move 4010's "addciu" - instruction after the 4650's "mul" instruction; nobody's using the - 4010 these days. If object files someday indicate which processor - variant they're intended for, we can do a better job at this. - -start-sanitize-r5900 -Tue Jan 13 09:21:56 1998 Jeffrey A Law (law@cygnus.com) - - * mips-opc.c (c.lt.s): Add r5900 variant. - (c.le.s): Likewise. - -end-sanitize-r5900 -Mon Jan 12 14:43:54 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen-asm.c (build_asm_hash_table): Traverse compiled in table using - table provided entry size. Use CGEN_INSN_MNEMONIC. - (cgen_parse_keyword): Rewrite. - * cgen-dis.c (build_dis_hash_table): Traverse compiled in table using - table provided entry size. Use CGEN_INSN_MASK_BITSIZE. - * cgen-opc.c: Clean up pass over `struct foo' usage. - (cgen_keyword_lookup_value): Handle "" entry. - (cgen_keyword_add): Likewise. -start-sanitize-cygnus - * Makefile.am: Add cgen support. - * Makefile.in: Regenerate. - * configure.in: Add cgen support. - * configure: Regenerate. - * aclocal.m4: Regenerate. - * cgen.sh, cgen-asm.in, cgen-dis.in: New files. -end-sanitize-cygnus - -Mon Dec 22 12:37:06 1997 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c: Add FP_D to s.d instruction flags. - -Wed Dec 17 11:38:29 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-opc.c (halt, pulse): Enable them on the 68060. - -start-sanitize-tic80 -Tue Dec 16 15:22:53 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_opcodes): Revert change that put the 32 bit - PC relative offset forms before the 15 bit forms. An assembler command - line option now chooses the default. - -end-sanitize-tic80 -start-sanitize-r5900 -Tue Dec 16 13:24:22 1997 Jeffrey A Law (law@cygnus.com) - - * mips-opc.c: Add many missing r5900 instructions. - -end-sanitize-r5900 -Tue Dec 16 15:22:51 1997 Michael Meissner <meissner@cygnus.com> - - * d30v-opc.c (d30v_opcode_table): Set new flags bits - FLAG_{2WORD,MUL{16,32},ADDSUBppp}, in appropriate instructions. - -1997-12-15 Brendan Kehoe <brendan@lisa.cygnus.com> - - * configure: Only build libopcodes shared if --enable-shared's value - was `yes', or was set to `*opcodes*'. - * aclocal.m4: Likewise. - * NOTE: this really needs to be fixed in libtool/libtool.m4, the - original source of this bit of code. It's not clear what the best fix - would be, though. - -start-sanitize-r5900 -Mon Dec 15 12:43:36 1997 Jeffrey A Law (law@cygnus.com) - - * mips-opc.c (mtpc, mfpc, mtps, mfps): Add r5900 variants. -end-sanitize-r5900 -start-sanitize-tic80 -Fri Dec 12 11:57:04 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (OFF_SL_PC, OFF_SL_BR): Minor formatting change. - (tic80_opcodes): Reorder table entries to put the 32 bit PC relative - offset forms before the 15 bit forms, to default to the long forms. - -end-sanitize-tic80 -Fri Dec 12 01:32:30 1997 Richard Henderson <rth@cygnus.com> - - * alpha-opc.c (cvttq/*u*): Remove, as that suffix is invalid. - -Wed Dec 10 17:42:35 1997 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (print_insn_little_arm): Prevent examination of stored - symbol if none is present. - (print_insn_big_arm): Prevent examination of stored symbol if - none is present. - -Thu Oct 23 21:13:37 1997 Fred Fish <fnf@cygnus.com> - - * d10v-opc.c (d10v_opcodes): Correct entry for RTE. - -Mon Dec 8 11:21:07 1997 Nick Clifton <nickc@cygnus.com> - - * disassemble.c: Remove disasm_symaddr() function. - - * arm-dis.c: Use info->symbol instead of info->flags to determine - if disassmbly should be in Thumb or Arm mode. - -Tue Dec 2 09:54:27 1997 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c: Add support for disassembling Thumb opcodes. - (print_insn_thumb): New function. - - * disassemble.c (disasm_symaddr): New function. - - * arm-opc.h: Display nop pseudo ops alongside equivalent disassembly. - (thumb_opcodes): Table of Thumb opcodes. - -Mon Dec 1 12:25:57 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-opc.c (btst): Change Dd@s to Dd;b. - - * m68k-dis.c (print_insn_arg): Recognize 'm', 'n', 'o', 'p', 'q', - and 'v' as operand types. - -Mon Dec 1 11:56:50 1997 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: Add argument for lpstop. From Olivier Carmona - <olivier.carmona@di.epfl.ch>. - * m68k-dis.c (print_insn_m68k): Handle special case of lpstop, - which has a two word opcode with a one word argument. - -Sun Nov 23 22:25:21 1997 Michael Meissner <meissner@cygnus.com> - - * d30v-opc.c (d30v_opcode_table, case cmpu): Immediate field is - unsigned, not signed. - (d30v_format_table): Add SHORT_CMPU cases for cmpu. - -Wed Nov 19 17:42:35 1997 Richard Henderson <rth@cygnus.com> - - * sh-dis.c (print_insn_shx): Recognize all sh4 additions. - * sh-opc.h (fmov): Add @<REG_M>+,<DX_REG_N> variant for sh4. - (ftrv): Slay the cut-and-paste monster. - -Tue Nov 18 23:10:03 1997 J"orn Rennecke <amylaar@cygnus.co.uk> - - * d10v-dis.c (print_operand): - Split OPERAND_FLAG into OPERAND_FFLAG and OPERAND_CFLAG. - -Tue Nov 18 18:45:14 1997 J"orn Rennecke <amylaar@cygnus.co.uk> - - * d10v-opc.c (OPERAND_FLAG): Split into: - (OPERAND_FFLAG, OPERAND_CFLAG) . - (FSRC): Split into: - (FFSRC, CFSRC). - -Thu Nov 13 11:05:33 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c: Move the INSN_MACRO ISA value to the membership - field for all INSN_MACRO's. - * mips16-opc.c: same - -Wed Nov 12 10:16:57 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c (sync,cache): These are 3900 insns. - -Tue Nov 11 23:53:41 1997 J"orn Rennecke <amylaar@cygnus.co.uk> - - sh-opc.h (sh_table): Remove ftst/nan. - -start-sanitize-cygnus -Mon Nov 3 13:23:15 1997 Ken Raeburn <raeburn@cygnus.com> - - * mips-opc.c (dror32, dror, rzu.ob): Fix bugs in encoding. - (c.*.ob, mula.ob, mull.ob, muls.ob, mulsl.ob): Put 'k' version - last. - * mips-dis.c (print_insn_arg): Handle VR5400 operand types. - -end-sanitize-cygnus -start-sanitize-tx49 -Wed Oct 29 15:10:56 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c (deret,dmult,dmultu,madd,maddu,pref,sdbbp): - Add tx49 insns and configury. - -end-sanitize-tx49 -Tue Oct 28 17:59:32 1997 Ken Raeburn <raeburn@cygnus.com> - - * mips-opc.c (ffc, ffs): Fix mask. - -Tue Oct 28 16:34:54 1997 Michael Meissner <meissner@cygnus.com> - - * d30v-opc.c (pre_defined_registers): Add eit_vb, int_s, and int_m - control registers. - -Mon Oct 27 22:34:03 1997 Ken Raeburn <raeburn@cygnus.com> - - * mips-opc.c: Fix bug in mask for "not" pseudo-instruction. -start-sanitize-cygnus - Added VR5400 instructions. - (N5): New cpu-id macro. -end-sanitize-cygnus - (WR_HILO, RD_HILO, MOD_HILO): New macros. - -Mon Oct 27 22:34:03 1997 Ken Raeburn <raeburn@cygnus.com> - - * mips-opc.c: Fix bug in mask for "not" pseudo-instruction. - (WR_HILO, RD_HILO, MOD_HILO): New macros. - -Thu Oct 23 14:57:58 1997 Nick Clifton <nickc@cygnus.com> - - * v850-dis.c (disassemble): Replace // with /* ... */ - -Wed Oct 22 17:33:21 1997 Richard Henderson <rth@cygnus.com> - - * sparc-opc.c: Add wr & rd for v9a asr's. - * sparc-dis.c (print_insn_sparc): Recognize '_' and '/' for v9a asr's. - (v9a_asr_reg_names): New variable. - Patch from David Miller <davem@vger.rutgers.edu>. - -Wed Oct 22 17:18:02 1997 Richard Henderson <rth@cygnus.com> - - * sparc-opc.c (v9notv9a): New insn type. - (IMPDEP): Move to the end to not conflict with edge8 et al. - Patch from David Miller <davem@vger.rutgers.edu>. - -Fri Oct 17 13:18:53 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c (bnezl,beqzl): Mark these as also tx39. - -Thu Oct 16 11:55:20 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c: Note that 'jalx' is (probably incorrectly) marked I1. - -Tue Oct 14 16:10:31 1997 Nick Clifton <nickc@cygnus.com> - - * v850-dis.c (disassemble): Use new symbol_at_address_func() field - of disassemble_info structure to determine if an overlay address - has a matching symbol in low memory. - - * dis-buf.c (generic_symbol_at_address): New (dummy) function for - new symbol_at_address_func field in disassemble_info structure. - -Fri Oct 10 16:44:52 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c (extract_d22): Use signed arithmatic. - -Tue Oct 7 23:40:43 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c: Three op mult is not an ISA insn. - -Tue Oct 7 23:37:21 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c: Fix formatting. - -Fri Oct 3 17:26:54 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386-dis.c (OP_E): Explicitly sign extend 8 bit values, rather - than assuming that char is signed. Explicitly sign extend 16 bit - values, rather than assuming that short is 16 bits. - (OP_sI, OP_J, OP_DIR): Likewise. - -Thu Oct 2 13:36:45 1997 Nick Clifton <nickc@cygnus.com> - - * v850-dis.c (v850_sreg_names): Use symbolic names for higher - system registers. - -Wed Oct 1 16:58:54 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c: Fix typo in comment. - - * v850-dis.c (disassemble): Add test of processor type when - determining opcodes. - -Wed Oct 1 14:10:20 1997 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Use a diversion to set enable_shared before the - arguments are parsed. - * configure: Rebuild. - -Thu Sep 25 13:04:59 1997 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c (TBL1): Use ! rather than `. - * m68k-dis.c (print_insn_arg): Remove ` operand specifier. - -Wed Sep 24 11:29:35 1997 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: Correct bchg, bclr, bset, and btst on ColdFire. - - * m68k-opc.c: Accept tst{b,w,l} with immediate operands on cpu32. - - * m68k-opc.c: Correct movew of an immediate operand to %sr or %ccr - for mcf5200. - - * configure.in: Call AC_CHECK_TOOL before AM_PROG_LIBTOOL. - * aclocal.m4: Rebuild with new libtool. - * configure: Rebuild. - -Fri Sep 19 11:45:49 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * v850-opc.c ("cmov"): Order reg param r1, r2 not r2, r2. - -Thu Sep 18 11:21:43 1997 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparclet_cpreg_table): Add %ccsr2, %cccrr, %ccrstr. - -Tue Sep 16 15:18:20 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c (v850_opcodes): Further rearrangements. - -Tue Sep 16 16:12:11 1997 Ken Raeburn <raeburn@cygnus.com> - - * d30v-opc.c (rot2h, sra2h, srl2h insns): Revert last change. - -Tue Sep 16 09:48:50 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c (v850_opcodes): Fields reordered to allow assembler - parser to work. - -Tue Sep 16 10:01:00 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c: Added tx39 insns sdbbp, rfe, and deret. -start-sanitize-tx19 - * mips16-opc.c: Added mips16 sdbbp. -end-sanitize-tx19 - -Mon Sep 15 18:31:52 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c: Initialise processors field of v850_opcode structure. - -Wed Aug 27 21:42:39 1997 Ken Raeburn <raeburn@cygnus.com> - - Merge changes from Martin Hunt: - - * d30v-opc.c: Change mvfacc to accept 6-bit unsigned values. - - * d30v-opc.c (pre_defined_registers): Add control registers from 0-63. - (d30v_opcode_tabel): Add dbt, rtd, srah, and srlh instructions. Fix - rot2h, sra2h, and srl2h to use new SHORT_A5S format. - - * d30v-dis.c (print_insn): Fix disassembly of SHORT_D2 opcodes. - - * d30v-dis.c (print_insn): First operand of d*i (delayed - branch) instructions is relative. - - * d30v-opc.c (d30v_opcode_table): Change form for repeati. - (d30v_operand_table): Add IMM6S3 type. - (d30v_format_table): Change SHORT_D2. Add LONG_Db. - - * d30v-dis.c: Fix bug with ".s" and ".l" extensions - and cmp instructions. - - * d30v-opc.c: Correct entries for repeat*, and sat*. - Make IMM5 unsigned. Create IMM6U and IMM12S3U operand - types. Correct several formats. - - * d30v-opc.c: (pre_defined_registers): Add dpsw and dpc. - - * d30v-opc.c (pre_defined_registers): Change control registers. - - * d30v-opc.c (d30v_format_table): Correct SHORT_C1 and - SHORT_C2. Manual was incorrect. - - * d30v-dis.c (lookup_opcode): Return value now indicates - if an opcode has a short and a long form. Used for deciding - to append a ".s" or ".l". - (print_insn): Append a ".s" to an instruction if it is - the short form and ".l" if it is a long form. Do not append - anything if the instruction has only one possible size. - - * d30v-opc.c: Change mulx2h to require an even register. - New form: SHORT_A2; a SHORT_A form that needs an even - register as the first operand. - - * d30v-dis.c (print_insn_d30v): Fix problem where the last - instruction was not being disassembled if there were an odd - number of instructions. - - * d30v-opc.c (SHORT_M2, LONG_M2): Two new forms. - -Fri Sep 12 11:43:54 1997 Nick Clifton <nickc@cygnus.com> - - * v850-dis.c (disassemble): Improved display of register lists. - -Thu Sep 11 17:35:10 1997 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparc_opcodes): Fix assembler args to - fzeros, fones, fsrc1, fsrc1s, fsrc2s, fnot1, fnot1s, fnot2s, - fors, fnors, fands, fnands, fxors, fxnors, fornot1s, fornot2s, - fandnot1s, fandnot2s. - -Tue Sep 9 10:03:49 1997 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparc_opcodes): Fix op3 field for fcmpq/fcmpeq. - -Mon Sep 8 14:06:59 1997 Doug Evans <dje@canuck.cygnus.com> - - * cgen-asm.c (cgen_parse_address): New argument resultp. - All callers updated. - * m32r-asm.c (parse_h_hi16): Right shift numbers by 16. - -Tue Sep 2 18:39:08 1997 Jeffrey A Law (law@cygnus.com) - - * mn10200-dis.c (disassemble): PC relative instructions are - relative to the next instruction, not the current instruction. - -Tue Sep 2 15:41:55 1997 Nick Clifton <nickc@cygnus.com> - - * v850-dis.c (disassemble): Only signed extend values that are not - returned by extract functions. - Remove use of V850_OPERAND_ADJUST_SHORT_MEMORY flag. - -Tue Sep 2 15:39:40 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c: Update comments. Remove use of - V850_OPERAND_ADJUST_SHORT_MEMORY. Fix several operand patterns. - -Tue Aug 26 09:42:28 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c (MOVHI): Immediate parameter is unsigned. - -Mon Aug 25 15:58:07 1997 Christopher Provenzano <proven@cygnus.com> - - * configure: Rebuilt with latest devo autoconf for NT support. - -Fri Aug 22 10:35:15 1997 Nick Clifton <nickc@cygnus.com> - - * v850-dis.c (disassemble): Use curly brace syntax for register - lists. - - * v850-opc.c (v850_opcodes[]): Add NOT_R0 flag to decect cases - where r0 is being used as a destination register. - -Thu Aug 21 11:09:09 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c (v850_opcodes[]): Move divh opcodes next to each other. - -Wed Aug 20 00:43:11 1997 J"orn Rennecke <amylaar@cygnus.co.uk> - - * sh-opc.h (sh_arg_type): Add A_SGR and A_DBR. - (sh_nibble_type, sh_arg_type): Add SH4 floating point extensions. - (sh_table): Likewise. Add movca.l, ocbi, ocbp, ocbwb. - Add insns to access SGR and DBR. - * sh-dis.c (print_insn_shx): Add SH4 floating point extensions. - -Tue Aug 19 10:59:59 1997 Richard Henderson <rth@cygnus.com> - - * alpha-opc.c (alpha_opcodes): Fix hw_rei_stall mungage. - -Mon Aug 18 11:10:03 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c (v850_opcodes[]): Remove use of flag field. - * v850-opc.c (v850_opcodes[]): Add support for reversed short load - opcodes.. - -Mon Aug 18 11:08:25 1997 Nick Clifton <nickc@cygnus.com> - - * configure (cgen_files): Add support for v850e target. - * configure.in (cgen_files): Add support for v850e target. - -Mon Aug 18 11:08:25 1997 Nick Clifton <nickc@cygnus.com> - - * configure (cgen_files): Add support for v850ea target. - * configure.in (cgen_files): Add support for v850ea target. - -Fri Aug 15 05:17:48 1997 Doug Evans <dje@canuck.cygnus.com> - - * configure.in (bfd_arc_arch): Add. - * configure: Rebuild. - * Makefile.am (ALL_MACHINES): Add arc-dis.lo, arc-opc.lo. - * Makefile.in: Rebuild. - * arc-dis.c, arc-opc.c: New files. - * disassemble.c (ARCH_all): Define ARCH_arc. - (disassembler): Add ARC support. - -Wed Aug 13 18:52:11 1997 Nick Clifton <nickc@cygnus.com> - - * v850-dis.c (disassemble): Add support for v850EA instructions. - - * v850-opc.c (insert_i5div, extract_i5div): New Functions. - (v850_opcodes): Add v850EA instructions. - - * v850-dis.c (disassemble): Add support for v850E instructions. - - * v850-opc.c (insert_d5_4, extract_d5_4, insert_d16_16, - extract_d16_16, insert_i9, extract_i9, insert_u9, extract_u9, - insert_spe, extract_spe): New Functions. - (v850_opcodes): Add v850E instructions. - - * v850-opc.c: Reorganised and re-layed out to improve readability - and portability. - -Tue Aug 5 23:09:31 1997 Ian Lance Taylor <ian@cygnus.com> - - * configure: Rebuild with autoconf 2.12.1. - -Mon Aug 4 12:02:16 1997 Ian Lance Taylor <ian@cygnus.com> - - * aclocal.m4, configure: Rebuild with new automake patches. - -Fri Aug 1 13:02:04 1997 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Set enable_shared before AM_PROG_LIBTOOL. - * acinclude.m4: Just include acinclude.m4 from BFD. - * aclocal.m4, configure: Rebuild. - -Thu Jul 31 21:44:42 1997 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.am: New file, based on old Makefile.in. - * acconfig.h: New file. - * acinclude.m4: New file. - * stamp-h.in: New file. - * configure.in: Call AM_INIT_AUTOMAKE and AM_PROG_LIBTOOL. - Removed shared library handling; now handled by libtool. Replace - AC_CONFIG_HEADER with AM_CONFIG_HEADER. Call AM_MAINTAINER_MODE, - AM_CYGWIN32, and AM_EXEEXT. Replace AC_PROG_INSTALL with - AM_PROG_INSTALL. Change all .o files to .lo. Remove stamp-h - handling in AC_OUTPUT. - * dep-in.sed: Change .o to .lo. - * Makefile.in: Now built with automake. - * aclocal.m4: Now built with aclocal. - * config.in, configure: Rebuild. - -Mon Jul 28 21:52:24 1997 Jeffrey A Law (law@cygnus.com) - - * mips-opc.c: Fix typo/thinko in "eret" instruction. - -start-sanitize-r5900 -Mon Jul 28 22:07:14 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * mips-opc.c: Fix coding of mtsa. - -end-sanitize-r5900 -Thu Jul 24 13:03:26 1997 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparc_opcodes): Fix spelling on fpaddX, fpsubX insns. - Make array const. - * sparc-dis.c (sorted_opcodes): New static local. - (struct opcode_hash): `opcode' is pointer to const element. - (build_hash): First arg is now table of sorted pointers. - (print_insn_sparc): Sort opcodes by sorting table of pointers. - (compare_opcodes): Update. - -Tue Jul 15 12:05:23 1997 Doug Evans <dje@canuck.cygnus.com> - - * cgen-opc.c: #include <ctype.h>. - (hash_keyword_name): New arg `case_sensitive_p'. Callers updated. - Handle case insensitive hashing. - (hash_keyword_value): Change type of `value' to unsigned int. - -Thu Jul 10 12:56:10 1997 Jeffrey A Law (law@cygnus.com) - - * mips-opc.c (mips_builtin_opcodes): If an insn uses single - precision FP, mark it as such. Likewise for double precision - FP. Mark ISA1 insns. Consolidate duplicate opcodes where - possible. -start-sanitize-r5900 - (mips_builtin_opcodes): Remove non-existant r5900 instructions -end-sanitize-r5900 - -start-sanitize-r5900 -Thu Jun 26 16:20:27 1997 Jeffrey A Law (law@cygnus.com) - - * mips-opc.c (mips_builtin_opcodes): Add "pinteh", "pexeh" and - "pexew" as synonyms for "pintoh", "pexoh", "pexow". - -end-sanitize-r5900 -Wed Jun 25 15:25:57 1997 Felix Lee <flee@cirdan.cygnus.com> - - * ppc-opc.c (extract_nsi): make unsigned expression signed before - negating it. - (UNUSED): remove one level of parens, so MSVC doesn't choke on - nesting depth when all the macros are expanded. - -Tue Jun 17 17:02:17 1997 Ian Lance Taylor <ian@cygnus.com> - - * sparc-opc.c: The fcmp v9a instructions take an integer register - as a destination, not a floating point register. From Christian - Kuehnke <Christian.Kuehnke@arbi.Informatik.Uni-Oldenburg.DE>. - -Mon Jun 16 14:13:18 1997 Ian Lance Taylor <ian@cygnus.com> - - * m68k-dis.c (print_insn_arg): Print case 7.2 using %pc@() - syntax. From Roman Hodek - <rnhodek@faui22c.informatik.uni-erlangen.de>. - - * i386-dis.c (twobyte_has_modrm): Fix pand. - -Mon Jun 16 14:08:38 1997 Michael Taylor <mbt@mit.edu> - - * i386-dis.c (dis386_twobyte): Fix pand and pandn. - -Tue Jun 10 11:26:47 1997 H.J. Lu <hjl@gnu.ai.mit.edu> - - * arm-dis.c: Add prototypes for arm_decode_shift and - print_insn_arm. - -Mon Jun 2 11:39:04 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c: Add r3900 insns. - -Tue May 27 15:55:44 1997 Ian Lance Taylor <ian@cygnus.com> - - * sh-dis.c (print_insn_shx): Change relmask to bfd_vma. Don't - print delay slot instructions on the same line. When using a PC - relative load, add a comment with the value being loaded if it can - be obtained. - -Tue May 27 11:02:08 1997 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c (dis386[], dis386_twobyte[]): change pushl/popl - to pushS/popS for segment regs and byte constant so that - pushw/popw printed when in 16 bit data mode. - - * i386-dis.c (dis386[]): change cwtl, cltd to cWtS, cStd to - print cbtw, cwtd in 16 bit data mode. - * i386-dis.c (putop): extra case W to support above. - - * i386-dis.c (print_insn_x86): print addr32 prefix when given - address size prefix in 16 bit address mode. - -Fri May 23 16:47:23 1997 Ian Lance Taylor <ian@cygnus.com> - - * sh-dis.c: Reindent. Rename local variable fprintf to - fprintf_fn. - -Thu May 22 14:06:02 1997 Doug Evans <dje@canuck.cygnus.com> - - * m32r-opc.c (m32r_cgen_insn_table, cmpui): Undo patch of May 2. - -Tue May 20 11:26:27 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c (mips_builtin_opcodes): Moved INSN_ISA field into new - field membership. - * mips16-opc.c (mip16_opcodes): same. - -Mon May 12 15:10:53 1997 Jim Wilson <wilson@cygnus.com> - - * m68k-opc.c (moveb): Change $d to %d. - -Mon May 5 14:28:41 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386-dis.c: (dis386_twobyte): Add MMX instructions. - (twobyte_has_modrm): Likewise. - (grps): Likewise. - (OP_MMX, OP_EM, OP_MS): New static functions. - - * i386-dis.c: Revert patch of April 4. The output now matches - what gcc generates. - -Fri May 2 12:48:37 1997 Doug Evans <dje@canuck.cygnus.com> - - * m32r-opc.c (m32r_cgen_insn_table, cmpui): Use $uimm16 instead - of $simm16. - -Thu May 1 15:34:15 1997 Doug Evans <dje@canuck.cygnus.com> - - * m32r-opc.h (CGEN_ARCH): Renamed from CGEN_CPU. - -Tue Apr 15 12:40:08 1997 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (install): Depend upon installdirs. - (installdirs): New target. - -Mon Apr 14 12:13:51 1997 Ian Lance Taylor <ian@cygnus.com> - - From Thomas Graichen <graichen@rzpd.de>: - * configure.in: Use ${CONFIG_SHELL} when running $ac_config_sub. - * configure: Rebuild. - -Sun Apr 13 17:50:41 1997 Doug Evans <dje@canuck.cygnus.com> - - * cgen-*.c, m32r-*.c: #include sysdep.h instead of config.h. - Delete string{,s}.h support. - -Thu Apr 10 14:44:56 1997 Doug Evans <dje@canuck.cygnus.com> - - * cgen-asm.c (cgen_parse_operand_fn): New global. - (cgen_parse_{{,un}signed_integer,address}): Update call to - cgen_parse_operand_fn. - (cgen_init_parse_operand): New function. - * m32r-asm.c (parse_insn_normal): cgen_init_parse_operand renamed - from cgen_asm_init_parse. - (m32r_cgen_assemble_insn): New operand `errmsg'. - Delete call to as_bad, return error message to caller. - (m32r_cgen_asm_hash_keywords): #if 0 out. - -Wed Apr 9 12:05:25 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-dis.c (print_insn_arg) [case 'd']: Print as address register, - not data register. - [case 'J']: Fix typo in register name. - -Mon Apr 7 16:48:22 1997 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Substitute SHLIB_LIBS. - * configure: Rebuild. - * Makefile.in (SHLIB_LIBS): New variable. - ($(SHLIB)): Use $(SHLIB_LIBS). - -Mon Apr 7 11:45:44 1997 Doug Evans <dje@canuck.cygnus.com> - - * cgen-dis.c (build_dis_hash_table): Fix xmalloc size computation. - - * cgen-opc.c (hash_keyword_name): Improve algorithm. - - * disassemble.c (disassembler): Handle m32r. - -Fri Apr 4 12:29:38 1997 Doug Evans <dje@canuck.cygnus.com> - - * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: New files. - * cgen-asm.c, cgen-dis.c, cgen-opc.c: New files. - * Makefile.in (CFILES): Add them. - (ALL_MACHINES): Add them. - (dependencies): Regenerate. - * configure.in (cgen_files): New variable. - (bfd_m32r_arch): Add entry. - * configure: Regenerate. - -Fri Apr 4 14:04:16 1997 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Correct file names for bfd_mn10[23]00_arch. - * configure: Rebuild. - - * Makefile.in: Rebuild dependencies. - - * d10v-dis.c: Include "ansidecl.h" before "opcode/d10v.h". - - * i386-dis.c (float_reg): Swap fsubrp and fsubp. Swap fdivrp and - fdivp. - -Thu Apr 3 13:22:45 1997 Ian Lance Taylor <ian@cygnus.com> - - * Branched binutils 2.8. - -Wed Apr 2 12:23:53 1997 Ian Lance Taylor <ian@cygnus.com> - - * m10200-dis.c: Rename from mn10200-dis.c. - * m10200-opc.c: Rename from mn10200-opc.c. - * m10300-dis.c: Rename from mn10300-dis.c - * m10300-opc.c: Rename from mn10300-opc.c. - * Makefile.in: Update accordingly. - - * mips16-opc.c: Add mul and dmul macros. - -Tue Apr 1 16:27:45 1997 Klaus Kaempf <kkaempf@progis.de> - - * makefile.vms: Update CFLAGS, add clean target. - -Fri Mar 28 12:10:09 1997 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c: Add "wait". From Ralf Baechle - <ralf@gnu.ai.mit.edu>. - - * configure.in: Add stdlib.h to AC_CHECK_HEADERS list. - * configure, config.in: Rebuild. - * sysdep.h: Include <stdlib.h> if it exists. - * sparc-dis.c: Include <stdio.h> and "sysdep.h". Don't include - <string.h>. - * Makefile.in: Rebuild dependencies. - -Thu Mar 27 14:24:43 1997 Ian Lance Taylor <ian@cygnus.com> - - * ppc-opc.c: Add PPC 403 instructions and extended opcodes. From - Andrew Bray <andy@madhouse.demon.co.uk>. - - * mips-opc.c: Add cast when setting mips_opcodes. - -Tue Mar 25 23:04:00 1997 Stu Grossman (grossman@critters.cygnus.com) - - * v850-dis.c (disassemble): Fix sign extension problem. - * v850-opc.c (extract_d*): Fix sign extension problems to make - disassembly calculate branch offsets correctly. - -Mon Mar 24 13:22:13 1997 Ian Lance Taylor <ian@cygnus.com> - - * sh-opc.h: Add bf/s and bt/s as synonyms for bf.s and bt.s. - - * mips-opc.c: Add dctr and dctw. - -Sun Mar 23 18:08:10 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d30v-dis.c (print_insn): Change the way signed constants - are displayed. - -Fri Mar 21 14:37:52 1997 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (BFD_H): New variable. - (HFILES): New variable. - (CFILES): Add all C files. - (.dep, .dep1, dep.sed, dep, dep-in): New targets. - Delete old dependencies, and build new ones. - * dep-in.sed: New file. - -Thu Mar 20 19:03:30 1997 Philippe De Muyter <phdm@info.ucl.ac.be> - - * m68k-opc.c (m68k_opcode_aliases): Added blo and blo{s,b,w,l}. - -start-sanitize-coldfire -Wed Mar 19 06:53:58 1997 J.T. Conklin <jtc@rtl.cygnus.com> - - * m68k-opc.c (m68k_opcodes): Provide coldfire division module - instructions. - -end-sanitize-coldfire -Tue Mar 18 14:17:03 1997 Jeffrey A Law (law@cygnus.com) - - * mn10200-opc.c: Change "trap" to "syscall". - * mn10300-opc.c: Add new "syscall" instruction. - -Mon Mar 17 08:48:03 1997 J.T. Conklin <jtc@beauty.cygnus.com> - - * m68k-opc.c (m68k_opcodes): Provide correct entries for mulsl and - mulul insns on the coldfire. - -Sat Mar 15 17:13:05 1997 Ian Lance Taylor <ian@cygnus.com> - - * arm-dis.c (print_insn_arm): Don't print instruction bytes. - (print_insn_big_arm): Set bytes_per_chunk and display_endian. - (print_insn_little_arm): Likewise. - -Fri Mar 14 15:08:59 1997 Ian Lance Taylor <ian@cygnus.com> - - Based on patches from H.J. Lu <hjl@lucon.org>: - * i386-dis.c (fetch_data): Add prototype. - * m68k-dis.c (fetch_data): Add prototype. - (dummy_print_address): Add prototype. Make static. - * ppc-opc.c (valid_bo): Add prototype. - * sparc-dis.c (build_hash_table): Add prototype. - (is_delayed_branch, compute_arch_mask): Add prototypes. - (print_insn_sparc): Make several local variables const. - (compare_opcodes): Change arguments to const PTR. Add prototype. - * sparc-opc.c (arg): Change name field to be const. - (lookup_name, lookup_value): Add prototypes. Change table and - name parameters to be const. - (sparc_encode_asi): Change name parameter to be const. - (sparc_encode_membar, sparc_encode_prefetch): Likewise. - (sparc_encode_sparclet_cpreg): Likewise. - (sparc_decode_asi): Change return type to be const. - (sparc_decode_membar, sparc_decode_prefetch): Likewise. - (sparc_decode_sparclet_cpreg): Likewise. - -Fri Mar 7 10:51:49 1997 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in ($(SHLINK)): Just use ln -s, not ln -sf, since - Solaris doesn't like the combined options, and the -f is - unnecessary. - (stamp-tshlink, install): Likewise. - -Thu Mar 6 16:51:11 1997 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (IMM16_PCREL, SD8N_PCREL, D16_SHIFT): Mark these - as relaxable. - -Tue Mar 4 06:10:36 1997 J.T. Conklin <jtc@cygnus.com> - - * m68k-opc.c (m68k_opcodes): Fix last change for the mc68010. - -Mon Mar 3 07:45:20 1997 J.T. Conklin <jtc@cygnus.com> - - * m68k-opc.c (m68k_opcodes): Added entries for the tst insns on - the mc68000. - -Thu Feb 27 14:04:32 1997 Philippe De Muyter <phdm@info.ucl.ac.be> - - * m68k-opc.c (m68k_opcodes): Added swbegl pseudo-instruction. - -start-sanitize-tic80 -Thu Feb 27 11:36:41 1997 Michael Meissner <meissner@cygnus.com> - - * tic80-dis.c (print_insn_tic80): Set info->bytes_per_line to 8. - -Wed Feb 26 15:34:48 1997 Michael Meissner <meissner@cygnus.com> - - * tic80-opc.c (tic80_predefined_symbols): Define r25 properly. - -end-sanitize-tic80 -Wed Feb 26 13:38:30 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-dis.c (NEXTSINGLE, NEXTDOUBLE, NEXTEXTEND): Use - floatformat_to_double to make portable. - (print_insn_arg): Use NEXTEXTEND macro when extracting extended - precision float. - -Mon Feb 24 19:26:12 1997 Dawn Perchik <dawn@cygnus.com> - - * mips-opc.c: Initialize mips_opcodes to mips_builtin_opcodes, - and bfd_mips_num_opcodes to bfd_mips_num_builtin_opcodes. - -Mon Feb 24 15:19:01 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-dis.c, d10v-opc.c: Change pre_defined_registers to - d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt. - -start-sanitize-tic80 -Mon Feb 24 14:33:26 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (LSI_SCALED): Renamed from this ... - (OFF_SL_BR_SCALED): ... to this, and added the flag - TIC80_OPERAND_BASEREL to the flags word. - (tic80_opcodes): Replace all occurances of LSI_SCALED with - OFF_SL_BR_SCALED. - -end-sanitize-tic80 -Sat Feb 22 21:25:00 1997 Dawn Perchik <dawn@cygnus.com> - - * mips-opc.c: Add macros for cop0, cop1 cop2 and cop3. - Change mips_opcodes from const array to a pointer, - and change bfd_mips_num_opcodes from const int to int, - so that we can increase the size of the mips opcodes table - dynamically. - -start-sanitize-tic80 -Sat Feb 22 21:03:47 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_predefined_symbols): Revert change to - store BITNUM values in the table in one's complement form - to match behavior when assembler is given a raw numeric - value for a BITNUM operand. - * tic80-dis.c (print_operand_bitnum): Ditto. - -end-sanitize-tic80 -Fri Feb 21 16:31:18 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d30v-opc.c: Removed references to FLAG_X. - -Wed Feb 19 14:51:20 1997 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in: Add dependencies on ../bfd/bfd.h as required. - -Tue Feb 18 17:43:43 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - - * Makefile.in: Added d30v object files. - * configure: (bfd_d30v_arch) Rebuilt. - * configure.in: (bfd_d30v_arch) Added new case. - * d30v-dis.c: New file. - * d30v-opc.c: New file. - * disassemble.c (disassembler) Add entry for d30v. - -start-sanitize-tic80 -Tue Feb 18 16:32:08 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_predefined_symbols): Add symbolic - representations for the floating point BITNUM values. - -Fri Feb 14 12:14:05 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_predefined_symbols): Store BITNUM values - in the table in one's complement form, as they appear in the - actual instruction. - (tic80_symbol_to_value): Use macros to access predefined - symbol fields. - (tic80_value_to_symbol): Ditto. - (tic80_next_predefined_symbol): New function. - * tic80-dis.c (print_operand_bitnum): Remove code that did - one's complement for BITNUM values. - -end-sanitize-tic80 -start-sanitize-r5900 -Fri Feb 14 13:56:51 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c: bug fix, can't mark insns INSN_5900 and INSN_ISA4 - -end-sanitize-r5900 -Thu Feb 13 21:56:51 1997 Klaus Kaempf <kkaempf@progis.de> - - * makefile.vms: Remove 8 bit characters. Update to latest - gcc release. - -Thu Feb 13 20:41:22 1997 Philippe De Muyter <phdm@info.ucl.ac.be> - - * m68k-opc.c (m68k_opcodes): Add swbeg pseudo-instruction. - -Thu Feb 13 16:30:02 1997 Jeffrey A Law (law@cygnus.com) - - * mn10200-opc.c (IMM16_PCREL): This is a signed operand. - (IMM24_PCREL): Likewise. - -Thu Feb 13 13:28:43 1997 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (print_mips16_insn_arg): Use memaddr - 2 as the base - address for an extended PC relative instruction that is not a - branch. - -Wed Feb 12 12:27:40 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-dis.c (print_insn_m68k): Set bytes_per_chunk and - bytes_per_line. - -start-sanitize-tic80 -Tue Feb 11 16:36:31 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_operands): Fix typo '+' -> '|'. - (tic80_opcodes): Sort entries so that long immediate forms - come after short immediate forms, making it easier for - assembler to select the right one for a given operand. - -end-sanitize-tic80 -Tue Feb 11 15:26:47 1997 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (_print_insn_mips): Set bytes_per_chunk and - display_endian. - (print_insn_mips16): Likewise. - -start-sanitize-r5900 -Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c: add r5900. - -end-sanitize-r5900 -start-sanitize-tic80 -Mon Feb 10 10:12:41 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_symbol_to_value): Changed to accept - a symbol class that restricts translation to just that - class (general register, condition code, etc). - -Thu Feb 6 17:34:09 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_operands): Add REG_0_E, REG_22_E, - and REG_DEST_E for register operands that have to be - an even numbered register. Add REG_FPA for operands that - are one of the floating point accumulator registers. - Add TIC80_OPERAND_MASK to flags for ENDMASK operand. - (tic80_opcodes): Change entries that need even numbered - register operands to use the new operand table entries. - Add "or" entries that are identical to "or.tt" entries. - -end-sanitize-tic80 -Wed Feb 5 11:12:44 1997 Ian Lance Taylor <ian@cygnus.com> - - * mips16-opc.c: Add new cases of exit instruction for - disassembler. - * mips-dis.c (print_mips16_insn_arg): Display floating point - registers in operands of exit instruction. Print `$' before - register names in operands of entry and exit instructions. - -start-sanitize-tic80 -Thu Jan 30 14:09:03 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_predefined_symbols): Table of name/value - pairs for all predefined symbols recognized by the assembler. - Also used by the disassembling routines. - (tic80_symbol_to_value): New function. - (tic80_value_to_symbol): New function. - * tic80-dis.c (print_operand_control_register, - print_operand_condition_code, print_operand_bitnum): - Remove private tables and use tic80_value_to_symbol function. - -end-sanitize-tic80 -Thu Jan 30 11:30:45 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-dis.c (print_operand): Change address printing - to correctly handle PC wrapping. Fixes PR11490. - -Wed Jan 29 09:39:17 1997 Jeffrey A Law (law@cygnus.com) - - * mn10200-opc.c (mn10200_operands): Make 8 and 16 bit pc-relative - branches relaxable. - -Tue Jan 28 15:57:34 1997 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (print_insn_mips16): Set insn_info information. - (print_mips16_insn_arg): Likewise. - - * mips-dis.c (print_insn_mips16): Better handling of an extend - opcode followed by an instruction which can not be extended. - -Fri Jan 24 12:08:21 1997 J.T. Conklin <jtc@cygnus.com> - - * m68k-opc.c (m68k_opcodes): Changed operand specifier for the - coldfire moveb instruction to not allow an address register as - destination. Although the documentation does not indicate that - this is invalid, experiments uncovered unexpected behavior. - Added a comment explaining the situation. Thanks to Andreas - Schwab for pointing this out to me. - -start-sanitize-tic80 -Wed Jan 22 20:13:51 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_opcodes): Expand comment to note that the - entries are presorted so that entries with the same mnemonic are - adjacent to each other in the table. Sort the entries for each - instruction so that this is true. - -end-sanitize-tic80 -Mon Jan 20 12:48:57 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-dis.c: Include <libiberty.h>. - (print_insn_m68k): Sort the opcode table on the most significant - nibble of the opcode. - -start-sanitize-tic80 -Sat Jan 18 15:15:05 1997 Fred Fish <fnf@cygnus.com> - - * tic80-dis.c (tic80_opcodes): Add "wrcr", "vmpy", "vrnd", - "vsub", "vst", "xnor", and "xor" instructions. - (V_a1): Renamed from V_a, msb of accumulator reg number. - (V_a0): Add macro, lsb of accumulator reg number. - -Fri Jan 17 18:24:31 1997 Fred Fish <fnf@cygnus.com> - - * tic80-dis.c (print_insn_tic80): Broke excessively long - function up into several smaller ones and arranged for - the instruction printing function to be callable recursively - to print vector instructions that have both a load and a - math instruction packed into a single opcode. - * tic80-opc.c (tic80_opcodes): Expand comment for vld opcode - to explain why it comes after the other vector opcodes. - -end-sanitize-tic80 -Fri Jan 17 16:19:15 1997 J.T. Conklin <jtc@beauty.cygnus.com> - - * m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire - move insns to handle immediate operands. - -Thu Jan 17 16:19:00 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-opc.c (m68k_opcodes): Delete duplicate entry for "cmpil". - fix operand mask in the "moveml" entries for the coldfire. - -start-sanitize-tic80 -Thu Jan 16 20:54:40 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (V_a, V_m, V_S, V_Z, V_p, OP_V, MASK_V): - New macros for building vector instruction opcodes. - (tic80_opcodes): Remove all uses of FMT_SI, FMT_REG, and - FMT_LI, which were unused. The field is now a flags field. - Remove some opcodes that are possible, but illegal, such - as long immediate instructions with doubles for immediate - values. Add "vadd" and "vld" instructions. - -Wed Jan 15 18:59:51 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_operands): Reorder some table entries to make - the order more logical. Move the shift alias instructions ("rotl", - "shl", "ins", "rotr", "extu", "exts", "srl", and "sra" to be - interspersed with the regular sr.x and sl.x instructions. Add - and test new instruction opcodes for "sl", "sli", "sr", "sri", "st", - "sub", "subu", "swcr", and "trap". - -Tue Jan 14 19:42:50 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (OFF_SS_PC): Renamed from OFF_SS. - (OFF_SL_PC): Renamed from OFF_SL. - (OFF_SS_BR): New operand type for base relative operand. - (OFF_SL_BR): New operand type for base relative operand. - (REG_BASE): New operand type for base register operand. - (tic80_opcodes): Add and test "fmpy", "frndm", "frndn", "frndp", - "frndz", "fsqrt", "fsub", "illop0", "illopF", "ins", "jsr", - "ld", "ld.u", "lmo", "or", "rdcr", "rmo", "rotl", and "rotr" - instructions. - * tic80-dis.c (print_insn_tic80): Print opcode name with fixed width - 10 char field, padded with spaces on rhs, rather than a string - followed by a tab. Use renamed TIC80_OPERAND_PCREL flag bit rather - than old TIC80_OPERAND_RELATIVE. Add support for new - TIC80_OPERAND_BASEREL flag bit. - -Mon Jan 13 15:58:56 1997 Fred Fish <fnf@cygnus.com> - - * tic80-dis.c (print_insn_tic80): Print floating point operands - as floats. - * tic80-opc.c (SPFI): Add single precision floating point - immediate operand type. - (ROTATE): Add rotate operand type for shifts. - (ENDMASK): Add for shifts. - (n): Macro for the 'n' bit. - (i): Macro for the 'i' bit. - (PD): Macro for the 'PD' field. - (P2): Macro for the 'P2' field. - (P1): Macro for the 'P1' field. - (tic80_opcodes): Add entries for "exts", "extu", "fadd", - "fcmp", and "fdiv". - -end-sanitize-tic80 -Mon Jan 6 15:06:55 1997 Jeffrey A Law (law@cygnus.com) - - * mn10200-dis.c (disassemble): Mask off unwanted bits after - adding in current address for pc-relative operands. - -start-sanitize-tic80 -Mon Jan 6 10:56:25 1997 Fred Fish <fnf@cygnus.com> - - * tic80-dis.c (R_SCALED): Add macro to test for ":s" modifier bit. - (print_insn_tic80): If R_SCALED then print ":s" modifier for operand. - * tic80-opc.c (REG0, REG22, REG27, SSOFF, LSOFF): Names - changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively. - (SICR, LICR, REGM_SI, REGM_LI): Names changed to CR_SI, CR_LI, - REG_BASE_M_SI, REG_BASE_M_LI respectively. - (REG_SCALED, LSI_SCALED): New operand types. - (E): New macro for 'E' bit at bit 27. - (tic80_opcodes): Add and test dld, dld.u, dst, estop, and etrap - opcodes, including the various size flavors (b,h,w,d) for - the direct load and store instructions. - -Sun Jan 5 12:18:14 1997 Fred Fish <fnf@cygnus.com> - - * tic80-dis.c (M_SI, M_LI): Add macros to test for ":m" modifier bit - in an instruction. - * tic80-dis.c (print_insn_tic80): Change comma and paren handling. - Use M_SI and M_LI macros to check for ":m" modifier for GPR operands. - * tic80-opc.c (tic80_operands): Add REGM_SI and REGM_LI operands. - (F, M_REG, M_LI, M_SI, SZ_REG, SZ_LI, SZ_SI, D, S): New bit-twiddlers. - (MASK_LI_M, MASK_SI_M, MASK_REG_M): Remove and replace in opcode - masks with "MASK_* & ~M_*" to get the M bit reset. - (tic80_opcodes): Add bsr, bsr.a, cmnd, cmp, dcachec, and dcachef. - -Sat Jan 4 19:05:05 1997 Fred Fish <fnf@cygnus.com> - - * tic80-dis.c (print_insn_tic80): Print TIC80_OPERAND_RELATIVE - correctly. Add support for printing TIC80_OPERAND_BITNUM and - TIC80_OPERAND_CC, and TIC80_OPERAND_CR operands in symbolic - form. - * tic80-opc.c (tic80_operands): Add SSOFF, LSOFF, BITNUM, - CC, SICR, and LICR table entries. - (tic80_opcodes): Add and test "nop", "br", "bbo", "bbz", - "bcnd", and "brcr" opcodes. - -end-sanitize-tic80 -Fri Jan 3 18:32:11 1997 Fred Fish <fnf@cygnus.com> - - * ppc-opc.c (powerpc_operands): Make comment match the - actual fields (no shift field). - * sparc-opc.c (sparc_opcodes): Document why this cannot be "const". -start-sanitize-tic80 - * tic80-dis.c (print_insn_tic80): Replace abort stub with a - partial implementation, work in progress. - * tic80-opc.c (tic80_operands): Begin construction operands table. - (tic80_opcodes): Continue populating opcodes table and start - filling in the operand indices. - (tic80_num_opcodes): Add this. -end-sanitize-tic80 - -Fri Jan 3 12:13:52 1997 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: Add #B case for moveq. - -Thu Jan 2 12:14:29 1997 Jeffrey A Law (law@cygnus.com) - - * mn10300-dis.c (disassemble): Make sure all variables are initialized - before they are used. - -Tue Dec 31 12:20:38 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (v850_opcodes): Put curly-braces around operands - for "breakpoint" instruction. - -Tue Dec 31 15:38:13 1996 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (ALL_CFLAGS): Add -D_GNU_SOURCE. - (dep): Use ALL_CFLAGS rather than CFLAGS. - -Tue Dec 31 15:09:16 1996 Michael Meissner <meissner@tiktok.cygnus.com> - - * v850-opc.c (D8_{6,7}): Set V850_OPERAND_ADJUST_SHORT_MEMORY - flag. - -Mon Dec 30 17:02:11 1996 Fred Fish <fnf@cygnus.com> - - * Makefile.in (m68k-opc.o, alpha-opc.o): Remove dis-asm.h dependency. -start-sanitize-tic80 - (tic80-dis.o, tic80-opc.o): Add rules per comment in Makefile.in. -end-sanitize-tic80 - -Mon Dec 30 11:38:01 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips16-opc.c: Add "abs". - -start-sanitize-tic80 -Sun Dec 29 10:58:22 1996 Fred Fish <fnf@cygnus.com> - - * Makefile.in (ALL_MACHINES): Add tic80-dis.o and tic80-opc.o. - * disassemble.c (ARCH_tic80): Define if ARCH_all is defined. - (disassembler): Add bfd_arch_tic80 support to set disassemble - to print_insn_tic80. - * tic80-dis.c (print_insn_tic80): Add stub. - -Fri Dec 27 22:30:57 1996 Fred Fish <fnf@cygnus.com> - - * configure.in (arch in $selarchs): Add bfd_tic80_arch entry. - * configure: Regenerate with autoconf. - * tic80-dis.c: Add file. - * tic80-opc.c: Add file. - -end-sanitize-tic80 -Fri Dec 20 14:30:19 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c (pre_defined_registers): Add cr[0-15], dpc, dpsw, link. - -Mon Dec 16 13:00:15 1996 Jeffrey A Law (law@cygnus.com) - - * mn10200-opc.c (mn10200_operands): Add SIMM16N. - (mn10200_opcodes): Use it for some logicals and btst insns. - Add "break" and "trap" instructions. - - * mn10300-opc.c (mn10300_opcodes): Add "break" instruction. - - * mn10200-opc.c: Add pseudo-ops for "mov (an),am" and "mov an,(am)". - -Sat Dec 14 22:36:20 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (print_mips16_insn_arg): The base address of a PC - relative load or add now depends upon whether the instruction is - in a delay slot. - -Wed Dec 11 09:23:46 1996 Jeffrey A Law (law@cygnus.com) - - * mn10200-dis.c: Finish writing disassembler. - * mn10200-opc.c (mn10200_opcodes): Fix mask for "mov imm8,dn". - Fix mask for "jmp (an)". - - * mn10300-dis.c (disassemble, print_insn_mn10300): Corrently - handle endianness issues for mn10300. - - * mn10200-opc.c (mn10200_opcodes): Fix operands for "movb dm,(an)". - -Tue Dec 10 12:08:05 1996 Jeffrey A Law (law@cygnus.com) - - * mn10200-opc.c (mn10200_opcodes): "mov imm8,d0" is a format 2 - instruction. Fix opcode field for "movb (imm24),dn". - - * mn10200-opc.c (mn10200_operands): Fix insertion position - for DI operand. - -Mon Dec 9 16:42:43 1996 Jeffrey A Law (law@cygnus.com) - - * mn10200-opc.c: Create mn10200 opcode table. - * mn10200-dis.c: Flesh out mn10200 disassembler. Not ready, - but moving along nicely. - -Sun Dec 8 04:28:31 1996 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * Makefile.in (ALL_MACHINES): Add mips16-opc.o. - -Fri Dec 6 16:47:40 1996 J.T. Conklin <jtc@rhino.cygnus.com> - - * m68k-opc.c (m68k_opcodes): Revert change to use < and > - specifiers for fmovem* instructions. - -Fri Dec 6 14:48:09 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-dis.c (disassemble): Remove '$' register prefixing. - -Fri Dec 6 17:34:39 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips16-opc.c: Change opcode for entry/exit to avoid conflicting - with dsrl. - -Fri Dec 6 14:48:09 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c: Add some comments explaining the various - operands and such. - - * mn10300-dis.c (disassemble): Fix minor gcc -Wall warnings. - -Thu Dec 5 12:09:48 1996 J.T. Conklin <jtc@rtl.cygnus.com> - - * m68k-dis.c (print_insn_arg): Handle new < and > operand - specifiers. - - * m68k-opc.c (m68k_opcodes): Simplify table by using < and > - operand specifiers in fmovm* instructions. - -Wed Dec 4 14:52:18 1996 Ian Lance Taylor <ian@cygnus.com> - - * ppc-opc.c (insert_li): Give an error if the offset has the two - least significant bits set. - -Wed Nov 27 13:09:01 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (print_insn_mips16): Separate the instruction from - the arguments with a tab, not a space. - -Tue Nov 26 13:24:17 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-dis.c (disasemble): Finish conversion to '$' as - register prefix. - - * mn10300-opc.c (mn10300_opcodes): Fix mask field for - mov am,(imm32,sp). - -Tue Nov 26 10:53:21 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure: Rebuild with autoconf 2.12. - - Add support for mips16 (16 bit MIPS implementation): - * mips16-opc.c: New file. - * mips-dis.c: Include "elf-bfd.h" and "elf/mips.h". - (mips16_reg_names): New static array. - (print_insn_big_mips): Use print_insn_mips16 in 16 bit mode or - after seeing a 16 bit symbol. - (print_insn_little_mips): Likewise. - (print_insn_mips16): New static function. - (print_mips16_insn_arg): New static function. - * mips-opc.c: Add jalx instruction. - * Makefile.in (mips16-opc.o): New target. - * configure.in: Use mips16-opc.o for bfd_mips_arch. - * configure: Rebuild. - -Mon Nov 25 16:15:17 1996 J.T. Conklin <jtc@cygnus.com> - - * m68k-opc.c (m68k_opcodes): Simplify table by using < and > - operand specifiers in *save, *restore and movem* instructions. - - * m68k-opc.c (m68k_opcodes): Fix move and movem instructions for - the coldfire. - - * m68k-opc.c (m68k_opcodes): The coldfire (mcf5200) can only use - register operands for immediate arithmetic, not, neg, negx, and - set according to condition instructions. - - * m68k-opc.c (m68k_opcodes): Consistantly Use "s" as the storage - specifier of the effective-address operand in immediate forms of - arithmetic instructions. The specifier for the immediate operand - notes how and where the constant will be stored. - -Mon Nov 25 11:17:01 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_opcodes): Remove redundant "lcc" - opcode. - - * mn10300-dis.c (disassemble): Use '$' instead of '%' for - register prefix. - - * mn10300-dis.c (disassemble): Prefix registers with '%'. - -Wed Nov 20 10:37:13 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-dis.c (disassemble): Handle register lists. - - * mn10300-opc.c: Fix handling of register list operand for - "call", "ret", and "rets" instructions. - - * mn10300-dis.c (disassemble): Print PC-relative and memory - addresses symbolically if possible. - * mn10300-opc.c: Distinguish between absolute memory addresses, - pc-relative offsets & random immediates. - - * mn10300-dis.c (print_insn_mn10300): Fix fetch of last byte - in 7 byte insns. - (disassemble): Handle SPLIT and EXTENDED operands. - -Tue Nov 19 13:33:01 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-dis.c: Rough cut at printing some operands. - - * mn10300-dis.c: Start working on disassembler support. - * mn10300-opc.c (mn10300_opcodes): Fix masks on several insns. - - * mn10300-opc.c (mn10300_operands): Add "REGS" for a register - list. - (mn10300_opcodes): Use REGS for register list in "movm" instructions. - -Mon Nov 18 15:20:35 1996 Michael Meissner <meissner@tiktok.cygnus.com> - - * d10v-opc.c (d10v_opcodes): Add3 sets the carry. - -Fri Nov 15 13:43:19 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_opcodes): Demand parens around - register argument is calls and jmp instructions. - -Thu Nov 7 00:26:05 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_opcodes): Use DN01 for putx and - getx operand. Fix opcode for mulqu imm,dn. - -Wed Nov 6 13:42:32 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_operands): Hijack "bits" field - in MN10300_OPERAND_SPLIT operands for how many bits - appear in the basic insn word. Add IMM32_HIGH24, - IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8. - (mn10300_opcodes): Use new operands as needed. - - * mn10300-opc.c (mn10300_operands): Add IMM32_LOWSHIFT8 - for bset, bclr, btst instructions. - (mn10300_opcodes): Use new IMM32_LOWSHIFT8 as needed. - - * mn10300-opc.c (mn10300_operands): Remove many redundant - operands. Update opcode table as appropriate. - (IMM32): Add MN10300_OPERAND_SPLIT flag. - (mn10300_opcodes): Fix single bit error in mov imm32,dn insn. - -Tue Nov 5 13:26:58 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_operands): Add DN2, DM2, AN2, AM2 - operands (for indexed load/stores). Fix bitpos for DI - operand. Add SN8N_SHIFT8, IMM8_SHIFT8, and D16_SHIFT for the - few instructions that insert immediates/displacements in the - middle of the instruction. Add IMM8E for 8 bit immediate in - the extended part of an instruction. - (mn10300_operands): Use new opcodes as appropriate. - -Tue Nov 5 10:30:51 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c (d10v_opcodes): Declare the trap instruction - sequential so the assembler never parallelizes it with - other instructions. - -Mon Nov 4 12:50:40 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_operands): Add DN01 and AN01 for - a data/address register that appears in register field 0 - and register field 1. - (mn10300_opcodes): Use DN01 and AN01 for mov/cmp imm8,DN/AN - -Fri Nov 1 10:29:11 1996 Richard Henderson <rth@tamu.edu> - - * alpha-dis.c (print_insn_alpha): Use new NOPAL mask for - standard disassembly. - - * alpha-opc.c (alpha_operands): Rearrange flags slot. - (alpha_opcodes): Add new BWX, CIX, and MAX instructions. - Recategorize PALcode instructions. - -Wed Oct 30 16:46:58 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (v850_opcodes): Add relaxing "jbr". - -Tue Oct 29 16:30:28 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (_print_insn_mips): Don't print a trailing tab if - there are no operand types. - -Tue Oct 29 12:22:21 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (D9_RELAX): Renamed from D9, all references - changed. - (v850_operands): Make sure D22 immediately follows D9_RELAX. - -Fri Oct 25 12:12:53 1996 Ian Lance Taylor <ian@cygnus.com> - - * i386-dis.c (print_insn_x86): Set info->bytes_per_line to 5. - -Thu Oct 24 17:53:52 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (insert_d8_6): Fix operand insertion for sld.w - and sst.w instructions. - - * v850-opc.c (v850_opcodes): Add "jCC" instructions (aliases for - "bCC"instructions). - -Thu Oct 24 17:21:20 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (_print_insn_mips): Use a tab between the instruction - and the arguments. - -Tue Oct 22 23:32:56 1996 Ian Lance Taylor <ian@cygnus.com> - - * ppc-opc.c (PPCPWR2): Define. - (powerpc_opcodes): Use PPCPWR2 for fsqrt, rather than duplicating - it. - -Fri Oct 11 16:03:49 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode - field for movhu instruction. - - * v850-dis.c (disassemble): For V850_OPERAND_SIGNED operands, - cast value to "long" not "signed long" to keep hpux10 - compiler quiet. - -Thu Oct 10 10:25:58 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode field - for mov (abs16),DN. - - * mn10300-opc.c (FMT*): Remove definitions. - - * mn10300-opc.c (mn10300_opcodes): Fix destination register - for shift-by-register opcodes. - - * mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AM - into [AD][MN][01] for encoding the position of the register - in the opcode. - -Wed Oct 9 11:19:26 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_opcodes): Add "extended" instructions, - "putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch". - -Tue Oct 8 11:55:35 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_operands): Remove "REGS" operand. - Fix various typos. Add "PAREN" operand. - (MEM, MEM2): Define. - (mn10300_opcodes): Surround all memory addresses with "PAREN" - operands. Fix several typos. - - * mn10300-opc.c (mn10300_opcodes): Fix typos in yesterday's - changes. - -Mon Oct 7 16:48:45 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (FMT_XX): Renumber starting at one. - (mn10300_operands): Rough cut. Enough to parse "mov" instructions - at this time. - (mn10300_opcodes): Break opcode format out into its own field. - Update many operand fields to deal with signed vs unsigned - issues. Fix one or two typos in the "mov" instruction - opcode, mask and/or operand fields. - -Mon Oct 7 11:39:49 1996 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-opc.c (plusha): Prefer encoding for m68040up, in case - m68851 wasn't reset. - -Thu Oct 3 17:17:02 1996 Ian Lance Taylor <ian@cygnus.com> - - * mn10300-opc.c (mn10300_opcodes): Add opcode & masks for - all opcodes. Very rough cut at operands for all opcodes. - - * mn10300-opc.c (mn10300_opcodes): Start fleshing out the - opcode table. - -Thu Oct 3 10:06:07 1996 Jeffrey A Law (law@cygnus.com) - - * mn10200-opc.c, mn10300-opc.c: New files. - * mn10200-dis.c, mn10300-dis.c: New files. - * mn10x00-opc.c, mn10x00-dis.c: Deleted. - * disassemble.c: Break mn10x00 support into 10200 and 10300 - support. - * configure.in: Likewise. - * configure: Rebuilt. - -Thu Oct 3 15:59:12 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) - - * Makefile.in (MOSTLYCLEAN): Move config.log to distclean. - -Wed Oct 2 23:28:42 1996 Jeffrey A Law (law@cygnus.com) - - * mn10x00-opc.c, mn10x00-dis.c: New files for Matsushita - MN10x00 processors. - * disassemble (ARCH_mn10x00): Define. - (disassembler): Handle bfd_arch_mn10x00. - * configure.in: Recognize bfd_mn10x00_arch. - * configure: Rebuilt. - -Tue Oct 1 10:49:11 1996 Ian Lance Taylor <ian@cygnus.com> - - * i386-dis.c (op_rtn): Change to be a pointer. Adjust uses - accordingly. Don't declare functions using op_rtn. - -Fri Sep 27 18:28:59 1996 Stu Grossman (grossman@critters.cygnus.com) - - * v850-dis.c (disassemble): Add memaddr argument. Re-arrange - params to be more standard. - * (disassemble): Print absolute addresses and symbolic names for - branch and jump targets. - * v850-opc.c (v850_operand): Add displacement flag to 9 and 22 - bit operands. - * (v850_opcodes): Add breakpoint insn. - -Mon Sep 23 12:32:26 1996 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: Move the fmovemx data register cases before the - other cases, so that they get recognized before the data register - does gets treated as a degenerate register list. - -Tue Sep 17 12:06:51 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c: Add a case for "div" and "divu" with two registers - and a destination of $0. - -Tue Sep 10 16:12:39 1996 Fred Fish <fnf@rtl.cygnus.com> - - * mips-dis.c (print_insn_arg): Add prototype. - (_print_insn_mips): Ditto. - -Mon Sep 9 14:26:26 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (print_insn_arg): Print condition code registers as - $fccN. - -Tue Sep 3 12:09:46 1996 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparc_opcodes): Add setuw, setsw, setx. - -Tue Sep 3 12:05:25 1996 Jeffrey A Law (law@cygnus.com) - - * v850-dis.c (disassemble): Make static. Provide prototype. - -Sun Sep 1 22:30:40 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (insert_d9, insert_d22): Fix boundary case - in range checks. - -Sat Aug 31 01:27:26 1996 Jeffrey A Law (law@cygnus.com) - - * v850-dis.c (disassemble): Handle insertion of ',', '[' and - ']' characters into the output stream. - * v850-opc.c (v850_opcodes: Remove size field from all opcodes. - Add "memop" field to all opcodes (for the disassembler). - Reorder opcodes so that "nop" comes before "mov" and "jr" - comes before "jarl". - - * v850-dis.c (print_insn_v850): Fix typo in last change. - - * v850-dis.c (print_insn_v850): Properly handle disassembling - a two byte insn at the end of a memory region when the memory - region's size is only two byte aligned. - - * v850-dis.c (v850_cc_names): Fix stupid thinkos. - - * v850-dis.c (v850_reg_names): Define. - (v850_sreg_names, v850_cc_names): Likewise. - (disassemble): Very rough cut at printing operands (unformatted). - - * v850-opc.c (BOP_MASK): Fix. - (v850_opcodes): Fix mask for jarl and jr. - - * v850-dis.c: New file. Skeleton for disassembler support. - * Makefile.in Remove v850 references, they're not needed here. - * configure.in: Add v850-dis.o when building v850 toolchains. - * configure: Rebuilt. - * disassemble.c (disassembler): Call v850 disassembler. - - * v850-opc.c (insert_d8_7, extract_d8_7): New functions. - (insert_d8_6, extract_d8_6): New functions. - (v850_operands): Rename D7S to D7; operand for D7 is unsigned. - Rename D8 to D8_7, use {insert,extract}_d8_7 routines. - Add D8_6. - (IF4A, IF4B): Use "D7" instead of "D7S". - (IF4C, IF4D): Use "D8_7" instead of "D8". - (IF4E, IF4F): New. Use "D8_6". - (v850_opcodes): Use IF4A/IF4B for sld.b/sst.b. Use IF4C/IF4D for - sld.h/sst.h. Use IF4E/IF4F for sld.w/sst.w. - - * v850-opc.c (insert_d16_15, extract_d16_15): New functions. - (v850_operands): Change D16 to D16_15, use special insert/extract - routines. New new D16 that uses the generic insert/extract code. - (IF7A, IF7B): Use D16_15. - (IF7C, IF7D): New. Use D16. - (v850_opcodes): Use IF7C and IF7D for ld.b and st.b. - - * v850-opc.c (insert_d9, insert_d22): Slightly improve error - message. Issue an error if the branch offset is odd. - - * v850-opc.c: Add notes about needing special insert/extract - for all the load/store insns, except "ld.b" and "st.b". - - * v850-opc.c (insert_d22, extract_d22): New functions. - (v850_operands): Use insert_d22 and extract_d22 for - D22 operands. - (insert_d9): Fix range check. - -Fri Aug 30 18:01:02 1996 J.T. Conklin <jtc@hippo.cygnus.com> - - * v850-opc.c (v850_operands): Add V850_OPERAND_SIGNED flag - and set bits field to D9 and D22 operands. - -Thu Aug 29 11:10:46 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (v850_operands): Define SR2 operand. - (v850_opcodes): "ldsr" uses R1,SR2. - - * v850-opc.c (v850_opcodes): Fix opcode specs for - sld.w, sst.b, sst.h, sst.w, and nop. - -Wed Aug 28 15:55:43 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (v850_opcodes): Add null opcode to mark the - end of the opcode table. - -Mon Aug 26 13:35:53 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c (pre_defined_registers): Added register pairs, - "r0-r1", "r2-r3", etc. - -Fri Aug 23 00:27:01 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (v850_operands): Make I16 be a signed operand. - Create I16U for an unsigned 16bit mmediate operand. - (v850_opcodes): Use I16U for "ori", "andi" and "xori". - - * v850-opc.c (v850_operands): Define EP operand. - (IF4A, IF4B, IF4C, IF4D): Use EP. - - * v850-opc.c (v850_opcodes): Fix opcode numbers for "mov" - with immediate operand, "movhi". Tweak "ldsr". - - * v850-opc.c (v850_opcodes): Get ld.[bhw] and st.[bhw] - correct. Get sld.[bhw] and sst.[bhw] closer. - - * v850-opc.c (v850_operands): "not" is a two byte insn - - * v850-opc.c (v850_opcodes): Correct bit pattern for setf. - - * v850-opc.c (v850_operands): D16 inserts at offset 16! - - * v850-opc.c (two): Get order of words correct. - - * v850-opc.c (v850_operands): I16 inserts at offset 16! - - * v850-opc.c (v850_operands): Add "SR1" and "SR2" for system - register source and destination operands. - (v850_opcodes): Use SR1 and SR2 for "ldsr" and "stsr". - - * v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode. Fix - same thinko in "trap" opcode. - - * v850-opc.c (v850_opcodes): Add initializer for size field - on all opcodes. - - * v850-opc.c (v850_operands): D6 -> DS7. References changed. - Add D8 for 8-bit unsigned field in short load/store insns. - (IF4A, IF4D): These both need two registers. - (IF4C, IF4D): Define. Use 8-bit unsigned field. - (v850_opcodes): For "sld.h", "sld.w", "sst.h", "sst.w", use - IF4C & IF4D. For "trap" use I5U, not I5. Add IF1 operand - for "ldsr" and "stsr". - * v850-opc.c (v850_operands): 3-bit immediate for bit insns - is unsigned. - - * v850-opc.c (v850_opcodes): Correct short store half (sst.h) and - short store word (sst.w). - -Thu Aug 22 16:57:27 1996 J.T. Conklin <jtc@rtl.cygnus.com> - - * v850-opc.c (v850_operands): Added insert and extract fields, - pointers to functions that handle unusual operand encodings. - -Thu Aug 22 01:05:24 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (v850_opcodes): Enable "trap". - - * v850-opc.c (v850_opcodes): Fix order of displacement - and register for "set1", "clr1", "not1", and "tst1". - -Wed Aug 21 18:46:26 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (v850_operands): Add "B3" support. - (v850_opcodes): Fix and enable "set1", "clr1", "not1" - and "tst1". - - * v850-opc.c (v850_opcodes): "jmp" has only an R1 operand. - - * v850-opc.c: Close unterminated comment. - -Wed Aug 21 17:31:26 1996 J.T. Conklin <jtc@hippo.cygnus.com> - - * v850-opc.c (v850_operands): Add flags field. - (v850_opcodes): add move opcodes. - -Tue Aug 20 14:41:03 1996 J.T. Conklin <jtc@hippo.cygnus.com> - - * Makefile.in (ALL_MACHINES): Add v850-opc.o. - * configure: (bfd_v850v_arch) Add new case. - * configure.in: (bfd_v850_arch) Add new case. - * v850-opc.c: New file. - -Mon Aug 19 15:21:38 1996 Doug Evans <dje@canuck.cygnus.com> - - * sparc-dis.c (print_insn_sparc): Handle little endian sparcs. - -Thu Aug 15 13:14:43 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c: Add additional information to the opcode - table to help determinine which instructions can be done - in parallel. - -Thu Aug 15 13:11:13 1996 Stan Shebs <shebs@andros.cygnus.com> - - * mpw-make.sed: Update editing of include pathnames to be - more general. - -Thu Aug 15 16:28:41 1996 James G. Smith <jsmith@cygnus.co.uk> - - * arm-opc.h: Added "bx" instruction definition. - -Wed Aug 14 17:00:04 1996 Richard Henderson <rth@tamu.edu> - - * alpha-opc.c (EV4EXTHWINDEX): Field width should be 8 not 5. - -Mon Aug 12 14:30:37 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c (d10v_opcodes): Minor fixes to addi and bl.l. - -Fri Aug 9 13:21:59 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c (d10v_opcodes): Correct 'mv' unit entry to EITHER. - -Thu Aug 8 12:43:52 1996 Klaus Kaempf <kkaempf@progis.de> - - * makefile.vms: Update for alpha-opc changes. - -Wed Aug 7 11:55:10 1996 Ian Lance Taylor <ian@cygnus.com> - - * i386-dis.c (print_insn_i386): Actually return the correct value. - (ONE, OP_ONE): #ifdef out; not used. - -Fri Aug 2 17:47:03 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c (d10v_opcodes): Added 2 accumulator sub instructions. - Changed subi operand type to treat 0 as 16. - -Wed Jul 31 16:21:41 1996 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: Add cpushl for the mcf5200. From Ken Rose - <rose@netcom.com>. - -Wed Jul 31 14:39:27 1996 James G. Smith <jsmith@cygnus.co.uk> - - * arm-opc.h: (arm_opcodes): Added halfword and sign-extension - memory transfer instructions. Add new format string entries %h and %s. - * arm-dis.c: (print_insn_arm): Provide decoding of the new - formats %h and %s. - -Fri Jul 26 11:45:04 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c (d10v_operands): Added UNUM4S; a 4-bit accumulator shift. - (d10v_opcodes): Modified accumulator shift instructions to use UNUM4S. - -Fri Jul 26 14:01:43 1996 Ian Lance Taylor <ian@cygnus.com> - - * alpha-dis.c (print_insn_alpha_osf): Remove. - (print_insn_alpha_vms): Remove. - (print_insn_alpha): Make globally visible. Chose the register - names based on info->flavour. - * disassemble.c: Always return print_insn_alpha for the alpha. - -Thu Jul 25 15:24:17 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-dis.c (dis_long): Handle unknown opcodes. - -Thu Jul 25 12:08:09 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c: Changes to support signed and unsigned numbers. - All instructions with the same name that have long and short forms - now end in ".l" or ".s". Divs added. - * d10v-dis.c: Changes to support signed and unsigned numbers. - -Tue Jul 23 11:02:53 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-dis.c: Change all functions to use info->print_address_func. - -Mon Jul 22 15:38:53 1996 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-opc.c (m68k_opcodes): Make opcode masks for the ColdFire - move ccr/sr insns more strict so that the disassembler only - selects them when the addressing mode is data register. - -Mon Jul 22 11:25:24 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - * d10v-opc.c (pre_defined_registers): Declare. - * d10v-dis.c (print_operand): Now uses pre_defined_registers - to pick a better name for the registers. - -Mon Jul 22 13:47:23 1996 Ian Lance Taylor <ian@cygnus.com> - - * sparc-opc.c: Fix opcode values for fpack16, and fpackfix. Fix - operands for fexpand and fpmerge. From Christian Kuehnke - <Christian.Kuehnke@arbi.informatik.uni-oldenburg.de>. - -Mon Jul 22 13:17:06 1996 Richard Henderson <rth@tamu.edu> - - * alpha-dis.c (print_insn_alpha): No longer the user-visible - print routine. Take new regnames and cpumask arguments. - Kill the environment variable nonsense. - (print_insn_alpha_osf): New function. Do OSF/1 style regnames. - (print_insn_alpha_vms): New function. Do VMS style regnames. - * disassemble.c (disassembler): Test bfd flavour to pick - between OSF and VMS routines. Default to OSF. - -Thu Jul 18 17:19:34 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Call AC_SUBST (INSTALL_SHLIB). - * configure: Rebuild. - * Makefile.in (install): Use @INSTALL_SHLIB@. - -Wed Jul 17 14:39:05 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * configure: (bfd_d10v_arch) Add new case. - * configure.in: (bfd_d10v_arch) Add new case. - * d10v-dis.c: New file. - * d10v-opc.c: New file. - * disassemble.c (disassembler) Add entry for d10v. - -Wed Jul 17 10:12:05 1996 J.T. Conklin <jtc@rtl.cygnus.com> - - * m68k-opc.c (m68k_opcodes): Fix bugs in coldfire insns relating - to bcc, trapfl, subxl, and wddata discovered by Andreas Schwab. - -Mon Jul 15 16:59:55 1996 Stu Grossman (grossman@critters.cygnus.com) - - * i386-dis.c: Get rid of print_insn_i8086. Use info.mach to - distinguish between variants of the instruction set. - * sparc-dis.c: Get rid of print_insn_sparclite. Use info.mach to - distinguish between variants of the instruction set. - -Fri Jul 12 10:12:01 1996 Stu Grossman (grossman@critters.cygnus.com) - - * i386-dis.c (print_insn_i8086): New routine to disassemble using - the 8086 instruction set. - * i386-dis.c: General cleanups. Make most things static. Add - prototypes. Get rid of static variables aflags and dflags. Pass - them as args (to almost everything). - -Thu Jul 11 11:58:44 1996 Jeffrey A Law (law@cygnus.com) - - * h8300-dis.c (bfd_h8_disassemble): Handle macregs in ldmac insns. - - * h8300-dis.c (bfd_h8_disassemble): Handle "ldm.l" and "stm.l". - - * h8300-dis.c (bfd_h8_disassemble): "abs" is implicitly two - if the next arg is marked with SRC_IN_DST. Gross. - - * h8300-dis.c (bfd_h8_disassemble): Print "exr" when - we're looking for and find EXR. - - * h8300-dis.c (bfd_h8_disassemble): We don't have a match - if we're looking for KBIT and we don't find it. - - * h8300-dis.c (bfd_h8_disassemble): Mask off unwanted bits - for L_3 and L_2. - - * h8300-dis.c (bfd_h8_disassemble): Don't set plen for - 3bit immediate operands. - -Tue Jul 9 10:55:20 1996 Ian Lance Taylor <ian@cygnus.com> - - * Released binutils 2.7. - - * alpha-opc.c: Add new case of "mov". From Klaus Kaempf - <kkaempf@progis.ac-net.de>. - -Thu Jul 4 11:42:51 1996 Ian Lance Taylor <ian@cygnus.com> - - * alpha-opc.c: Correct second case of "mov" to use OPRL. - -Wed Jul 3 16:03:47 1996 Stu Grossman (grossman@critters.cygnus.com) - - * sparc-dis.c (print_insn_sparclite): New routine to print - sparclite instructions. - -Wed Jul 3 14:21:18 1996 J.T. Conklin <jtc@rtl.cygnus.com> - - * m68k-opc.c (m68k_opcodes): Add coldfire support. - -Fri Jun 28 15:53:51 1996 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (asi_table): Add #ASI_N, #ASI_N_L, #ASI_NUCLEUS, - #ASI_NUCLEUS_LITTLE. Rename #ASI_AS_IF_USER_{PRIMARY,SECONDARY}_L - to #ASI_AS_IF_USER_{PRIMARY,SECONDARY}_LITTLE. - -Tue Jun 25 22:58:31 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) - - * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir): - Use autoconf-set values. - (docdir, oldincludedir): Removed. - * configure.in (AC_PREREQ): autoconf 2.5 or higher. - -Fri Jun 21 13:53:36 1996 Richard Henderson <rth@tamu.edu> - - * alpha-opc.c: New file. - * alpha-opc.h: Remove. - * alpha-dis.c: Complete rewrite to use new opcode table. - * configure.in: For bfd_alpha_arch, use alpha-opc.o. - * configure: Rebuild with autoconf 2.10. - * Makefile.in (ALL_MACHINES): Add alpha-opc.o. - (alpha-dis.o): Depend upon $(INCDIR)/opcode/alpha.h, not - alpha-opc.h. - (alpha-opc.o): New target. - -Wed Jun 19 15:55:12 1996 Ian Lance Taylor <ian@cygnus.com> - - * sparc-dis.c (print_insn_sparc): Remove unused local variable i. - Set imm_added_to_rs1 even if the source and destination register - are not the same. - - * sparc-opc.c: Add some two operand forms of the wr instruction. - -Tue Jun 18 15:58:27 1996 Jeffrey A. Law <law@rtl.cygnus.com> - - * h8300-dis.c (bfd_h8_disassemble): Rename "hmode" argument - to just "mode". - - * disassemble.c (disassembler): Handle H8/S. - * h8300-dis.c (print_insn_h8300s): New function for H8/S. - -Tue Jun 18 18:06:50 1996 Ian Lance Taylor <ian@cygnus.com> - - * sparc-opc.c: Add beq/teq as aliases for be/te. - - * ppc-opc.c: Fix fcmpo opcode. From Sergei Steshenko - <sergei@msil.sps.mot.com>. - -Tue Jun 18 15:08:54 1996 Klaus Kaempf <kkaempf@progis.de> - - * makefile.vms: New file. - - * alpha-dis.c (print_insn_alpha): Print lda ra,lit(rz) as mov. - -Mon Jun 10 18:50:38 1996 Ian Lance Taylor <ian@cygnus.com> - - * h8300-dis.c (bfd_h8_disassemble): Always print ABS8MEM with :8, - regardless of plen. - -Tue Jun 4 09:15:53 1996 Doug Evans <dje@canuck.cygnus.com> - - * i386-dis.c (OP_OFF): Call append_prefix. - -Thu May 23 15:18:23 1996 Michael Meissner <meissner@tiktok.cygnus.com> - - * ppc-opc.c (instruction encoding macros): Add explicit casts to - unsigned long to silence a warning from the Solaris PowerPC - compiler. - -Thu Apr 25 19:33:32 1996 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparc_opcodes): Add ultrasparc vis extensions. - -Mon Apr 22 17:12:35 1996 Doug Evans <dje@blues.cygnus.com> - - * sparc-dis.c (X_IMM,X_SIMM): New macros. - (X_IMM13): Delete. - (print_insn_sparc): Merge cases i,I,j together. New cases X,Y. - * sparc-opc.c (sparc_opcodes): Use X for 5 bit shift constants, - Y for 6 bit shift constants. Rewrite entries for crdcxt, cwrcxt, - cpush, cpusha, cpull sparclet insns. - -Wed Apr 17 14:20:22 1996 Doug Evans <dje@canuck.cygnus.com> - - * sparc-dis.c (compute_arch_mask): Replace ANSI style def with K&R. - -Thu Apr 11 17:30:02 1996 Ian Lance Taylor <ian@cygnus.com> - - * sparc-opc.c: Set F_FBR on floating point branch instructions. - Set F_FLOAT on other floating point instructions. - -Mon Apr 8 17:02:48 1996 Michael Meissner <meissner@tiktok.cygnus.com> - - * ppc-opc.c (PPC860): Macro for 860/821 specific instructions and - registers. - (powerpc_opcodes): Add 860/821 specific SPRs. - -Mon Apr 8 14:00:44 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Permit --enable-shared to specify a list of - directories. Set and substitute BFD_PICLIST. - * configure: Rebuild. - * Makefile.in (BFD_PICLIST): Rename from BFD_LIST. Change all - uses. Set to @BFD_PICLIST@. - -Fri Apr 5 17:12:27 1996 Jeffrey A Law (law@cygnus.com) - - * h8300-dis.c (bfd_h8_disassemble): Use "bit" for L_3 immediates, - not "abs", which may be needed for the absolute in something - like btst #0,@10:8. Print L_3 immediates separately from other - immediates. Change ABSMOV reference to ABS8MEM. - -Wed Apr 3 10:40:45 1996 Doug Evans <dje@canuck.cygnus.com> - - * sparc-dis.c (opcodes_initialized): Move inside print_insn_sparc. - (current_arch_mask): New static global. - (compute_arch_mask): New static function. - (print_insn_sparc): Delete sparc_v9_p. New static local - current_mach. Resort opcode table if current_mach changes. - Generalize "insn not supported" test. - (compare_opcodes): Prefer supported opcodes to nonsupported ones. - Delete test for v9/!v9. - * sparc-opc.c (MASK_*): Use SPARC_OPCODE_ARCH_MASK. - (v6notlet): Define. - (brfc): Split into CBR and FBR for coprocessor/fp branches. - (brfcx): Renamed to FBRX. - (condfc): Renamed to CONDFC. Pass v6notlet to CBR (standard - coprocessor mnemonics are not supported on the sparclet). - (condf): Renamed to CONDF. - (SLCBCC2): Delete F_ALIAS flag. - -Sat Mar 30 21:45:59 1996 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparc_opcodes): rd must be 0 for - mov foo,{%y,%psr,%wim,%tbr}. Support mov foo,%asrX. - -Fri Mar 29 13:02:40 1996 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (config.status): Depend upon BFD VERSION file, so - that the shared library version number is set correctly. - -Tue Mar 26 15:47:14 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Use AC_CHECK_TOOL to find ar and ranlib. From - Miles Bader <miles@gnu.ai.mit.edu>. - * configure: Rebuild. - -Sat Mar 16 13:04:07 1996 Fred Fish <fnf@cygnus.com> - - * z8kgen.c (internal, gas): Call xmalloc rather than unchecked - malloc. - -Tue Mar 12 12:14:10 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure: Rebuild with autoconf 2.8. - -Thu Mar 7 15:11:10 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc-dis.c (print_insn_sparc): Handle 'O' operand char like 'r'. - * sparc-opc.c (sparc_opcodes): Use 'O' operand char for `neg reg'. - -Tue Mar 5 15:51:57 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Don't set SHLIB or SHLINK to an empty string, - since they appear as targets in Makefile.in. - * configure: Rebuild. - -Mon Feb 26 13:03:40 1996 Stan Shebs <shebs@andros.cygnus.com> - - * mpw-make.sed: Edit out shared library support bits. - -Tue Feb 20 20:48:28 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc-opc.c (v8,v6notv9): Add MASK_SPARCLET. - (sparc_opcode_archs): Add MASK_V8 to sparclet entry. - (sparc_opcodes): Add sparclet insns. - (sparclet_cpreg_table): New static local. - (sparc_{encode,decode}_sparclet_cpreg): New functions. - * sparc-dis.c (print_insn_sparc): Handle sparclet cpregs. - -Tue Feb 20 11:02:44 1996 Alan Modra <alan@mullet.Levels.UniSA.Edu.Au> - - * i386-dis.c (index16): New static variable. - (putop): Print jecxz for 32 bit case, jcxz for 16 bit, not the - other way around. - (OP_indirE): Return result of OP_E. - (OP_E): Check for 16 bit addressing mode, and disassemble - correctly. Optimised 32 bit case a little. Don't print - "(base,index,scale)" when sib specifies only an offset. - -Mon Feb 19 12:32:17 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Set and substitute SHLIB_DEP. - * configure: Rebuild. - * Makefile.in (SHLIB_DEP): New variable. - (LIBIBERTY_LISTS, BFD_LIST): New variables. - (stamp-piclist): Depend upon LIBIBERTY_LISTS and BFD_LIST. If - COMMON_SHLIB, add them to piclist with appropriate modifications. - ($(SHLIB)): Depend upon $(SHLIB_DEP). Don't check COMMON_SHLIB - here: just use piclist. - -Mon Feb 19 02:03:50 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc-dis.c (MASK_V9,V9_ONLY_P,V9_P): Define. - (print_insn_sparc): Rewrite v9/not-v9 tests. - (compare_opcodes): Likewise. - * sparc-opc.c (MASK_<ARCH>): Define. - (v6,v7,v8,sparclite,v9,v9a): Redefine. - (sparclet,v6notv9): Define. - (sparc_opcode_archs): Delete member `conflicts'. Add `supported'. - (sparc_opcodes): Delete F_NOTV9, use v6notv9 instead. - -Thu Feb 15 14:45:05 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Call AC_PROG_CC before configure.host. - * configure: Rebuild. - - * Makefile.in (SONAME): Remove leading ../bfd/ from $(SHLIB). - -Wed Feb 14 19:01:27 1996 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c (onebyte_has_modrm): New static array. - (twobyte_has_modrm): New static array. - (print_insn_i386): Only fetch the mod/reg/rm byte if it is needed. - -Tue Feb 13 15:15:01 1996 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in ($(SHLINK)): Check ts against $(SHLIB), not - $(SHLINK). - -Mon Feb 12 16:26:06 1996 Michael Meissner <meissner@tiktok.cygnus.com> - - * ppc-opc.c (PPC): Undef, so default defination on Windows NT - doesn't conflict. - -Wed Feb 7 13:59:54 1996 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c (m68k_opcodes): The bkpt instruction is supported on - m68010up, not just m68020up | cpu32. - - * Makefile.in (SONAME): New variable. - ($(SHLINK)): Make a link to the transformed name, as well. - (stamp-tshlink): New target. - (install): Skip stamp-tshlink during install. - -Tue Feb 6 12:28:54 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Call AC_ARG_PROGRAM. - * configure: Rebuild. - * Makefile.in (program_transform_name): New variable. - (install): Transform library name before installing it. - -Mon Feb 5 16:14:42 1996 Ian Lance Taylor <ian@cygnus.com> - - * i960-dis.c (mem): Add HX dcinva instruction. - - Support for building as a shared library, based on patches from - Alan Modra <alan@spri.levels.unisa.edu.au>: - * configure.in: Add AC_ARG_ENABLE for shared and commonbfdlib. - New substitutions: ALLLIBS, PICFLAG, SHLIB, SHLIB_CC, - SHLIB_CFLAGS, COMMON_SHLIB, SHLINK. - * configure: Rebuild. - * Makefile.in (ALLLIBS): New variable. - (PICFLAG, SHLIB, SHLIB_CC, SHLIB_CFLAGS): New variables. - (COMMON_SHLIB, SHLINK): New variables. - (.c.o): If PICFLAG is set, compile twice, once PIC, once normal. - (STAGESTUFF): Remove variable. - (all): Depend upon $(ALLLIBS) rather than $(TARGETLIB). - (stamp-piclist, piclist): New targets. - ($(SHLIB), $(SHLINK)): New targets. - ($(OFILES)): Depend upon stamp-picdir. - (disassemble.o): Build twice if PICFLAG is set. - (MOSTLYCLEAN): Add pic/*.o. - (clean): Remove $(SHLIB), $(SHLINK), piclist, and stamp-piclist. - (distclean): Remove pic and stamp-picdir. - (install): Install shared libraries. - (stamp-picdir): New target. - -Fri Feb 2 17:15:25 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc-dis.c (print_insn_sparc): Delete DISASM_RAW_INSN support. - Print unknown instruction as "unknown", rather than in hex. - -Tue Jan 30 14:06:08 1996 Ian Lance Taylor <ian@cygnus.com> - - * dis-buf.c: Include "sysdep.h" before "dis-asm.h". - -Thu Jan 25 20:24:07 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc-opc.c (sparc_opcode_archs): Mark v8/sparclite as conflicting. - -Thu Jan 25 11:56:49 1996 Ian Lance Taylor <ian@cygnus.com> - - * i386-dis.c (print_insn_i386): Only fetch the mod/reg/rm byte - when necessary. From Ulrich Drepper - <drepper@myware.rz.uni-karlsruhe.de>. - -Thu Jan 25 03:39:10 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc-dis.c (print_insn_sparc): NUMOPCODES replaced with - sparc_num_opcodes. Update architecture enum values. - * sparc-opc.c (sparc_opcode_archs): Replaces architecture_pname. - (sparc_opcode_lookup_arch): New function. - (sparc_num_opcodes): Renamed from bfd_sparc_num_opcodes. - (sparc_opcodes): Add v9a shutdown insn. - -Mon Jan 22 08:29:59 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc-dis.c (print_insn_sparc): Renamed from print_insn. - If DISASM_RAW_INSN, print insn in hex. Handle v9a as opcode - architecture. - (print_insn_sparc64): Deleted. - * disassemble.c (disassembler, case bfd_arch_sparc): Always use - print_insn_sparc. - - * sparc-opc.c (architecture_pname): Add v9a. - -Fri Jan 12 14:35:58 1996 David Mosberger-Tang <davidm@AZStarNet.com> - - * alpha-opc.h (alpha_insn_set): VAX floating point opcode was - incorrectly defined as 0x16 when it should be 0x15. - (FLOAT_FORMAT_MASK): function code is 11 bits, not just 7 bits! - (alpha_insn_set): added cvtst and cvttq float ops. Also added - excb (exception barrier) which is defined in the Alpha - Architecture Handbook version 2. - * alpha-dis.c (print_insn_alpha): Fixed special-case decoding for - OPERATE_FORMAT_CODE type instructions. The bug caused mulq to be - disassembled as or, for example. - -Wed Jan 10 12:37:22 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (print_insn_arg): Print cases 'i' and 'u' in hex. - (_print_insn_mips): Change i from int to unsigned int. - -Thu Jan 4 17:21:10 1996 David Edelsohn <edelsohn@mhpcc.edu> - - * ppc-opc.c (powerpc_opcodes): tlbi POWER opcode form different - from tlbie PowerPC opcode. Add PPC603 tlbld and tlbli. - -Thu Dec 28 13:29:19 1995 John Hassey <hassey@rtp.dg.com> - - * i386-dis.c: Added Pentium Pro instructions. - -Tue Dec 19 22:56:35 1995 Michael Meissner <meissner@tiktok.cygnus.com> - - * ppc-opc.c (fsqrt{,.}): Duplicate for PowerPC in addition to - being for Power2. - -Fri Dec 15 14:14:15 1995 J.T. Conklin <jtc@rtl.cygnus.com> - - * sh-opc.h (sh_nibble_type): Added REG_B. - (sh_arg_type): Added A_REG_B. - (sh_table): Added pref and bank reg versions of ldc, ldc.l, stc - and stc.l opcodes. - * sh-dis.c (print_insn_shx): Added cases for REG_B and A_REG_B. - -Fri Dec 15 16:44:31 1995 Ian Lance Taylor <ian@cygnus.com> - - * disassemble.c (disassembler): Use new bfd_big_endian macro. - -Tue Dec 12 12:22:24 1995 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (distclean): Remove stamp-h. From Ronald - F. Guilmette <rfg@monkeys.com>. - -Tue Dec 5 13:42:44 1995 Stan Shebs <shebs@andros.cygnus.com> - - From David Mosberger-Tang <davidm@azstarnet.com>: - * alpha-dis.c (print_insn_alpha): fixed decoding of cpys - instruction. - -Mon Dec 4 12:29:05 1995 J.T. Conklin <jtc@rtl.cygnus.com> - - * sh-opc.h (sh_arg_type): Added A_SSR and A_SPC. - (sh_table): Added many SH3 opcodes. - * sh-dis.c (print_insn_shx): Added cases for A_SSR and A_SPC. - -Fri Dec 1 07:42:18 1995 Michael Meissner <meissner@tiktok.cygnus.com> - - * ppc-opc.c (subfc., subfco): Mark this PPCCOM, not PPC. - (subco,subco.): Mark this PPC, not PPCCOM. - -Mon Nov 27 13:09:52 1995 Ian Lance Taylor <ian@cygnus.com> - - * configure: Rebuild with autoconf 2.7. - -Tue Nov 21 18:28:06 1995 Ian Lance Taylor <ian@cygnus.com> - - * configure: Rebuild with autoconf 2.6. - -Wed Nov 15 19:02:53 1995 Ken Raeburn <raeburn@cygnus.com> - - * configure.in: Sort list of architectures. Accept but do nothing - for alliant, convex, pyramid, romp, and tahoe. - -Wed Nov 8 20:18:59 1995 Ian Lance Taylor <ian@cygnus.com> - - * a29k-dis.c (print_special): Change num to unsigned int. - -Wed Nov 8 20:10:35 1995 Eric Freudenthal <freudenthal@nyu.edu> - - * a29k-dis.c (print_insn): Cast insn24 to unsigned long when - shifting it. - -Tue Nov 7 15:21:06 1995 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Call AC_CHECK_PROG to find and cache AR. - * configure: Rebuilt. - -Mon Nov 6 17:39:47 1995 Harry Dolan <dolan@ssd.intel.com> - - * configure.in: Add case for bfd_i860_arch. - * configure: Rebuild. - -Fri Nov 3 12:45:31 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c (m68k_opcodes): Correct fmoveml operands. - * m68k-dis.c (NEXTSINGLE): Change i to unsigned int. - (NEXTDOUBLE): Likewise. - (print_insn_m68k): Don't match fmoveml if there is more than one - register in the list. - (print_insn_arg): Handle a place of '8' for a type of 'L'. - -Thu Nov 2 23:06:33 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: Use #W rather than #w. - * m68k-dis.c (print_insn_arg): Handle new 'W' place. - -Wed Nov 1 13:30:24 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c (m68k_opcode_aliases): Add dbfw as an alias for dbf, - and likewise for all the dbxx opcodes. - -Mon Oct 30 20:50:40 1995 Fred Fish <fnf@cygnus.com> - - * arc-dis.c: Include elf-bfd.h rather than libelf.h. - -Mon Oct 23 11:11:34 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk> - - * mips-opc.c: Added shorthand (V1) for INSN_4100 manifest. Added - the VR4100 specific instructions to the mips_opcodes structure. - -Thu Oct 19 11:05:23 1995 Stan Shebs <shebs@andros.cygnus.com> - - * mpw-config.in, mpw-make.sed: Remove ugly workaround for - ugly Metrowerks bug in CW6, is fixed in CW7. - -Mon Oct 16 12:59:01 1995 Michael Meissner <meissner@tiktok.cygnus.com> - - * ppc-opc.c (whole file): Add flags for common/any support. - -Tue Oct 10 11:06:07 1995 Fred Fish <fnf@cygnus.com> - - * Makefile.in (BISON): Remove macro. - (FLAGS_TO_PASS): Remove BISON. - -Fri Oct 6 16:26:45 1995 Ken Raeburn <raeburn@cygnus.com> - - Mon Sep 25 22:49:32 1995 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-dis.c (print_insn_m68k): Recognize all two-word - instructions that take no args by looking at the match mask. - (print_insn_arg): Always print "%" before register names. - [case 'c']: Use "nc" for the no-cache case, as recognized by gas. - [case '_']: Don't print "@#" before address. - [case 'J']: Use "%s" as format string, not register name. - [case 'B']: Treat place == 'C' like 'l' and 'L'. - -Thu Oct 5 22:16:20 1995 Ken Raeburn <raeburn@cygnus.com> - - * i386-dis.c: Describe cmpxchg8b operand, and spell the opcode - name correctly. - -Tue Oct 3 08:30:20 1995 steve chamberlain <sac@slash.cygnus.com> - - From David Mosberger-Tang <davidm@azstarnet.com> - - * alpha-opc.h (MEMORY_FUNCTION_FORMAT_MASK): added. - (alpha_insn_set): added definitions for VAX floating point - instructions (Unix compilers don't generate these, but handcoded - assembly might still use them). - - * alpha-dis.c (print_insn_alpha): added support for disassembling - the miscellaneous instructions in the Alpha instruction set. - -Tue Sep 26 18:47:20 1995 Stan Shebs <shebs@andros.cygnus.com> - - * mpw-config.in: Add m68k-opc.c.o to BFD_MACHINES for m68k, - no longer create sysdep.h, sed ppc-opc.c to work around a - serious Metrowerks C bug. - * mpw-make.in: Remove. - * mpw-make.sed: New file, used by mpw-configure to edit - Makefile.in into an MPW makefile. - -Wed Sep 20 12:55:28 1995 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (maintainer-clean): New synonym for realclean. - -Tue Sep 19 15:28:36 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: Split pmove patterns which use 'P' into patterns - which use '0', '1', and '2' instead. Specify the proper size for - a pmove immediate operand. Correct the pmovefd patterns to be - moves to a register, not from a register. - * m68k-dis.c (print_insn_arg): Replace 'P' with '0', '1', '2'. - -Thu Sep 14 11:58:22 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparc_opcodes): Mark all insns that reference - %psr, %wim, %tbr as F_NOTV9. - -Fri Sep 8 01:07:38 1995 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (Makefile): Just rebuild Makefile when running - config.status. - (config.h, stamp-h): New targets. - * configure.in: Call AC_CONFIG_HEADER and AC_CANONICAL_SYSTEM - earlier. Don't bother to call AC_ARG_PROGRAM. Touch stamp-h when - rebuilding config.h. - * configure: Rebuild. - - * mips-opc.c: Change unaligned loads and stores with "t,A" - operands to use "t,A(b)". - -Thu Sep 7 19:02:46 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh-dis.c (print_insn_shx): Add F_FR0 support. - -Thu Sep 7 19:02:46 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh-dis.c (print_insn_shx): Change loop over op->arg[n] to iterate - until 3 instead of until 2. - -Wed Sep 6 21:21:33 1995 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (ALL_CFLAGS): Define. - (.c.o, disassemble.o): Use $(ALL_CFLAGS). - (MOSTLYCLEAN): Add config.log. - (distclean): Don't remove config.log. - * configure.in: Substitute HDEFINES. - * configure: Rebuild. - -Wed Sep 6 15:08:09 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh-opc.h (sh_arg_type): Add F_FR0. - (sh_table, case fmac): Add F_FR0 as first argument. - -Wed Sep 6 15:08:09 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh-opc.h (sh_opcode_info): Increase arg array size to 4. - -Tue Sep 5 18:28:10 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc-dis.c: Remove all references to NO_V9. - -Tue Sep 5 20:03:26 1995 Ian Lance Taylor <ian@cygnus.com> - - * aclocal.m4: Just include ../bfd/aclocal.m4. - * configure: Rebuild. - -Tue Sep 5 16:09:59 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc-dis.c (X_DISP19): Define. - (print_insn, case 'G'): Use it. - (print_insn, case 'L'): Sign extend displacement. - -Mon Sep 4 14:28:46 1995 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Run ../bfd/configure.host before AC_PROG_CC. - Subsitute CFLAGS and AR. Call AC_PROG_INSTALL. Don't substitute - host_makefile_frag or frags. - * aclocal.m4: New file. - * configure: Rebuild. - * Makefile.in (INSTALL): Set to @INSTALL@. - (INSTALL_PROGRAM): Set to @INSTALL_PROGRAM@. - (INSTALL_DATA): Set to @INSTALL_DATA@. - (AR): Set to @AR@. - (AR_FLAGS): Set to rc rather than qc. - (CC): Define as @CC@. - (CFLAGS): Set to @CFLAGS@. - (@host_makefile_frag@): Remove. - (config.status): Remove dependency upon @frags@. - - * configure.in: ../bfd/config.bfd now just sets shell variables. - Use them rather than looking through target Makefile fragments. - * configure: Rebuild. - -Thu Aug 31 12:35:32 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh-opc.h (ftrc): Change FPUL_N to FPUL_M. - -Wed Aug 30 13:52:28 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparc_opcodes): Delete duplicate wr %y insn. - Add clrx, iprefetch, signx, clruw, cas, casl, casx, casxl synthetic - sparc64 insns. - - * sparc-opc.c (sparc_opcodes): Fix prefetcha insn. - (lookup_{name,value}): New functions. - (prefetch_table): New static local. - (sparc_{encode,decode}_prefetch): New functions. - * sparc-dis.c (print_insn): Handle '*' arg (prefetch function). - -Wed Aug 30 11:11:58 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh-opc.h: Add blank lines to improve readabililty of sh3e - instructions. - -Wed Aug 30 11:09:38 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh-dis.c: Correct comment on first line of file. - -Tue Aug 29 15:37:18 1995 Doug Evans <dje@canuck.cygnus.com> - - * disassemble.c (disassembler): Handle bfd_mach_sparc64. - - * sparc-opc.c (asi, membar): New static locals. - (sparc_{encode,decode}_{asi,membar}): New functions. - (sparc_opcodes, membar insn): Fix. - * sparc-dis.c (print_insn): Call sparc_decode_asi. - Support decoding of membar masks. - (X_MEMBAR): Define. - -Sat Aug 26 21:22:48 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c (m68k_opcode_aliases): Add br, brs, brb, brw, brl. - -Mon Aug 21 17:33:36 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c (m68k_opcode_aliases): Add bhib as an alias for bhis, - and likewise for the other branches. Add bhs as an alias for bcc, - and likewise for the size variants. Add dbhs as an alias for - dbcc. - -Fri Aug 11 13:40:24 1995 Jeff Law (law@snake.cs.utah.edu) - - * sh-opc.h (FP sts instructions): Update to match reality. - -Mon Aug 7 16:12:58 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k-dis.c: (fpcr_names): Add % before all register names. - (reg_names): Likewise. - (print_insn_arg): Don't explicitly print % before register names. - Add % before register names in static array names. In case 'r', - print data registers as `@(Dn)', not `Dn@'. When printing a - memory address, don't print @# before it. - (print_indexed): Change base_disp and outer_disp from int to - bfd_vma. Print using MIT syntax, not mutant invalid Motorola - syntax. Sign extend 8 byte displacement correctly. - (print_base): Print using MIT syntax. Print zpc when appropriate. - Change parameter disp from int to bfd_vma. - - * m68k-opc.c (m68k_opcode_aliases): Add jsrl and jsrs as aliases - for jsr. - -Mon Aug 7 02:21:40 1995 Jeff Law (law@snake.cs.utah.edu) - - * sh-dis.c (print_insn_shx): Handle new operand types F_REG_N, - F_REG_M, FPSCR_M, FPSCR_N, FPUL_M and FPUL_N. - * sh-opc.h (sh_arg_type): Add new operand types. - (sh_table): Add new opcodes from SH3E Floating Point ISA. - -Sat Aug 5 16:50:14 1995 Fred Fish <fnf@cygnus.com> - - * Makefile.in (distclean): Remove generated file config.h. - -Sat Aug 5 16:50:14 1995 Fred Fish <fnf@cygnus.com> - - * Makefile.in (distclean): Remove generated file config.h. - -Wed Aug 2 18:33:40 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: New file, holding tables from include/opcode/m68k.h. - Clean up tables. - * m68k-dis.c: Remove BREAK_UP_BIG_DECL stuff. - (opcode): Remove. - (print_insn_m68k): Change d to be const. Use m68k_numopcodes - rather than numopcodes. Use m68k_opcodes rather than removed - opcode function. Don't check F_ALIAS. - (print_insn_arg): Change first parameter to be const char *. - * Makefile.in (ALL_MACHINES): Add m68k-opc.o. - (m68k-opc.o): New target. - * configure.in: Build m68k-opc.o for bfd_m68k_arch. - * configure: Rebuild. - -Wed Aug 2 08:23:38 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc-dis.c (HASH_SIZE, HASH_INSN): Define. - (opcode_bits, opcode_hash_table): New variables. - (opcodes_initialized): Renamed from opcodes_sorted. - (build_hash_table): New function. - (is_delayed_branch): Use hash table. - (print_insn): Renamed from print_insn_sparc, made static. - Build and use hash table. If !sparc64, ignore sparc64 insns, - and vice-versa if sparc64. - (print_insn_sparc, print_insn_sparc64): New functions. - (compare_opcodes): Move sparc64 opcodes to end. - Print commutative insns with constant second. - * sparc-opc.c (all non-v9 insns): Use flag F_NOTV9 instead of F_ALIAS. - -Tue Aug 1 00:12:49 1995 Ian Lance Taylor <ian@cygnus.com> - - * sh-dis.c (print_insn_shx): Remove unused local dslot. Use - print_address_func for A_BDISP12 and A_BDISP8. Correct test which - avoids printing a delay slot in a delay slot. - * sh-opc.h (sh_table): Fully bracket last entry. - -Mon Jul 31 12:04:47 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sllx, srax, srlx): Fix disassembly. - -Wed Jul 12 00:59:34 1995 Ken Raeburn <raeburn@kr-pc.cygnus.com> - - * configure.in: Get host_makefile_frag from ${srcdir}. - - * configure.in: Autoconfiscated. Check for string[s].h. Create - config.h from config.in. Don't set up sysdep.h link. - * sysdep.h: New file. - * configure, config.in: New files, generated from configure.in. - * Makefile.in: Updated to be processed autoconf-style. - (distclean): Keep sysdep.h. Remove config.log and config.cache. - (Makefile): Depend on config.status. - (config.status): New rule. - * configure.bat: Update Makefile substitutions. - -Tue Jul 11 14:23:37 1995 Jeff Spiegel <jeffs@lsil.com> - - * mips-opc.c (L1): Define. - (mips_opcodes): Add R4010 instructions: flushi, flushd, flushid, - addciu, madd, maddu, ffc, ffs, msub, msubu, selsi, selsr, waiti, - and wb. - -Tue Jul 11 11:49:49 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c (mips_opcodes): For the move pseudo-op, prefer daddu - if ISA 3 and addu otherwise, replacing or, since some MIPS chips - have multiple add units but only a single logical unit. - - * ppc-opc.c (powerpc_operands): Change CR to use a bitsize of 3, - shifted by 18, without any insertion or extraction function. - (insert_cr, extract_cr): Remove. - -Wed Jun 21 20:05:39 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - * m68k-dis.c (print_insn_arg, print_indexed): Print "%" before - register names. - -Thu Jun 15 17:23:31 1995 Stan Shebs <shebs@andros.cygnus.com> - - * mpw-config.in: Add sh and i386 configs, remove sparc config. - * sh-opc.h: Add copyright. - -Mon Jun 5 03:30:43 1995 Ken Raeburn <raeburn@kr-laptop.cygnus.com> - - * Makefile.in (crunch-m68k): Delete extra target accidentally - checked in a while ago. - -Wed May 24 16:22:13 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh-opc.h (sh_table): Add SH3 support. - -Wed May 24 14:16:08 1995 Steve Chamberlain <sac@slash.cygnus.com> - - * sh-opc.h: Added bsrf and braf. - -Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk) - - * arm-opc.h (arm_opcodes): Add 64-bit multiply patterns. Delete - bogus [ls]fm{ea,fd} patterns. - - * arm-opc.h (arm_opcodes): Correct typos in stm, ldm, std, and ldc. - * arm-dis.c (print_insn_arm): Make GIVEN a parameter, don't try and - initialize it from memory. Make function static. - (print_insn_{big,little}_arm): New functions. - * disassemble.c (disassembler, case bfd_arch_arm): Disassemble for - the correct endianness. - -Mon Apr 24 14:18:05 1995 Jason Molenda (crash@phydeaux.cygnus.com> - - * sh-opc.h (sh_nibble_type, sh_arg_type): remove trailing , from - enum list. - -Wed Apr 19 14:07:03 1995 Michael Meissner <meissner@tiktok.cygnus.com> - - * m68k-dis.c (opcode): Finish change made by Kung Hsu on April - 17th, so that it builds again using GCC as the compiler. - -Tue Apr 18 12:14:51 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - * mips-dis.c (print_insn_little_mips): Cast return value from - bfd_getl32 from bfd_vma to unsigned long, because _print_insn_mips - expects an unsigned long, and that might be fewer words of - argument storage (e.g., if bfd_vma is long long on a 32-bit - machine). - (print_insn_big_mips): Likewise with bfd_getb32 value. - (_print_insn_mips): Now static. - -Mon Apr 17 12:23:28 1995 Kung Hsu <kung@rtl.cygnus.com> - - * m68k-dis.c: Take out #define BREAK_UP_BIG_DECL kludge, because - gcc memory hog problem with initializer is fixed. - -Mon Apr 10 15:55:01 1995 Stan Shebs <shebs@andros.cygnus.com> - - Merge in support for Mac MPW as a host. - (Old change descriptions retained for informational value.) - - * mpw-config.in (archname): Compute from the config. - (BFD_MACHINES, ARCHDEFS): Put into mk.tmp. - - * mpw-config.in (target_arch): Compute from canonical target. - (m68k, mips, powerpc, sparc): Add architectures. - * mpw-make.in (disassemble.c.o): Add. - (ALL_CFLAGS): Remove special flags (-mc68020 -mc68881 -model far). - - * mpw-config.in (BFD_MACHINES): Set to a default value. - * mpw-make.in (BFD_MACHINES): Remove wired-in value. - - * mpw-make.in (CSEARCH): Add extra-include to search path. - - * mpw-config.in (varargs.h): Don't create. - (sysdep.h): Create using forward-include. - * mpw-make.in (CSEARCH): Add include/mpw to search path. - - * mpw-config.in: New file, MPW version of configure.in. - * mpw-make.in: New file, MPW version of Makefile.in. - -Fri Mar 31 14:23:38 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - * alpha-dis.c (print_insn_alpha): Put empty statement after - default label. - -Tue Mar 21 10:51:40 1995 Jeff Law (law@snake.cs.utah.edu) - - * hppa-dis.c (sign_extend): Delete, redundant with libhppa.h version. - (low_sign_extend): Likewise. - (get_field): Delete unused function. - (set_field, deposit_14, deposit_21): Likewise. - -Fri Mar 17 15:55:53 1995 J.T. Conklin <jtc@rtl.cygnus.com> - - * i386-dis.c: Support for more pentium opcodes. From Guy Harris - (guy@netapp.com). - -Tue Mar 14 00:52:57 1995 Ken Raeburn (raeburn@kr-pc.cygnus.com) - - Sat Feb 11 17:22:41 1995 Klaus Kaempf (kkaempf@didymus.rmi.de) - - * alpha-opc.h (OSF_ASMCODE): define - print pal-code names as defined in App C of the - Alpha Architecture Reference Manual - - * alpha-dis.c: cleaned up output - print stylized code forms as defined in App A.4.3 of the - Alpha Architecture Reference Manual - -Wed Mar 8 15:21:14 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c: Add new mips4 instructions. Don't set INSN_RFE for - `rfe'. - * mips-dis.c (print_insn_arg): Handle new argument types 'h', 'R', - 'N', and 'M'. - -Wed Mar 8 02:54:05 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - * m68k-dis.c (opcode): New function. Returns address of opcode - table entry given index, even if the opcode table was split to - work around gcc bugs. - (print_insn_m68k): Call opcode instead of referencing m68k_opcodes - directly. - (BREAK_UP_BIG_DECL): Make secondary array static and const. - (reg_names): Now const. - (print_insn_arg): Arrays cacheFieldName and names now const. - (print_indexed): Array scales now const. - -Tue Mar 7 16:41:21 1995 Ian Lance Taylor <ian@cygnus.com> - - * ppc-opc.c: Sort recently added instructions by minor opcode - number within major opcode number. - -Mon Mar 6 10:04:36 1995 Jeff Law (law@snake.cs.utah.edu) - - * hppa-dis.c: Include libhppa.h. - -Fri Feb 24 19:15:36 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c: Change dli to use M_DLI, and add dla. - -Mon Feb 20 23:54:38 1995 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * Makefile.in (ALL_MACHINES): Add w65-dis.o. - -Thu Feb 16 17:34:41 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c: Add r4650 mul instruction. - -Wed Feb 15 15:45:20 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c: Add uld and usd macros for unaligned double load and - store. - -Tue Feb 14 13:17:37 1995 Michael Meissner <meissner@tiktok.cygnus.com> - - * ppc-opc.c (powerpc_opcodes): Add 403GA opcodes rfci, dccci, - mfdcr, mtdcr, icbt, iccci. - -Thu Feb 9 12:28:13 1995 Stan Shebs <shebs@andros.cygnus.com> - - * i960-dis.c (struct tabent, struct sparse_tabent): Change the - signed char fields to shorts, more portable. - -Wed Feb 8 17:29:29 1995 Stan Shebs <shebs@andros.cygnus.com> - - * i960-dis.c (struct tabent, struct sparse_tabent): Declare the - char fields as signed chars, since they may have negative values. - -Mon Feb 6 10:52:06 1995 J.T. Conklin <jtc@rtl.cygnus.com> - - * i386-dis.c (dis386_twobyte): Add cpuid, From Charles Hannum - (mycroft@netbsd.org). - -Mon Jan 30 12:38:00 1995 Ian Lance Taylor <ian@cygnus.com> - - From "Logg, Ed" <elogg@ea.com>: - * ppc-opc.c (extract_bdm): Correct parenthezisation. - * ppc-dis.c (print_insn_powerpc): Print .long before unrecognized - value. - -Thu Jan 26 18:32:08 1995 Ian Lance Taylor <ian@cygnus.com> - - * ppc-opc.c: Changes based on patch from David Edelsohn - <edelsohn@mhpcc.edu>. - (powerpc_operands): Add operands SPRBAT and SPRG. Split TBR out of - SPR. - (FXM_MASK): Define. - (insert_tbr): New static function. - (extract_tbr): New static function. - (XFXFXM_MASK, XFXM): Define. - (XSPRBAT_MASK, XSPRG_MASK): Define. - (powerpc_opcodes): Add instructions to access special registers by - name. Add mtcr and mftbu. - -Tue Jan 17 10:56:43 1995 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * mips-opc.c (P3): Define. - (mips_opcodes): Add mad and madu. - -Sun Jan 15 16:32:59 1995 Steve Chamberlain <sac@splat> - - * configure.in: Add W65 support. - * disassemble.c: Likewise. - * w65-opc.h, w65-dis.c: New files. - -Wed Dec 28 22:15:33 1994 Steve Chamberlain (sac@jonny.cygnus.com) - - * h8300-dis.c (bfd_h8_disassemble): Add support for 2 bit - immediates. - -Tue Dec 20 11:25:12 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * mips-opc.c: Add dli as a synonym for li. - -Thu Dec 8 18:23:31 1994 Ken Raeburn <raeburn@cujo.cygnus.com> - - * alpha-dis.c (print_insn_alpha): Handle call_pal instruction, and - print something for reserved opcode values, even if it won't - assemble again. - - * mips-dis.c (_print_insn_mips): When initializing, shift right - and mask, to avoid sign extension problems on the Alpha. - - * m68k-dis.c (print_insn_arg, case 'J'): Handle buscr and pcr - control registers. - -Wed Nov 23 22:34:51 1994 Steve Chamberlain (sac@jonny.cygnus.com) - - * sh-opc.h (mov.l gbr): Get direction right. - * sh-dis.c (print_insn_shx): New function. - (print_insn_shl, print_insn_sh): Call print_insn_shx to - print opcodes with right byte order. - -Thu Nov 3 19:32:22 1994 Ken Raeburn <raeburn@cujo.cygnus.com> - - * ns32k-dis.c (struct ns32k_option): Renamed from struct option, - to avoid conflicts with getopt. - -Mon Oct 31 18:48:10 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * hppa-dis.c (print_insn_hppa): Read the instruction using - bfd_getb32, so that it works on a little endian or 64 bit host. - Remove unused local variable op. - -Tue Oct 25 17:07:57 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * mips-opc.c: Use or instead of addu for pseudo-op move, since - addu does not work correctly if -mips3. - -Wed Oct 19 13:40:16 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * a29k-dis.c (print_special): Add special register names defined - on 29030, 29040 and 29050. - (print_insn): Handle new operand type 'I'. - -Wed Oct 12 11:59:55 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * Makefile.in (INSTALL): Use top level install.sh script. - -Wed Oct 5 19:16:29 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * sparc-dis.c: Rewrite to use bitfields, rather than a union, so - that it works on a little endian host. - -Tue Oct 4 12:14:21 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * configure.in: Use ${config_shell} when running config.bfd. - -Wed Sep 21 18:49:12 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) - - * mips-opc.c (mips_opcodes): "dabs" is only available with -mips3. - -Thu Sep 15 16:30:22 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) - - * a29k-dis.c (print_insn): Print the opcode. - -Wed Sep 14 17:52:14 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) - - * mips-opc.c (mips_opcodes): Set WR_t for sc and scd. - -Sun Sep 11 22:32:17 1994 Jeff Law (law@snake.cs.utah.edu) - - * hppa-dis.c (reg_names): Use r26-r23 for arg0-arg3. - -Tue Sep 6 11:37:12 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) - - * mips-opc.c: Set INSN_STORE_MEMORY flag for all instructions - which store a value into memory. - -Sun Sep 04 17:58:10 1994 Richard Earnshaw (rwe@pegasus.esprit.ec.org) - - * configure.in, Makefile.in, disassemble.c: Add support for the ARM. - * arm-dis.c, arm-opc.h: New files. - -Fri Aug 5 14:00:05 1994 Stan Shebs (shebs@andros.cygnus.com) - - * Makefile.in (ns32k-dis.o): Add dependency. - * ns32k-dis.c (print_insn_arg): Declare initialized local as - string, not as array of chars. - -Thu Jul 28 18:14:16 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * sparc-dis.c (print_insn_sparc): Handle new operand type 'x'. - - * sparc-opc.c: Added sparclite extended FP operations, and - versions of v9 impdep* instructions permitting specification of - the OPF field. - -Tue Jul 26 16:36:03 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * i960-dis.c (reg_names): Now const. - (struct sparse_tabent): New type, copied from array type in mem - function. - (ctrl): Local static array ctrl_tab now const. - (cobr): Local static array cobr_tab now const. - (mem): Local variables reg1, reg2, reg3 now point to const. Local - static variable mem_tab no longer explicitly initialized. Changed - mem_init to const array of struct sparse_tabent. - (reg): Local static variable reg_tab no longer explicitly - initialized. Changed reg_init to const array of struct - sparse_tabent. - (ea): Local static array scale_tab now const. - - * i960-dis.c (reg): Added i960JX instructions to reg_init table. - (REG_MAX): Updated. - -Tue Jul 19 21:00:00 1994 DJ Delorie (dj@ctron.com) - - * configure.bat: the disassember needs to be enabled for - "objdump -d" to work in djgpp. - -Wed Jul 13 18:01:58 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * ns32k-dis.c: Deleted all code in "#ifdef GDB". - (invalid_float): Enabled general version, doesn't require running - on ns32k host. Changed to take char* argument, and test for - explicitly specified sizes, instead of using sizeof() on host CPU - types. - (INVALID_FLOAT): Cast first argument. - (opt_u, opt_U, opt_O, opt_C, opt_S, list_P532, list_M532, - list_P032, list_M032): Now const. - (optlist, list_search): Made appropriate arguments now point to - const. - (print_insn_arg): Changed static array of one-character-string - pointers into a static const array of characters; fixed sprintf - statement accordingly. - -Sun Jul 10 00:27:47 1994 Ian Dall (dall@hfrd.dsto.gov.au) - - * opcodes/ns32k-dis.c: Semi-new file. Had apparently been dropped - from distribution. A ns32k-dis.c from a previous distribution has - been brought up to date and supports the new interface. - - * disassemble.c: define ARCH_ns32k and add case bfd_arch_ns32k. - - * configure.in: add bfd_ns32k_arch target support. - - * Makefile.in: add ns32k-dis.o to ALL_MACHINES. - Add ns32k-dis.c to CFILES. Add dependencies for ns32k-dis.o. - -Wed Jun 29 22:10:37 1994 Steve Chamberlain (sac@cygnus.com) - - * h8300-dis.c (bfd_h8_disassemble): Get 16bit branch - disassembly right. - -Tue Jun 28 13:22:06 1994 Stan Shebs (shebs@andros.cygnus.com) - - * h8300-dis.c, mips-dis.c: Don't use true and false. - -Thu Jun 23 12:53:19 1994 David J. Mackenzie (djm@rtl.cygnus.com) - - * configure.in: Change --with-targets to --enable-targets. - -Wed Jun 22 13:38:32 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) - - * mips-dis.c (_print_insn_mips): Build a static hash table mapping - opcodes to the first instruction with that opcode, to speed - disassembly of large files. From ralphc@pyramid.com (Ralph - Campbell). - -Tue Jun 7 12:49:44 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * Makefile.in (mostlyclean): Fix typo (was mostyclean). - -Wed May 11 22:32:00 1994 DJ Delorie (dj@ctron.com) - - * configure.bat: update to latest makefile.in - -Sat May 7 17:13:21 1994 Steve Chamberlain (sac@cygnus.com) - - * a29k-dis.c (print_insn): Print 'x' type operand in hex. - * h8300-dis.c (bfd_h8_disassemble): Print 16bit rels correctly. - * sh-dis.c (print_insn_sh): Don't recur endlessly if delay - slot insn is in a delay slot. - * z8k-opc.h: (resflg): Fix patterns. - * h8500-opc.h Fix CR insn patterns. - -Fri May 6 14:34:46 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc-opc.c (powerpc_opcodes): Put PowerPC versions of "cmp" and - "cmpl" before POWER versions, so that gas -many uses them. - -Thu Apr 28 18:32:36 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * disassemble.c: New file. - * Makefile.in (OFILES): Add disassemble.o. - (disassemble.o): Provide dependencies; compile with $(ARCHDEFS). - * configure.in: Define ARCHDEFS in Makefile. Code taken from - binutils/configure.in. - - * m68k-dis.c (print_insn_m68k): If F_ALIAS flag is set, skip the - opcode being examined. - -Thu Apr 21 17:08:40 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc-opc.c (powerpc_operands): Added RAL, RAM and RAS. - (insert_ral, insert_ram, insert_ras): New functions. - (powerpc_opcodes): Use RAL for load with update, RAM for lmw, and - RAS for store with update. - -Sat Apr 16 23:41:44 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc-opc.c (powerpc_opcodes): Correct fcir. From David Edelsohn - (edelsohn@npac.syr.edu). - -Wed Apr 6 17:11:45 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c (mips_opcodes): Correct operands of "nor" with an - immediate argument. - -Mon Apr 4 16:30:46 1994 Doug Evans (dje@canuck.cygnus.com) - - * sparc-opc.c (sparc_opcodes): Fix "rd %fprs,%l0". - -Mon Apr 4 13:22:00 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc-opc.c (powerpc_operands): The signedp field has been - removed, so don't initialize it. Set the PPC_OPERAND_SIGNED flag - instead. Add new operand SISIGNOPT. - (powerpc_opcodes): For lis, liu, addis, and cau use SISIGNOPT. - Based on patch from David Edelsohn (edelsohn@npac.syr.edu). - * ppc-dis.c (print_insn_powerpc): Check PPC_OPERAND_SIGNED rather - than signedp field. - -Wed Mar 30 00:31:49 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * i386-dis.c (struct private): Renamed to dis_private. `private' - is a reserved word for dynix cc. - -Mon Mar 28 13:00:15 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * configure.in: Change error message to refer to bfd/config.bfd - rather than bfd/configure.in. - -Mon Mar 28 12:28:30 1994 David Edelsohn (edelsohn@npac.syr.edu) - - * ppc-opc.c: Define POWER2 as short alias flag. - (powerpc_opcodes): Add POWER/2 opcodes lfq*, stfq*, fcir[z], and - fsqrt. - -Wed Mar 23 12:23:05 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * i960-dis.c (print_insn_i960): Don't read a second word for - opcodes 0, 1, 2 and 3. - -Wed Mar 16 15:37:58 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * configure.in: Don't build m68881-ext.o for bfd_m68k_arch. - -Mon Mar 14 14:53:50 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * m68881-ext.c: Removed; no longer used. - * Makefile.in: Changed accordingly. - - * m68k-dis.c (ext_format_68881): Don't declare. - (print_insn_m68k): If an instruction uses place 'i', it uses at - least four fixed bytes. - (print_insn_arg): Don't bump p by 2 for case 'I', place 'i'. For - extended float, convert to double using floatformat_to_double, not - ieee_extended_to_double, and fetch the data before converting it. - -Tue Mar 8 18:12:25 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: It's sqrt.s, not sqrt.w. From - davidj@ICSI.Berkeley.EDU (David Johnson). - -Tue Feb 8 16:55:27 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc-opc.c (powerpc_opcodes): The POWER uses bdn[l][a] where the - PowerPC uses bdnz[l][a]. - -Tue Feb 8 00:32:28 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * dis-buf.c, i386-dis.c: Include sysdep.h. - -Mon Feb 7 19:22:23 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * configure.in (bfd_powerpc_arch): Use ppc-dis.o and ppc-opc.o. - - * ppc-opc.c (powerpc_opcodes): Mark POWER instructions supported - by Motorola PowerPC 601 with PPC_OPCODE_601. - * ppc-dis.c (print_insn_big_powerpc, print_insn_little_powerpc): - Disassemble Motorola PowerPC 601 instructions as well as normal - PowerPC instructions. - -Sun Feb 6 07:45:17 1994 Jim Kingdon (kingdon@lioth.cygnus.com) - - * i960-dis.c (reg, mem): Just use a static array instead of - calling xmalloc. - -Sat Feb 5 00:04:02 1994 Jeffrey A. Law (law@snake.cs.utah.edu) - - * hppa-dis.c (print_insn_hppa): For '?' and '@' only adjust the - condition name index if this is for a negated condition. - - * hppa-dis.c (print_insn_hppa): No space before 'H' operand. - Floating point format for 'H' operand is backwards from normal - case (0 == double, 1 == single). For '4', '6', '7', '9', and '8' - operands (fmpyadd and fmpysub), handle bizarre register - translation correctly for single precision format. - - * hppa-dis.c (print_insn_hppa): Do not emit a space after 'F' - or 'I' operands if the next format specifier is 'M' (fcmp - condition completer). - -Feb 4 23:38:03 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc-opc.c (powerpc_operands): New operand type MBE to handle a - single number giving a bitmask for the MB and ME fields of an M - form instruction. Change NB to accept 32, and turn it into 0; - also turn 0 into 32 when disassembling. Seperated SH from NB. - (insert_mbe, extract_mbe): New functions. - (insert_nb, extract_nb): New functions. - (SC_MASK): Mask out SA and LK bits. - (powerpc_opcodes): Change "cal" to use RT, D, RA rather than RT, - RA, SI. Change "liu" and "cau" to use UI rather than SI. Mark - "bctr" and "bctrl" as accepted by POWER. Change "rlwimi", - "rlimi", "rlwimi.", "rlimi.", "rlwinm", "rlinm", "rlwinm.", - "rlinm.", "rlmi", "rlmi.", "rlwnm", "rlnm", "rlwnm.", "rlnm." to - use MBE rather than MB. Add "mfmq" and "mtmq" POWER instructions. - (powerpc_macros): Define table of macro definitions. - (powerpc_num_macros): Define. - - * ppc-dis.c (print_insn_powerpc): Don't skip optional operands - if PPC_OPERAND_NEXT is set. - -Sat Jan 22 23:10:07 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * i960-dis.c (print_insn_i960): Make buffer bfd_byte instead of - char. Retrieve contents using bfd_getl32 instead of shifting. - -Fri Jan 21 19:01:39 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc-opc.c: New file. Opcode table for PowerPC, including - opcodes for POWER (RS/6000). - * ppc-dis.c: New file. PowerPC and Power (RS/6000) disassembler. - * Makefile.in (ALL_MACHINES): Add ppc-dis.o and ppc-opc.o. - (CFILES): Add ppc-dis.c. - (ppc-dis.o, ppc-opc.o): New targets. - * configure.in: Build ppc-dis.o and ppc-opc.o for bfd_rs6000_arch. - -Mon Jan 17 20:05:49 1994 Jeffrey A. Law (law@snake.cs.utah.edu) - - * hppa-dis.c (print_insn_hppa): Handle 'N' in assembler template. - No space before 'u', 'f', or 'N'. - -Sun Jan 16 14:20:16 1994 Jim Kingdon (kingdon@deneb.cygnus.com) - - * i386-dis.c (print_insn_i386): Add FIXME comment regarding reading - farther than we should. - - * i386-dis.c (dis386): Use Yb and Yv for scasb and scasS. - -Thu Jan 6 12:38:05 1994 David J. Mackenzie (djm@thepub.cygnus.com) - - * sparc-dis.c m68k-dis.c alpha-dis.c a29k-dis.c: Fix comments. - -Wed Jan 5 11:56:21 1994 David J. Mackenzie (djm@thepub.cygnus.com) - - * i960-dis.c (print_insn_i960): Only read word2 if the instruction - needs it, to prevent reading past the end of a section. - -Wed Nov 17 17:20:12 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.h: Use macro for j instruction, to support SVR4 PIC. - Removed t,A case for la; always use t,A(b) case. - -Mon Nov 8 12:37:36 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - From Ted Lemen <mellon@pepper.ncd.com> - * mips-dis.c (print_insn_arg): Handle 'k'. - * mips-opc.c: Make cache use k, not t. - -Sun Nov 7 23:52:34 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * alpha-opc.h, alpha-dis.c (print_insn_alpha): Add - FLOAT_MEMORY_FORMAT_CODE, FLOAT_BRANCH_FORMAT_CODE, correct - FLOAT_FORMAT_CODE to put out floating point register names. - -Mon Nov 1 18:17:51 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Use macros for jal variants, to support SVR4 PIC. - -Thu Oct 28 17:42:23 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * a29k-dis.c (print_insn): Use 0x%08x, not 0x%8x. - -Wed Oct 27 11:48:01 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c (dsll, dsra, dsrl): Added '>' cases for shift counts - larger than 32. Moved dsxx32 variants first for disassembler. - -Mon Oct 25 11:33:14 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - * z8kgen.c, z8k-opc.h: Add full lda information. - -Tue Oct 19 12:39:25 1993 Jeffrey A Law (law@cs.utah.edu) - - * hppa-dis.c (print_insn_hppa): Do not emit a space after - movb instructions. Any necessary space will be emitted by - the code to handle nullification completers. - -Wed Oct 13 16:19:07 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Moved l.d down so that it disassembles as ldc1. - -Fri Oct 8 02:34:21 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * alpha-opc.h: Add ldl_l, fix typo for ldq_u. - * alpha-dis.c (print_insn_alpha): Add code for PAL_FORMAT_CODE. - -Tue Oct 5 17:47:53 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Correct lwu opcode value (book had it wrong). - -Thu Sep 30 11:26:18 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - * z8k-dis.c (FETCH_DATA): get just the right amount of data. - (unpack_instr): Cope with ARG_IMM4M1 type instructions. - -Wed Sep 29 16:24:49 1993 K. Richard Pixley (rich@sendai.cygnus.com) - - * m88k-dis.c (m88kdis): comment change. Remove space after - printing mnemonic. - (printop): handle new arg types DEC and XREG for m88110. - -Tue Sep 28 19:20:16 1993 Jeffrey A Law (law@snake.cs.utah.edu) - - * hppa-dis.c (print_insn_hppa): Handle 'z' operand - type for absolute branch addresses. Delete special - "ble" and "be" code in 'W' operand code. - -Fri Sep 24 14:08:33 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Set hazard information correctly for branch - likely instructions. - -Fri Sep 17 04:41:17 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * alpha-dis.c (print_insn_alpha), alpha-opc.h: Fix bugs, use - info->fprintf_func for printing and info->print_address_func for - address output. - -Wed Sep 15 12:12:07 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Set INSN_TRAP for tXX instructions. - -Thu Sep 9 10:11:27 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): - Corrected second case of "b" for disassembler. - -Tue Sep 7 14:25:15 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-dis.c, m88k-dis.c: Don't include libbfd.h. Changed calls - to BFD swapping routines to correspond to BFD name changes. - -Thu Sep 2 10:35:25 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Change div machine instruction to be z,s,t rather - than s,t. Change div macro to be d,v,t rather than d,s,t. - Likewise for divu, ddiv, ddivu. Added z,s,t case for drem, dremu, - rem and remu which generates only the corresponding div - instruction. This is for compatibility with the MIPS assembler, - which only generates the simple machine instruction when an - explicit destination of $0 is used. - * mips-dis.c (print_insn_arg): Handle 'z' (always register zero). - -Thu Aug 26 17:41:44 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): Set - WR_31 hazard for bal, bgezal, bltzal. - -Thu Aug 26 17:20:02 1993 Jim Kingdon (kingdon@lioth.cygnus.com) - - * hppa-dis.c (print_insn_hppa): Use print function - from within the disassemble_info, not fprintf_filtered. - -Wed Aug 25 13:51:40 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * hppa-dis.c (print_insn_hppa): Handle '|' like '>'. (From Jeff - Law, law@cs.utah.edu.) - -Mon Aug 23 12:44:05 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c ("absu"): Removed. - ("dabs"): Added. - -Fri Aug 20 10:52:52 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Added r6000 and r4000 instructions and macros. - Changed hazard information to distinguish between memory load - delays and coprocessor load delays. - -Wed Aug 18 15:39:23 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: li.d uses "T,L", not "S,F". Added li.s. - -Tue Aug 17 09:44:42 1993 David J. Mackenzie (djm@thepub.cygnus.com) - - * configure.in: Don't pass cpu to config.bfd. - -Tue Aug 17 12:23:52 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * m88k-dis.c (m88kdis): Make class unsigned. - -Thu Aug 12 15:08:18 1993 Ian Lance Taylor (ian@cygnus.com) - - * alpha-dis.c (print_insn_alpha): One branch format case was - missing the instruction name. - -Wed Aug 11 19:29:39 1993 David J. Mackenzie (djm@thepub.cygnus.com) - - * Makefile.in (ALL_MACHINES): Renamed from DIS_LIBS. - Add the arch-specific auxiliary files. - (OFILES): Remove the arch-specific auxiliary files - and use BFD_MACHINES instead of DIS_LIBS. - * configure.in: Set BFD_MACHINES based on --with-targets option. - -Thu Aug 12 12:04:53 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Added lwc1 E,A(b) to go with lwc1 T,A(b). Similarly - for swc1. - -Sun Aug 8 15:09:30 1993 Jim Kingdon (kingdon@lioth.cygnus.com) - - * sparc-opc.c: Change CONST to const to deal with gcc - -Dconst=__const -traditional. - -Fri Aug 6 10:58:55 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): Took - coprocessor instructions out of #if 0, and made them use new - argument type "C". - -Thu Aug 5 17:11:06 1993 Jim Kingdon (kingdon@lioth.cygnus.com) - - * sparc-dis.c: Include ansidecl.h before opcodes/sparc.h. - -Fri Jul 30 18:48:15 1993 John Gilmore (gnu@cygnus.com) - - * sparc-opc.c: Add F_JSR, F_UNBR, or F_CONDBR flags to each branch - instruction, for use by the disassembler. - - * sparc-dis.c (SEX): Add sign extension macro. Replace many - hand-coded sign extensions that depended on 32-bit host ints. - FIXME, we still depend on big-endian host bitfield ordering. - (sparc_print_insn): Set the insn_info_valid field, and the - other fields that describe the instruction being printed. - -Tue Jul 27 17:04:58 1993 Jim Wilson (wilson@sphagnum.cygnus.com) - - * sparc-opc.c (call): Accept all 6 addressing modes valid for - `jmp' instead of just one of them. - -Wed Jul 21 11:43:32 1993 Jim Kingdon (kingdon@deneb.cygnus.com) - - * hppa-dis.c: Move floating registers from reg_names to fp_reg_names. - (fput_fp_reg_r): Renamed from fput_reg_r. - (fput_fp_reg): New function. - (print_insn_hppa): Use fput_fp_reg{,_r} where appropriate. - - * hppa-dis.c (print_insn_hppa, cases 'a', 'd'): Print space afterwards. - - * hppa-dis.c (print_insn_hppa, case 'd'): Use GET_COND not GET_FIELD. - -Mon Jul 19 13:52:21 1993 Jim Kingdon (kingdon@deneb.cygnus.com) - - * hppa-dis.c (print_insn_hppa): Use extract_5r_store for 'r'. - - * hppa-dis.c (print_insn_hppa, case '>'): If next character is 'n', - don't output a space. - - * hppa-dis.c (float_format_names): 10 is undefined, and 11 is quad. - -Sun Jul 18 16:30:02 1993 Jim Kingdon (kingdon@rtl.cygnus.com) - - * mips-opc.c: New file, containing opcode table from - ../include/opcode/mips.h. - * Makefile.in: Add it. - -Thu Jul 15 12:37:05 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * m88k-dis.c: New file, moved in from gdb and changed to use the - new dis-asm.h disassembler interface. - * Makefile.in (DIS_LIBS): Added m88k-dis.o. - (m88k-dis.o): New target. - -Tue Jul 13 10:04:16 1993 Ian Lance Taylor (ian@cygnus.com) - - * mips-dis.c (print_insn_arg, _print_insn_mips): Made pointer to - argument string const char * to correspond to opcode/mips.h. - -Tue Jul 6 15:18:37 1993 Ian Lance Taylor (ian@cygnus.com) - - * mips-dis.c: Updated to account for name changes in new version - of opcode/mips.h. - * Makefile.in: Added header file dependencies. - -Sat Jul 3 23:47:56 1993 Doug Evans (dje@canuck.cygnus.com) - - * h8300-dis.c (bfd_h8_disassemble): Correct fetching of instruction. - -Thu Jul 1 12:23:38 1993 Jim Kingdon (kingdon@lioth.cygnus.com) - - * m68k-dis.c (NEXTWORD, NEXTLONG): Use ((x) ^ 0x8000) - 0x8000 to sign - extend, rather than shifts. - -Sun Jun 20 20:56:56 1993 Ken Raeburn (raeburn@poseidon.cygnus.com) - - * Makefile.in: Undo 15 June change. - -Fri Jun 18 14:15:15 1993 Per Bothner (bothner@deneb.cygnus.com) - - * m68k-dis.c (print_insn_arg): Change return value to byte count - or error code. - * m68k-dis.c: Re-write to detect invalid operands before - printing anything, so we can handle this the same way we - handle invalid opcodes. - -Thu Jun 17 15:01:36 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - * sh-dis.c, sh-opc.h: Understand some more opcodes. - -Wed Jun 16 13:48:05 1993 Ian Lance Taylor (ian@cygnus.com) - - * hppa-dis.c: Include <ansidecl.h> and sysdep.h before other - header files. - -Tue Jun 15 21:45:26 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * sparc-dis.c: Don't declare qsort, since sysdep.h might. - - * configure.in: Do make sysdep.h link. - * Makefile.in: Search ../include. Don't search ../bfd. - -Tue Jun 15 13:36:10 1993 Stu Grossman (grossman@cygnus.com) - - Changes from Jeff Law, law@cs.utah.edu: - * hppa-dis.c: Fix typo. 'a' and 'd' were reversed. - Do not print a space before the completers specified by - 'a' and 'd'. - -Fri Jun 11 18:40:21 1993 Ken Raeburn (raeburn@cygnus.com) - - * mips-dis.c: No longer need to bomb out if HOST_64_BIT is - defined, since gdb has been fixed. - - Changes from Jeff Law, law@cs.utah.edu: - * hppa-dis.c (print_insn_hppa): Last argument to fput_reg, - fput_reg_r, fput_creg, fput_const, and fputs_filtered should - be a *disassemble_info, not a *FILE. - * hppa-dis.c: Support 'd', '!', and 'a'. - * hppa-dis.c: Support 's' to extract a 2 bit space register. - * hppa-dis.c: Delete cases which are no longer needed. - -Fri Jun 11 07:53:48 1993 Jim Kingdon (kingdon@cygnus.com) - - * m68k-dis.c (print_insn_{m68k,arg}): Add MMU codes. - -Tue Jun 8 12:25:01 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - * h8300-dis.c: New file, removed from bfd/cpu-h8300.c, with - H8/300-H opcodes. - -Mon Jun 7 12:58:49 1993 Per Bothner (bothner@rtl.cygnus.com) - - * Makefile.in (CSEARCH): Add -I../bfd for sysdep.h and bfd.h. - * configure.in: No longer need to configure to get sysdep.h. - -Thu Jun 3 15:56:49 1993 Stu Grossman (grossman@cygnus.com) - - * Patches from Jeffrey Law <law@cs.utah.edu>. - * hppa-dis.c: Support 'I', 'J', and 'K' in output - templates for 1.1 FP computational instructions. - -Tue May 25 13:05:48 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * h8500-dis.c (print_insn_h8500): Address argument is type - bfd_vma. - * z8k-dis.c (print_insn_z8k, print_insn_z8001, print_insn_z8002): - Ditto. - - * h8500-opc.h (addr_class_type): No comma at end of enumerator. - * sh-opc.h (sh_nibble_type, sh_arg_type): Ditto. - - * sparc-dis.c (compare_opcodes): Move static declaration to - top-level. - -Fri May 21 14:17:37 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * sparc-dis.c (print_insn_sparc): Implement 'n' argument for unimp - instruction, remove unimp hack from 'l' argument. - -Wed May 19 15:35:54 1993 Stu Grossman (grossman@cygnus.com) - - * z8k-dis.c (fetch_data): Use unsigned char to make ancient gcc's - happy. - -Fri May 14 15:22:46 1993 Ian Lance Taylor (ian@cygnus.com) - - * Based on patches from davidj@ICSI.Berkeley.EDU (David Johnson): - * mips-dis.c (print_insn_arg): Handle 'C' for general coprocessor - instructions. - -Fri May 14 00:09:14 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * hppa-dis.c: Include dis-asm.h before sysdep.h. Changed some - arrays of string pointers to 2-d arrays of chars, to save - space. - -Thu May 6 20:51:17 1993 Fred Fish (fnf@cygnus.com) - - * a29k-dis.c, alpha-dis.c, i960-dis.c, sparc-dis.c, z8k-dis.c: - Cast second arg to read_memory_func to "bfd_byte *", as necessary. - -Tue May 4 20:31:10 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * hppa-dis.c: New file from Utah, adapted to new disassembler - calling interface. - * Makefile.in: Include it. - -Mon Apr 26 18:17:42 1993 Steve Chamberlain (sac@thepub.cygnus.com) - - * sh-dis.c, sh-opc.h: New files. - -Fri Apr 23 18:51:22 1993 Steve Chamberlain (sac@thepub.cygnus.com) - - * alpha-dis.c, alpha-opc.h: New files. - -Tue Apr 6 12:54:08 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * mips-dis.c: Sign extend 'j' and 'b' arguments, delta is a signed - value. - -Mon Apr 5 17:37:37 1993 John Gilmore (gnu@cygnus.com) - - * sparc-dis.c: Make "ta" the default trap instruction, "t" the alias. - -Fri Apr 2 07:24:27 1993 Ian Lance Taylor (ian@cygnus.com) - - * a29k-dis.c, sparc-dis.c, sparc-opc.c: Use CONST rather than - const. - -Thu Apr 1 11:20:43 1993 Jim Kingdon (kingdon@cygnus.com) - - * sparc-dis.c: Use fprintf_func a few places where I forgot, - and double percent signs a few places. - - * a29k-dis.c, i960-dis.c: New, merged from gdb and binutils. - - * i386-dis.c, m68k-dis.c, mips-dis.c, sparc-dis.c: - Use info->print_address_func not print_address. - - * dis-buf.c (generic_print_address): New function. - -Wed Mar 31 10:07:04 1993 Jim Kingdon (kingdon@lioth.cygnus.com) - - * Makefile.in: Add sparc-dis.c. - sparc-dis.c: New file, merges binutils and gdb versions as follows: - From GDB: - Add `add' instruction to the set that get checked - for a preceding `sethi' in order to print an absolute address. - * (print_insn): Disassembly prefers real instructions. - (is_delayed_branch): Speed up. - * sparc-opcode.h: Add ALIAS bit to aliases. Fix up opcode tables. - Still missing some float ops, and needs testing. - * sparc-pinsn.c (print_insn): Eliminate 'set' test, subsumed by - F_ALIAS. Use printf, not fprintf, when not passing a file - pointer... - (compare_opcodes): Check that identical instructions have - identical opcodes, complain otherwise. - From binutils: - * New 'm' arg. - * Include reg_names. - From neither: - Use dis-asm.h/read_memory_func interface. - -Wed Mar 31 20:49:06 1993 K. Richard Pixley (rich@rtl.cygnus.com) - - * h8500-dis.c, i386-dis.c, m68k-dis.c, z8k-dis.c (fetch_data): - deliberately return non-zero to setjmp from longjmp. Otherwise - this code fails to compile. - -Wed Mar 31 17:04:31 1993 Stu Grossman (grossman@cygnus.com) - - * m68k-dis.c: Fix prototype for fetch_arg(). - -Wed Mar 31 10:07:04 1993 Jim Kingdon (kingdon@lioth.cygnus.com) - - * dis-buf.c: New file, for new read_memory_func interface. - Makefile.in (OFILES): Include it. - m68k-dis.c, i386-dis.c, h8500-dis.c, mips-dis.c, z8k-dis.c: - Use new read_memory_func interface. - -Mon Mar 29 14:02:17 1993 Steve Chamberlain (sac@thepub.cygnus.com) - - * h8500-dis.c (print_insn_h8500): Get sign of fp offsets right. - * h8500-opc.h: Fix couple of opcodes. - -Wed Mar 24 02:03:36 1993 david d `zoo' zuhn (zoo at poseidon.cygnus.com) - - * Makefile.in: add dvi & installcheck targets - -Mon Mar 22 18:55:04 1993 John Gilmore (gnu@cygnus.com) - - * Makefile.in: Update for h8500-dis.c. - -Fri Mar 19 14:27:17 1993 Steve Chamberlain (sac@thepub.cygnus.com) - - * h8500-dis.c, h8500-opc.h: New files - -Thu Mar 18 14:12:37 1993 Per Bothner (bothner@rtl.cygnus.com) - - * mips-dis.c, z8k-dis.c: Converted to use interface defined in - ../include/dis-asm.h. - * m68k-dis.c: New file (merge of ../binutils/m68k-pinsn.c - and ../gdb/m68k-pinsn.c). - * i386-dis.c: New file (merge of ../binutils/i386-pinsn.c - and ../gdb/i386-pinsn.c). - * m68881-ext.c: New file. Moved definition of - ext_format ext_format_68881 from ../gdb/m68k-tdep.c. - * Makefile.in: Adjust for new files. - * i386-dis.c: Patches from John Hassey (hassey@dg-rtp.dg.com). - * m68k-dis.c: Recognize '9' placement code, so (say) pflush - can be dis-assembled. - -Wed Feb 17 09:19:47 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * mips-dis.c (print_insn_arg): Now returns void. - -Mon Jan 11 16:09:16 1993 Fred Fish (fnf@cygnus.com) - - * mips-dis.c (ansidecl.h): Include for benefit of sysdep.h - files that use the macros. - -Thu Jan 7 13:15:17 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-dis.c: New file, from gdb/mips-pinsn.c. - * Makefile.in (DIS_LIBS): Added mips-dis.o. - (CFILES): Added mips-dis.c. - -Thu Jan 7 07:36:33 1993 Steve Chamberlain (sac@thepub.cygnus.com) - - * z8k-dis.c (print_insn_z8001, print_insn_z8002): new routines - * z8kgen.c, z8k-opc.h: fix sizes of some shifts. - -Tue Dec 22 15:42:44 1992 Per Bothner (bothner@rtl.cygnus.com) - - * Makefile.in: Improve *clean rules. - * configure.in: Allow a default host. - -Tue Nov 17 19:53:54 1992 david d `zoo' zuhn (zoo at cirdan.cygnus.com) - - * Makefile.in: also use -I$(srcdir)/../bfd, since some sysdep - files include other sysdep files - -Thu Nov 12 16:10:37 1992 Steve Chamberlain (sac@thepub.cygnus.com) - - * z8k-dis.c z8k-opc.h z8kgen.c: checkpoint - -Fri Oct 9 04:56:05 1992 John Gilmore (gnu@cygnus.com) - - * configure.in: For host support, use ../bfd/configure.host - so it stays in sync with the ../bfd/hosts database. - -Thu Oct 1 23:38:54 1992 david d `zoo' zuhn (zoo at cirdan.cygnus.com) - - * configure.in: use cpu-vendor-os triple instead of nested cases - -Wed Sep 30 16:09:20 1992 Michael Werner (mtw@cygnus.com) - - * z8k-dis.c (unparse_instr): fix bug where opcode returned was - *always* the wrong one. - -Wed Sep 30 07:42:17 1992 Steve Chamberlain (sac@thepub.cygnus.com) - - * z8kgen.c: added copyright info - -Tue Sep 29 12:20:21 1992 Steve Chamberlain (sac@thepub.cygnus.com) - - * z8k-dis.c (unparse_instr): prettier tabs - * z8kgen.c -> z8k-opc.h: bug fixes in tables - -Fri Sep 25 12:50:32 1992 Stu Grossman (grossman at cygnus.com) - - * configure.in: Add ncr* configuration. - * z8k-dis.c (struct instr_data_s): Make instr_asmsrc char to make - picayune ANSI compilers happy. - -Sep 20 08:50:55 1992 Fred Fish (fnf@cygnus.com) - - * configure.in (i386): Make i386 and i486 synonymous for now. - * configure.in (i[34]86-*-sysv4): Add my_host definition. - -Fri Sep 18 17:01:23 1992 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * Makefile.in (install): Fix typo. - -Fri Sep 18 02:04:24 1992 John Gilmore (gnu@cygnus.com) - - * Makefile.in (make): Remove obsolete crud. - (sparc-opc.o): Avoid Sun Make VPATH bug. - -Tue Sep 8 17:29:27 1992 K. Richard Pixley (rich@sendai.cygnus.com) - - * Makefile.in: since there are no SUBDIRS, remove rule and - references of subdir_do. - -Tue Sep 8 17:02:58 1992 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * Makefile.in (install): Get the library name right here too. - Don't install bfd.h, since it's unrelated to this library. No - subdirs to recurse into, either. - (CFILES): The source file has a .c suffix, not .o. - - * sparc-opc.c: New file, moved from BFD. - * Makefile.in (OFILES): Build it. - -Thu Sep 3 16:59:20 1992 Michael Werner (mtw@cygnus.com) - - * z8k-dis.c: fixed forward refferences of some declarations. - -Mon Aug 31 16:09:45 1992 Michael Werner (mtw@cygnus.com) - - * Makefile.in: get the name of the library right - -Mon Aug 31 13:47:35 1992 Steve Chamberlain (sac@thepub.cygnus.com) - - * z8k-dis.c: knows how to disassemble z8k stuff - * z8k-opc.h: new file full of z8000 opcodes - - -Local Variables: -version-control: never -End: diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am deleted file mode 100644 index 8732b1ce0b1..00000000000 --- a/opcodes/Makefile.am +++ /dev/null @@ -1,409 +0,0 @@ -## Process this file with automake to generate Makefile.in - -AUTOMAKE_OPTIONS = cygnus - -SUBDIRS = po - -INCDIR = $(srcdir)/../include -BFDDIR = $(srcdir)/../bfd -DEP = mkdep - -lib_LTLIBRARIES = libopcodes.la - -# This is where bfd.h lives. -BFD_H = ../bfd/bfd.h - -# Header files. -HFILES = \ - arm-opc.h \ - fr30-desc.h fr30-opc.h \ - h8500-opc.h \ - m32r-desc.h m32r-opc.h \ - sh-opc.h \ - sysdep.h \ - w65-opc.h \ - z8k-opc.h - -# C source files that correspond to .o's. -CFILES = \ - a29k-dis.c \ - alpha-dis.c \ - alpha-opc.c \ - arm-dis.c \ - cgen-asm.c \ - cgen-dis.c \ - cgen-opc.c \ - d10v-dis.c \ - d10v-opc.c \ - d30v-dis.c \ - d30v-opc.c \ - dis-buf.c \ - disassemble.c \ - fr30-asm.c \ - fr30-desc.c \ - fr30-dis.c \ - fr30-ibld.c \ - fr30-opc.c \ - h8300-dis.c \ - h8500-dis.c \ - hppa-dis.c \ - i386-dis.c \ - i960-dis.c \ - m32r-asm.c \ - m32r-desc.c \ - m32r-dis.c \ - m32r-ibld.c \ - m32r-opc.c \ - m32r-opinst.c \ - m68k-dis.c \ - m68k-opc.c \ - m88k-dis.c \ - mips-dis.c \ - mips-opc.c \ - mips16-opc.c \ - m10200-dis.c \ - m10200-opc.c \ - m10300-dis.c \ - m10300-opc.c \ - ns32k-dis.c \ - ppc-dis.c \ - ppc-opc.c \ - sh-dis.c \ - sparc-dis.c \ - sparc-opc.c \ - tic30-dis.c \ - vax-dis.c \ - w65-dis.c \ - z8k-dis.c \ - z8kgen.c - -ALL_MACHINES = \ - a29k-dis.lo \ - alpha-dis.lo \ - alpha-opc.lo \ - arc-dis.lo \ - arc-opc.lo \ - arm-dis.lo \ - cgen-asm.lo \ - cgen-dis.lo \ - cgen-opc.lo \ - d10v-dis.lo \ - d10v-opc.lo \ - d30v-dis.lo \ - d30v-opc.lo \ - fr30-asm.lo \ - fr30-desc.lo \ - fr30-dis.lo \ - fr30-ibld.lo \ - fr30-opc.lo \ - h8300-dis.lo \ - h8500-dis.lo \ - hppa-dis.lo \ - i386-dis.lo \ - i960-dis.lo \ - m32r-asm.lo \ - m32r-desc.lo \ - m32r-dis.lo \ - m32r-ibld.lo \ - m32r-opc.lo \ - m32r-opinst.lo \ - m68k-dis.lo \ - m68k-opc.lo \ - m88k-dis.lo \ - m10200-dis.lo \ - m10200-opc.lo \ - m10300-dis.lo \ - m10300-opc.lo \ - mips-dis.lo \ - mips-opc.lo \ - mips16-opc.lo \ - ppc-dis.lo \ - ppc-opc.lo \ - ns32k-dis.lo \ - sh-dis.lo \ - sparc-dis.lo \ - sparc-opc.lo \ - tic30-dis.lo \ - $(start-sanitize-tic80) \ - tic80-dis.lo \ - tic80-opc.lo \ - $(end-sanitize-tic80) \ - $(start-sanitize-sky) \ - dvp-dis.lo \ - dvp-opc.lo \ - $(end-sanitize-sky) \ - v850-dis.lo \ - v850-opc.lo \ - vax-dis.lo \ - w65-dis.lo \ - z8k-dis.lo - -OFILES = @BFD_MACHINES@ - -INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(INCDIR) -I$(BFDDIR) @HDEFINES@ -I$(srcdir)/../intl -I../intl - -disassemble.lo: disassemble.c $(INCDIR)/dis-asm.h - $(LIBTOOL) --mode=compile $(COMPILE) -c @archdefs@ $(srcdir)/disassemble.c - -libopcodes_la_SOURCES = dis-buf.c disassemble.c -libopcodes_la_DEPENDENCIES = $(OFILES) -libopcodes_la_LIBADD = $(OFILES) @WIN32LIBADD@ -libopcodes_la_LDFLAGS = -release $(VERSION) @WIN32LDFLAGS@ - -# libtool will build .libs/libopcodes.a. We create libopcodes.a in -# the build directory so that we don't have to convert all the -# programs that use libopcodes.a simultaneously. This is a hack which -# should be removed if everything else starts using libtool. FIXME. - -noinst_LIBRARIES = libopcodes.a - -stamp-lib: libopcodes.la - if [ -f .libs/libopcodes.a ]; then \ - cp .libs/libopcodes.a libopcodes.tmp; \ - $(SHELL) $(srcdir)/../move-if-change libopcodes.tmp libopcodes.a; \ - else true; fi - touch stamp-lib - -libopcodes.a: stamp-lib ; @true - -POTFILES = $(HFILES) $(CFILES) -po/POTFILES.in: @MAINT@ Makefile - for file in $(POTFILES); do echo $$file; done | sort > tmp \ - && mv tmp $(srcdir)/po/POTFILES.in - -# We should reconfigure whenever bfd/configure.in changes, because -# that's where the version number comes from. -config.status: $(srcdir)/configure $(srcdir)/../bfd/configure.in - $(SHELL) ./config.status --recheck - -CLEANFILES = libopcodes.a stamp-lib dep.sed .dep .dep1 -# start-sanitize-cygnus -CLEANFILES = libopcodes.a stamp-lib dep.sed .dep .dep1 \ - stamp-m32r stamp-fr30 -# end-sanitize-cygnus - -# start-sanitize-cygnus-never -# CGEN support is sanitized out of FSF releases for now. -# Sanitization must be split between assignments and rules because -# automake splits them that way. -# end-sanitize-cygnus-never - -# start-sanitize-cygnus -CGENDIR = @cgendir@ -CGEN = @cgen@ -CGENFLAGS = -v - -CGENFILES = $(CGENDIR)/cos.scm $(CGENDIR)/utils.scm \ - $(CGENDIR)/attr.scm $(CGENDIR)/enum.scm $(CGENDIR)/types.scm \ - $(CGENDIR)/utils-cgen.scm $(CGENDIR)/read.scm \ - $(CGENDIR)/mode.scm $(CGENDIR)/mach.scm \ - $(CGENDIR)/model.scm $(CGENDIR)/hardware.scm \ - $(CGENDIR)/ifield.scm $(CGENDIR)/iformat.scm \ - $(CGENDIR)/operand.scm $(CGENDIR)/insn.scm $(CGENDIR)/minsn.scm \ - $(CGENDIR)/rtl.scm $(CGENDIR)/rtx-funcs.scm \ - $(CGENDIR)/desc.scm $(CGENDIR)/desc-cpu.scm \ - $(CGENDIR)/opc-asmdis.scm $(CGENDIR)/opc-ibld.scm \ - $(CGENDIR)/opc-itab.scm $(CGENDIR)/opc-opinst.scm \ - $(CGENDIR)/opcodes.scm $(CGENDIR)/cgen-opc.scm \ - cgen-asm.in cgen-dis.in cgen-ibld.in -# The CGEN_MAINT conditional is put here so it ends up in Makefile.in -# properly sanitised. -if CGEN_MAINT -M32R_DEPS = stamp-m32r -FR30_DEPS = stamp-fr30 -else -M32R_DEPS = -FR30_DEPS = -endif -# The end marker is written this way to pass through automake unscathed. -ENDSAN = end-sanitize-cygnus - -# start-sanitize-cygnus -run-cgen: - $(SHELL) $(srcdir)/cgen.sh opcodes $(srcdir) $(CGEN) $(CGENDIR) $(CGENFLAGS) $(arch) $(prefix) $(options) $(extrafiles) - touch stamp-${prefix} -.PHONY: run-cgen - -# For now, require developers to configure with --enable-cgen-maint. -m32r-desc.h m32r-desc.c m32r-opc.h m32r-opc.c m32r-ibld.c m32r-opinst.c m32r-asm.c m32r-dis.c: $(M32R_DEPS) - @true -stamp-m32r: $(CGENFILES) $(CGENDIR)/m32r.cpu $(CGENDIR)/m32r.opc - $(MAKE) run-cgen arch=m32r prefix=m32r options=opinst extrafiles=opinst - -fr30-desc.h fr30-desc.c fr30-opc.h fr30-opc.c fr30-ibld.c fr30-asm.c fr30-dis.c: $(FR30_DEPS) - @true -stamp-fr30: $(CGENFILES) $(CGENDIR)/fr30.cpu $(CGENDIR)/fr30.opc - $(MAKE) run-cgen arch=fr30 prefix=fr30 options= extrafiles= -# end-sanitize-cygnus - -# start-sanitize-tic80 -tic80-dis.lo: tic80-dis.c $(INCDIR)/dis-asm.h ../bfd/bfd.h \ - $(INCDIR)/opcode/tic80.h -tic80-opc.lo: tic80-opc.c $(INCDIR)/opcode/tic80.h -# end-sanitize-tic80 - -# start-sanitize-sky -dvp-dis.lo: dvp-dis.c $(INCDIR)/dis-asm.h ../bfd/bfd.h \ - $(INCDIR)/opcode/dvp.h -dvp-opc.lo: dvp-opc.c $(INCDIR)/opcode/dvp.h - -mips-dis.lo: mips-dis.c - $(LIBTOOL) --mode=compile $(COMPILE) -c @archdefs@ $(srcdir)/mips-dis.c -# end-sanitize-sky - -# This dependency stuff is copied from BFD. - -.dep: dep.sed $(CFILES) $(HFILES) config.h - rm -f .dep1 - $(MAKE) DEP=$(DEP) .dep1 - sed -f dep.sed < .dep1 > .dep - -.dep1: $(CFILES) - rm -f .dep2 .dep2a - echo '# DO NOT DELETE THIS LINE -- mkdep uses it.' > .dep2 - echo > .dep2a - $(DEP) -f .dep2a $(INCLUDES) $(CFLAGS) $? - sed -e '/DO NOT DELETE/d' -e '/^$$/d' < .dep2a >> .dep2 - rm -f .dep2a - $(srcdir)/../move-if-change .dep2 .dep1 - -dep.sed: dep-in.sed config.status - sed <$(srcdir)/dep-in.sed >dep.sed \ - -e 's!@BFD_H@!$(BFD_H)!' \ - -e 's!@INCDIR@!$(INCDIR)!' \ - -e 's!@BFDDIR@!$(BFDDIR)!' \ - -e 's!@SRCDIR@!$(srcdir)!' - -dep: .dep - sed -e '/^..DO NOT DELETE THIS LINE/,$$d' < Makefile > tmp-Makefile - cat .dep >> tmp-Makefile - $(srcdir)/../move-if-change tmp-Makefile Makefile - -dep-in: .dep - sed -e '/^..DO NOT DELETE THIS LINE/,$$d' < $(srcdir)/Makefile.in > tmp-Makefile.in - cat .dep >> tmp-Makefile.in - $(srcdir)/../move-if-change tmp-Makefile.in $(srcdir)/Makefile.in - -dep-am: .dep - sed -e '/^..DO NOT DELETE THIS LINE/,$$d' < $(srcdir)/Makefile.am > tmp-Makefile.am - cat .dep >> tmp-Makefile.am - $(srcdir)/../move-if-change tmp-Makefile.am $(srcdir)/Makefile.am - -.PHONY: dep dep-in dep-am - -# What appears below is generated by a hacked mkdep using gcc -MM. - -# DO NOT DELETE THIS LINE -- mkdep uses it. -# DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY. -a29k-dis.lo: a29k-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ - $(INCDIR)/ansidecl.h $(INCDIR)/opcode/a29k.h -alpha-dis.lo: alpha-dis.c $(INCDIR)/ansidecl.h sysdep.h \ - config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/alpha.h -alpha-opc.lo: alpha-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/alpha.h \ - $(BFD_H) opintl.h -arm-dis.lo: arm-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ - $(INCDIR)/ansidecl.h arm-opc.h $(INCDIR)/coff/internal.h \ - $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h opintl.h $(BFDDIR)/elf-bfd.h \ - $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ - $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h -cgen-asm.lo: cgen-asm.c sysdep.h config.h $(INCDIR)/libiberty.h \ - $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h \ - opintl.h -cgen-dis.lo: cgen-dis.c sysdep.h config.h $(INCDIR)/libiberty.h \ - $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h -cgen-opc.lo: cgen-opc.c sysdep.h config.h $(INCDIR)/libiberty.h \ - $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h -d10v-dis.lo: d10v-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/d10v.h \ - $(INCDIR)/dis-asm.h $(BFD_H) -d10v-opc.lo: d10v-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/d10v.h -d30v-dis.lo: d30v-dis.c $(INCDIR)/opcode/d30v.h $(INCDIR)/dis-asm.h \ - $(BFD_H) $(INCDIR)/ansidecl.h opintl.h -d30v-opc.lo: d30v-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/d30v.h -dis-buf.lo: dis-buf.c sysdep.h config.h $(INCDIR)/dis-asm.h \ - $(BFD_H) opintl.h -disassemble.lo: disassemble.c $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) -fr30-asm.lo: fr30-asm.c sysdep.h config.h $(BFD_H) \ - $(INCDIR)/symcat.h fr30-desc.h fr30-opc.h $(INCDIR)/opcode/cgen.h \ - opintl.h -fr30-desc.lo: fr30-desc.c sysdep.h config.h $(BFD_H) \ - $(INCDIR)/symcat.h fr30-desc.h fr30-opc.h $(INCDIR)/opcode/cgen.h \ - opintl.h -fr30-dis.lo: fr30-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \ - $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h fr30-opc.h $(INCDIR)/opcode/cgen.h \ - opintl.h -fr30-ibld.lo: fr30-ibld.c sysdep.h config.h $(BFD_H) \ - $(INCDIR)/symcat.h fr30-desc.h fr30-opc.h $(INCDIR)/opcode/cgen.h \ - opintl.h -fr30-opc.lo: fr30-opc.c sysdep.h config.h $(INCDIR)/libiberty.h \ - $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h fr30-opc.h $(INCDIR)/opcode/cgen.h \ - opintl.h -h8300-dis.lo: h8300-dis.c $(INCDIR)/opcode/h8300.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h opintl.h -h8500-dis.lo: h8500-dis.c h8500-opc.h $(INCDIR)/dis-asm.h \ - $(BFD_H) $(INCDIR)/ansidecl.h opintl.h -hppa-dis.lo: hppa-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \ - $(BFD_H) $(BFDDIR)/libhppa.h $(INCDIR)/opcode/hppa.h -i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ - $(INCDIR)/ansidecl.h sysdep.h config.h opintl.h -i960-dis.lo: i960-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ - $(INCDIR)/ansidecl.h -m32r-asm.lo: m32r-asm.c sysdep.h config.h $(BFD_H) \ - $(INCDIR)/symcat.h m32r-desc.h m32r-opc.h $(INCDIR)/opcode/cgen.h \ - opintl.h -m32r-desc.lo: m32r-desc.c sysdep.h config.h $(BFD_H) \ - $(INCDIR)/symcat.h m32r-desc.h m32r-opc.h $(INCDIR)/opcode/cgen.h \ - opintl.h -m32r-dis.lo: m32r-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \ - $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h m32r-opc.h $(INCDIR)/opcode/cgen.h \ - opintl.h -m32r-ibld.lo: m32r-ibld.c sysdep.h config.h $(BFD_H) \ - $(INCDIR)/symcat.h m32r-desc.h m32r-opc.h $(INCDIR)/opcode/cgen.h \ - opintl.h -m32r-opc.lo: m32r-opc.c sysdep.h config.h $(INCDIR)/libiberty.h \ - $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h m32r-opc.h $(INCDIR)/opcode/cgen.h \ - opintl.h -m32r-opinst.lo: m32r-opinst.c sysdep.h config.h $(INCDIR)/libiberty.h \ - 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Copyright (C) 1990, 93, 94, 95, 1998 Free Software Foundation, Inc. - Contributed by Cygnus Support. Written by Jim Kingdon. - -This file is part of GDB. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "dis-asm.h" -#include "opcode/a29k.h" - -/* Print a symbolic representation of a general-purpose - register number NUM on STREAM. - NUM is a number as found in the instruction, not as found in - debugging symbols; it must be in the range 0-255. */ -static void -print_general (num, info) - int num; - struct disassemble_info *info; -{ - if (num < 128) - (*info->fprintf_func) (info->stream, "gr%d", num); - else - (*info->fprintf_func) (info->stream, "lr%d", num - 128); -} - -/* Like print_general but a special-purpose register. - - The mnemonics used by the AMD assembler are not quite the same - as the ones in the User's Manual. We use the ones that the - assembler uses. */ -static void -print_special (num, info) - unsigned int num; - struct disassemble_info *info; -{ - /* Register names of registers 0-SPEC0_NUM-1. */ - static char *spec0_names[] = { - "vab", "ops", "cps", "cfg", "cha", "chd", "chc", "rbp", "tmc", "tmr", - "pc0", "pc1", "pc2", "mmu", "lru", "rsn", "rma0", "rmc0", "rma1", "rmc1", - "spc0", "spc1", "spc2", "iba0", "ibc0", "iba1", "ibc1", "dba", "dbc", - "cir", "cdr" - }; -#define SPEC0_NUM ((sizeof spec0_names) / (sizeof spec0_names[0])) - - /* Register names of registers 128-128+SPEC128_NUM-1. */ - static char *spec128_names[] = { - "ipc", "ipa", "ipb", "q", "alu", "bp", "fc", "cr" - }; -#define SPEC128_NUM ((sizeof spec128_names) / (sizeof spec128_names[0])) - - /* Register names of registers 160-160+SPEC160_NUM-1. */ - static char *spec160_names[] = { - "fpe", "inte", "fps", "sr163", "exop" - }; -#define SPEC160_NUM ((sizeof spec160_names) / (sizeof spec160_names[0])) - - if (num < SPEC0_NUM) - (*info->fprintf_func) (info->stream, spec0_names[num]); - else if (num >= 128 && num < 128 + SPEC128_NUM) - (*info->fprintf_func) (info->stream, spec128_names[num-128]); - else if (num >= 160 && num < 160 + SPEC160_NUM) - (*info->fprintf_func) (info->stream, spec160_names[num-160]); - else - (*info->fprintf_func) (info->stream, "sr%d", num); -} - -/* Is an instruction with OPCODE a delayed branch? */ -static int -is_delayed_branch (opcode) - int opcode; -{ - return (opcode == 0xa8 || opcode == 0xa9 || opcode == 0xa0 || opcode == 0xa1 - || opcode == 0xa4 || opcode == 0xa5 - || opcode == 0xb4 || opcode == 0xb5 - || opcode == 0xc4 || opcode == 0xc0 - || opcode == 0xac || opcode == 0xad - || opcode == 0xcc); -} - -/* Now find the four bytes of INSN and put them in *INSN{0,8,16,24}. */ -static void -find_bytes_big (insn, insn0, insn8, insn16, insn24) - char *insn; - unsigned char *insn0; - unsigned char *insn8; - unsigned char *insn16; - unsigned char *insn24; -{ - *insn24 = insn[0]; - *insn16 = insn[1]; - *insn8 = insn[2]; - *insn0 = insn[3]; -} - -static void -find_bytes_little (insn, insn0, insn8, insn16, insn24) - char *insn; - unsigned char *insn0; - unsigned char *insn8; - unsigned char *insn16; - unsigned char *insn24; -{ - *insn24 = insn[3]; - *insn16 = insn[2]; - *insn8 = insn[1]; - *insn0 = insn[0]; -} - -typedef void (*find_byte_func_type) - PARAMS ((char *, unsigned char *, unsigned char *, - unsigned char *, unsigned char *)); - -/* Print one instruction from MEMADDR on INFO->STREAM. - Return the size of the instruction (always 4 on a29k). */ - -static int -print_insn (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - /* The raw instruction. */ - char insn[4]; - - /* The four bytes of the instruction. */ - unsigned char insn24, insn16, insn8, insn0; - - find_byte_func_type find_byte_func = (find_byte_func_type)info->private_data; - - struct a29k_opcode CONST * opcode; - - { - int status = - (*info->read_memory_func) (memaddr, (bfd_byte *) &insn[0], 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - } - - (*find_byte_func) (insn, &insn0, &insn8, &insn16, &insn24); - - printf ("%02x%02x%02x%02x ", insn24, insn16, insn8, insn0); - - /* Handle the nop (aseq 0x40,gr1,gr1) specially */ - if ((insn24==0x70) && (insn16==0x40) && (insn8==0x01) && (insn0==0x01)) { - (*info->fprintf_func) (info->stream,"nop"); - return 4; - } - - /* The opcode is always in insn24. */ - for (opcode = &a29k_opcodes[0]; - opcode < &a29k_opcodes[num_opcodes]; - ++opcode) - { - if (((unsigned long) insn24 << 24) == opcode->opcode) - { - char *s; - - (*info->fprintf_func) (info->stream, "%s ", opcode->name); - for (s = opcode->args; *s != '\0'; ++s) - { - switch (*s) - { - case 'a': - print_general (insn8, info); - break; - - case 'b': - print_general (insn0, info); - break; - - case 'c': - print_general (insn16, info); - break; - - case 'i': - (*info->fprintf_func) (info->stream, "%d", insn0); - break; - - case 'x': - (*info->fprintf_func) (info->stream, "0x%x", (insn16 << 8) + insn0); - break; - - case 'h': - /* This used to be %x for binutils. */ - (*info->fprintf_func) (info->stream, "0x%x", - (insn16 << 24) + (insn0 << 16)); - break; - - case 'X': - (*info->fprintf_func) (info->stream, "%d", - ((insn16 << 8) + insn0) | 0xffff0000); - break; - - case 'P': - /* This output looks just like absolute addressing, but - maybe that's OK (it's what the GDB m68k and EBMON - a29k disassemblers do). */ - /* All the shifting is to sign-extend it. p*/ - (*info->print_address_func) - (memaddr + - (((int)((insn16 << 10) + (insn0 << 2)) << 14) >> 14), - info); - break; - - case 'A': - (*info->print_address_func) - ((insn16 << 10) + (insn0 << 2), info); - break; - - case 'e': - (*info->fprintf_func) (info->stream, "%d", insn16 >> 7); - break; - - case 'n': - (*info->fprintf_func) (info->stream, "0x%x", insn16 & 0x7f); - break; - - case 'v': - (*info->fprintf_func) (info->stream, "0x%x", insn16); - break; - - case 's': - print_special (insn8, info); - break; - - case 'u': - (*info->fprintf_func) (info->stream, "%d", insn0 >> 7); - break; - - case 'r': - (*info->fprintf_func) (info->stream, "%d", (insn0 >> 4) & 7); - break; - - case 'I': - if ((insn16 & 3) != 0) - (*info->fprintf_func) (info->stream, "%d", insn16 & 3); - break; - - case 'd': - (*info->fprintf_func) (info->stream, "%d", (insn0 >> 2) & 3); - break; - - case 'f': - (*info->fprintf_func) (info->stream, "%d", insn0 & 3); - break; - - case 'F': - (*info->fprintf_func) (info->stream, "%d", (insn16 >> 2) & 15); - break; - - case 'C': - (*info->fprintf_func) (info->stream, "%d", insn16 & 3); - break; - - default: - (*info->fprintf_func) (info->stream, "%c", *s); - } - } - - /* Now we look for a const,consth pair of instructions, - in which case we try to print the symbolic address. */ - if (insn24 == 2) /* consth */ - { - int errcode; - char prev_insn[4]; - unsigned char prev_insn0, prev_insn8, prev_insn16, prev_insn24; - - errcode = (*info->read_memory_func) (memaddr - 4, - (bfd_byte *) &prev_insn[0], - 4, - info); - if (errcode == 0) - { - /* If it is a delayed branch, we need to look at the - instruction before the delayed brach to handle - things like - - const _foo - call _printf - consth _foo - */ - (*find_byte_func) (prev_insn, &prev_insn0, &prev_insn8, - &prev_insn16, &prev_insn24); - if (is_delayed_branch (prev_insn24)) - { - errcode = (*info->read_memory_func) - (memaddr - 8, (bfd_byte *) &prev_insn[0], 4, info); - (*find_byte_func) (prev_insn, &prev_insn0, &prev_insn8, - &prev_insn16, &prev_insn24); - } - } - - /* If there was a problem reading memory, then assume - the previous instruction was not const. */ - if (errcode == 0) - { - /* Is it const to the same register? */ - if (prev_insn24 == 3 - && prev_insn8 == insn8) - { - (*info->fprintf_func) (info->stream, "\t; "); - (*info->print_address_func) - (((insn16 << 24) + (insn0 << 16) - + (prev_insn16 << 8) + (prev_insn0)), - info); - } - } - } - - return 4; - } - } - /* This used to be %8x for binutils. */ - (*info->fprintf_func) - (info->stream, ".word 0x%08x", - (insn24 << 24) + (insn16 << 16) + (insn8 << 8) + insn0); - return 4; -} - -/* Disassemble an big-endian a29k instruction. */ -int -print_insn_big_a29k (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - info->private_data = (PTR) find_bytes_big; - return print_insn (memaddr, info); -} - -/* Disassemble a little-endian a29k instruction. */ -int -print_insn_little_a29k (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - info->private_data = (PTR) find_bytes_little; - return print_insn (memaddr, info); -} diff --git a/opcodes/acinclude.m4 b/opcodes/acinclude.m4 deleted file mode 100644 index 71b09b9f6ac..00000000000 --- a/opcodes/acinclude.m4 +++ /dev/null @@ -1 +0,0 @@ -sinclude(../bfd/acinclude.m4) diff --git a/opcodes/aclocal.m4 b/opcodes/aclocal.m4 deleted file mode 100644 index d38c985efa9..00000000000 --- a/opcodes/aclocal.m4 +++ /dev/null @@ -1,817 +0,0 @@ -dnl aclocal.m4 generated automatically by aclocal 1.3 - -dnl Copyright (C) 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc. -dnl This Makefile.in is free software; the Free Software Foundation -dnl gives unlimited permission to copy and/or distribute it, -dnl with or without modifications, as long as this notice is preserved. - -dnl This program is distributed in the hope that it will be useful, -dnl but WITHOUT ANY WARRANTY, to the extent permitted by law; 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While doing this - dnl we only have to keep exactly one list of the available catalogs - dnl in configure.in. - for lang in $ALL_LINGUAS; do - GMOFILES="$GMOFILES $lang.gmo" - POFILES="$POFILES $lang.po" - done - - dnl Make all variables we use known to autoconf. - AC_SUBST(USE_INCLUDED_LIBINTL) - AC_SUBST(CATALOGS) - AC_SUBST(CATOBJEXT) - AC_SUBST(DATADIRNAME) - AC_SUBST(GMOFILES) - AC_SUBST(INSTOBJEXT) - AC_SUBST(INTLDEPS) - AC_SUBST(INTLLIBS) - AC_SUBST(INTLOBJS) - AC_SUBST(POFILES) - AC_SUBST(POSUB) - ]) - -AC_DEFUN(CY_GNU_GETTEXT, - [AC_REQUIRE([AC_PROG_MAKE_SET])dnl - AC_REQUIRE([AC_PROG_CC])dnl - AC_REQUIRE([AC_PROG_RANLIB])dnl - AC_REQUIRE([AC_ISC_POSIX])dnl - AC_REQUIRE([AC_HEADER_STDC])dnl - AC_REQUIRE([AC_C_CONST])dnl - AC_REQUIRE([AC_C_INLINE])dnl - AC_REQUIRE([AC_TYPE_OFF_T])dnl - AC_REQUIRE([AC_TYPE_SIZE_T])dnl - AC_REQUIRE([AC_FUNC_ALLOCA])dnl - AC_REQUIRE([AC_FUNC_MMAP])dnl - - AC_CHECK_HEADERS([argz.h limits.h locale.h nl_types.h malloc.h string.h \ -unistd.h values.h sys/param.h]) - AC_CHECK_FUNCS([getcwd munmap putenv setenv setlocale strchr strcasecmp \ -__argz_count __argz_stringify __argz_next]) - - if test "${ac_cv_func_stpcpy+set}" != "set"; then - AC_CHECK_FUNCS(stpcpy) - fi - if test "${ac_cv_func_stpcpy}" = "yes"; then - AC_DEFINE(HAVE_STPCPY) - fi - - AM_LC_MESSAGES - CY_WITH_NLS - - if test "x$CATOBJEXT" != "x"; then - if test "x$ALL_LINGUAS" = "x"; then - LINGUAS= - else - AC_MSG_CHECKING(for catalogs to be installed) - NEW_LINGUAS= - for lang in ${LINGUAS=$ALL_LINGUAS}; do - case "$ALL_LINGUAS" in - *$lang*) NEW_LINGUAS="$NEW_LINGUAS $lang" ;; - esac - done - LINGUAS=$NEW_LINGUAS - AC_MSG_RESULT($LINGUAS) - fi - - dnl Construct list of names of catalog files to be constructed. - if test -n "$LINGUAS"; then - for lang in $LINGUAS; do CATALOGS="$CATALOGS $lang$CATOBJEXT"; done - fi - fi - - dnl The reference to <locale.h> in the installed <libintl.h> file - dnl must be resolved because we cannot expect the users of this - dnl to define HAVE_LOCALE_H. - if test $ac_cv_header_locale_h = yes; then - INCLUDE_LOCALE_H="#include <locale.h>" - else - INCLUDE_LOCALE_H="\ -/* The system does not provide the header <locale.h>. Take care yourself. */" - fi - AC_SUBST(INCLUDE_LOCALE_H) - - dnl Determine which catalog format we have (if any is needed) - dnl For now we know about two different formats: - dnl Linux libc-5 and the normal X/Open format - if test -f $srcdir/po2tbl.sed.in; then - if test "$CATOBJEXT" = ".cat"; then - AC_CHECK_HEADER(linux/version.h, msgformat=linux, msgformat=xopen) - - dnl Transform the SED scripts while copying because some dumb SEDs - dnl cannot handle comments. - sed -e '/^#/d' $srcdir/$msgformat-msg.sed > po2msg.sed - fi - dnl po2tbl.sed is always needed. - sed -e '/^#.*[^\\]$/d' -e '/^#$/d' \ - $srcdir/po2tbl.sed.in > po2tbl.sed - fi - - dnl In the intl/Makefile.in we have a special dependency which makes - dnl only sense for gettext. We comment this out for non-gettext - dnl packages. - if test "$PACKAGE" = "gettext"; then - GT_NO="#NO#" - GT_YES= - else - GT_NO= - GT_YES="#YES#" - fi - AC_SUBST(GT_NO) - AC_SUBST(GT_YES) - - MKINSTALLDIRS="\$(srcdir)/../../mkinstalldirs" - AC_SUBST(MKINSTALLDIRS) - - dnl *** For now the libtool support in intl/Makefile is not for real. - l= - AC_SUBST(l) - - dnl Generate list of files to be processed by xgettext which will - dnl be included in po/Makefile. But only do this if the po directory - dnl exists in srcdir. - if test -d $srcdir/po; then - test -d po || mkdir po - if test "x$srcdir" != "x."; then - if test "x`echo $srcdir | sed 's@/.*@@'`" = "x"; then - posrcprefix="$srcdir/" - else - posrcprefix="../$srcdir/" - fi - else - posrcprefix="../" - fi - rm -f po/POTFILES - sed -e "/^#/d" -e "/^\$/d" -e "s,.*, $posrcprefix& \\\\," -e "\$s/\(.*\) \\\\/\1/" \ - < $srcdir/po/POTFILES.in > po/POTFILES - fi - ]) - -# Search path for a program which passes the given test. -# Ulrich Drepper <drepper@cygnus.com>, 1996. -# -# This file file be copied and used freely without restrictions. It can -# be used in projects which are not available under the GNU Public License -# but which still want to provide support for the GNU gettext functionality. -# Please note that the actual code is *not* freely available. - -# serial 1 - -dnl AM_PATH_PROG_WITH_TEST(VARIABLE, PROG-TO-CHECK-FOR, -dnl TEST-PERFORMED-ON-FOUND_PROGRAM [, VALUE-IF-NOT-FOUND [, PATH]]) -AC_DEFUN(AM_PATH_PROG_WITH_TEST, -[# Extract the first word of "$2", so it can be a program name with args. -set dummy $2; ac_word=[$]2 -AC_MSG_CHECKING([for $ac_word]) -AC_CACHE_VAL(ac_cv_path_$1, -[case "[$]$1" in - /*) - ac_cv_path_$1="[$]$1" # Let the user override the test with a path. - ;; - *) - IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:" - for ac_dir in ifelse([$5], , $PATH, [$5]); do - test -z "$ac_dir" && ac_dir=. - if test -f $ac_dir/$ac_word; then - if [$3]; then - ac_cv_path_$1="$ac_dir/$ac_word" - break - fi - fi - done - IFS="$ac_save_ifs" -dnl If no 4th arg is given, leave the cache variable unset, -dnl so AC_PATH_PROGS will keep looking. -ifelse([$4], , , [ test -z "[$]ac_cv_path_$1" && ac_cv_path_$1="$4" -])dnl - ;; -esac])dnl -$1="$ac_cv_path_$1" -if test -n "[$]$1"; then - AC_MSG_RESULT([$]$1) -else - AC_MSG_RESULT(no) -fi -AC_SUBST($1)dnl -]) - -# Check whether LC_MESSAGES is available in <locale.h>. -# Ulrich Drepper <drepper@cygnus.com>, 1995. -# -# This file file be copied and used freely without restrictions. It can -# be used in projects which are not available under the GNU Public License -# but which still want to provide support for the GNU gettext functionality. -# Please note that the actual code is *not* freely available. - -# serial 1 - -AC_DEFUN(AM_LC_MESSAGES, - [if test $ac_cv_header_locale_h = yes; then - AC_CACHE_CHECK([for LC_MESSAGES], am_cv_val_LC_MESSAGES, - [AC_TRY_LINK([#include <locale.h>], [return LC_MESSAGES], - am_cv_val_LC_MESSAGES=yes, am_cv_val_LC_MESSAGES=no)]) - if test $am_cv_val_LC_MESSAGES = yes; then - AC_DEFINE(HAVE_LC_MESSAGES) - fi - fi]) - diff --git a/opcodes/alpha-dis.c b/opcodes/alpha-dis.c deleted file mode 100644 index d2ea92d6b2d..00000000000 --- a/opcodes/alpha-dis.c +++ /dev/null @@ -1,212 +0,0 @@ -/* alpha-dis.c -- Disassemble Alpha AXP instructions - Copyright 1996 Free Software Foundation, Inc. - Contributed by Richard Henderson <rth@tamu.edu>, - patterned after the PPC opcode handling written by Ian Lance Taylor. - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -2, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA -02111-1307, USA. */ - -#include <stdlib.h> -#include <stdio.h> -#include "ansidecl.h" -#include "sysdep.h" -#include "dis-asm.h" -#include "opcode/alpha.h" - -static int print_insn_alpha - PARAMS ((bfd_vma, struct disassemble_info *, const char * const *, int)); - -/* Disassemble Alpha instructions using OSF register names. */ - -int -print_insn_alpha_osf (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - static const char * const osf_regnames[64] = { - "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", - "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", - "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", - "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero", - "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", - "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", - "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", - "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" - }; - - return print_insn_alpha (memaddr, info, osf_regnames, AXP_OPCODE_ALL); -} - -/* Disassemble Alpha instructions using VMS register names. */ - -int -print_insn_alpha_vms (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - static const char * const vms_regnames[64] = { - "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", - "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", - "R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23", - "R24", "AI", "RA", "PV", "AT", "FP", "SP", "RZ", - "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7", - "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15", - "F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23", - "F24", "F25", "F26", "F27", "F28", "F29", "F30", "FZ" - }; - - return print_insn_alpha (memaddr, info, vms_regnames, AXP_OPCODE_ALL); -} - -/* Disassemble Alpha instructions. */ - -static int -print_insn_alpha (memaddr, info, regnames, cpumask) - bfd_vma memaddr; - struct disassemble_info *info; - const char * const * regnames; - int cpumask; -{ - static const struct alpha_opcode *opcode_index[AXP_NOPS+1]; - const struct alpha_opcode *opcode, *opcode_end; - const unsigned char *opindex; - unsigned insn, op; - int need_comma; - - /* Initialize the majorop table the first time through */ - if (!opcode_index[0]) - { - opcode = alpha_opcodes; - opcode_end = opcode + alpha_num_opcodes; - - for (op = 0; op < AXP_NOPS; ++op) - { - opcode_index[op] = opcode; - while (opcode < opcode_end && op == AXP_OP (opcode->opcode)) - ++opcode; - } - opcode_index[op] = opcode; - } - - /* Read the insn into a host word */ - { - bfd_byte buffer[4]; - int status = (*info->read_memory_func) (memaddr, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn = bfd_getl32 (buffer); - } - - /* Get the major opcode of the instruction. */ - op = AXP_OP (insn); - - /* Find the first match in the opcode table. */ - opcode_end = opcode_index[op+1]; - for (opcode = opcode_index[op]; opcode < opcode_end; ++opcode) - { - if ((insn & opcode->mask) != opcode->opcode) - continue; - - if (!(opcode->flags & cpumask)) - continue; - - /* Make two passes over the operands. First see if any of them - have extraction functions, and, if they do, make sure the - instruction is valid. */ - { - int invalid = 0; - for (opindex = opcode->operands; *opindex != 0; opindex++) - { - const struct alpha_operand *operand = alpha_operands + *opindex; - if (operand->extract) - (*operand->extract) (insn, &invalid); - } - if (invalid) - continue; - } - - /* The instruction is valid. */ - goto found; - } - - /* No instruction found */ - (*info->fprintf_func) (info->stream, ".long %#08x", insn); - - return 4; - -found: - (*info->fprintf_func) (info->stream, "%s", opcode->name); - if (opcode->operands[0] != 0) - (*info->fprintf_func) (info->stream, "\t"); - - /* Now extract and print the operands. */ - need_comma = 0; - for (opindex = opcode->operands; *opindex != 0; opindex++) - { - const struct alpha_operand *operand = alpha_operands + *opindex; - int value; - - /* Operands that are marked FAKE are simply ignored. We - already made sure that the extract function considered - the instruction to be valid. */ - if ((operand->flags & AXP_OPERAND_FAKE) != 0) - continue; - - /* Extract the value from the instruction. */ - if (operand->extract) - value = (*operand->extract) (insn, (int *) NULL); - else - { - value = (insn >> operand->shift) & ((1 << operand->bits) - 1); - if (operand->flags & AXP_OPERAND_SIGNED) - { - int signbit = 1 << (operand->bits - 1); - value = (value ^ signbit) - signbit; - } - } - - if (need_comma && - ((operand->flags & (AXP_OPERAND_PARENS|AXP_OPERAND_COMMA)) - != AXP_OPERAND_PARENS)) - { - (*info->fprintf_func) (info->stream, ","); - } - if (operand->flags & AXP_OPERAND_PARENS) - (*info->fprintf_func) (info->stream, "("); - - /* Print the operand as directed by the flags. */ - if (operand->flags & AXP_OPERAND_IR) - (*info->fprintf_func) (info->stream, "%s", regnames[value]); - else if (operand->flags & AXP_OPERAND_FPR) - (*info->fprintf_func) (info->stream, "%s", regnames[value+32]); - else if (operand->flags & AXP_OPERAND_RELATIVE) - (*info->print_address_func) (memaddr + 4 + value, info); - else if (operand->flags & AXP_OPERAND_SIGNED) - (*info->fprintf_func) (info->stream, "%d", value); - else - (*info->fprintf_func) (info->stream, "%#x", value); - - if (operand->flags & AXP_OPERAND_PARENS) - (*info->fprintf_func) (info->stream, ")"); - need_comma = 1; - } - - return 4; -} diff --git a/opcodes/alpha-opc.c b/opcodes/alpha-opc.c deleted file mode 100644 index b1935eabe61..00000000000 --- a/opcodes/alpha-opc.c +++ /dev/null @@ -1,1356 +0,0 @@ -/* alpha-opc.c -- Alpha AXP opcode list - Copyright 1996 Free Software Foundation, Inc. - Contributed by Richard Henderson <rth@tamu.edu>, - patterned after the PPC opcode handling written by Ian Lance Taylor. - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version - 2, or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -#include <stdio.h> -#include "ansidecl.h" -#include "opcode/alpha.h" - -/* This file holds the Alpha AXP opcode table. The opcode table - includes almost all of the extended instruction mnemonics. This - permits the disassembler to use them, and simplifies the assembler - logic, at the cost of increasing the table size. The table is - strictly constant data, so the compiler should be able to put it in - the .text section. - - This file also holds the operand table. All knowledge about - inserting operands into instructions and vice-versa is kept in this - file. */ - -/* Local insertion and extraction functions */ - -static unsigned insert_rba PARAMS((unsigned, int, const char **)); -static unsigned insert_rca PARAMS((unsigned, int, const char **)); -static unsigned insert_za PARAMS((unsigned, int, const char **)); -static unsigned insert_zb PARAMS((unsigned, int, const char **)); -static unsigned insert_zc PARAMS((unsigned, int, const char **)); -static unsigned insert_bdisp PARAMS((unsigned, int, const char **)); -static unsigned insert_jhint PARAMS((unsigned, int, const char **)); - -static int extract_rba PARAMS((unsigned, int *)); -static int extract_rca PARAMS((unsigned, int *)); -static int extract_za PARAMS((unsigned, int *)); -static int extract_zb PARAMS((unsigned, int *)); -static int extract_zc PARAMS((unsigned, int *)); -static int extract_bdisp PARAMS((unsigned, int *)); -static int extract_jhint PARAMS((unsigned, int *)); - - -/* The operands table */ - -const struct alpha_operand alpha_operands[] = -{ - /* The fields are bits, shift, insert, extract, flags */ - /* The zero index is used to indicate end-of-list */ -#define UNUSED 0 - { 0, 0, BFD_RELOC_UNUSED, 0, 0 }, - - /* The plain integer register fields */ -#define RA (UNUSED + 1) - { 5, 21, BFD_RELOC_UNUSED, 0, 0, AXP_OPERAND_IR }, -#define RB (RA + 1) - { 5, 16, BFD_RELOC_UNUSED, 0, 0, AXP_OPERAND_IR }, -#define RC (RB + 1) - { 5, 0, BFD_RELOC_UNUSED, 0, 0, AXP_OPERAND_IR }, - - /* The plain fp register fields */ -#define FA (RC + 1) - { 5, 21, BFD_RELOC_UNUSED, 0, 0, AXP_OPERAND_FPR }, -#define FB (FA + 1) - { 5, 16, BFD_RELOC_UNUSED, 0, 0, AXP_OPERAND_FPR }, -#define FC (FB + 1) - { 5, 0, BFD_RELOC_UNUSED, 0, 0, AXP_OPERAND_FPR }, - - /* The integer registers when they are ZERO */ -#define ZA (FC + 1) - { 5, 21, BFD_RELOC_UNUSED, insert_za, extract_za, AXP_OPERAND_FAKE }, -#define ZB (ZA + 1) - { 5, 16, BFD_RELOC_UNUSED, insert_zb, extract_zb, AXP_OPERAND_FAKE }, -#define ZC (ZB + 1) - { 5, 0, BFD_RELOC_UNUSED, insert_zc, extract_zc, AXP_OPERAND_FAKE }, - - /* The RB field when it needs parentheses */ -#define PRB (ZC + 1) - { 5, 16, BFD_RELOC_UNUSED, 0, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS }, - - /* The RB field when it needs parentheses _and_ a preceding comma */ -#define CPRB (PRB + 1) - { 5, 16, BFD_RELOC_UNUSED, 0, 0, - AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA }, - - /* The RB field when it must be the same as the RA field */ -#define RBA (CPRB + 1) - { 5, 16, BFD_RELOC_UNUSED, insert_rba, extract_rba, AXP_OPERAND_FAKE }, - - /* The RC field when it must be the same as the RB field */ -#define RCA (RBA + 1) - { 5, 0, BFD_RELOC_UNUSED, insert_rca, extract_rca, AXP_OPERAND_FAKE }, - - /* The RC field when it can *default* to RA */ -#define DRC1 (RCA + 1) - { 5, 0, BFD_RELOC_UNUSED, 0, 0, - AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST }, - - /* The RC field when it can *default* to RB */ -#define DRC2 (DRC1 + 1) - { 5, 0, BFD_RELOC_UNUSED, 0, 0, - AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND }, - - /* The FC field when it can *default* to RA */ -#define DFC1 (DRC2 + 1) - { 5, 0, BFD_RELOC_UNUSED, 0, 0, - AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST }, - - /* The FC field when it can *default* to RB */ -#define DFC2 (DFC1 + 1) - { 5, 0, BFD_RELOC_UNUSED, 0, 0, - AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND }, - - /* The unsigned 8-bit literal of Operate format insns */ -#define LIT (DFC2 + 1) - { 8, 13, BFD_RELOC_UNUSED+LIT, 0, 0, AXP_OPERAND_UNSIGNED }, - - /* The signed 16-bit displacement of Memory format insns. From here - we can't tell what relocation should be used, so don't use a default. */ -#define MDISP (LIT + 1) - { 16, 0, BFD_RELOC_UNUSED+MDISP, 0, 0, AXP_OPERAND_SIGNED }, - - /* The signed "23-bit" aligned displacement of Branch format insns */ -#define BDISP (MDISP + 1) - { 21, 0, BFD_RELOC_23_PCREL_S2, insert_bdisp, extract_bdisp, - AXP_OPERAND_RELATIVE }, - - /* The 26-bit PALcode function */ -#define PALFN (BDISP + 1) - { 26, 0, BFD_RELOC_UNUSED+PALFN, 0, 0, AXP_OPERAND_UNSIGNED }, - - /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */ -#define JMPHINT (PALFN + 1) - { 14, 0, BFD_RELOC_ALPHA_HINT, insert_jhint, extract_jhint, - AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW }, - - /* The optional hint to RET/JSR_COROUTINE */ -#define RETHINT (JMPHINT + 1) - { 14, 0, BFD_RELOC_UNUSED+RETHINT, 0, 0, - AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO }, - - /* The 12-bit displacement for the ev4 hw_{ld,st} (pal1b/pal1f) insns */ -#define EV4HWDISP (RETHINT + 1) - { 12, 0, BFD_RELOC_UNUSED+EV4HWDISP, 0, 0, AXP_OPERAND_SIGNED }, - - /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */ -#define EV4HWINDEX (EV4HWDISP + 1) - { 5, 0, BFD_RELOC_UNUSED+EV4HWINDEX, 0, 0, AXP_OPERAND_UNSIGNED }, - - /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns - that occur in DEC PALcode. */ -#define EV4EXTHWINDEX (EV4HWINDEX + 1) - { 5, 0, BFD_RELOC_UNUSED+EV4EXTHWINDEX, 0, 0, AXP_OPERAND_UNSIGNED }, - - /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */ -#define EV5HWDISP (EV4EXTHWINDEX + 1) - { 10, 0, BFD_RELOC_UNUSED+EV5HWDISP, 0, 0, AXP_OPERAND_SIGNED }, - - /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */ -#define EV5HWINDEX (EV5HWDISP + 1) - { 16, 0, BFD_RELOC_UNUSED+EV5HWINDEX, 0, 0, AXP_OPERAND_UNSIGNED }, -}; - -const int alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands); - -/* The RB field when it is the same as the RA field in the same insn. - This operand is marked fake. The insertion function just copies - the RA field into the RB field, and the extraction function just - checks that the fields are the same. */ - -/*ARGSUSED*/ -static unsigned -insert_rba(insn, value, errmsg) - unsigned insn; - int value; - const char **errmsg; -{ - return insn | (((insn >> 21) & 0x1f) << 16); -} - -static int -extract_rba(insn, invalid) - unsigned insn; - int *invalid; -{ - if (invalid != (int *) NULL - && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) - *invalid = 1; - return 0; -} - - -/* The same for the RC field */ - -/*ARGSUSED*/ -static unsigned -insert_rca(insn, value, errmsg) - unsigned insn; - int value; - const char **errmsg; -{ - return insn | ((insn >> 21) & 0x1f); -} - -static int -extract_rca(insn, invalid) - unsigned insn; - int *invalid; -{ - if (invalid != (int *) NULL - && ((insn >> 21) & 0x1f) != (insn & 0x1f)) - *invalid = 1; - return 0; -} - - -/* Fake arguments in which the registers must be set to ZERO */ - -/*ARGSUSED*/ -static unsigned -insert_za(insn, value, errmsg) - unsigned insn; - int value; - const char **errmsg; -{ - return insn | (31 << 21); -} - -static int -extract_za(insn, invalid) - unsigned insn; - int *invalid; -{ - if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31) - *invalid = 1; - return 0; -} - -/*ARGSUSED*/ -static unsigned -insert_zb(insn, value, errmsg) - unsigned insn; - int value; - const char **errmsg; -{ - return insn | (31 << 16); -} - -static int -extract_zb(insn, invalid) - unsigned insn; - int *invalid; -{ - if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31) - *invalid = 1; - return 0; -} - -/*ARGSUSED*/ -static unsigned -insert_zc(insn, value, errmsg) - unsigned insn; - int value; - const char **errmsg; -{ - return insn | 31; -} - -static int -extract_zc(insn, invalid) - unsigned insn; - int *invalid; -{ - if (invalid != (int *) NULL && (insn & 0x1f) != 31) - *invalid = 1; - return 0; -} - - -/* The displacement field of a Branch format insn. */ - -static unsigned -insert_bdisp(insn, value, errmsg) - unsigned insn; - int value; - const char **errmsg; -{ - if (errmsg != (const char **)NULL && (value & 3)) - *errmsg = "branch operand unaligned"; - return insn | ((value / 4) & 0x1FFFFF); -} - -/*ARGSUSED*/ -static int -extract_bdisp(insn, invalid) - unsigned insn; - int *invalid; -{ - return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000); -} - - -/* The hint field of a JMP/JSR insn. */ - -static unsigned -insert_jhint(insn, value, errmsg) - unsigned insn; - int value; - const char **errmsg; -{ - if (errmsg != (const char **)NULL && (value & 3)) - *errmsg = "jump hint unaligned"; - return insn | ((value / 4) & 0xFFFF); -} - -/*ARGSUSED*/ -static int -extract_jhint(insn, invalid) - unsigned insn; - int *invalid; -{ - return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000); -} - - -/* Macros used to form opcodes */ - -/* The main opcode */ -#define OP(x) (((x) & 0x3F) << 26) -#define OP_MASK 0xFC000000 - -/* Branch format instructions */ -#define BRA_(oo) OP(oo) -#define BRA_MASK OP_MASK -#define BRA(oo) BRA_(oo), BRA_MASK - -/* Floating point format instructions */ -#define FP_(oo,fff) (OP(oo) | (((fff) & 0x7FF) << 5)) -#define FP_MASK (OP_MASK | 0xFFE0) -#define FP(oo,fff) FP_(oo,fff), FP_MASK - -/* Memory format instructions */ -#define MEM_(oo) OP(oo) -#define MEM_MASK OP_MASK -#define MEM(oo) MEM_(oo), MEM_MASK - -/* Memory/Func Code format instructions */ -#define MFC_(oo,ffff) (OP(oo) | ((ffff) & 0xFFFF)) -#define MFC_MASK (OP_MASK | 0xFFFF) -#define MFC(oo,ffff) MFC_(oo,ffff), MFC_MASK - -/* Memory/Branch format instructions */ -#define MBR_(oo,h) (OP(oo) | (((h) & 3) << 14)) -#define MBR_MASK (OP_MASK | 0xC000) -#define MBR(oo,h) MBR_(oo,h), MBR_MASK - -/* Operate format instructions. The OPRL variant specifies a - literal second argument. */ -#define OPR_(oo,ff) (OP(oo) | (((ff) & 0x7F) << 5)) -#define OPRL_(oo,ff) (OPR_((oo),(ff)) | 0x1000) -#define OPR_MASK (OP_MASK | 0x1FE0) -#define OPR(oo,ff) OPR_(oo,ff), OPR_MASK -#define OPRL(oo,ff) OPRL_(oo,ff), OPR_MASK - -/* Generic PALcode format instructions */ -#define PCD_(oo) OP(oo) -#define PCD_MASK OP_MASK -#define PCD(oo) PCD_(oo), PCD_MASK - -/* Specific PALcode instructions */ -#define SPCD_(oo,ffff) (OP(oo) | ((ffff) & 0x3FFFFFF)) -#define SPCD_MASK 0xFFFFFFFF -#define SPCD(oo,ffff) SPCD_(oo,ffff), SPCD_MASK - -/* Hardware memory (hw_{ld,st}) instructions */ -#define EV4HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12)) -#define EV4HWMEM_MASK (OP_MASK | 0xF000) -#define EV4HWMEM(oo,f) EV4HWMEM_(oo,f), EV4HWMEM_MASK - -#define EV5HWMEM_(oo,f) (OP(oo) | (((f) & 0x3F) << 10)) -#define EV5HWMEM_MASK (OP_MASK | 0xF800) -#define EV5HWMEM(oo,f) EV5HWMEM_(oo,f), EV5HWMEM_MASK - -/* Common combinations of flags and arguments */ -#define ALL AXP_OPCODE_ALL -#define EV4 AXP_OPCODE_EV4 -#define EV5 AXP_OPCODE_EV5 -#define EV56 AXP_OPCODE_EV56 -#define EV5x EV5|EV56 - -#define ARG_NONE { 0 } -#define ARG_BRA { RA, BDISP } -#define ARG_FBRA { FA, BDISP } -#define ARG_FP { FA, FB, DFC1 } -#define ARG_FPZ1 { ZA, FB, DFC1 } -#define ARG_MEM { RA, MDISP, PRB } -#define ARG_FMEM { FA, MDISP, PRB } -#define ARG_OPR { RA, RB, DRC1 } -#define ARG_OPRL { RA, LIT, DRC1 } -#define ARG_OPRZ1 { ZA, RB, DRC1 } -#define ARG_OPRLZ1 { ZA, LIT, RC } -#define ARG_PCD { PALFN } -#define ARG_EV4HWMEM { RA, EV4HWDISP, PRB } -#define ARG_EV4HWMPR { RA, RBA, EV4HWINDEX } -#define ARG_EV5HWMEM { RA, EV5HWDISP, PRB } - - -/* The opcode table. - - The format of the opcode table is: - - NAME OPCODE MASK { OPERANDS } - - NAME is the name of the instruction. - - OPCODE is the instruction opcode. - - MASK is the opcode mask; this is used to tell the disassembler - which bits in the actual opcode must match OPCODE. - - OPERANDS is the list of operands. - - The preceding macros merge the text of the OPCODE and MASK fields. - - The disassembler reads the table in order and prints the first - instruction which matches, so this table is sorted to put more - specific instructions before more general instructions. - - Otherwise, it is sorted by major opcode and minor function code. - - There are three classes of not-really-instructions in this table: - - ALIAS is another name for another instruction. Some of - these come from the Architecture Handbook, some - come from the original gas opcode tables. In all - cases, the functionality of the opcode is unchanged. - - PSEUDO a stylized code form endorsed by Chapter A.4 of the - Architecture Handbook. - - EXTRA a stylized code form found in the original gas tables. - - XXX: Can anyone shed light on the pal{19,1b,1d,1e,1f} opcodes? - XXX: Do we want to conditionally compile complete sets of the - PALcodes described in the Architecture Handbook? -*/ - -const struct alpha_opcode alpha_opcodes[] = { - { "halt", SPCD(0x00,0x0000), ALL, ARG_NONE }, - { "draina", SPCD(0x00,0x0002), ALL, ARG_NONE }, - { "bpt", SPCD(0x00,0x0080), ALL, ARG_NONE }, - { "callsys", SPCD(0x00,0x0083), ALL, ARG_NONE }, - { "chmk", SPCD(0x00,0x0083), ALL, ARG_NONE }, - { "imb", SPCD(0x00,0x0086), ALL, ARG_NONE }, - { "call_pal", PCD(0x00), ALL, ARG_PCD }, - { "pal", PCD(0x00), ALL, ARG_PCD }, /* alias */ - - { "lda", MEM(0x08), ALL, ARG_MEM }, - { "ldah", MEM(0x09), ALL, ARG_MEM }, - { "unop", MEM(0x0B), ALL, { ZA } }, /* pseudo */ - { "ldq_u", MEM(0x0B), ALL, ARG_MEM }, - { "stq_u", MEM(0x0F), ALL, ARG_MEM }, - - { "sextl", OPR(0x10,0x00), ALL, ARG_OPRZ1 }, /* pseudo */ - { "sextl", OPRL(0x10,0x00), ALL, ARG_OPRLZ1 }, /* pseudo */ - { "addl", OPR(0x10,0x00), ALL, ARG_OPR }, - { "addl", OPRL(0x10,0x00), ALL, ARG_OPRL }, - { "s4addl", OPR(0x10,0x02), ALL, ARG_OPR }, - { "s4addl", OPRL(0x10,0x02), ALL, ARG_OPRL }, - { "negl", OPR(0x10,0x09), ALL, ARG_OPRZ1 }, /* pseudo */ - { "negl", OPRL(0x10,0x09), ALL, ARG_OPRLZ1 }, /* pseudo */ - { "subl", OPR(0x10,0x09), ALL, ARG_OPR }, - { "subl", OPRL(0x10,0x09), ALL, ARG_OPRL }, - { "s4subl", OPR(0x10,0x0B), ALL, ARG_OPR }, - { "s4subl", OPRL(0x10,0x0B), ALL, ARG_OPRL }, - { "cmpbge", OPR(0x10,0x0F), ALL, ARG_OPR }, - { "cmpbge", OPRL(0x10,0x0F), ALL, ARG_OPRL }, - { "s8addl", OPR(0x10,0x12), ALL, ARG_OPR }, - { "s8addl", OPRL(0x10,0x12), ALL, ARG_OPRL }, - { "s8subl", OPR(0x10,0x1B), ALL, ARG_OPR }, - { "s8subl", OPRL(0x10,0x1B), ALL, ARG_OPRL }, - { "cmpult", OPR(0x10,0x1D), ALL, ARG_OPR }, - { "cmpult", OPRL(0x10,0x1D), ALL, ARG_OPRL }, - { "addq", OPR(0x10,0x20), ALL, ARG_OPR }, - { "addq", OPRL(0x10,0x20), ALL, ARG_OPRL }, - { "s4addq", OPR(0x10,0x22), ALL, ARG_OPR }, - { "s4addq", OPRL(0x10,0x22), ALL, ARG_OPRL }, - { "negq", OPR(0x10,0x29), ALL, ARG_OPRZ1 }, /* pseudo */ - { "negq", OPRL(0x10,0x29), ALL, ARG_OPRLZ1 }, /* pseudo */ - { "subq", OPR(0x10,0x29), ALL, ARG_OPR }, - { "subq", OPRL(0x10,0x29), ALL, ARG_OPRL }, - { "s4subq", OPR(0x10,0x2B), ALL, ARG_OPR }, - { "s4subq", OPRL(0x10,0x2B), ALL, ARG_OPRL }, - { "cmpeq", OPR(0x10,0x2D), ALL, ARG_OPR }, - { "cmpeq", OPRL(0x10,0x2D), ALL, ARG_OPRL }, - { "s8addq", OPR(0x10,0x32), ALL, ARG_OPR }, - { "s8addq", OPRL(0x10,0x32), ALL, ARG_OPRL }, - { "s8subq", OPR(0x10,0x3B), ALL, ARG_OPR }, - { "s8subq", OPRL(0x10,0x3B), ALL, ARG_OPRL }, - { "cmpule", OPR(0x10,0x3D), ALL, ARG_OPR }, - { "cmpule", OPRL(0x10,0x3D), ALL, ARG_OPRL }, - { "addl/v", OPR(0x10,0x40), ALL, ARG_OPR }, - { "addl/v", OPRL(0x10,0x40), ALL, ARG_OPRL }, - { "negl/v", OPR(0x10,0x49), ALL, ARG_OPRZ1 }, /* pseudo */ - { "negl/v", OPRL(0x10,0x49), ALL, ARG_OPRLZ1 }, /* pseudo */ - { "subl/v", OPR(0x10,0x49), ALL, ARG_OPR }, - { "subl/v", OPRL(0x10,0x49), ALL, ARG_OPRL }, - { "cmplt", OPR(0x10,0x4D), ALL, ARG_OPR }, - { "cmplt", OPRL(0x10,0x4D), ALL, ARG_OPRL }, - { "addq/v", OPR(0x10,0x60), ALL, ARG_OPR }, - { "addq/v", OPRL(0x10,0x60), ALL, ARG_OPRL }, - { "negq/v", OPR(0x10,0x69), ALL, ARG_OPRZ1 }, /* pseudo */ - { "negq/v", OPRL(0x10,0x69), ALL, ARG_OPRLZ1 }, /* pseudo */ - { "subq/v", OPR(0x10,0x69), ALL, ARG_OPR }, - { "subq/v", OPRL(0x10,0x69), ALL, ARG_OPRL }, - { "cmple", OPR(0x10,0x6D), ALL, ARG_OPR }, - { "cmple", OPRL(0x10,0x6D), ALL, ARG_OPRL }, - - { "and", OPR(0x11,0x00), ALL, ARG_OPR }, - { "and", OPRL(0x11,0x00), ALL, ARG_OPRL }, - { "andnot", OPR(0x11,0x08), ALL, ARG_OPR }, /* alias */ - { "andnot", OPRL(0x11,0x08), ALL, ARG_OPRL }, /* alias */ - { "bic", OPR(0x11,0x08), ALL, ARG_OPR }, - { "bic", OPRL(0x11,0x08), ALL, ARG_OPRL }, - { "cmovlbs", OPR(0x11,0x14), ALL, ARG_OPR }, - { "cmovlbs", OPRL(0x11,0x14), ALL, ARG_OPRL }, - { "cmovlbc", OPR(0x11,0x16), ALL, ARG_OPR }, - { "cmovlbc", OPRL(0x11,0x16), ALL, ARG_OPRL }, - { "nop", OPR(0x11,0x20), ALL, { ZA, ZB, ZC } }, /* pseudo */ - { "clr", OPR(0x11,0x20), ALL, { ZA, ZB, RC } }, /* pseudo */ - { "mov", OPR(0x11,0x20), ALL, { ZA, RB, RC } }, /* pseudo */ - { "mov", OPR(0x11,0x20), ALL, { RA, RBA, RC } }, /* pseudo */ - { "mov", OPRL(0x11,0x20), ALL, { ZA, LIT, RC } }, /* pseudo */ - { "or", OPR(0x11,0x20), ALL, ARG_OPR }, /* alias */ - { "or", OPRL(0x11,0x20), ALL, ARG_OPRL }, /* alias */ - { "bis", OPR(0x11,0x20), ALL, ARG_OPR }, - { "bis", OPRL(0x11,0x20), ALL, ARG_OPRL }, - { "cmoveq", OPR(0x11,0x24), ALL, ARG_OPR }, - { "cmoveq", OPRL(0x11,0x24), ALL, ARG_OPRL }, - { "cmovne", OPR(0x11,0x26), ALL, ARG_OPR }, - { "cmovne", OPRL(0x11,0x26), ALL, ARG_OPRL }, - { "not", OPR(0x11,0x28), ALL, ARG_OPRZ1 }, /* pseudo */ - { "not", OPRL(0x11,0x28), ALL, ARG_OPRLZ1 }, /* pseudo */ - { "ornot", OPR(0x11,0x28), ALL, ARG_OPR }, - { "ornot", OPRL(0x11,0x28), ALL, ARG_OPRL }, - { "xor", OPR(0x11,0x40), ALL, ARG_OPR }, - { "xor", OPRL(0x11,0x40), ALL, ARG_OPRL }, - { "cmovlt", OPR(0x11,0x44), ALL, ARG_OPR }, - { "cmovlt", OPRL(0x11,0x44), ALL, ARG_OPRL }, - { "cmovge", OPR(0x11,0x46), ALL, ARG_OPR }, - { "cmovge", OPRL(0x11,0x46), ALL, ARG_OPRL }, - { "eqv", OPR(0x11,0x48), ALL, ARG_OPR }, - { "eqv", OPRL(0x11,0x48), ALL, ARG_OPRL }, - { "xornot", OPR(0x11,0x48), ALL, ARG_OPR }, /* alias */ - { "xornot", OPRL(0x11,0x48), ALL, ARG_OPRL }, /* alias */ - { "amask", OPR(0x11,0x61), EV56, ARG_OPRZ1 }, /* ev56 */ - { "amask", OPRL(0x11,0x61), EV56, ARG_OPRLZ1 }, /* ev56 */ - { "cmovle", OPR(0x11,0x64), ALL, ARG_OPR }, - { "cmovle", OPRL(0x11,0x64), ALL, ARG_OPRL }, - { "cmovgt", OPR(0x11,0x66), ALL, ARG_OPR }, - { "cmovgt", OPRL(0x11,0x66), ALL, ARG_OPRL }, - { "implver", OPR(0x11,0x6C), ALL, ARG_OPRZ1 }, /* ev56 */ - { "implver", OPRL(0x11,0x6C), ALL, ARG_OPRLZ1 }, /* ev56 */ - - { "mskbl", OPR(0x12,0x02), ALL, ARG_OPR }, - { "mskbl", OPRL(0x12,0x02), ALL, ARG_OPRL }, - { "extbl", OPR(0x12,0x06), ALL, ARG_OPR }, - { "extbl", OPRL(0x12,0x06), ALL, ARG_OPRL }, - { "insbl", OPR(0x12,0x0B), ALL, ARG_OPR }, - { "insbl", OPRL(0x12,0x0B), ALL, ARG_OPRL }, - { "mskwl", OPR(0x12,0x12), ALL, ARG_OPR }, - { "mskwl", OPRL(0x12,0x12), ALL, ARG_OPRL }, - { "extwl", OPR(0x12,0x16), ALL, ARG_OPR }, - { "extwl", OPRL(0x12,0x16), ALL, ARG_OPRL }, - { "inswl", OPR(0x12,0x1B), ALL, ARG_OPR }, - { "inswl", OPRL(0x12,0x1B), ALL, ARG_OPRL }, - { "mskll", OPR(0x12,0x22), ALL, ARG_OPR }, - { "mskll", OPRL(0x12,0x22), ALL, ARG_OPRL }, - { "extll", OPR(0x12,0x26), ALL, ARG_OPR }, - { "extll", OPRL(0x12,0x26), ALL, ARG_OPRL }, - { "insll", OPR(0x12,0x2B), ALL, ARG_OPR }, - { "insll", OPRL(0x12,0x2B), ALL, ARG_OPRL }, - { "zap", OPR(0x12,0x30), ALL, ARG_OPR }, - { "zap", OPRL(0x12,0x30), ALL, ARG_OPRL }, - { "zapnot", OPR(0x12,0x31), ALL, ARG_OPR }, - { "zapnot", OPRL(0x12,0x31), ALL, ARG_OPRL }, - { "mskql", OPR(0x12,0x32), ALL, ARG_OPR }, - { "mskql", OPRL(0x12,0x32), ALL, ARG_OPRL }, - { "srl", OPR(0x12,0x34), ALL, ARG_OPR }, - { "srl", OPRL(0x12,0x34), ALL, ARG_OPRL }, - { "extql", OPR(0x12,0x36), ALL, ARG_OPR }, - { "extql", OPRL(0x12,0x36), ALL, ARG_OPRL }, - { "sll", OPR(0x12,0x39), ALL, ARG_OPR }, - { "sll", OPRL(0x12,0x39), ALL, ARG_OPRL }, - { "insql", OPR(0x12,0x3B), ALL, ARG_OPR }, - { "insql", OPRL(0x12,0x3B), ALL, ARG_OPRL }, - { "sra", OPR(0x12,0x3C), ALL, ARG_OPR }, - { "sra", OPRL(0x12,0x3C), ALL, ARG_OPRL }, - { "mskwh", OPR(0x12,0x52), ALL, ARG_OPR }, - { "mskwh", OPRL(0x12,0x52), ALL, ARG_OPRL }, - { "inswh", OPR(0x12,0x57), ALL, ARG_OPR }, - { "inswh", OPRL(0x12,0x57), ALL, ARG_OPRL }, - { "extwh", OPR(0x12,0x5A), ALL, ARG_OPR }, - { "extwh", OPRL(0x12,0x5A), ALL, ARG_OPRL }, - { "msklh", OPR(0x12,0x62), ALL, ARG_OPR }, - { "msklh", OPRL(0x12,0x62), ALL, ARG_OPRL }, - { "inslh", OPR(0x12,0x67), ALL, ARG_OPR }, - { "inslh", OPRL(0x12,0x67), ALL, ARG_OPRL }, - { "extlh", OPR(0x12,0x6A), ALL, ARG_OPR }, - { "extlh", OPRL(0x12,0x6A), ALL, ARG_OPRL }, - { "mskqh", OPR(0x12,0x72), ALL, ARG_OPR }, - { "mskqh", OPRL(0x12,0x72), ALL, ARG_OPRL }, - { "insqh", OPR(0x12,0x77), ALL, ARG_OPR }, - { "insqh", OPRL(0x12,0x77), ALL, ARG_OPRL }, - { "extqh", OPR(0x12,0x7A), ALL, ARG_OPR }, - { "extqh", OPRL(0x12,0x7A), ALL, ARG_OPRL }, - - { "mull", OPR(0x13,0x00), ALL, ARG_OPR }, - { "mull", OPRL(0x13,0x00), ALL, ARG_OPRL }, - { "mulq", OPR(0x13,0x20), ALL, ARG_OPR }, - { "mulq", OPRL(0x13,0x20), ALL, ARG_OPRL }, - { "umulh", OPR(0x13,0x30), ALL, ARG_OPR }, - { "umulh", OPRL(0x13,0x30), ALL, ARG_OPRL }, - { "mull/v", OPR(0x13,0x40), ALL, ARG_OPR }, - { "mull/v", OPRL(0x13,0x40), ALL, ARG_OPRL }, - { "mulq/v", OPR(0x13,0x60), ALL, ARG_OPR }, - { "mulq/v", OPRL(0x13,0x60), ALL, ARG_OPRL }, - - { "addf/c", FP(0x15,0x000), ALL, ARG_FP }, - { "subf/c", FP(0x15,0x001), ALL, ARG_FP }, - { "mulf/c", FP(0x15,0x002), ALL, ARG_FP }, - { "divf/c", FP(0x15,0x003), ALL, ARG_FP }, - { "cvtdg/c", FP(0x15,0x01E), ALL, ARG_FPZ1 }, - { "addg/c", FP(0x15,0x020), ALL, ARG_FP }, - { "subg/c", FP(0x15,0x021), ALL, ARG_FP }, - { "mulg/c", FP(0x15,0x022), ALL, ARG_FP }, - { "divg/c", FP(0x15,0x023), ALL, ARG_FP }, - { "cvtgf/c", FP(0x15,0x02C), ALL, ARG_FPZ1 }, - { "cvtgd/c", FP(0x15,0x02D), ALL, ARG_FPZ1 }, - { "cvtgq/c", FP(0x15,0x02F), ALL, ARG_FPZ1 }, - { "cvtqf/c", FP(0x15,0x03C), ALL, ARG_FPZ1 }, - { "cvtqg/c", FP(0x15,0x03E), ALL, ARG_FPZ1 }, - { "addf", FP(0x15,0x080), ALL, ARG_FP }, - { "negf", FP(0x15,0x081), ALL, ARG_FPZ1 }, /* pseudo */ - { "subf", FP(0x15,0x081), ALL, ARG_FP }, - { "mulf", FP(0x15,0x082), ALL, ARG_FP }, - { "divf", FP(0x15,0x083), ALL, ARG_FP }, - { "cvtdg", FP(0x15,0x09E), ALL, ARG_FPZ1 }, - { "addg", FP(0x15,0x0A0), ALL, ARG_FP }, - { "negg", FP(0x15,0x0A1), ALL, ARG_FPZ1 }, /* pseudo */ - { "subg", FP(0x15,0x0A1), ALL, ARG_FP }, - { "mulg", FP(0x15,0x0A2), ALL, ARG_FP }, - { "divg", FP(0x15,0x0A3), ALL, ARG_FP }, - { "cmpgeq", FP(0x15,0x0A5), ALL, ARG_FP }, - { "cmpglt", FP(0x15,0x0A6), ALL, ARG_FP }, - { "cmpgle", FP(0x15,0x0A7), ALL, ARG_FP }, - { "cvtgf", FP(0x15,0x0AC), ALL, ARG_FPZ1 }, - { "cvtgd", FP(0x15,0x0AD), ALL, ARG_FPZ1 }, - { "cvtgq", FP(0x15,0x0AF), ALL, ARG_FPZ1 }, - { "cvtqf", FP(0x15,0x0BC), ALL, ARG_FPZ1 }, - { "cvtqg", FP(0x15,0x0BE), ALL, ARG_FPZ1 }, - { "addf/uc", FP(0x15,0x100), ALL, ARG_FP }, - { "subf/uc", FP(0x15,0x101), ALL, ARG_FP }, - { "mulf/uc", FP(0x15,0x102), ALL, ARG_FP }, - { "divf/uc", FP(0x15,0x103), ALL, ARG_FP }, - { "cvtdg/uc", FP(0x15,0x11E), ALL, ARG_FPZ1 }, - { "addg/uc", FP(0x15,0x120), ALL, ARG_FP }, - { "subg/uc", FP(0x15,0x121), ALL, ARG_FP }, - { "mulg/uc", FP(0x15,0x122), ALL, ARG_FP }, - { "divg/uc", FP(0x15,0x123), ALL, ARG_FP }, - { "cvtgf/uc", FP(0x15,0x12C), ALL, ARG_FPZ1 }, - { "cvtgd/uc", FP(0x15,0x12D), ALL, ARG_FPZ1 }, - { "cvtgq/vc", FP(0x15,0x12F), ALL, ARG_FPZ1 }, - { "addf/u", FP(0x15,0x180), ALL, ARG_FP }, - { "subf/u", FP(0x15,0x181), ALL, ARG_FP }, - { "mulf/u", FP(0x15,0x182), ALL, ARG_FP }, - { "divf/u", FP(0x15,0x183), ALL, ARG_FP }, - { "cvtdg/u", FP(0x15,0x19E), ALL, ARG_FPZ1 }, - { "addg/u", FP(0x15,0x1A0), ALL, ARG_FP }, - { "subg/u", FP(0x15,0x1A1), ALL, ARG_FP }, - { "mulg/u", FP(0x15,0x1A2), ALL, ARG_FP }, - { "divg/u", FP(0x15,0x1A3), ALL, ARG_FP }, - { "cvtgf/u", FP(0x15,0x1AC), ALL, ARG_FPZ1 }, - { "cvtgd/u", FP(0x15,0x1AD), ALL, ARG_FPZ1 }, - { "cvtgq/v", FP(0x15,0x1AF), ALL, ARG_FPZ1 }, - { "addf/sc", FP(0x15,0x400), ALL, ARG_FP }, - { "subf/sc", FP(0x15,0x401), ALL, ARG_FP }, - { "mulf/sc", FP(0x15,0x402), ALL, ARG_FP }, - { "divf/sc", FP(0x15,0x403), ALL, ARG_FP }, - { "cvtdg/sc", FP(0x15,0x41E), ALL, ARG_FPZ1 }, - { "addg/sc", FP(0x15,0x420), ALL, ARG_FP }, - { "subg/sc", FP(0x15,0x421), ALL, ARG_FP }, - { "mulg/sc", FP(0x15,0x422), ALL, ARG_FP }, - { "divg/sc", FP(0x15,0x423), ALL, ARG_FP }, - { "cvtgf/sc", FP(0x15,0x42C), ALL, ARG_FPZ1 }, - { "cvtgd/sc", FP(0x15,0x42D), ALL, ARG_FPZ1 }, - { "cvtgq/sc", FP(0x15,0x42F), ALL, ARG_FPZ1 }, - { "addf/s", FP(0x15,0x480), ALL, ARG_FP }, - { "negf/s", FP(0x15,0x481), ALL, ARG_FPZ1 }, /* pseudo */ - { "subf/s", FP(0x15,0x481), ALL, ARG_FP }, - { "mulf/s", FP(0x15,0x482), ALL, ARG_FP }, - { "divf/s", FP(0x15,0x483), ALL, ARG_FP }, - { "cvtdg/s", FP(0x15,0x49E), ALL, ARG_FPZ1 }, - { "addg/s", FP(0x15,0x4A0), ALL, ARG_FP }, - { "negg/s", FP(0x15,0x4A1), ALL, ARG_FPZ1 }, /* pseudo */ - { "subg/s", FP(0x15,0x4A1), ALL, ARG_FP }, - { "mulg/s", FP(0x15,0x4A2), ALL, ARG_FP }, - { "divg/s", FP(0x15,0x4A3), ALL, ARG_FP }, - { "cmpgeq/s", FP(0x15,0x4A5), ALL, ARG_FP }, - { "cmpglt/s", FP(0x15,0x4A6), ALL, ARG_FP }, - { "cmpgle/s", FP(0x15,0x4A7), ALL, ARG_FP }, - { "cvtgf/s", FP(0x15,0x4AC), ALL, ARG_FPZ1 }, - { "cvtgd/s", FP(0x15,0x4AD), ALL, ARG_FPZ1 }, - { "cvtgq/s", FP(0x15,0x4AF), ALL, ARG_FPZ1 }, - { "addf/suc", FP(0x15,0x500), ALL, ARG_FP }, - { "subf/suc", FP(0x15,0x501), ALL, ARG_FP }, - { "mulf/suc", FP(0x15,0x502), ALL, ARG_FP }, - { "divf/suc", FP(0x15,0x503), ALL, ARG_FP }, - { "cvtdg/suc", FP(0x15,0x51E), ALL, ARG_FPZ1 }, - { "addg/suc", FP(0x15,0x520), ALL, ARG_FP }, - { "subg/suc", FP(0x15,0x521), ALL, ARG_FP }, - { "mulg/suc", FP(0x15,0x522), ALL, ARG_FP }, - { "divg/suc", FP(0x15,0x523), ALL, ARG_FP }, - { "cvtgf/suc", FP(0x15,0x52C), ALL, ARG_FPZ1 }, - { "cvtgd/suc", FP(0x15,0x52D), ALL, ARG_FPZ1 }, - { "cvtgq/svc", FP(0x15,0x52F), ALL, ARG_FPZ1 }, - { "addf/su", FP(0x15,0x580), ALL, ARG_FP }, - { "subf/su", FP(0x15,0x581), ALL, ARG_FP }, - { "mulf/su", FP(0x15,0x582), ALL, ARG_FP }, - { "divf/su", FP(0x15,0x583), ALL, ARG_FP }, - { "cvtdg/su", FP(0x15,0x59E), ALL, ARG_FPZ1 }, - { "addg/su", FP(0x15,0x5A0), ALL, ARG_FP }, - { "subg/su", FP(0x15,0x5A1), ALL, ARG_FP }, - { "mulg/su", FP(0x15,0x5A2), ALL, ARG_FP }, - { "divg/su", FP(0x15,0x5A3), ALL, ARG_FP }, - { "cvtgf/su", FP(0x15,0x5AC), ALL, ARG_FPZ1 }, - { "cvtgd/su", FP(0x15,0x5AD), ALL, ARG_FPZ1 }, - { "cvtgq/sv", FP(0x15,0x5AF), ALL, ARG_FPZ1 }, - - { "adds/c", FP(0x16,0x000), ALL, ARG_FP }, - { "subs/c", FP(0x16,0x001), ALL, ARG_FP }, - { "muls/c", FP(0x16,0x002), ALL, ARG_FP }, - { "divs/c", FP(0x16,0x003), ALL, ARG_FP }, - { "addt/c", FP(0x16,0x020), ALL, ARG_FP }, - { "subt/c", FP(0x16,0x021), ALL, ARG_FP }, - { "mult/c", FP(0x16,0x022), ALL, ARG_FP }, - { "divt/c", FP(0x16,0x023), ALL, ARG_FP }, - { "cvtts/c", FP(0x16,0x02C), ALL, ARG_FPZ1 }, - { "cvttq/c", FP(0x16,0x02F), ALL, ARG_FPZ1 }, - { "cvtqs/c", FP(0x16,0x03C), ALL, ARG_FPZ1 }, - { "cvtqt/c", FP(0x16,0x03E), ALL, ARG_FPZ1 }, - { "adds/m", FP(0x16,0x040), ALL, ARG_FP }, - { "subs/m", FP(0x16,0x041), ALL, ARG_FP }, - { "muls/m", FP(0x16,0x042), ALL, ARG_FP }, - { "divs/m", FP(0x16,0x043), ALL, ARG_FP }, - { "addt/m", FP(0x16,0x060), ALL, ARG_FP }, - { "subt/m", FP(0x16,0x061), ALL, ARG_FP }, - { "mult/m", FP(0x16,0x062), ALL, ARG_FP }, - { "divt/m", FP(0x16,0x063), ALL, ARG_FP }, - { "cvtts/m", FP(0x16,0x06C), ALL, ARG_FPZ1 }, - { "cvttq/m", FP(0x16,0x06F), ALL, ARG_FPZ1 }, - { "cvtqs/m", FP(0x16,0x07C), ALL, ARG_FPZ1 }, - { "cvtqt/m", FP(0x16,0x07E), ALL, ARG_FPZ1 }, - { "adds", FP(0x16,0x080), ALL, ARG_FP }, - { "negs", FP(0x16,0x081), ALL, ARG_FPZ1 }, /* pseudo */ - { "subs", FP(0x16,0x081), ALL, ARG_FP }, - { "muls", FP(0x16,0x082), ALL, ARG_FP }, - { "divs", FP(0x16,0x083), ALL, ARG_FP }, - { "addt", FP(0x16,0x0A0), ALL, ARG_FP }, - { "negt", FP(0x16,0x0A1), ALL, ARG_FPZ1 }, /* pseudo */ - { "subt", FP(0x16,0x0A1), ALL, ARG_FP }, - { "mult", FP(0x16,0x0A2), ALL, ARG_FP }, - { "divt", FP(0x16,0x0A3), ALL, ARG_FP }, - { "cmptun", FP(0x16,0x0A4), ALL, ARG_FP }, - { "cmpteq", FP(0x16,0x0A5), ALL, ARG_FP }, - { "cmptlt", FP(0x16,0x0A6), ALL, ARG_FP }, - { "cmptle", FP(0x16,0x0A7), ALL, ARG_FP }, - { "cvtts", FP(0x16,0x0AC), ALL, ARG_FPZ1 }, - { "cvttq", FP(0x16,0x0AF), ALL, ARG_FPZ1 }, - { "cvtqs", FP(0x16,0x0BC), ALL, ARG_FPZ1 }, - { "cvtqt", FP(0x16,0x0BE), ALL, ARG_FPZ1 }, - { "adds/d", FP(0x16,0x0C0), ALL, ARG_FP }, - { "subs/d", FP(0x16,0x0C1), ALL, ARG_FP }, - { "muls/d", FP(0x16,0x0C2), ALL, ARG_FP }, - { "divs/d", FP(0x16,0x0C3), ALL, ARG_FP }, - { "addt/d", FP(0x16,0x0E0), ALL, ARG_FP }, - { "subt/d", FP(0x16,0x0E1), ALL, ARG_FP }, - { "mult/d", FP(0x16,0x0E2), ALL, ARG_FP }, - { "divt/d", FP(0x16,0x0E3), ALL, ARG_FP }, - { "cvtts/d", FP(0x16,0x0EC), ALL, ARG_FPZ1 }, - { "cvttq/d", FP(0x16,0x0EF), ALL, ARG_FPZ1 }, - { "cvtqs/d", FP(0x16,0x0FC), ALL, ARG_FPZ1 }, - { "cvtqt/d", FP(0x16,0x0FE), ALL, ARG_FPZ1 }, - { "adds/uc", FP(0x16,0x100), ALL, ARG_FP }, - { "subs/uc", FP(0x16,0x101), ALL, ARG_FP }, - { "muls/uc", FP(0x16,0x102), ALL, ARG_FP }, - { "divs/uc", FP(0x16,0x103), ALL, ARG_FP }, - { "addt/uc", FP(0x16,0x120), ALL, ARG_FP }, - { "subt/uc", FP(0x16,0x121), ALL, ARG_FP }, - { "mult/uc", FP(0x16,0x122), ALL, ARG_FP }, - { "divt/uc", FP(0x16,0x123), ALL, ARG_FP }, - { "cvtts/uc", FP(0x16,0x12C), ALL, ARG_FPZ1 }, - { "cvttq/vc", FP(0x16,0x12F), ALL, ARG_FPZ1 }, - { "adds/um", FP(0x16,0x140), ALL, ARG_FP }, - { "subs/um", FP(0x16,0x141), ALL, ARG_FP }, - { "muls/um", FP(0x16,0x142), ALL, ARG_FP }, - { "divs/um", FP(0x16,0x143), ALL, ARG_FP }, - { "addt/um", FP(0x16,0x160), ALL, ARG_FP }, - { "subt/um", FP(0x16,0x161), ALL, ARG_FP }, - { "mult/um", FP(0x16,0x162), ALL, ARG_FP }, - { "divt/um", FP(0x16,0x163), ALL, ARG_FP }, - { "cvtts/um", FP(0x16,0x16C), ALL, ARG_FPZ1 }, - { "cvttq/um", FP(0x16,0x16F), ALL, ARG_FPZ1 }, - { "cvtqs/um", FP(0x16,0x17C), ALL, ARG_FPZ1 }, - { "adds/u", FP(0x16,0x180), ALL, ARG_FP }, - { "subs/u", FP(0x16,0x181), ALL, ARG_FP }, - { "muls/u", FP(0x16,0x182), ALL, ARG_FP }, - { "divs/u", FP(0x16,0x183), ALL, ARG_FP }, - { "addt/u", FP(0x16,0x1A0), ALL, ARG_FP }, - { "subt/u", FP(0x16,0x1A1), ALL, ARG_FP }, - { "mult/u", FP(0x16,0x1A2), ALL, ARG_FP }, - { "divt/u", FP(0x16,0x1A3), ALL, ARG_FP }, - { "cvtts/u", FP(0x16,0x1AC), ALL, ARG_FPZ1 }, - { "cvttq/v", FP(0x16,0x1AF), ALL, ARG_FPZ1 }, - { "adds/ud", FP(0x16,0x1C0), ALL, ARG_FP }, - { "subs/ud", FP(0x16,0x1C1), ALL, ARG_FP }, - { "muls/ud", FP(0x16,0x1C2), ALL, ARG_FP }, - { "divs/ud", FP(0x16,0x1C3), ALL, ARG_FP }, - { "addt/ud", FP(0x16,0x1E0), ALL, ARG_FP }, - { "subt/ud", FP(0x16,0x1E1), ALL, ARG_FP }, - { "mult/ud", FP(0x16,0x1E2), ALL, ARG_FP }, - { "divt/ud", FP(0x16,0x1E3), ALL, ARG_FP }, - { "cvtts/ud", FP(0x16,0x1EC), ALL, ARG_FPZ1 }, - { "cvttq/ud", FP(0x16,0x1EF), ALL, ARG_FPZ1 }, - { "cvtst", FP(0x16,0x2AC), ALL, ARG_FPZ1 }, - { "adds/suc", FP(0x16,0x500), ALL, ARG_FP }, - { "subs/suc", FP(0x16,0x501), ALL, ARG_FP }, - { "muls/suc", FP(0x16,0x502), ALL, ARG_FP }, - { "divs/suc", FP(0x16,0x503), ALL, ARG_FP }, - { "addt/suc", FP(0x16,0x520), ALL, ARG_FP }, - { "subt/suc", FP(0x16,0x521), ALL, ARG_FP }, - { "mult/suc", FP(0x16,0x522), ALL, ARG_FP }, - { "divt/suc", FP(0x16,0x523), ALL, ARG_FP }, - { "cvtts/suc", FP(0x16,0x52C), ALL, ARG_FPZ1 }, - { "cvttq/svc", FP(0x16,0x52F), ALL, ARG_FPZ1 }, - { "adds/sum", FP(0x16,0x540), ALL, ARG_FP }, - { "subs/sum", FP(0x16,0x541), ALL, ARG_FP }, - { "muls/sum", FP(0x16,0x542), ALL, ARG_FP }, - { "divs/sum", FP(0x16,0x543), ALL, ARG_FP }, - { "addt/sum", FP(0x16,0x560), ALL, ARG_FP }, - { "subt/sum", FP(0x16,0x561), ALL, ARG_FP }, - { "mult/sum", FP(0x16,0x562), ALL, ARG_FP }, - { "divt/sum", FP(0x16,0x563), ALL, ARG_FP }, - { "cvtts/sum", FP(0x16,0x56C), ALL, ARG_FPZ1 }, - { "cvttq/sum", FP(0x16,0x56F), ALL, ARG_FPZ1 }, - { "cvtqs/sum", FP(0x16,0x57C), ALL, ARG_FPZ1 }, - { "adds/su", FP(0x16,0x580), ALL, ARG_FP }, - { "negs/su", FP(0x16,0x581), ALL, ARG_FPZ1 }, /* pseudo */ - { "subs/su", FP(0x16,0x581), ALL, ARG_FP }, - { "muls/su", FP(0x16,0x582), ALL, ARG_FP }, - { "divs/su", FP(0x16,0x583), ALL, ARG_FP }, - { "addt/su", FP(0x16,0x5A0), ALL, ARG_FP }, - { "negt/su", FP(0x16,0x5A1), ALL, ARG_FPZ1 }, /* pseudo */ - { "subt/su", FP(0x16,0x5A1), ALL, ARG_FP }, - { "mult/su", FP(0x16,0x5A2), ALL, ARG_FP }, - { "divt/su", FP(0x16,0x5A3), ALL, ARG_FP }, - { "cmptun/su", FP(0x16,0x5A4), ALL, ARG_FP }, - { "cmpteq/su", FP(0x16,0x5A5), ALL, ARG_FP }, - { "cmptlt/su", FP(0x16,0x5A6), ALL, ARG_FP }, - { "cmptle/su", FP(0x16,0x5A7), ALL, ARG_FP }, - { "cvtts/su", FP(0x16,0x5AC), ALL, ARG_FPZ1 }, - { "cvttq/sv", FP(0x16,0x5AF), ALL, ARG_FPZ1 }, - { "adds/sud", FP(0x16,0x5C0), ALL, ARG_FP }, - { "subs/sud", FP(0x16,0x5C1), ALL, ARG_FP }, - { "muls/sud", FP(0x16,0x5C2), ALL, ARG_FP }, - { "divs/sud", FP(0x16,0x5C3), ALL, ARG_FP }, - { "addt/sud", FP(0x16,0x5E0), ALL, ARG_FP }, - { "subt/sud", FP(0x16,0x5E1), ALL, ARG_FP }, - { "mult/sud", FP(0x16,0x5E2), ALL, ARG_FP }, - { "divt/sud", FP(0x16,0x5E3), ALL, ARG_FP }, - { "cvtts/sud", FP(0x16,0x5EC), ALL, ARG_FPZ1 }, - { "cvttq/sud", FP(0x16,0x5EF), ALL, ARG_FPZ1 }, - { "cvtst/s", FP(0x16,0x6AC), ALL, ARG_FPZ1 }, - { "adds/suic", FP(0x16,0x700), ALL, ARG_FP }, - { "subs/suic", FP(0x16,0x701), ALL, ARG_FP }, - { "muls/suic", FP(0x16,0x702), ALL, ARG_FP }, - { "divs/suic", FP(0x16,0x703), ALL, ARG_FP }, - { "addt/suic", FP(0x16,0x720), ALL, ARG_FP }, - { "subt/suic", FP(0x16,0x721), ALL, ARG_FP }, - { "mult/suic", FP(0x16,0x722), ALL, ARG_FP }, - { "divt/suic", FP(0x16,0x723), ALL, ARG_FP }, - { "cvtts/suic", FP(0x16,0x72C), ALL, ARG_FPZ1 }, - { "cvttq/svic", FP(0x16,0x72F), ALL, ARG_FPZ1 }, - { "cvtqs/suic", FP(0x16,0x73C), ALL, ARG_FPZ1 }, - { "cvtqt/suic", FP(0x16,0x73E), ALL, ARG_FPZ1 }, - { "adds/suim", FP(0x16,0x740), ALL, ARG_FP }, - { "subs/suim", FP(0x16,0x741), ALL, ARG_FP }, - { "muls/suim", FP(0x16,0x742), ALL, ARG_FP }, - { "divs/suim", FP(0x16,0x743), ALL, ARG_FP }, - { "addt/suim", FP(0x16,0x760), ALL, ARG_FP }, - { "subt/suim", FP(0x16,0x761), ALL, ARG_FP }, - { "mult/suim", FP(0x16,0x762), ALL, ARG_FP }, - { "divt/suim", FP(0x16,0x763), ALL, ARG_FP }, - { "cvtts/suim", FP(0x16,0x76C), ALL, ARG_FPZ1 }, - { "cvttq/suim", FP(0x16,0x76F), ALL, ARG_FPZ1 }, - { "cvtqs/suim", FP(0x16,0x77C), ALL, ARG_FPZ1 }, - { "cvtqt/suim", FP(0x16,0x77E), ALL, ARG_FPZ1 }, - { "adds/sui", FP(0x16,0x780), ALL, ARG_FP }, - { "negs/sui", FP(0x16,0x781), ALL, ARG_FPZ1 }, /* pseudo */ - { "subs/sui", FP(0x16,0x781), ALL, ARG_FP }, - { "muls/sui", FP(0x16,0x782), ALL, ARG_FP }, - { "divs/sui", FP(0x16,0x783), ALL, ARG_FP }, - { "addt/sui", FP(0x16,0x7A0), ALL, ARG_FP }, - { "negt/sui", FP(0x16,0x7A1), ALL, ARG_FPZ1 }, /* pseudo */ - { "subt/sui", FP(0x16,0x7A1), ALL, ARG_FP }, - { "mult/sui", FP(0x16,0x7A2), ALL, ARG_FP }, - { "divt/sui", FP(0x16,0x7A3), ALL, ARG_FP }, - { "cvtts/sui", FP(0x16,0x7AC), ALL, ARG_FPZ1 }, - { "cvttq/svi", FP(0x16,0x7AF), ALL, ARG_FPZ1 }, - { "cvtqs/sui", FP(0x16,0x7BC), ALL, ARG_FPZ1 }, - { "cvtqt/sui", FP(0x16,0x7BE), ALL, ARG_FPZ1 }, - { "adds/suid", FP(0x16,0x7C0), ALL, ARG_FP }, - { "subs/suid", FP(0x16,0x7C1), ALL, ARG_FP }, - { "muls/suid", FP(0x16,0x7C2), ALL, ARG_FP }, - { "divs/suid", FP(0x16,0x7C3), ALL, ARG_FP }, - { "addt/suid", FP(0x16,0x7E0), ALL, ARG_FP }, - { "subt/suid", FP(0x16,0x7E1), ALL, ARG_FP }, - { "mult/suid", FP(0x16,0x7E2), ALL, ARG_FP }, - { "divt/suid", FP(0x16,0x7E3), ALL, ARG_FP }, - { "cvtts/suid", FP(0x16,0x7EC), ALL, ARG_FPZ1 }, - { "cvttq/suid", FP(0x16,0x7EF), ALL, ARG_FPZ1 }, - { "cvtqs/suid", FP(0x16,0x7FC), ALL, ARG_FPZ1 }, - { "cvtqt/suid", FP(0x16,0x7FE), ALL, ARG_FPZ1 }, - - { "cvtlq", FP(0x17,0x010), ALL, ARG_FPZ1 }, - { "fnop", FP(0x17,0x020), ALL, { ZA, ZB, ZC } }, /* pseudo */ - { "fclr", FP(0x17,0x020), ALL, { ZA, ZB, FC } }, /* pseudo */ - { "fabs", FP(0x17,0x020), ALL, ARG_FPZ1 }, /* pseudo */ - { "fmov", FP(0x17,0x020), ALL, { FA, RBA, FC } }, /* pseudo */ - { "cpys", FP(0x17,0x020), ALL, ARG_FP }, - { "fneg", FP(0x17,0x021), ALL, { FA, RBA, FC } }, /* pseudo */ - { "cpysn", FP(0x17,0x021), ALL, ARG_FP }, - { "cpyse", FP(0x17,0x022), ALL, ARG_FP }, - { "mt_fpcr", FP(0x17,0x024), ALL, { FA, RBA, RCA } }, - { "mf_fpcr", FP(0x17,0x025), ALL, { FA, RBA, RCA } }, - { "fcmoveq", FP(0x17,0x02A), ALL, ARG_FP }, - { "fcmovne", FP(0x17,0x02B), ALL, ARG_FP }, - { "fcmovlt", FP(0x17,0x02C), ALL, ARG_FP }, - { "fcmovge", FP(0x17,0x02D), ALL, ARG_FP }, - { "fcmovle", FP(0x17,0x02E), ALL, ARG_FP }, - { "fcmovgt", FP(0x17,0x02F), ALL, ARG_FP }, - { "cvtql", FP(0x17,0x030), ALL, ARG_FPZ1 }, - { "cvtql/v", FP(0x17,0x130), ALL, ARG_FPZ1 }, - { "cvtql/sv", FP(0x17,0x530), ALL, ARG_FPZ1 }, - - { "trapb", MFC(0x18,0x0000), ALL, ARG_NONE }, - { "draint", MFC(0x18,0x0000), ALL, ARG_NONE }, /* alias */ - { "excb", MFC(0x18,0x0400), ALL, ARG_NONE }, - { "mb", MFC(0x18,0x4000), ALL, ARG_NONE }, - { "wmb", MFC(0x18,0x4400), ALL, ARG_NONE }, - { "fetch", MFC(0x18,0x8000), ALL, { MDISP, RB } }, - { "fetch_m", MFC(0x18,0xA000), ALL, { MDISP, RB } }, - { "rpcc", MFC(0x18,0xC000), ALL, { RA } }, - { "rc", MFC(0x18,0xE000), ALL, { RA } }, - { "rs", MFC(0x18,0xF000), ALL, { RA } }, - - { "hw_mfpr", OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, - { "hw_mfpr", OP(0x19), OP_MASK, EV5x, { RA, RBA, EV5HWINDEX } }, - { "hw_mfpr/i", OPR(0x19,0x01), EV4, ARG_EV4HWMPR }, - { "hw_mfpr/a", OPR(0x19,0x02), EV4, ARG_EV4HWMPR }, - { "hw_mfpr/ai", OPR(0x19,0x03), EV4, ARG_EV4HWMPR }, - { "hw_mfpr/p", OPR(0x19,0x04), EV4, ARG_EV4HWMPR }, - { "hw_mfpr/pi", OPR(0x19,0x05), EV4, ARG_EV4HWMPR }, - { "hw_mfpr/pa", OPR(0x19,0x06), EV4, ARG_EV4HWMPR }, - { "hw_mfpr/pai", OPR(0x19,0x07), EV4, ARG_EV4HWMPR }, - { "pal19", PCD(0x19), ALL, ARG_PCD }, - - { "jmp", MBR(0x1A,0), ALL, { RA, CPRB, JMPHINT } }, - { "jsr", MBR(0x1A,1), ALL, { RA, CPRB, JMPHINT } }, - { "ret", MBR(0x1A,2), ALL, { RA, CPRB, RETHINT } }, - { "jcr", MBR(0x1A,3), ALL, { RA, CPRB, RETHINT } }, /* alias */ - { "jsr_coroutine", MBR(0x1A,3), ALL, { RA, CPRB, RETHINT } }, - - { "hw_ldl", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM }, - { "hw_ldl", EV5HWMEM(0x1B,0x00), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM }, - { "hw_ldl/a", EV5HWMEM(0x1B,0x10), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/al", EV5HWMEM(0x1B,0x11), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM }, - { "hw_ldl/av", EV5HWMEM(0x1B,0x12), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/avl", EV5HWMEM(0x1B,0x13), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/aw", EV5HWMEM(0x1B,0x18), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/awl", EV5HWMEM(0x1B,0x19), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/awv", EV5HWMEM(0x1B,0x1a), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/awvl", EV5HWMEM(0x1B,0x1b), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/l", EV5HWMEM(0x1B,0x01), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM }, - { "hw_ldl/p", EV5HWMEM(0x1B,0x20), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM }, - { "hw_ldl/pa", EV5HWMEM(0x1B,0x30), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/pal", EV5HWMEM(0x1B,0x31), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM }, - { "hw_ldl/pav", EV5HWMEM(0x1B,0x32), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/pavl", EV5HWMEM(0x1B,0x33), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/paw", EV5HWMEM(0x1B,0x38), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/pawl", EV5HWMEM(0x1B,0x39), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/pawv", EV5HWMEM(0x1B,0x3a), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/pawvl", EV5HWMEM(0x1B,0x3b), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/pl", EV5HWMEM(0x1B,0x21), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM }, - { "hw_ldl/pv", EV5HWMEM(0x1B,0x22), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/pvl", EV5HWMEM(0x1B,0x23), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/pw", EV5HWMEM(0x1B,0x28), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/pwl", EV5HWMEM(0x1B,0x29), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/pwv", EV5HWMEM(0x1B,0x2a), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/pwvl", EV5HWMEM(0x1B,0x2b), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM }, - { "hw_ldl/v", EV5HWMEM(0x1B,0x02), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/vl", EV5HWMEM(0x1B,0x03), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/w", EV5HWMEM(0x1B,0x08), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/wl", EV5HWMEM(0x1B,0x09), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/wv", EV5HWMEM(0x1B,0x0a), EV5x, ARG_EV5HWMEM }, - { "hw_ldl/wvl", EV5HWMEM(0x1B,0x0b), EV5x, ARG_EV5HWMEM }, - { "hw_ldl_l", EV5HWMEM(0x1B,0x01), EV5x, ARG_EV5HWMEM }, - { "hw_ldl_l/a", EV5HWMEM(0x1B,0x11), EV5x, ARG_EV5HWMEM }, - { "hw_ldl_l/av", EV5HWMEM(0x1B,0x13), EV5x, ARG_EV5HWMEM }, - { "hw_ldl_l/aw", EV5HWMEM(0x1B,0x19), EV5x, ARG_EV5HWMEM }, - { "hw_ldl_l/awv", EV5HWMEM(0x1B,0x1b), EV5x, ARG_EV5HWMEM }, - { "hw_ldl_l/p", EV5HWMEM(0x1B,0x21), EV5x, ARG_EV5HWMEM }, - { "hw_ldl_l/pa", EV5HWMEM(0x1B,0x31), EV5x, ARG_EV5HWMEM }, - { "hw_ldl_l/pav", EV5HWMEM(0x1B,0x33), EV5x, ARG_EV5HWMEM }, - { "hw_ldl_l/paw", EV5HWMEM(0x1B,0x39), EV5x, ARG_EV5HWMEM }, - { "hw_ldl_l/pawv", EV5HWMEM(0x1B,0x3b), EV5x, ARG_EV5HWMEM }, - { "hw_ldl_l/pv", EV5HWMEM(0x1B,0x23), EV5x, ARG_EV5HWMEM }, - { "hw_ldl_l/pw", EV5HWMEM(0x1B,0x29), EV5x, ARG_EV5HWMEM }, - { "hw_ldl_l/pwv", EV5HWMEM(0x1B,0x2b), EV5x, ARG_EV5HWMEM }, - { "hw_ldl_l/v", EV5HWMEM(0x1B,0x03), EV5x, ARG_EV5HWMEM }, - { "hw_ldl_l/w", EV5HWMEM(0x1B,0x09), EV5x, ARG_EV5HWMEM }, - { "hw_ldl_l/wv", EV5HWMEM(0x1B,0x0b), EV5x, ARG_EV5HWMEM }, - { "hw_ldq", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM }, - { "hw_ldq", EV5HWMEM(0x1B,0x04), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/a", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM }, - { "hw_ldq/a", EV5HWMEM(0x1B,0x14), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/al", EV5HWMEM(0x1B,0x15), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/ar", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM }, - { "hw_ldq/av", EV5HWMEM(0x1B,0x16), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/avl", EV5HWMEM(0x1B,0x17), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/aw", EV5HWMEM(0x1B,0x1c), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/awl", EV5HWMEM(0x1B,0x1d), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/awv", EV5HWMEM(0x1B,0x1e), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/awvl", EV5HWMEM(0x1B,0x1f), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/l", EV5HWMEM(0x1B,0x05), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/p", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM }, - { "hw_ldq/p", EV5HWMEM(0x1B,0x24), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/pa", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM }, - { "hw_ldq/pa", EV5HWMEM(0x1B,0x34), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/pal", EV5HWMEM(0x1B,0x35), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/par", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM }, - { "hw_ldq/pav", EV5HWMEM(0x1B,0x36), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/pavl", EV5HWMEM(0x1B,0x37), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/paw", EV5HWMEM(0x1B,0x3c), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/pawl", EV5HWMEM(0x1B,0x3d), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/pawv", EV5HWMEM(0x1B,0x3e), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/pawvl", EV5HWMEM(0x1B,0x3f), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/pl", EV5HWMEM(0x1B,0x25), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/pr", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM }, - { "hw_ldq/pv", EV5HWMEM(0x1B,0x26), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/pvl", EV5HWMEM(0x1B,0x27), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/pw", EV5HWMEM(0x1B,0x2c), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/pwl", EV5HWMEM(0x1B,0x2d), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/pwv", EV5HWMEM(0x1B,0x2e), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/pwvl", EV5HWMEM(0x1B,0x2f), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/r", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM }, - { "hw_ldq/v", EV5HWMEM(0x1B,0x06), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/vl", EV5HWMEM(0x1B,0x07), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/w", EV5HWMEM(0x1B,0x0c), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/wl", EV5HWMEM(0x1B,0x0d), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/wv", EV5HWMEM(0x1B,0x0e), EV5x, ARG_EV5HWMEM }, - { "hw_ldq/wvl", EV5HWMEM(0x1B,0x0f), EV5x, ARG_EV5HWMEM }, - { "hw_ldq_l", EV5HWMEM(0x1B,0x05), EV5x, ARG_EV5HWMEM }, - { "hw_ldq_l/a", EV5HWMEM(0x1B,0x15), EV5x, ARG_EV5HWMEM }, - { "hw_ldq_l/av", EV5HWMEM(0x1B,0x17), EV5x, ARG_EV5HWMEM }, - { "hw_ldq_l/aw", EV5HWMEM(0x1B,0x1d), EV5x, ARG_EV5HWMEM }, - { "hw_ldq_l/awv", EV5HWMEM(0x1B,0x1f), EV5x, ARG_EV5HWMEM }, - { "hw_ldq_l/p", EV5HWMEM(0x1B,0x25), EV5x, ARG_EV5HWMEM }, - { "hw_ldq_l/pa", EV5HWMEM(0x1B,0x35), EV5x, ARG_EV5HWMEM }, - { "hw_ldq_l/pav", EV5HWMEM(0x1B,0x37), EV5x, ARG_EV5HWMEM }, - { "hw_ldq_l/paw", EV5HWMEM(0x1B,0x3d), EV5x, ARG_EV5HWMEM }, - { "hw_ldq_l/pawv", EV5HWMEM(0x1B,0x3f), EV5x, ARG_EV5HWMEM }, - { "hw_ldq_l/pv", EV5HWMEM(0x1B,0x27), EV5x, ARG_EV5HWMEM }, - { "hw_ldq_l/pw", EV5HWMEM(0x1B,0x2d), EV5x, ARG_EV5HWMEM }, - { "hw_ldq_l/pwv", EV5HWMEM(0x1B,0x2f), EV5x, ARG_EV5HWMEM }, - { "hw_ldq_l/v", EV5HWMEM(0x1B,0x07), EV5x, ARG_EV5HWMEM }, - { "hw_ldq_l/w", EV5HWMEM(0x1B,0x0d), EV5x, ARG_EV5HWMEM }, - { "hw_ldq_l/wv", EV5HWMEM(0x1B,0x0f), EV5x, ARG_EV5HWMEM }, - { "hw_ld", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM }, - { "hw_ld", EV5HWMEM(0x1B,0x00), EV5x, ARG_EV5HWMEM }, - { "hw_ld/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM }, - { "hw_ld/a", EV5HWMEM(0x1B,0x10), EV5x, ARG_EV5HWMEM }, - { "hw_ld/al", EV5HWMEM(0x1B,0x11), EV5x, ARG_EV5HWMEM }, - { "hw_ld/aq", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM }, - { "hw_ld/aq", EV5HWMEM(0x1B,0x14), EV5x, ARG_EV5HWMEM }, - { "hw_ld/aql", EV5HWMEM(0x1B,0x15), EV5x, ARG_EV5HWMEM }, - { "hw_ld/aqv", EV5HWMEM(0x1B,0x16), EV5x, ARG_EV5HWMEM }, - { "hw_ld/aqvl", EV5HWMEM(0x1B,0x17), EV5x, ARG_EV5HWMEM }, - { "hw_ld/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM }, - { "hw_ld/arq", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM }, - { "hw_ld/av", EV5HWMEM(0x1B,0x12), EV5x, ARG_EV5HWMEM }, - { "hw_ld/avl", EV5HWMEM(0x1B,0x13), EV5x, ARG_EV5HWMEM }, - { "hw_ld/aw", EV5HWMEM(0x1B,0x18), EV5x, ARG_EV5HWMEM }, - { "hw_ld/awl", EV5HWMEM(0x1B,0x19), EV5x, ARG_EV5HWMEM }, - { "hw_ld/awq", EV5HWMEM(0x1B,0x1c), EV5x, ARG_EV5HWMEM }, - { "hw_ld/awql", EV5HWMEM(0x1B,0x1d), EV5x, ARG_EV5HWMEM }, - { "hw_ld/awqv", EV5HWMEM(0x1B,0x1e), EV5x, ARG_EV5HWMEM }, - { "hw_ld/awqvl", EV5HWMEM(0x1B,0x1f), EV5x, ARG_EV5HWMEM }, - { "hw_ld/awv", EV5HWMEM(0x1B,0x1a), EV5x, ARG_EV5HWMEM }, - { "hw_ld/awvl", EV5HWMEM(0x1B,0x1b), EV5x, ARG_EV5HWMEM }, - { "hw_ld/l", EV5HWMEM(0x1B,0x01), EV5x, ARG_EV5HWMEM }, - { "hw_ld/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM }, - { "hw_ld/p", EV5HWMEM(0x1B,0x20), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM }, - { "hw_ld/pa", EV5HWMEM(0x1B,0x30), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pal", EV5HWMEM(0x1B,0x31), EV5x, ARG_EV5HWMEM }, - { "hw_ld/paq", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM }, - { "hw_ld/paq", EV5HWMEM(0x1B,0x34), EV5x, ARG_EV5HWMEM }, - { "hw_ld/paql", EV5HWMEM(0x1B,0x35), EV5x, ARG_EV5HWMEM }, - { "hw_ld/paqv", EV5HWMEM(0x1B,0x36), EV5x, ARG_EV5HWMEM }, - { "hw_ld/paqvl", EV5HWMEM(0x1B,0x37), EV5x, ARG_EV5HWMEM }, - { "hw_ld/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM }, - { "hw_ld/parq", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM }, - { "hw_ld/pav", EV5HWMEM(0x1B,0x32), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pavl", EV5HWMEM(0x1B,0x33), EV5x, ARG_EV5HWMEM }, - { "hw_ld/paw", EV5HWMEM(0x1B,0x38), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pawl", EV5HWMEM(0x1B,0x39), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pawq", EV5HWMEM(0x1B,0x3c), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pawql", EV5HWMEM(0x1B,0x3d), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pawqv", EV5HWMEM(0x1B,0x3e), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pawqvl", EV5HWMEM(0x1B,0x3f), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pawv", EV5HWMEM(0x1B,0x3a), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pawvl", EV5HWMEM(0x1B,0x3b), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pl", EV5HWMEM(0x1B,0x21), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pq", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM }, - { "hw_ld/pq", EV5HWMEM(0x1B,0x24), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pql", EV5HWMEM(0x1B,0x25), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pqv", EV5HWMEM(0x1B,0x26), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pqvl", EV5HWMEM(0x1B,0x27), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM }, - { "hw_ld/prq", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM }, - { "hw_ld/pv", EV5HWMEM(0x1B,0x22), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pvl", EV5HWMEM(0x1B,0x23), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pw", EV5HWMEM(0x1B,0x28), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pwl", EV5HWMEM(0x1B,0x29), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pwq", EV5HWMEM(0x1B,0x2c), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pwql", EV5HWMEM(0x1B,0x2d), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pwqv", EV5HWMEM(0x1B,0x2e), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pwqvl", EV5HWMEM(0x1B,0x2f), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pwv", EV5HWMEM(0x1B,0x2a), EV5x, ARG_EV5HWMEM }, - { "hw_ld/pwvl", EV5HWMEM(0x1B,0x2b), EV5x, ARG_EV5HWMEM }, - { "hw_ld/q", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM }, - { "hw_ld/q", EV5HWMEM(0x1B,0x04), EV5x, ARG_EV5HWMEM }, - { "hw_ld/ql", EV5HWMEM(0x1B,0x05), EV5x, ARG_EV5HWMEM }, - { "hw_ld/qv", EV5HWMEM(0x1B,0x06), EV5x, ARG_EV5HWMEM }, - { "hw_ld/qvl", EV5HWMEM(0x1B,0x07), EV5x, ARG_EV5HWMEM }, - { "hw_ld/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM }, - { "hw_ld/rq", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM }, - { "hw_ld/v", EV5HWMEM(0x1B,0x02), EV5x, ARG_EV5HWMEM }, - { "hw_ld/vl", EV5HWMEM(0x1B,0x03), EV5x, ARG_EV5HWMEM }, - { "hw_ld/w", EV5HWMEM(0x1B,0x08), EV5x, ARG_EV5HWMEM }, - { "hw_ld/wl", EV5HWMEM(0x1B,0x09), EV5x, ARG_EV5HWMEM }, - { "hw_ld/wq", EV5HWMEM(0x1B,0x0c), EV5x, ARG_EV5HWMEM }, - { "hw_ld/wql", EV5HWMEM(0x1B,0x0d), EV5x, ARG_EV5HWMEM }, - { "hw_ld/wqv", EV5HWMEM(0x1B,0x0e), EV5x, ARG_EV5HWMEM }, - { "hw_ld/wqvl", EV5HWMEM(0x1B,0x0f), EV5x, ARG_EV5HWMEM }, - { "hw_ld/wv", EV5HWMEM(0x1B,0x0a), EV5x, ARG_EV5HWMEM }, - { "hw_ld/wvl", EV5HWMEM(0x1B,0x0b), EV5x, ARG_EV5HWMEM }, - { "pal1b", PCD(0x1B), ALL, ARG_PCD }, - - { "hw_mtpr", OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, - { "hw_mtpr", OP(0x1D), OP_MASK, EV5x, { RA, RBA, EV5HWINDEX } }, - { "hw_mtpr/i", OPR(0x1D,0x01), EV4, ARG_EV4HWMPR }, - { "hw_mtpr/a", OPR(0x1D,0x02), EV4, ARG_EV4HWMPR }, - { "hw_mtpr/ai", OPR(0x1D,0x03), EV4, ARG_EV4HWMPR }, - { "hw_mtpr/p", OPR(0x1D,0x04), EV4, ARG_EV4HWMPR }, - { "hw_mtpr/pi", OPR(0x1D,0x05), EV4, ARG_EV4HWMPR }, - { "hw_mtpr/pa", OPR(0x1D,0x06), EV4, ARG_EV4HWMPR }, - { "hw_mtpr/pai", OPR(0x1D,0x07), EV4, ARG_EV4HWMPR }, - { "pal1d", PCD(0x1D), ALL, ARG_PCD }, - - { "hw_rei", SPCD(0x1E,0x3FF8000), EV4|EV5x, ARG_NONE }, - { "hw_rei_stall", SPCD(0x1E,0x3FFC000), EV5x, ARG_NONE }, - { "pal1e", PCD(0x1E), ALL, ARG_PCD }, - - { "hw_stl", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM }, - { "hw_stl", EV5HWMEM(0x1F,0x00), EV5x, ARG_EV5HWMEM }, - { "hw_stl/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM }, - { "hw_stl/a", EV5HWMEM(0x1F,0x10), EV5x, ARG_EV5HWMEM }, - { "hw_stl/ac", EV5HWMEM(0x1F,0x11), EV5x, ARG_EV5HWMEM }, - { "hw_stl/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM }, - { "hw_stl/av", EV5HWMEM(0x1F,0x12), EV5x, ARG_EV5HWMEM }, - { "hw_stl/avc", EV5HWMEM(0x1F,0x13), EV5x, ARG_EV5HWMEM }, - { "hw_stl/c", EV5HWMEM(0x1F,0x01), EV5x, ARG_EV5HWMEM }, - { "hw_stl/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM }, - { "hw_stl/p", EV5HWMEM(0x1F,0x20), EV5x, ARG_EV5HWMEM }, - { "hw_stl/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM }, - { "hw_stl/pa", EV5HWMEM(0x1F,0x30), EV5x, ARG_EV5HWMEM }, - { "hw_stl/pac", EV5HWMEM(0x1F,0x31), EV5x, ARG_EV5HWMEM }, - { "hw_stl/pav", EV5HWMEM(0x1F,0x32), EV5x, ARG_EV5HWMEM }, - { "hw_stl/pavc", EV5HWMEM(0x1F,0x33), EV5x, ARG_EV5HWMEM }, - { "hw_stl/pc", EV5HWMEM(0x1F,0x21), EV5x, ARG_EV5HWMEM }, - { "hw_stl/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM }, - { "hw_stl/pv", EV5HWMEM(0x1F,0x22), EV5x, ARG_EV5HWMEM }, - { "hw_stl/pvc", EV5HWMEM(0x1F,0x23), EV5x, ARG_EV5HWMEM }, - { "hw_stl/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM }, - { "hw_stl/v", EV5HWMEM(0x1F,0x02), EV5x, ARG_EV5HWMEM }, - { "hw_stl/vc", EV5HWMEM(0x1F,0x03), EV5x, ARG_EV5HWMEM }, - { "hw_stl_c", EV5HWMEM(0x1F,0x01), EV5x, ARG_EV5HWMEM }, - { "hw_stl_c/a", EV5HWMEM(0x1F,0x11), EV5x, ARG_EV5HWMEM }, - { "hw_stl_c/av", EV5HWMEM(0x1F,0x13), EV5x, ARG_EV5HWMEM }, - { "hw_stl_c/p", EV5HWMEM(0x1F,0x21), EV5x, ARG_EV5HWMEM }, - { "hw_stl_c/pa", EV5HWMEM(0x1F,0x31), EV5x, ARG_EV5HWMEM }, - { "hw_stl_c/pav", EV5HWMEM(0x1F,0x33), EV5x, ARG_EV5HWMEM }, - { "hw_stl_c/pv", EV5HWMEM(0x1F,0x23), EV5x, ARG_EV5HWMEM }, - { "hw_stl_c/v", EV5HWMEM(0x1F,0x03), EV5x, ARG_EV5HWMEM }, - { "hw_stq", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM }, - { "hw_stq", EV5HWMEM(0x1F,0x04), EV5x, ARG_EV5HWMEM }, - { "hw_stq/a", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM }, - { "hw_stq/a", EV5HWMEM(0x1F,0x14), EV5x, ARG_EV5HWMEM }, - { "hw_stq/ac", EV5HWMEM(0x1F,0x15), EV5x, ARG_EV5HWMEM }, - { "hw_stq/ar", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM }, - { "hw_stq/av", EV5HWMEM(0x1F,0x16), EV5x, ARG_EV5HWMEM }, - { "hw_stq/avc", EV5HWMEM(0x1F,0x17), EV5x, ARG_EV5HWMEM }, - { "hw_stq/c", EV5HWMEM(0x1F,0x05), EV5x, ARG_EV5HWMEM }, - { "hw_stq/p", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM }, - { "hw_stq/p", EV5HWMEM(0x1F,0x24), EV5x, ARG_EV5HWMEM }, - { "hw_stq/pa", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM }, - { "hw_stq/pa", EV5HWMEM(0x1F,0x34), EV5x, ARG_EV5HWMEM }, - { "hw_stq/pac", EV5HWMEM(0x1F,0x35), EV5x, ARG_EV5HWMEM }, - { "hw_stq/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM }, - { "hw_stq/par", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM }, - { "hw_stq/pav", EV5HWMEM(0x1F,0x36), EV5x, ARG_EV5HWMEM }, - { "hw_stq/pavc", EV5HWMEM(0x1F,0x37), EV5x, ARG_EV5HWMEM }, - { "hw_stq/pc", EV5HWMEM(0x1F,0x25), EV5x, ARG_EV5HWMEM }, - { "hw_stq/pr", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM }, - { "hw_stq/pv", EV5HWMEM(0x1F,0x26), EV5x, ARG_EV5HWMEM }, - { "hw_stq/pvc", EV5HWMEM(0x1F,0x27), EV5x, ARG_EV5HWMEM }, - { "hw_stq/r", EV4HWMEM(0x1F,0x3), EV4, ARG_EV4HWMEM }, - { "hw_stq/v", EV5HWMEM(0x1F,0x06), EV5x, ARG_EV5HWMEM }, - { "hw_stq/vc", EV5HWMEM(0x1F,0x07), EV5x, ARG_EV5HWMEM }, - { "hw_stq_c", EV5HWMEM(0x1F,0x05), EV5x, ARG_EV5HWMEM }, - { "hw_stq_c/a", EV5HWMEM(0x1F,0x15), EV5x, ARG_EV5HWMEM }, - { "hw_stq_c/av", EV5HWMEM(0x1F,0x17), EV5x, ARG_EV5HWMEM }, - { "hw_stq_c/p", EV5HWMEM(0x1F,0x25), EV5x, ARG_EV5HWMEM }, - { "hw_stq_c/pa", EV5HWMEM(0x1F,0x35), EV5x, ARG_EV5HWMEM }, - { "hw_stq_c/pav", EV5HWMEM(0x1F,0x37), EV5x, ARG_EV5HWMEM }, - { "hw_stq_c/pv", EV5HWMEM(0x1F,0x27), EV5x, ARG_EV5HWMEM }, - { "hw_stq_c/v", EV5HWMEM(0x1F,0x07), EV5x, ARG_EV5HWMEM }, - { "hw_st", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM }, - { "hw_st", EV5HWMEM(0x1F,0x00), EV5x, ARG_EV5HWMEM }, - { "hw_st/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM }, - { "hw_st/a", EV5HWMEM(0x1F,0x10), EV5x, ARG_EV5HWMEM }, - { "hw_st/ac", EV5HWMEM(0x1F,0x11), EV5x, ARG_EV5HWMEM }, - { "hw_st/aq", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM }, - { "hw_st/aq", EV5HWMEM(0x1F,0x14), EV5x, ARG_EV5HWMEM }, - { "hw_st/aqc", EV5HWMEM(0x1F,0x15), EV5x, ARG_EV5HWMEM }, - { "hw_st/aqv", EV5HWMEM(0x1F,0x16), EV5x, ARG_EV5HWMEM }, - { "hw_st/aqvc", EV5HWMEM(0x1F,0x17), EV5x, ARG_EV5HWMEM }, - { "hw_st/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM }, - { "hw_st/arq", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM }, - { "hw_st/av", EV5HWMEM(0x1F,0x12), EV5x, ARG_EV5HWMEM }, - { "hw_st/avc", EV5HWMEM(0x1F,0x13), EV5x, ARG_EV5HWMEM }, - { "hw_st/c", EV5HWMEM(0x1F,0x01), EV5x, ARG_EV5HWMEM }, - { "hw_st/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM }, - { "hw_st/p", EV5HWMEM(0x1F,0x20), EV5x, ARG_EV5HWMEM }, - { "hw_st/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM }, - { "hw_st/pa", EV5HWMEM(0x1F,0x30), EV5x, ARG_EV5HWMEM }, - { "hw_st/pac", EV5HWMEM(0x1F,0x31), EV5x, ARG_EV5HWMEM }, - { "hw_st/paq", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM }, - { "hw_st/paq", EV5HWMEM(0x1F,0x34), EV5x, ARG_EV5HWMEM }, - { "hw_st/paqc", EV5HWMEM(0x1F,0x35), EV5x, ARG_EV5HWMEM }, - { "hw_st/paqv", EV5HWMEM(0x1F,0x36), EV5x, ARG_EV5HWMEM }, - { "hw_st/paqvc", EV5HWMEM(0x1F,0x37), EV5x, ARG_EV5HWMEM }, - { "hw_st/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM }, - { "hw_st/parq", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM }, - { "hw_st/pav", EV5HWMEM(0x1F,0x32), EV5x, ARG_EV5HWMEM }, - { "hw_st/pavc", EV5HWMEM(0x1F,0x33), EV5x, ARG_EV5HWMEM }, - { "hw_st/pc", EV5HWMEM(0x1F,0x21), EV5x, ARG_EV5HWMEM }, - { "hw_st/pq", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM }, - { "hw_st/pq", EV5HWMEM(0x1F,0x24), EV5x, ARG_EV5HWMEM }, - { "hw_st/pqc", EV5HWMEM(0x1F,0x25), EV5x, ARG_EV5HWMEM }, - { "hw_st/pqv", EV5HWMEM(0x1F,0x26), EV5x, ARG_EV5HWMEM }, - { "hw_st/pqvc", EV5HWMEM(0x1F,0x27), EV5x, ARG_EV5HWMEM }, - { "hw_st/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM }, - { "hw_st/prq", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM }, - { "hw_st/pv", EV5HWMEM(0x1F,0x22), EV5x, ARG_EV5HWMEM }, - { "hw_st/pvc", EV5HWMEM(0x1F,0x23), EV5x, ARG_EV5HWMEM }, - { "hw_st/q", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM }, - { "hw_st/q", EV5HWMEM(0x1F,0x04), EV5x, ARG_EV5HWMEM }, - { "hw_st/qc", EV5HWMEM(0x1F,0x05), EV5x, ARG_EV5HWMEM }, - { "hw_st/qv", EV5HWMEM(0x1F,0x06), EV5x, ARG_EV5HWMEM }, - { "hw_st/qvc", EV5HWMEM(0x1F,0x07), EV5x, ARG_EV5HWMEM }, - { "hw_st/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM }, - { "hw_st/v", EV5HWMEM(0x1F,0x02), EV5x, ARG_EV5HWMEM }, - { "hw_st/vc", EV5HWMEM(0x1F,0x03), EV5x, ARG_EV5HWMEM }, - { "pal1f", PCD(0x1F), ALL, ARG_PCD }, - - { "ldf", MEM(0x20), ALL, ARG_FMEM }, - { "ldg", MEM(0x21), ALL, ARG_FMEM }, - { "lds", MEM(0x22), ALL, ARG_FMEM }, - { "ldt", MEM(0x23), ALL, ARG_FMEM }, - { "stf", MEM(0x24), ALL, ARG_FMEM }, - { "stg", MEM(0x25), ALL, ARG_FMEM }, - { "sts", MEM(0x26), ALL, ARG_FMEM }, - { "stt", MEM(0x27), ALL, ARG_FMEM }, - - { "ldl", MEM(0x28), ALL, ARG_MEM }, - { "ldq", MEM(0x29), ALL, ARG_MEM }, - { "ldl_l", MEM(0x2A), ALL, ARG_MEM }, - { "ldq_l", MEM(0x2B), ALL, ARG_MEM }, - { "stl", MEM(0x2C), ALL, ARG_MEM }, - { "stq", MEM(0x2D), ALL, ARG_MEM }, - { "stl_c", MEM(0x2E), ALL, ARG_MEM }, - { "stq_c", MEM(0x2F), ALL, ARG_MEM }, - - { "br", BRA(0x30), ALL, { ZA, BDISP } }, /* pseudo */ - { "br", BRA(0x30), ALL, ARG_BRA }, - { "fbeq", BRA(0x31), ALL, ARG_FBRA }, - { "fblt", BRA(0x32), ALL, ARG_FBRA }, - { "fble", BRA(0x33), ALL, ARG_FBRA }, - { "bsr", BRA(0x34), ALL, ARG_BRA }, - { "fbne", BRA(0x35), ALL, ARG_FBRA }, - { "fbge", BRA(0x36), ALL, ARG_FBRA }, - { "fbgt", BRA(0x37), ALL, ARG_FBRA }, - { "blbc", BRA(0x38), ALL, ARG_BRA }, - { "beq", BRA(0x39), ALL, ARG_BRA }, - { "blt", BRA(0x3A), ALL, ARG_BRA }, - { "ble", BRA(0x3B), ALL, ARG_BRA }, - { "blbs", BRA(0x3C), ALL, ARG_BRA }, - { "bne", BRA(0x3D), ALL, ARG_BRA }, - { "bge", BRA(0x3E), ALL, ARG_BRA }, - { "bgt", BRA(0x3F), ALL, ARG_BRA }, -}; - -const int alpha_num_opcodes = sizeof(alpha_opcodes)/sizeof(*alpha_opcodes); diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c deleted file mode 100644 index 9868ae73756..00000000000 --- a/opcodes/arc-dis.c +++ /dev/null @@ -1,315 +0,0 @@ -/* Instruction printing code for the ARC. - Copyright (C) 1994, 1995 Free Software Foundation, Inc. - Contributed by Doug Evans (dje@cygnus.com). - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ - -#include "dis-asm.h" -#include "opcode/arc.h" -#include "libelf.h" -#include "elf/arc.h" - -static int print_insn_arc_base_little PARAMS ((bfd_vma, disassemble_info *)); -static int print_insn_arc_host_little PARAMS ((bfd_vma, disassemble_info *)); -static int print_insn_arc_graphics_little PARAMS ((bfd_vma, disassemble_info *)); -static int print_insn_arc_audio_little PARAMS ((bfd_vma, disassemble_info *)); -static int print_insn_arc_base_big PARAMS ((bfd_vma, disassemble_info *)); -static int print_insn_arc_host_big PARAMS ((bfd_vma, disassemble_info *)); -static int print_insn_arc_graphics_big PARAMS ((bfd_vma, disassemble_info *)); -static int print_insn_arc_audio_big PARAMS ((bfd_vma, disassemble_info *)); - -static int print_insn PARAMS ((bfd_vma, disassemble_info *, int, int)); - -/* Print one instruction from PC on INFO->STREAM. - Return the size of the instruction (4 or 8 for the ARC). */ - -static int -print_insn (pc, info, mach, big_p) - bfd_vma pc; - disassemble_info *info; - int mach; - int big_p; -{ - const struct arc_opcode *opcode,*opcode_end; - bfd_byte buffer[4]; - void *stream = info->stream; - fprintf_ftype func = info->fprintf_func; - int status; - /* First element is insn, second element is limm (if present). */ - arc_insn insn[2]; - int got_limm_p = 0; - static int initialized = 0; - static int current_mach = 0; - - if (!initialized || mach != current_mach) - { - initialized = 1; - current_mach = arc_get_opcode_mach (mach, big_p); - arc_opcode_init_tables (current_mach); - } - - status = (*info->read_memory_func) (pc, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return -1; - } - if (big_p) - insn[0] = bfd_getb32 (buffer); - else - insn[0] = bfd_getl32 (buffer); - - (*func) (stream, "%08lx\t", insn[0]); - - opcode_end = arc_opcodes + arc_opcodes_count; - for (opcode = arc_opcodes; opcode < opcode_end; opcode++) - { - char *syn; - int mods,invalid; - long value; - const struct arc_operand *operand; - const struct arc_operand_value *opval; - - /* Basic bit mask must be correct. */ - if ((insn[0] & opcode->mask) != opcode->value) - continue; - - /* Supported by this cpu? */ - if (! arc_opcode_supported (opcode)) - continue; - - /* Make two passes over the operands. First see if any of them - have extraction functions, and, if they do, make sure the - instruction is valid. */ - - arc_opcode_init_extract (); - invalid = 0; - - /* ??? Granted, this is slower than the `ppc' way. Maybe when this is - done it'll be clear what the right way to do this is. */ - /* Instructions like "add.f r0,r1,1" are tricky because the ".f" gets - printed first, but we don't know how to print it until we've processed - the regs. Since we're scanning all the args before printing the insn - anyways, it's actually quite easy. */ - - for (syn = opcode->syntax; *syn; ++syn) - { - if (*syn != '%' || *++syn == '%') - continue; - mods = 0; - while (ARC_MOD_P (arc_operands[arc_operand_map[*syn]].flags)) - { - mods |= arc_operands[arc_operand_map[*syn]].flags & ARC_MOD_BITS; - ++syn; - } - operand = arc_operands + arc_operand_map[*syn]; - if (operand->extract) - (*operand->extract) (insn, operand, mods, - (const struct arc_operand_value **) NULL, - &invalid); - } - if (invalid) - continue; - - /* The instruction is valid. */ - - /* If we have an insn with a limm, fetch it now. Scanning the insns - twice lets us do this. */ - if (arc_opcode_limm_p (NULL)) - { - status = (*info->read_memory_func) (pc + 4, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return -1; - } - if (big_p) - insn[1] = bfd_getb32 (buffer); - else - insn[1] = bfd_getl32 (buffer); - got_limm_p = 1; - } - - for (syn = opcode->syntax; *syn; ++syn) - { - if (*syn != '%' || *++syn == '%') - { - (*func) (stream, "%c", *syn); - continue; - } - - /* We have an operand. Fetch any special modifiers. */ - mods = 0; - while (ARC_MOD_P (arc_operands[arc_operand_map[*syn]].flags)) - { - mods |= arc_operands[arc_operand_map[*syn]].flags & ARC_MOD_BITS; - ++syn; - } - operand = arc_operands + arc_operand_map[*syn]; - - /* Extract the value from the instruction. */ - opval = NULL; - if (operand->extract) - { - value = (*operand->extract) (insn, operand, mods, - &opval, (int *) NULL); - } - else - { - value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1); - if ((operand->flags & ARC_OPERAND_SIGNED) - && (value & (1 << (operand->bits - 1)))) - value -= 1 << operand->bits; - - /* If this is a suffix operand, set `opval'. */ - if (operand->flags & ARC_OPERAND_SUFFIX) - opval = arc_opcode_lookup_suffix (operand, value); - } - - /* Print the operand as directed by the flags. */ - if (operand->flags & ARC_OPERAND_FAKE) - ; /* nothing to do (??? at least not yet) */ - else if (operand->flags & ARC_OPERAND_SUFFIX) - { - /* Default suffixes aren't printed. Fortunately, they all have - zero values. Also, zero values for boolean suffixes are - represented by the absence of text. */ - - if (value != 0) - { - /* ??? OPVAL should have a value. If it doesn't just cope - as we want disassembly to be reasonably robust. - Also remember that several condition code values (16-31) - aren't defined yet. For these cases just print the - number suitably decorated. */ - if (opval) - (*func) (stream, "%s%s", - mods & ARC_MOD_DOT ? "." : "", - opval->name); - else - (*func) (stream, "%s%c%d", - mods & ARC_MOD_DOT ? "." : "", - operand->fmt, value); - } - } - else if (operand->flags & ARC_OPERAND_RELATIVE_BRANCH) - (*info->print_address_func) (pc + 4 + value, info); - /* ??? Not all cases of this are currently caught. */ - else if (operand->flags & ARC_OPERAND_ABSOLUTE_BRANCH) - (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); - else if (operand->flags & ARC_OPERAND_ADDRESS) - (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); - else if (opval) - /* Note that this case catches both normal and auxiliary regs. */ - (*func) (stream, "%s", opval->name); - else - (*func) (stream, "%ld", value); - } - - /* We have found and printed an instruction; return. */ - return got_limm_p ? 8 : 4; - } - - (*func) (stream, "*unknown*"); - return 4; -} - -/* Given MACH, one of bfd_mach_arc_xxx, return the print_insn function to use. - This does things a non-standard way (the "standard" way would be to copy - this code into disassemble.c). Since there are more than a couple of - variants, hiding all this crud here seems cleaner. */ - -disassembler_ftype -arc_get_disassembler (mach, big_p) - int mach; - int big_p; -{ - switch (mach) - { - case bfd_mach_arc_base: - return big_p ? print_insn_arc_base_big : print_insn_arc_base_little; - case bfd_mach_arc_host: - return big_p ? print_insn_arc_host_big : print_insn_arc_host_little; - case bfd_mach_arc_graphics: - return big_p ? print_insn_arc_graphics_big : print_insn_arc_graphics_little; - case bfd_mach_arc_audio: - return big_p ? print_insn_arc_audio_big : print_insn_arc_audio_little; - } - return print_insn_arc_base_little; -} - -static int -print_insn_arc_base_little (pc, info) - bfd_vma pc; - disassemble_info *info; -{ - return print_insn (pc, info, bfd_mach_arc_base, 0); -} - -static int -print_insn_arc_host_little (pc, info) - bfd_vma pc; - disassemble_info *info; -{ - return print_insn (pc, info, bfd_mach_arc_host, 0); -} - -static int -print_insn_arc_graphics_little (pc, info) - bfd_vma pc; - disassemble_info *info; -{ - return print_insn (pc, info, bfd_mach_arc_graphics, 0); -} - -static int -print_insn_arc_audio_little (pc, info) - bfd_vma pc; - disassemble_info *info; -{ - return print_insn (pc, info, bfd_mach_arc_audio, 0); -} - -static int -print_insn_arc_base_big (pc, info) - bfd_vma pc; - disassemble_info *info; -{ - return print_insn (pc, info, bfd_mach_arc_base, 1); -} - -static int -print_insn_arc_host_big (pc, info) - bfd_vma pc; - disassemble_info *info; -{ - return print_insn (pc, info, bfd_mach_arc_host, 1); -} - -static int -print_insn_arc_graphics_big (pc, info) - bfd_vma pc; - disassemble_info *info; -{ - return print_insn (pc, info, bfd_mach_arc_graphics, 1); -} - -static int -print_insn_arc_audio_big (pc, info) - bfd_vma pc; - disassemble_info *info; -{ - return print_insn (pc, info, bfd_mach_arc_audio, 1); -} diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c deleted file mode 100644 index e0cdef6c6da..00000000000 --- a/opcodes/arc-opc.c +++ /dev/null @@ -1,1157 +0,0 @@ -/* Opcode table for the ARC. - Copyright 1994, 1995 Free Software Foundation, Inc. - Contributed by Doug Evans (dje@cygnus.com). - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ - -#include "ansidecl.h" -#include "opcode/arc.h" - -#define INSERT_FN(fn) \ -static arc_insn fn PARAMS ((arc_insn, const struct arc_operand *, \ - int, const struct arc_operand_value *, long, \ - const char **)) -#define EXTRACT_FN(fn) \ -static long fn PARAMS ((arc_insn *, const struct arc_operand *, \ - int, const struct arc_operand_value **, int *)) - -INSERT_FN (insert_reg); -INSERT_FN (insert_shimmfinish); -INSERT_FN (insert_limmfinish); -INSERT_FN (insert_shimmoffset); -INSERT_FN (insert_shimmzero); -INSERT_FN (insert_flag); -INSERT_FN (insert_flagfinish); -INSERT_FN (insert_cond); -INSERT_FN (insert_forcelimm); -INSERT_FN (insert_reladdr); -INSERT_FN (insert_absaddr); -INSERT_FN (insert_unopmacro); -INSERT_FN (insert_multshift); - -EXTRACT_FN (extract_reg); -EXTRACT_FN (extract_flag); -EXTRACT_FN (extract_cond); -EXTRACT_FN (extract_reladdr); -EXTRACT_FN (extract_unopmacro); -EXTRACT_FN (extract_multshift); - -/* Various types of ARC operands, including insn suffixes. */ - -/* Insn format values: - - 'a' REGA register A field - 'b' REGB register B field - 'c' REGC register C field - 'S' SHIMMFINISH finish inserting a shimm value - 'L' LIMMFINISH finish inserting a limm value - 'd' SHIMMOFFSET shimm offset in ld,st insns - '0' SHIMMZERO 0 shimm value in ld,st insns - 'f' FLAG F flag - 'F' FLAGFINISH finish inserting the F flag - 'G' FLAGINSN insert F flag in "flag" insn - 'n' DELAY N field (nullify field) - 'q' COND condition code field - 'Q' FORCELIMM set `cond_p' to 1 to ensure a constant is a limm - 'B' BRANCH branch address (22 bit pc relative) - 'J' JUMP jump address (26 bit absolute) - 'z' SIZE1 size field in ld a,[b,c] - 'Z' SIZE10 size field in ld a,[b,shimm] - 'y' SIZE22 size field in st c,[b,shimm] - 'x' SIGN0 sign extend field ld a,[b,c] - 'X' SIGN9 sign extend field ld a,[b,shimm] - 'w' ADDRESS3 write-back field in ld a,[b,c] - 'W' ADDRESS12 write-back field in ld a,[b,shimm] - 'v' ADDRESS24 write-back field in st c,[b,shimm] - 'e' CACHEBYPASS5 cache bypass in ld a,[b,c] - 'E' CACHEBYPASS14 cache bypass in ld a,[b,shimm] - 'D' CACHEBYPASS26 cache bypass in st c,[b,shimm] - 'u' UNSIGNED unsigned multiply - 's' SATURATION saturation limit in audio arc mac insn - 'U' UNOPMACRO fake operand to copy REGB to REGC for unop macros - - The following modifiers may appear between the % and char (eg: %.f): - - '.' MODDOT '.' prefix must be present - 'r' REG generic register value, for register table - 'A' AUXREG auxiliary register in lr a,[b], sr c,[b] - - Fields are: - - CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN -*/ - -const struct arc_operand arc_operands[] = -{ -/* place holder (??? not sure if needed) */ -#define UNUSED 0 - { 0 }, - -/* register A or shimm/limm indicator */ -#define REGA (UNUSED + 1) - { 'a', 6, ARC_SHIFT_REGA, 0, insert_reg, extract_reg }, - -/* register B or shimm/limm indicator */ -#define REGB (REGA + 1) - { 'b', 6, ARC_SHIFT_REGB, 0, insert_reg, extract_reg }, - -/* register C or shimm/limm indicator */ -#define REGC (REGB + 1) - { 'c', 6, ARC_SHIFT_REGC, 0, insert_reg, extract_reg }, - -/* fake operand used to insert shimm value into most instructions */ -#define SHIMMFINISH (REGC + 1) - { 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 }, - -/* fake operand used to insert limm value into most instructions; - this is also used for .word handling */ -#define LIMMFINISH (SHIMMFINISH + 1) - { 'L', 32, 32, ARC_OPERAND_ADDRESS + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_limmfinish, 0 }, - -/* shimm operand when there is no reg indicator (ld,st) */ -#define SHIMMOFFSET (LIMMFINISH + 1) - { 'd', 9, 0, ARC_OPERAND_SIGNED, insert_shimmoffset, 0 }, - -/* 0 shimm operand for ld,st insns */ -#define SHIMMZERO (SHIMMOFFSET + 1) - { '0', 9, 0, ARC_OPERAND_FAKE, insert_shimmzero, 0 }, - -/* flag update bit (insertion is defered until we know how) */ -#define FLAG (SHIMMZERO + 1) - { 'f', 1, 8, ARC_OPERAND_SUFFIX, insert_flag, extract_flag }, - -/* fake utility operand to finish 'f' suffix handling */ -#define FLAGFINISH (FLAG + 1) - { 'F', 1, 8, ARC_OPERAND_FAKE, insert_flagfinish, 0 }, - -/* fake utility operand to set the 'f' flag for the "flag" insn */ -#define FLAGINSN (FLAGFINISH + 1) - { 'G', 1, 8, ARC_OPERAND_FAKE, insert_flag, 0 }, - -/* branch delay types */ -#define DELAY (FLAGINSN + 1) - { 'n', 2, 5, ARC_OPERAND_SUFFIX }, - -/* conditions */ -#define COND (DELAY + 1) - { 'q', 5, 0, ARC_OPERAND_SUFFIX, insert_cond, extract_cond }, - -/* set `cond_p' to 1 to ensure a constant is treated as a limm */ -#define FORCELIMM (COND + 1) - { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm }, - -/* branch address; b, bl, and lp insns */ -#define BRANCH (FORCELIMM + 1) - { 'B', 20, 7, ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED, insert_reladdr, extract_reladdr }, - -/* jump address; j insn (this is basically the same as 'L' except that the - value is right shifted by 2); this is also used for .word handling */ -#define JUMP (BRANCH + 1) - { 'J', 24, 32, ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_absaddr }, - -/* size field, stored in bit 1,2 */ -#define SIZE1 (JUMP + 1) - { 'z', 2, 1, ARC_OPERAND_SUFFIX }, - -/* size field, stored in bit 10,11 */ -#define SIZE10 (SIZE1 + 1) - { 'Z', 2, 10, ARC_OPERAND_SUFFIX, }, - -/* size field, stored in bit 22,23 */ -#define SIZE22 (SIZE10 + 1) - { 'y', 2, 22, ARC_OPERAND_SUFFIX, }, - -/* sign extend field, stored in bit 0 */ -#define SIGN0 (SIZE22 + 1) - { 'x', 1, 0, ARC_OPERAND_SUFFIX }, - -/* sign extend field, stored in bit 9 */ -#define SIGN9 (SIGN0 + 1) - { 'X', 1, 9, ARC_OPERAND_SUFFIX }, - -/* address write back, stored in bit 3 */ -#define ADDRESS3 (SIGN9 + 1) - { 'w', 1, 3, ARC_OPERAND_SUFFIX }, - -/* address write back, stored in bit 12 */ -#define ADDRESS12 (ADDRESS3 + 1) - { 'W', 1, 12, ARC_OPERAND_SUFFIX }, - -/* address write back, stored in bit 24 */ -#define ADDRESS24 (ADDRESS12 + 1) - { 'v', 1, 24, ARC_OPERAND_SUFFIX }, - -/* cache bypass, stored in bit 5 */ -#define CACHEBYPASS5 (ADDRESS24 + 1) - { 'e', 1, 5, ARC_OPERAND_SUFFIX }, - -/* cache bypass, stored in bit 14 */ -#define CACHEBYPASS14 (CACHEBYPASS5 + 1) - { 'E', 1, 14, ARC_OPERAND_SUFFIX }, - -/* cache bypass, stored in bit 26 */ -#define CACHEBYPASS26 (CACHEBYPASS14 + 1) - { 'D', 1, 26, ARC_OPERAND_SUFFIX }, - -/* unsigned multiply */ -#define UNSIGNED (CACHEBYPASS26 + 1) - { 'u', 1, 27, ARC_OPERAND_SUFFIX }, - -/* unsigned multiply */ -#define SATURATION (UNSIGNED + 1) - { 's', 1, 28, ARC_OPERAND_SUFFIX }, - -/* unop macro, used to copy REGB to REGC */ -#define UNOPMACRO (SATURATION + 1) - { 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro }, - -/* '.' modifier ('.' required). */ -#define MODDOT (UNOPMACRO + 1) - { '.', 1, 0, ARC_MOD_DOT }, - -/* Dummy 'r' modifier for the register table. - It's called a "dummy" because there's no point in inserting an 'r' into all - the %a/%b/%c occurrences in the insn table. */ -#define REG (MODDOT + 1) - { 'r', 6, 0, ARC_MOD_REG }, - -/* Known auxiliary register modifier (stored in shimm field). */ -#define AUXREG (REG + 1) - { 'A', 9, 0, ARC_MOD_AUXREG }, - -/* end of list place holder */ - { 0 } -}; - -/* Given a format letter, yields the index into `arc_operands'. - eg: arc_operand_map['a'] = REGA. */ -unsigned char arc_operand_map[256]; - -#define I(x) (((x) & 31) << 27) -#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA) -#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB) -#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC) -#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */ - -/* ARC instructions (sorted by at least the first letter, and equivalent - opcodes kept together). - - By recording the insns this way, the table is not hashable on the opcode. - That's not a real loss though as there are only a few entries for each - insn (ld/st being the exception), which are quickly found and since - they're stored together (eg: all `ld' variants are together) very little - time is spent on the opcode itself. The slow part is parsing the options, - but that's always going to be slow. - - Longer versions of insns must appear before shorter ones (if gas sees - "lsr r2,r3,1" when it's parsing "lsr %a,%b" it will think the ",1" is - junk). - - This table is best viewed on a wide screen (161 columns). - I'd prefer to keep it this way. */ - -/* ??? This table also includes macros: asl, lsl, and mov. The ppc port has - a more general facility for dealing with macros which could be used if - we need to. */ -/* ??? As an experiment, the "mov" macro appears at the start so it is - prefered to "and" when disassembling. At present, the table needn't be - sorted, though all opcodes with the same first letter must be kept - together. */ - -const struct arc_opcode arc_opcodes[] = { - { "mac%u%.s%.q%.f %a,%b,%c%F%S%L", I(-4), I(24), ARC_MACH_AUDIO }, - /* Note that "mov" is really an "and". */ - { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12) }, - { "mul%u%.q%.f %a,%b,%c%F%S%L", I(-2), I(28), ARC_MACH_AUDIO }, - /* ??? This insn allows an optional "0," preceding the args. */ - /* We can't use %u here because it's not a suffix (the "64" is in the way). */ - { "mul64%.q%.f %b,%c%F%S%L", I(-1)+A(-1), I(20)+A(-1), ARC_MACH_HOST+ARC_MACH_GRAPHICS }, - { "mulu64%.q%.f %b,%c%F%S%L", I(-1)+A(-1), I(21)+A(-1), ARC_MACH_HOST+ARC_MACH_GRAPHICS }, - - { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9) }, - { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8) }, - { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12) }, - { "asl%.q%.f %a,%b,%c%F%S%L", I(-1), I(16), ARC_MACH_HOST+ARC_MACH_GRAPHICS }, - /* Note that "asl" is really an "add". */ - { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) }, - { "asr%.q%.f %a,%b,%c%F%S%L", I(-1), I(18), ARC_MACH_HOST+ARC_MACH_GRAPHICS }, - { "asr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(1) }, - { "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14) }, - { "b%q%.n %B", I(-1), I(4) }, - { "bl%q%.n %B", I(-1), I(5) }, - { "extb%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(7) }, - { "extw%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(8) }, - { "flag%.q %b%G%S%L", I(-1)+A(-1)+C(-1), I(3)+A(ARC_REG_SHIMM_UPDATE)+C(0) }, - /* %Q: force cond_p=1 --> no shimm values */ - /* ??? This insn allows an optional flags spec. */ - { "j%q%Q%.n%.f %b%J", I(-1)+A(-1)+C(-1)+R(-1,7,1), I(7)+A(0)+C(0)+R(0,7,1) }, - /* Put opcode 1 ld insns first so shimm gets prefered over limm. */ - /* "[%b]" is before "[%b,%d]" so 0 offsets don't get printed. */ - { "ld%Z%.X%.W%.E %0%a,[%b]%L", I(-1)+R(-1,13,1)+R(-1,0,511), I(1)+R(0,13,1)+R(0,0,511) }, - { "ld%Z%.X%.W%.E %a,[%b,%d]%S%L", I(-1)+R(-1,13,1), I(1)+R(0,13,1) }, - { "ld%z%.x%.w%.e %a,[%b,%c]", I(-1)+R(-1,4,1)+R(-1,6,7), I(0)+R(0,4,1)+R(0,6,7) }, - { "lp%q%.n %B", I(-1), I(6), }, - { "lr %a,[%Ab]%S%L", I(-1)+C(-1), I(1)+C(0x10) }, - /* Note that "lsl" is really an "add". */ - { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) }, - { "lsr%.q%.f %a,%b,%c%F%S%L", I(-1), I(17), ARC_MACH_HOST+ARC_MACH_GRAPHICS }, - { "lsr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(2) }, - /* Note that "nop" is really an "xor". */ - { "nop", 0xffffffff, 0x7fffffff }, - { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13) }, - /* ??? The %a here should be %p or something. */ - { "padc%.q%.f %a,%b,%c%F%S%L", I(-1), I(25), ARC_MACH_GRAPHICS }, - { "padd%.q%.f %a,%b,%c%F%S%L", I(-1), I(24), ARC_MACH_GRAPHICS }, - /* Note that "pmov" is really a "pand". */ - { "pmov%.q%.f %a,%b%F%S%L%U", I(-1), I(28), ARC_MACH_GRAPHICS }, - { "pand%.q%.f %a,%b,%c%F%S%L", I(-1), I(28), ARC_MACH_GRAPHICS }, - { "psbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(27), ARC_MACH_GRAPHICS }, - { "psub%.q%.f %a,%b,%c%F%S%L", I(-1), I(26), ARC_MACH_GRAPHICS }, - /* Note that "rlc" is really an "adc". */ - { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9) }, - { "ror%.q%.f %a,%b,%c%F%S%L", I(-1), I(19), ARC_MACH_HOST+ARC_MACH_GRAPHICS }, - { "ror%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(3) }, - { "rrc%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(4) }, - { "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11) }, - { "sexb%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(5) }, - { "sexw%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(6) }, - { "sr %c,[%Ab]%S%L", I(-1)+A(-1), I(2)+A(0x10) }, - /* "[%b]" is before "[%b,%d]" so 0 offsets don't get printed. */ - { "st%y%.v%.D %0%c,[%b]%L", I(-1)+R(-1,25,3)+R(-1,21,1)+R(-1,0,511), I(2)+R(0,25,3)+R(0,21,1)+R(0,0,511) }, - { "st%y%.v%.D %c,[%b,%d]%S%L", I(-1)+R(-1,25,3)+R(-1,21,1), I(2)+R(0,25,3)+R(0,21,1) }, - { "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10) }, - { "swap%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(9), ARC_MACH_AUDIO }, - { "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15) } -}; -const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]); - -const struct arc_operand_value arc_reg_names[] = -{ - /* Sort this so that the first 61 entries are sequential. - IE: For each i (i<61), arc_reg_names[i].value == i. */ - - { "r0", 0, REG }, { "r1", 1, REG }, { "r2", 2, REG }, { "r3", 3, REG }, - { "r4", 4, REG }, { "r5", 5, REG }, { "r6", 6, REG }, { "r7", 7, REG }, - { "r8", 8, REG }, { "r9", 9, REG }, { "r10", 10, REG }, { "r11", 11, REG }, - { "r12", 12, REG }, { "r13", 13, REG }, { "r14", 14, REG }, { "r15", 15, REG }, - { "r16", 16, REG }, { "r17", 17, REG }, { "r18", 18, REG }, { "r19", 19, REG }, - { "r20", 20, REG }, { "r21", 21, REG }, { "r22", 22, REG }, { "r23", 23, REG }, - { "r24", 24, REG }, { "r25", 25, REG }, { "r26", 26, REG }, { "fp", 27, REG }, - { "sp", 28, REG }, { "ilink1", 29, REG }, { "ilink2", 30, REG }, { "blink", 31, REG }, - { "r32", 32, REG }, { "r33", 33, REG }, { "r34", 34, REG }, { "r35", 35, REG }, - { "r36", 36, REG }, { "r37", 37, REG }, { "r38", 38, REG }, { "r39", 39, REG }, - { "r40", 40, REG }, { "r41", 41, REG }, { "r42", 42, REG }, { "r43", 43, REG }, - { "r44", 44, REG }, { "r45", 45, REG }, { "r46", 46, REG }, { "r47", 47, REG }, - { "r48", 48, REG }, { "r49", 49, REG }, { "r50", 50, REG }, { "r51", 51, REG }, - { "r52", 52, REG }, { "r53", 53, REG }, { "r54", 54, REG }, { "r55", 55, REG }, - { "r56", 56, REG }, { "r57", 57, REG }, { "r58", 58, REG }, { "r59", 59, REG }, - { "lp_count", 60, REG }, - - /* I'd prefer to output these as "fp" and "sp" by default, but we still need - to recognize the canonical values. */ - { "r27", 27, REG }, { "r28", 28, REG }, - - /* Standard auxiliary registers. */ - { "status", 0, AUXREG }, - { "semaphore", 1, AUXREG }, - { "lp_start", 2, AUXREG }, - { "lp_end", 3, AUXREG }, - { "identity", 4, AUXREG }, - { "debug", 5, AUXREG }, - - /* Host ARC Extensions. */ - { "mlo", 57, REG, ARC_MACH_HOST }, - { "mmid", 58, REG, ARC_MACH_HOST }, - { "mhi", 59, REG, ARC_MACH_HOST }, - { "ivic", 0x10, AUXREG, ARC_MACH_HOST }, - { "ivdc", 0x11, AUXREG, ARC_MACH_HOST }, - { "ivdcn", 0x12, AUXREG, ARC_MACH_HOST }, - { "flushd", 0x13, AUXREG, ARC_MACH_HOST }, - { "saha", 0x14, AUXREG, ARC_MACH_HOST }, - { "gahd", 0x15, AUXREG, ARC_MACH_HOST }, - { "aahd", 0x16, AUXREG, ARC_MACH_HOST }, - { "rrcr", 0x17, AUXREG, ARC_MACH_HOST }, - { "rpcr", 0x18, AUXREG, ARC_MACH_HOST }, - { "flushdn", 0x19, AUXREG, ARC_MACH_HOST }, - { "dbgad1", 0x1a, AUXREG, ARC_MACH_HOST }, - { "dbgad2", 0x1b, AUXREG, ARC_MACH_HOST }, - { "dbgmde", 0x1c, AUXREG, ARC_MACH_HOST }, - { "dbgstat", 0x1d, AUXREG, ARC_MACH_HOST }, - { "wag", 0x1e, AUXREG, ARC_MACH_HOST }, - { "mulhi", 0x1f, AUXREG, ARC_MACH_HOST }, - { "intwide", 0x20, AUXREG, ARC_MACH_HOST }, - { "intgen", 0x21, AUXREG, ARC_MACH_HOST }, - { "rfsh_n", 0x22, AUXREG, ARC_MACH_HOST }, - - /* Graphics ARC Extensions. */ - { "mlo", 57, REG, ARC_MACH_GRAPHICS }, - { "mmid", 58, REG, ARC_MACH_GRAPHICS }, - { "mhi", 59, REG, ARC_MACH_GRAPHICS }, - { "ivic", 0x10, AUXREG, ARC_MACH_GRAPHICS }, - { "wag", 0x1e, AUXREG, ARC_MACH_GRAPHICS }, - { "mulhi", 0x1f, AUXREG, ARC_MACH_GRAPHICS }, - { "intwide", 0x20, AUXREG, ARC_MACH_GRAPHICS }, - { "intgen", 0x21, AUXREG, ARC_MACH_GRAPHICS }, - { "pix", 0x100, AUXREG, ARC_MACH_GRAPHICS }, - { "scratch", 0x120, AUXREG, ARC_MACH_GRAPHICS }, - - /* Audio ARC Extensions. */ - { "macmode", 39, REG, ARC_MACH_AUDIO }, - { "rs1", 40, REG, ARC_MACH_AUDIO }, - { "rs1n", 41, REG, ARC_MACH_AUDIO }, - { "rs1start", 42, REG, ARC_MACH_AUDIO }, - { "rs1size", 43, REG, ARC_MACH_AUDIO }, - { "rs1delta", 44, REG, ARC_MACH_AUDIO }, - { "rs1pos", 45, REG, ARC_MACH_AUDIO }, - { "rd1", 46, REG, ARC_MACH_AUDIO }, - { "rd1n", 47, REG, ARC_MACH_AUDIO }, - { "rd1d", 48, REG, ARC_MACH_AUDIO }, - { "rd1pos", 49, REG, ARC_MACH_AUDIO }, - { "rs2", 50, REG, ARC_MACH_AUDIO }, - { "rs2n", 51, REG, ARC_MACH_AUDIO }, - { "rs2start", 52, REG, ARC_MACH_AUDIO }, - { "rs2size", 53, REG, ARC_MACH_AUDIO }, - { "rs2delta", 54, REG, ARC_MACH_AUDIO }, - { "rs2pos", 55, REG, ARC_MACH_AUDIO }, - { "rd2", 56, REG, ARC_MACH_AUDIO }, - { "rd2n", 57, REG, ARC_MACH_AUDIO }, - { "rd2d", 58, REG, ARC_MACH_AUDIO }, - { "rd2pos", 59, REG, ARC_MACH_AUDIO }, - { "ivic", 0x10, AUXREG, ARC_MACH_AUDIO }, - { "wag", 0x1e, AUXREG, ARC_MACH_AUDIO }, - { "intwide", 0x20, AUXREG, ARC_MACH_AUDIO }, - { "intgen", 0x21, AUXREG, ARC_MACH_AUDIO }, - { "bm_sstart", 0x30, AUXREG, ARC_MACH_AUDIO }, - { "bm_length", 0x31, AUXREG, ARC_MACH_AUDIO }, - { "bm_rstart", 0x32, AUXREG, ARC_MACH_AUDIO }, - { "bm_go", 0x33, AUXREG, ARC_MACH_AUDIO }, - { "xtp_newval", 0x40, AUXREG, ARC_MACH_AUDIO }, - { "sram", 0x400, AUXREG, ARC_MACH_AUDIO }, - { "reg_file", 0x800, AUXREG, ARC_MACH_AUDIO }, -}; -const int arc_reg_names_count = sizeof (arc_reg_names) / sizeof (arc_reg_names[0]); - -/* The suffix table. - Operands with the same name must be stored together. */ - -const struct arc_operand_value arc_suffixes[] = -{ - /* Entry 0 is special, default values aren't printed by the disassembler. */ - { "", 0, -1 }, - { "al", 0, COND }, - { "ra", 0, COND }, - { "eq", 1, COND }, - { "z", 1, COND }, - { "ne", 2, COND }, - { "nz", 2, COND }, - { "p", 3, COND }, - { "pl", 3, COND }, - { "n", 4, COND }, - { "mi", 4, COND }, - { "c", 5, COND }, - { "cs", 5, COND }, - { "lo", 5, COND }, - { "nc", 6, COND }, - { "cc", 6, COND }, - { "hs", 6, COND }, - { "v", 7, COND }, - { "vs", 7, COND }, - { "nv", 8, COND }, - { "vc", 8, COND }, - { "gt", 9, COND }, - { "ge", 10, COND }, - { "lt", 11, COND }, - { "le", 12, COND }, - { "hi", 13, COND }, - { "ls", 14, COND }, - { "pnz", 15, COND }, - { "f", 1, FLAG }, - { "nd", 0, DELAY }, - { "d", 1, DELAY }, - { "jd", 2, DELAY }, -/*{ "b", 7, SIZEEXT },*/ -/*{ "b", 5, SIZESEX },*/ - { "b", 1, SIZE1 }, - { "b", 1, SIZE10 }, - { "b", 1, SIZE22 }, -/*{ "w", 8, SIZEEXT },*/ -/*{ "w", 6, SIZESEX },*/ - { "w", 2, SIZE1 }, - { "w", 2, SIZE10 }, - { "w", 2, SIZE22 }, - { "x", 1, SIGN0 }, - { "x", 1, SIGN9 }, - { "a", 1, ADDRESS3 }, - { "a", 1, ADDRESS12 }, - { "a", 1, ADDRESS24 }, - { "di", 1, CACHEBYPASS5 }, - { "di", 1, CACHEBYPASS14 }, - { "di", 1, CACHEBYPASS26 }, - - /* Audio ARC Extensions. */ - /* ??? The values here are guesses. */ - { "ss", 16, COND, ARC_MACH_AUDIO }, - { "sc", 17, COND, ARC_MACH_AUDIO }, - { "mh", 18, COND, ARC_MACH_AUDIO }, - { "ml", 19, COND, ARC_MACH_AUDIO }, -}; -const int arc_suffixes_count = sizeof (arc_suffixes) / sizeof (arc_suffixes[0]); - -/* Configuration flags. */ - -/* Various ARC_HAVE_XXX bits. */ -static int cpu_type; - -/* Translate a bfd_mach_arc_xxx value to a ARC_MACH_XXX value. */ - -int -arc_get_opcode_mach (bfd_mach, big_p) - int bfd_mach, big_p; -{ - static int mach_type_map[] = - { - ARC_MACH_BASE, ARC_MACH_HOST, ARC_MACH_GRAPHICS, ARC_MACH_AUDIO - }; - - return mach_type_map[bfd_mach] | (big_p ? ARC_MACH_BIG : 0); -} - -/* Initialize any tables that need it. - Must be called once at start up (or when first needed). - - FLAGS is a set of bits that say what version of the cpu we have, - and in particular at least (one of) ARC_MACH_XXX. */ - -void -arc_opcode_init_tables (flags) - int flags; -{ - register int i,n; - static int map_init_p = 0; - - cpu_type = flags; - - /* We may be intentionally called more than once (for example gdb will call - us each time the user switches cpu). This table only needs to be init'd - once though. */ - if (!map_init_p) - { - memset (arc_operand_map, 0, sizeof (arc_operand_map)); - n = sizeof (arc_operands) / sizeof (arc_operands[0]); - for (i = 0; i < n; i++) - arc_operand_map[arc_operands[i].fmt] = i; - map_init_p = 1; - } -} - -/* Return non-zero if OPCODE is supported on the specified cpu. - Cpu selection is made when calling `arc_opcode_init_tables'. */ - -int -arc_opcode_supported (opcode) - const struct arc_opcode *opcode; -{ - if (ARC_OPCODE_CPU (opcode->flags) == 0) - return 1; - if (ARC_OPCODE_CPU (opcode->flags) & ARC_HAVE_CPU (cpu_type)) - return 1; - return 0; -} - -/* Return non-zero if OPVAL is supported on the specified cpu. - Cpu selection is made when calling `arc_opcode_init_tables'. */ - -int -arc_opval_supported (opval) - const struct arc_operand_value *opval; -{ - if (ARC_OPVAL_CPU (opval->flags) == 0) - return 1; - if (ARC_OPVAL_CPU (opval->flags) & ARC_HAVE_CPU (cpu_type)) - return 1; - return 0; -} - -/* Nonzero if we've seen an 'f' suffix (in certain insns). */ -static int flag_p; - -/* Nonzero if we've finished processing the 'f' suffix. */ -static int flagshimm_handled_p; - -/* Nonzero if we've seen a 'q' suffix (condition code). */ -static int cond_p; - -/* Nonzero if we've inserted a shimm. */ -static int shimm_p; - -/* The value of the shimm we inserted (each insn only gets one but it can - appear multiple times. */ -static int shimm; - -/* Nonzero if we've inserted a limm (during assembly) or seen a limm - (during disassembly). */ -static int limm_p; - -/* The value of the limm we inserted. Each insn only gets one but it can - appear multiple times. */ -static long limm; - -/* Insertion functions. */ - -/* Called by the assembler before parsing an instruction. */ - -void -arc_opcode_init_insert () -{ - flag_p = 0; - flagshimm_handled_p = 0; - cond_p = 0; - shimm_p = 0; - limm_p = 0; -} - -/* Called by the assembler to see if the insn has a limm operand. - Also called by the disassembler to see if the insn contains a limm. */ - -int -arc_opcode_limm_p (limmp) - long *limmp; -{ - if (limmp) - *limmp = limm; - return limm_p; -} - -/* Insert a value into a register field. - If REG is NULL, then this is actually a constant. - - We must also handle auxiliary registers for lr/sr insns. */ - -static arc_insn -insert_reg (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - static char buf[100]; - - if (!reg) - { - /* We have a constant that also requires a value stored in a register - field. Handle these by updating the register field and saving the - value for later handling by either %S (shimm) or %L (limm). */ - - /* Try to use a shimm value before a limm one. */ - if (ARC_SHIMM_CONST_P (value) - /* If we've seen a conditional suffix we have to use a limm. */ - && !cond_p - /* If we already have a shimm value that is different than ours - we have to use a limm. */ - && (!shimm_p || shimm == value)) - { - int marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM; - flagshimm_handled_p = 1; - shimm_p = 1; - shimm = value; - insn |= marker << operand->shift; - /* insn |= value & 511; - done later */ - } - /* We have to use a limm. If we've already seen one they must match. */ - else if (!limm_p || limm == value) - { - limm_p = 1; - limm = value; - insn |= ARC_REG_LIMM << operand->shift; - /* The constant is stored later. */ - } - else - { - *errmsg = "unable to fit different valued constants into instruction"; - } - } - else - { - /* We have to handle both normal and auxiliary registers. */ - - if (reg->type == AUXREG) - { - if (!(mods & ARC_MOD_AUXREG)) - *errmsg = "auxiliary register not allowed here"; - else - { - insn |= ARC_REG_SHIMM << operand->shift; - insn |= reg->value << arc_operands[reg->type].shift; - } - } - else - { - /* We should never get an invalid register number here. */ - if ((unsigned int) reg->value > 60) - { - sprintf (buf, "invalid register number `%d'", reg->value); - *errmsg = buf; - } - else - insn |= reg->value << operand->shift; - } - } - - return insn; -} - -/* Called when we see an 'f' flag. */ - -static arc_insn -insert_flag (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - /* We can't store anything in the insn until we've parsed the registers. - Just record the fact that we've got this flag. `insert_reg' will use it - to store the correct value (ARC_REG_SHIMM_UPDATE or bit 0x100). */ - flag_p = 1; - - return insn; -} - -/* Called after completely building an insn to ensure the 'f' flag gets set - properly. This is needed because we don't know how to set this flag until - we've parsed the registers. */ - -static arc_insn -insert_flagfinish (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - if (flag_p && !flagshimm_handled_p) - { - if (shimm_p) - abort (); - flagshimm_handled_p = 1; - insn |= (1 << operand->shift); - } - return insn; -} - -/* Called when we see a conditional flag (eg: .eq). */ - -static arc_insn -insert_cond (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - cond_p = 1; - insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; - return insn; -} - -/* Used in the "j" instruction to prevent constants from being interpreted as - shimm values (which the jump insn doesn't accept). This can also be used - to force the use of limm values in other situations (eg: ld r0,[foo] uses - this). - ??? The mechanism is sound. Access to it is a bit klunky right now. */ - -static arc_insn -insert_forcelimm (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - cond_p = 1; - return insn; -} - -/* Used in ld/st insns to handle the shimm offset field. */ - -static arc_insn -insert_shimmoffset (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; - return insn; -} - -/* Used in ld/st insns when the shimm offset is 0. */ - -static arc_insn -insert_shimmzero (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - shimm_p = 1; - shimm = 0; - return insn; -} - -/* Called at the end of processing normal insns (eg: add) to insert a shimm - value (if present) into the insn. */ - -static arc_insn -insert_shimmfinish (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - if (shimm_p) - insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift; - return insn; -} - -/* Called at the end of processing normal insns (eg: add) to insert a limm - value (if present) into the insn. - - Note that this function is only intended to handle instructions (with 4 byte - immediate operands). It is not intended to handle data. */ - -/* ??? Actually, there's nothing for us to do as we can't call frag_more, the - caller must do that. The extract fns take a pointer to two words. The - insert fns could be converted and then we could do something useful, but - then the reloc handlers would have to know to work on the second word of - a 2 word quantity. That's too much so we don't handle them. */ - -static arc_insn -insert_limmfinish (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - if (limm_p) - /* FIXME: put an abort here and see what happens. */ - ; /* nothing to do, gas does it */ - return insn; -} - -/* Called at the end of unary operand macros to copy the B field to C. */ - -static arc_insn -insert_unopmacro (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - insn |= ((insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) << operand->shift; - return insn; -} - -/* Insert a relative address for a branch insn (b, bl, or lp). */ - -static arc_insn -insert_reladdr (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - if (value & 3) - *errmsg = "branch address not on 4 byte boundary"; - insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift; - return insn; -} - -/* Insert a limm value as a 26 bit address right shifted 2 into the insn. - - Note that this function is only intended to handle instructions (with 4 byte - immediate operands). It is not intended to handle data. */ - -/* ??? Actually, there's nothing for us to do as we can't call frag_more, the - caller must do that. The extract fns take a pointer to two words. The - insert fns could be converted and then we could do something useful, but - then the reloc handlers would have to know to work on the second word of - a 2 word quantity. That's too much so we don't handle them. */ - -static arc_insn -insert_absaddr (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - if (limm_p) - /* FIXME: put an abort here and see what happens. */ - ; /* nothing to do */ - return insn; -} - -/* Extraction functions. - - The suffix extraction functions' return value is redundant since it can be - obtained from (*OPVAL)->value. However, the boolean suffixes don't have - a suffix table entry for the "false" case, so values of zero must be - obtained from the return value (*OPVAL == NULL). */ - -static const struct arc_operand_value *lookup_register (int type, long regno); - -/* Called by the disassembler before printing an instruction. */ - -void -arc_opcode_init_extract () -{ - flag_p = 0; - flagshimm_handled_p = 0; - shimm_p = 0; - limm_p = 0; -} - -/* As we're extracting registers, keep an eye out for the 'f' indicator - (ARC_REG_SHIMM_UPDATE). If we find a register (not a constant marker, - like ARC_REG_SHIMM), set OPVAL so our caller will know this is a register. - - We must also handle auxiliary registers for lr/sr insns. They are just - constants with special names. */ - -static long -extract_reg (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value **opval; - int *invalid; -{ - int regno; - long value; - - /* Get the register number. */ - regno = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1); - - /* Is it a constant marker? */ - if (regno == ARC_REG_SHIMM) - { - value = insn[0] & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) - && (value & 256)) - value -= 512; - flagshimm_handled_p = 1; - } - else if (regno == ARC_REG_SHIMM_UPDATE) - { - value = insn[0] & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) - && (value & 256)) - value -= 512; - flag_p = 1; - flagshimm_handled_p = 1; - } - else if (regno == ARC_REG_LIMM) - { - value = insn[1]; - limm_p = 1; - } - /* It's a register, set OPVAL (that's the only way we distinguish registers - from constants here). */ - else - { - const struct arc_operand_value *reg = lookup_register (REG, regno); - - if (!reg) - abort (); - if (opval) - *opval = reg; - value = regno; - } - - /* If this field takes an auxiliary register, see if it's a known one. */ - if ((mods & ARC_MOD_AUXREG) - && ARC_REG_CONSTANT_P (regno)) - { - const struct arc_operand_value *reg = lookup_register (AUXREG, value); - - /* This is really a constant, but tell the caller it has a special - name. */ - if (reg && opval) - *opval = reg; - } - - return value; -} - -/* Return the value of the "flag update" field for shimm insns. - This value is actually stored in the register field. */ - -static long -extract_flag (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value **opval; - int *invalid; -{ - int f; - const struct arc_operand_value *val; - - if (flagshimm_handled_p) - f = flag_p != 0; - else - f = (insn[0] & (1 << operand->shift)) != 0; - - /* There is no text for zero values. */ - if (f == 0) - return 0; - - val = arc_opcode_lookup_suffix (operand, 1); - if (opval && val) - *opval = val; - return val->value; -} - -/* Extract the condition code (if it exists). - If we've seen a shimm value in this insn (meaning that the insn can't have - a condition code field), then we don't store anything in OPVAL and return - zero. */ - -static long -extract_cond (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value **opval; - int *invalid; -{ - long cond; - const struct arc_operand_value *val; - - if (flagshimm_handled_p) - return 0; - - cond = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1); - val = arc_opcode_lookup_suffix (operand, cond); - - /* Ignore NULL values of `val'. Several condition code values are - reserved for extensions. */ - if (opval && val) - *opval = val; - return cond; -} - -/* Extract a branch address. - We return the value as a real address (not right shifted by 2). */ - -static long -extract_reladdr (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value **opval; - int *invalid; -{ - long addr; - - addr = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1); - if ((operand->flags & ARC_OPERAND_SIGNED) - && (addr & (1 << (operand->bits - 1)))) - addr -= 1 << operand->bits; - - return addr << 2; -} - -/* The only thing this does is set the `invalid' flag if B != C. - This is needed because the "mov" macro appears before it's real insn "and" - and we don't want the disassembler to confuse them. */ - -static long -extract_unopmacro (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value **opval; - int *invalid; -{ - /* ??? This misses the case where B == ARC_REG_SHIMM_UPDATE && - C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get - printed as "and"s. */ - if (((insn[0] >> ARC_SHIFT_REGB) & ARC_MASK_REG) - != ((insn[0] >> ARC_SHIFT_REGC) & ARC_MASK_REG)) - if (invalid) - *invalid = 1; - - return 0; -} - -/* Utility for the extraction functions to return the index into - `arc_suffixes'. */ - -const struct arc_operand_value * -arc_opcode_lookup_suffix (type, value) - const struct arc_operand *type; - int value; -{ - register const struct arc_operand_value *v,*end; - - /* ??? This is a little slow and can be speeded up. */ - - for (v = arc_suffixes, end = arc_suffixes + arc_suffixes_count; v < end; ++v) - if (type == &arc_operands[v->type] - && value == v->value) - return v; - return 0; -} - -static const struct arc_operand_value * -lookup_register (type, regno) - int type; - long regno; -{ - register const struct arc_operand_value *r,*end; - - if (type == REG) - return &arc_reg_names[regno]; - - /* ??? This is a little slow and can be speeded up. */ - - for (r = arc_reg_names, end = arc_reg_names + arc_reg_names_count; - r < end; ++r) - if (type == r->type && regno == r->value) - return r; - return 0; -} diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c deleted file mode 100644 index 3e4e002f1c2..00000000000 --- a/opcodes/arm-dis.c +++ /dev/null @@ -1,860 +0,0 @@ -/* Instruction printing code for the ARM - Copyright (C) 1994, 95, 96, 97, 1998 Free Software Foundation, Inc. - Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) - Modification by James G. Smith (jsmith@cygnus.co.uk) - -This file is part of libopcodes. - -This program is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 2 of the License, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, but WITHOUT -ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "dis-asm.h" -#define DEFINE_TABLE -#include "arm-opc.h" -#include "coff/internal.h" -#include "libcoff.h" -#include "opintl.h" - -/* FIXME: This shouldn't be done here */ -#include "elf-bfd.h" -#include "elf/internal.h" - -static char *arm_conditional[] = -{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", - "hi", "ls", "ge", "lt", "gt", "le", "", "nv"}; - -static char *arm_regnames[] = -{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", - "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc"}; - -static char *arm_fp_const[] = -{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; - -static char *arm_shift[] = -{"lsl", "lsr", "asr", "ror"}; - -static int print_insn_arm PARAMS ((bfd_vma, struct disassemble_info *, - long)); - -static void -arm_decode_shift (given, func, stream) - long given; - fprintf_ftype func; - void *stream; -{ - func (stream, "%s", arm_regnames[given & 0xf]); - if ((given & 0xff0) != 0) - { - if ((given & 0x10) == 0) - { - int amount = (given & 0xf80) >> 7; - int shift = (given & 0x60) >> 5; - if (amount == 0) - { - if (shift == 3) - { - func (stream, ", rrx"); - return; - } - amount = 32; - } - func (stream, ", %s #%d", arm_shift[shift], amount); - } - else - func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5], - arm_regnames[(given & 0xf00) >> 8]); - } -} - -/* Print one instruction from PC on INFO->STREAM. - Return the size of the instruction (always 4 on ARM). */ - -static int -print_insn_arm (pc, info, given) - bfd_vma pc; - struct disassemble_info *info; - long given; -{ - struct arm_opcode *insn; - void *stream = info->stream; - fprintf_ftype func = info->fprintf_func; - - for (insn = arm_opcodes; insn->assembler; insn++) - { - if ((given & insn->mask) == insn->value) - { - char *c; - for (c = insn->assembler; *c; c++) - { - if (*c == '%') - { - switch (*++c) - { - case '%': - func (stream, "%%"); - break; - - case 'a': - if (((given & 0x000f0000) == 0x000f0000) - && ((given & 0x02000000) == 0)) - { - int offset = given & 0xfff; - if ((given & 0x00800000) == 0) - offset = -offset; - (*info->print_address_func) - (offset + pc + 8, info); - } - else - { - func (stream, "[%s", - arm_regnames[(given >> 16) & 0xf]); - if ((given & 0x01000000) != 0) - { - if ((given & 0x02000000) == 0) - { - int offset = given & 0xfff; - if (offset) - func (stream, ", %s#%d", - (((given & 0x00800000) == 0) - ? "-" : ""), offset); - } - else - { - func (stream, ", %s", - (((given & 0x00800000) == 0) - ? "-" : "")); - arm_decode_shift (given, func, stream); - } - - func (stream, "]%s", - ((given & 0x00200000) != 0) ? "!" : ""); - } - else - { - if ((given & 0x02000000) == 0) - { - int offset = given & 0xfff; - if (offset) - func (stream, "], %s#%d", - (((given & 0x00800000) == 0) - ? "-" : ""), offset); - else - func (stream, "]"); - } - else - { - func (stream, "], %s", - (((given & 0x00800000) == 0) - ? "-" : "")); - arm_decode_shift (given, func, stream); - } - } - } - break; - - case 's': - if ((given & 0x004f0000) == 0x004f0000) - { - /* PC relative with immediate offset */ - int offset = ((given & 0xf00) >> 4) | (given & 0xf); - if ((given & 0x00800000) == 0) - offset = -offset; - (*info->print_address_func) - (offset + pc + 8, info); - } - else - { - func (stream, "[%s", - arm_regnames[(given >> 16) & 0xf]); - if ((given & 0x01000000) != 0) - { - /* pre-indexed */ - if ((given & 0x00400000) == 0x00400000) - { - /* immediate */ - int offset = ((given & 0xf00) >> 4) | (given & 0xf); - if (offset) - func (stream, ", %s#%d", - (((given & 0x00800000) == 0) - ? "-" : ""), offset); - } - else - { - /* register */ - func (stream, ", %s%s", - (((given & 0x00800000) == 0) - ? "-" : ""), - arm_regnames[given & 0xf]); - } - - func (stream, "]%s", - ((given & 0x00200000) != 0) ? "!" : ""); - } - else - { - /* post-indexed */ - if ((given & 0x00400000) == 0x00400000) - { - /* immediate */ - int offset = ((given & 0xf00) >> 4) | (given & 0xf); - if (offset) - func (stream, "], %s#%d", - (((given & 0x00800000) == 0) - ? "-" : ""), offset); - else - func (stream, "]"); - } - else - { - /* register */ - func (stream, "], %s%s", - (((given & 0x00800000) == 0) - ? "-" : ""), - arm_regnames[given & 0xf]); - } - } - } - break; - - case 'b': - (*info->print_address_func) - (BDISP (given) * 4 + pc + 8, info); - break; - - case 'c': - func (stream, "%s", - arm_conditional [(given >> 28) & 0xf]); - break; - - case 'm': - { - int started = 0; - int reg; - - func (stream, "{"); - for (reg = 0; reg < 16; reg++) - if ((given & (1 << reg)) != 0) - { - if (started) - func (stream, ", "); - started = 1; - func (stream, "%s", arm_regnames[reg]); - } - func (stream, "}"); - } - break; - - case 'o': - if ((given & 0x02000000) != 0) - { - int rotate = (given & 0xf00) >> 7; - int immed = (given & 0xff); - func (stream, "#%d", - ((immed << (32 - rotate)) - | (immed >> rotate)) & 0xffffffff); - } - else - arm_decode_shift (given, func, stream); - break; - - case 'p': - if ((given & 0x0000f000) == 0x0000f000) - func (stream, "p"); - break; - - case 't': - if ((given & 0x01200000) == 0x00200000) - func (stream, "t"); - break; - - case 'h': - if ((given & 0x00000020) == 0x00000020) - func (stream, "h"); - else - func (stream, "b"); - break; - - case 'A': - func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); - if ((given & 0x01000000) != 0) - { - int offset = given & 0xff; - if (offset) - func (stream, ", %s#%d]%s", - ((given & 0x00800000) == 0 ? "-" : ""), - offset * 4, - ((given & 0x00200000) != 0 ? "!" : "")); - else - func (stream, "]"); - } - else - { - int offset = given & 0xff; - if (offset) - func (stream, "], %s#%d", - ((given & 0x00800000) == 0 ? "-" : ""), - offset * 4); - else - func (stream, "]"); - } - break; - - case 'C': - switch (given & 0x00090000) - { - default: - func (stream, "_???"); - break; - case 0x90000: - func (stream, "_all"); - break; - case 0x10000: - func (stream, "_ctl"); - break; - case 0x80000: - func (stream, "_flg"); - break; - } - break; - - case 'F': - switch (given & 0x00408000) - { - case 0: - func (stream, "4"); - break; - case 0x8000: - func (stream, "1"); - break; - case 0x00400000: - func (stream, "2"); - break; - default: - func (stream, "3"); - } - break; - - case 'P': - switch (given & 0x00080080) - { - case 0: - func (stream, "s"); - break; - case 0x80: - func (stream, "d"); - break; - case 0x00080000: - func (stream, "e"); - break; - default: - func (stream, _("<illegal precision>")); - break; - } - break; - case 'Q': - switch (given & 0x00408000) - { - case 0: - func (stream, "s"); - break; - case 0x8000: - func (stream, "d"); - break; - case 0x00400000: - func (stream, "e"); - break; - default: - func (stream, "p"); - break; - } - break; - case 'R': - switch (given & 0x60) - { - case 0: - break; - case 0x20: - func (stream, "p"); - break; - case 0x40: - func (stream, "m"); - break; - default: - func (stream, "z"); - break; - } - break; - - case '0': case '1': case '2': case '3': case '4': - case '5': case '6': case '7': case '8': case '9': - { - int bitstart = *c++ - '0'; - int bitend = 0; - while (*c >= '0' && *c <= '9') - bitstart = (bitstart * 10) + *c++ - '0'; - - switch (*c) - { - case '-': - c++; - while (*c >= '0' && *c <= '9') - bitend = (bitend * 10) + *c++ - '0'; - if (!bitend) - abort (); - switch (*c) - { - case 'r': - { - long reg; - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - func (stream, "%s", arm_regnames[reg]); - } - break; - case 'd': - { - long reg; - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - func (stream, "%d", reg); - } - break; - case 'x': - { - long reg; - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - func (stream, "0x%08x", reg); - } - break; - case 'f': - { - long reg; - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - if (reg > 7) - func (stream, "#%s", - arm_fp_const[reg & 7]); - else - func (stream, "f%d", reg); - } - break; - default: - abort (); - } - break; - case '`': - c++; - if ((given & (1 << bitstart)) == 0) - func (stream, "%c", *c); - break; - case '\'': - c++; - if ((given & (1 << bitstart)) != 0) - func (stream, "%c", *c); - break; - case '?': - ++c; - if ((given & (1 << bitstart)) != 0) - func (stream, "%c", *c++); - else - func (stream, "%c", *++c); - break; - default: - abort (); - } - break; - - default: - abort (); - } - } - } - else - func (stream, "%c", *c); - } - return 4; - } - } - abort (); -} - -/* Print one instruction from PC on INFO->STREAM. - Return the size of the instruction. */ - -static int -print_insn_thumb (pc, info, given) - bfd_vma pc; - struct disassemble_info *info; - long given; -{ - struct thumb_opcode *insn; - void *stream = info->stream; - fprintf_ftype func = info->fprintf_func; - - for (insn = thumb_opcodes; insn->assembler; insn++) - { - if ((given & insn->mask) == insn->value) - { - char *c = insn->assembler; - - /* Special processing for Thumb 2 instruction BL sequence: */ - if (!*c) /* check for empty (not NULL) assembler string */ - { - info->bytes_per_chunk = 4; - info->bytes_per_line = 4; - - func (stream, "%04x\tbl\t", given & 0xffff); - (*info->print_address_func) - (BDISP23 (given) * 2 + pc + 4, info); - return 4; - } - else - { - info->bytes_per_chunk = 2; - info->bytes_per_line = 4; - - given &= 0xffff; - func (stream, "%04x\t", given); - for (; *c; c++) - { - if (*c == '%') - { - int domaskpc = 0; - int domasklr = 0; - switch (*++c) - { - case '%': - func (stream, "%%"); - break; - - case 'S': - { - long reg; - reg = (given >> 3) & 0x7; - if (given & (1 << 6)) - reg += 8; - func (stream, "%s", arm_regnames[reg]); - } - break; - - case 'D': - { - long reg; - reg = given & 0x7; - if (given & (1 << 7)) - reg += 8; - func (stream, "%s", arm_regnames[reg]); - } - break; - - case 'T': - func (stream, "%s", - arm_conditional [(given >> 8) & 0xf]); - break; - - case 'N': - if (given & (1 << 8)) - domasklr = 1; - /* fall through */ - case 'O': - if (*c == 'O' && (given & (1 << 8))) - domaskpc = 1; - /* fall through */ - case 'M': - { - int started = 0; - int reg; - func (stream, "{"); - /* It would be nice if we could spot - ranges, and generate the rS-rE format: */ - for (reg = 0; (reg < 8); reg++) - if ((given & (1 << reg)) != 0) - { - if (started) - func (stream, ", "); - started = 1; - func (stream, "%s", arm_regnames[reg]); - } - - if (domasklr) - { - if (started) - func (stream, ", "); - started = 1; - func (stream, "lr"); - } - - if (domaskpc) - { - if (started) - func (stream, ", "); - func (stream, "pc"); - } - - func (stream, "}"); - } - break; - - - case '0': case '1': case '2': case '3': case '4': - case '5': case '6': case '7': case '8': case '9': - { - int bitstart = *c++ - '0'; - int bitend = 0; - while (*c >= '0' && *c <= '9') - bitstart = (bitstart * 10) + *c++ - '0'; - - switch (*c) - { - case '-': - { - long reg; - c++; - while (*c >= '0' && *c <= '9') - bitend = (bitend * 10) + *c++ - '0'; - if (!bitend) - abort (); - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - switch (*c) - { - case 'r': - func (stream, "%s", arm_regnames[reg]); - break; - - case 'd': - func (stream, "%d", reg); - break; - - case 'H': - func (stream, "%d", reg << 1); - break; - - case 'W': - func (stream, "%d", reg << 2); - break; - - case 'a': - /* PC-relative address -- the bottom two - bits of the address are dropped before - the calculation. */ - info->print_address_func - (((pc + 4) & ~3) + (reg << 2), info); - break; - - case 'x': - func (stream, "0x%04x", reg); - break; - - case 'I': - reg = ((reg ^ (1 << bitend)) - (1 << bitend)); - func (stream, "%d", reg); - break; - - case 'B': - reg = ((reg ^ (1 << bitend)) - (1 << bitend)); - (*info->print_address_func) - (reg * 2 + pc + 4, info); - break; - - default: - abort(); - } - } - break; - - case '\'': - c++; - if ((given & (1 << bitstart)) != 0) - func (stream, "%c", *c); - break; - - case '?': - ++c; - if ((given & (1 << bitstart)) != 0) - func (stream, "%c", *c++); - else - func (stream, "%c", *++c); - break; - - default: - abort(); - } - } - break; - - default: - abort (); - } - } - else - func (stream, "%c", *c); - } - } - return 2; - } - } - - /* no match */ - abort (); -} - -/* NOTE: There are no checks in these routines that the relevant number of data bytes exist */ - -int -print_insn_big_arm (pc, info) - bfd_vma pc; - struct disassemble_info *info; -{ - unsigned char b[4]; - long given; - int status; - coff_symbol_type *cs; - elf_symbol_type *es; - int is_thumb; - - is_thumb = false; - if (info->symbols != NULL) - { - if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour) - { - cs = coffsymbol (*info->symbols); - is_thumb = (cs->native->u.syment.n_sclass == C_THUMBEXT - || cs->native->u.syment.n_sclass == C_THUMBSTAT - || cs->native->u.syment.n_sclass == C_THUMBLABEL - || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC - || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC); - - } - else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour) - { - es = *(elf_symbol_type **)(info->symbols); - is_thumb = ELF_ST_TYPE (es->internal_elf_sym.st_info) == - STT_ARM_TFUNC; - } - } - - info->bytes_per_chunk = 4; - info->display_endian = BFD_ENDIAN_BIG; - - /* Always fetch word aligned values. */ - - status = (*info->read_memory_func) (pc & ~ 0x3, (bfd_byte *) &b[0], 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return -1; - } - - if (is_thumb) - { - if (pc & 0x2) - { - given = (b[2] << 8) | b[3]; - - status = info->read_memory_func ((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info); - if (status != 0) - { - info->memory_error_func (status, pc + 4, info); - return -1; - } - - given |= (b[0] << 24) | (b[1] << 16); - } - else - { - given = (b[0] << 8) | b[1] | (b[2] << 24) | (b[3] << 16); - } - } - else - { - given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]); - } - - if (is_thumb) - { - status = print_insn_thumb (pc, info, given); - } - else - { - status = print_insn_arm (pc, info, given); - } - - return status; -} - -int -print_insn_little_arm (pc, info) - bfd_vma pc; - struct disassemble_info * info; -{ - unsigned char b[4]; - long given; - int status; - coff_symbol_type *cs; - elf_symbol_type *es; - int is_thumb; - - is_thumb = false; - if (info->symbols != NULL) - { - if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour) - { - cs = coffsymbol (*info->symbols); - is_thumb = (cs->native->u.syment.n_sclass == C_THUMBEXT - || cs->native->u.syment.n_sclass == C_THUMBSTAT - || cs->native->u.syment.n_sclass == C_THUMBLABEL - || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC - || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC); - - } - else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour) - { - es = *(elf_symbol_type **)(info->symbols); - is_thumb = ELF_ST_TYPE (es->internal_elf_sym.st_info) == - STT_ARM_TFUNC; - } - } - - info->bytes_per_chunk = 4; - info->display_endian = BFD_ENDIAN_LITTLE; - - status = (*info->read_memory_func) (pc, (bfd_byte *) &b[0], 4, info); - if (status != 0 && is_thumb) - { - info->bytes_per_chunk = 2; - - status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); - b[3] = b[2] = 0; - } - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return -1; - } - - given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); - - if (is_thumb) - { - status = print_insn_thumb (pc, info, given); - } - else - { - status = print_insn_arm (pc, info, given); - } - - return status; -} diff --git a/opcodes/arm-opc.h b/opcodes/arm-opc.h deleted file mode 100644 index f49298fb0cd..00000000000 --- a/opcodes/arm-opc.h +++ /dev/null @@ -1,281 +0,0 @@ -/* Opcode table for the ARM. - - Copyright 1994, 1995, 1996, 1997 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - - -struct arm_opcode { - unsigned long value, mask; /* recognise instruction if (op&mask)==value */ - char *assembler; /* how to disassemble this instruction */ -}; - -struct thumb_opcode -{ - unsigned short value, mask; /* recognise instruction if (op&mask)==value */ - char * assembler; /* how to disassemble this instruction */ -}; - -/* format of the assembler string : - - %% % - %<bitfield>d print the bitfield in decimal - %<bitfield>x print the bitfield in hex - %<bitfield>r print as an ARM register - %<bitfield>f print a floating point constant if >7 else a - floating point register - %c print condition code (always bits 28-31) - %P print floating point precision in arithmetic insn - %Q print floating point precision in ldf/stf insn - %R print floating point rounding mode - %<bitnum>'c print specified char iff bit is one - %<bitnum>`c print specified char iff bit is zero - %<bitnum>?ab print a if bit is one else print b - %p print 'p' iff bits 12-15 are 15 - %t print 't' iff bit 21 set and bit 24 clear - %h print 'h' iff bit 5 set, else print 'b' - %o print operand2 (immediate or register + shift) - %a print address for ldr/str instruction - %s print address for ldr/str halfword/signextend instruction - %b print branch destination - %A print address for ldc/stc/ldf/stf instruction - %m print register mask for ldm/stm instruction - %C print the PSR sub type. - %F print the COUNT field of a LFM/SFM instruction. -Thumb specific format options: - %D print Thumb register (bits 0..2 as high number if bit 7 set) - %S print Thumb register (bits 3..5 as high number if bit 6 set) - %<bitfield>I print bitfield as a signed decimal - (top bit of range being the sign bit) - %M print Thumb register mask - %N print Thumb register mask (with LR) - %O print Thumb register mask (with PC) - %T print Thumb condition code (always bits 8-11) - %<bitfield>B print Thumb branch destination (signed displacement) - %<bitfield>W print (bitfield * 4) as a decimal - %<bitfield>H print (bitfield * 2) as a decimal - %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol -*/ - -/* Note: There is a partial ordering in this table - it must be searched from - the top to obtain a correct match. */ - -static struct arm_opcode arm_opcodes[] = { - /* ARM instructions */ - {0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"}, - {0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, - {0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"}, - {0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"}, - {0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {0x00000090, 0x0e100090, "str%c%6's%h\t%12-15r, %s"}, - {0x00100090, 0x0e100090, "ldr%c%6's%h\t%12-15r, %s"}, - {0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"}, - {0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"}, - {0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"}, - {0x00600000, 0x0de00000, "rsb%c%20's\t%12-15r, %16-19r, %o"}, - {0x00800000, 0x0de00000, "add%c%20's\t%12-15r, %16-19r, %o"}, - {0x00a00000, 0x0de00000, "adc%c%20's\t%12-15r, %16-19r, %o"}, - {0x00c00000, 0x0de00000, "sbc%c%20's\t%12-15r, %16-19r, %o"}, - {0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"}, - {0x0120f000, 0x0db6f000, "msr%c\t%22?scpsr%C, %o"}, - {0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?scpsr"}, - {0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"}, - {0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"}, - {0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"}, - {0x01600000, 0x0de00000, "cmn%c%p\t%16-19r, %o"}, - {0x01800000, 0x0de00000, "orr%c%20's\t%12-15r, %16-19r, %o"}, - {0x01a00000, 0x0de00000, "mov%c%20's\t%12-15r, %o"}, - {0x01c00000, 0x0de00000, "bic%c%20's\t%12-15r, %16-19r, %o"}, - {0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"}, - {0x04000000, 0x0e100000, "str%c%22'b%t\t%12-15r, %a"}, - {0x06000000, 0x0e100ff0, "str%c%22'b%t\t%12-15r, %a"}, - {0x04000000, 0x0c100010, "str%c%22'b%t\t%12-15r, %a"}, - {0x06000010, 0x0e000010, "undefined"}, - {0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"}, - {0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"}, - {0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"}, - {0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, - {0x0f000000, 0x0f000000, "swi%c\t%0-23x"}, - - /* Floating point coprocessor instructions */ - {0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, - {0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, - {0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, - {0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, - {0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, - {0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, - {0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, - {0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, - {0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, - {0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, - {0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, - {0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, - {0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, - {0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, - {0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, - {0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, - {0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, - {0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, - {0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, - {0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, - {0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, - {0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, - {0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, - {0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, - {0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, - {0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, - {0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, - {0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, - {0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, - {0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, - - /* Generic coprocessor instructions */ - {0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, - {0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, - {0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, - {0x0c000000, 0x0e100000, "stc%c%22'l\t%8-11d, cr%12-15d, %A"}, - {0x0c100000, 0x0e100000, "ldc%c%22'l\t%8-11d, cr%12-15d, %A"}, - /* the rest */ - {0x00000000, 0x00000000, "undefined instruction %0-31x"}, - {0x00000000, 0x00000000, 0} -}; - -#define BDISP(x) ((((x) & 0xffffff) ^ 0x800000) - 0x800000) /* 26 bit */ - -static struct thumb_opcode thumb_opcodes[] = -{ - /* Thumb instructions */ - {0x46C0, 0xFFFF, "nop\t\t\t(mov r8,r8)"}, /* format 5 instructions do not update the PSR */ - {0x1C00, 0xFFC0, "mov\t%0-2r, %3-5r\t\t(add %0-2r, %3-5r, #%6-8d)"}, - /* format 4 */ - {0x4000, 0xFFC0, "and\t%0-2r, %3-5r"}, - {0x4040, 0xFFC0, "eor\t%0-2r, %3-5r"}, - {0x4080, 0xFFC0, "lsl\t%0-2r, %3-5r"}, - {0x40C0, 0xFFC0, "lsr\t%0-2r, %3-5r"}, - {0x4100, 0xFFC0, "asr\t%0-2r, %3-5r"}, - {0x4140, 0xFFC0, "adc\t%0-2r, %3-5r"}, - {0x4180, 0xFFC0, "sbc\t%0-2r, %3-5r"}, - {0x41C0, 0xFFC0, "ror\t%0-2r, %3-5r"}, - {0x4200, 0xFFC0, "tst\t%0-2r, %3-5r"}, - {0x4240, 0xFFC0, "neg\t%0-2r, %3-5r"}, - {0x4280, 0xFFC0, "cmp\t%0-2r, %3-5r"}, - {0x42C0, 0xFFC0, "cmn\t%0-2r, %3-5r"}, - {0x4300, 0xFFC0, "orr\t%0-2r, %3-5r"}, - {0x4340, 0xFFC0, "mul\t%0-2r, %3-5r"}, - {0x4380, 0xFFC0, "bic\t%0-2r, %3-5r"}, - {0x43C0, 0xFFC0, "mvn\t%0-2r, %3-5r"}, - /* format 13 */ - {0xB000, 0xFF80, "add\tsp, #%0-6W"}, - {0xB080, 0xFF80, "sub\tsp, #%0-6W"}, - /* format 5 */ - {0x4700, 0xFF80, "bx\t%S"}, - {0x4400, 0xFF00, "add\t%D, %S"}, - {0x4500, 0xFF00, "cmp\t%D, %S"}, - {0x4600, 0xFF00, "mov\t%D, %S"}, - /* format 14 */ - {0xB400, 0xFE00, "push\t%N"}, - {0xBC00, 0xFE00, "pop\t%O"}, - /* format 2 */ - {0x1800, 0xFE00, "add\t%0-2r, %3-5r, %6-8r"}, - {0x1A00, 0xFE00, "sub\t%0-2r, %3-5r, %6-8r"}, - {0x1C00, 0xFE00, "add\t%0-2r, %3-5r, #%6-8d"}, - {0x1E00, 0xFE00, "sub\t%0-2r, %3-5r, #%6-8d"}, - /* format 8 */ - {0x5200, 0xFE00, "strh\t%0-2r, [%3-5r, %6-8r]"}, - {0x5A00, 0xFE00, "ldrh\t%0-2r, [%3-5r, %6-8r]"}, - {0x5600, 0xF600, "lds%11?hb\t%0-2r, [%3-5r, %6-8r]"}, - /* format 7 */ - {0x5000, 0xFA00, "str%10'b\t%0-2r, [%3-5r, %6-8r]"}, - {0x5800, 0xFA00, "ldr%10'b\t%0-2r, [%3-5r, %6-8r]"}, - /* format 1 */ - {0x0000, 0xF800, "lsl\t%0-2r, %3-5r, #%6-10d"}, - {0x0800, 0xF800, "lsr\t%0-2r, %3-5r, #%6-10d"}, - {0x1000, 0xF800, "asr\t%0-2r, %3-5r, #%6-10d"}, - /* format 3 */ - {0x2000, 0xF800, "mov\t%8-10r, #%0-7d"}, - {0x2800, 0xF800, "cmp\t%8-10r, #%0-7d"}, - {0x3000, 0xF800, "add\t%8-10r, #%0-7d"}, - {0x3800, 0xF800, "sub\t%8-10r, #%0-7d"}, - /* format 6 */ - {0x4800, 0xF800, "ldr\t%8-10r, [pc, #%0-7W]\t(%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */ - /* format 9 */ - {0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"}, - {0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"}, - {0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"}, - {0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"}, - /* format 10 */ - {0x8000, 0xF800, "strh\t%0-2r, [%3-5r, #%6-10H]"}, - {0x8800, 0xF800, "ldrh\t%0-2r, [%3-5r, #%6-10H]"}, - /* format 11 */ - {0x9000, 0xF800, "str\t%8-10r, [sp, #%0-7W]"}, - {0x9800, 0xF800, "ldr\t%8-10r, [sp, #%0-7W]"}, - /* format 12 */ - {0xA000, 0xF800, "add\t%8-10r, pc, #%0-7W\t(adr %8-10r,%0-7a)"}, - {0xA800, 0xF800, "add\t%8-10r, sp, #%0-7W"}, - /* format 15 */ - {0xC000, 0xF800, "stmia\t%8-10r!,%M"}, - {0xC800, 0xF800, "ldmia\t%8-10r!,%M"}, - /* format 18 */ - {0xE000, 0xF800, "b\t%0-10B"}, - {0xE800, 0xF800, "undefined"}, - /* format 19 */ - {0xF000, 0xF800, ""}, /* special processing required in disassembler */ - {0xF800, 0xF800, "second half of BL instruction %0-15x"}, - /* format 16 */ - {0xD000, 0xFF00, "beq\t%0-7B"}, - {0xD100, 0xFF00, "bne\t%0-7B"}, - {0xD200, 0xFF00, "bcs\t%0-7B"}, - {0xD300, 0xFF00, "bcc\t%0-7B"}, - {0xD400, 0xFF00, "bmi\t%0-7B"}, - {0xD500, 0xFF00, "bpl\t%0-7B"}, - {0xD600, 0xFF00, "bvs\t%0-7B"}, - {0xD700, 0xFF00, "bvc\t%0-7B"}, - {0xD800, 0xFF00, "bhi\t%0-7B"}, - {0xD900, 0xFF00, "bls\t%0-7B"}, - {0xDA00, 0xFF00, "bge\t%0-7B"}, - {0xDB00, 0xFF00, "blt\t%0-7B"}, - {0xDC00, 0xFF00, "bgt\t%0-7B"}, - {0xDD00, 0xFF00, "ble\t%0-7B"}, - /* format 17 */ - {0xDE00, 0xFF00, "undefined"}, - {0xDF00, 0xFF00, "swi\t%0-7d"}, - /* format 9 */ - {0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"}, - {0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"}, - {0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"}, - {0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"}, - /* the rest */ - {0x0000, 0x0000, "undefined instruction %0-15x"}, - {0x0000, 0x0000, 0} -}; - -#define BDISP23(x) ((((((x) & 0x07ff) << 11) | (((x) & 0x07ff0000) >> 16)) \ - ^ 0x200000) - 0x200000) /* 23bit */ - diff --git a/opcodes/cgen-asm.c b/opcodes/cgen-asm.c deleted file mode 100644 index e522d160157..00000000000 --- a/opcodes/cgen-asm.c +++ /dev/null @@ -1,364 +0,0 @@ -/* CGEN generic assembler support code. - - Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. - - This file is part of the GNU Binutils and GDB, the GNU debugger. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include <stdio.h> -#include <ctype.h> -#include "ansidecl.h" -#include "libiberty.h" -#include "bfd.h" -#include "symcat.h" -#include "opcode/cgen.h" -#include "opintl.h" - -/* Operand parsing callback. */ -const char * (*cgen_parse_operand_fn) - PARAMS ((enum cgen_parse_operand_type, const char **, int, int, - enum cgen_parse_operand_result *, bfd_vma *)); - -/* This is not published as part of the public interface so we don't - declare this in cgen.h. */ -extern CGEN_OPCODE_TABLE *cgen_current_opcode_table; - -/* Assembler instruction hash table. */ -static CGEN_INSN_LIST **asm_hash_table; -static CGEN_INSN_LIST *asm_hash_table_entries; - -/* Called once at startup and whenever machine/endian change. */ - -void -cgen_asm_init () -{ - if (asm_hash_table) - { - free (asm_hash_table); - free (asm_hash_table_entries); - asm_hash_table = NULL; - asm_hash_table_entries = NULL; - } -} - -/* Called whenever starting to parse an insn. */ - -void -cgen_init_parse_operand () -{ - /* This tells the callback to re-initialize. */ - (void) (*cgen_parse_operand_fn) (CGEN_PARSE_OPERAND_INIT, NULL, 0, 0, - NULL, NULL); -} - -/* Subroutine of build_asm_hash_table to add INSNS to the hash table. - - COUNT is the number of elements in INSNS. - ENTSIZE is sizeof (CGEN_INSN) for the target. - This is a bit tricky as the size of the attribute member of CGEN_INSN - is variable among architectures. This code could be moved to - cgen-asm.in, but I prefer to keep it here for now. - OTABLE is the opcode table. - HTABLE points to the hash table. - HENTBUF is a pointer to sufficiently large buffer of hash entries. - The result is a pointer to the next entry to use. - - The table is scanned backwards as additions are made to the front of the - list and we want earlier ones to be prefered. */ - -static CGEN_INSN_LIST * -hash_insn_array (insns, count, entsize, otable, htable, hentbuf) - const CGEN_INSN * insns; - int count; - int entsize; - const CGEN_OPCODE_TABLE * otable; - CGEN_INSN_LIST ** htable; - CGEN_INSN_LIST * hentbuf; -{ - const CGEN_INSN * insn; - - for (insn = (CGEN_INSN *) ((char *) insns + entsize * (count - 1)); - insn >= insns; - insn = (CGEN_INSN *) ((char *) insn - entsize), ++ hentbuf) - { - unsigned int hash; - - if (! (*otable->asm_hash_p) (insn)) - continue; - hash = (*otable->asm_hash) (CGEN_INSN_MNEMONIC (insn)); - hentbuf->next = htable[hash]; - hentbuf->insn = insn; - htable[hash] = hentbuf; - } - - return hentbuf; -} - -/* Subroutine of build_asm_hash_table to add INSNS to the hash table. - This function is identical to hash_insn_array except the insns are - in a list. */ - -static CGEN_INSN_LIST * -hash_insn_list (insns, otable, htable, hentbuf) - const CGEN_INSN_LIST * insns; - const CGEN_OPCODE_TABLE * otable; - CGEN_INSN_LIST ** htable; - CGEN_INSN_LIST * hentbuf; -{ - const CGEN_INSN_LIST * ilist; - - for (ilist = insns; ilist != NULL; ilist = ilist->next, ++ hentbuf) - { - unsigned int hash; - - if (! (*otable->asm_hash_p) (ilist->insn)) - continue; - hash = (*otable->asm_hash) (CGEN_INSN_MNEMONIC (ilist->insn)); - hentbuf->next = htable[hash]; - hentbuf->insn = ilist->insn; - asm_hash_table[hash] = hentbuf; - } - - return hentbuf; -} - -/* Build the assembler instruction hash table. */ - -static void -build_asm_hash_table () -{ - int count = cgen_insn_count () + cgen_macro_insn_count (); - CGEN_OPCODE_TABLE *opcode_table = cgen_current_opcode_table; - CGEN_INSN_TABLE *insn_table = opcode_table->insn_table; - CGEN_INSN_TABLE *macro_insn_table = opcode_table->macro_insn_table; - unsigned int hash_size = opcode_table->asm_hash_table_size; - CGEN_INSN_LIST *hash_entry_buf; - - /* The space allocated for the hash table consists of two parts: - the hash table and the hash lists. */ - - asm_hash_table = (CGEN_INSN_LIST **) - xmalloc (hash_size * sizeof (CGEN_INSN_LIST *)); - memset (asm_hash_table, 0, hash_size * sizeof (CGEN_INSN_LIST *)); - asm_hash_table_entries = hash_entry_buf = (CGEN_INSN_LIST *) - xmalloc (count * sizeof (CGEN_INSN_LIST)); - - /* Add compiled in insns. - Don't include the first one as it is a reserved entry. */ - /* ??? It was the end of all hash chains, and also the special - "illegal insn" marker. May be able to do it differently now. */ - - hash_entry_buf = hash_insn_array ((CGEN_INSN *) ((char *) insn_table->init_entries - + insn_table->entry_size), - insn_table->num_init_entries - 1, - insn_table->entry_size, - opcode_table, asm_hash_table, hash_entry_buf); - - /* Add compiled in macro-insns. */ - - hash_entry_buf = hash_insn_array (macro_insn_table->init_entries, - macro_insn_table->num_init_entries, - macro_insn_table->entry_size, - opcode_table, asm_hash_table, hash_entry_buf); - - /* Add runtime added insns. - Later added insns will be prefered over earlier ones. */ - - hash_entry_buf = hash_insn_list (insn_table->new_entries, opcode_table, - asm_hash_table, hash_entry_buf); - - /* Add runtime added macro-insns. */ - - hash_insn_list (macro_insn_table->new_entries, - opcode_table, asm_hash_table, hash_entry_buf); -} - -/* Return the first entry in the hash list for INSN. - ??? Of course it would be better to pass in a pointer to the - opcode data structure, rather than reference a global. Later. */ - -CGEN_INSN_LIST * -cgen_asm_lookup_insn (insn) - const char *insn; -{ - unsigned int hash; - - if (asm_hash_table == NULL) - build_asm_hash_table (); - - hash = (*cgen_current_opcode_table->asm_hash) (insn); - return asm_hash_table[hash]; -} - -/* Keyword parser. - The result is NULL upon success or an error message. - If successful, *STRP is updated to point passed the keyword. - - ??? At present we have a static notion of how to pick out a keyword. - Later we can allow a target to customize this if necessary [say by - recording something in the keyword table]. */ - -const char * -cgen_parse_keyword (strp, keyword_table, valuep) - const char **strp; - CGEN_KEYWORD *keyword_table; - long *valuep; -{ - const CGEN_KEYWORD_ENTRY *ke; - char buf[256]; - const char *p,*start; - - p = start = *strp; - - /* Allow any first character. - Note that this allows recognizing ",a" for the annul flag in sparc - even though "," is subsequently not a valid keyword char. */ - if (*p) - ++p; - - /* Now allow letters, digits, and _. */ - while (((p - start) < (int) sizeof (buf)) - && (isalnum ((unsigned char) *p) || *p == '_')) - ++p; - - if (p - start >= (int) sizeof (buf)) - return _("unrecognized keyword/register name"); - - memcpy (buf, start, p - start); - buf[p - start] = 0; - - ke = cgen_keyword_lookup_name (keyword_table, buf); - - if (ke != NULL) - { - *valuep = ke->value; - /* Don't advance pointer if we recognized the null keyword. */ - if (ke->name[0] != 0) - *strp = p; - return NULL; - } - - return "unrecognized keyword/register name"; -} - -/* Signed integer parser. */ - -const char * -cgen_parse_signed_integer (strp, opindex, valuep) - const char **strp; - int opindex; - long *valuep; -{ - bfd_vma value; - enum cgen_parse_operand_result result; - const char *errmsg; - - errmsg = (*cgen_parse_operand_fn) (CGEN_PARSE_OPERAND_INTEGER, strp, - opindex, BFD_RELOC_NONE, - &result, &value); - /* FIXME: Examine `result'. */ - if (!errmsg) - *valuep = value; - return errmsg; -} - -/* Unsigned integer parser. */ - -const char * -cgen_parse_unsigned_integer (strp, opindex, valuep) - const char **strp; - int opindex; - unsigned long *valuep; -{ - bfd_vma value; - enum cgen_parse_operand_result result; - const char *errmsg; - - errmsg = (*cgen_parse_operand_fn) (CGEN_PARSE_OPERAND_INTEGER, strp, - opindex, BFD_RELOC_NONE, - &result, &value); - /* FIXME: Examine `result'. */ - if (!errmsg) - *valuep = value; - return errmsg; -} - -/* Address parser. */ - -const char * -cgen_parse_address (strp, opindex, opinfo, resultp, valuep) - const char **strp; - int opindex; - int opinfo; - enum cgen_parse_operand_result *resultp; - long *valuep; -{ - bfd_vma value; - enum cgen_parse_operand_result result_type; - const char *errmsg; - - errmsg = (*cgen_parse_operand_fn) (CGEN_PARSE_OPERAND_ADDRESS, strp, - opindex, opinfo, - &result_type, &value); - /* FIXME: Examine `result'. */ - if (!errmsg) - { - if (resultp != NULL) - *resultp = result_type; - *valuep = value; - } - return errmsg; -} - -/* Signed integer validation routine. */ - -const char * -cgen_validate_signed_integer (value, min, max) - long value, min, max; -{ - if (value < min || value > max) - { - static char buf[100]; - - /* xgettext:c-format */ - sprintf (buf, _("operand out of range (%ld not between %ld and %ld)"), - value, min, max); - return buf; - } - - return NULL; -} - -/* Unsigned integer validation routine. - Supplying `min' here may seem unnecessary, but we also want to handle - cases where min != 0 (and max > LONG_MAX). */ - -const char * -cgen_validate_unsigned_integer (value, min, max) - unsigned long value, min, max; -{ - if (value < min || value > max) - { - static char buf[100]; - - sprintf (buf, _("operand out of range (%lu not between %lu and %lu)"), - value, min, max); - return buf; - } - - return NULL; -} diff --git a/opcodes/cgen-asm.in b/opcodes/cgen-asm.in deleted file mode 100644 index 27d6bb64022..00000000000 --- a/opcodes/cgen-asm.in +++ /dev/null @@ -1,534 +0,0 @@ -/* Assembler interface for targets using CGEN. -*- C -*- - CGEN: Cpu tools GENerator - -THIS FILE IS USED TO GENERATE @prefix@-asm.c. - -Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. - -This file is part of the GNU Binutils and GDB, the GNU debugger. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include <ctype.h> -#include <stdio.h> -#include "ansidecl.h" -#include "bfd.h" -#include "symcat.h" -#include "@prefix@-opc.h" -#include "opintl.h" - -#undef min -#define min(a,b) ((a) < (b) ? (a) : (b)) -#undef max -#define max(a,b) ((a) > (b) ? (a) : (b)) - -#undef INLINE -#ifdef __GNUC__ -#define INLINE __inline__ -#else -#define INLINE -#endif - -/* Used by the ifield rtx function. */ -#define FLD(f) (fields->f) - -static const char * insert_normal - PARAMS ((CGEN_OPCODE_DESC, long, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); -static const char * parse_insn_normal - PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *, - const char **, CGEN_FIELDS *)); -static const char * insert_insn_normal - PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *, - CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); - -/* -- assembler routines inserted here */ - -#if ! CGEN_INT_INSN_P - -/* Subroutine of insert_normal. */ - -static INLINE void -insert_1 (od, value, start, length, word_length, bufp) - CGEN_OPCODE_DESC od; - unsigned long value; - int start,length,word_length; - unsigned char *bufp; -{ - unsigned long x,mask; - int shift; - int big_p = CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG; - - switch (word_length) - { - case 8: - x = *bufp; - break; - case 16: - if (big_p) - x = bfd_getb16 (bufp); - else - x = bfd_getl16 (bufp); - break; - case 24: - /* ??? This may need reworking as these cases don't necessarily - want the first byte and the last two bytes handled like this. */ - if (big_p) - x = (bufp[0] << 16) | bfd_getb16 (bufp + 1); - else - x = bfd_getl16 (bufp) | (bufp[2] << 16); - break; - case 32: - if (big_p) - x = bfd_getb32 (bufp); - else - x = bfd_getl32 (bufp); - break; - default : - abort (); - } - - /* Written this way to avoid undefined behaviour. */ - mask = (((1L << (length - 1)) - 1) << 1) | 1; - if (CGEN_INSN_LSB0_P) - shift = (start + 1) - length; - else - shift = (word_length - (start + length)); - x = (x & ~(mask << shift)) | ((value & mask) << shift); - - switch (word_length) - { - case 8: - *bufp = x; - break; - case 16: - if (big_p) - bfd_putb16 (x, bufp); - else - bfd_putl16 (x, bufp); - break; - case 24: - /* ??? This may need reworking as these cases don't necessarily - want the first byte and the last two bytes handled like this. */ - if (big_p) - { - bufp[0] = x >> 16; - bfd_putb16 (x, bufp + 1); - } - else - { - bfd_putl16 (x, bufp); - bufp[2] = x >> 16; - } - break; - case 32: - if (big_p) - bfd_putb32 (x, bufp); - else - bfd_putl32 (x, bufp); - break; - default : - abort (); - } -} - -#endif /* ! CGEN_INT_INSN_P */ - -/* Default insertion routine. - - ATTRS is a mask of the boolean attributes. - WORD_OFFSET is the offset in bits from the start of the insn of the value. - WORD_LENGTH is the length of the word in bits in which the value resides. - START is the starting bit number in the word, architecture origin. - LENGTH is the length of VALUE in bits. - TOTAL_LENGTH is the total length of the insn in bits. - - The result is an error message or NULL if success. */ - -/* ??? This duplicates functionality with bfd's howto table and - bfd_install_relocation. */ -/* ??? This doesn't handle bfd_vma's. Create another function when - necessary. */ - -static const char * -insert_normal (od, value, attrs, word_offset, start, length, word_length, - total_length, buffer) - CGEN_OPCODE_DESC od; - long value; - unsigned int attrs; - unsigned int word_offset, start, length, word_length, total_length; - CGEN_INSN_BYTES_PTR buffer; -{ - static char errbuf[100]; - /* Written this way to avoid undefined behaviour. */ - unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; - - /* If LENGTH is zero, this operand doesn't contribute to the value. */ - if (length == 0) - return NULL; - - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); - - if (word_length > 32) - abort (); - - /* For architectures with insns smaller than the insn-base-bitsize, - word_length may be too big. */ -#if CGEN_MIN_INSN_BITSIZE < CGEN_BASE_INSN_BITSIZE - if (word_offset == 0 - && word_length > total_length) - word_length = total_length; -#endif - - /* Ensure VALUE will fit. */ - if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED)) - { - unsigned long maxval = mask; - if ((unsigned long) value > maxval) - { - /* xgettext:c-format */ - sprintf (errbuf, - _("operand out of range (%lu not between 0 and %lu)"), - value, maxval); - return errbuf; - } - } - else - { - long minval = - (1L << (length - 1)); - long maxval = (1L << (length - 1)) - 1; - if (value < minval || value > maxval) - { - sprintf - /* xgettext:c-format */ - (errbuf, _("operand out of range (%ld not between %ld and %ld)"), - value, minval, maxval); - return errbuf; - } - } - -#if CGEN_INT_INSN_P - - { - int shift; - - if (CGEN_INSN_LSB0_P) - shift = (start + 1) - length; - else - shift = word_length - (start + length); - *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); - } - -#else /* ! CGEN_INT_INSN_P */ - - { - unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; - - insert_1 (od, value, start, length, word_length, bufp); - } - -#endif /* ! CGEN_INT_INSN_P */ - - return NULL; -} - -/* Default insn parser. - - The syntax string is scanned and operands are parsed and stored in FIELDS. - Relocs are queued as we go via other callbacks. - - ??? Note that this is currently an all-or-nothing parser. If we fail to - parse the instruction, we return 0 and the caller will start over from - the beginning. Backtracking will be necessary in parsing subexpressions, - but that can be handled there. Not handling backtracking here may get - expensive in the case of the m68k. Deal with later. - - Returns NULL for success, an error message for failure. -*/ - -static const char * -parse_insn_normal (od, insn, strp, fields) - CGEN_OPCODE_DESC od; - const CGEN_INSN * insn; - const char ** strp; - CGEN_FIELDS * fields; -{ - const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn); - const char * str = *strp; - const char * errmsg; - const char * p; - const unsigned char * syn; -#ifdef CGEN_MNEMONIC_OPERANDS - /* FIXME: wip */ - int past_opcode_p; -#endif - - /* For now we assume the mnemonic is first (there are no leading operands). - We can parse it without needing to set up operand parsing. - GAS's input scrubber will ensure mnemonics are lowercase, but we may - not be called from GAS. */ - p = CGEN_INSN_MNEMONIC (insn); - while (*p && tolower (*p) == tolower (*str)) - ++p, ++str; - - if (* p || (* str && !isspace (* str))) - return _("unrecognized instruction"); - - CGEN_INIT_PARSE (od); - cgen_init_parse_operand (od); -#ifdef CGEN_MNEMONIC_OPERANDS - past_opcode_p = 0; -#endif - - /* We don't check for (*str != '\0') here because we want to parse - any trailing fake arguments in the syntax string. */ - syn = CGEN_SYNTAX_STRING (syntax); - - /* Mnemonics come first for now, ensure valid string. */ - if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) - abort (); - - ++syn; - - while (* syn != 0) - { - /* Non operand chars must match exactly. */ - if (CGEN_SYNTAX_CHAR_P (* syn)) - { - if (*str == CGEN_SYNTAX_CHAR (* syn)) - { -#ifdef CGEN_MNEMONIC_OPERANDS - if (* syn == ' ') - past_opcode_p = 1; -#endif - ++ syn; - ++ str; - } - else - { - /* Syntax char didn't match. Can't be this insn. */ - /* FIXME: would like to return something like - "expected char `c'" */ - return _("syntax error"); - } - continue; - } - - /* We have an operand of some sort. */ - errmsg = @arch@_cgen_parse_operand (od, CGEN_SYNTAX_FIELD (*syn), - &str, fields); - if (errmsg) - return errmsg; - - /* Done with this operand, continue with next one. */ - ++ syn; - } - - /* If we're at the end of the syntax string, we're done. */ - if (* syn == '\0') - { - /* FIXME: For the moment we assume a valid `str' can only contain - blanks now. IE: We needn't try again with a longer version of - the insn and it is assumed that longer versions of insns appear - before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ - while (isspace (* str)) - ++ str; - - if (* str != '\0') - return _("junk at end of line"); /* FIXME: would like to include `str' */ - - return NULL; - } - - /* We couldn't parse it. */ - return _("unrecognized instruction"); -} - -/* Default insn builder (insert handler). - The instruction is recorded in CGEN_INT_INSN_P byte order - (meaning that if CGEN_INT_INSN_P BUFFER is an int * and thus the value is - recorded in host byte order, otherwise BUFFER is an array of bytes and the - value is recorded in target byte order). - The result is an error message or NULL if success. */ - -static const char * -insert_insn_normal (od, insn, fields, buffer, pc) - CGEN_OPCODE_DESC od; - const CGEN_INSN * insn; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc; -{ - const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn); - unsigned long value; - const unsigned char * syn; - - CGEN_INIT_INSERT (od); - value = CGEN_INSN_BASE_VALUE (insn); - - /* If we're recording insns as numbers (rather than a string of bytes), - target byte order handling is deferred until later. */ - -#if CGEN_INT_INSN_P - - *buffer = value; - -#else - - cgen_put_insn_value (od, buffer, min (CGEN_BASE_INSN_BITSIZE, - CGEN_FIELDS_BITSIZE (fields)), - value); - -#endif /* ! CGEN_INT_INSN_P */ - - /* ??? It would be better to scan the format's fields. - Still need to be able to insert a value based on the operand though; - e.g. storing a branch displacement that got resolved later. - Needs more thought first. */ - - for (syn = CGEN_SYNTAX_STRING (syntax); * syn != '\0'; ++ syn) - { - const char *errmsg; - - if (CGEN_SYNTAX_CHAR_P (* syn)) - continue; - - errmsg = @arch@_cgen_insert_operand (od, CGEN_SYNTAX_FIELD (*syn), - fields, buffer, pc); - if (errmsg) - return errmsg; - } - - return NULL; -} - -/* Main entry point. - This routine is called for each instruction to be assembled. - STR points to the insn to be assembled. - We assume all necessary tables have been initialized. - The assembled instruction, less any fixups, is stored in BUF. - Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value - still needs to be converted to target byte order, otherwise BUF is an array - of bytes in target byte order. - The result is a pointer to the insn's entry in the opcode table, - or NULL if an error occured (an error message will have already been - printed). - - Note that when processing (non-alias) macro-insns, - this function recurses. */ - -const CGEN_INSN * -@arch@_cgen_assemble_insn (od, str, fields, buf, errmsg) - CGEN_OPCODE_DESC od; - const char * str; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buf; - char ** errmsg; -{ - const char * start; - CGEN_INSN_LIST * ilist; - - /* Skip leading white space. */ - while (isspace (* str)) - ++ str; - - /* The instructions are stored in hashed lists. - Get the first in the list. */ - ilist = CGEN_ASM_LOOKUP_INSN (od, str); - - /* Keep looking until we find a match. */ - - start = str; - for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) - { - const CGEN_INSN *insn = ilist->insn; - -#if 0 /* not needed as unsupported opcodes shouldn't be in the hash lists */ - /* Is this insn supported by the selected cpu? */ - if (! @arch@_cgen_insn_supported (od, insn)) - continue; -#endif - - /* If the RELAX attribute is set, this is an insn that shouldn't be - chosen immediately. Instead, it is used during assembler/linker - relaxation if possible. */ - if (CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX) != 0) - continue; - - str = start; - - /* Allow parse/insert handlers to obtain length of insn. */ - CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); - - if (! CGEN_PARSE_FN (insn) (od, insn, & str, fields)) - { - /* ??? 0 is passed for `pc' */ - if (CGEN_INSERT_FN (insn) (od, insn, fields, buf, (bfd_vma) 0) != NULL) - continue; - /* It is up to the caller to actually output the insn and any - queued relocs. */ - return insn; - } - - /* Try the next entry. */ - } - - /* FIXME: We can return a better error message than this. - Need to track why it failed and pick the right one. */ - { - static char errbuf[100]; - if (strlen (start) > 50) - /* xgettext:c-format */ - sprintf (errbuf, _("bad instruction `%.50s...'"), start); - else - /* xgettext:c-format */ - sprintf (errbuf, _("bad instruction `%.50s'"), start); - - *errmsg = errbuf; - return NULL; - } -} - -#if 0 /* This calls back to GAS which we can't do without care. */ - -/* Record each member of OPVALS in the assembler's symbol table. - This lets GAS parse registers for us. - ??? Interesting idea but not currently used. */ - -/* Record each member of OPVALS in the assembler's symbol table. - FIXME: Not currently used. */ - -void -@arch@_cgen_asm_hash_keywords (od, opvals) - CGEN_OPCODE_DESC od; - CGEN_KEYWORD * opvals; -{ - CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); - const CGEN_KEYWORD_ENTRY * ke; - - while ((ke = cgen_keyword_search_next (& search)) != NULL) - { -#if 0 /* Unnecessary, should be done in the search routine. */ - if (! @arch@_cgen_opval_supported (ke)) - continue; -#endif - cgen_asm_record_register (od, ke->name, ke->value); - } -} - -#endif /* 0 */ diff --git a/opcodes/cgen-dis.c b/opcodes/cgen-dis.c deleted file mode 100644 index 0f7a170dda1..00000000000 --- a/opcodes/cgen-dis.c +++ /dev/null @@ -1,168 +0,0 @@ -/* CGEN generic disassembler support code. - - Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. - - This file is part of the GNU Binutils and GDB, the GNU debugger. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include <stdio.h> -#include "ansidecl.h" -#include "libiberty.h" -#include "bfd.h" -#include "opcode/cgen.h" - -/* This is not published as part of the public interface so we don't - declare this in cgen.h. */ -extern CGEN_OPCODE_DATA *cgen_current_opcode_data; - -/* Disassembler instruction hash table. */ -static CGEN_INSN_LIST **dis_hash_table; - -void -cgen_dis_init () -{ - if (dis_hash_table) - { - free (dis_hash_table); - dis_hash_table = NULL; - } -} - -/* Build the disassembler instruction hash table. */ - -static void -build_dis_hash_table () -{ - int i; - int big_p = cgen_current_endian == CGEN_ENDIAN_BIG; - unsigned int hash; - char buf[4]; - unsigned long value; - int count = cgen_insn_count (); - CGEN_OPCODE_DATA *data = cgen_current_opcode_data; - CGEN_INSN_TABLE *insn_table = data->insn_table; - unsigned int entry_size = insn_table->entry_size; - unsigned int hash_size = insn_table->dis_hash_table_size; - const CGEN_INSN *insn; - CGEN_INSN_LIST *insn_lists,*new_insns; - - /* The space allocated for the hash table consists of two parts: - the hash table and the hash lists. */ - - dis_hash_table = (CGEN_INSN_LIST **) - xmalloc (hash_size * sizeof (CGEN_INSN_LIST *) - + count * sizeof (CGEN_INSN_LIST)); - memset (dis_hash_table, 0, - hash_size * sizeof (CGEN_INSN_LIST *) - + count * sizeof (CGEN_INSN_LIST)); - insn_lists = (CGEN_INSN_LIST *) (dis_hash_table + hash_size); - - /* Add compiled in insns. - The table is scanned backwards as later additions are inserted in - front of earlier ones and we want earlier ones to be prefered. - We stop at the first one as it is a reserved entry. - This is a bit tricky as the attribute member of CGEN_INSN is variable - among architectures. This code could be moved to cgen-asm.in, but - I prefer to keep it here for now. */ - - for (insn = (CGEN_INSN *) - ((char *) insn_table->init_entries - + entry_size * (insn_table->num_init_entries - 1)); - insn > insn_table->init_entries; - insn = (CGEN_INSN *) ((char *) insn - entry_size), ++insn_lists) - { - /* We don't know whether the target uses the buffer or the base insn - to hash on, so set both up. */ - value = CGEN_INSN_VALUE (insn); - switch (CGEN_INSN_MASK_BITSIZE (insn)) - { - case 8: - buf[0] = value; - break; - case 16: - if (big_p) - bfd_putb16 ((bfd_vma) value, buf); - else - bfd_putl16 ((bfd_vma) value, buf); - break; - case 32: - if (big_p) - bfd_putb32 ((bfd_vma) value, buf); - else - bfd_putl32 ((bfd_vma) value, buf); - break; - default: - abort (); - } - hash = (*insn_table->dis_hash) (buf, value); - insn_lists->next = dis_hash_table[hash]; - insn_lists->insn = insn; - dis_hash_table[hash] = insn_lists; - } - - /* Add runtime added insns. - ??? Currently later added insns will be prefered over earlier ones. - Not sure this is a bug or not. */ - for (new_insns = insn_table->new_entries; - new_insns != NULL; - new_insns = new_insns->next, ++insn_lists) - { - /* We don't know whether the target uses the buffer or the base insn - to hash on, so set both up. */ - value = CGEN_INSN_VALUE (new_insns->insn); - switch (CGEN_INSN_MASK_BITSIZE (new_insns->insn)) - { - case 8: - buf[0] = value; - break; - case 16: - if (big_p) - bfd_putb16 ((bfd_vma) value, buf); - else - bfd_putl16 ((bfd_vma) value, buf); - break; - case 32: - if (big_p) - bfd_putb32 ((bfd_vma) value, buf); - else - bfd_putl32 ((bfd_vma) value, buf); - break; - default: - abort (); - } - hash = (*insn_table->dis_hash) (buf, value); - insn_lists->next = dis_hash_table[hash]; - insn_lists->insn = new_insns->insn; - dis_hash_table[hash] = insn_lists; - } -} - -/* Return the first entry in the hash list for INSN. */ - -CGEN_INSN_LIST * -cgen_dis_lookup_insn (buf, value) - const char *buf; - unsigned long value; -{ - unsigned int hash; - - if (dis_hash_table == NULL) - build_dis_hash_table (); - - hash = (*cgen_current_opcode_data->insn_table->dis_hash) (buf, value); - return dis_hash_table[hash]; -} diff --git a/opcodes/cgen-dis.in b/opcodes/cgen-dis.in deleted file mode 100644 index 31a6afd9954..00000000000 --- a/opcodes/cgen-dis.in +++ /dev/null @@ -1,582 +0,0 @@ -/* Disassembler interface for targets using CGEN. -*- C -*- - CGEN: Cpu tools GENerator - -THIS FILE IS USED TO GENERATE @prefix@-dis.c. - -Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. - -This file is part of the GNU Binutils and GDB, the GNU debugger. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include <stdio.h> -#include "ansidecl.h" -#include "dis-asm.h" -#include "bfd.h" -#include "symcat.h" -#include "@prefix@-opc.h" -#include "opintl.h" - -#undef INLINE -#ifdef __GNUC__ -#define INLINE __inline__ -#else -#define INLINE -#endif - -/* Default text to print if an instruction isn't recognized. */ -#define UNKNOWN_INSN_MSG _("*unknown*") - -/* Used by the ifield rtx function. */ -#define FLD(f) (fields->f) - -static int extract_normal - PARAMS ((CGEN_OPCODE_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - unsigned int, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, bfd_vma, long *)); -static void print_normal - PARAMS ((CGEN_OPCODE_DESC, PTR, long, unsigned int, bfd_vma, int)); -static void print_address - PARAMS ((CGEN_OPCODE_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); -static void print_keyword - PARAMS ((CGEN_OPCODE_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); -static int extract_insn_normal - PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, - CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); -static void print_insn_normal - PARAMS ((CGEN_OPCODE_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, - bfd_vma, int)); -static int print_insn PARAMS ((CGEN_OPCODE_DESC, bfd_vma, - disassemble_info *, char *, int)); -static int default_print_insn - PARAMS ((CGEN_OPCODE_DESC, bfd_vma, disassemble_info *)); - -/* -- disassembler routines inserted here */ - -#if ! CGEN_INT_INSN_P - -/* Subroutine of extract_normal. - Ensure sufficient bytes are cached in EX_INFO. - OFFSET is the offset in bytes from the start of the insn of the value. - BYTES is the length of the needed value. - Returns 1 for success, 0 for failure. */ - -static INLINE int -fill_cache (od, ex_info, offset, bytes, pc) - CGEN_OPCODE_DESC od; - CGEN_EXTRACT_INFO *ex_info; - int offset, bytes; - bfd_vma pc; -{ - /* It's doubtful that the middle part has already been fetched so - we don't optimize that case. kiss. */ - int mask; - disassemble_info *info = (disassemble_info *) ex_info->dis_info; - - /* First do a quick check. */ - mask = (1 << bytes) - 1; - if (((ex_info->valid >> offset) & mask) == mask) - return 1; - - /* Search for the first byte we need to read. */ - for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) - if (! (mask & ex_info->valid)) - break; - - if (bytes) - { - int status; - - pc += offset; - status = (*info->read_memory_func) - (pc, ex_info->insn_bytes + offset, bytes, info); - - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return 0; - } - - ex_info->valid |= ((1 << bytes) - 1) << offset; - } - - return 1; -} - -/* Subroutine of extract_normal. */ - -static INLINE long -extract_1 (od, ex_info, start, length, word_length, bufp, pc) - CGEN_OPCODE_DESC od; - CGEN_EXTRACT_INFO *ex_info; - int start,length,word_length; - unsigned char *bufp; - bfd_vma pc; -{ - unsigned long x,mask; - int shift; - int big_p = CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG; - - switch (word_length) - { - case 8: - x = *bufp; - break; - case 16: - if (big_p) - x = bfd_getb16 (bufp); - else - x = bfd_getl16 (bufp); - break; - case 24: - /* ??? This may need reworking as these cases don't necessarily - want the first byte and the last two bytes handled like this. */ - if (big_p) - x = (bufp[0] << 16) | bfd_getb16 (bufp + 1); - else - x = bfd_getl16 (bufp) | (bufp[2] << 16); - break; - case 32: - if (big_p) - x = bfd_getb32 (bufp); - else - x = bfd_getl32 (bufp); - break; - default : - abort (); - } - - /* Written this way to avoid undefined behaviour. */ - mask = (((1L << (length - 1)) - 1) << 1) | 1; - if (CGEN_INSN_LSB0_P) - shift = (start + 1) - length; - else - shift = (word_length - (start + length)); - return (x >> shift) & mask; -} - -#endif /* ! CGEN_INT_INSN_P */ - -/* Default extraction routine. - - INSN_VALUE is the first CGEN_BASE_INSN_SIZE bits of the insn in host order, - or sometimes less for cases like the m32r where the base insn size is 32 - but some insns are 16 bits. - ATTRS is a mask of the boolean attributes. We only need `UNSIGNED', - but for generality we take a bitmask of all of them. - WORD_OFFSET is the offset in bits from the start of the insn of the value. - WORD_LENGTH is the length of the word in bits in which the value resides. - START is the starting bit number in the word, architecture origin. - LENGTH is the length of VALUE in bits. - TOTAL_LENGTH is the total length of the insn in bits. - - Returns 1 for success, 0 for failure. */ - -/* ??? The return code isn't properly used. wip. */ - -/* ??? This doesn't handle bfd_vma's. Create another function when - necessary. */ - -static int -extract_normal (od, ex_info, insn_value, attrs, word_offset, start, length, - word_length, total_length, pc, valuep) - CGEN_OPCODE_DESC od; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - unsigned int attrs; - unsigned int word_offset, start, length, word_length, total_length; - bfd_vma pc; - long *valuep; -{ - CGEN_INSN_INT value; - - /* If LENGTH is zero, this operand doesn't contribute to the value - so give it a standard value of zero. */ - if (length == 0) - { - *valuep = 0; - return 1; - } - - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); - - if (word_length > 32) - abort (); - - /* For architectures with insns smaller than the insn-base-bitsize, - word_length may be too big. */ -#if CGEN_MIN_INSN_BITSIZE < CGEN_BASE_INSN_BITSIZE - if (word_offset == 0 - && word_length > total_length) - word_length = total_length; -#endif - - /* Does the value reside in INSN_VALUE? */ - - if (word_offset == 0) - { - /* Written this way to avoid undefined behaviour. */ - CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; - - if (CGEN_INSN_LSB0_P) - value = insn_value >> ((start + 1) - length); - else - value = insn_value >> (word_length - (start + length)); - value &= mask; - /* sign extend? */ - if (! CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED) - && (value & (1L << (length - 1)))) - value |= ~mask; - } - -#if ! CGEN_INT_INSN_P - - else - { - unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; - - if (word_length > 32) - abort (); - - if (fill_cache (od, ex_info, word_offset / 8, word_length / 8, pc) == 0) - return 0; - - value = extract_1 (od, ex_info, start, length, word_length, bufp, pc); - } - -#endif /* ! CGEN_INT_INSN_P */ - - *valuep = value; - - return 1; -} - -/* Default print handler. */ - -static void -print_normal (od, dis_info, value, attrs, pc, length) - CGEN_OPCODE_DESC od; - PTR dis_info; - long value; - unsigned int attrs; - bfd_vma pc; - int length; -{ - disassemble_info *info = (disassemble_info *) dis_info; - -#ifdef CGEN_PRINT_NORMAL - CGEN_PRINT_NORMAL (od, info, value, attrs, pc, length); -#endif - - /* Print the operand as directed by the attributes. */ - if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) - ; /* nothing to do */ - else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED)) - (*info->fprintf_func) (info->stream, "0x%lx", value); - else - (*info->fprintf_func) (info->stream, "%ld", value); -} - -/* Default address handler. */ - -static void -print_address (od, dis_info, value, attrs, pc, length) - CGEN_OPCODE_DESC od; - PTR dis_info; - bfd_vma value; - unsigned int attrs; - bfd_vma pc; - int length; -{ - disassemble_info *info = (disassemble_info *) dis_info; - -#ifdef CGEN_PRINT_ADDRESS - CGEN_PRINT_ADDRESS (od, info, value, attrs, pc, length); -#endif - - /* Print the operand as directed by the attributes. */ - if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) - ; /* nothing to do */ - else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) - (*info->print_address_func) (value, info); - else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) - (*info->print_address_func) (value, info); - else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED)) - (*info->fprintf_func) (info->stream, "0x%lx", (long) value); - else - (*info->fprintf_func) (info->stream, "%ld", (long) value); -} - -/* Keyword print handler. */ - -static void -print_keyword (od, dis_info, keyword_table, value, attrs) - CGEN_OPCODE_DESC od; - PTR dis_info; - CGEN_KEYWORD *keyword_table; - long value; - unsigned int attrs; -{ - disassemble_info *info = (disassemble_info *) dis_info; - const CGEN_KEYWORD_ENTRY *ke; - - ke = cgen_keyword_lookup_value (keyword_table, value); - if (ke != NULL) - (*info->fprintf_func) (info->stream, "%s", ke->name); - else - (*info->fprintf_func) (info->stream, "???"); -} - -/* Default insn extractor. - - INSN_VALUE is the first CGEN_BASE_INSN_SIZE bytes, translated to host order. - The extracted fields are stored in FIELDS. - EX_INFO is used to handle reading variable length insns. - Return the length of the insn in bits, or 0 if no match, - or -1 if an error occurs fetching data (memory_error_func will have - been called). */ - -static int -extract_insn_normal (od, insn, ex_info, insn_value, fields, pc) - CGEN_OPCODE_DESC od; - const CGEN_INSN *insn; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - CGEN_FIELDS *fields; - bfd_vma pc; -{ - const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); - const unsigned char *syn; - - CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); - - CGEN_INIT_EXTRACT (od); - - for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) - { - int length; - - if (CGEN_SYNTAX_CHAR_P (*syn)) - continue; - - length = @arch@_cgen_extract_operand (od, CGEN_SYNTAX_FIELD (*syn), - ex_info, insn_value, fields, pc); - if (length <= 0) - return length; - } - - /* We recognized and successfully extracted this insn. */ - return CGEN_INSN_BITSIZE (insn); -} - -/* Default insn printer. - - DIS_INFO is defined as `PTR' so the disassembler needn't know anything - about disassemble_info. */ - -static void -print_insn_normal (od, dis_info, insn, fields, pc, length) - CGEN_OPCODE_DESC od; - PTR dis_info; - const CGEN_INSN *insn; - CGEN_FIELDS *fields; - bfd_vma pc; - int length; -{ - const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); - disassemble_info *info = (disassemble_info *) dis_info; - const unsigned char *syn; - - CGEN_INIT_PRINT (od); - - for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) - { - if (CGEN_SYNTAX_MNEMONIC_P (*syn)) - { - (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); - continue; - } - if (CGEN_SYNTAX_CHAR_P (*syn)) - { - (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); - continue; - } - - /* We have an operand. */ - @arch@_cgen_print_operand (od, CGEN_SYNTAX_FIELD (*syn), info, - fields, CGEN_INSN_ATTRS (insn), pc, length); - } -} - -/* Utility to print an insn. - BUF is the base part of the insn, target byte order, BUFLEN bytes long. - The result is the size of the insn in bytes or zero for an unknown insn - or -1 if an error occurs fetching data (memory_error_func will have - been called). */ - -static int -print_insn (od, pc, info, buf, buflen) - CGEN_OPCODE_DESC od; - bfd_vma pc; - disassemble_info *info; - char *buf; - int buflen; -{ - unsigned long insn_value; - const CGEN_INSN_LIST *insn_list; - CGEN_EXTRACT_INFO ex_info; - - ex_info.dis_info = info; - ex_info.valid = (1 << CGEN_BASE_INSN_SIZE) - 1; - ex_info.insn_bytes = buf; - - switch (buflen) - { - case 1: - insn_value = buf[0]; - break; - case 2: - insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf); - break; - case 4: - insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf); - break; - default: - abort (); - } - - /* The instructions are stored in hash lists. - Pick the first one and keep trying until we find the right one. */ - - insn_list = CGEN_DIS_LOOKUP_INSN (od, buf, insn_value); - while (insn_list != NULL) - { - const CGEN_INSN *insn = insn_list->insn; - CGEN_FIELDS fields; - int length; - -#if 0 /* not needed as insn shouldn't be in hash lists if not supported */ - /* Supported by this cpu? */ - if (! @arch@_cgen_insn_supported (od, insn)) - continue; -#endif - - /* Basic bit mask must be correct. */ - /* ??? May wish to allow target to defer this check until the extract - handler. */ - if ((insn_value & CGEN_INSN_BASE_MASK (insn)) - == CGEN_INSN_BASE_VALUE (insn)) - { - /* Printing is handled in two passes. The first pass parses the - machine insn and extracts the fields. The second pass prints - them. */ - - length = (*CGEN_EXTRACT_FN (insn)) (od, insn, &ex_info, insn_value, - &fields, pc); - /* length < 0 -> error */ - if (length < 0) - return length; - if (length > 0) - { - (*CGEN_PRINT_FN (insn)) (od, info, insn, &fields, pc, length); - /* length is in bits, result is in bytes */ - return length / 8; - } - } - - insn_list = CGEN_DIS_NEXT_INSN (insn_list); - } - - return 0; -} - -/* Default value for CGEN_PRINT_INSN. - The result is the size of the insn in bytes or zero for an unknown insn - or -1 if an error occured fetching bytes. */ - -#ifndef CGEN_PRINT_INSN -#define CGEN_PRINT_INSN default_print_insn -#endif - -static int -default_print_insn (od, pc, info) - CGEN_OPCODE_DESC od; - bfd_vma pc; - disassemble_info *info; -{ - char buf[CGEN_MAX_INSN_SIZE]; - int status; - - /* Read the base part of the insn. */ - - status = (*info->read_memory_func) (pc, buf, CGEN_BASE_INSN_SIZE, info); - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return -1; - } - - return print_insn (od, pc, info, buf, CGEN_BASE_INSN_SIZE); -} - -/* Main entry point. - Print one instruction from PC on INFO->STREAM. - Return the size of the instruction (in bytes). */ - -int -print_insn_@arch@ (pc, info) - bfd_vma pc; - disassemble_info *info; -{ - int length; - static CGEN_OPCODE_DESC od = 0; - int mach = info->mach; - int big_p = info->endian == BFD_ENDIAN_BIG; - - /* If we haven't initialized yet, initialize the opcode table. */ - if (! od) - { - od = @arch@_cgen_opcode_open (mach, - big_p ? - CGEN_ENDIAN_BIG - : CGEN_ENDIAN_LITTLE); - @arch@_cgen_init_dis (od); - } - /* If we've switched cpu's, re-initialize. */ - /* ??? Perhaps we should use BFD_ENDIAN. */ - else if (mach != CGEN_OPCODE_MACH (od) - || (CGEN_OPCODE_ENDIAN (od) - != (big_p ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE))) - { - cgen_set_cpu (od, mach, big_p ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); - } - - /* We try to have as much common code as possible. - But at this point some targets need to take over. */ - /* ??? Some targets may need a hook elsewhere. Try to avoid this, - but if not possible try to move this hook elsewhere rather than - have two hooks. */ - length = CGEN_PRINT_INSN (od, pc, info); - if (length > 0) - return length; - if (length < 0) - return -1; - - (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); - return CGEN_DEFAULT_INSN_SIZE; -} diff --git a/opcodes/cgen-opc.c b/opcodes/cgen-opc.c deleted file mode 100644 index aef9d6b3582..00000000000 --- a/opcodes/cgen-opc.c +++ /dev/null @@ -1,368 +0,0 @@ -/* CGEN generic opcode support. - - Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. - - This file is part of the GNU Binutils and GDB, the GNU debugger. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include <ctype.h> -#include <stdio.h> -#include "ansidecl.h" -#include "libiberty.h" -#include "bfd.h" -#include "symcat.h" -#include "opcode/cgen.h" - -/* State variables. - These record the state of the currently selected cpu, machine, endian, etc. - They are set by cgen_set_cpu. */ - -/* Current opcode data. */ -const CGEN_OPCODE_TABLE *cgen_current_opcode_table; - -/* Current machine (a la BFD machine number). */ -int cgen_current_mach; - -/* Current endian. */ -enum cgen_endian cgen_current_endian = CGEN_ENDIAN_UNKNOWN; - -/* FIXME: To support multiple architectures, we need to return a handle - to the state set up by this function, and pass the handle back to the - other functions. Later. */ - -void -cgen_set_cpu (table, mach, endian) - const CGEN_OPCODE_TABLE * table; - int mach; - enum cgen_endian endian; -{ - static int init_once_p; - - cgen_current_opcode_table = table; - cgen_current_mach = mach; - cgen_current_endian = endian; - - /* Initialize those things that only need be done once. */ - if (! init_once_p) - { - /* Nothing to do currently. */ - init_once_p = 1; - } - -#if 0 /* This isn't done here because it would put assembler support in the - disassembler, etc. The caller is required to call these after calling - us. */ - /* Reset the hash tables. */ - cgen_asm_init (); - cgen_dis_init (); -#endif -} - -static unsigned int hash_keyword_name - PARAMS ((const CGEN_KEYWORD *, const char *, int)); -static unsigned int hash_keyword_value - PARAMS ((const CGEN_KEYWORD *, unsigned int)); -static void build_keyword_hash_tables - PARAMS ((CGEN_KEYWORD *)); - -/* Return number of hash table entries to use for N elements. */ -#define KEYWORD_HASH_SIZE(n) ((n) <= 31 ? 17 : 31) - -/* Look up *NAMEP in the keyword table KT. - The result is the keyword entry or NULL if not found. */ - -const CGEN_KEYWORD_ENTRY * -cgen_keyword_lookup_name (kt, name) - CGEN_KEYWORD *kt; - const char *name; -{ - const CGEN_KEYWORD_ENTRY *ke; - const char *p,*n; - - if (kt->name_hash_table == NULL) - build_keyword_hash_tables (kt); - - ke = kt->name_hash_table[hash_keyword_name (kt, name, 0)]; - - /* We do case insensitive comparisons. - If that ever becomes a problem, add an attribute that denotes - "do case sensitive comparisons". */ - - while (ke != NULL) - { - n = name; - p = ke->name; - - while (*p - && (*p == *n - || (isalpha ((unsigned char) *p) - && (tolower ((unsigned char) *p) - == tolower ((unsigned char) *n))))) - ++n, ++p; - - if (!*p && !*n) - return ke; - - ke = ke->next_name; - } - - if (kt->null_entry) - return kt->null_entry; - return NULL; -} - -/* Look up VALUE in the keyword table KT. - The result is the keyword entry or NULL if not found. */ - -const CGEN_KEYWORD_ENTRY * -cgen_keyword_lookup_value (kt, value) - CGEN_KEYWORD *kt; - int value; -{ - const CGEN_KEYWORD_ENTRY *ke; - - if (kt->name_hash_table == NULL) - build_keyword_hash_tables (kt); - - ke = kt->value_hash_table[hash_keyword_value (kt, value)]; - - while (ke != NULL) - { - if (value == ke->value) - return ke; - ke = ke->next_value; - } - - return NULL; -} - -/* Add an entry to a keyword table. */ - -void -cgen_keyword_add (kt, ke) - CGEN_KEYWORD *kt; - CGEN_KEYWORD_ENTRY *ke; -{ - unsigned int hash; - - if (kt->name_hash_table == NULL) - build_keyword_hash_tables (kt); - - hash = hash_keyword_name (kt, ke->name, 0); - ke->next_name = kt->name_hash_table[hash]; - kt->name_hash_table[hash] = ke; - - hash = hash_keyword_value (kt, ke->value); - ke->next_value = kt->value_hash_table[hash]; - kt->value_hash_table[hash] = ke; - - if (ke->name[0] == 0) - kt->null_entry = ke; -} - -/* FIXME: Need function to return count of keywords. */ - -/* Initialize a keyword table search. - SPEC is a specification of what to search for. - A value of NULL means to find every keyword. - Currently NULL is the only acceptable value [further specification - deferred]. - The result is an opaque data item used to record the search status. - It is passed to each call to cgen_keyword_search_next. */ - -CGEN_KEYWORD_SEARCH -cgen_keyword_search_init (kt, spec) - CGEN_KEYWORD *kt; - const char *spec; -{ - CGEN_KEYWORD_SEARCH search; - - /* FIXME: Need to specify format of PARAMS. */ - if (spec != NULL) - abort (); - - if (kt->name_hash_table == NULL) - build_keyword_hash_tables (kt); - - search.table = kt; - search.spec = spec; - search.current_hash = 0; - search.current_entry = NULL; - return search; -} - -/* Return the next keyword specified by SEARCH. - The result is the next entry or NULL if there are no more. */ - -const CGEN_KEYWORD_ENTRY * -cgen_keyword_search_next (search) - CGEN_KEYWORD_SEARCH *search; -{ - /* Has search finished? */ - if (search->current_hash == search->table->hash_table_size) - return NULL; - - /* Search in progress? */ - if (search->current_entry != NULL - /* Anything left on this hash chain? */ - && search->current_entry->next_name != NULL) - { - search->current_entry = search->current_entry->next_name; - return search->current_entry; - } - - /* Move to next hash chain [unless we haven't started yet]. */ - if (search->current_entry != NULL) - ++search->current_hash; - - while (search->current_hash < search->table->hash_table_size) - { - search->current_entry = search->table->name_hash_table[search->current_hash]; - if (search->current_entry != NULL) - return search->current_entry; - ++search->current_hash; - } - - return NULL; -} - -/* Return first entry in hash chain for NAME. - If CASE_SENSITIVE_P is non-zero, return a case sensitive hash. */ - -static unsigned int -hash_keyword_name (kt, name, case_sensitive_p) - const CGEN_KEYWORD *kt; - const char *name; - int case_sensitive_p; -{ - unsigned int hash; - - if (case_sensitive_p) - for (hash = 0; *name; ++name) - hash = (hash * 97) + (unsigned char) *name; - else - for (hash = 0; *name; ++name) - hash = (hash * 97) + (unsigned char) tolower (*name); - return hash % kt->hash_table_size; -} - -/* Return first entry in hash chain for VALUE. */ - -static unsigned int -hash_keyword_value (kt, value) - const CGEN_KEYWORD *kt; - unsigned int value; -{ - return value % kt->hash_table_size; -} - -/* Build a keyword table's hash tables. - We probably needn't build the value hash table for the assembler when - we're using the disassembler, but we keep things simple. */ - -static void -build_keyword_hash_tables (kt) - CGEN_KEYWORD *kt; -{ - int i; - /* Use the number of compiled in entries as an estimate for the - typical sized table [not too many added at runtime]. */ - unsigned int size = KEYWORD_HASH_SIZE (kt->num_init_entries); - - kt->hash_table_size = size; - kt->name_hash_table = (CGEN_KEYWORD_ENTRY **) - xmalloc (size * sizeof (CGEN_KEYWORD_ENTRY *)); - memset (kt->name_hash_table, 0, size * sizeof (CGEN_KEYWORD_ENTRY *)); - kt->value_hash_table = (CGEN_KEYWORD_ENTRY **) - xmalloc (size * sizeof (CGEN_KEYWORD_ENTRY *)); - memset (kt->value_hash_table, 0, size * sizeof (CGEN_KEYWORD_ENTRY *)); - - /* The table is scanned backwards as we want keywords appearing earlier to - be prefered over later ones. */ - for (i = kt->num_init_entries - 1; i >= 0; --i) - cgen_keyword_add (kt, &kt->init_entries[i]); -} - -/* Hardware support. */ - -/* Lookup a hardware element by its name. */ - -const CGEN_HW_ENTRY * -cgen_hw_lookup_by_name (name) - const char *name; -{ - const CGEN_HW_ENTRY * hw = cgen_current_opcode_table->hw_list; - - while (hw != NULL) - { - if (strcmp (name, hw->name) == 0) - return hw; - hw = hw->next; - } - - return NULL; -} - -/* Lookup a hardware element by its enum. - Hardware elements are enumerated, however it may be possible to add some - at runtime, thus HWNUM is not an enum type but rather an int. */ - -const CGEN_HW_ENTRY * -cgen_hw_lookup_by_enum (hwnum) - int hwnum; -{ - const CGEN_HW_ENTRY * hw = cgen_current_opcode_table->hw_list; - - /* ??? This can be speeded up if we first make a guess into - the compiled in table. */ - while (hw != NULL) - { - if (hwnum == hw->type) - return hw; - } - return NULL; -} - -/* Instruction support. */ - -/* Return number of instructions. This includes any added at runtime. */ - -int -cgen_insn_count () -{ - int count = cgen_current_opcode_table->insn_table->num_init_entries; - CGEN_INSN_LIST * insn = cgen_current_opcode_table->insn_table->new_entries; - - for ( ; insn != NULL; insn = insn->next) - ++count; - - return count; -} - -/* Return number of macro-instructions. This includes any added at runtime. */ - -int -cgen_macro_insn_count () -{ - int count = cgen_current_opcode_table->macro_insn_table->num_init_entries; - CGEN_INSN_LIST * insn = cgen_current_opcode_table->macro_insn_table->new_entries; - - for ( ; insn != NULL; insn = insn->next) - ++count; - - return count; -} diff --git a/opcodes/cgen.sh b/opcodes/cgen.sh deleted file mode 100644 index f6171f47aa7..00000000000 --- a/opcodes/cgen.sh +++ /dev/null @@ -1,43 +0,0 @@ -#! /bin/sh -# Generate CGEN opcode files: arch-opc.[ch], arch-asm.c, arch-asm.c. -# -# We store the generated files in the source directory until we decide to -# ship a scheme with gdb/binutils. Maybe we never will. - -# We want to behave like make, any error forces us to stop. -set -e - -srcdir=$1 -cgendir=$2 -cgenflags=$3 -scheme=$4 -schemeflags=$5 -arch=$6 - -rm -f tmp-opc.h tmp-opc.c tmp-asm.c tmp-dis.c -rm -f tmp-opc.h1 tmp-opc.c1 tmp-asm.c1 tmp-dis.c1 -rm -f tmp-asm.in tmp-asm.in1 tmp-dis.in tmp-dis.in1 - -$scheme $schemeflags $cgendir/cgen-opc.scm \ - -s $cgendir \ - $cgenflags \ - -m all \ - -a $arch \ - -h tmp-opc.h1 \ - -t tmp-opc.c1 \ - -A tmp-asm.in1 \ - -D tmp-dis.in1 - -sed -e "s/@arch@/${arch}/g" < tmp-opc.h1 > tmp-opc.h -${srcdir}/../move-if-change tmp-opc.h ${srcdir}/${arch}-opc.h -sed -e "s/@arch@/${arch}/g" < tmp-opc.c1 > tmp-opc.c -${srcdir}/../move-if-change tmp-opc.c ${srcdir}/${arch}-opc.c -sed -e "/ -- assembler routines/ r tmp-asm.in1" ${srcdir}/cgen-asm.in \ - | sed -e "s/@arch@/${arch}/g" > tmp-asm.c -${srcdir}/../move-if-change tmp-asm.c ${srcdir}/${arch}-asm.c -sed -e "/ -- disassembler routines/ r tmp-dis.in1" ${srcdir}/cgen-dis.in \ - | sed -e "s/@arch@/${arch}/g" > tmp-dis.c -${srcdir}/../move-if-change tmp-dis.c ${srcdir}/${arch}-dis.c - -rm -f tmp-opc.h1 tmp-opc.c1 tmp-asm.c1 tmp-dis.c1 -rm -f tmp-asm.in tmp-asm.in1 tmp-dis.in tmp-dis.in1 diff --git a/opcodes/config.in b/opcodes/config.in deleted file mode 100644 index aedc4907c58..00000000000 --- a/opcodes/config.in +++ /dev/null @@ -1,10 +0,0 @@ -/* config.in. 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For user convenience, we always use the same version -# number that BFD is using. -changequote(,)dnl -BFD_VERSION=`grep INIT_AUTOMAKE ${srcdir}/../bfd/configure.in | sed -n -e 's/[ ]//g' -e 's/^.*,\(.*\)).*$/\1/p'` -changequote([,])dnl - -AM_INIT_AUTOMAKE(opcodes, ${BFD_VERSION}) - -dnl These must be called before AM_PROG_LIBTOOL, because it may want -dnl to call AC_CHECK_PROG. -AC_CHECK_TOOL(AR, ar) -AC_CHECK_TOOL(RANLIB, ranlib, :) - -dnl Default to a non shared library. This may be overridden by the -dnl configure option --enable-shared. -AM_DISABLE_SHARED - -AM_PROG_LIBTOOL - -AC_ARG_ENABLE(targets, -[ --enable-targets alternative target configurations], -[case "${enableval}" in - yes | "") AC_ERROR(enable-targets option must specify target names or 'all') - ;; - no) enable_targets= ;; - *) enable_targets=$enableval ;; -esac])dnl -AC_ARG_ENABLE(commonbfdlib, -[ --enable-commonbfdlib build shared BFD/opcodes/libiberty library], -[case "${enableval}" in - yes) commonbfdlib=true ;; - no) commonbfdlib=false ;; - *) AC_MSG_ERROR([bad value ${enableval} for opcodes commonbfdlib option]) ;; -esac])dnl - -AM_CONFIG_HEADER(config.h:config.in) - -if test -z "$target" ; then - AC_MSG_ERROR(Unrecognized target system type; please check config.sub.) -fi -AC_ARG_PROGRAM - -AM_MAINTAINER_MODE -AM_CYGWIN32 -AM_EXEEXT - -# host-specific stuff: - -AC_PROG_CC - -ALL_LINGUAS= -CY_GNU_GETTEXT - -. ${srcdir}/../bfd/configure.host - -AC_SUBST(HDEFINES) -AM_PROG_INSTALL - -AC_CHECK_HEADERS(string.h strings.h stdlib.h) - -# start-sanitize-cygnus -cgen_maint=no -# Default is to use one in build tree. -cgen=../cgen/cgen -cgendir='$(srcdir)/../cgen' -# Having --enable-maintainer-mode take arguments is another way to go. -# ??? One can argue --with is more appropriate if one wants to specify -# a directory name, but what we're doing here is an enable/disable kind -# of thing and specifying both --enable and --with is klunky. -# If you reeely want this to be --with, go ahead and change it. -AC_ARG_ENABLE(cgen-maint, -[ --enable-cgen-maint[=dir] build cgen generated files], -[case "${enableval}" in - yes) cgen_maint=yes ;; - no) cgen_maint=no ;; - *) - # argument is cgen install directory (not implemented yet). - # Having a `share' directory might be more appropriate for the .scm, - # .cpu, etc. files. - cgen_maint=yes - cgendir=${cgen_maint}/lib/cgen - cgen=${cgendir}/bin/cgen - ;; -esac])dnl -AM_CONDITIONAL(CGEN_MAINT, test x${cgen_maint} = xyes) -AC_SUBST(cgendir) -AC_SUBST(cgen) -# end-sanitize-cygnus - -# Horrible hacks to build DLLs on Windows. -WIN32LDFLAGS= -WIN32LIBADD= -case "${host}" in -*-*-cygwin*) - if test "$enable_shared" = "yes"; then - WIN32LDFLAGS="-no-undefined" - WIN32LIBADD="-L`pwd`/../bfd -lbfd -L`pwd`/../libiberty -liberty -L`pwd`/../intl -lintl -lcygwin" - fi - ;; -esac -AC_SUBST(WIN32LDFLAGS) -AC_SUBST(WIN32LIBADD) - -# target-specific stuff: - -# Canonicalize the secondary target names. -if test -n "$enable_targets" ; then - for targ in `echo $enable_targets | sed 's/,/ /g'` - do - result=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $targ 2>/dev/null` - if test -n "$result" ; then - canon_targets="$canon_targets $result" - else - # Allow targets that config.sub doesn't recognize, like "all". - canon_targets="$canon_targets $targ" - fi - done -fi - -all_targets=false -selarchs= -for targ in $target $canon_targets -do - if test "x$targ" = "xall" ; then - all_targets=true - else - . $srcdir/../bfd/config.bfd - selarchs="$selarchs $targ_archs" - fi -done - -# Utility var, documents generic cgen support files. - -cgen_files="cgen-opc.lo cgen-asm.lo cgen-dis.lo" - -# We don't do any links based on the target system, just makefile config. - -if test x${all_targets} = xfalse ; then - - # Target architecture .o files. - ta= - - for arch in $selarchs - do - ad=`echo $arch | sed -e s/bfd_//g -e s/_arch//g` - archdefs="$archdefs -DARCH_$ad" - case "$arch" in - bfd_a29k_arch) ta="$ta a29k-dis.lo" ;; - bfd_alliant_arch) ;; - bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;; - bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo" ;; - bfd_arm_arch) ta="$ta arm-dis.lo" ;; - bfd_convex_arch) ;; - bfd_d10v_arch) ta="$ta d10v-dis.lo d10v-opc.lo" ;; - bfd_d30v_arch) ta="$ta d30v-dis.lo d30v-opc.lo" ;; - bfd_fr30_arch) ta="$ta $cgen_files fr30-opc.lo fr30-asm.lo fr30-dis.lo" ;; - bfd_h8300_arch) ta="$ta h8300-dis.lo" ;; - bfd_h8500_arch) ta="$ta h8500-dis.lo" ;; - bfd_hppa_arch) ta="$ta hppa-dis.lo" ;; - bfd_i386_arch) ta="$ta i386-dis.lo" ;; - bfd_i860_arch) ;; - bfd_i960_arch) ta="$ta $cgen_files i960-dis.lo i960c-opc.lo i960c-asm.lo i960c-dis.lo" ;; - bfd_m32r_arch) ta="$ta $cgen_files m32r-opc.lo m32r-asm.lo m32r-dis.lo" ;; - bfd_m68k_arch) ta="$ta m68k-dis.lo m68k-opc.lo" ;; - bfd_m88k_arch) ta="$ta m88k-dis.lo" ;; - bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;; - bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;; - bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;; - bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;; - bfd_powerpc_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; - bfd_pyramid_arch) ;; - bfd_romp_arch) ;; - bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; - bfd_sh_arch) ta="$ta sh-dis.lo" ;; - bfd_sparc_arch) ta="$ta sparc-dis.lo sparc-opc.lo" ;; - bfd_tahoe_arch) ;; - bfd_tic30_arch) ta="$ta tic30-dis.lo" ;; -# start-sanitize-tic80 - bfd_tic80_arch) ta="$ta tic80-dis.lo tic80-opc.lo" ;; -# end-sanitize-tic80 -# start-sanitize-sky - bfd_dvp_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo dvp-dis.lo dvp-opc.lo" ;; -# end-sanitize-sky - bfd_v850_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; - bfd_v850e_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; - bfd_v850ea_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; - bfd_vax_arch) ta="$ta vax-dis.lo" ;; - bfd_w65_arch) ta="$ta w65-dis.lo" ;; - bfd_we32k_arch) ;; - bfd_z8k_arch) ta="$ta z8k-dis.lo" ;; - - "") ;; - *) AC_MSG_ERROR(*** unknown target architecture $arch) ;; - esac - done - - # Weed out duplicate .o files. - f="" - for i in $ta ; do - case " $f " in - *" $i "*) ;; - *) f="$f $i" ;; - esac - done - ta="$f" - - # And duplicate -D flags. - f="" - for i in $archdefs ; do - case " $f " in - *" $i "*) ;; - *) f="$f $i" ;; - esac - done - archdefs="$f" - - BFD_MACHINES="$ta" - -else # all_targets is true - archdefs=-DARCH_all - BFD_MACHINES='$(ALL_MACHINES)' -fi - -AC_SUBST(archdefs) -AC_SUBST(BFD_MACHINES) - -AC_OUTPUT(Makefile po/Makefile.in:po/Make-in, -[sed -e '/POTFILES =/r po/POTFILES' po/Makefile.in > po/Makefile]) diff --git a/opcodes/d10v-dis.c b/opcodes/d10v-dis.c deleted file mode 100644 index 04184f8da76..00000000000 --- a/opcodes/d10v-dis.c +++ /dev/null @@ -1,292 +0,0 @@ -/* Disassemble D10V instructions. - Copyright (C) 1996, 1997 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - - -#include <stdio.h> - -#include "opcode/d10v.h" -#include "dis-asm.h" - -/* the PC wraps at 18 bits, except for the segment number */ -/* so use this mask to keep the parts we want */ -#define PC_MASK 0x03003FFF - -static void dis_2_short PARAMS ((unsigned long insn, bfd_vma memaddr, - struct disassemble_info *info, int order)); -static void dis_long PARAMS ((unsigned long insn, bfd_vma memaddr, - struct disassemble_info *info)); - -int -print_insn_d10v (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - int status; - bfd_byte buffer[4]; - unsigned long insn; - - status = (*info->read_memory_func) (memaddr, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn = bfd_getb32 (buffer); - - status = insn & FM11; - switch (status) { - case 0: - dis_2_short (insn, memaddr, info, 2); - break; - case FM01: - dis_2_short (insn, memaddr, info, 0); - break; - case FM10: - dis_2_short (insn, memaddr, info, 1); - break; - case FM11: - dis_long (insn, memaddr, info); - break; - } - return 4; -} - -static void -print_operand (oper, insn, op, memaddr, info) - struct d10v_operand *oper; - unsigned long insn; - struct d10v_opcode *op; - bfd_vma memaddr; - struct disassemble_info *info; -{ - int num, shift; - - if (oper->flags == OPERAND_ATMINUS) - { - (*info->fprintf_func) (info->stream, "@-"); - return; - } - if (oper->flags == OPERAND_MINUS) - { - (*info->fprintf_func) (info->stream, "-"); - return; - } - if (oper->flags == OPERAND_PLUS) - { - (*info->fprintf_func) (info->stream, "+"); - return; - } - if (oper->flags == OPERAND_ATSIGN) - { - (*info->fprintf_func) (info->stream, "@"); - return; - } - if (oper->flags == OPERAND_ATPAR) - { - (*info->fprintf_func) (info->stream, "@("); - return; - } - - shift = oper->shift; - - /* the LONG_L format shifts registers over by 15 */ - if (op->format == LONG_L && (oper->flags & OPERAND_REG)) - shift += 15; - - num = (insn >> shift) & (0x7FFFFFFF >> (31 - oper->bits)); - - if (oper->flags & OPERAND_REG) - { - int i; - int match=0; - num += oper->flags & (OPERAND_ACC|OPERAND_FLAG|OPERAND_CONTROL); - for (i=0;i<reg_name_cnt();i++) - { - if (num == pre_defined_registers[i].value) - { - if (pre_defined_registers[i].pname) - (*info->fprintf_func) (info->stream, "%s",pre_defined_registers[i].pname); - else - (*info->fprintf_func) (info->stream, "%s",pre_defined_registers[i].name); - match=1; - break; - } - } - if (match==0) - { - /* this would only get executed if a register was not in the - register table */ - if (oper->flags & OPERAND_ACC) - (*info->fprintf_func) (info->stream, "a"); - else if (oper->flags & OPERAND_CONTROL) - (*info->fprintf_func) (info->stream, "cr"); - else if(oper->flags & OPERAND_REG) - (*info->fprintf_func) (info->stream, "r"); - (*info->fprintf_func) (info->stream, "%d",num); - } - } - else - { - /* addresses are right-shifted by 2 */ - if (oper->flags & OPERAND_ADDR) - { - long max; - int neg=0; - max = (1 << (oper->bits - 1)); - if (num & max) - { - num = -num & ((1 << oper->bits)-1); - neg = 1; - } - num = num<<2; - if (neg) - (*info->print_address_func) ((memaddr - num) & PC_MASK, info); - else - (*info->print_address_func) ((memaddr + num) & PC_MASK, info); - } - else - { - if (oper->flags & OPERAND_SIGNED) - { - int max = (1 << (oper->bits - 1)); - if (num & max) - { - num = -num & ((1 << oper->bits)-1); - (*info->fprintf_func) (info->stream, "-"); - } - } - (*info->fprintf_func) (info->stream, "0x%x",num); - } - } -} - - -static void -dis_long (insn, memaddr, info) - unsigned long insn; - bfd_vma memaddr; - struct disassemble_info *info; -{ - int i; - char buf[32]; - struct d10v_opcode *op = (struct d10v_opcode *)d10v_opcodes; - struct d10v_operand *oper; - int need_paren = 0; - int match = 0; - - while (op->name) - { - if ((op->format & LONG_OPCODE) && ((op->mask & insn) == op->opcode)) - { - match = 1; - (*info->fprintf_func) (info->stream, "%s\t", op->name); - for ( i=0; op->operands[i]; i++) - { - oper = (struct d10v_operand *)&d10v_operands[op->operands[i]]; - if (oper->flags == OPERAND_ATPAR) - need_paren = 1; - print_operand (oper, insn, op, memaddr, info); - if (op->operands[i+1] && oper->bits && - d10v_operands[op->operands[i+1]].flags != OPERAND_PLUS && - d10v_operands[op->operands[i+1]].flags != OPERAND_MINUS) - (*info->fprintf_func) (info->stream, ", "); - } - break; - } - op++; - } - - if (!match) - (*info->fprintf_func) (info->stream, ".long\t0x%08x",insn); - - if (need_paren) - (*info->fprintf_func) (info->stream, ")"); -} - -static void -dis_2_short (insn, memaddr, info, order) - unsigned long insn; - bfd_vma memaddr; - struct disassemble_info *info; - int order; -{ - int i,j; - char astr[2][32]; - unsigned int ins[2]; - struct d10v_opcode *op; - char buf[32]; - int match, num_match=0; - struct d10v_operand *oper; - int need_paren = 0; - - ins[0] = (insn & 0x3FFFFFFF) >> 15; - ins[1] = insn & 0x00007FFF; - - for(j=0;j<2;j++) - { - op = (struct d10v_opcode *)d10v_opcodes; - match=0; - while (op->name) - { - if ((op->format & SHORT_OPCODE) && ((op->mask & ins[j]) == op->opcode)) - { - (*info->fprintf_func) (info->stream, "%s\t",op->name); - for (i=0; op->operands[i]; i++) - { - oper = (struct d10v_operand *)&d10v_operands[op->operands[i]]; - if (oper->flags == OPERAND_ATPAR) - need_paren = 1; - print_operand (oper, ins[j], op, memaddr, info); - if (op->operands[i+1] && oper->bits && - d10v_operands[op->operands[i+1]].flags != OPERAND_PLUS && - d10v_operands[op->operands[i+1]].flags != OPERAND_MINUS) - (*info->fprintf_func) (info->stream, ", "); - } - match = 1; - num_match++; - break; - } - op++; - } - if (!match) - (*info->fprintf_func) (info->stream, "unknown"); - - switch (order) - { - case 0: - (*info->fprintf_func) (info->stream, "\t->\t"); - order = -1; - break; - case 1: - (*info->fprintf_func) (info->stream, "\t<-\t"); - order = -1; - break; - case 2: - (*info->fprintf_func) (info->stream, "\t||\t"); - order = -1; - break; - default: - break; - } - } - - if (num_match == 0) - (*info->fprintf_func) (info->stream, ".long\t0x%08x",insn); - - if (need_paren) - (*info->fprintf_func) (info->stream, ")"); -} diff --git a/opcodes/d10v-opc.c b/opcodes/d10v-opc.c deleted file mode 100644 index 0441e6afd75..00000000000 --- a/opcodes/d10v-opc.c +++ /dev/null @@ -1,301 +0,0 @@ -/* d10v-opc.c -- D10V opcode list - Copyright 1996 Free Software Foundation, Inc. - Written by Martin Hunt, Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -2, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include <stdio.h> -#include "ansidecl.h" -#include "opcode/d10v.h" - - -/* The table is sorted. Suitable for searching by a binary search. */ -const struct pd_reg pre_defined_registers[] = -{ - { "a0", NULL, OPERAND_ACC+0 }, - { "a1", NULL, OPERAND_ACC+1 }, - { "bpc", NULL, OPERAND_CONTROL+3 }, - { "bpsw", NULL, OPERAND_CONTROL+1 }, - { "c", NULL, OPERAND_FLAG+3 }, - { "f0", NULL, OPERAND_FLAG+0 }, - { "f1", NULL, OPERAND_FLAG+1 }, - { "iba", NULL, OPERAND_CONTROL+14 }, - { "mod_e", NULL, OPERAND_CONTROL+11 }, - { "mod_s", NULL, OPERAND_CONTROL+10 }, - { "pc", NULL, OPERAND_CONTROL+2 }, - { "psw", NULL, OPERAND_CONTROL+0 }, - { "r0", NULL, 0 }, - { "r1", NULL, 1 }, - { "r10", NULL, 10 }, - { "r11", NULL, 11 }, - { "r12", NULL, 12 }, - { "r13", NULL, 13 }, - { "r14", NULL, 14 }, - { "r15", "sp", 15 }, - { "r2", NULL, 2 }, - { "r3", NULL, 3 }, - { "r4", NULL, 4 }, - { "r5", NULL, 5 }, - { "r6", NULL, 6 }, - { "r7", NULL, 7 }, - { "r8", NULL, 8 }, - { "r9", NULL, 9 }, - { "rpt_c", NULL, OPERAND_CONTROL+7 }, - { "rpt_e", NULL, OPERAND_CONTROL+9 }, - { "rpt_s", NULL, OPERAND_CONTROL+8 }, - { "sp", NULL, 15 }, -}; - -int -reg_name_cnt() -{ - return (sizeof(pre_defined_registers) / sizeof(struct pd_reg)); -} - -const struct d10v_operand d10v_operands[] = -{ -#define UNUSED (0) - { 0, 0, 0 }, -#define RSRC (UNUSED + 1) - { 4, 1, OPERAND_REG }, -#define RDST (RSRC + 1) - { 4, 5, OPERAND_DEST|OPERAND_REG }, -#define ASRC (RDST + 1) - { 1, 4, OPERAND_ACC|OPERAND_REG }, -#define ADST (ASRC + 1) - { 1, 8, OPERAND_DEST|OPERAND_ACC|OPERAND_REG }, -#define RSRCE (ADST + 1) - { 4, 1, OPERAND_EVEN|OPERAND_REG }, -#define RDSTE (RSRCE + 1) - { 4, 5, OPERAND_EVEN|OPERAND_DEST|OPERAND_REG }, -#define NUM16 (RDSTE + 1) - { 16, 0, OPERAND_NUM|OPERAND_SIGNED }, -#define NUM3 (NUM16 + 1) /* rac, rachi */ - { 3, 1, OPERAND_NUM|OPERAND_SIGNED }, -#define NUM4 (NUM3 + 1) - { 4, 1, OPERAND_NUM|OPERAND_SIGNED }, -#define UNUM4 (NUM4 + 1) - { 4, 1, OPERAND_NUM }, -#define UNUM4S (UNUM4 + 1) /* slli, srai, srli, subi */ - { 4, 1, OPERAND_NUM|OPERAND_SHIFT }, -#define UNUM8 (UNUM4S + 1) /* repi */ - { 8, 16, OPERAND_NUM }, -#define UNUM16 (UNUM8 + 1) /* cmpui */ - { 16, 0, OPERAND_NUM }, -#define ANUM16 (UNUM16 + 1) - { 16, 0, OPERAND_ADDR|OPERAND_SIGNED }, -#define ANUM8 (ANUM16 + 1) - { 8, 0, OPERAND_ADDR|OPERAND_SIGNED }, -#define ASRC2 (ANUM8 + 1) - { 1, 8, OPERAND_ACC|OPERAND_REG }, -#define RSRC2 (ASRC2 + 1) - { 4, 5, OPERAND_REG }, -#define RSRC2E (RSRC2 + 1) - { 4, 5, OPERAND_REG|OPERAND_EVEN }, -#define ASRC0 (RSRC2E + 1) - { 1, 0, OPERAND_ACC|OPERAND_REG }, -#define ADST0 (ASRC0 + 1) - { 1, 0, OPERAND_ACC|OPERAND_REG|OPERAND_DEST }, -#define FSRC (ADST0 + 1) - { 2, 1, OPERAND_REG | OPERAND_FLAG }, -#define FDST (FSRC + 1) - { 1, 5, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST}, -#define ATSIGN (FDST + 1) - { 0, 0, OPERAND_ATSIGN}, -#define ATPAR (ATSIGN + 1) /* "@(" */ - { 0, 0, OPERAND_ATPAR}, -#define PLUS (ATPAR + 1) /* postincrement */ - { 0, 0, OPERAND_PLUS}, -#define MINUS (PLUS + 1) /* postdecrement */ - { 0, 0, OPERAND_MINUS}, -#define ATMINUS (MINUS + 1) /* predecrement */ - { 0, 0, OPERAND_ATMINUS}, -#define CSRC (ATMINUS + 1) /* control register */ - { 4, 1, OPERAND_REG|OPERAND_CONTROL}, -#define CDST (CSRC + 1) /* control register */ - { 4, 5, OPERAND_REG|OPERAND_CONTROL|OPERAND_DEST}, -}; - -const struct d10v_opcode d10v_opcodes[] = { - { "abs", SHORT_2, 1, EITHER, PAR, 0x4607, 0x7e1f, { RDST } }, - { "abs", SHORT_2, 1, IU, PAR, 0x5607, 0x7eff, { ADST } }, - { "add", SHORT_2, 1, EITHER, PAR, 0x0200, 0x7e01, { RDST, RSRC } }, - { "add", SHORT_2, 1, IU, PAR, 0x1201, 0x7ee3, { ADST, RSRCE } }, - { "add", SHORT_2, 1, IU, PAR, 0x1203, 0x7eef, { ADST, ASRC } }, - { "add2w", SHORT_2, 2, IU, PAR, 0x1200, 0x7e23, { RDSTE, RSRCE } }, - { "add3", LONG_L, 1, MU, SEQ, 0x1000000, 0x3f000000, { RDST, RSRC, NUM16 } }, - { "addac3", LONG_R, 1, IU, SEQ, 0x17000200, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } }, - { "addac3", LONG_R, 1, IU, SEQ, 0x17000202, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } }, - { "addac3s", LONG_R, 1, IU, SEQ, 0x17001200, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } }, - { "addac3s", LONG_R, 1, IU, SEQ, 0x17001202, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } }, - { "addi", SHORT_2, 1, EITHER, PAR, 0x201, 0x7e01, { RDST, UNUM4 } }, - { "and", SHORT_2, 1, EITHER, PAR, 0xc00, 0x7e01, { RDST, RSRC } }, - { "and3", LONG_L, 1, MU, SEQ, 0x6000000, 0x3f000000, { RDST, RSRC, NUM16 } }, - { "bclri", SHORT_2, 1, IU, PAR, 0xc01, 0x7e01, { RDST, UNUM4 } }, - { "bl", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } }, - { "bl.s", SHORT_B, 3, MU, BRANCH_LINK, 0x4900, 0x7f00, { ANUM8 } }, - { "bl.l", LONG_B, 3, MU, BRANCH_LINK, 0x24800000, 0x3fff8000, { ANUM16 } }, - { "bnoti", SHORT_2, 1, IU, PAR, 0xa01, 0x7e01, { RDST, UNUM4 } }, - { "bra", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } }, - { "bra.s", SHORT_B, 3, MU, PAR, 0x4800, 0x7f00, { ANUM8 } }, - { "bra.l", LONG_B, 3, MU, SEQ, 0x24000000, 0x3fff0000, { ANUM16 } }, - { "brf0f", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } }, - { "brf0f.s", SHORT_B, 3, MU, PAR, 0x4a00, 0x7f00, { ANUM8 } }, - { "brf0f.l", LONG_B, 3, MU, SEQ, 0x25000000, 0x3fff0000, { ANUM16 } }, - { "brf0t", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } }, - { "brf0t.s", SHORT_B, 3, MU, PAR, 0x4b00, 0x7f00, { ANUM8 } }, - { "brf0t.l", LONG_B, 3, MU, SEQ, 0x25800000, 0x3fff0000, { ANUM16 } }, - { "bseti", SHORT_2, 1, IU, PAR, 0x801, 0x7e01, { RDST, UNUM4 } }, - { "btsti", SHORT_2, 1, IU, PAR, 0xe01, 0x7e01, { RDST, UNUM4 } }, - { "clrac", SHORT_2, 1, IU, PAR, 0x5601, 0x7eff, { ADST } }, - { "cmp", SHORT_2, 1, EITHER, PAR, 0x600, 0x7e01, { RSRC2, RSRC } }, - { "cmp", SHORT_2, 1, IU, PAR, 0x1603, 0x7eef, { ASRC2, ASRC } }, - { "cmpeq", SHORT_2, 1, EITHER, PAR, 0x400, 0x7e01, { RSRC2, RSRC } }, - { "cmpeq", SHORT_2, 1, IU, PAR, 0x1403, 0x7eef, { ASRC2, ASRC } }, - { "cmpeqi", OPCODE_FAKE, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } }, - { "cmpeqi.s", SHORT_2, 1, EITHER, PAR, 0x401, 0x7e01, { RSRC2, NUM4 } }, - { "cmpeqi.l", LONG_L, 1, MU, SEQ, 0x2000000, 0x3f0f0000, { RSRC2, NUM16 } }, - { "cmpi", OPCODE_FAKE, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } }, - { "cmpi.s", SHORT_2, 1, EITHER, PAR, 0x601, 0x7e01, { RSRC2, NUM4 } }, - { "cmpi.l", LONG_L, 1, MU, SEQ, 0x3000000, 0x3f0f0000, { RSRC2, NUM16 } }, - { "cmpu", SHORT_2, 1, EITHER, PAR, 0x4600, 0x7e01, { RSRC2, RSRC } }, - { "cmpui", LONG_L, 1, MU, SEQ, 0x23000000, 0x3f0f0000, { RSRC2, UNUM16 } }, - { "cpfg", SHORT_2, 1, MU, PAR, 0x4e09, 0x7fd9, { FDST, FSRC } }, - { "dbt", SHORT_2, 5, MU, PAR, 0x5f20, 0x7fff, { 0 } }, - { "divs", LONG_L, 1, BOTH, SEQ, 0x14002800, 0x3f10fe21, { RDSTE, RSRC } }, - { "exef0f", SHORT_2, 1, EITHER, PARONLY, 0x4e04, 0x7fff, { 0 } }, - { "exef0t", SHORT_2, 1, EITHER, PARONLY, 0x4e24, 0x7fff, { 0 } }, - { "exef1f", SHORT_2, 1, EITHER, PARONLY, 0x4e40, 0x7fff, { 0 } }, - { "exef1t", SHORT_2, 1, EITHER, PARONLY, 0x4e42, 0x7fff, { 0 } }, - { "exefaf", SHORT_2, 1, EITHER, PARONLY, 0x4e00, 0x7fff, { 0 } }, - { "exefat", SHORT_2, 1, EITHER, PARONLY, 0x4e02, 0x7fff, { 0 } }, - { "exetaf", SHORT_2, 1, EITHER, PARONLY, 0x4e20, 0x7fff, { 0 } }, - { "exetat", SHORT_2, 1, EITHER, PARONLY, 0x4e22, 0x7fff, { 0 } }, - { "exp", LONG_R, 1, IU, SEQ, 0x15002a00, 0x3ffffe03, { RDST, RSRCE } }, - { "exp", LONG_R, 1, IU, SEQ, 0x15002a02, 0x3ffffe0f, { RDST, ASRC } }, - { "jl", SHORT_2, 3, MU, BRANCH_LINK, 0x4d00, 0x7fe1, { RSRC } }, - { "jmp", SHORT_2, 3, MU, PAR, 0x4c00, 0x7fe1, { RSRC } }, - { "ld", LONG_L, 1, MU, SEQ, 0x30000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } }, - { "ld", SHORT_2, 1, MU, PAR, 0x6401, 0x7e01, { RDST, ATSIGN, RSRC, MINUS } }, - { "ld", SHORT_2, 1, MU, PAR, 0x6001, 0x7e01, { RDST, ATSIGN, RSRC, PLUS } }, - { "ld", SHORT_2, 1, MU, PAR, 0x6000, 0x7e01, { RDST, ATSIGN, RSRC } }, - { "ld2w", LONG_L, 1, MU, SEQ, 0x31000000, 0x3f100000, { RDSTE, ATPAR, NUM16, RSRC } }, - { "ld2w", SHORT_2, 1, MU, PAR, 0x6601, 0x7e21, { RDSTE, ATSIGN, RSRC, MINUS } }, - { "ld2w", SHORT_2, 1, MU, PAR, 0x6201, 0x7e21, { RDSTE, ATSIGN, RSRC, PLUS } }, - { "ld2w", SHORT_2, 1, MU, PAR, 0x6200, 0x7e21, { RDSTE, ATSIGN, RSRC } }, - { "ldb", LONG_L, 1, MU, SEQ, 0x38000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } }, - { "ldb", SHORT_2, 1, MU, PAR, 0x7000, 0x7e01, { RDST, ATSIGN, RSRC } }, - { "ldi", OPCODE_FAKE, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } }, - { "ldi.s", SHORT_2, 1, EITHER, PAR,0x4001, 0x7e01 , { RDST, NUM4 } }, - { "ldi.l", LONG_L, 1, MU, SEQ, 0x20000000, 0x3f0f0000, { RDST, NUM16 } }, - { "ldub", LONG_L, 1, MU, SEQ, 0x39000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } }, - { "ldub", SHORT_2, 1, MU, PAR, 0x7200, 0x7e01, { RDST, ATSIGN, RSRC } }, - { "mac", SHORT_2, 1, IU, PAR, 0x2a00, 0x7e00, { ADST0, RSRC2, RSRC } }, - { "macsu", SHORT_2, 1, IU, PAR, 0x1a00, 0x7e00, { ADST0, RSRC2, RSRC } }, - { "macu", SHORT_2, 1, IU, PAR, 0x3a00, 0x7e00, { ADST0, RSRC2, RSRC } }, - { "max", SHORT_2, 1, IU, PAR, 0x2600, 0x7e01, { RDST, RSRC } }, - { "max", SHORT_2, 1, IU, PAR, 0x3600, 0x7ee3, { ADST, RSRCE } }, - { "max", SHORT_2, 1, IU, PAR, 0x3602, 0x7eef, { ADST, ASRC } }, - { "min", SHORT_2, 1, IU, PAR, 0x2601, 0x7e01 , { RDST, RSRC } }, - { "min", SHORT_2, 1, IU, PAR, 0x3601, 0x7ee3 , { ADST, RSRCE } }, - { "min", SHORT_2, 1, IU, PAR, 0x3603, 0x7eef, { ADST, ASRC } }, - { "msb", SHORT_2, 1, IU, PAR, 0x2800, 0x7e00, { ADST0, RSRC2, RSRC } }, - { "msbsu", SHORT_2, 1, IU, PAR, 0x1800, 0x7e00, { ADST0, RSRC2, RSRC } }, - { "msbu", SHORT_2, 1, IU, PAR, 0x3800, 0x7e00, { ADST0, RSRC2, RSRC } }, - { "mul", SHORT_2, 1, IU, PAR, 0x2e00, 0x7e01 , { RDST, RSRC } }, - { "mulx", SHORT_2, 1, IU, PAR, 0x2c00, 0x7e00, { ADST0, RSRC2, RSRC } }, - { "mulxsu", SHORT_2, 1, IU, PAR, 0x1c00, 0x7e00, { ADST0, RSRC2, RSRC } }, - { "mulxu", SHORT_2, 1, IU, PAR, 0x3c00, 0x7e00, { ADST0, RSRC2, RSRC } }, - { "mv", SHORT_2, 1, EITHER, PAR, 0x4000, 0x7e01, { RDST, RSRC } }, - { "mv2w", SHORT_2, 1, IU, PAR, 0x5000, 0x7e23, { RDSTE, RSRCE } }, - { "mv2wfac", SHORT_2, 1, IU, PAR, 0x3e00, 0x7e2f, { RDSTE, ASRC } }, - { "mv2wtac", SHORT_2, 1, IU, PAR, 0x3e01, 0x7ee3, { RSRCE, ADST } }, - { "mvac", SHORT_2, 1, IU, PAR, 0x3e03, 0x7eef, { ADST, ASRC } }, - { "mvb", SHORT_2, 1, IU, PAR, 0x5400, 0x7e01, { RDST, RSRC } }, - { "mvf0f", SHORT_2, 1, EITHER, PAR, 0x4400, 0x7e01, { RDST, RSRC } }, - { "mvf0t", SHORT_2, 1, EITHER, PAR, 0x4401, 0x7e01, { RDST, RSRC } }, - { "mvfacg", SHORT_2, 1, IU, PAR, 0x1e04, 0x7e0f, { RDST, ASRC } }, - { "mvfachi", SHORT_2, 1, IU, PAR, 0x1e00, 0x7e0f, { RDST, ASRC } }, - { "mvfaclo", SHORT_2, 1, IU, PAR, 0x1e02, 0x7e0f, { RDST, ASRC } }, - { "mvfc", SHORT_2, 1, MU, PAR, 0x5200, 0x7e01, { RDST, CSRC } }, - { "mvtacg", SHORT_2, 1, IU, PAR, 0x1e41, 0x7ee1, { RSRC, ADST } }, - { "mvtachi", SHORT_2, 1, IU, PAR, 0x1e01, 0x7ee1, { RSRC, ADST } }, - { "mvtaclo", SHORT_2, 1, IU, PAR, 0x1e21, 0x7ee1, { RSRC, ADST } }, - { "mvtc", SHORT_2, 1, MU, PAR, 0x5600, 0x7e01, { RSRC, CDST } }, - { "mvub", SHORT_2, 1, IU, PAR, 0x5401, 0x7e01, { RDST, RSRC } }, - { "neg", SHORT_2, 1, EITHER, PAR, 0x4605, 0x7e1f, { RDST } }, - { "neg", SHORT_2, 1, IU, PAR, 0x5605, 0x7eff, { ADST } }, - { "nop", SHORT_2, 1, EITHER, PAR, 0x5e00, 0x7fff, { 0 } }, - { "not", SHORT_2, 1, EITHER, PAR, 0x4603, 0x7e1f, { RDST } }, - { "or", SHORT_2, 1, EITHER, PAR, 0x800, 0x7e01, { RDST, RSRC } }, - { "or3", LONG_L, 1, MU, SEQ, 0x4000000, 0x3f000000, { RDST, RSRC, NUM16 } }, - { "rac", SHORT_2, 1, IU, PAR, 0x5201, 0x7e21, { RDSTE, ASRC, NUM3 } }, - { "rachi", SHORT_2, 1, IU, PAR, 0x4201, 0x7e01, { RDST, ASRC, NUM3 } }, - { "rep", LONG_L, 2, MU, SEQ, 0x27000000, 0x3ff00000, { RSRC, ANUM16 } }, - { "repi", LONG_L, 2, MU, SEQ, 0x2f000000, 0x3f000000, { UNUM8, ANUM16 } }, - { "rtd", SHORT_2, 3, MU, PAR, 0x5f60, 0x7fff, { 0 } }, - { "rte", SHORT_2, 3, MU, PAR, 0x5f40, 0x7ff, { 0 } }, - { "sadd", SHORT_2, 1, IU, PAR, 0x1223, 0x7eef, { ADST, ASRC } }, - { "setf0f", SHORT_2, 1, MU, PAR, 0x4611, 0x7e1f, { RDST } }, - { "setf0t", SHORT_2, 1, MU, PAR, 0x4613, 0x7e1f, { RDST } }, - { "sleep", SHORT_2, 1, MU, PAR, 0x5fc0, 0x7fff, { 0 } }, - { "sll", SHORT_2, 1, IU, PAR, 0x2200, 0x7e01, { RDST, RSRC } }, - { "sll", SHORT_2, 1, IU, PAR, 0x3200, 0x7ee1, { ADST, RSRC } }, - { "slli", SHORT_2, 1, IU, PAR, 0x2201, 0x7e01, { RDST, UNUM4 } }, - { "slli", SHORT_2, 1, IU, PAR, 0x3201, 0x7ee1, { ADST, UNUM4S } }, - { "slx", SHORT_2, 1, IU, PAR, 0x460b, 0x7e1f, { RDST } }, - { "sra", SHORT_2, 1, IU, PAR, 0x2400, 0x7e01, { RDST, RSRC } }, - { "sra", SHORT_2, 1, IU, PAR, 0x3400, 0x7ee1, { ADST, RSRC } }, - { "srai", SHORT_2, 1, IU, PAR, 0x2401, 0x7e01, { RDST, UNUM4 } }, - { "srai", SHORT_2, 1, IU, PAR, 0x3401, 0x7ee1, { ADST, UNUM4S } }, - { "srl", SHORT_2, 1, IU, PAR, 0x2000, 0x7e01, { RDST, RSRC } }, - { "srl", SHORT_2, 1, IU, PAR, 0x3000, 0x7ee1, { ADST, RSRC } }, - { "srli", SHORT_2, 1, IU, PAR, 0x2001, 0x7e01, { RDST, UNUM4 } }, - { "srli", SHORT_2, 1, IU, PAR, 0x3001, 0x7ee1, { ADST, UNUM4S } }, - { "srx", SHORT_2, 1, IU, PAR, 0x4609, 0x7e1f, { RDST } }, - { "st", LONG_L, 1, MU, SEQ, 0x34000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } }, - { "st", SHORT_2, 1, MU, PAR, 0x6800, 0x7e01, { RSRC2, ATSIGN, RSRC } }, - { "st", SHORT_2, 1, MU, PAR, 0x6c1f, 0x7e1f, { RSRC2, ATMINUS, RSRC } }, - { "st", SHORT_2, 1, MU, PAR, 0x6801, 0x7e01, { RSRC2, ATSIGN, RSRC, PLUS } }, - { "st", SHORT_2, 1, MU, PAR, 0x6c01, 0x7e01, { RSRC2, ATSIGN, RSRC, MINUS } }, - { "st2w", LONG_L, 1, MU, SEQ, 0x35000000, 0x3f100000, { RSRC2E, ATPAR, NUM16, RSRC } }, - { "st2w", SHORT_2, 1, MU, PAR, 0x6a00, 0x7e21, { RSRC2E, ATSIGN, RSRC } }, - { "st2w", SHORT_2, 1, MU, PAR, 0x6e1f, 0x7e3f, { RSRC2E, ATMINUS, RSRC } }, - { "st2w", SHORT_2, 1, MU, PAR, 0x6a01, 0x7e21, { RSRC2E, ATSIGN, RSRC, PLUS } }, - { "st2w", SHORT_2, 1, MU, PAR, 0x6e01, 0x7e21, { RSRC2E, ATSIGN, RSRC, MINUS } }, - { "stb", LONG_L, 1, MU, SEQ, 0x3c000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } }, - { "stb", SHORT_2, 1, MU, PAR, 0x7800, 0x7e01, { RSRC2, ATSIGN, RSRC } }, - { "stop", SHORT_2, 1, MU, PAR, 0x5fe0, 0x7fff, { 0 } }, - { "sub", SHORT_2, 1, EITHER, PAR, 0x0, 0x7e01, { RDST, RSRC } }, - { "sub", SHORT_2, 1, IU, PAR, 0x1001, 0x7ee3, { ADST, RSRC } }, - { "sub", SHORT_2, 1, IU, PAR, 0x1003, 0x7eef, { ADST, ASRC } }, - { "sub2w", SHORT_2, 1, IU, PAR, 0x1000, 0x7e23, { RDSTE, RSRCE } }, - { "subac3", LONG_R, 1, IU, SEQ, 0x17000000, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } }, - { "subac3", LONG_R, 1, IU, SEQ, 0x17000002, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } }, - { "subac3s", LONG_R, 1, IU, SEQ, 0x17001000, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } }, - { "subac3s", LONG_R, 1, IU, SEQ, 0x17001002, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } }, - { "subi", SHORT_2, 1, EITHER, PAR, 0x1, 0x7e01, { RDST, UNUM4S } }, - { "trap", SHORT_2, 5, MU, PAR, 0x5f00, 0x7fe1, { UNUM4 } }, - { "tst0i", LONG_L, 1, MU, SEQ, 0x7000000, 0x3f0f0000, { RSRC2, NUM16 } }, - { "tst1i", LONG_L, 1, MU, SEQ, 0xf000000, 0x3f0f0000, { RSRC2, NUM16 } }, - { "wait", SHORT_2, 1, MU, PAR, 0x5f80, 0x7fff, { 0 } }, - { "xor", SHORT_2, 1, EITHER, PAR, 0xa00, 0x7e01, { RDST, RSRC } }, - { "xor3", LONG_L, 1, MU, SEQ, 0x5000000, 0x3f000000, { RDST, RSRC, NUM16 } }, - { 0, 0, 0, 0, 0, 0, 0, { 0 } }, -}; - - diff --git a/opcodes/d30v-dis.c b/opcodes/d30v-dis.c deleted file mode 100644 index 91262adce80..00000000000 --- a/opcodes/d30v-dis.c +++ /dev/null @@ -1,345 +0,0 @@ -/* Disassemble D30V instructions. - Copyright (C) 1997 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include <stdio.h> -#include "opcode/d30v.h" -#include "dis-asm.h" - -#define PC_MASK 0xFFFFFFFF - -static int lookup_opcode PARAMS (( struct d30v_insn *insn, long num, int is_long )); -static void print_insn PARAMS (( struct disassemble_info *info, bfd_vma memaddr, long long num, - struct d30v_insn *insn, int is_long )); -static int extract_value PARAMS (( long long num, struct d30v_operand *oper, int is_long )); - -int -print_insn_d30v (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - int status, i; - bfd_byte buffer[12]; - unsigned long in1,in2; - struct d30v_insn insn; - long long num; - - insn.form = (struct d30v_format *)NULL; - - status = (*info->read_memory_func) (memaddr, buffer, 8, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - info->bytes_per_line = 8; - info->bytes_per_chunk = 4; - info->display_endian = BFD_ENDIAN_BIG; - in1 = bfd_getb32 (buffer); - in2 = bfd_getb32 (buffer+4); - - if (in1 & in2 & FM01) - { - /* LONG instruction */ - if (!lookup_opcode(&insn, in1, 1)) - { - (*info->fprintf_func) (info->stream, ".long\t0x%x,0x%x",in1,in2); - return 8; - } - num = (long long)in1 << 32 | in2; - print_insn(info, memaddr, num, &insn, 1); - } - else - { - num = in1; - if (!lookup_opcode(&insn, in1, 0)) - (*info->fprintf_func) (info->stream, ".long\t0x%x",in1); - else - print_insn(info, memaddr, num, &insn, 0); - - switch ( ((in1>>31)<<1) | (in2>>31) ) - { - case 0: - (*info->fprintf_func) (info->stream, "\t||\t"); - break; - case 1: - (*info->fprintf_func) (info->stream, "\t->\t"); - break; - case 2: - (*info->fprintf_func) (info->stream, "\t<-\t"); - default: - break; - } - - insn.form = (struct d30v_format *)NULL; - num = in2; - if (!lookup_opcode(&insn, in2, 0)) - (*info->fprintf_func) (info->stream, ".long\t0x%x",in2); - else - print_insn(info, memaddr, num, &insn, 0); - - } - return 8; -} - - -static int -lookup_opcode (insn, num, is_long) - struct d30v_insn *insn; - long num; - int is_long; -{ - int i=0, index; - struct d30v_format *f; - struct d30v_opcode *op = (struct d30v_opcode *)d30v_opcode_table; - int op1 = (num >> 25) & 0x7; - int op2 = (num >> 20) & 0x1f; - int mod = (num >> 18) & 0x3; - - /* find the opcode */ - do { - if ((op->op1 == op1) && (op->op2 == op2)) - break; - op++; - } while (op->name); - - if (!op || !op->name) - return 0; - - while (op->op1 == op1 && op->op2 == op2) - { - /* scan through all the formats for the opcode */ - while (index = op->format[i++]) - { - f = (struct d30v_format *)&d30v_format_table[index]; - while (f->form == index) - { - if ((!is_long || f->form >= LONG) && (f->modifier == mod)) - { - insn->form = f; - break; - } - f++; - } - if (insn->form) - break; - } - if (insn->form) - break; - op++; - i=0; - } - if (insn->form == NULL) - return 0; - - insn->op = op; - insn->ecc = (num >> 28) & 0x7; - return 1; -} - - -static void -print_insn ( info, memaddr, num, insn, is_long ) - struct disassemble_info *info; - bfd_vma memaddr; - long long num; - struct d30v_insn *insn; - int is_long; -{ - char buffer[128]; - int val, opnum, need_comma=0; - struct d30v_operand *oper; - int i, match, opind=0, need_paren=0, found_control=0; - - (*info->fprintf_func) (info->stream, "%s",insn->op->name); - - /* check for CMP or CMPU */ - if (d30v_operand_table[insn->form->operands[0]].flags & OPERAND_NAME) - { - opind++; - val = extract_value(num,(struct d30v_operand *)&d30v_operand_table[insn->form->operands[0]],is_long); - (*info->fprintf_func) (info->stream, "%s",d30v_cc_names[val]); - } - - if (insn->ecc) - (*info->fprintf_func) (info->stream, "/%s",d30v_ecc_names[insn->ecc]); - - (*info->fprintf_func) (info->stream, "\t"); - - while (opnum = insn->form->operands[opind++]) - { - oper = (struct d30v_operand *)&d30v_operand_table[opnum]; - - if (need_comma && oper->flags != OPERAND_PLUS && oper->flags != OPERAND_MINUS) - { - need_comma=0; - (*info->fprintf_func) (info->stream, ", "); - } - - if (oper->flags == OPERAND_ATMINUS) - { - (*info->fprintf_func) (info->stream, "@-"); - continue; - } - if (oper->flags == OPERAND_MINUS) - { - (*info->fprintf_func) (info->stream, "-"); - continue; - } - if (oper->flags == OPERAND_PLUS) - { - (*info->fprintf_func) (info->stream, "+"); - continue; - } - if (oper->flags == OPERAND_ATSIGN) - { - (*info->fprintf_func) (info->stream, "@"); - continue; - } - if (oper->flags == OPERAND_ATPAR) - { - (*info->fprintf_func) (info->stream, "@("); - need_paren = 1; - continue; - } - - if (oper->flags == OPERAND_SPECIAL) - continue; - - val = extract_value(num, oper, is_long); - - if (oper->flags & OPERAND_REG) - { - match = 0; - if (oper->flags & OPERAND_CONTROL) - { - struct d30v_operand *oper3 = - (struct d30v_operand *)&d30v_operand_table[insn->form->operands[2]]; - int id = extract_value (num, oper3, is_long ); - found_control = 1; - switch ( id ) - { - case 0: - val |= OPERAND_CONTROL; - break; - case 1: - case 2: - val = OPERAND_CONTROL + MAX_CONTROL_REG + id; - break; - case 3: - val |= OPERAND_FLAG; - break; - default: - fprintf(stderr,"illegal id (%d)\n",id); - } - } - else if (oper->flags & OPERAND_ACC) - val |= OPERAND_ACC; - else if (oper->flags & OPERAND_FLAG) - val |= OPERAND_FLAG; - for (i=0;i<reg_name_cnt();i++) - { - if (val == pre_defined_registers[i].value) - { - if (pre_defined_registers[i].pname) - (*info->fprintf_func) (info->stream, "%s",pre_defined_registers[i].pname); - else - (*info->fprintf_func) (info->stream, "%s",pre_defined_registers[i].name); - match=1; - break; - } - } - if (match==0) - { - /* this would only get executed if a register was not in the - register table */ - (*info->fprintf_func) (info->stream, "<unknown register %d>",val & 0x3F); - } - } - else if (insn->op->reloc_flag == RELOC_PCREL) - { - long max; - int neg=0; - max = (1 << (oper->bits - 1)); - if (val & max) - { - if (oper->bits == 32) - val = -val; - else - val = -val & ((1 << oper->bits)-1); - neg = 1; - } - if (neg) - (*info->print_address_func) ((memaddr - val) & PC_MASK, info); - else - (*info->print_address_func) ((memaddr + val) & PC_MASK, info); - } - else if (insn->op->reloc_flag == RELOC_ABS) - { - (*info->print_address_func) (val, info); - } - else - { - if (oper->flags & OPERAND_SIGNED) - { - int max = (1 << (oper->bits - 1)); - if (val & max) - { - val = -val & ((1 << oper->bits) - 1); - (*info->fprintf_func) (info->stream, "-"); - } - } - (*info->fprintf_func) (info->stream, "0x%x",val); - } - /* if there is another operand, then write a comma and space */ - if (insn->form->operands[opind] && !(found_control && opind == 2)) - need_comma = 1; - } - if (need_paren) - (*info->fprintf_func) (info->stream, ")"); -} - - - -static int -extract_value (num, oper, is_long) - long long num; - struct d30v_operand *oper; - int is_long; -{ - int val; - int shift = 12 - oper->position; - int mask = (0xFFFFFFFF >> (32 - oper->bits)); - - if (is_long) - { - if (oper->bits == 32) - { - /* piece together 32-bit constant */ - val = num & 0x3FFFF | (num & 0xFF00000) >> 2 | - (num & 0x3F00000000LL) >> 6; - } - else - val = (num >> (32 + shift)) & mask; - } - else - val = (num >> shift) & mask; - - if (oper->flags & OPERAND_SHIFT) - val <<= 3; - - return val; -} diff --git a/opcodes/d30v-opc.c b/opcodes/d30v-opc.c deleted file mode 100644 index 4e50aa52672..00000000000 --- a/opcodes/d30v-opc.c +++ /dev/null @@ -1,500 +0,0 @@ -/* d30v-opc.c -- D30V opcode list - Copyright 1997, 1998 Free Software Foundation, Inc. - Written by Martin Hunt, Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -2, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include <stdio.h> -#include "ansidecl.h" -#include "opcode/d30v.h" - - -/* This table is sorted. */ -/* If you add anything, it MUST be in alphabetical order */ -/* The first field is the name the assembler uses when looking */ -/* up orcodes. The second field is the name the disassembler will use. */ -/* This allows the assembler to assemble references to r63 (for example) */ -/* or "sp". The disassembler will always use the preferred form (sp) */ -const struct pd_reg pre_defined_registers[] = -{ - { "a0", NULL, OPERAND_ACC+0 }, - { "a1", NULL, OPERAND_ACC+1 }, - { "bpc", NULL, OPERAND_CONTROL+3 }, - { "bpsw", NULL, OPERAND_CONTROL+1 }, - { "c", "c", OPERAND_FLAG+7 }, - { "cr0", "psw", OPERAND_CONTROL }, - { "cr1", "bpsw", OPERAND_CONTROL+1 }, - { "cr10", "mod_s", OPERAND_CONTROL+10 }, - { "cr11", "mod_e", OPERAND_CONTROL+11 }, - { "cr12", NULL, OPERAND_CONTROL+12 }, - { "cr13", NULL, OPERAND_CONTROL+13 }, - { "cr14", "iba", OPERAND_CONTROL+14 }, - { "cr15", "eit_vb", OPERAND_CONTROL+15 }, - { "cr16", "int_s", OPERAND_CONTROL+16 }, - { "cr17", "int_m", OPERAND_CONTROL+17 }, - { "cr18", NULL, OPERAND_CONTROL+18 }, - { "cr19", NULL, OPERAND_CONTROL+19 }, - { "cr2", "pc", OPERAND_CONTROL+2 }, - { "cr20", NULL, OPERAND_CONTROL+20 }, - { "cr21", NULL, OPERAND_CONTROL+21 }, - { "cr22", NULL, OPERAND_CONTROL+22 }, - { "cr23", NULL, OPERAND_CONTROL+23 }, - { "cr24", NULL, OPERAND_CONTROL+24 }, - { "cr25", NULL, OPERAND_CONTROL+25 }, - { "cr26", NULL, OPERAND_CONTROL+26 }, - { "cr27", NULL, OPERAND_CONTROL+27 }, - { "cr28", NULL, OPERAND_CONTROL+28 }, - { "cr29", NULL, OPERAND_CONTROL+29 }, - { "cr3", "bpc", OPERAND_CONTROL+3 }, - { "cr30", NULL, OPERAND_CONTROL+30 }, - { "cr31", NULL, OPERAND_CONTROL+31 }, - { "cr32", NULL, OPERAND_CONTROL+32 }, - { "cr33", NULL, OPERAND_CONTROL+33 }, - { "cr34", NULL, OPERAND_CONTROL+34 }, - { "cr35", NULL, OPERAND_CONTROL+35 }, - { "cr36", NULL, OPERAND_CONTROL+36 }, - { "cr37", NULL, OPERAND_CONTROL+37 }, - { "cr38", NULL, OPERAND_CONTROL+38 }, - { "cr39", NULL, OPERAND_CONTROL+39 }, - { "cr4", "dpsw", OPERAND_CONTROL+4 }, - { "cr40", NULL, OPERAND_CONTROL+40 }, - { "cr41", NULL, OPERAND_CONTROL+41 }, - { "cr42", NULL, OPERAND_CONTROL+42 }, - { "cr43", NULL, OPERAND_CONTROL+43 }, - { "cr44", NULL, OPERAND_CONTROL+44 }, - { "cr45", NULL, OPERAND_CONTROL+45 }, - { "cr46", NULL, OPERAND_CONTROL+46 }, - { "cr47", NULL, OPERAND_CONTROL+47 }, - { "cr48", NULL, OPERAND_CONTROL+48 }, - { "cr49", NULL, OPERAND_CONTROL+49 }, - { "cr5","dpc", OPERAND_CONTROL+5 }, - { "cr50", NULL, OPERAND_CONTROL+50 }, - { "cr51", NULL, OPERAND_CONTROL+51 }, - { "cr52", NULL, OPERAND_CONTROL+52 }, - { "cr53", NULL, OPERAND_CONTROL+53 }, - { "cr54", NULL, OPERAND_CONTROL+54 }, - { "cr55", NULL, OPERAND_CONTROL+55 }, - { "cr56", NULL, OPERAND_CONTROL+56 }, - { "cr57", NULL, OPERAND_CONTROL+57 }, - { "cr58", NULL, OPERAND_CONTROL+58 }, - { "cr59", NULL, OPERAND_CONTROL+59 }, - { "cr6", NULL, OPERAND_CONTROL+6 }, - { "cr60", NULL, OPERAND_CONTROL+60 }, - { "cr61", NULL, OPERAND_CONTROL+61 }, - { "cr62", NULL, OPERAND_CONTROL+62 }, - { "cr63", NULL, OPERAND_CONTROL+63 }, - { "cr7", "rpt_c", OPERAND_CONTROL+7 }, - { "cr8", "rpt_s", OPERAND_CONTROL+8 }, - { "cr9", "rpt_e", OPERAND_CONTROL+9 }, - { "dpc", NULL, OPERAND_CONTROL+5 }, - { "dpsw", NULL, OPERAND_CONTROL+4 }, - { "eit_vb", NULL, OPERAND_CONTROL+15 }, - { "f0", NULL, OPERAND_FLAG+0 }, - { "f1", NULL, OPERAND_FLAG+1 }, - { "f2", NULL, OPERAND_FLAG+2 }, - { "f3", NULL, OPERAND_FLAG+3 }, - { "f4", "s", OPERAND_FLAG+4 }, - { "f5", "v", OPERAND_FLAG+5 }, - { "f6", "va", OPERAND_FLAG+6 }, - { "f7", "c", OPERAND_FLAG+7 }, - { "iba", NULL, OPERAND_CONTROL+14 }, - { "int_m", NULL, OPERAND_CONTROL+17 }, - { "int_s", NULL, OPERAND_CONTROL+16 }, - { "link", "r62", 62 }, - { "mod_e", NULL, OPERAND_CONTROL+11 }, - { "mod_s", NULL, OPERAND_CONTROL+10 }, - { "pc", NULL, OPERAND_CONTROL+2 }, - { "psw", NULL, OPERAND_CONTROL }, - { "pswh", NULL, OPERAND_CONTROL+MAX_CONTROL_REG+2 }, - { "pswl", NULL, OPERAND_CONTROL+MAX_CONTROL_REG+1 }, - { "r0", NULL, 0 }, - { "r1", NULL, 1 }, - { "r10", NULL, 10 }, - { "r11", NULL, 11 }, - { "r12", NULL, 12 }, - { "r13", NULL, 13 }, - { "r14", NULL, 14 }, - { "r15", NULL, 15 }, - { "r16", NULL, 16 }, - { "r17", NULL, 17 }, - { "r18", NULL, 18 }, - { "r19", NULL, 19 }, - { "r2", NULL, 2 }, - { "r20", NULL, 20 }, - { "r21", NULL, 21 }, - { "r22", NULL, 22 }, - { "r23", NULL, 23 }, - { "r24", NULL, 24 }, - { "r25", NULL, 25 }, - { "r26", NULL, 26 }, - { "r27", NULL, 27 }, - { "r28", NULL, 28 }, - { "r29", NULL, 29 }, - { "r3", NULL, 3 }, - { "r30", NULL, 30 }, - { "r31", NULL, 31 }, - { "r32", NULL, 32 }, - { "r33", NULL, 33 }, - { "r34", NULL, 34 }, - { "r35", NULL, 35 }, - { "r36", NULL, 36 }, - { "r37", NULL, 37 }, - { "r38", NULL, 38 }, - { "r39", NULL, 39 }, - { "r4", NULL, 4 }, - { "r40", NULL, 40 }, - { "r41", NULL, 41 }, - { "r42", NULL, 42 }, - { "r43", NULL, 43 }, - { "r44", NULL, 44 }, - { "r45", NULL, 45 }, - { "r46", NULL, 46 }, - { "r47", NULL, 47 }, - { "r48", NULL, 48 }, - { "r49", NULL, 49 }, - { "r5", NULL, 5 }, - { "r50", NULL, 50 }, - { "r51", NULL, 51 }, - { "r52", NULL, 52 }, - { "r53", NULL, 53 }, - { "r54", NULL, 54 }, - { "r55", NULL, 55 }, - { "r56", NULL, 56 }, - { "r57", NULL, 57 }, - { "r58", NULL, 58 }, - { "r59", NULL, 59 }, - { "r6", NULL, 6 }, - { "r60", NULL, 60 }, - { "r61", NULL, 61 }, - { "r62", "link", 62 }, - { "r63", "sp", 63 }, - { "r7", NULL, 7 }, - { "r8", NULL, 8 }, - { "r9", NULL, 9 }, - { "rpt_c", NULL, OPERAND_CONTROL+7 }, - { "rpt_e", NULL, OPERAND_CONTROL+9 }, - { "rpt_s", NULL, OPERAND_CONTROL+8 }, - { "s", NULL, OPERAND_FLAG+4 }, - { "sp", NULL, 63 }, - { "v", NULL, OPERAND_FLAG+5 }, - { "va", NULL, OPERAND_FLAG+6 }, -}; - -int -reg_name_cnt() -{ - return (sizeof(pre_defined_registers) / sizeof(struct pd_reg)); -} - -/* OPCODE TABLE */ -/* The format of this table is defined in opcode/d30v.h */ -const struct d30v_opcode d30v_opcode_table[] = { - { "abs", IALU1, 0x8, { SHORT_U }, EITHER, 0, 0, 0 }, - { "add", IALU1, 0x0, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, - { "add2h", IALU1, 0x1, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, - { "addc", IALU1, 0x4, { SHORT_A, LONG }, EITHER, FLAG_C, FLAG_CVVA, 0 }, - { "addhlll", IALU1, 0x10, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, - { "addhllh", IALU1, 0x11, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, - { "addhlhl", IALU1, 0x12, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, - { "addhlhh", IALU1, 0x13, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, - { "addhhll", IALU1, 0x14, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, - { "addhhlh", IALU1, 0x15, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, - { "addhhhl", IALU1, 0x16, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, - { "addhhhh", IALU1, 0x17, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, - { "adds", IALU1, 0x6, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 }, - { "adds2h", IALU1, 0x7, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, - { "and", LOGIC, 0x18, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, - { "andfg", LOGIC, 0x8, { SHORT_F }, EITHER, 0, 0, 0 }, - { "avg", IALU1, 0xa, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, - { "avg2h", IALU1, 0xb, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, - { "bclr", LOGIC, 0x3, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 }, - { "bnot", LOGIC, 0x1, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 }, - { "bra", BRA, 0, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JMP, 0, RELOC_PCREL }, - { "bratnz", BRA, 0x4, { SHORT_B3b, LONG_2b }, MU, FLAG_JMP, 0, RELOC_PCREL }, - { "bratzr", BRA, 0x4, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, 0, RELOC_PCREL }, - { "bset", LOGIC, 0x2, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 }, - { "bsr", BRA, 0x2, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JSR, 0, RELOC_PCREL }, - { "bsrtnz", BRA, 0x6, { SHORT_B3b, LONG_2b }, MU, FLAG_JSR, 0, RELOC_PCREL }, - { "bsrtzr", BRA, 0x6, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, 0, RELOC_PCREL }, - { "btst", LOGIC, 0, { SHORT_AF }, EITHER_BUT_PREFER_MU, 0, 0, 0 }, - { "cmp", LOGIC, 0xC, { SHORT_CMP, LONG_CMP }, EITHER, 0, 0, 0 }, - { "cmpu", LOGIC, 0xD, { SHORT_CMPU, LONG_CMP }, EITHER, 0, 0, 0 }, - { "dbra", BRA, 0x10, { SHORT_B3, LONG_2 }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_PCREL }, - { "dbrai", BRA, 0x14, { SHORT_D2, LONG_D }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_PCREL }, - { "dbsr", BRA, 0x12, { SHORT_B3, LONG_2 }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_PCREL }, - { "dbsri", BRA, 0x16, { SHORT_D2, LONG_D }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_PCREL }, - { "dbt", BRA, 0xb, { SHORT_NONE }, MU, 0, FLAG_LKR, 0 }, - { "djmp", BRA, 0x11, { SHORT_B3, LONG_2 }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_ABS }, - { "djmpi", BRA, 0x15, { SHORT_D2, LONG_D }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_ABS }, - { "djsr", BRA, 0x13, { SHORT_B3, LONG_2 }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_ABS }, - { "djsri", BRA, 0x17, { SHORT_D2, LONG_D }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_ABS }, - { "jmp", BRA, 0x1, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JMP, 0, RELOC_ABS }, - { "jmptnz", BRA, 0x5, { SHORT_B3b, LONG_2b }, MU, FLAG_JMP, 0, RELOC_ABS }, - { "jmptzr", BRA, 0x5, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, 0, RELOC_ABS }, - { "joinll", IALU1, 0xC, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, - { "joinlh", IALU1, 0xD, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, - { "joinhl", IALU1, 0xE, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, - { "joinhh", IALU1, 0xF, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, - { "jsr", BRA, 0x3, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JSR, 0, RELOC_ABS }, - { "jsrtnz", BRA, 0x7, { SHORT_B3b, LONG_2b }, MU, FLAG_JSR, 0, RELOC_ABS }, - { "jsrtzr", BRA, 0x7, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, 0, RELOC_ABS }, - { "ld2h", IMEM, 0x3, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM, 0, 0 }, - { "ld2w", IMEM, 0x6, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM | FLAG_2WORD, 0, 0 }, - { "ld4bh", IMEM, 0x5, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM | FLAG_2WORD, 0, 0 }, - { "ld4bhu", IMEM, 0xd, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM, 0, 0 }, - { "ldb", IMEM, 0, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, - { "ldbu", IMEM, 0x9, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, - { "ldh", IMEM, 0x2, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, - { "ldhh", IMEM, 0x1, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, - { "ldhu", IMEM, 0xa, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, - { "ldw", IMEM, 0x4, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, - { "mac0", IALU2, 0x14, { SHORT_A }, IU, FLAG_MUL32, 0, 0 }, - { "mac1", IALU2, 0x14, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 }, - { "macs0", IALU2, 0x15, { SHORT_A }, IU, FLAG_MUL32, 0, 0 }, - { "macs1", IALU2, 0x15, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 }, - { "moddec", IMEM, 0x7, { SHORT_MODDEC }, MU, 0, 0, 0 }, - { "modinc", IMEM, 0x7, { SHORT_MODINC }, MU, 0, 0, 0 }, - { "msub0", IALU2, 0x16, { SHORT_A }, IU, FLAG_MUL32, 0, 0 }, - { "msub1", IALU2, 0x16, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 }, - { "msubs0", IALU2, 0x17, { SHORT_A }, IU, FLAG_MUL32, 0, 0 }, - { "msubs1", IALU2, 0x17, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 }, - { "mul", IALU2, 0x10, { SHORT_A }, IU, FLAG_MUL32, 0, 0 }, - { "mul2h", IALU2, 0, { SHORT_A }, IU, FLAG_MUL16, 0, 0 }, - { "mulhxll", IALU2, 0x4, { SHORT_A }, IU, FLAG_MUL16, 0, 0 }, - { "mulhxlh", IALU2, 0x5, { SHORT_A }, IU, FLAG_MUL16, 0, 0 }, - { "mulhxhl", IALU2, 0x6, { SHORT_A }, IU, FLAG_MUL16, 0, 0 }, - { "mulhxhh", IALU2, 0x7, { SHORT_A }, IU, FLAG_MUL16, 0, 0 }, - { "mulx", IALU2, 0x18, { SHORT_AA }, IU, FLAG_MUL32, 0, 0 }, - { "mulx2h", IALU2, 0x1, { SHORT_A2 }, IU, FLAG_MUL16, 0, 0 }, - { "mulxs", IALU2, 0x19, { SHORT_AA }, IU, FLAG_MUL32, 0, 0 }, - { "mvfacc", IALU2, 0x1f, { SHORT_RA }, IU, 0, 0, 0 }, - { "mvfsys", BRA, 0x1e, { SHORT_C1 }, MU, FLAG_ALL, FLAG_ALL, 0 }, - { "mvtacc", IALU2, 0xf, { SHORT_AA }, IU, 0, 0, 0 }, - { "mvtsys", BRA, 0xe, { SHORT_C2 }, MU, FLAG_ALL, FLAG_ALL | FLAG_LKR, 0 }, - { "nop", BRA, 0xF, { SHORT_NONE }, EITHER, 0, 0, 0 }, - { "not", LOGIC, 0x19, { SHORT_U }, EITHER, 0, 0, 0 }, - { "notfg", LOGIC, 0x9, { SHORT_UF }, EITHER, 0, 0, 0 }, - { "or", LOGIC, 0x1a, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, - { "orfg", LOGIC, 0xa, { SHORT_F }, EITHER, 0, 0, 0 }, - { "reit", BRA, 0x8, { SHORT_NONE }, MU, FLAG_SM, FLAG_SM | FLAG_LKR, 0 }, - { "repeat", BRA, 0x18, { SHORT_D1, LONG_2 }, MU, FLAG_RP, FLAG_RP, RELOC_PCREL }, - { "repeati", BRA, 0x1a, { SHORT_D2B, LONG_Db }, MU, FLAG_RP, FLAG_RP, RELOC_PCREL }, - { "rot", LOGIC, 0x14, { SHORT_A }, EITHER, 0, 0, 0 }, - { "rot2h", LOGIC, 0x15, { SHORT_A }, EITHER, 0, 0, 0 }, - { "rtd", BRA, 0xa, { SHORT_NONE }, MU, 0, FLAG_LKR, 0 }, - { "sat", IALU2, 0x8, { SHORT_A5 }, IU, 0, 0, 0 }, - { "sat2h", IALU2, 0x9, { SHORT_A5 }, IU, 0, 0, 0 }, - { "sathl", IALU2, 0x1c, { SHORT_A5 }, IU, FLAG_ADDSUBppp, 0, 0 }, - { "sathh", IALU2, 0x1d, { SHORT_A5 }, IU, FLAG_ADDSUBppp, 0, 0 }, - { "satz", IALU2, 0xa, { SHORT_A5 }, IU, 0, 0, 0 }, - { "satz2h", IALU2, 0xb, { SHORT_A5 }, IU, 0, 0, 0 }, - { "sra", LOGIC, 0x10, { SHORT_A }, EITHER, 0, 0, 0 }, - { "sra2h", LOGIC, 0x11, { SHORT_A }, EITHER, 0, 0, 0 }, - { "srahh", LOGIC, 0x5, { SHORT_A }, EITHER, 0, 0, 0 }, - { "srahl", LOGIC, 0x4, { SHORT_A }, EITHER, 0, 0, 0 }, - { "src", LOGIC, 0x16, { SHORT_A }, EITHER, FLAG_ADDSUBppp, 0, 0 }, - { "srl", LOGIC, 0x12, { SHORT_A }, EITHER, 0, 0, 0 }, - { "srl2h", LOGIC, 0x13, { SHORT_A }, EITHER, 0, 0, 0 }, - { "srlhh", LOGIC, 0x7, { SHORT_A }, EITHER, 0, 0, 0 }, - { "srlhl", LOGIC, 0x6, { SHORT_A }, EITHER, 0, 0, 0 }, - { "st2h", IMEM, 0x13, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM, 0 }, - { "st2w", IMEM, 0x16, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_2WORD, 0 }, - { "st4hb", IMEM, 0x15, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_2WORD, 0 }, - { "stb", IMEM, 0x10, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 }, - { "sth", IMEM, 0x12, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 }, - { "sthh", IMEM, 0x11, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 }, - { "stw", IMEM, 0x14, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 }, - { "sub", IALU1, 0x2, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, - { "sub2h", IALU1, 0x3, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, - { "subb", IALU1, 0x5, { SHORT_A, LONG}, EITHER, FLAG_C, FLAG_CVVA, 0 }, - { "subhlll", IALU1, 0x18, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, - { "subhllh", IALU1, 0x19, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, - { "subhlhl", IALU1, 0x1a, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, - { "subhlhh", IALU1, 0x1b, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, - { "subhhll", IALU1, 0x1c, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, - { "subhhlh", IALU1, 0x1d, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, - { "subhhhl", IALU1, 0x1e, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, - { "subhhhh", IALU1, 0x1f, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, - { "trap", BRA, 0x9, { SHORT_B1, SHORT_T}, MU, 0, FLAG_SM | FLAG_LKR, 0 }, - { "xor", LOGIC, 0x1b, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, - { "xorfg", LOGIC, 0xb, { SHORT_F }, EITHER, 0, 0, 0 }, - { NULL, 0, 0, { 0 }, 0, 0, 0, 0 }, -}; - - -/* now define the operand types */ -/* format is length, bits, position, flags */ -const struct d30v_operand d30v_operand_table[] = -{ -#define UNUSED (0) - { 0, 0, 0, 0 }, -#define Ra (UNUSED + 1) - { 6, 6, 0, OPERAND_REG|OPERAND_DEST }, -#define Ra2 (Ra + 1) - { 6, 6, 0, OPERAND_REG|OPERAND_DEST|OPERAND_2REG }, -#define Ra3 (Ra2 + 1) - { 6, 6, 0, OPERAND_REG }, -#define Rb (Ra3 + 1) - { 6, 6, 6, OPERAND_REG }, -#define Rc (Rb + 1) - { 6, 6, 12, OPERAND_REG }, -#define Aa (Rc + 1) - { 6, 1, 0, OPERAND_ACC|OPERAND_REG|OPERAND_DEST }, -#define Ab (Aa + 1) - { 6, 1, 6, OPERAND_ACC|OPERAND_REG }, -#define IMM5 (Ab + 1) - { 6, 5, 12, OPERAND_NUM }, -#define IMM5U (IMM5 + 1) - { 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED }, -#define IMM5S3 (IMM5U + 1) - { 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED }, -#define IMM6 (IMM5S3 + 1) - { 6, 6, 12, OPERAND_NUM|OPERAND_SIGNED }, -#define IMM6U (IMM6 + 1) - { 6, 6, 0, OPERAND_NUM }, -#define IMM6U2 (IMM6U + 1) - { 6, 6, 12, OPERAND_NUM }, -#define IMM6S3 (IMM6U2 + 1) - { 6, 6, 0, OPERAND_NUM|OPERAND_SHIFT }, -#define IMM12S3 (IMM6S3 + 1) - { 12, 12, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT }, -#define IMM12S3U (IMM12S3 + 1) - { 12, 12, 12, OPERAND_NUM|OPERAND_SHIFT }, -#define IMM18S3 (IMM12S3U + 1) - { 18, 18, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT }, -#define IMM32 (IMM18S3 + 1) - { 32, 32, 0, OPERAND_NUM }, -#define Fa (IMM32 + 1) - { 6, 3, 0, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST }, -#define Fb (Fa + 1) - { 6, 3, 6, OPERAND_REG | OPERAND_FLAG }, -#define Fc (Fb + 1) - { 6, 3, 12, OPERAND_REG | OPERAND_FLAG }, -#define ATSIGN (Fc + 1) - { 0, 0, 0, OPERAND_ATSIGN}, -#define ATPAR (ATSIGN + 1) /* "@(" */ - { 0, 0, 0, OPERAND_ATPAR}, -#define PLUS (ATPAR + 1) /* postincrement */ - { 0, 0, 0, OPERAND_PLUS}, -#define MINUS (PLUS + 1) /* postdecrement */ - { 0, 0, 0, OPERAND_MINUS}, -#define ATMINUS (MINUS + 1) /* predecrement */ - { 0, 0, 0, OPERAND_ATMINUS}, -#define Ca (ATMINUS + 1) /* control register */ - { 6, 6, 0, OPERAND_REG|OPERAND_CONTROL|OPERAND_DEST}, -#define Cb (Ca + 1) /* control register */ - { 6, 6, 6, OPERAND_REG|OPERAND_CONTROL}, -#define CC (Cb + 1) /* condition code (CMPcc and CMPUcc) */ - { 3, 3, -3, OPERAND_NAME}, -#define Fa2 (CC + 1) /* flag register (CMPcc and CMPUcc) */ - { 3, 3, 0, OPERAND_REG|OPERAND_FLAG|OPERAND_DEST}, -#define Fake (Fa2 + 1) /* place holder for "id" field in mvfsys and mvtsys */ - { 6, 2, 12, OPERAND_SPECIAL}, -}; - -/* now we need to define the instruction formats */ -const struct d30v_format d30v_format_table[] = -{ - { 0, 0, { 0 } }, - { SHORT_M, 0, { Ra, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */ - { SHORT_M, 1, { Ra, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */ - { SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */ - { SHORT_M, 3, { Ra, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) */ - { SHORT_M2, 0, { Ra2, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */ - { SHORT_M2, 1, { Ra2, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */ - { SHORT_M2, 2, { Ra2, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */ - { SHORT_M2, 3, { Ra2, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) */ - { SHORT_A, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */ - { SHORT_A, 2, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 */ - { SHORT_B1, 0, { Rc } }, /* Rc */ - { SHORT_B2, 2, { IMM18S3 } }, /* imm18 */ - { SHORT_B3, 0, { Ra3, Rc } }, /* Ra,Rc */ - { SHORT_B3, 2, { Ra3, IMM12S3 } }, /* Ra,imm12 */ - { SHORT_B3b, 1, { Ra3, Rc } }, /* Ra,Rc */ - { SHORT_B3b, 3, { Ra3, IMM12S3 } }, /* Ra,imm12 */ - { SHORT_D1, 0, { Ra, Rc } }, /* Ra,Rc */ - { SHORT_D1, 2, { Ra, IMM12S3 } }, /* Ra,imm12s3 */ - { SHORT_D2, 0, { IMM6S3, Rc } }, /* imm6s3,Rc */ - { SHORT_D2, 2, { IMM6S3, IMM12S3 } }, /* imm6s3,imm12s3 */ - { SHORT_D2B, 0, { IMM6U, Rc } }, /* imm6u,Rc */ - { SHORT_D2B, 2, { IMM6U, IMM12S3U } }, /* imm6u,imm12s3u */ - { SHORT_U, 0, { Ra, Rb } }, /* Ra,Rb */ - { SHORT_U, 2, { Ra, IMM12S3 } }, /* Ra,imm12 (repeat) */ - { SHORT_F, 0, { Fa, Fb, Fc } }, /* Fa,Fb,Fc (orfg, xorfg) */ - { SHORT_F, 2, { Fa, Fb, IMM6 } }, /* Fa,Fb,imm6 */ - { SHORT_AF, 0, { Fa, Rb, Rc } }, /* Fa,Rb,Rc */ - { SHORT_AF, 2, { Fa, Rb, IMM6 } }, /* Fa,Rb,imm6 */ - { SHORT_T, 2, { IMM5 } }, /* imm5s3 (trap) */ - { SHORT_A5, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */ - { SHORT_A5, 2, { Ra, Rb, IMM5 } }, /* Ra,Rb,imm5 (sat*) */ - { SHORT_CMP, 0, { CC, Fa2, Rb, Rc} }, /* CC Fa2,Rb,Rc */ - { SHORT_CMP, 2, { CC, Fa2, Rb, IMM6} }, /* CC Fa2,Rb,imm6 */ - { SHORT_CMPU, 0, { CC, Fa2, Rb, Rc} }, /* CC Fa2,Rb,Rc */ - { SHORT_CMPU, 2, { CC, Fa2, Rb, IMM6U2} }, /* CC Fa2,Rb,imm6 */ - { SHORT_A1, 1, { Ra, Rb, Rc } }, /* Ra,Rb,Rc for MAC where a=1 */ - { SHORT_A1, 3, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 for MAC where a=1 */ - { SHORT_AA, 0, { Aa, Rb, Rc } }, /* Aa,Rb,Rc */ - { SHORT_AA, 2, { Aa, Rb, IMM6 } }, /* Aa,Rb,imm6 */ - { SHORT_RA, 0, { Ra, Ab, Rc } }, /* Ra,Ab,Rc */ - { SHORT_RA, 2, { Ra, Ab, IMM6U2 } }, /* Ra,Ab,imm6u */ - { SHORT_MODINC, 1, { Rb, IMM5 } }, /* Rb,imm5 (modinc) */ - { SHORT_MODDEC, 3, { Rb, IMM5 } }, /* Rb,imm5 (moddec) */ - { SHORT_C1, 0, { Ra, Cb, Fake } }, /* Ra,Cb (mvfsys) */ - { SHORT_C2, 0, { Ca, Rb, Fake } }, /* Ca,Rb (mvtsys) */ - { SHORT_UF, 0, { Fa, Fb } }, /* Fa,Fb (notfg) */ - { SHORT_A2, 0, { Ra2, Rb, Rc } }, /* Ra2,Rb,Rc */ - { SHORT_A2, 2, { Ra2, Rb, IMM6 } }, /* Ra2,Rb,imm6 */ - { SHORT_A5S, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */ - { SHORT_A5S, 2, { Ra, Rb, IMM5U } }, /* Ra,Rb,imm5u (shifts) */ - { SHORT_NONE, 0, { 0 } }, /* no operands (nop, reit) */ - { LONG, 2, { Ra, Rb, IMM32 } }, /* Ra,Rb,imm32 */ - { LONG_U, 2, { IMM32 } }, /* imm32 */ - { LONG_AF, 2, { Fa, Rb, IMM32 } }, /* Fa,Rb,imm32 */ - { LONG_CMP, 2, { CC, Fa2, Rb, IMM32} }, /* CC Fa2,Rb,imm32 */ - { LONG_M, 2, { Ra, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */ - { LONG_M2, 2, { Ra2, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */ - { LONG_2, 2, { Ra3, IMM32 } }, /* Ra,imm32 */ - { LONG_2b, 3, { Ra3, IMM32 } }, /* Ra,imm32 */ - { LONG_D, 2, { IMM6S3, IMM32 } }, /* imm6s3,imm32 */ - { LONG_Db, 2, { IMM6U, IMM32 } }, /* imm6,imm32 */ - { 0, 0, { 0 } }, -}; - -const char *d30v_ecc_names[] = -{ - "al", - "tx", - "fx", - "xt", - "xf", - "tt", - "tf", - "res" -}; - -const char *d30v_cc_names[] = -{ - "eq", - "ne", - "gt", - "ge", - "lt", - "le", - "ps", - "ng", - NULL -}; diff --git a/opcodes/dep-in.sed b/opcodes/dep-in.sed deleted file mode 100644 index ebf69ebf4b1..00000000000 --- a/opcodes/dep-in.sed +++ /dev/null @@ -1,19 +0,0 @@ -:loop -/\\$/N -s/\\\n */ /g -t loop - -s! @BFD_H@! $(BFD_H)!g -s!@INCDIR@!$(INCDIR)!g -s!@BFDDIR@!$(BFDDIR)!g -s!@SRCDIR@/!!g - -s/\\\n */ /g - -s/ *$// -s/ */ /g -s/ *:/:/g -/:$/d - -s/\(.\{50\}[^ ]*\) /\1 \\\ - /g diff --git a/opcodes/dis-buf.c b/opcodes/dis-buf.c deleted file mode 100644 index 34384347f8c..00000000000 --- a/opcodes/dis-buf.c +++ /dev/null @@ -1,104 +0,0 @@ -/* Disassemble from a buffer, for GNU. - Copyright (C) 1993, 1994, 1998 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include "dis-asm.h" -#include <errno.h> -#include "opintl.h" - -/* Get LENGTH bytes from info's buffer, at target address memaddr. - Transfer them to myaddr. */ -int -buffer_read_memory (memaddr, myaddr, length, info) - bfd_vma memaddr; - bfd_byte *myaddr; - int length; - struct disassemble_info *info; -{ - if (memaddr < info->buffer_vma - || memaddr + length > info->buffer_vma + info->buffer_length) - /* Out of bounds. Use EIO because GDB uses it. */ - return EIO; - memcpy (myaddr, info->buffer + (memaddr - info->buffer_vma), length); - return 0; -} - -/* Print an error message. We can assume that this is in response to - an error return from buffer_read_memory. */ -void -perror_memory (status, memaddr, info) - int status; - bfd_vma memaddr; - struct disassemble_info *info; -{ - if (status != EIO) - /* Can't happen. */ - info->fprintf_func (info->stream, _("Unknown error %d\n"), status); - else - /* Actually, address between memaddr and memaddr + len was - out of bounds. */ - info->fprintf_func (info->stream, - _("Address 0x%x is out of bounds.\n"), memaddr); -} - -/* This could be in a separate file, to save miniscule amounts of space - in statically linked executables. */ - -/* Just print the address is hex. This is included for completeness even - though both GDB and objdump provide their own (to print symbolic - addresses). */ - -void -generic_print_address (addr, info) - bfd_vma addr; - struct disassemble_info *info; -{ - (*info->fprintf_func) (info->stream, "0x%x", addr); -} - -/* Just concatenate the address as hex. This is included for - completeness even though both GDB and objdump provide their own (to - print symbolic addresses). */ - -void -generic_strcat_address (addr, buf, len) - bfd_vma addr; - char *buf; - int len; -{ - if (buf != (char *)NULL && len > 0) - { - char tmpBuf[30]; - - sprintf(tmpBuf, "0x%x", addr); - if ((strlen(buf) + strlen(tmpBuf)) <= len) - strcat(buf, tmpBuf); - else - strncat(buf, tmpBuf, (len - strlen(buf))); - } - return; -} - -/* Just return the given address. */ - -int -generic_symbol_at_address (addr, info) - bfd_vma addr; - struct disassemble_info * info; -{ - return 1; -} diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c deleted file mode 100644 index 31f6a541299..00000000000 --- a/opcodes/disassemble.c +++ /dev/null @@ -1,234 +0,0 @@ -/* Select disassembly routine for specified architecture. - Copyright (C) 1994, 1995, 1996, 1997 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "ansidecl.h" -#include "dis-asm.h" - -#ifdef ARCH_all -#define ARCH_a29k -#define ARCH_alpha -#define ARCH_arc -#define ARCH_arm -#define ARCH_d10v -/* start-sanitize-d30v */ -#define ARCH_d30v -/* end-sanitize-d30v */ -#define ARCH_h8300 -#define ARCH_h8500 -#define ARCH_hppa -#define ARCH_i386 -#define ARCH_i960 -#define ARCH_m32r -#define ARCH_m68k -#define ARCH_m88k -#define ARCH_mips -#define ARCH_mn10200 -#define ARCH_mn10300 -#define ARCH_ns32k -#define ARCH_powerpc -#define ARCH_rs6000 -#define ARCH_sh -#define ARCH_sparc -/* start-sanitize-tic80 */ -#define ARCH_tic80 -/* end-sanitize-tic80 */ -#define ARCH_v850 -#define ARCH_w65 -#define ARCH_z8k -#endif - -/* start-sanitize-sky */ -#if defined (ARCH_dvp) && ! defined (ARCH_mips) -#define ARCH_mips -#endif -/* end-sanitize-sky */ - -disassembler_ftype -disassembler (abfd) - bfd *abfd; -{ - enum bfd_architecture a = bfd_get_arch (abfd); - disassembler_ftype disassemble; - - switch (a) - { - /* If you add a case to this table, also add it to the - ARCH_all definition right above this function. */ -#ifdef ARCH_a29k - case bfd_arch_a29k: - /* As far as I know we only handle big-endian 29k objects. */ - disassemble = print_insn_big_a29k; - break; -#endif -#ifdef ARCH_alpha - case bfd_arch_alpha: - disassemble = print_insn_alpha; - break; -#endif -#ifdef ARCH_arc - case bfd_arch_arc: - { - disassemble = arc_get_disassembler (bfd_get_mach (abfd), - bfd_big_endian (abfd)); - break; - } -#endif -#ifdef ARCH_arm - case bfd_arch_arm: - if (bfd_big_endian (abfd)) - disassemble = print_insn_big_arm; - else - disassemble = print_insn_little_arm; - break; -#endif -#ifdef ARCH_d10v - case bfd_arch_d10v: - disassemble = print_insn_d10v; - break; -#endif -/* start-sanitize-d30v */ -#ifdef ARCH_d30v - case bfd_arch_d30v: - disassemble = print_insn_d30v; - break; -#endif -/* end-sanitize-d30v */ -#ifdef ARCH_h8300 - case bfd_arch_h8300: - if (bfd_get_mach(abfd) == bfd_mach_h8300h) - disassemble = print_insn_h8300h; - else if (bfd_get_mach(abfd) == bfd_mach_h8300s) - disassemble = print_insn_h8300s; - else - disassemble = print_insn_h8300; - break; -#endif -#ifdef ARCH_h8500 - case bfd_arch_h8500: - disassemble = print_insn_h8500; - break; -#endif -#ifdef ARCH_hppa - case bfd_arch_hppa: - disassemble = print_insn_hppa; - break; -#endif -#ifdef ARCH_i386 - case bfd_arch_i386: - disassemble = print_insn_i386; - break; -#endif -#ifdef ARCH_i960 - case bfd_arch_i960: - disassemble = print_insn_i960; - break; -#endif -#ifdef ARCH_m32r - case bfd_arch_m32r: - disassemble = print_insn_m32r; - break; -#endif -#ifdef ARCH_m68k - case bfd_arch_m68k: - disassemble = print_insn_m68k; - break; -#endif -#ifdef ARCH_m88k - case bfd_arch_m88k: - disassemble = print_insn_m88k; - break; -#endif -#ifdef ARCH_ns32k - case bfd_arch_ns32k: - disassemble = print_insn_ns32k; - break; -#endif -#ifdef ARCH_mips - case bfd_arch_mips: - if (bfd_big_endian (abfd)) - disassemble = print_insn_big_mips; - else - disassemble = print_insn_little_mips; - break; -#endif -#ifdef ARCH_mn10200 - case bfd_arch_mn10200: - disassemble = print_insn_mn10200; - break; -#endif -#ifdef ARCH_mn10300 - case bfd_arch_mn10300: - disassemble = print_insn_mn10300; - break; -#endif -#ifdef ARCH_powerpc - case bfd_arch_powerpc: - if (bfd_big_endian (abfd)) - disassemble = print_insn_big_powerpc; - else - disassemble = print_insn_little_powerpc; - break; -#endif -#ifdef ARCH_rs6000 - case bfd_arch_rs6000: - disassemble = print_insn_rs6000; - break; -#endif -#ifdef ARCH_sh - case bfd_arch_sh: - if (bfd_big_endian (abfd)) - disassemble = print_insn_sh; - else - disassemble = print_insn_shl; - break; -#endif -#ifdef ARCH_sparc - case bfd_arch_sparc: - disassemble = print_insn_sparc; - break; -#endif -/* start-sanitize-tic80 */ -#ifdef ARCH_tic80 - case bfd_arch_tic80: - disassemble = print_insn_tic80; - break; -#endif -/* end-sanitize-tic80 */ -#ifdef ARCH_v850 - case bfd_arch_v850: - disassemble = print_insn_v850; - break; -#endif -#ifdef ARCH_w65 - case bfd_arch_w65: - disassemble = print_insn_w65; - break; -#endif -#ifdef ARCH_z8k - case bfd_arch_z8k: - if (bfd_get_mach(abfd) == bfd_mach_z8001) - disassemble = print_insn_z8001; - else - disassemble = print_insn_z8002; - break; -#endif - default: - return 0; - } - return disassemble; -} - diff --git a/opcodes/fr30-asm.c b/opcodes/fr30-asm.c deleted file mode 100644 index 8094201310a..00000000000 --- a/opcodes/fr30-asm.c +++ /dev/null @@ -1,1012 +0,0 @@ -/* Assembler interface for targets using CGEN. -*- C -*- - CGEN: Cpu tools GENerator - -THIS FILE IS USED TO GENERATE fr30-asm.c. - -Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. - -This file is part of the GNU Binutils and GDB, the GNU debugger. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include <ctype.h> -#include <stdio.h> -#include "ansidecl.h" -#include "bfd.h" -#include "symcat.h" -#include "fr30-opc.h" -#include "opintl.h" - -#undef min -#define min(a,b) ((a) < (b) ? (a) : (b)) -#undef max -#define max(a,b) ((a) > (b) ? (a) : (b)) - -#undef INLINE -#ifdef __GNUC__ -#define INLINE __inline__ -#else -#define INLINE -#endif - -/* Used by the ifield rtx function. */ -#define FLD(f) (fields->f) - -static const char * insert_normal - PARAMS ((CGEN_OPCODE_DESC, long, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); -static const char * parse_insn_normal - PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *, - const char **, CGEN_FIELDS *)); -static const char * insert_insn_normal - PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *, - CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); - -/* -- assembler routines inserted here */ -/* -- asm.c */ -/* Handle register lists for LDMx and STMx */ - -static int -parse_register_number (strp) - const char **strp; -{ - int regno; - if (**strp < '0' || **strp > '9') - return -1; /* error */ - regno = **strp - '0'; - ++*strp; - - if (**strp >= '0' && **strp <= '9') - { - regno = regno * 10 + (**strp - '0'); - ++*strp; - } - - return regno; -} - -static const char * -parse_register_list (od, strp, opindex, valuep, high_low, load_store) - CGEN_OPCODE_DESC od; - const char **strp; - int opindex; - unsigned long *valuep; - int high_low; /* 0 == high, 1 == low */ - int load_store; /* 0 == load, 1 == store */ -{ - int regno; - *valuep = 0; - while (**strp && **strp != ')') - { - if (**strp != 'R' && **strp != 'r') - break; - ++*strp; - - regno = parse_register_number (strp); - if (regno == -1) - return "Register number is not valid"; - if (regno > 7 && !high_low) - return "Register must be between r0 and r7"; - if (regno < 8 && high_low) - return "Register must be between r8 and r15"; - - if (high_low) - regno -= 8; - - if (load_store) /* mask is reversed for store */ - *valuep |= 0x80 >> regno; - else - *valuep |= 1 << regno; - - if (**strp == ',') - { - if (*(*strp + 1) == ')') - break; - ++*strp; - } - } - - if (!*strp || **strp != ')') - return "Register list is not valid"; - - return NULL; -} - -static const char * -parse_low_register_list_ld (od, strp, opindex, valuep) - CGEN_OPCODE_DESC od; - const char **strp; - int opindex; - unsigned long *valuep; -{ - return parse_register_list (od, strp, opindex, valuep, 0/*low*/, 0/*load*/); -} - -static const char * -parse_hi_register_list_ld (od, strp, opindex, valuep) - CGEN_OPCODE_DESC od; - const char **strp; - int opindex; - unsigned long *valuep; -{ - return parse_register_list (od, strp, opindex, valuep, 1/*high*/, 0/*load*/); -} - -static const char * -parse_low_register_list_st (od, strp, opindex, valuep) - CGEN_OPCODE_DESC od; - const char **strp; - int opindex; - unsigned long *valuep; -{ - return parse_register_list (od, strp, opindex, valuep, 0/*low*/, 1/*store*/); -} - -static const char * -parse_hi_register_list_st (od, strp, opindex, valuep) - CGEN_OPCODE_DESC od; - const char **strp; - int opindex; - unsigned long *valuep; -{ - return parse_register_list (od, strp, opindex, valuep, 1/*high*/, 1/*store*/); -} - -/* -- */ - -/* Main entry point for operand parsing. - - This function is basically just a big switch statement. Earlier versions - used tables to look up the function to use, but - - if the table contains both assembler and disassembler functions then - the disassembler contains much of the assembler and vice-versa, - - there's a lot of inlining possibilities as things grow, - - using a switch statement avoids the function call overhead. - - This function could be moved into `parse_insn_normal', but keeping it - separate makes clear the interface between `parse_insn_normal' and each of - the handlers. -*/ - -const char * -fr30_cgen_parse_operand (od, opindex, strp, fields) - CGEN_OPCODE_DESC od; - int opindex; - const char ** strp; - CGEN_FIELDS * fields; -{ - const char * errmsg; - - switch (opindex) - { - case FR30_OPERAND_RI : - errmsg = cgen_parse_keyword (od, strp, & fr30_cgen_opval_h_gr, & fields->f_Ri); - break; - case FR30_OPERAND_RJ : - errmsg = cgen_parse_keyword (od, strp, & fr30_cgen_opval_h_gr, & fields->f_Rj); - break; - case FR30_OPERAND_RIC : - errmsg = cgen_parse_keyword (od, strp, & fr30_cgen_opval_h_gr, & fields->f_Ric); - break; - case FR30_OPERAND_RJC : - errmsg = cgen_parse_keyword (od, strp, & fr30_cgen_opval_h_gr, & fields->f_Rjc); - break; - case FR30_OPERAND_CRI : - errmsg = cgen_parse_keyword (od, strp, & fr30_cgen_opval_h_cr, & fields->f_CRi); - break; - case FR30_OPERAND_CRJ : - errmsg = cgen_parse_keyword (od, strp, & fr30_cgen_opval_h_cr, & fields->f_CRj); - break; - case FR30_OPERAND_RS1 : - errmsg = cgen_parse_keyword (od, strp, & fr30_cgen_opval_h_dr, & fields->f_Rs1); - break; - case FR30_OPERAND_RS2 : - errmsg = cgen_parse_keyword (od, strp, & fr30_cgen_opval_h_dr, & fields->f_Rs2); - break; - case FR30_OPERAND_R13 : - errmsg = cgen_parse_keyword (od, strp, & fr30_cgen_opval_h_r13, & fields->f_nil); - break; - case FR30_OPERAND_R14 : - errmsg = cgen_parse_keyword (od, strp, & fr30_cgen_opval_h_r14, & fields->f_nil); - break; - case FR30_OPERAND_R15 : - errmsg = cgen_parse_keyword (od, strp, & fr30_cgen_opval_h_r15, & fields->f_nil); - break; - case FR30_OPERAND_PS : - errmsg = cgen_parse_keyword (od, strp, & fr30_cgen_opval_h_ps, & fields->f_nil); - break; - case FR30_OPERAND_U4 : - errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_U4, &fields->f_u4); - break; - case FR30_OPERAND_U4C : - errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_U4C, &fields->f_u4c); - break; - case FR30_OPERAND_U8 : - errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_U8, &fields->f_u8); - break; - case FR30_OPERAND_I8 : - errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_I8, &fields->f_i8); - break; - case FR30_OPERAND_UDISP6 : - errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_UDISP6, &fields->f_udisp6); - break; - case FR30_OPERAND_DISP8 : - errmsg = cgen_parse_signed_integer (od, strp, FR30_OPERAND_DISP8, &fields->f_disp8); - break; - case FR30_OPERAND_DISP9 : - errmsg = cgen_parse_signed_integer (od, strp, FR30_OPERAND_DISP9, &fields->f_disp9); - break; - case FR30_OPERAND_DISP10 : - errmsg = cgen_parse_signed_integer (od, strp, FR30_OPERAND_DISP10, &fields->f_disp10); - break; - case FR30_OPERAND_S10 : - errmsg = cgen_parse_signed_integer (od, strp, FR30_OPERAND_S10, &fields->f_s10); - break; - case FR30_OPERAND_U10 : - errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_U10, &fields->f_u10); - break; - case FR30_OPERAND_I32 : - errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_I32, &fields->f_i32); - break; - case FR30_OPERAND_M4 : - errmsg = cgen_parse_signed_integer (od, strp, FR30_OPERAND_M4, &fields->f_m4); - break; - case FR30_OPERAND_I20 : - errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_I20, &fields->f_i20); - break; - case FR30_OPERAND_DIR8 : - errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_DIR8, &fields->f_dir8); - break; - case FR30_OPERAND_DIR9 : - errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_DIR9, &fields->f_dir9); - break; - case FR30_OPERAND_DIR10 : - errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_DIR10, &fields->f_dir10); - break; - case FR30_OPERAND_LABEL9 : - { - bfd_vma value; - errmsg = cgen_parse_address (od, strp, FR30_OPERAND_LABEL9, 0, NULL, & value); - fields->f_rel9 = value; - } - break; - case FR30_OPERAND_LABEL12 : - { - bfd_vma value; - errmsg = cgen_parse_address (od, strp, FR30_OPERAND_LABEL12, 0, NULL, & value); - fields->f_rel12 = value; - } - break; - case FR30_OPERAND_REGLIST_LOW_LD : - errmsg = parse_low_register_list_ld (od, strp, FR30_OPERAND_REGLIST_LOW_LD, &fields->f_reglist_low_ld); - break; - case FR30_OPERAND_REGLIST_HI_LD : - errmsg = parse_hi_register_list_ld (od, strp, FR30_OPERAND_REGLIST_HI_LD, &fields->f_reglist_hi_ld); - break; - case FR30_OPERAND_REGLIST_LOW_ST : - errmsg = parse_low_register_list_st (od, strp, FR30_OPERAND_REGLIST_LOW_ST, &fields->f_reglist_low_st); - break; - case FR30_OPERAND_REGLIST_HI_ST : - errmsg = parse_hi_register_list_st (od, strp, FR30_OPERAND_REGLIST_HI_ST, &fields->f_reglist_hi_st); - break; - case FR30_OPERAND_CC : - errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_CC, &fields->f_cc); - break; - case FR30_OPERAND_CCC : - errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_CCC, &fields->f_ccc); - break; - - default : - /* xgettext:c-format */ - fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); - abort (); - } - - return errmsg; -} - -/* Main entry point for operand insertion. - - This function is basically just a big switch statement. Earlier versions - used tables to look up the function to use, but - - if the table contains both assembler and disassembler functions then - the disassembler contains much of the assembler and vice-versa, - - there's a lot of inlining possibilities as things grow, - - using a switch statement avoids the function call overhead. - - This function could be moved into `parse_insn_normal', but keeping it - separate makes clear the interface between `parse_insn_normal' and each of - the handlers. It's also needed by GAS to insert operands that couldn't be - resolved during parsing. -*/ - -const char * -fr30_cgen_insert_operand (od, opindex, fields, buffer, pc) - CGEN_OPCODE_DESC od; - int opindex; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc; -{ - const char * errmsg; - unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); - - switch (opindex) - { - case FR30_OPERAND_RI : - errmsg = insert_normal (od, fields->f_Ri, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 16, total_length, buffer); - break; - case FR30_OPERAND_RJ : - errmsg = insert_normal (od, fields->f_Rj, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 4, 16, total_length, buffer); - break; - case FR30_OPERAND_RIC : - errmsg = insert_normal (od, fields->f_Ric, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 12, 4, 16, total_length, buffer); - break; - case FR30_OPERAND_RJC : - errmsg = insert_normal (od, fields->f_Rjc, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 8, 4, 16, total_length, buffer); - break; - case FR30_OPERAND_CRI : - errmsg = insert_normal (od, fields->f_CRi, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 12, 4, 16, total_length, buffer); - break; - case FR30_OPERAND_CRJ : - errmsg = insert_normal (od, fields->f_CRj, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 8, 4, 16, total_length, buffer); - break; - case FR30_OPERAND_RS1 : - errmsg = insert_normal (od, fields->f_Rs1, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 4, 16, total_length, buffer); - break; - case FR30_OPERAND_RS2 : - errmsg = insert_normal (od, fields->f_Rs2, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 16, total_length, buffer); - break; - case FR30_OPERAND_R13 : - errmsg = insert_normal (od, fields->f_nil, 0, 0, 0, 0, 0, total_length, buffer); - break; - case FR30_OPERAND_R14 : - errmsg = insert_normal (od, fields->f_nil, 0, 0, 0, 0, 0, total_length, buffer); - break; - case FR30_OPERAND_R15 : - errmsg = insert_normal (od, fields->f_nil, 0, 0, 0, 0, 0, total_length, buffer); - break; - case FR30_OPERAND_PS : - errmsg = insert_normal (od, fields->f_nil, 0, 0, 0, 0, 0, total_length, buffer); - break; - case FR30_OPERAND_U4 : - errmsg = insert_normal (od, fields->f_u4, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 4, 16, total_length, buffer); - break; - case FR30_OPERAND_U4C : - errmsg = insert_normal (od, fields->f_u4c, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 16, total_length, buffer); - break; - case FR30_OPERAND_U8 : - errmsg = insert_normal (od, fields->f_u8, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, buffer); - break; - case FR30_OPERAND_I8 : - errmsg = insert_normal (od, fields->f_i8, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 8, 16, total_length, buffer); - break; - case FR30_OPERAND_UDISP6 : - { - long value = fields->f_udisp6; - value = ((unsigned int) (value) >> (2)); - errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 4, 16, total_length, buffer); - } - break; - case FR30_OPERAND_DISP8 : - errmsg = insert_normal (od, fields->f_disp8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 4, 8, 16, total_length, buffer); - break; - case FR30_OPERAND_DISP9 : - { - long value = fields->f_disp9; - value = ((int) (value) >> (1)); - errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 4, 8, 16, total_length, buffer); - } - break; - case FR30_OPERAND_DISP10 : - { - long value = fields->f_disp10; - value = ((int) (value) >> (2)); - errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 4, 8, 16, total_length, buffer); - } - break; - case FR30_OPERAND_S10 : - { - long value = fields->f_s10; - value = ((int) (value) >> (2)); - errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 8, 8, 16, total_length, buffer); - } - break; - case FR30_OPERAND_U10 : - { - long value = fields->f_u10; - value = ((unsigned int) (value) >> (2)); - errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, buffer); - } - break; - case FR30_OPERAND_I32 : - errmsg = insert_normal (od, fields->f_i32, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 0, 32, 32, total_length, buffer); - break; - case FR30_OPERAND_M4 : - { - long value = fields->f_m4; - value = ((value) & (15)); - errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 4, 16, total_length, buffer); - } - break; - case FR30_OPERAND_I20 : - { -do { - FLD (f_i20_4) = ((unsigned int) (FLD (f_i20)) >> (16)); - FLD (f_i20_16) = ((FLD (f_i20)) & (65535)); -} while (0); - errmsg = insert_normal (od, fields->f_i20_4, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED)|(1<<CGEN_OPERAND_VIRTUAL), 0, 8, 4, 16, total_length, buffer); - if (errmsg) - break; - errmsg = insert_normal (od, fields->f_i20_16, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED)|(1<<CGEN_OPERAND_VIRTUAL), 16, 0, 16, 16, total_length, buffer); - if (errmsg) - break; - } - break; - case FR30_OPERAND_DIR8 : - errmsg = insert_normal (od, fields->f_dir8, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, buffer); - break; - case FR30_OPERAND_DIR9 : - { - long value = fields->f_dir9; - value = ((unsigned int) (value) >> (1)); - errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, buffer); - } - break; - case FR30_OPERAND_DIR10 : - { - long value = fields->f_dir10; - value = ((unsigned int) (value) >> (2)); - errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, buffer); - } - break; - case FR30_OPERAND_LABEL9 : - { - long value = fields->f_rel9; - value = ((int) (((value) - (((pc) + (2))))) >> (1)); - errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 8, 8, 16, total_length, buffer); - } - break; - case FR30_OPERAND_LABEL12 : - { - long value = fields->f_rel12; - value = ((int) (((value) - (((pc) + (2))))) >> (1)); - errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 5, 11, 16, total_length, buffer); - } - break; - case FR30_OPERAND_REGLIST_LOW_LD : - errmsg = insert_normal (od, fields->f_reglist_low_ld, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, buffer); - break; - case FR30_OPERAND_REGLIST_HI_LD : - errmsg = insert_normal (od, fields->f_reglist_hi_ld, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, buffer); - break; - case FR30_OPERAND_REGLIST_LOW_ST : - errmsg = insert_normal (od, fields->f_reglist_low_st, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, buffer); - break; - case FR30_OPERAND_REGLIST_HI_ST : - errmsg = insert_normal (od, fields->f_reglist_hi_st, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, buffer); - break; - case FR30_OPERAND_CC : - errmsg = insert_normal (od, fields->f_cc, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 4, 16, total_length, buffer); - break; - case FR30_OPERAND_CCC : - errmsg = insert_normal (od, fields->f_ccc, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 16, 0, 8, 16, total_length, buffer); - break; - - default : - /* xgettext:c-format */ - fprintf (stderr, _("Unrecognized field %d while building insn.\n"), - opindex); - abort (); - } - - return errmsg; -} - -cgen_parse_fn * const fr30_cgen_parse_handlers[] = -{ - 0, /* default */ - parse_insn_normal, -}; - -cgen_insert_fn * const fr30_cgen_insert_handlers[] = -{ - 0, /* default */ - insert_insn_normal, -}; - -void -fr30_cgen_init_asm (od) - CGEN_OPCODE_DESC od; -{ -} - - -#if ! CGEN_INT_INSN_P - -/* Subroutine of insert_normal. */ - -static INLINE void -insert_1 (od, value, start, length, word_length, bufp) - CGEN_OPCODE_DESC od; - unsigned long value; - int start,length,word_length; - unsigned char *bufp; -{ - unsigned long x,mask; - int shift; - int big_p = CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG; - - switch (word_length) - { - case 8: - x = *bufp; - break; - case 16: - if (big_p) - x = bfd_getb16 (bufp); - else - x = bfd_getl16 (bufp); - break; - case 24: - /* ??? This may need reworking as these cases don't necessarily - want the first byte and the last two bytes handled like this. */ - if (big_p) - x = (bufp[0] << 16) | bfd_getb16 (bufp + 1); - else - x = bfd_getl16 (bufp) | (bufp[2] << 16); - break; - case 32: - if (big_p) - x = bfd_getb32 (bufp); - else - x = bfd_getl32 (bufp); - break; - default : - abort (); - } - - /* Written this way to avoid undefined behaviour. */ - mask = (((1L << (length - 1)) - 1) << 1) | 1; - if (CGEN_INSN_LSB0_P) - shift = (start + 1) - length; - else - shift = (word_length - (start + length)); - x = (x & ~(mask << shift)) | ((value & mask) << shift); - - switch (word_length) - { - case 8: - *bufp = x; - break; - case 16: - if (big_p) - bfd_putb16 (x, bufp); - else - bfd_putl16 (x, bufp); - break; - case 24: - /* ??? This may need reworking as these cases don't necessarily - want the first byte and the last two bytes handled like this. */ - if (big_p) - { - bufp[0] = x >> 16; - bfd_putb16 (x, bufp + 1); - } - else - { - bfd_putl16 (x, bufp); - bufp[2] = x >> 16; - } - break; - case 32: - if (big_p) - bfd_putb32 (x, bufp); - else - bfd_putl32 (x, bufp); - break; - default : - abort (); - } -} - -#endif /* ! CGEN_INT_INSN_P */ - -/* Default insertion routine. - - ATTRS is a mask of the boolean attributes. - WORD_OFFSET is the offset in bits from the start of the insn of the value. - WORD_LENGTH is the length of the word in bits in which the value resides. - START is the starting bit number in the word, architecture origin. - LENGTH is the length of VALUE in bits. - TOTAL_LENGTH is the total length of the insn in bits. - - The result is an error message or NULL if success. */ - -/* ??? This duplicates functionality with bfd's howto table and - bfd_install_relocation. */ -/* ??? This doesn't handle bfd_vma's. Create another function when - necessary. */ - -static const char * -insert_normal (od, value, attrs, word_offset, start, length, word_length, - total_length, buffer) - CGEN_OPCODE_DESC od; - long value; - unsigned int attrs; - unsigned int word_offset, start, length, word_length, total_length; - CGEN_INSN_BYTES_PTR buffer; -{ - static char errbuf[100]; - /* Written this way to avoid undefined behaviour. */ - unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; - - /* If LENGTH is zero, this operand doesn't contribute to the value. */ - if (length == 0) - return NULL; - - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); - - if (word_length > 32) - abort (); - - /* For architectures with insns smaller than the insn-base-bitsize, - word_length may be too big. */ -#if CGEN_MIN_INSN_BITSIZE < CGEN_BASE_INSN_BITSIZE - if (word_offset == 0 - && word_length > total_length) - word_length = total_length; -#endif - - /* Ensure VALUE will fit. */ - if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED)) - { - unsigned long maxval = mask; - if ((unsigned long) value > maxval) - { - /* xgettext:c-format */ - sprintf (errbuf, - _("operand out of range (%lu not between 0 and %lu)"), - value, maxval); - return errbuf; - } - } - else - { - long minval = - (1L << (length - 1)); - long maxval = (1L << (length - 1)) - 1; - if (value < minval || value > maxval) - { - sprintf - /* xgettext:c-format */ - (errbuf, _("operand out of range (%ld not between %ld and %ld)"), - value, minval, maxval); - return errbuf; - } - } - -#if CGEN_INT_INSN_P - - { - int shift; - - if (CGEN_INSN_LSB0_P) - shift = (start + 1) - length; - else - shift = word_length - (start + length); - *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); - } - -#else /* ! CGEN_INT_INSN_P */ - - { - unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; - - insert_1 (od, value, start, length, word_length, bufp); - } - -#endif /* ! CGEN_INT_INSN_P */ - - return NULL; -} - -/* Default insn parser. - - The syntax string is scanned and operands are parsed and stored in FIELDS. - Relocs are queued as we go via other callbacks. - - ??? Note that this is currently an all-or-nothing parser. If we fail to - parse the instruction, we return 0 and the caller will start over from - the beginning. Backtracking will be necessary in parsing subexpressions, - but that can be handled there. Not handling backtracking here may get - expensive in the case of the m68k. Deal with later. - - Returns NULL for success, an error message for failure. -*/ - -static const char * -parse_insn_normal (od, insn, strp, fields) - CGEN_OPCODE_DESC od; - const CGEN_INSN * insn; - const char ** strp; - CGEN_FIELDS * fields; -{ - const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn); - const char * str = *strp; - const char * errmsg; - const char * p; - const unsigned char * syn; -#ifdef CGEN_MNEMONIC_OPERANDS - /* FIXME: wip */ - int past_opcode_p; -#endif - - /* For now we assume the mnemonic is first (there are no leading operands). - We can parse it without needing to set up operand parsing. - GAS's input scrubber will ensure mnemonics are lowercase, but we may - not be called from GAS. */ - p = CGEN_INSN_MNEMONIC (insn); - while (*p && tolower (*p) == tolower (*str)) - ++p, ++str; - - if (* p || (* str && !isspace (* str))) - return _("unrecognized instruction"); - - CGEN_INIT_PARSE (od); - cgen_init_parse_operand (od); -#ifdef CGEN_MNEMONIC_OPERANDS - past_opcode_p = 0; -#endif - - /* We don't check for (*str != '\0') here because we want to parse - any trailing fake arguments in the syntax string. */ - syn = CGEN_SYNTAX_STRING (syntax); - - /* Mnemonics come first for now, ensure valid string. */ - if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) - abort (); - - ++syn; - - while (* syn != 0) - { - /* Non operand chars must match exactly. */ - if (CGEN_SYNTAX_CHAR_P (* syn)) - { - if (*str == CGEN_SYNTAX_CHAR (* syn)) - { -#ifdef CGEN_MNEMONIC_OPERANDS - if (* syn == ' ') - past_opcode_p = 1; -#endif - ++ syn; - ++ str; - } - else - { - /* Syntax char didn't match. Can't be this insn. */ - /* FIXME: would like to return something like - "expected char `c'" */ - return _("syntax error"); - } - continue; - } - - /* We have an operand of some sort. */ - errmsg = fr30_cgen_parse_operand (od, CGEN_SYNTAX_FIELD (*syn), - &str, fields); - if (errmsg) - return errmsg; - - /* Done with this operand, continue with next one. */ - ++ syn; - } - - /* If we're at the end of the syntax string, we're done. */ - if (* syn == '\0') - { - /* FIXME: For the moment we assume a valid `str' can only contain - blanks now. IE: We needn't try again with a longer version of - the insn and it is assumed that longer versions of insns appear - before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ - while (isspace (* str)) - ++ str; - - if (* str != '\0') - return _("junk at end of line"); /* FIXME: would like to include `str' */ - - return NULL; - } - - /* We couldn't parse it. */ - return _("unrecognized instruction"); -} - -/* Default insn builder (insert handler). - The instruction is recorded in CGEN_INT_INSN_P byte order - (meaning that if CGEN_INT_INSN_P BUFFER is an int * and thus the value is - recorded in host byte order, otherwise BUFFER is an array of bytes and the - value is recorded in target byte order). - The result is an error message or NULL if success. */ - -static const char * -insert_insn_normal (od, insn, fields, buffer, pc) - CGEN_OPCODE_DESC od; - const CGEN_INSN * insn; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc; -{ - const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn); - unsigned long value; - const unsigned char * syn; - - CGEN_INIT_INSERT (od); - value = CGEN_INSN_BASE_VALUE (insn); - - /* If we're recording insns as numbers (rather than a string of bytes), - target byte order handling is deferred until later. */ - -#if CGEN_INT_INSN_P - - *buffer = value; - -#else - - cgen_put_insn_value (od, buffer, min (CGEN_BASE_INSN_BITSIZE, - CGEN_FIELDS_BITSIZE (fields)), - value); - -#endif /* ! CGEN_INT_INSN_P */ - - /* ??? It would be better to scan the format's fields. - Still need to be able to insert a value based on the operand though; - e.g. storing a branch displacement that got resolved later. - Needs more thought first. */ - - for (syn = CGEN_SYNTAX_STRING (syntax); * syn != '\0'; ++ syn) - { - const char *errmsg; - - if (CGEN_SYNTAX_CHAR_P (* syn)) - continue; - - errmsg = fr30_cgen_insert_operand (od, CGEN_SYNTAX_FIELD (*syn), - fields, buffer, pc); - if (errmsg) - return errmsg; - } - - return NULL; -} - -/* Main entry point. - This routine is called for each instruction to be assembled. - STR points to the insn to be assembled. - We assume all necessary tables have been initialized. - The assembled instruction, less any fixups, is stored in BUF. - Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value - still needs to be converted to target byte order, otherwise BUF is an array - of bytes in target byte order. - The result is a pointer to the insn's entry in the opcode table, - or NULL if an error occured (an error message will have already been - printed). - - Note that when processing (non-alias) macro-insns, - this function recurses. */ - -const CGEN_INSN * -fr30_cgen_assemble_insn (od, str, fields, buf, errmsg) - CGEN_OPCODE_DESC od; - const char * str; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buf; - char ** errmsg; -{ - const char * start; - CGEN_INSN_LIST * ilist; - - /* Skip leading white space. */ - while (isspace (* str)) - ++ str; - - /* The instructions are stored in hashed lists. - Get the first in the list. */ - ilist = CGEN_ASM_LOOKUP_INSN (od, str); - - /* Keep looking until we find a match. */ - - start = str; - for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) - { - const CGEN_INSN *insn = ilist->insn; - -#if 0 /* not needed as unsupported opcodes shouldn't be in the hash lists */ - /* Is this insn supported by the selected cpu? */ - if (! fr30_cgen_insn_supported (od, insn)) - continue; -#endif - - /* If the RELAX attribute is set, this is an insn that shouldn't be - chosen immediately. Instead, it is used during assembler/linker - relaxation if possible. */ - if (CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX) != 0) - continue; - - str = start; - - /* Allow parse/insert handlers to obtain length of insn. */ - CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); - - if (! CGEN_PARSE_FN (insn) (od, insn, & str, fields)) - { - /* ??? 0 is passed for `pc' */ - if (CGEN_INSERT_FN (insn) (od, insn, fields, buf, (bfd_vma) 0) != NULL) - continue; - /* It is up to the caller to actually output the insn and any - queued relocs. */ - return insn; - } - - /* Try the next entry. */ - } - - /* FIXME: We can return a better error message than this. - Need to track why it failed and pick the right one. */ - { - static char errbuf[100]; - if (strlen (start) > 50) - /* xgettext:c-format */ - sprintf (errbuf, _("bad instruction `%.50s...'"), start); - else - /* xgettext:c-format */ - sprintf (errbuf, _("bad instruction `%.50s'"), start); - - *errmsg = errbuf; - return NULL; - } -} - -#if 0 /* This calls back to GAS which we can't do without care. */ - -/* Record each member of OPVALS in the assembler's symbol table. - This lets GAS parse registers for us. - ??? Interesting idea but not currently used. */ - -/* Record each member of OPVALS in the assembler's symbol table. - FIXME: Not currently used. */ - -void -fr30_cgen_asm_hash_keywords (od, opvals) - CGEN_OPCODE_DESC od; - CGEN_KEYWORD * opvals; -{ - CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); - const CGEN_KEYWORD_ENTRY * ke; - - while ((ke = cgen_keyword_search_next (& search)) != NULL) - { -#if 0 /* Unnecessary, should be done in the search routine. */ - if (! fr30_cgen_opval_supported (ke)) - continue; -#endif - cgen_asm_record_register (od, ke->name, ke->value); - } -} - -#endif /* 0 */ diff --git a/opcodes/fr30-dis.c b/opcodes/fr30-dis.c deleted file mode 100644 index f171395cbea..00000000000 --- a/opcodes/fr30-dis.c +++ /dev/null @@ -1,1049 +0,0 @@ -/* Disassembler interface for targets using CGEN. -*- C -*- - CGEN: Cpu tools GENerator - -THIS FILE IS USED TO GENERATE fr30-dis.c. - -Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. - -This file is part of the GNU Binutils and GDB, the GNU debugger. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include <stdio.h> -#include "ansidecl.h" -#include "dis-asm.h" -#include "bfd.h" -#include "symcat.h" -#include "fr30-opc.h" -#include "opintl.h" - -#undef INLINE -#ifdef __GNUC__ -#define INLINE __inline__ -#else -#define INLINE -#endif - -/* Default text to print if an instruction isn't recognized. */ -#define UNKNOWN_INSN_MSG _("*unknown*") - -/* Used by the ifield rtx function. */ -#define FLD(f) (fields->f) - -static int extract_normal - PARAMS ((CGEN_OPCODE_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - unsigned int, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, bfd_vma, long *)); -static void print_normal - PARAMS ((CGEN_OPCODE_DESC, PTR, long, unsigned int, bfd_vma, int)); -static void print_address - PARAMS ((CGEN_OPCODE_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); -static void print_keyword - PARAMS ((CGEN_OPCODE_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); -static int extract_insn_normal - PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, - CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); -static void print_insn_normal - PARAMS ((CGEN_OPCODE_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, - bfd_vma, int)); -static int print_insn PARAMS ((CGEN_OPCODE_DESC, bfd_vma, - disassemble_info *, char *, int)); -static int default_print_insn - PARAMS ((CGEN_OPCODE_DESC, bfd_vma, disassemble_info *)); - -/* -- disassembler routines inserted here */ -/* -- dis.c */ - -static void -print_register_list (dis_info, value, offset, load_store) - PTR dis_info; - long value; - long offset; - int load_store; /* 0 == load, 1 == store */ -{ - disassemble_info *info = dis_info; - int mask; - int index = 0; - char* comma = ""; - - if (load_store) - mask = 0x80; - else - mask = 1; - - if (value & mask) - { - (*info->fprintf_func) (info->stream, "r%i", index + offset); - comma = ","; - } - - for (index = 1; index <= 7; ++index) - { - if (load_store) - mask >>= 1; - else - mask <<= 1; - - if (value & mask) - { - (*info->fprintf_func) (info->stream, "%sr%i", comma, index + offset); - comma = ","; - } - } -} - -static void -print_hi_register_list_ld (od, dis_info, value, attrs, pc, length) - CGEN_OPCODE_DESC od; - PTR dis_info; - long value; - unsigned int attrs; - bfd_vma pc; - int length; -{ - print_register_list (dis_info, value, 8, 0/*load*/); -} - -static void -print_low_register_list_ld (od, dis_info, value, attrs, pc, length) - CGEN_OPCODE_DESC od; - PTR dis_info; - long value; - unsigned int attrs; - bfd_vma pc; - int length; -{ - print_register_list (dis_info, value, 0, 0/*load*/); -} - -static void -print_hi_register_list_st (od, dis_info, value, attrs, pc, length) - CGEN_OPCODE_DESC od; - PTR dis_info; - long value; - unsigned int attrs; - bfd_vma pc; - int length; -{ - print_register_list (dis_info, value, 8, 1/*store*/); -} - -static void -print_low_register_list_st (od, dis_info, value, attrs, pc, length) - CGEN_OPCODE_DESC od; - PTR dis_info; - long value; - unsigned int attrs; - bfd_vma pc; - int length; -{ - print_register_list (dis_info, value, 0, 1/*store*/); -} - -static void -print_m4 (od, dis_info, value, attrs, pc, length) - CGEN_OPCODE_DESC od; - PTR dis_info; - long value; - unsigned int attrs; - bfd_vma pc; - int length; -{ - disassemble_info *info = (disassemble_info *) dis_info; - (*info->fprintf_func) (info->stream, "%ld", value); -} -/* -- */ - -/* Main entry point for operand extraction. - - This function is basically just a big switch statement. Earlier versions - used tables to look up the function to use, but - - if the table contains both assembler and disassembler functions then - the disassembler contains much of the assembler and vice-versa, - - there's a lot of inlining possibilities as things grow, - - using a switch statement avoids the function call overhead. - - This function could be moved into `print_insn_normal', but keeping it - separate makes clear the interface between `print_insn_normal' and each of - the handlers. -*/ - -int -fr30_cgen_extract_operand (od, opindex, ex_info, insn_value, fields, pc) - CGEN_OPCODE_DESC od; - int opindex; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - CGEN_FIELDS * fields; - bfd_vma pc; -{ - int length; - unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); - - switch (opindex) - { - case FR30_OPERAND_RI : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 16, total_length, pc, & fields->f_Ri); - break; - case FR30_OPERAND_RJ : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 4, 16, total_length, pc, & fields->f_Rj); - break; - case FR30_OPERAND_RIC : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 12, 4, 16, total_length, pc, & fields->f_Ric); - break; - case FR30_OPERAND_RJC : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 8, 4, 16, total_length, pc, & fields->f_Rjc); - break; - case FR30_OPERAND_CRI : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 12, 4, 16, total_length, pc, & fields->f_CRi); - break; - case FR30_OPERAND_CRJ : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 8, 4, 16, total_length, pc, & fields->f_CRj); - break; - case FR30_OPERAND_RS1 : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 4, 16, total_length, pc, & fields->f_Rs1); - break; - case FR30_OPERAND_RS2 : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 16, total_length, pc, & fields->f_Rs2); - break; - case FR30_OPERAND_R13 : - length = extract_normal (od, ex_info, insn_value, 0, 0, 0, 0, 0, total_length, pc, & fields->f_nil); - break; - case FR30_OPERAND_R14 : - length = extract_normal (od, ex_info, insn_value, 0, 0, 0, 0, 0, total_length, pc, & fields->f_nil); - break; - case FR30_OPERAND_R15 : - length = extract_normal (od, ex_info, insn_value, 0, 0, 0, 0, 0, total_length, pc, & fields->f_nil); - break; - case FR30_OPERAND_PS : - length = extract_normal (od, ex_info, insn_value, 0, 0, 0, 0, 0, total_length, pc, & fields->f_nil); - break; - case FR30_OPERAND_U4 : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 4, 16, total_length, pc, & fields->f_u4); - break; - case FR30_OPERAND_U4C : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 16, total_length, pc, & fields->f_u4c); - break; - case FR30_OPERAND_U8 : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, pc, & fields->f_u8); - break; - case FR30_OPERAND_I8 : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 8, 16, total_length, pc, & fields->f_i8); - break; - case FR30_OPERAND_UDISP6 : - { - long value; - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 4, 16, total_length, pc, & value); - value = ((value) << (2)); - fields->f_udisp6 = value; - } - break; - case FR30_OPERAND_DISP8 : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 4, 8, 16, total_length, pc, & fields->f_disp8); - break; - case FR30_OPERAND_DISP9 : - { - long value; - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 4, 8, 16, total_length, pc, & value); - value = ((value) << (1)); - fields->f_disp9 = value; - } - break; - case FR30_OPERAND_DISP10 : - { - long value; - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 4, 8, 16, total_length, pc, & value); - value = ((value) << (2)); - fields->f_disp10 = value; - } - break; - case FR30_OPERAND_S10 : - { - long value; - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 8, 8, 16, total_length, pc, & value); - value = ((value) << (2)); - fields->f_s10 = value; - } - break; - case FR30_OPERAND_U10 : - { - long value; - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, pc, & value); - value = ((value) << (2)); - fields->f_u10 = value; - } - break; - case FR30_OPERAND_I32 : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 0, 32, 32, total_length, pc, & fields->f_i32); - break; - case FR30_OPERAND_M4 : - { - long value; - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 4, 16, total_length, pc, & value); - value = ((value) | (((-1) << (4)))); - fields->f_m4 = value; - } - break; - case FR30_OPERAND_I20 : - { - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED)|(1<<CGEN_OPERAND_VIRTUAL), 0, 8, 4, 16, total_length, pc, & fields->f_i20_4); - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED)|(1<<CGEN_OPERAND_VIRTUAL), 16, 0, 16, 16, total_length, pc, & fields->f_i20_16); -do { - FLD (f_i20) = ((((FLD (f_i20_4)) << (16))) | (FLD (f_i20_16))); -} while (0); - } - break; - case FR30_OPERAND_DIR8 : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, pc, & fields->f_dir8); - break; - case FR30_OPERAND_DIR9 : - { - long value; - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, pc, & value); - value = ((value) << (1)); - fields->f_dir9 = value; - } - break; - case FR30_OPERAND_DIR10 : - { - long value; - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, pc, & value); - value = ((value) << (2)); - fields->f_dir10 = value; - } - break; - case FR30_OPERAND_LABEL9 : - { - long value; - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 8, 8, 16, total_length, pc, & value); - value = ((((value) << (1))) + (((pc) + (2)))); - fields->f_rel9 = value; - } - break; - case FR30_OPERAND_LABEL12 : - { - long value; - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 5, 11, 16, total_length, pc, & value); - value = ((((value) << (1))) + (((pc) + (2)))); - fields->f_rel12 = value; - } - break; - case FR30_OPERAND_REGLIST_LOW_LD : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, pc, & fields->f_reglist_low_ld); - break; - case FR30_OPERAND_REGLIST_HI_LD : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, pc, & fields->f_reglist_hi_ld); - break; - case FR30_OPERAND_REGLIST_LOW_ST : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, pc, & fields->f_reglist_low_st); - break; - case FR30_OPERAND_REGLIST_HI_ST : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, pc, & fields->f_reglist_hi_st); - break; - case FR30_OPERAND_CC : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 4, 16, total_length, pc, & fields->f_cc); - break; - case FR30_OPERAND_CCC : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 16, 0, 8, 16, total_length, pc, & fields->f_ccc); - break; - - default : - /* xgettext:c-format */ - fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), - opindex); - abort (); - } - - return length; -} - -/* Main entry point for printing operands. - - This function is basically just a big switch statement. Earlier versions - used tables to look up the function to use, but - - if the table contains both assembler and disassembler functions then - the disassembler contains much of the assembler and vice-versa, - - there's a lot of inlining possibilities as things grow, - - using a switch statement avoids the function call overhead. - - This function could be moved into `print_insn_normal', but keeping it - separate makes clear the interface between `print_insn_normal' and each of - the handlers. -*/ - -void -fr30_cgen_print_operand (od, opindex, info, fields, attrs, pc, length) - CGEN_OPCODE_DESC od; - int opindex; - disassemble_info * info; - CGEN_FIELDS * fields; - void const * attrs; - bfd_vma pc; - int length; -{ - switch (opindex) - { - case FR30_OPERAND_RI : - print_keyword (od, info, & fr30_cgen_opval_h_gr, fields->f_Ri, 0|(1<<CGEN_OPERAND_UNSIGNED)); - break; - case FR30_OPERAND_RJ : - print_keyword (od, info, & fr30_cgen_opval_h_gr, fields->f_Rj, 0|(1<<CGEN_OPERAND_UNSIGNED)); - break; - case FR30_OPERAND_RIC : - print_keyword (od, info, & fr30_cgen_opval_h_gr, fields->f_Ric, 0|(1<<CGEN_OPERAND_UNSIGNED)); - break; - case FR30_OPERAND_RJC : - print_keyword (od, info, & fr30_cgen_opval_h_gr, fields->f_Rjc, 0|(1<<CGEN_OPERAND_UNSIGNED)); - break; - case FR30_OPERAND_CRI : - print_keyword (od, info, & fr30_cgen_opval_h_cr, fields->f_CRi, 0|(1<<CGEN_OPERAND_UNSIGNED)); - break; - case FR30_OPERAND_CRJ : - print_keyword (od, info, & fr30_cgen_opval_h_cr, fields->f_CRj, 0|(1<<CGEN_OPERAND_UNSIGNED)); - break; - case FR30_OPERAND_RS1 : - print_keyword (od, info, & fr30_cgen_opval_h_dr, fields->f_Rs1, 0|(1<<CGEN_OPERAND_UNSIGNED)); - break; - case FR30_OPERAND_RS2 : - print_keyword (od, info, & fr30_cgen_opval_h_dr, fields->f_Rs2, 0|(1<<CGEN_OPERAND_UNSIGNED)); - break; - case FR30_OPERAND_R13 : - print_keyword (od, info, & fr30_cgen_opval_h_r13, fields->f_nil, 0); - break; - case FR30_OPERAND_R14 : - print_keyword (od, info, & fr30_cgen_opval_h_r14, fields->f_nil, 0); - break; - case FR30_OPERAND_R15 : - print_keyword (od, info, & fr30_cgen_opval_h_r15, fields->f_nil, 0); - break; - case FR30_OPERAND_PS : - print_keyword (od, info, & fr30_cgen_opval_h_ps, fields->f_nil, 0); - break; - case FR30_OPERAND_U4 : - print_normal (od, info, fields->f_u4, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length); - break; - case FR30_OPERAND_U4C : - print_normal (od, info, fields->f_u4c, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length); - break; - case FR30_OPERAND_U8 : - print_normal (od, info, fields->f_u8, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length); - break; - case FR30_OPERAND_I8 : - print_normal (od, info, fields->f_i8, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length); - break; - case FR30_OPERAND_UDISP6 : - print_normal (od, info, fields->f_udisp6, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length); - break; - case FR30_OPERAND_DISP8 : - print_normal (od, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); - break; - case FR30_OPERAND_DISP9 : - print_normal (od, info, fields->f_disp9, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); - break; - case FR30_OPERAND_DISP10 : - print_normal (od, info, fields->f_disp10, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); - break; - case FR30_OPERAND_S10 : - print_normal (od, info, fields->f_s10, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); - break; - case FR30_OPERAND_U10 : - print_normal (od, info, fields->f_u10, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length); - break; - case FR30_OPERAND_I32 : - print_normal (od, info, fields->f_i32, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), pc, length); - break; - case FR30_OPERAND_M4 : - print_m4 (od, info, fields->f_m4, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length); - break; - case FR30_OPERAND_I20 : - print_normal (od, info, fields->f_i20, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); - break; - case FR30_OPERAND_DIR8 : - print_normal (od, info, fields->f_dir8, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length); - break; - case FR30_OPERAND_DIR9 : - print_normal (od, info, fields->f_dir9, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length); - break; - case FR30_OPERAND_DIR10 : - print_normal (od, info, fields->f_dir10, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length); - break; - case FR30_OPERAND_LABEL9 : - print_address (od, info, fields->f_rel9, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); - break; - case FR30_OPERAND_LABEL12 : - print_address (od, info, fields->f_rel12, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); - break; - case FR30_OPERAND_REGLIST_LOW_LD : - print_low_register_list_ld (od, info, fields->f_reglist_low_ld, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length); - break; - case FR30_OPERAND_REGLIST_HI_LD : - print_hi_register_list_ld (od, info, fields->f_reglist_hi_ld, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length); - break; - case FR30_OPERAND_REGLIST_LOW_ST : - print_low_register_list_st (od, info, fields->f_reglist_low_st, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length); - break; - case FR30_OPERAND_REGLIST_HI_ST : - print_hi_register_list_st (od, info, fields->f_reglist_hi_st, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length); - break; - case FR30_OPERAND_CC : - print_normal (od, info, fields->f_cc, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length); - break; - case FR30_OPERAND_CCC : - print_normal (od, info, fields->f_ccc, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length); - break; - - default : - /* xgettext:c-format */ - fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), - opindex); - abort (); - } -} - -cgen_extract_fn * const fr30_cgen_extract_handlers[] = -{ - 0, /* default */ - extract_insn_normal, -}; - -cgen_print_fn * const fr30_cgen_print_handlers[] = -{ - 0, /* default */ - print_insn_normal, -}; - - -void -fr30_cgen_init_dis (od) - CGEN_OPCODE_DESC od; -{ -} - - -#if ! CGEN_INT_INSN_P - -/* Subroutine of extract_normal. - Ensure sufficient bytes are cached in EX_INFO. - OFFSET is the offset in bytes from the start of the insn of the value. - BYTES is the length of the needed value. - Returns 1 for success, 0 for failure. */ - -static INLINE int -fill_cache (od, ex_info, offset, bytes, pc) - CGEN_OPCODE_DESC od; - CGEN_EXTRACT_INFO *ex_info; - int offset, bytes; - bfd_vma pc; -{ - /* It's doubtful that the middle part has already been fetched so - we don't optimize that case. kiss. */ - int mask; - disassemble_info *info = (disassemble_info *) ex_info->dis_info; - - /* First do a quick check. */ - mask = (1 << bytes) - 1; - if (((ex_info->valid >> offset) & mask) == mask) - return 1; - - /* Search for the first byte we need to read. */ - for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) - if (! (mask & ex_info->valid)) - break; - - if (bytes) - { - int status; - - pc += offset; - status = (*info->read_memory_func) - (pc, ex_info->insn_bytes + offset, bytes, info); - - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return 0; - } - - ex_info->valid |= ((1 << bytes) - 1) << offset; - } - - return 1; -} - -/* Subroutine of extract_normal. */ - -static INLINE long -extract_1 (od, ex_info, start, length, word_length, bufp, pc) - CGEN_OPCODE_DESC od; - CGEN_EXTRACT_INFO *ex_info; - int start,length,word_length; - unsigned char *bufp; - bfd_vma pc; -{ - unsigned long x,mask; - int shift; - int big_p = CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG; - - switch (word_length) - { - case 8: - x = *bufp; - break; - case 16: - if (big_p) - x = bfd_getb16 (bufp); - else - x = bfd_getl16 (bufp); - break; - case 24: - /* ??? This may need reworking as these cases don't necessarily - want the first byte and the last two bytes handled like this. */ - if (big_p) - x = (bufp[0] << 16) | bfd_getb16 (bufp + 1); - else - x = bfd_getl16 (bufp) | (bufp[2] << 16); - break; - case 32: - if (big_p) - x = bfd_getb32 (bufp); - else - x = bfd_getl32 (bufp); - break; - default : - abort (); - } - - /* Written this way to avoid undefined behaviour. */ - mask = (((1L << (length - 1)) - 1) << 1) | 1; - if (CGEN_INSN_LSB0_P) - shift = (start + 1) - length; - else - shift = (word_length - (start + length)); - return (x >> shift) & mask; -} - -#endif /* ! CGEN_INT_INSN_P */ - -/* Default extraction routine. - - INSN_VALUE is the first CGEN_BASE_INSN_SIZE bits of the insn in host order, - or sometimes less for cases like the m32r where the base insn size is 32 - but some insns are 16 bits. - ATTRS is a mask of the boolean attributes. We only need `UNSIGNED', - but for generality we take a bitmask of all of them. - WORD_OFFSET is the offset in bits from the start of the insn of the value. - WORD_LENGTH is the length of the word in bits in which the value resides. - START is the starting bit number in the word, architecture origin. - LENGTH is the length of VALUE in bits. - TOTAL_LENGTH is the total length of the insn in bits. - - Returns 1 for success, 0 for failure. */ - -/* ??? The return code isn't properly used. wip. */ - -/* ??? This doesn't handle bfd_vma's. Create another function when - necessary. */ - -static int -extract_normal (od, ex_info, insn_value, attrs, word_offset, start, length, - word_length, total_length, pc, valuep) - CGEN_OPCODE_DESC od; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - unsigned int attrs; - unsigned int word_offset, start, length, word_length, total_length; - bfd_vma pc; - long *valuep; -{ - CGEN_INSN_INT value; - - /* If LENGTH is zero, this operand doesn't contribute to the value - so give it a standard value of zero. */ - if (length == 0) - { - *valuep = 0; - return 1; - } - - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); - - if (word_length > 32) - abort (); - - /* For architectures with insns smaller than the insn-base-bitsize, - word_length may be too big. */ -#if CGEN_MIN_INSN_BITSIZE < CGEN_BASE_INSN_BITSIZE - if (word_offset == 0 - && word_length > total_length) - word_length = total_length; -#endif - - /* Does the value reside in INSN_VALUE? */ - - if (word_offset == 0) - { - /* Written this way to avoid undefined behaviour. */ - CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; - - if (CGEN_INSN_LSB0_P) - value = insn_value >> ((start + 1) - length); - else - value = insn_value >> (word_length - (start + length)); - value &= mask; - /* sign extend? */ - if (! CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED) - && (value & (1L << (length - 1)))) - value |= ~mask; - } - -#if ! CGEN_INT_INSN_P - - else - { - unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; - - if (word_length > 32) - abort (); - - if (fill_cache (od, ex_info, word_offset / 8, word_length / 8, pc) == 0) - return 0; - - value = extract_1 (od, ex_info, start, length, word_length, bufp, pc); - } - -#endif /* ! CGEN_INT_INSN_P */ - - *valuep = value; - - return 1; -} - -/* Default print handler. */ - -static void -print_normal (od, dis_info, value, attrs, pc, length) - CGEN_OPCODE_DESC od; - PTR dis_info; - long value; - unsigned int attrs; - bfd_vma pc; - int length; -{ - disassemble_info *info = (disassemble_info *) dis_info; - -#ifdef CGEN_PRINT_NORMAL - CGEN_PRINT_NORMAL (od, info, value, attrs, pc, length); -#endif - - /* Print the operand as directed by the attributes. */ - if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) - ; /* nothing to do */ - else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED)) - (*info->fprintf_func) (info->stream, "0x%lx", value); - else - (*info->fprintf_func) (info->stream, "%ld", value); -} - -/* Default address handler. */ - -static void -print_address (od, dis_info, value, attrs, pc, length) - CGEN_OPCODE_DESC od; - PTR dis_info; - bfd_vma value; - unsigned int attrs; - bfd_vma pc; - int length; -{ - disassemble_info *info = (disassemble_info *) dis_info; - -#ifdef CGEN_PRINT_ADDRESS - CGEN_PRINT_ADDRESS (od, info, value, attrs, pc, length); -#endif - - /* Print the operand as directed by the attributes. */ - if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) - ; /* nothing to do */ - else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) - (*info->print_address_func) (value, info); - else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) - (*info->print_address_func) (value, info); - else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED)) - (*info->fprintf_func) (info->stream, "0x%lx", (long) value); - else - (*info->fprintf_func) (info->stream, "%ld", (long) value); -} - -/* Keyword print handler. */ - -static void -print_keyword (od, dis_info, keyword_table, value, attrs) - CGEN_OPCODE_DESC od; - PTR dis_info; - CGEN_KEYWORD *keyword_table; - long value; - unsigned int attrs; -{ - disassemble_info *info = (disassemble_info *) dis_info; - const CGEN_KEYWORD_ENTRY *ke; - - ke = cgen_keyword_lookup_value (keyword_table, value); - if (ke != NULL) - (*info->fprintf_func) (info->stream, "%s", ke->name); - else - (*info->fprintf_func) (info->stream, "???"); -} - -/* Default insn extractor. - - INSN_VALUE is the first CGEN_BASE_INSN_SIZE bytes, translated to host order. - The extracted fields are stored in FIELDS. - EX_INFO is used to handle reading variable length insns. - Return the length of the insn in bits, or 0 if no match, - or -1 if an error occurs fetching data (memory_error_func will have - been called). */ - -static int -extract_insn_normal (od, insn, ex_info, insn_value, fields, pc) - CGEN_OPCODE_DESC od; - const CGEN_INSN *insn; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - CGEN_FIELDS *fields; - bfd_vma pc; -{ - const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); - const unsigned char *syn; - - CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); - - CGEN_INIT_EXTRACT (od); - - for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) - { - int length; - - if (CGEN_SYNTAX_CHAR_P (*syn)) - continue; - - length = fr30_cgen_extract_operand (od, CGEN_SYNTAX_FIELD (*syn), - ex_info, insn_value, fields, pc); - if (length <= 0) - return length; - } - - /* We recognized and successfully extracted this insn. */ - return CGEN_INSN_BITSIZE (insn); -} - -/* Default insn printer. - - DIS_INFO is defined as `PTR' so the disassembler needn't know anything - about disassemble_info. */ - -static void -print_insn_normal (od, dis_info, insn, fields, pc, length) - CGEN_OPCODE_DESC od; - PTR dis_info; - const CGEN_INSN *insn; - CGEN_FIELDS *fields; - bfd_vma pc; - int length; -{ - const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); - disassemble_info *info = (disassemble_info *) dis_info; - const unsigned char *syn; - - CGEN_INIT_PRINT (od); - - for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) - { - if (CGEN_SYNTAX_MNEMONIC_P (*syn)) - { - (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); - continue; - } - if (CGEN_SYNTAX_CHAR_P (*syn)) - { - (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); - continue; - } - - /* We have an operand. */ - fr30_cgen_print_operand (od, CGEN_SYNTAX_FIELD (*syn), info, - fields, CGEN_INSN_ATTRS (insn), pc, length); - } -} - -/* Utility to print an insn. - BUF is the base part of the insn, target byte order, BUFLEN bytes long. - The result is the size of the insn in bytes or zero for an unknown insn - or -1 if an error occurs fetching data (memory_error_func will have - been called). */ - -static int -print_insn (od, pc, info, buf, buflen) - CGEN_OPCODE_DESC od; - bfd_vma pc; - disassemble_info *info; - char *buf; - int buflen; -{ - unsigned long insn_value; - const CGEN_INSN_LIST *insn_list; - CGEN_EXTRACT_INFO ex_info; - - ex_info.dis_info = info; - ex_info.valid = (1 << CGEN_BASE_INSN_SIZE) - 1; - ex_info.insn_bytes = buf; - - switch (buflen) - { - case 1: - insn_value = buf[0]; - break; - case 2: - insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf); - break; - case 4: - insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf); - break; - default: - abort (); - } - - /* The instructions are stored in hash lists. - Pick the first one and keep trying until we find the right one. */ - - insn_list = CGEN_DIS_LOOKUP_INSN (od, buf, insn_value); - while (insn_list != NULL) - { - const CGEN_INSN *insn = insn_list->insn; - CGEN_FIELDS fields; - int length; - -#if 0 /* not needed as insn shouldn't be in hash lists if not supported */ - /* Supported by this cpu? */ - if (! fr30_cgen_insn_supported (od, insn)) - continue; -#endif - - /* Basic bit mask must be correct. */ - /* ??? May wish to allow target to defer this check until the extract - handler. */ - if ((insn_value & CGEN_INSN_BASE_MASK (insn)) - == CGEN_INSN_BASE_VALUE (insn)) - { - /* Printing is handled in two passes. The first pass parses the - machine insn and extracts the fields. The second pass prints - them. */ - - length = (*CGEN_EXTRACT_FN (insn)) (od, insn, &ex_info, insn_value, - &fields, pc); - /* length < 0 -> error */ - if (length < 0) - return length; - if (length > 0) - { - (*CGEN_PRINT_FN (insn)) (od, info, insn, &fields, pc, length); - /* length is in bits, result is in bytes */ - return length / 8; - } - } - - insn_list = CGEN_DIS_NEXT_INSN (insn_list); - } - - return 0; -} - -/* Default value for CGEN_PRINT_INSN. - The result is the size of the insn in bytes or zero for an unknown insn - or -1 if an error occured fetching bytes. */ - -#ifndef CGEN_PRINT_INSN -#define CGEN_PRINT_INSN default_print_insn -#endif - -static int -default_print_insn (od, pc, info) - CGEN_OPCODE_DESC od; - bfd_vma pc; - disassemble_info *info; -{ - char buf[CGEN_MAX_INSN_SIZE]; - int status; - - /* Read the base part of the insn. */ - - status = (*info->read_memory_func) (pc, buf, CGEN_BASE_INSN_SIZE, info); - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return -1; - } - - return print_insn (od, pc, info, buf, CGEN_BASE_INSN_SIZE); -} - -/* Main entry point. - Print one instruction from PC on INFO->STREAM. - Return the size of the instruction (in bytes). */ - -int -print_insn_fr30 (pc, info) - bfd_vma pc; - disassemble_info *info; -{ - int length; - static CGEN_OPCODE_DESC od = 0; - int mach = info->mach; - int big_p = info->endian == BFD_ENDIAN_BIG; - - /* If we haven't initialized yet, initialize the opcode table. */ - if (! od) - { - od = fr30_cgen_opcode_open (mach, - big_p ? - CGEN_ENDIAN_BIG - : CGEN_ENDIAN_LITTLE); - fr30_cgen_init_dis (od); - } - /* If we've switched cpu's, re-initialize. */ - /* ??? Perhaps we should use BFD_ENDIAN. */ - else if (mach != CGEN_OPCODE_MACH (od) - || (CGEN_OPCODE_ENDIAN (od) - != (big_p ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE))) - { - cgen_set_cpu (od, mach, big_p ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); - } - - /* We try to have as much common code as possible. - But at this point some targets need to take over. */ - /* ??? Some targets may need a hook elsewhere. Try to avoid this, - but if not possible try to move this hook elsewhere rather than - have two hooks. */ - length = CGEN_PRINT_INSN (od, pc, info); - if (length > 0) - return length; - if (length < 0) - return -1; - - (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); - return CGEN_DEFAULT_INSN_SIZE; -} diff --git a/opcodes/fr30-opc.c b/opcodes/fr30-opc.c deleted file mode 100644 index 2f33646b03b..00000000000 --- a/opcodes/fr30-opc.c +++ /dev/null @@ -1,3278 +0,0 @@ -/* Generic opcode table support for targets using CGEN. -*- C -*- - CGEN: Cpu tools GENerator - -THIS FILE IS USED TO GENERATE fr30-opc.c. - -Copyright (C) 1998 Free Software Foundation, Inc. - -This file is part of the GNU Binutils and GDB, the GNU debugger. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include <stdio.h> -#include "ansidecl.h" -#include "libiberty.h" -#include "bfd.h" -#include "symcat.h" -#include "fr30-opc.h" -#include "opintl.h" - -/* Used by the ifield rtx function. */ -#define FLD(f) (fields->f) - -/* The hash functions are recorded here to help keep assembler code out of - the disassembler and vice versa. */ - -static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int asm_hash_insn PARAMS ((const char *)); -static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); - -/* Look up instruction INSN_VALUE and extract its fields. - INSN, if non-null, is the insn table entry. - Otherwise INSN_VALUE is examined to compute it. - LENGTH is the bit length of INSN_VALUE if known, otherwise 0. - 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'. - If INSN != NULL, LENGTH must be valid. - ALIAS_P is non-zero if alias insns are to be included in the search. - - The result is a pointer to the insn table entry, or NULL if the instruction - wasn't recognized. */ - -const CGEN_INSN * -fr30_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p) - CGEN_OPCODE_DESC od; - const CGEN_INSN *insn; - CGEN_INSN_BYTES insn_value; - int length; - CGEN_FIELDS *fields; - int alias_p; -{ - unsigned char buf[CGEN_MAX_INSN_SIZE]; - unsigned char *bufp; - CGEN_INSN_INT base_insn; -#if CGEN_INT_INSN_P - CGEN_EXTRACT_INFO *info = NULL; -#else - CGEN_EXTRACT_INFO ex_info; - CGEN_EXTRACT_INFO *info = &ex_info; -#endif - -#if CGEN_INT_INSN_P - cgen_put_insn_value (od, buf, length, insn_value); - bufp = buf; - base_insn = insn_value; /*???*/ -#else - ex_info.dis_info = NULL; - ex_info.insn_bytes = insn_value; - ex_info.valid = -1; - base_insn = cgen_get_insn_value (od, buf, length); - bufp = insn_value; -#endif - - if (!insn) - { - const CGEN_INSN_LIST *insn_list; - - /* The instructions are stored in hash lists. - Pick the first one and keep trying until we find the right one. */ - - insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn); - while (insn_list != NULL) - { - insn = insn_list->insn; - - if (alias_p - || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS)) - { - /* Basic bit mask must be correct. */ - /* ??? May wish to allow target to defer this check until the - extract handler. */ - if ((base_insn & CGEN_INSN_BASE_MASK (insn)) - == CGEN_INSN_BASE_VALUE (insn)) - { - /* ??? 0 is passed for `pc' */ - int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, - base_insn, fields, - (bfd_vma) 0); - if (elength > 0) - { - /* sanity check */ - if (length != 0 && length != elength) - abort (); - return insn; - } - } - } - - insn_list = CGEN_DIS_NEXT_INSN (insn_list); - } - } - else - { - /* Sanity check: can't pass an alias insn if ! alias_p. */ - if (! alias_p - && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS)) - abort (); - /* Sanity check: length must be correct. */ - if (length != CGEN_INSN_BITSIZE (insn)) - abort (); - - /* ??? 0 is passed for `pc' */ - length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields, - (bfd_vma) 0); - /* Sanity check: must succeed. - Could relax this later if it ever proves useful. */ - if (length == 0) - abort (); - return insn; - } - - return NULL; -} - -/* Fill in the operand instances used by INSN whose operands are FIELDS. - INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled - in. */ - -void -fr30_cgen_get_insn_operands (od, insn, fields, indices) - CGEN_OPCODE_DESC od; - const CGEN_INSN * insn; - const CGEN_FIELDS * fields; - int *indices; -{ - const CGEN_OPERAND_INSTANCE *opinst; - int i; - - for (i = 0, opinst = CGEN_INSN_OPERANDS (insn); - opinst != NULL - && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END; - ++i, ++opinst) - { - const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst); - if (op == NULL) - indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst); - else - indices[i] = fr30_cgen_get_int_operand (CGEN_OPERAND_INDEX (op), - fields); - } -} - -/* Cover function to fr30_cgen_get_insn_operands when either INSN or FIELDS - isn't known. - The INSN, INSN_VALUE, and LENGTH arguments are passed to - fr30_cgen_lookup_insn unchanged. - - The result is the insn table entry or NULL if the instruction wasn't - recognized. */ - -const CGEN_INSN * -fr30_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices) - CGEN_OPCODE_DESC od; - const CGEN_INSN *insn; - CGEN_INSN_BYTES insn_value; - int length; - int *indices; -{ - CGEN_FIELDS fields; - - /* Pass non-zero for ALIAS_P only if INSN != NULL. - If INSN == NULL, we want a real insn. */ - insn = fr30_cgen_lookup_insn (od, insn, insn_value, length, &fields, - insn != NULL); - if (! insn) - return NULL; - - fr30_cgen_get_insn_operands (od, insn, &fields, indices); - return insn; -} -/* Attributes. */ - -static const CGEN_ATTR_ENTRY bool_attr[] = -{ - { "#f", 0 }, - { "#t", 1 }, - { 0, 0 } -}; - -static const CGEN_ATTR_ENTRY MACH_attr[] = -{ - { "base", MACH_BASE }, - { "fr30", MACH_FR30 }, - { "max", MACH_MAX }, - { 0, 0 } -}; - -const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] = -{ - { "MACH", & MACH_attr[0] }, - { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, - { "UNSIGNED", &bool_attr[0], &bool_attr[0] }, - { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, - { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, - { "RESERVED", &bool_attr[0], &bool_attr[0] }, - { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, - { 0, 0, 0 } -}; - -const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] = -{ - { "MACH", & MACH_attr[0] }, - { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, - { "UNSIGNED", &bool_attr[0], &bool_attr[0] }, - { "SIGNED", &bool_attr[0], &bool_attr[0] }, - { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, - { "FUN-ACCESS", &bool_attr[0], &bool_attr[0] }, - { "PC", &bool_attr[0], &bool_attr[0] }, - { "PROFILE", &bool_attr[0], &bool_attr[0] }, - { 0, 0, 0 } -}; - -const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] = -{ - { "MACH", & MACH_attr[0] }, - { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, - { "UNSIGNED", &bool_attr[0], &bool_attr[0] }, - { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, - { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, - { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, - { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, - { "RELAX", &bool_attr[0], &bool_attr[0] }, - { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, - { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] }, - { 0, 0, 0 } -}; - -const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] = -{ - { "MACH", & MACH_attr[0] }, - { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, - { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, - { "COND-CTI", &bool_attr[0], &bool_attr[0] }, - { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, - { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, - { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, - { "RELAX", &bool_attr[0], &bool_attr[0] }, - { "ALIAS", &bool_attr[0], &bool_attr[0] }, - { "NO-DIS", &bool_attr[0], &bool_attr[0] }, - { "PBB", &bool_attr[0], &bool_attr[0] }, - { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, - { 0, 0, 0 } -}; - -CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_gr_entries[] = -{ - { "r0", 0 }, - { "r1", 1 }, - { "r2", 2 }, - { "r3", 3 }, - { "r4", 4 }, - { "r5", 5 }, - { "r6", 6 }, - { "r7", 7 }, - { "r8", 8 }, - { "r9", 9 }, - { "r10", 10 }, - { "r11", 11 }, - { "r12", 12 }, - { "r13", 13 }, - { "r14", 14 }, - { "r15", 15 }, - { "ac", 13 }, - { "fp", 14 }, - { "sp", 15 } -}; - -CGEN_KEYWORD fr30_cgen_opval_h_gr = -{ - & fr30_cgen_opval_h_gr_entries[0], - 19 -}; - -CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_cr_entries[] = -{ - { "cr0", 0 }, - { "cr1", 1 }, - { "cr2", 2 }, - { "cr3", 3 }, - { "cr4", 4 }, - { "cr5", 5 }, - { "cr6", 6 }, - { "cr7", 7 }, - { "cr8", 8 }, - { "cr9", 9 }, - { "cr10", 10 }, - { "cr11", 11 }, - { "cr12", 12 }, - { "cr13", 13 }, - { "cr14", 14 }, - { "cr15", 15 } -}; - -CGEN_KEYWORD fr30_cgen_opval_h_cr = -{ - & fr30_cgen_opval_h_cr_entries[0], - 16 -}; - -CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries[] = -{ - { "tbr", 0 }, - { "rp", 1 }, - { "ssp", 2 }, - { "usp", 3 }, - { "mdh", 4 }, - { "mdl", 5 } -}; - -CGEN_KEYWORD fr30_cgen_opval_h_dr = -{ - & fr30_cgen_opval_h_dr_entries[0], - 6 -}; - -CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] = -{ - { "ps", 0 } -}; - -CGEN_KEYWORD fr30_cgen_opval_h_ps = -{ - & fr30_cgen_opval_h_ps_entries[0], - 1 -}; - -CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] = -{ - { "r13", 0 } -}; - -CGEN_KEYWORD fr30_cgen_opval_h_r13 = -{ - & fr30_cgen_opval_h_r13_entries[0], - 1 -}; - -CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] = -{ - { "r14", 0 } -}; - -CGEN_KEYWORD fr30_cgen_opval_h_r14 = -{ - & fr30_cgen_opval_h_r14_entries[0], - 1 -}; - -CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] = -{ - { "r15", 0 } -}; - -CGEN_KEYWORD fr30_cgen_opval_h_r15 = -{ - & fr30_cgen_opval_h_r15_entries[0], - 1 -}; - - -/* The hardware table. */ - -#define HW_ENT(n) fr30_cgen_hw_entries[n] -static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] = -{ - { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { (1<<MACH_BASE) } } }, - { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { (1<<MACH_BASE) } } }, - { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_cr, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } }, - { HW_H_PS, & HW_ENT (HW_H_PS + 1), "h-ps", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } }, - { HW_H_R13, & HW_ENT (HW_H_R13 + 1), "h-r13", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_R14, & HW_ENT (HW_H_R14 + 1), "h-r14", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_R15, & HW_ENT (HW_H_R15 + 1), "h-r15", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_IBIT, & HW_ENT (HW_H_IBIT + 1), "h-ibit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_SBIT, & HW_ENT (HW_H_SBIT + 1), "h-sbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } }, - { HW_H_TBIT, & HW_ENT (HW_H_TBIT + 1), "h-tbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_D0BIT, & HW_ENT (HW_H_D0BIT + 1), "h-d0bit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_D1BIT, & HW_ENT (HW_H_D1BIT + 1), "h-d1bit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_CCR, & HW_ENT (HW_H_CCR + 1), "h-ccr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } }, - { HW_H_SCR, & HW_ENT (HW_H_SCR + 1), "h-scr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } }, - { HW_H_ILM, & HW_ENT (HW_H_ILM + 1), "h-ilm", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } }, - { 0 } -}; - -/* The instruction field table. */ - -static const CGEN_IFLD fr30_cgen_ifld_table[] = -{ - { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_CC, "f-cc", 0, 16, 4, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_U4, "f-u4", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_I4, "f-i4", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { FR30_F_M4, "f-m4", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_U8, "f-u8", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_I8, "f-i8", 0, 16, 4, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_I32, "f-i32", 16, 32, 0, 32, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_SIGN_OPT)|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { FR30_F_S10, "f-s10", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { FR30_F_U10, "f-u10", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } }, - { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } }, - { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { 0 } -}; - -/* The operand table. */ - -#define OPERAND(op) CONCAT2 (FR30_OPERAND_,op) -#define OP_ENT(op) fr30_cgen_operand_table[OPERAND (op)] - -const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] = -{ -/* pc: program counter */ - { "pc", & HW_ENT (HW_H_PC), 0, 0, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } }, -/* Ri: destination register */ - { "Ri", & HW_ENT (HW_H_GR), 12, 4, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* Rj: source register */ - { "Rj", & HW_ENT (HW_H_GR), 8, 4, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* Ric: target register coproc insn */ - { "Ric", & HW_ENT (HW_H_GR), 12, 4, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* Rjc: source register coproc insn */ - { "Rjc", & HW_ENT (HW_H_GR), 8, 4, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* CRi: coprocessor register */ - { "CRi", & HW_ENT (HW_H_CR), 12, 4, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* CRj: coprocessor register */ - { "CRj", & HW_ENT (HW_H_CR), 8, 4, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* Rs1: dedicated register */ - { "Rs1", & HW_ENT (HW_H_DR), 8, 4, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* Rs2: dedicated register */ - { "Rs2", & HW_ENT (HW_H_DR), 12, 4, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* R13: General Register 13 */ - { "R13", & HW_ENT (HW_H_R13), 0, 0, - { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, -/* R14: General Register 14 */ - { "R14", & HW_ENT (HW_H_R14), 0, 0, - { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, -/* R15: General Register 15 */ - { "R15", & HW_ENT (HW_H_R15), 0, 0, - { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, -/* ps: Program Status register */ - { "ps", & HW_ENT (HW_H_PS), 0, 0, - { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, -/* u4: 4 bit unsigned immediate */ - { "u4", & HW_ENT (HW_H_UINT), 8, 4, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* u4c: 4 bit unsigned immediate */ - { "u4c", & HW_ENT (HW_H_UINT), 12, 4, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* u8: 8 bit unsigned immediate */ - { "u8", & HW_ENT (HW_H_UINT), 8, 8, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* i8: 8 bit unsigned immediate */ - { "i8", & HW_ENT (HW_H_UINT), 4, 8, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* udisp6: 6 bit unsigned immediate */ - { "udisp6", & HW_ENT (HW_H_UINT), 8, 4, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* disp8: 8 bit signed immediate */ - { "disp8", & HW_ENT (HW_H_SINT), 4, 8, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } }, -/* disp9: 9 bit signed immediate */ - { "disp9", & HW_ENT (HW_H_SINT), 4, 8, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } }, -/* disp10: 10 bit signed immediate */ - { "disp10", & HW_ENT (HW_H_SINT), 4, 8, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } }, -/* s10: 10 bit signed immediate */ - { "s10", & HW_ENT (HW_H_SINT), 8, 8, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } }, -/* u10: 10 bit unsigned immediate */ - { "u10", & HW_ENT (HW_H_UINT), 8, 8, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* i32: 32 bit immediate */ - { "i32", & HW_ENT (HW_H_UINT), 0, 32, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* m4: 4 bit negative immediate */ - { "m4", & HW_ENT (HW_H_SINT), 8, 4, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* i20: 20 bit immediate */ - { "i20", & HW_ENT (HW_H_UINT), 0, 20, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED)|(1<<CGEN_OPERAND_VIRTUAL), { (1<<MACH_BASE) } } }, -/* dir8: 8 bit direct address */ - { "dir8", & HW_ENT (HW_H_UINT), 8, 8, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* dir9: 9 bit direct address */ - { "dir9", & HW_ENT (HW_H_UINT), 8, 8, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* dir10: 10 bit direct address */ - { "dir10", & HW_ENT (HW_H_UINT), 8, 8, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* label9: 9 bit pc relative address */ - { "label9", & HW_ENT (HW_H_IADDR), 8, 8, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } }, -/* label12: 12 bit pc relative address */ - { "label12", & HW_ENT (HW_H_IADDR), 5, 11, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } }, -/* reglist_low_ld: 8 bit register mask for ldm */ - { "reglist_low_ld", & HW_ENT (HW_H_UINT), 8, 8, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* reglist_hi_ld: 8 bit register mask for ldm */ - { "reglist_hi_ld", & HW_ENT (HW_H_UINT), 8, 8, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* reglist_low_st: 8 bit register mask for ldm */ - { "reglist_low_st", & HW_ENT (HW_H_UINT), 8, 8, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* reglist_hi_st: 8 bit register mask for ldm */ - { "reglist_hi_st", & HW_ENT (HW_H_UINT), 8, 8, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* cc: condition codes */ - { "cc", & HW_ENT (HW_H_UINT), 4, 4, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* ccc: coprocessor calc */ - { "ccc", & HW_ENT (HW_H_UINT), 0, 8, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* nbit: negative bit */ - { "nbit", & HW_ENT (HW_H_NBIT), 0, 0, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } }, -/* vbit: overflow bit */ - { "vbit", & HW_ENT (HW_H_VBIT), 0, 0, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } }, -/* zbit: zero bit */ - { "zbit", & HW_ENT (HW_H_ZBIT), 0, 0, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } }, -/* cbit: carry bit */ - { "cbit", & HW_ENT (HW_H_CBIT), 0, 0, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } }, -/* ibit: interrupt bit */ - { "ibit", & HW_ENT (HW_H_IBIT), 0, 0, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } }, -/* sbit: stack bit */ - { "sbit", & HW_ENT (HW_H_SBIT), 0, 0, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } }, -/* tbit: trace trap bit */ - { "tbit", & HW_ENT (HW_H_TBIT), 0, 0, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } }, -/* d0bit: division 0 bit */ - { "d0bit", & HW_ENT (HW_H_D0BIT), 0, 0, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } }, -/* d1bit: division 1 bit */ - { "d1bit", & HW_ENT (HW_H_D1BIT), 0, 0, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } }, -/* ccr: condition code bits */ - { "ccr", & HW_ENT (HW_H_CCR), 0, 0, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } }, -/* scr: system condition bits */ - { "scr", & HW_ENT (HW_H_SCR), 0, 0, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } }, -/* ilm: interrupt level mask */ - { "ilm", & HW_ENT (HW_H_ILM), 0, 0, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } }, -}; - -/* Instruction formats. */ - -#define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)] - -static const CGEN_IFMT fmt_empty = { - 0, 0, 0x0, { 0 } -}; - -static const CGEN_IFMT fmt_add = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_addi = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_add2 = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_addc = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_addn = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_addni = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_addn2 = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_cmp = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_cmpi = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_cmp2 = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_and = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_andm = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_andh = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_andb = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_bandl = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_btstl = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_mul = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_mulu = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_mulh = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_div0s = { - 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_div0u = { - 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_div1 = { - 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_div2 = { - 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_div3 = { - 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 } -}; - -static const CGEN_IFMT fmt_div4s = { - 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 } -}; - -static const CGEN_IFMT fmt_lsl = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_lsli = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_ldi8 = { - 16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_ldi20 = { - 16, 32, 0xff00, { F (F_OP1), F (F_I20), F (F_OP2), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_ldi32 = { - 16, 48, 0xfff0, { F (F_OP1), F (F_I32), F (F_OP2), F (F_OP3), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_ld = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_lduh = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_ldub = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_ldr13 = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_ldr13uh = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_ldr13ub = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_ldr14 = { - 16, 16, 0xf000, { F (F_OP1), F (F_DISP10), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_ldr14uh = { - 16, 16, 0xf000, { F (F_OP1), F (F_DISP9), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_ldr14ub = { - 16, 16, 0xf000, { F (F_OP1), F (F_DISP8), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_ldr15 = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_UDISP6), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_ldr15gr = { - 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_ldr15dr = { - 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RS2), 0 } -}; - -static const CGEN_IFMT fmt_ldr15ps = { - 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 } -}; - -static const CGEN_IFMT fmt_st = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_sth = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_stb = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_str13 = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_str13h = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_str13b = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_str14 = { - 16, 16, 0xf000, { F (F_OP1), F (F_DISP10), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_str14h = { - 16, 16, 0xf000, { F (F_OP1), F (F_DISP9), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_str14b = { - 16, 16, 0xf000, { F (F_OP1), F (F_DISP8), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_str15 = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_UDISP6), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_str15gr = { - 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_str15dr = { - 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RS2), 0 } -}; - -static const CGEN_IFMT fmt_str15ps = { - 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 } -}; - -static const CGEN_IFMT fmt_mov = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_movdr = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_movps = { - 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_mov2dr = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_mov2ps = { - 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_jmp = { - 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_callr = { - 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_call = { - 16, 16, 0xf800, { F (F_OP1), F (F_OP5), F (F_REL12), 0 } -}; - -static const CGEN_IFMT fmt_ret = { - 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 } -}; - -static const CGEN_IFMT fmt_int = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 } -}; - -static const CGEN_IFMT fmt_inte = { - 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 } -}; - -static const CGEN_IFMT fmt_reti = { - 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 } -}; - -static const CGEN_IFMT fmt_brad = { - 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 } -}; - -static const CGEN_IFMT fmt_beqd = { - 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 } -}; - -static const CGEN_IFMT fmt_bcd = { - 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 } -}; - -static const CGEN_IFMT fmt_bnd = { - 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 } -}; - -static const CGEN_IFMT fmt_bvd = { - 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 } -}; - -static const CGEN_IFMT fmt_bltd = { - 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 } -}; - -static const CGEN_IFMT fmt_bled = { - 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 } -}; - -static const CGEN_IFMT fmt_blsd = { - 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 } -}; - -static const CGEN_IFMT fmt_dmovr13 = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 } -}; - -static const CGEN_IFMT fmt_dmovr13h = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 } -}; - -static const CGEN_IFMT fmt_dmovr13b = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 } -}; - -static const CGEN_IFMT fmt_dmovr13pi = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 } -}; - -static const CGEN_IFMT fmt_dmovr13pih = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 } -}; - -static const CGEN_IFMT fmt_dmovr13pib = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 } -}; - -static const CGEN_IFMT fmt_dmovr15pi = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 } -}; - -static const CGEN_IFMT fmt_dmov2r13 = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 } -}; - -static const CGEN_IFMT fmt_dmov2r13h = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 } -}; - -static const CGEN_IFMT fmt_dmov2r13b = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 } -}; - -static const CGEN_IFMT fmt_dmov2r13pi = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 } -}; - -static const CGEN_IFMT fmt_dmov2r13pih = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 } -}; - -static const CGEN_IFMT fmt_dmov2r13pib = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 } -}; - -static const CGEN_IFMT fmt_dmov2r15pd = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 } -}; - -static const CGEN_IFMT fmt_ldres = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_copop = { - 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_CRI), 0 } -}; - -static const CGEN_IFMT fmt_copld = { - 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_RJC), F (F_U4C), F (F_CRI), 0 } -}; - -static const CGEN_IFMT fmt_copst = { - 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_RIC), 0 } -}; - -static const CGEN_IFMT fmt_nop = { - 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 } -}; - -static const CGEN_IFMT fmt_andccr = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 } -}; - -static const CGEN_IFMT fmt_stilm = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 } -}; - -static const CGEN_IFMT fmt_addsp = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_S10), 0 } -}; - -static const CGEN_IFMT fmt_extsb = { - 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_extub = { - 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_extsh = { - 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_extuh = { - 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_ldm0 = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_LOW_LD), 0 } -}; - -static const CGEN_IFMT fmt_ldm1 = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_HI_LD), 0 } -}; - -static const CGEN_IFMT fmt_stm0 = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_LOW_ST), 0 } -}; - -static const CGEN_IFMT fmt_stm1 = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_HI_ST), 0 } -}; - -static const CGEN_IFMT fmt_enter = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U10), 0 } -}; - -static const CGEN_IFMT fmt_leave = { - 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 } -}; - -static const CGEN_IFMT fmt_xchb = { - 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 } -}; - -#undef F - -#define A(a) (1 << CONCAT2 (CGEN_INSN_,a)) -#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ -#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) - -/* The instruction table. - This is currently non-static because the simulator accesses it - directly. */ - -const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] = -{ - /* Special null first entry. - A `num' value of zero is thus invalid. - Also, the special `invalid' insn resides here. */ - { { 0 }, 0 }, -/* add $Rj,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_ADD, "add", "add", - { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, - & fmt_add, { 0xa600 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* add $u4,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_ADDI, "addi", "add", - { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, - & fmt_addi, { 0xa400 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* add2 $m4,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_ADD2, "add2", "add2", - { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } }, - & fmt_add2, { 0xa500 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* addc $Rj,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_ADDC, "addc", "addc", - { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, - & fmt_addc, { 0xa700 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* addn $Rj,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_ADDN, "addn", "addn", - { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, - & fmt_addn, { 0xa200 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* addn $u4,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_ADDNI, "addni", "addn", - { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, - & fmt_addni, { 0xa000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* addn2 $m4,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_ADDN2, "addn2", "addn2", - { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } }, - & fmt_addn2, { 0xa100 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* sub $Rj,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_SUB, "sub", "sub", - { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, - & fmt_add, { 0xac00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* subc $Rj,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_SUBC, "subc", "subc", - { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, - & fmt_addc, { 0xad00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* subn $Rj,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_SUBN, "subn", "subn", - { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, - & fmt_addn, { 0xae00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* cmp $Rj,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_CMP, "cmp", "cmp", - { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, - & fmt_cmp, { 0xaa00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* cmp $u4,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_CMPI, "cmpi", "cmp", - { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, - & fmt_cmpi, { 0xa800 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* cmp2 $m4,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_CMP2, "cmp2", "cmp2", - { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } }, - & fmt_cmp2, { 0xa900 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* and $Rj,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_AND, "and", "and", - { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, - & fmt_and, { 0x8200 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* or $Rj,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_OR, "or", "or", - { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, - & fmt_and, { 0x9200 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* eor $Rj,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_EOR, "eor", "eor", - { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, - & fmt_and, { 0x9a00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* and $Rj,@$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_ANDM, "andm", "and", - { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, - & fmt_andm, { 0x8400 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* andh $Rj,@$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_ANDH, "andh", "andh", - { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, - & fmt_andh, { 0x8500 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* andb $Rj,@$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_ANDB, "andb", "andb", - { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, - & fmt_andb, { 0x8600 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* or $Rj,@$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_ORM, "orm", "or", - { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, - & fmt_andm, { 0x9400 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* orh $Rj,@$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_ORH, "orh", "orh", - { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, - & fmt_andh, { 0x9500 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* orb $Rj,@$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_ORB, "orb", "orb", - { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, - & fmt_andb, { 0x9600 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* eor $Rj,@$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_EORM, "eorm", "eor", - { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, - & fmt_andm, { 0x9c00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* eorh $Rj,@$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_EORH, "eorh", "eorh", - { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, - & fmt_andh, { 0x9d00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* eorb $Rj,@$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_EORB, "eorb", "eorb", - { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, - & fmt_andb, { 0x9e00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* bandl $u4,@$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BANDL, "bandl", "bandl", - { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } }, - & fmt_bandl, { 0x8000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* borl $u4,@$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BORL, "borl", "borl", - { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } }, - & fmt_bandl, { 0x9000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* beorl $u4,@$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BEORL, "beorl", "beorl", - { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } }, - & fmt_bandl, { 0x9800 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* bandh $u4,@$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BANDH, "bandh", "bandh", - { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } }, - & fmt_bandl, { 0x8100 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* borh $u4,@$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BORH, "borh", "borh", - { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } }, - & fmt_bandl, { 0x9100 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* beorh $u4,@$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BEORH, "beorh", "beorh", - { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } }, - & fmt_bandl, { 0x9900 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* btstl $u4,@$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BTSTL, "btstl", "btstl", - { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } }, - & fmt_btstl, { 0x8800 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* btsth $u4,@$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BTSTH, "btsth", "btsth", - { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } }, - & fmt_btstl, { 0x8900 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* mul $Rj,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_MUL, "mul", "mul", - { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, - & fmt_mul, { 0xaf00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* mulu $Rj,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_MULU, "mulu", "mulu", - { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, - & fmt_mulu, { 0xab00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* mulh $Rj,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_MULH, "mulh", "mulh", - { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, - & fmt_mulh, { 0xbf00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* muluh $Rj,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_MULUH, "muluh", "muluh", - { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, - & fmt_mulh, { 0xbb00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* div0s $Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_DIV0S, "div0s", "div0s", - { { MNEM, ' ', OP (RI), 0 } }, - & fmt_div0s, { 0x9740 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* div0u $Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_DIV0U, "div0u", "div0u", - { { MNEM, ' ', OP (RI), 0 } }, - & fmt_div0u, { 0x9750 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* div1 $Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_DIV1, "div1", "div1", - { { MNEM, ' ', OP (RI), 0 } }, - & fmt_div1, { 0x9760 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* div2 $Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_DIV2, "div2", "div2", - { { MNEM, ' ', OP (RI), 0 } }, - & fmt_div2, { 0x9770 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* div3 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_DIV3, "div3", "div3", - { { MNEM, 0 } }, - & fmt_div3, { 0x9f60 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* div4s */ - { - { 1, 1, 1, 1 }, - FR30_INSN_DIV4S, "div4s", "div4s", - { { MNEM, 0 } }, - & fmt_div4s, { 0x9f70 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* lsl $Rj,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LSL, "lsl", "lsl", - { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, - & fmt_lsl, { 0xb600 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* lsl $u4,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LSLI, "lsli", "lsl", - { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, - & fmt_lsli, { 0xb400 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* lsl2 $u4,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LSL2, "lsl2", "lsl2", - { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, - & fmt_lsli, { 0xb500 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* lsr $Rj,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LSR, "lsr", "lsr", - { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, - & fmt_lsl, { 0xb200 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* lsr $u4,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LSRI, "lsri", "lsr", - { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, - & fmt_lsli, { 0xb000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* lsr2 $u4,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LSR2, "lsr2", "lsr2", - { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, - & fmt_lsli, { 0xb100 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* asr $Rj,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_ASR, "asr", "asr", - { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, - & fmt_lsl, { 0xba00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* asr $u4,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_ASRI, "asri", "asr", - { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, - & fmt_lsli, { 0xb800 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* asr2 $u4,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_ASR2, "asr2", "asr2", - { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, - & fmt_lsli, { 0xb900 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* ldi:8 $i8,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LDI8, "ldi8", "ldi:8", - { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } }, - & fmt_ldi8, { 0xc000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* ldi:20 $i20,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LDI20, "ldi20", "ldi:20", - { { MNEM, ' ', OP (I20), ',', OP (RI), 0 } }, - & fmt_ldi20, { 0x9b00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* ldi:32 $i32,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LDI32, "ldi32", "ldi:32", - { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } }, - & fmt_ldi32, { 0x9f80 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* ld @$Rj,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LD, "ld", "ld", - { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } }, - & fmt_ld, { 0x400 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* lduh @$Rj,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LDUH, "lduh", "lduh", - { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } }, - & fmt_lduh, { 0x500 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* ldub @$Rj,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LDUB, "ldub", "ldub", - { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } }, - & fmt_ldub, { 0x600 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* ld @($R13,$Rj),$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LDR13, "ldr13", "ld", - { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } }, - & fmt_ldr13, { 0x0 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* lduh @($R13,$Rj),$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LDR13UH, "ldr13uh", "lduh", - { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } }, - & fmt_ldr13uh, { 0x100 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* ldub @($R13,$Rj),$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LDR13UB, "ldr13ub", "ldub", - { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } }, - & fmt_ldr13ub, { 0x200 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* ld @($R14,$disp10),$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LDR14, "ldr14", "ld", - { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP10), ')', ',', OP (RI), 0 } }, - & fmt_ldr14, { 0x2000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* lduh @($R14,$disp9),$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LDR14UH, "ldr14uh", "lduh", - { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP9), ')', ',', OP (RI), 0 } }, - & fmt_ldr14uh, { 0x4000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* ldub @($R14,$disp8),$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LDR14UB, "ldr14ub", "ldub", - { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP8), ')', ',', OP (RI), 0 } }, - & fmt_ldr14ub, { 0x6000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* ld @($R15,$udisp6),$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LDR15, "ldr15", "ld", - { { MNEM, ' ', '@', '(', OP (R15), ',', OP (UDISP6), ')', ',', OP (RI), 0 } }, - & fmt_ldr15, { 0x300 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* ld @$R15+,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LDR15GR, "ldr15gr", "ld", - { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RI), 0 } }, - & fmt_ldr15gr, { 0x700 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* ld @$R15+,$Rs2 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LDR15DR, "ldr15dr", "ld", - { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RS2), 0 } }, - & fmt_ldr15dr, { 0x780 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* ld @$R15+,$ps */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LDR15PS, "ldr15ps", "ld", - { { MNEM, ' ', '@', OP (R15), '+', ',', OP (PS), 0 } }, - & fmt_ldr15ps, { 0x790 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* st $Ri,@$Rj */ - { - { 1, 1, 1, 1 }, - FR30_INSN_ST, "st", "st", - { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } }, - & fmt_st, { 0x1400 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* sth $Ri,@$Rj */ - { - { 1, 1, 1, 1 }, - FR30_INSN_STH, "sth", "sth", - { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } }, - & fmt_sth, { 0x1500 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* stb $Ri,@$Rj */ - { - { 1, 1, 1, 1 }, - FR30_INSN_STB, "stb", "stb", - { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } }, - & fmt_stb, { 0x1600 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* st $Ri,@($R13,$Rj) */ - { - { 1, 1, 1, 1 }, - FR30_INSN_STR13, "str13", "st", - { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } }, - & fmt_str13, { 0x1000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* sth $Ri,@($R13,$Rj) */ - { - { 1, 1, 1, 1 }, - FR30_INSN_STR13H, "str13h", "sth", - { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } }, - & fmt_str13h, { 0x1100 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* stb $Ri,@($R13,$Rj) */ - { - { 1, 1, 1, 1 }, - FR30_INSN_STR13B, "str13b", "stb", - { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } }, - & fmt_str13b, { 0x1200 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* st $Ri,@($R14,$disp10) */ - { - { 1, 1, 1, 1 }, - FR30_INSN_STR14, "str14", "st", - { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP10), ')', 0 } }, - & fmt_str14, { 0x3000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* sth $Ri,@($R14,$disp9) */ - { - { 1, 1, 1, 1 }, - FR30_INSN_STR14H, "str14h", "sth", - { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP9), ')', 0 } }, - & fmt_str14h, { 0x5000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* stb $Ri,@($R14,$disp8) */ - { - { 1, 1, 1, 1 }, - FR30_INSN_STR14B, "str14b", "stb", - { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP8), ')', 0 } }, - & fmt_str14b, { 0x7000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* st $Ri,@($R15,$udisp6) */ - { - { 1, 1, 1, 1 }, - FR30_INSN_STR15, "str15", "st", - { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R15), ',', OP (UDISP6), ')', 0 } }, - & fmt_str15, { 0x1300 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* st $Ri,@-$R15 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_STR15GR, "str15gr", "st", - { { MNEM, ' ', OP (RI), ',', '@', '-', OP (R15), 0 } }, - & fmt_str15gr, { 0x1700 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* st $Rs2,@-$R15 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_STR15DR, "str15dr", "st", - { { MNEM, ' ', OP (RS2), ',', '@', '-', OP (R15), 0 } }, - & fmt_str15dr, { 0x1780 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* st $ps,@-$R15 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_STR15PS, "str15ps", "st", - { { MNEM, ' ', OP (PS), ',', '@', '-', OP (R15), 0 } }, - & fmt_str15ps, { 0x1790 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* mov $Rj,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_MOV, "mov", "mov", - { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, - & fmt_mov, { 0x8b00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* mov $Rs1,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_MOVDR, "movdr", "mov", - { { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } }, - & fmt_movdr, { 0xb700 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* mov $ps,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_MOVPS, "movps", "mov", - { { MNEM, ' ', OP (PS), ',', OP (RI), 0 } }, - & fmt_movps, { 0x1710 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* mov $Ri,$Rs1 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_MOV2DR, "mov2dr", "mov", - { { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } }, - & fmt_mov2dr, { 0xb300 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* mov $Ri,$ps */ - { - { 1, 1, 1, 1 }, - FR30_INSN_MOV2PS, "mov2ps", "mov", - { { MNEM, ' ', OP (RI), ',', OP (PS), 0 } }, - & fmt_mov2ps, { 0x710 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* jmp @$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_JMP, "jmp", "jmp", - { { MNEM, ' ', '@', OP (RI), 0 } }, - & fmt_jmp, { 0x9700 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } } - }, -/* jmp:d @$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_JMPD, "jmpd", "jmp:d", - { { MNEM, ' ', '@', OP (RI), 0 } }, - & fmt_jmp, { 0x9f00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* call @$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_CALLR, "callr", "call", - { { MNEM, ' ', '@', OP (RI), 0 } }, - & fmt_callr, { 0x9710 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } } - }, -/* call:d @$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_CALLRD, "callrd", "call:d", - { { MNEM, ' ', '@', OP (RI), 0 } }, - & fmt_callr, { 0x9f10 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* call $label12 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_CALL, "call", "call", - { { MNEM, ' ', OP (LABEL12), 0 } }, - & fmt_call, { 0xd000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } } - }, -/* call:d $label12 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_CALLD, "calld", "call:d", - { { MNEM, ' ', OP (LABEL12), 0 } }, - & fmt_call, { 0xd800 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* ret */ - { - { 1, 1, 1, 1 }, - FR30_INSN_RET, "ret", "ret", - { { MNEM, 0 } }, - & fmt_ret, { 0x9720 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } } - }, -/* ret:d */ - { - { 1, 1, 1, 1 }, - FR30_INSN_RET_D, "ret:d", "ret:d", - { { MNEM, 0 } }, - & fmt_ret, { 0x9f20 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* int $u8 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_INT, "int", "int", - { { MNEM, ' ', OP (U8), 0 } }, - & fmt_int, { 0x1f00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } } - }, -/* inte */ - { - { 1, 1, 1, 1 }, - FR30_INSN_INTE, "inte", "inte", - { { MNEM, 0 } }, - & fmt_inte, { 0x9f30 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } } - }, -/* reti */ - { - { 1, 1, 1, 1 }, - FR30_INSN_RETI, "reti", "reti", - { { MNEM, 0 } }, - & fmt_reti, { 0x9730 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } - }, -/* bra:d $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BRAD, "brad", "bra:d", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_brad, { 0xf000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* bra $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BRA, "bra", "bra", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_brad, { 0xe000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } } - }, -/* bno:d $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BNOD, "bnod", "bno:d", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_brad, { 0xf100 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* bno $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BNO, "bno", "bno", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_brad, { 0xe100 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } } - }, -/* beq:d $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BEQD, "beqd", "beq:d", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_beqd, { 0xf200 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* beq $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BEQ, "beq", "beq", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_beqd, { 0xe200 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } - }, -/* bne:d $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BNED, "bned", "bne:d", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_beqd, { 0xf300 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* bne $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BNE, "bne", "bne", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_beqd, { 0xe300 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } - }, -/* bc:d $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BCD, "bcd", "bc:d", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_bcd, { 0xf400 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* bc $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BC, "bc", "bc", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_bcd, { 0xe400 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } - }, -/* bnc:d $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BNCD, "bncd", "bnc:d", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_bcd, { 0xf500 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* bnc $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BNC, "bnc", "bnc", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_bcd, { 0xe500 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } - }, -/* bn:d $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BND, "bnd", "bn:d", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_bnd, { 0xf600 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* bn $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BN, "bn", "bn", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_bnd, { 0xe600 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } - }, -/* bp:d $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BPD, "bpd", "bp:d", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_bnd, { 0xf700 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* bp $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BP, "bp", "bp", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_bnd, { 0xe700 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } - }, -/* bv:d $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BVD, "bvd", "bv:d", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_bvd, { 0xf800 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* bv $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BV, "bv", "bv", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_bvd, { 0xe800 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } - }, -/* bnv:d $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BNVD, "bnvd", "bnv:d", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_bvd, { 0xf900 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* bnv $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BNV, "bnv", "bnv", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_bvd, { 0xe900 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } - }, -/* blt:d $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BLTD, "bltd", "blt:d", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_bltd, { 0xfa00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* blt $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BLT, "blt", "blt", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_bltd, { 0xea00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } - }, -/* bge:d $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BGED, "bged", "bge:d", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_bltd, { 0xfb00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* bge $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BGE, "bge", "bge", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_bltd, { 0xeb00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } - }, -/* ble:d $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BLED, "bled", "ble:d", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_bled, { 0xfc00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* ble $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BLE, "ble", "ble", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_bled, { 0xec00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } - }, -/* bgt:d $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BGTD, "bgtd", "bgt:d", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_bled, { 0xfd00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* bgt $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BGT, "bgt", "bgt", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_bled, { 0xed00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } - }, -/* bls:d $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BLSD, "blsd", "bls:d", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_blsd, { 0xfe00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* bls $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BLS, "bls", "bls", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_blsd, { 0xee00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } - }, -/* bhi:d $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BHID, "bhid", "bhi:d", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_blsd, { 0xff00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* bhi $label9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_BHI, "bhi", "bhi", - { { MNEM, ' ', OP (LABEL9), 0 } }, - & fmt_blsd, { 0xef00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } } - }, -/* dmov $R13,@$dir10 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_DMOVR13, "dmovr13", "dmov", - { { MNEM, ' ', OP (R13), ',', '@', OP (DIR10), 0 } }, - & fmt_dmovr13, { 0x1800 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* dmovh $R13,@$dir9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_DMOVR13H, "dmovr13h", "dmovh", - { { MNEM, ' ', OP (R13), ',', '@', OP (DIR9), 0 } }, - & fmt_dmovr13h, { 0x1900 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* dmovb $R13,@$dir8 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_DMOVR13B, "dmovr13b", "dmovb", - { { MNEM, ' ', OP (R13), ',', '@', OP (DIR8), 0 } }, - & fmt_dmovr13b, { 0x1a00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* dmov @$R13+,@$dir10 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov", - { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR10), 0 } }, - & fmt_dmovr13pi, { 0x1c00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* dmovh @$R13+,@$dir9 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh", - { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR9), 0 } }, - & fmt_dmovr13pih, { 0x1d00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* dmovb @$R13+,@$dir8 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb", - { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR8), 0 } }, - & fmt_dmovr13pib, { 0x1e00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* dmov @$R15+,@$dir10 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov", - { { MNEM, ' ', '@', OP (R15), '+', ',', '@', OP (DIR10), 0 } }, - & fmt_dmovr15pi, { 0x1b00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* dmov @$dir10,$R13 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_DMOV2R13, "dmov2r13", "dmov", - { { MNEM, ' ', '@', OP (DIR10), ',', OP (R13), 0 } }, - & fmt_dmov2r13, { 0x800 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* dmovh @$dir9,$R13 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh", - { { MNEM, ' ', '@', OP (DIR9), ',', OP (R13), 0 } }, - & fmt_dmov2r13h, { 0x900 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* dmovb @$dir8,$R13 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb", - { { MNEM, ' ', '@', OP (DIR8), ',', OP (R13), 0 } }, - & fmt_dmov2r13b, { 0xa00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* dmov @$dir10,@$R13+ */ - { - { 1, 1, 1, 1 }, - FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov", - { { MNEM, ' ', '@', OP (DIR10), ',', '@', OP (R13), '+', 0 } }, - & fmt_dmov2r13pi, { 0xc00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* dmovh @$dir9,@$R13+ */ - { - { 1, 1, 1, 1 }, - FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh", - { { MNEM, ' ', '@', OP (DIR9), ',', '@', OP (R13), '+', 0 } }, - & fmt_dmov2r13pih, { 0xd00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* dmovb @$dir8,@$R13+ */ - { - { 1, 1, 1, 1 }, - FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb", - { { MNEM, ' ', '@', OP (DIR8), ',', '@', OP (R13), '+', 0 } }, - & fmt_dmov2r13pib, { 0xe00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* dmov @$dir10,@-$R15 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov", - { { MNEM, ' ', '@', OP (DIR10), ',', '@', '-', OP (R15), 0 } }, - & fmt_dmov2r15pd, { 0xb00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* ldres @$Ri+,$u4 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LDRES, "ldres", "ldres", - { { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } }, - & fmt_ldres, { 0xbc00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* stres $u4,@$Ri+ */ - { - { 1, 1, 1, 1 }, - FR30_INSN_STRES, "stres", "stres", - { { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } }, - & fmt_ldres, { 0xbd00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* copop $u4c,$ccc,$CRj,$CRi */ - { - { 1, 1, 1, 1 }, - FR30_INSN_COPOP, "copop", "copop", - { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (CRI), 0 } }, - & fmt_copop, { 0x9fc0 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* copld $u4c,$ccc,$Rjc,$CRi */ - { - { 1, 1, 1, 1 }, - FR30_INSN_COPLD, "copld", "copld", - { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (RJC), ',', OP (CRI), 0 } }, - & fmt_copld, { 0x9fd0 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* copst $u4c,$ccc,$CRj,$Ric */ - { - { 1, 1, 1, 1 }, - FR30_INSN_COPST, "copst", "copst", - { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } }, - & fmt_copst, { 0x9fe0 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* copsv $u4c,$ccc,$CRj,$Ric */ - { - { 1, 1, 1, 1 }, - FR30_INSN_COPSV, "copsv", "copsv", - { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } }, - & fmt_copst, { 0x9ff0 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* nop */ - { - { 1, 1, 1, 1 }, - FR30_INSN_NOP, "nop", "nop", - { { MNEM, 0 } }, - & fmt_nop, { 0x9fa0 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* andccr $u8 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_ANDCCR, "andccr", "andccr", - { { MNEM, ' ', OP (U8), 0 } }, - & fmt_andccr, { 0x8300 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* orccr $u8 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_ORCCR, "orccr", "orccr", - { { MNEM, ' ', OP (U8), 0 } }, - & fmt_andccr, { 0x9300 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* stilm $u8 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_STILM, "stilm", "stilm", - { { MNEM, ' ', OP (U8), 0 } }, - & fmt_stilm, { 0x8700 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* addsp $s10 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_ADDSP, "addsp", "addsp", - { { MNEM, ' ', OP (S10), 0 } }, - & fmt_addsp, { 0xa300 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* extsb $Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_EXTSB, "extsb", "extsb", - { { MNEM, ' ', OP (RI), 0 } }, - & fmt_extsb, { 0x9780 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* extub $Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_EXTUB, "extub", "extub", - { { MNEM, ' ', OP (RI), 0 } }, - & fmt_extub, { 0x9790 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* extsh $Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_EXTSH, "extsh", "extsh", - { { MNEM, ' ', OP (RI), 0 } }, - & fmt_extsh, { 0x97a0 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* extuh $Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_EXTUH, "extuh", "extuh", - { { MNEM, ' ', OP (RI), 0 } }, - & fmt_extuh, { 0x97b0 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* ldm0 ($reglist_low_ld) */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LDM0, "ldm0", "ldm0", - { { MNEM, ' ', '(', OP (REGLIST_LOW_LD), ')', 0 } }, - & fmt_ldm0, { 0x8c00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* ldm1 ($reglist_hi_ld) */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LDM1, "ldm1", "ldm1", - { { MNEM, ' ', '(', OP (REGLIST_HI_LD), ')', 0 } }, - & fmt_ldm1, { 0x8d00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* stm0 ($reglist_low_st) */ - { - { 1, 1, 1, 1 }, - FR30_INSN_STM0, "stm0", "stm0", - { { MNEM, ' ', '(', OP (REGLIST_LOW_ST), ')', 0 } }, - & fmt_stm0, { 0x8e00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* stm1 ($reglist_hi_st) */ - { - { 1, 1, 1, 1 }, - FR30_INSN_STM1, "stm1", "stm1", - { { MNEM, ' ', '(', OP (REGLIST_HI_ST), ')', 0 } }, - & fmt_stm1, { 0x8f00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* enter $u10 */ - { - { 1, 1, 1, 1 }, - FR30_INSN_ENTER, "enter", "enter", - { { MNEM, ' ', OP (U10), 0 } }, - & fmt_enter, { 0xf00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -/* leave */ - { - { 1, 1, 1, 1 }, - FR30_INSN_LEAVE, "leave", "leave", - { { MNEM, 0 } }, - & fmt_leave, { 0x9f90 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } - }, -/* xchb @$Rj,$Ri */ - { - { 1, 1, 1, 1 }, - FR30_INSN_XCHB, "xchb", "xchb", - { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } }, - & fmt_xchb, { 0x8a00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } } - }, -}; - -#undef A -#undef MNEM -#undef OP - -static const CGEN_INSN_TABLE insn_table = -{ - & fr30_cgen_insn_table_entries[0], - sizeof (CGEN_INSN), - MAX_INSNS, - NULL -}; - -/* Formats for ALIAS macro-insns. */ - -#define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)] - -static const CGEN_IFMT fmt_ldi8m = { - 16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_ldi20m = { - 16, 32, 0xff00, { F (F_OP1), F (F_I20), F (F_OP2), F (F_RI), 0 } -}; - -static const CGEN_IFMT fmt_ldi32m = { - 16, 48, 0xfff0, { F (F_OP1), F (F_I32), F (F_OP2), F (F_OP3), F (F_RI), 0 } -}; - -#undef F - -/* Each non-simple macro entry points to an array of expansion possibilities. */ - -#define A(a) (1 << CONCAT2 (CGEN_INSN_,a)) -#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ -#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) - -/* The macro instruction table. */ - -static const CGEN_INSN macro_insn_table_entries[] = -{ -/* ldi8 $i8,$Ri */ - { - { 1, 1, 1, 1 }, - -1, "ldi8m", "ldi8", - { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } }, - & fmt_ldi8m, { 0xc000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } } - }, -/* ldi20 $i20,$Ri */ - { - { 1, 1, 1, 1 }, - -1, "ldi20m", "ldi20", - { { MNEM, ' ', OP (I20), ',', OP (RI), 0 } }, - & fmt_ldi20m, { 0x9b00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } } - }, -/* ldi32 $i32,$Ri */ - { - { 1, 1, 1, 1 }, - -1, "ldi32m", "ldi32", - { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } }, - & fmt_ldi32m, { 0x9f80 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } } - }, -}; - -#undef A -#undef MNEM -#undef OP - -static const CGEN_INSN_TABLE macro_insn_table = -{ - & macro_insn_table_entries[0], - sizeof (CGEN_INSN), - (sizeof (macro_insn_table_entries) / - sizeof (macro_insn_table_entries[0])), - NULL -}; - -static void -init_tables () -{ -} - -/* Return non-zero if INSN is to be added to the hash table. - Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */ - -static int -asm_hash_insn_p (insn) - const CGEN_INSN * insn; -{ - return CGEN_ASM_HASH_P (insn); -} - -static int -dis_hash_insn_p (insn) - const CGEN_INSN * insn; -{ - /* If building the hash table and the NO-DIS attribute is present, - ignore. */ - if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS)) - return 0; - return CGEN_DIS_HASH_P (insn); -} - -/* The result is the hash value of the insn. - Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */ - -static unsigned int -asm_hash_insn (mnem) - const char * mnem; -{ - return CGEN_ASM_HASH (mnem); -} - -/* BUF is a pointer to the insn's bytes in target order. - VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits, - host order. */ - -static unsigned int -dis_hash_insn (buf, value) - const char * buf; - CGEN_INSN_INT value; -{ - return CGEN_DIS_HASH (buf, value); -} - -/* Initialize an opcode table and return a descriptor. - It's much like opening a file, and must be the first function called. */ - -CGEN_OPCODE_DESC -fr30_cgen_opcode_open (mach, endian) - int mach; - enum cgen_endian endian; -{ - CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE)); - static int init_p; - - if (! init_p) - { - init_tables (); - init_p = 1; - } - - memset (table, 0, sizeof (*table)); - - CGEN_OPCODE_MACH (table) = mach; - CGEN_OPCODE_ENDIAN (table) = endian; - /* FIXME: for the sparc case we can determine insn-endianness statically. - The worry here is where both data and insn endian can be independently - chosen, in which case this function will need another argument. - Actually, will want to allow for more arguments in the future anyway. */ - CGEN_OPCODE_INSN_ENDIAN (table) = endian; - - CGEN_OPCODE_HW_LIST (table) = & fr30_cgen_hw_entries[0]; - - CGEN_OPCODE_IFLD_TABLE (table) = & fr30_cgen_ifld_table[0]; - - CGEN_OPCODE_OPERAND_TABLE (table) = & fr30_cgen_operand_table[0]; - - * CGEN_OPCODE_INSN_TABLE (table) = insn_table; - - * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table; - - CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p; - CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn; - CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE; - - CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p; - CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn; - CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE; - - return (CGEN_OPCODE_DESC) table; -} - -/* Close an opcode table. */ - -void -fr30_cgen_opcode_close (desc) - CGEN_OPCODE_DESC desc; -{ - free (desc); -} - -/* Getting values from cgen_fields is handled by a collection of functions. - They are distinguished by the type of the VALUE argument they return. - TODO: floating point, inlining support, remove cases where result type - not appropriate. */ - -int -fr30_cgen_get_int_operand (opindex, fields) - int opindex; - const CGEN_FIELDS * fields; -{ - int value; - - switch (opindex) - { - case FR30_OPERAND_RI : - value = fields->f_Ri; - break; - case FR30_OPERAND_RJ : - value = fields->f_Rj; - break; - case FR30_OPERAND_RIC : - value = fields->f_Ric; - break; - case FR30_OPERAND_RJC : - value = fields->f_Rjc; - break; - case FR30_OPERAND_CRI : - value = fields->f_CRi; - break; - case FR30_OPERAND_CRJ : - value = fields->f_CRj; - break; - case FR30_OPERAND_RS1 : - value = fields->f_Rs1; - break; - case FR30_OPERAND_RS2 : - value = fields->f_Rs2; - break; - case FR30_OPERAND_R13 : - value = fields->f_nil; - break; - case FR30_OPERAND_R14 : - value = fields->f_nil; - break; - case FR30_OPERAND_R15 : - value = fields->f_nil; - break; - case FR30_OPERAND_PS : - value = fields->f_nil; - break; - case FR30_OPERAND_U4 : - value = fields->f_u4; - break; - case FR30_OPERAND_U4C : - value = fields->f_u4c; - break; - case FR30_OPERAND_U8 : - value = fields->f_u8; - break; - case FR30_OPERAND_I8 : - value = fields->f_i8; - break; - case FR30_OPERAND_UDISP6 : - value = fields->f_udisp6; - break; - case FR30_OPERAND_DISP8 : - value = fields->f_disp8; - break; - case FR30_OPERAND_DISP9 : - value = fields->f_disp9; - break; - case FR30_OPERAND_DISP10 : - value = fields->f_disp10; - break; - case FR30_OPERAND_S10 : - value = fields->f_s10; - break; - case FR30_OPERAND_U10 : - value = fields->f_u10; - break; - case FR30_OPERAND_I32 : - value = fields->f_i32; - break; - case FR30_OPERAND_M4 : - value = fields->f_m4; - break; - case FR30_OPERAND_I20 : - value = fields->f_i20; - break; - case FR30_OPERAND_DIR8 : - value = fields->f_dir8; - break; - case FR30_OPERAND_DIR9 : - value = fields->f_dir9; - break; - case FR30_OPERAND_DIR10 : - value = fields->f_dir10; - break; - case FR30_OPERAND_LABEL9 : - value = fields->f_rel9; - break; - case FR30_OPERAND_LABEL12 : - value = fields->f_rel12; - break; - case FR30_OPERAND_REGLIST_LOW_LD : - value = fields->f_reglist_low_ld; - break; - case FR30_OPERAND_REGLIST_HI_LD : - value = fields->f_reglist_hi_ld; - break; - case FR30_OPERAND_REGLIST_LOW_ST : - value = fields->f_reglist_low_st; - break; - case FR30_OPERAND_REGLIST_HI_ST : - value = fields->f_reglist_hi_st; - break; - case FR30_OPERAND_CC : - value = fields->f_cc; - break; - case FR30_OPERAND_CCC : - value = fields->f_ccc; - break; - - default : - /* xgettext:c-format */ - fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), - opindex); - abort (); - } - - return value; -} - -bfd_vma -fr30_cgen_get_vma_operand (opindex, fields) - int opindex; - const CGEN_FIELDS * fields; -{ - bfd_vma value; - - switch (opindex) - { - case FR30_OPERAND_RI : - value = fields->f_Ri; - break; - case FR30_OPERAND_RJ : - value = fields->f_Rj; - break; - case FR30_OPERAND_RIC : - value = fields->f_Ric; - break; - case FR30_OPERAND_RJC : - value = fields->f_Rjc; - break; - case FR30_OPERAND_CRI : - value = fields->f_CRi; - break; - case FR30_OPERAND_CRJ : - value = fields->f_CRj; - break; - case FR30_OPERAND_RS1 : - value = fields->f_Rs1; - break; - case FR30_OPERAND_RS2 : - value = fields->f_Rs2; - break; - case FR30_OPERAND_R13 : - value = fields->f_nil; - break; - case FR30_OPERAND_R14 : - value = fields->f_nil; - break; - case FR30_OPERAND_R15 : - value = fields->f_nil; - break; - case FR30_OPERAND_PS : - value = fields->f_nil; - break; - case FR30_OPERAND_U4 : - value = fields->f_u4; - break; - case FR30_OPERAND_U4C : - value = fields->f_u4c; - break; - case FR30_OPERAND_U8 : - value = fields->f_u8; - break; - case FR30_OPERAND_I8 : - value = fields->f_i8; - break; - case FR30_OPERAND_UDISP6 : - value = fields->f_udisp6; - break; - case FR30_OPERAND_DISP8 : - value = fields->f_disp8; - break; - case FR30_OPERAND_DISP9 : - value = fields->f_disp9; - break; - case FR30_OPERAND_DISP10 : - value = fields->f_disp10; - break; - case FR30_OPERAND_S10 : - value = fields->f_s10; - break; - case FR30_OPERAND_U10 : - value = fields->f_u10; - break; - case FR30_OPERAND_I32 : - value = fields->f_i32; - break; - case FR30_OPERAND_M4 : - value = fields->f_m4; - break; - case FR30_OPERAND_I20 : - value = fields->f_i20; - break; - case FR30_OPERAND_DIR8 : - value = fields->f_dir8; - break; - case FR30_OPERAND_DIR9 : - value = fields->f_dir9; - break; - case FR30_OPERAND_DIR10 : - value = fields->f_dir10; - break; - case FR30_OPERAND_LABEL9 : - value = fields->f_rel9; - break; - case FR30_OPERAND_LABEL12 : - value = fields->f_rel12; - break; - case FR30_OPERAND_REGLIST_LOW_LD : - value = fields->f_reglist_low_ld; - break; - case FR30_OPERAND_REGLIST_HI_LD : - value = fields->f_reglist_hi_ld; - break; - case FR30_OPERAND_REGLIST_LOW_ST : - value = fields->f_reglist_low_st; - break; - case FR30_OPERAND_REGLIST_HI_ST : - value = fields->f_reglist_hi_st; - break; - case FR30_OPERAND_CC : - value = fields->f_cc; - break; - case FR30_OPERAND_CCC : - value = fields->f_ccc; - break; - - default : - /* xgettext:c-format */ - fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), - opindex); - abort (); - } - - return value; -} - -/* Stuffing values in cgen_fields is handled by a collection of functions. - They are distinguished by the type of the VALUE argument they accept. - TODO: floating point, inlining support, remove cases where argument type - not appropriate. */ - -void -fr30_cgen_set_int_operand (opindex, fields, value) - int opindex; - CGEN_FIELDS * fields; - int value; -{ - switch (opindex) - { - case FR30_OPERAND_RI : - fields->f_Ri = value; - break; - case FR30_OPERAND_RJ : - fields->f_Rj = value; - break; - case FR30_OPERAND_RIC : - fields->f_Ric = value; - break; - case FR30_OPERAND_RJC : - fields->f_Rjc = value; - break; - case FR30_OPERAND_CRI : - fields->f_CRi = value; - break; - case FR30_OPERAND_CRJ : - fields->f_CRj = value; - break; - case FR30_OPERAND_RS1 : - fields->f_Rs1 = value; - break; - case FR30_OPERAND_RS2 : - fields->f_Rs2 = value; - break; - case FR30_OPERAND_R13 : - fields->f_nil = value; - break; - case FR30_OPERAND_R14 : - fields->f_nil = value; - break; - case FR30_OPERAND_R15 : - fields->f_nil = value; - break; - case FR30_OPERAND_PS : - fields->f_nil = value; - break; - case FR30_OPERAND_U4 : - fields->f_u4 = value; - break; - case FR30_OPERAND_U4C : - fields->f_u4c = value; - break; - case FR30_OPERAND_U8 : - fields->f_u8 = value; - break; - case FR30_OPERAND_I8 : - fields->f_i8 = value; - break; - case FR30_OPERAND_UDISP6 : - fields->f_udisp6 = value; - break; - case FR30_OPERAND_DISP8 : - fields->f_disp8 = value; - break; - case FR30_OPERAND_DISP9 : - fields->f_disp9 = value; - break; - case FR30_OPERAND_DISP10 : - fields->f_disp10 = value; - break; - case FR30_OPERAND_S10 : - fields->f_s10 = value; - break; - case FR30_OPERAND_U10 : - fields->f_u10 = value; - break; - case FR30_OPERAND_I32 : - fields->f_i32 = value; - break; - case FR30_OPERAND_M4 : - fields->f_m4 = value; - break; - case FR30_OPERAND_I20 : - fields->f_i20 = value; - break; - case FR30_OPERAND_DIR8 : - fields->f_dir8 = value; - break; - case FR30_OPERAND_DIR9 : - fields->f_dir9 = value; - break; - case FR30_OPERAND_DIR10 : - fields->f_dir10 = value; - break; - case FR30_OPERAND_LABEL9 : - fields->f_rel9 = value; - break; - case FR30_OPERAND_LABEL12 : - fields->f_rel12 = value; - break; - case FR30_OPERAND_REGLIST_LOW_LD : - fields->f_reglist_low_ld = value; - break; - case FR30_OPERAND_REGLIST_HI_LD : - fields->f_reglist_hi_ld = value; - break; - case FR30_OPERAND_REGLIST_LOW_ST : - fields->f_reglist_low_st = value; - break; - case FR30_OPERAND_REGLIST_HI_ST : - fields->f_reglist_hi_st = value; - break; - case FR30_OPERAND_CC : - fields->f_cc = value; - break; - case FR30_OPERAND_CCC : - fields->f_ccc = value; - break; - - default : - /* xgettext:c-format */ - fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), - opindex); - abort (); - } -} - -void -fr30_cgen_set_vma_operand (opindex, fields, value) - int opindex; - CGEN_FIELDS * fields; - bfd_vma value; -{ - switch (opindex) - { - case FR30_OPERAND_RI : - fields->f_Ri = value; - break; - case FR30_OPERAND_RJ : - fields->f_Rj = value; - break; - case FR30_OPERAND_RIC : - fields->f_Ric = value; - break; - case FR30_OPERAND_RJC : - fields->f_Rjc = value; - break; - case FR30_OPERAND_CRI : - fields->f_CRi = value; - break; - case FR30_OPERAND_CRJ : - fields->f_CRj = value; - break; - case FR30_OPERAND_RS1 : - fields->f_Rs1 = value; - break; - case FR30_OPERAND_RS2 : - fields->f_Rs2 = value; - break; - case FR30_OPERAND_R13 : - fields->f_nil = value; - break; - case FR30_OPERAND_R14 : - fields->f_nil = value; - break; - case FR30_OPERAND_R15 : - fields->f_nil = value; - break; - case FR30_OPERAND_PS : - fields->f_nil = value; - break; - case FR30_OPERAND_U4 : - fields->f_u4 = value; - break; - case FR30_OPERAND_U4C : - fields->f_u4c = value; - break; - case FR30_OPERAND_U8 : - fields->f_u8 = value; - break; - case FR30_OPERAND_I8 : - fields->f_i8 = value; - break; - case FR30_OPERAND_UDISP6 : - fields->f_udisp6 = value; - break; - case FR30_OPERAND_DISP8 : - fields->f_disp8 = value; - break; - case FR30_OPERAND_DISP9 : - fields->f_disp9 = value; - break; - case FR30_OPERAND_DISP10 : - fields->f_disp10 = value; - break; - case FR30_OPERAND_S10 : - fields->f_s10 = value; - break; - case FR30_OPERAND_U10 : - fields->f_u10 = value; - break; - case FR30_OPERAND_I32 : - fields->f_i32 = value; - break; - case FR30_OPERAND_M4 : - fields->f_m4 = value; - break; - case FR30_OPERAND_I20 : - fields->f_i20 = value; - break; - case FR30_OPERAND_DIR8 : - fields->f_dir8 = value; - break; - case FR30_OPERAND_DIR9 : - fields->f_dir9 = value; - break; - case FR30_OPERAND_DIR10 : - fields->f_dir10 = value; - break; - case FR30_OPERAND_LABEL9 : - fields->f_rel9 = value; - break; - case FR30_OPERAND_LABEL12 : - fields->f_rel12 = value; - break; - case FR30_OPERAND_REGLIST_LOW_LD : - fields->f_reglist_low_ld = value; - break; - case FR30_OPERAND_REGLIST_HI_LD : - fields->f_reglist_hi_ld = value; - break; - case FR30_OPERAND_REGLIST_LOW_ST : - fields->f_reglist_low_st = value; - break; - case FR30_OPERAND_REGLIST_HI_ST : - fields->f_reglist_hi_st = value; - break; - case FR30_OPERAND_CC : - fields->f_cc = value; - break; - case FR30_OPERAND_CCC : - fields->f_ccc = value; - break; - - default : - /* xgettext:c-format */ - fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), - opindex); - abort (); - } -} - diff --git a/opcodes/fr30-opc.h b/opcodes/fr30-opc.h deleted file mode 100644 index 988a784d9d0..00000000000 --- a/opcodes/fr30-opc.h +++ /dev/null @@ -1,396 +0,0 @@ -/* Instruction description for fr30. - -THIS FILE IS MACHINE GENERATED WITH CGEN. - -Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. - -This file is part of the GNU Binutils and/or GDB, the GNU debugger. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License along -with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - -*/ - -#ifndef FR30_OPC_H -#define FR30_OPC_H - -#define CGEN_ARCH fr30 - -/* Given symbol S, return fr30_cgen_<S>. */ -#define CGEN_SYM(s) CONCAT3 (fr30,_cgen_,s) - -/* Selected cpu families. */ -#define HAVE_CPU_FR30BF - -#define CGEN_INSN_LSB0_P 0 -#define CGEN_WORD_BITSIZE 32 -#define CGEN_DEFAULT_INSN_BITSIZE 16 -#define CGEN_BASE_INSN_BITSIZE 16 -#define CGEN_MIN_INSN_BITSIZE 16 -#define CGEN_MAX_INSN_BITSIZE 48 -#define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8) -#define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8) -#define CGEN_MIN_INSN_SIZE (CGEN_MIN_INSN_BITSIZE / 8) -#define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8) -#define CGEN_INT_INSN_P 0 - -/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */ - -/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. - e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands - we can't hash on everything up to the space. */ -#define CGEN_MNEMONIC_OPERANDS -/* Maximum number of operands any insn or macro-insn has. */ -#define CGEN_MAX_INSN_OPERANDS 16 - -/* Maximum number of fields in an instruction. */ -#define CGEN_MAX_IFMT_OPERANDS 7 - -/* Enums. */ - -/* Enum declaration for insn op1 enums. */ -typedef enum insn_op1 { - OP1_0, OP1_1, OP1_2, OP1_3 - , OP1_4, OP1_5, OP1_6, OP1_7 - , OP1_8, OP1_9, OP1_A, OP1_B - , OP1_C, OP1_D, OP1_E, OP1_F -} INSN_OP1; - -/* Enum declaration for insn op2 enums. */ -typedef enum insn_op2 { - OP2_0, OP2_1, OP2_2, OP2_3 - , OP2_4, OP2_5, OP2_6, OP2_7 - , OP2_8, OP2_9, OP2_A, OP2_B - , OP2_C, OP2_D, OP2_E, OP2_F -} INSN_OP2; - -/* Enum declaration for insn op3 enums. */ -typedef enum insn_op3 { - OP3_0, OP3_1, OP3_2, OP3_3 - , OP3_4, OP3_5, OP3_6, OP3_7 - , OP3_8, OP3_9, OP3_A, OP3_B - , OP3_C, OP3_D, OP3_E, OP3_F -} INSN_OP3; - -/* Enum declaration for insn op4 enums. */ -typedef enum insn_op4 { - OP4_0 -} INSN_OP4; - -/* Enum declaration for insn op5 enums. */ -typedef enum insn_op5 { - OP5_0, OP5_1 -} INSN_OP5; - -/* Enum declaration for insn cc enums. */ -typedef enum insn_cc { - CC_RA, CC_NO, CC_EQ, CC_NE - , CC_C, CC_NC, CC_N, CC_P - , CC_V, CC_NV, CC_LT, CC_GE - , CC_LE, CC_GT, CC_LS, CC_HI -} INSN_CC; - -/* Enum declaration for general registers. */ -typedef enum h_gr { - H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3 - , H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7 - , H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11 - , H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15 - , H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15 -} H_GR; - -/* Enum declaration for coprocessor registers. */ -typedef enum h_cr { - H_CR_CR0, H_CR_CR1, H_CR_CR2, H_CR_CR3 - , H_CR_CR4, H_CR_CR5, H_CR_CR6, H_CR_CR7 - , H_CR_CR8, H_CR_CR9, H_CR_CR10, H_CR_CR11 - , H_CR_CR12, H_CR_CR13, H_CR_CR14, H_CR_CR15 -} H_CR; - -/* Enum declaration for dedicated registers. */ -typedef enum h_dr { - H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP - , H_DR_MDH, H_DR_MDL -} H_DR; - -/* Enum declaration for program status. */ -typedef enum h_ps { - H_PS_PS -} H_PS; - -/* Enum declaration for General Register 13 explicitely required. */ -typedef enum h_r13 { - H_R13_R13 -} H_R13; - -/* Enum declaration for General Register 14 explicitely required. */ -typedef enum h_r14 { - H_R14_R14 -} H_R14; - -/* Enum declaration for General Register 15 explicitely required. */ -typedef enum h_r15 { - H_R15_R15 -} H_R15; - -/* Attributes. */ - -/* Enum declaration for machine type selection. */ -typedef enum mach_attr { - MACH_BASE, MACH_FR30, MACH_MAX -} MACH_ATTR; - -/* Number of architecture variants. */ -#define MAX_MACHS ((int) MACH_MAX) - -/* Ifield attribute indices. */ - -/* Enum declaration for cgen_ifld attrs. */ -typedef enum cgen_ifld_attr { - CGEN_IFLD_MACH, CGEN_IFLD_VIRTUAL, CGEN_IFLD_UNSIGNED, CGEN_IFLD_PCREL_ADDR - , CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED, CGEN_IFLD_SIGN_OPT -} CGEN_IFLD_ATTR; - -/* Number of non-boolean elements in cgen_ifld. */ -#define CGEN_IFLD_NBOOL_ATTRS ((int) CGEN_IFLD_VIRTUAL) - -/* Enum declaration for fr30 ifield types. */ -typedef enum ifield_type { - FR30_F_NIL, FR30_F_OP1, FR30_F_OP2, FR30_F_OP3 - , FR30_F_OP4, FR30_F_OP5, FR30_F_CC, FR30_F_CCC - , FR30_F_RJ, FR30_F_RI, FR30_F_RS1, FR30_F_RS2 - , FR30_F_RJC, FR30_F_RIC, FR30_F_CRJ, FR30_F_CRI - , FR30_F_U4, FR30_F_U4C, FR30_F_I4, FR30_F_M4 - , FR30_F_U8, FR30_F_I8, FR30_F_I20_4, FR30_F_I20_16 - , FR30_F_I20, FR30_F_I32, FR30_F_UDISP6, FR30_F_DISP8 - , FR30_F_DISP9, FR30_F_DISP10, FR30_F_S10, FR30_F_U10 - , FR30_F_REL9, FR30_F_DIR8, FR30_F_DIR9, FR30_F_DIR10 - , FR30_F_REL12, FR30_F_REGLIST_HI_ST, FR30_F_REGLIST_LOW_ST, FR30_F_REGLIST_HI_LD - , FR30_F_REGLIST_LOW_LD, FR30_F_MAX -} IFIELD_TYPE; - -#define MAX_IFLD ((int) FR30_F_MAX) - -/* Hardware attribute indices. */ - -/* Enum declaration for cgen_hw attrs. */ -typedef enum cgen_hw_attr { - CGEN_HW_MACH, CGEN_HW_VIRTUAL, CGEN_HW_UNSIGNED, CGEN_HW_SIGNED - , CGEN_HW_CACHE_ADDR, CGEN_HW_FUN_ACCESS, CGEN_HW_PC, CGEN_HW_PROFILE -} CGEN_HW_ATTR; - -/* Number of non-boolean elements in cgen_hw. */ -#define CGEN_HW_NBOOL_ATTRS ((int) CGEN_HW_VIRTUAL) - -/* Enum declaration for fr30 hardware types. */ -typedef enum hw_type { - HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT - , HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_CR - , HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14 - , HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT - , HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_H_TBIT - , HW_H_D0BIT, HW_H_D1BIT, HW_H_CCR, HW_H_SCR - , HW_H_ILM, HW_MAX -} HW_TYPE; - -#define MAX_HW ((int) HW_MAX) - -/* Operand attribute indices. */ - -/* Enum declaration for cgen_operand attrs. */ -typedef enum cgen_operand_attr { - CGEN_OPERAND_MACH, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_UNSIGNED, CGEN_OPERAND_PCREL_ADDR - , CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX - , CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_HASH_PREFIX -} CGEN_OPERAND_ATTR; - -/* Number of non-boolean elements in cgen_operand. */ -#define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_VIRTUAL) - -/* Enum declaration for fr30 operand types. */ -typedef enum cgen_operand_type { - FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC - , FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ, FR30_OPERAND_RS1 - , FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15 - , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C, FR30_OPERAND_U8 - , FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8, FR30_OPERAND_DISP9 - , FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_I32 - , FR30_OPERAND_M4, FR30_OPERAND_I20, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9 - , FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW_LD - , FR30_OPERAND_REGLIST_HI_LD, FR30_OPERAND_REGLIST_LOW_ST, FR30_OPERAND_REGLIST_HI_ST, FR30_OPERAND_CC - , FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT, FR30_OPERAND_ZBIT - , FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT, FR30_OPERAND_TBIT - , FR30_OPERAND_D0BIT, FR30_OPERAND_D1BIT, FR30_OPERAND_CCR, FR30_OPERAND_SCR - , FR30_OPERAND_ILM, FR30_OPERAND_MAX -} CGEN_OPERAND_TYPE; - -/* Number of operands types. */ -#define MAX_OPERANDS ((int) FR30_OPERAND_MAX) - -/* Maximum number of operands referenced by any insn. */ -#define MAX_OPERAND_INSTANCES 12 - -/* Insn attribute indices. */ - -/* Enum declaration for cgen_insn attrs. */ -typedef enum cgen_insn_attr { - CGEN_INSN_MACH, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI - , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX - , CGEN_INSN_ALIAS, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT -} CGEN_INSN_ATTR; - -/* Number of non-boolean elements in cgen_insn. */ -#define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_VIRTUAL) - -/* Enum declaration for fr30 instruction types. */ -typedef enum cgen_insn_type { - FR30_INSN_INVALID, FR30_INSN_ADD, FR30_INSN_ADDI, FR30_INSN_ADD2 - , FR30_INSN_ADDC, FR30_INSN_ADDN, FR30_INSN_ADDNI, FR30_INSN_ADDN2 - , FR30_INSN_SUB, FR30_INSN_SUBC, FR30_INSN_SUBN, FR30_INSN_CMP - , FR30_INSN_CMPI, FR30_INSN_CMP2, FR30_INSN_AND, FR30_INSN_OR - , FR30_INSN_EOR, FR30_INSN_ANDM, FR30_INSN_ANDH, FR30_INSN_ANDB - , FR30_INSN_ORM, FR30_INSN_ORH, FR30_INSN_ORB, FR30_INSN_EORM - , FR30_INSN_EORH, FR30_INSN_EORB, FR30_INSN_BANDL, FR30_INSN_BORL - , FR30_INSN_BEORL, FR30_INSN_BANDH, FR30_INSN_BORH, FR30_INSN_BEORH - , FR30_INSN_BTSTL, FR30_INSN_BTSTH, FR30_INSN_MUL, FR30_INSN_MULU - , FR30_INSN_MULH, FR30_INSN_MULUH, FR30_INSN_DIV0S, FR30_INSN_DIV0U - , FR30_INSN_DIV1, FR30_INSN_DIV2, FR30_INSN_DIV3, FR30_INSN_DIV4S - , FR30_INSN_LSL, FR30_INSN_LSLI, FR30_INSN_LSL2, FR30_INSN_LSR - , FR30_INSN_LSRI, FR30_INSN_LSR2, FR30_INSN_ASR, FR30_INSN_ASRI - , FR30_INSN_ASR2, FR30_INSN_LDI8, FR30_INSN_LDI20, FR30_INSN_LDI32 - , FR30_INSN_LD, FR30_INSN_LDUH, FR30_INSN_LDUB, FR30_INSN_LDR13 - , FR30_INSN_LDR13UH, FR30_INSN_LDR13UB, FR30_INSN_LDR14, FR30_INSN_LDR14UH - , FR30_INSN_LDR14UB, FR30_INSN_LDR15, FR30_INSN_LDR15GR, FR30_INSN_LDR15DR - , FR30_INSN_LDR15PS, FR30_INSN_ST, FR30_INSN_STH, FR30_INSN_STB - , FR30_INSN_STR13, FR30_INSN_STR13H, FR30_INSN_STR13B, FR30_INSN_STR14 - , FR30_INSN_STR14H, FR30_INSN_STR14B, FR30_INSN_STR15, FR30_INSN_STR15GR - , FR30_INSN_STR15DR, FR30_INSN_STR15PS, FR30_INSN_MOV, FR30_INSN_MOVDR - , FR30_INSN_MOVPS, FR30_INSN_MOV2DR, FR30_INSN_MOV2PS, FR30_INSN_JMP - , FR30_INSN_JMPD, FR30_INSN_CALLR, FR30_INSN_CALLRD, FR30_INSN_CALL - , FR30_INSN_CALLD, FR30_INSN_RET, FR30_INSN_RET_D, FR30_INSN_INT - , FR30_INSN_INTE, FR30_INSN_RETI, FR30_INSN_BRAD, FR30_INSN_BRA - , FR30_INSN_BNOD, FR30_INSN_BNO, FR30_INSN_BEQD, FR30_INSN_BEQ - , FR30_INSN_BNED, FR30_INSN_BNE, FR30_INSN_BCD, FR30_INSN_BC - , FR30_INSN_BNCD, FR30_INSN_BNC, FR30_INSN_BND, FR30_INSN_BN - , FR30_INSN_BPD, FR30_INSN_BP, FR30_INSN_BVD, FR30_INSN_BV - , FR30_INSN_BNVD, FR30_INSN_BNV, FR30_INSN_BLTD, FR30_INSN_BLT - , FR30_INSN_BGED, FR30_INSN_BGE, FR30_INSN_BLED, FR30_INSN_BLE - , FR30_INSN_BGTD, FR30_INSN_BGT, FR30_INSN_BLSD, FR30_INSN_BLS - , FR30_INSN_BHID, FR30_INSN_BHI, FR30_INSN_DMOVR13, FR30_INSN_DMOVR13H - , FR30_INSN_DMOVR13B, FR30_INSN_DMOVR13PI, FR30_INSN_DMOVR13PIH, FR30_INSN_DMOVR13PIB - , FR30_INSN_DMOVR15PI, FR30_INSN_DMOV2R13, FR30_INSN_DMOV2R13H, FR30_INSN_DMOV2R13B - , FR30_INSN_DMOV2R13PI, FR30_INSN_DMOV2R13PIH, FR30_INSN_DMOV2R13PIB, FR30_INSN_DMOV2R15PD - , FR30_INSN_LDRES, FR30_INSN_STRES, FR30_INSN_COPOP, FR30_INSN_COPLD - , FR30_INSN_COPST, FR30_INSN_COPSV, FR30_INSN_NOP, FR30_INSN_ANDCCR - , FR30_INSN_ORCCR, FR30_INSN_STILM, FR30_INSN_ADDSP, FR30_INSN_EXTSB - , FR30_INSN_EXTUB, FR30_INSN_EXTSH, FR30_INSN_EXTUH, FR30_INSN_LDM0 - , FR30_INSN_LDM1, FR30_INSN_STM0, FR30_INSN_STM1, FR30_INSN_ENTER - , FR30_INSN_LEAVE, FR30_INSN_XCHB, FR30_INSN_MAX -} CGEN_INSN_TYPE; - -/* Index of `invalid' insn place holder. */ -#define CGEN_INSN_INVALID FR30_INSN_INVALID -/* Total number of insns in table. */ -#define MAX_INSNS ((int) FR30_INSN_MAX) - -/* cgen.h uses things we just defined. */ -#include "opcode/cgen.h" - -/* This struct records data prior to insertion or after extraction. */ -struct cgen_fields -{ - long f_nil; - long f_op1; - long f_op2; - long f_op3; - long f_op4; - long f_op5; - long f_cc; - long f_ccc; - long f_Rj; - long f_Ri; - long f_Rs1; - long f_Rs2; - long f_Rjc; - long f_Ric; - long f_CRj; - long f_CRi; - long f_u4; - long f_u4c; - long f_i4; - long f_m4; - long f_u8; - long f_i8; - long f_i20_4; - long f_i20_16; - long f_i20; - long f_i32; - long f_udisp6; - long f_disp8; - long f_disp9; - long f_disp10; - long f_s10; - long f_u10; - long f_rel9; - long f_dir8; - long f_dir9; - long f_dir10; - long f_rel12; - long f_reglist_hi_st; - long f_reglist_low_st; - long f_reglist_hi_ld; - long f_reglist_low_ld; - int length; -}; - -/* Attributes. */ -extern const CGEN_ATTR_TABLE fr30_cgen_hw_attr_table[]; -extern const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[]; -extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[]; - -/* Hardware decls. */ - -extern CGEN_KEYWORD fr30_cgen_opval_h_gr; -extern CGEN_KEYWORD fr30_cgen_opval_h_cr; -extern CGEN_KEYWORD fr30_cgen_opval_h_dr; -extern CGEN_KEYWORD fr30_cgen_opval_h_ps; -extern CGEN_KEYWORD fr30_cgen_opval_h_r13; -extern CGEN_KEYWORD fr30_cgen_opval_h_r14; -extern CGEN_KEYWORD fr30_cgen_opval_h_r15; - -#define CGEN_INIT_PARSE(od) \ -{\ -} -#define CGEN_INIT_INSERT(od) \ -{\ -} -#define CGEN_INIT_EXTRACT(od) \ -{\ -} -#define CGEN_INIT_PRINT(od) \ -{\ -} - -/* -- opc.h */ - -/* ??? This can be improved upon. */ -#undef CGEN_DIS_HASH_SIZE -#define CGEN_DIS_HASH_SIZE 16 -#undef CGEN_DIS_HASH -#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 4) - -/* -- */ - - -#endif /* FR30_OPC_H */ diff --git a/opcodes/h8300-dis.c b/opcodes/h8300-dis.c deleted file mode 100644 index b3a9496d5c1..00000000000 --- a/opcodes/h8300-dis.c +++ /dev/null @@ -1,449 +0,0 @@ -/* Disassemble h8300 instructions. - Copyright (C) 1993 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#define DEFINE_TABLE - -#define h8_opcodes h8ops -#include "opcode/h8300.h" -#include "dis-asm.h" - - -/* Run through the opcodes and sort them into order to make them easy - to disassemble - */ -static void -bfd_h8_disassemble_init () -{ - unsigned int i; - - - struct h8_opcode *p; - - for (p = h8_opcodes; p->name; p++) - { - int n1 = 0; - int n2 = 0; - - if ((int) p->data.nib[0] < 16) - { - n1 = (int) p->data.nib[0]; - } - else - n1 = 0; - if ((int) p->data.nib[1] < 16) - { - n2 = (int) p->data.nib[1]; - } - else - n2 = 0; - - /* Just make sure there are an even number of nibbles in it, and - that the count is the same s the length */ - for (i = 0; p->data.nib[i] != E; i++) - /*EMPTY*/ ; - if (i & 1) - abort (); - p->length = i / 2; - } - -} - - -unsigned int -bfd_h8_disassemble (addr, info, mode) - bfd_vma addr; - disassemble_info *info; - int mode; -{ - /* Find the first entry in the table for this opcode */ - static CONST char *regnames[] = - { - "r0h", "r1h", "r2h", "r3h", "r4h", "r5h", "r6h", "r7h", - "r0l", "r1l", "r2l", "r3l", "r4l", "r5l", "r6l", "r7l"}; - - static CONST char *wregnames[] = - { - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", - "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" - }; - - static CONST char *lregnames[] = - { - "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7", - "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" - } - ; - - int rs = 0; - int rd = 0; - int rdisp = 0; - int abs = 0; - int bit = 0; - int plen = 0; - static boolean init = 0; - struct h8_opcode *q = h8_opcodes; - char CONST **pregnames = mode != 0 ? lregnames : wregnames; - int status; - int l; - - unsigned char data[20]; - void *stream = info->stream; - fprintf_ftype fprintf = info->fprintf_func; - - if (!init) - { - bfd_h8_disassemble_init (); - init = 1; - } - - status = info->read_memory_func(addr, data, 2, info); - if (status != 0) - { - info->memory_error_func(status, addr, info); - return -1; - } - for (l = 2; status == 0 && l < 10; l+=2) - { - status = info->read_memory_func(addr+l, data+l, 2, info); - } - - - - /* Find the exact opcode/arg combo */ - while (q->name) - { - op_type *nib; - unsigned int len = 0; - - nib = q->data.nib; - - while (1) - { - op_type looking_for = *nib; - int thisnib = data[len >> 1]; - - thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf); - - if (looking_for < 16 && looking_for >=0) - { - - if (looking_for != thisnib) - goto fail; - } - - else - { - - if ((int) looking_for & (int) B31) - { - if (! (((int) thisnib & 0x8) != 0)) - goto fail; - looking_for = (op_type) ((int) looking_for & ~(int) B31); - } - if ((int) looking_for & (int) B30) - { - if (!(((int) thisnib & 0x8) == 0)) - goto fail; - looking_for = (op_type) ((int) looking_for & ~(int) B30); - } - - if (looking_for & DBIT) - { - if ((looking_for & 5) != (thisnib &5)) goto fail; - abs = (thisnib & 0x8) ? 2 : 1; - } - - else if (looking_for & (REG | IND|INC|DEC)) - { - if (looking_for & SRC) - { - rs = thisnib; - } - else - { - rd = thisnib; - } - } - else if (looking_for & L_16) - { - abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1]; - plen = 16; - - } - else if(looking_for & ABSJMP) - { - abs = - (data[1] << 16) - | (data[2] << 8) - | (data[3]); - } - else if(looking_for & MEMIND) - { - abs = data[1]; - } - else if (looking_for & L_32) - { - int i = len >> 1; - abs = (data[i] << 24) - | (data[i + 1] << 16) - | (data[i + 2] << 8) - | (data[i+ 3]); - - plen =32; - - } - else if (looking_for & L_24) - { - int i = len >> 1; - abs = (data[i] << 16) | (data[i + 1] << 8)| (data[i+ - 2]); - plen =24; - } - else if (looking_for & IGNORE) - { - - } - else if (looking_for & DISPREG) - { - rdisp = thisnib; - } - else if (looking_for & KBIT) - { - switch (thisnib) - { - case 9: - abs = 4; - break; - case 8: - abs = 2; - break; - case 0: - abs = 1; - break; - default: - goto fail; - } - } - else if (looking_for & L_8) - { - plen = 8; - abs = data[len >> 1]; - } - else if (looking_for & L_3) - { - bit = thisnib & 0x7; - } - else if (looking_for & L_2) - { - plen = 2; - abs = thisnib & 0x3; - } - else if (looking_for == E) - { - - { - int i; - - for (i = 0; i < q->length; i++) - { - fprintf (stream, "%02x ", data[i]); - } - for (; i < 6; i++) - { - fprintf (stream, " "); - } - } - fprintf (stream, "%s\t", q->name); - - /* Gross. Disgusting. */ - if (strcmp (q->name, "ldm.l") == 0) - { - int count, high; - - count = (data[1] >> 4) & 0x3; - high = data[3] & 0x7; - - fprintf (stream, "@sp+,er%d-er%d", high - count, high); - return q->length; - } - - if (strcmp (q->name, "stm.l") == 0) - { - int count, low; - - count = (data[1] >> 4) & 0x3; - low = data[3] & 0x7; - - fprintf (stream, "er%d-er%d,@-sp", low, low + count); - return q->length; - } - - /* Fill in the args */ - { - op_type *args = q->args.nib; - int hadone = 0; - - - while (*args != E) - { - int x = *args; - if (hadone) - fprintf (stream, ","); - - - if (x & L_3) - { - fprintf (stream, "#0x%x", (unsigned) bit); - } - else if (x & (IMM|KBIT|DBIT)) - { - /* Bletch. For shal #2,er0 and friends. */ - if (*(args+1) & SRC_IN_DST) - abs = 2; - - fprintf (stream, "#0x%x", (unsigned) abs); - } - else if (x & REG) - { - int rn = (x & DST) ? rd : rs; - switch (x & SIZE) - { - case L_8: - fprintf (stream, "%s", regnames[rn]); - break; - case L_16: - fprintf (stream, "%s", wregnames[rn]); - break; - case L_P: - case L_32: - fprintf (stream, "%s", lregnames[rn]); - break; - - } - } - - else if (x & INC) - { - fprintf (stream, "@%s+", pregnames[rs]); - } - else if (x & DEC) - { - fprintf (stream, "@-%s", pregnames[rd]); - } - - else if (x & IND) - { - int rn = (x & DST) ? rd : rs; - fprintf (stream, "@%s", pregnames[rn]); - } - - else if (x & ABS8MEM) - { - fprintf (stream, "@0x%x:8", (unsigned) abs); - } - - else if (x & (ABS|ABSJMP)) - { - fprintf (stream, "@0x%x:%d", (unsigned) abs, plen); - } - - else if (x & MEMIND) - { - fprintf (stream, "@@%d (%x)", abs, abs); - } - - else if (x & PCREL) - { - if (x & L_16) - { - abs +=2; - fprintf (stream, ".%s%d (%x)", (short) abs > 0 ? "+" : "", (short) abs, - addr + (short) abs + 2); - } - else { - fprintf (stream, ".%s%d (%x)", (char) abs > 0 ? "+" : "", (char) abs, - addr + (char) abs + 2); - } - } - else if (x & DISP) - { - fprintf (stream, "@(0x%x:%d,%s)", abs,plen, pregnames[rdisp]); - } - - else if (x & CCR) - { - fprintf (stream, "ccr"); - } - else if (x & EXR) - { - fprintf (stream, "exr"); - } - - else - fprintf (stream, "Hmmmm %x", x); - hadone = 1; - args++; - } - } - return q->length; - } - - - else - { - fprintf (stream, "Dont understand %x \n", looking_for); - } - } - - len++; - nib++; - } - - fail: - q++; - } - - /* Fell of the end */ - fprintf (stream, "%02x %02x .word\tH'%x,H'%x", - data[0], data[1], - data[0], data[1]); - return 2; -} - -int -print_insn_h8300 (addr, info) -bfd_vma addr; -disassemble_info *info; -{ - return bfd_h8_disassemble (addr, info , 0); -} - -int -print_insn_h8300h (addr, info) -bfd_vma addr; -disassemble_info *info; -{ - return bfd_h8_disassemble (addr, info , 1); -} - -int -print_insn_h8300s (addr, info) -bfd_vma addr; -disassemble_info *info; -{ - return bfd_h8_disassemble (addr, info , 2); -} diff --git a/opcodes/h8500-dis.c b/opcodes/h8500-dis.c deleted file mode 100644 index 856e580d7ae..00000000000 --- a/opcodes/h8500-dis.c +++ /dev/null @@ -1,330 +0,0 @@ -/* Disassemble h8500 instructions. - Copyright (C) 1993 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ - -#include <stdio.h> - -#define DISASSEMBLER_TABLE -#define DEFINE_TABLE - -#include "h8500-opc.h" -#include "dis-asm.h" - -/* Maximum length of an instruction. */ -#define MAXLEN 8 - -#include <setjmp.h> - -struct private -{ - /* Points to first byte not fetched. */ - bfd_byte *max_fetched; - bfd_byte the_buffer[MAXLEN]; - bfd_vma insn_start; - jmp_buf bailout; -}; - -/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) - to ADDR (exclusive) are valid. Returns 1 for success, longjmps - on error. */ -#define FETCH_DATA(info, addr) \ - ((addr) <= ((struct private *)(info->private_data))->max_fetched \ - ? 1 : fetch_data ((info), (addr))) - -static int -fetch_data (info, addr) - struct disassemble_info *info; - bfd_byte *addr; -{ - int status; - struct private *priv = (struct private *)info->private_data; - bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); - - status = (*info->read_memory_func) (start, - priv->max_fetched, - addr - priv->max_fetched, - info); - if (status != 0) - { - (*info->memory_error_func) (status, start, info); - longjmp (priv->bailout); - } - else - priv->max_fetched = addr; - return 1; -} - -static char *crname[] = -{"sr", "ccr", "*", "br", "ep", "dp", "*", "tp"}; - -int -print_insn_h8500 (addr, info) - unsigned long addr; - disassemble_info *info; -{ - h8500_opcode_info *opcode; - void *stream = info->stream; - fprintf_ftype func = info->fprintf_func; - - struct private priv; - bfd_byte *buffer = priv.the_buffer; - - info->private_data = (PTR) &priv; - priv.max_fetched = priv.the_buffer; - priv.insn_start = addr; - if (setjmp (priv.bailout) != 0) - /* Error return. */ - return -1; - - /* Run down the table to find the one which matches */ - for (opcode = h8500_table; opcode->name; opcode++) - { - int byte; - int rn; - int rd; - int rs; - int disp; - int abs; - int imm; - int pcrel; - int qim; - int i; - int cr; - for (byte = 0; byte < opcode->length; byte++) - { - FETCH_DATA (info, buffer + byte + 1); - if ((buffer[byte] & opcode->bytes[byte].mask) - != (opcode->bytes[byte].contents)) - { - goto next; - } - else - { - /* extract any info parts */ - switch (opcode->bytes[byte].insert) - { - case 0: - case FP: - break; - default: - func (stream, "can't cope with insert %d\n", - opcode->bytes[byte].insert); - break; - case RN: - rn = buffer[byte] & 0x7; - break; - case RS: - rs = buffer[byte] & 0x7; - break; - case CRB: - cr = buffer[byte] & 0x7; - if (cr == 0) - goto next; - break; - case CRW: - cr = buffer[byte] & 0x7; - if (cr != 0) - goto next; - break; - case DISP16: - FETCH_DATA (info, buffer + byte + 2); - disp = (buffer[byte] << 8) | (buffer[byte + 1]); - break; - case FPIND_D8: - case DISP8: - disp = ((char) (buffer[byte])); - break; - case RD: - case RDIND: - rd = buffer[byte] & 0x7; - break; - case ABS24: - FETCH_DATA (info, buffer + byte + 3); - abs = - (buffer[byte] << 16) - | (buffer[byte + 1] << 8) - | (buffer[byte + 2]); - break; - case ABS16: - FETCH_DATA (info, buffer + byte + 2); - abs = (buffer[byte] << 8) | (buffer[byte + 1]); - break; - case ABS8: - abs = (buffer[byte]); - break; - case IMM16: - FETCH_DATA (info, buffer + byte + 2); - imm = (buffer[byte] << 8) | (buffer[byte + 1]); - break; - case IMM4: - imm = (buffer[byte]) & 0xf; - break; - case IMM8: - case RLIST: - imm = (buffer[byte]); - break; - case PCREL16: - FETCH_DATA (info, buffer + byte + 2); - pcrel = (buffer[byte] << 8) | (buffer[byte + 1]); - break; - case PCREL8: - pcrel = (buffer[byte]); - break; - case QIM: - switch (buffer[byte] & 0x7) - { - case 0: - qim = 1; - break; - case 1: - qim = 2; - break; - case 4: - qim = -1; - break; - case 5: - qim = -2; - break; - } - break; - - } - } - } - /* We get here when all the masks have passed so we can output the - operands*/ - FETCH_DATA (info, buffer + opcode->length); - for (i = 0; i < opcode->length; i++) - { - (func) (stream, "%02x ", buffer[i]); - } - for (; i < 6; i++) - { - (func) (stream, " "); - } - (func) (stream, "%s\t", opcode->name); - for (i = 0; i < opcode->nargs; i++) - { - if (i) - (func) (stream, ","); - switch (opcode->arg_type[i]) - { - case FP: - func (stream, "fp"); - break; - case RNIND_D16: - func (stream, "@(0x%x:16,r%d)", disp, rn); - break; - case RNIND_D8: - func (stream, "@(0x%x:8 (%d),r%d)", disp & 0xff, disp, rn); - break; - case RDIND_D16: - func (stream, "@(0x%x:16,r%d)", disp, rd); - break; - case RDIND_D8: - func (stream, "@(0x%x:8 (%d), r%d)", disp & 0xff, disp, rd); - break; - case FPIND_D8: - func (stream, "@(0x%x:8 (%d), fp)", disp & 0xff, disp, rn); - break; - case CRB: - case CRW: - func (stream, "%s", crname[cr]); - break; - case RN: - func (stream, "r%d", rn); - break; - case RD: - func (stream, "r%d", rd); - break; - case RS: - func (stream, "r%d", rs); - break; - case RNDEC: - func (stream, "@-r%d", rn); - break; - case RNINC: - func (stream, "@r%d+", rn); - break; - case RNIND: - func (stream, "@r%d", rn); - break; - case RDIND: - func (stream, "@r%d", rd); - break; - case SPINC: - func (stream, "@sp+"); - break; - case SPDEC: - func (stream, "@-sp"); - break; - case ABS24: - func (stream, "@0x%0x:24", abs); - break; - case ABS16: - func (stream, "@0x%0x:16", abs & 0xffff); - break; - case ABS8: - func (stream, "@0x%0x:8", abs & 0xff); - break; - case IMM16: - func (stream, "#0x%0x:16", imm & 0xffff); - break; - case RLIST: - { - int i; - int nc = 0; - func (stream, "("); - for (i = 0; i < 8; i++) - { - if (imm & (1 << i)) - { - if (nc) - func (stream, ","); - nc += 1; - } - func (stream, "r%d", i); - } - func (stream, ")"); - } - break; - case IMM8: - func (stream, "#0x%0x:8", imm & 0xff); - break; - case PCREL16: - func (stream, "0x%0x:16", (pcrel + addr + opcode->length) & 0xffff); - break; - case PCREL8: - func (stream, "#0x%0x:8", - ((char) pcrel + addr + opcode->length) & 0xffff); - break; - case QIM: - func (stream, "#%d:q", qim); - break; - case IMM4: - func (stream, "#%d:4", imm); - break; - } - } - return opcode->length; - next:; - } - - /* Couldn't understand anything */ - func (stream, "%02x\t\t*unknown*", buffer[0]); - return 1; - -} diff --git a/opcodes/h8500-opc.h b/opcodes/h8500-opc.h deleted file mode 100644 index 1323ed63ab3..00000000000 --- a/opcodes/h8500-opc.h +++ /dev/null @@ -1,3799 +0,0 @@ -typedef enum -{ - GR0,GR1,GR2,GR3,GR4,GR5,GR6,GR7, - GPR0, GPR1, GPR2, GPR3, GPR4, GPR5, GPR6, GPR7, - GCCR, GPC, - GSEGC, GSEGD, GSEGE, GSEGT,GLAST -} gdbreg_type; -#define O_XORC 1 -#define O_XOR 2 -#define O_XCH 3 -#define O_UNLK 4 -#define O_TST 5 -#define O_TRAPA 6 -#define O_TRAP_VS 7 -#define O_TAS 8 -#define O_SWAP 9 -#define O_SUBX 10 -#define O_SUBS 11 -#define O_SUB 12 -#define O_STM 13 -#define O_STC 14 -#define O_SLEEP 15 -#define O_SHLR 16 -#define O_SHLL 17 -#define O_SHAR 18 -#define O_SHAL 19 -#define O_SCB_NE 20 -#define O_SCB_F 21 -#define O_SCB_EQ 22 -#define O_RTS 23 -#define O_RTD 24 -#define O_ROTXR 25 -#define O_ROTXL 26 -#define O_ROTR 27 -#define O_ROTL 28 -#define O_PRTS 29 -#define O_PRTD 30 -#define O_PJSR 31 -#define O_PJMP 32 -#define O_ORC 33 -#define O_OR 34 -#define O_NOT 35 -#define O_NOP 36 -#define O_NEG 37 -#define O_MULXU 38 -#define O_MOVTPE 39 -#define O_MOVFPE 40 -#define O_MOV 41 -#define O_LINK 42 -#define O_LDM 43 -#define O_LDC 44 -#define O_JSR 45 -#define O_JMP 46 -#define O_EXTU 47 -#define O_EXTS 48 -#define O_DSUB 49 -#define O_DIVXU 50 -#define O_DAAD 51 -#define O_CMP 52 -#define O_CLR 53 -#define O_BVS 54 -#define O_BVC 55 -#define O_BTST 56 -#define O_BT 57 -#define O_BSR 58 -#define O_BSET 59 -#define O_BRN 60 -#define O_BRA 61 -#define O_BPT 62 -#define O_BPL 63 -#define O_BNOT 64 -#define O_BNE 65 -#define O_BMI 66 -#define O_BLT 67 -#define O_BLS 68 -#define O_BLO 69 -#define O_BLE 70 -#define O_BHS 71 -#define O_BHI 72 -#define O_BGT 73 -#define O_BGE 74 -#define O_BF 75 -#define O_BEQ 76 -#define O_BCS 77 -#define O_BCLR 78 -#define O_BCC 79 -#define O_ANDC 80 -#define O_AND 81 -#define O_ADDX 82 -#define O_ADDS 83 -#define O_ADD 84 -#define O_BYTE 128 -#define O_WORD 0x000 -#define O_UNSZ 0x000 -#define FPIND_D8 10 -#define RDIND_D16 11 -#define RDIND_D8 12 -#define SPDEC 13 -#define RDIND 14 -#define RN 15 -#define RNIND_D8 16 -#define RNIND_D16 17 -#define RNDEC 18 -#define RNINC 19 -#define RNIND 20 -#define SPINC 21 -#define ABS16 22 -#define ABS24 23 -#define PCREL16 24 -#define PCREL8 25 -#define ABS8 26 -#define CRB 27 -#define CR 28 -#define CRW 29 -#define DISP16 30 -#define DISP8 31 -#define FP 32 -#define IMM16 33 -#define IMM4 34 -#define IMM8 35 -#define RLIST 36 -#define QIM 37 -#define RD 38 -#define RS 39 -#define SP 40 -typedef enum { AC_BAD, AC_EI, AC_RI, AC_D, AC_,AC_ERR, AC_X,AC_B, AC_EE,AC_RR,AC_IE, - AC_RE,AC_E, AC_I, AC_ER,AC_IRR, AC_IR, AC_RER, AC_ERE,AC_EIE, } addr_class_type; -typedef struct { - short int idx; - char flags,src1,src2,dst; - unsigned char flavor; - char *name; - int nargs; - int arg_type[2]; - int length; - struct { unsigned char contents;unsigned char mask; char insert; } bytes[6]; -} h8500_opcode_info; -h8500_opcode_info h8500_table[] -#ifdef ASSEMBLER_TABLE -#ifdef DEFINE_TABLE -={ -{1,'s','E','C','C',O_XORC|O_WORD,"xorc.w",2,{IMM16,CRW},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x68,0xf8,CRW }}}, -{2,'s','E','C','C',O_XORC|O_BYTE,"xorc.b",2,{IMM8,CRB},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x68,0xf8,CRB }}}, -{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x60,0xf8,RD }}}, -{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x60,0xf8,RD }}}, -{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x60,0xf8,RD }}}, -{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x60,0xf8,RD }}}, -{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x60,0xf8,RD }}}, -{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x60,0xf8,RD }}}, -{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x60,0xf8,RD }}}, -{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x60,0xf8,RD }}}, -{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x60,0xf8,RD }}}, -{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x60,0xf8,RD }}}, -{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x60,0xf8,RD }}}, -{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x60,0xf8,RD }}}, -{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x60,0xf8,RD }}}, -{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{IMM8,RD},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x60,0xf8,RD }}}, -{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{ABS8,RD},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x60,0xf8,RD }}}, -{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x60,0xf8,RD }}}, -{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{ABS16,RD},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x60,0xf8,RD }}}, -{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x60,0xf8,RD }}}, -{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x60,0xf8,RD }}}, -{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x60,0xf8,RD }}}, -{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x60,0xf8,RD }}}, -{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x60,0xf8,RD }}}, -{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x60,0xf8,RD }}}, -{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x60,0xf8,RD }}}, -{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x60,0xf8,RD }}}, -{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x60,0xf8,RD }}}, -{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x60,0xf8,RD }}}, -{6,'-','X','!','!',O_XCH|O_WORD,"xch.w",2,{RS,RD},2, {{0xa8,0xf8,RS },{0x90,0xf8,RD }}}, -{7,'-','X','!','!',O_XCH|O_UNSZ,"xch",2,{RS,RD},2, {{0xa8,0xf8,RS },{0x90,0xf8,RD }}}, -{8,'-','B','!','!',O_UNLK|O_UNSZ,"unlk",1,{FP,0},1, {{0x0f,0xff, }}}, -{9,'m','E','!','!',O_TST|O_WORD,"tst.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x16,0xff, }}}, -{9,'m','E','!','!',O_TST|O_WORD,"tst.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x16,0xff, }}}, -{9,'m','E','!','!',O_TST|O_WORD,"tst.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x16,0xff, }}}, -{9,'m','E','!','!',O_TST|O_WORD,"tst.w",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x16,0xff, }}}, -{9,'m','E','!','!',O_TST|O_WORD,"tst.w",1,{ABS8,0},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x16,0xff, }}}, -{9,'m','E','!','!',O_TST|O_WORD,"tst.w",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x16,0xff, }}}, -{9,'m','E','!','!',O_TST|O_WORD,"tst.w",1,{ABS16,0},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x16,0xff, }}}, -{9,'m','E','!','!',O_TST|O_WORD,"tst.w",1,{IMM16,0},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x16,0xff, }}}, -{9,'m','E','!','!',O_TST|O_WORD,"tst.w",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x16,0xff, }}}, -{10,'m','E','!','!',O_TST|O_BYTE,"tst.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x16,0xff, }}}, -{10,'m','E','!','!',O_TST|O_BYTE,"tst.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x16,0xff, }}}, -{10,'m','E','!','!',O_TST|O_BYTE,"tst.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x16,0xff, }}}, -{10,'m','E','!','!',O_TST|O_BYTE,"tst.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x16,0xff, }}}, -{10,'m','E','!','!',O_TST|O_BYTE,"tst.b",1,{IMM8,0},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x16,0xff, }}}, -{10,'m','E','!','!',O_TST|O_BYTE,"tst.b",1,{ABS8,0},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x16,0xff, }}}, -{10,'m','E','!','!',O_TST|O_BYTE,"tst.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x16,0xff, }}}, -{10,'m','E','!','!',O_TST|O_BYTE,"tst.b",1,{ABS16,0},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x16,0xff, }}}, -{10,'m','E','!','!',O_TST|O_BYTE,"tst.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x16,0xff, }}}, -{11,'m','E','!','!',O_TST|O_UNSZ,"tst",1,{RN,0},2, {{0xa8,0xf8,RN },{0x16,0xff, }}}, -{11,'m','E','!','!',O_TST|O_UNSZ,"tst",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x16,0xff, }}}, -{11,'m','E','!','!',O_TST|O_UNSZ,"tst",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x16,0xff, }}}, -{11,'m','E','!','!',O_TST|O_UNSZ,"tst",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x16,0xff, }}}, -{11,'m','E','!','!',O_TST|O_UNSZ,"tst",1,{ABS8,0},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x16,0xff, }}}, -{11,'m','E','!','!',O_TST|O_UNSZ,"tst",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x16,0xff, }}}, -{11,'m','E','!','!',O_TST|O_UNSZ,"tst",1,{IMM16,0},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x16,0xff, }}}, -{11,'m','E','!','!',O_TST|O_UNSZ,"tst",1,{ABS16,0},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x16,0xff, }}}, -{11,'m','E','!','!',O_TST|O_UNSZ,"tst",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x16,0xff, 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-{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{ABS8,0},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x15,0xff, }}}, -{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x15,0xff, }}}, -{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{ABS16,0},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x15,0xff, }}}, -{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{IMM16,0},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x15,0xff, }}}, -{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x15,0xff, }}}, -{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x15,0xff, }}}, -{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x15,0xff, }}}, -{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x15,0xff, }}}, -{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x15,0xff, }}}, -{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{IMM8,0},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x15,0xff, }}}, -{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{ABS8,0},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x15,0xff, }}}, -{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x15,0xff, }}}, -{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{ABS16,0},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x15,0xff, }}}, -{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x15,0xff, }}}, -{73,'m','E','!','E',O_NOT|O_UNSZ,"not",1,{RN,0},2, {{0xa8,0xf8,RN },{0x15,0xff, }}}, -{73,'m','E','!','E',O_NOT|O_UNSZ,"not",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x15,0xff, }}}, -{73,'m','E','!','E',O_NOT|O_UNSZ,"not",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x15,0xff, }}}, -{73,'m','E','!','E',O_NOT|O_UNSZ,"not",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x15,0xff, }}}, -{73,'m','E','!','E',O_NOT|O_UNSZ,"not",1,{ABS8,0},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x15,0xff, }}}, -{73,'m','E','!','E',O_NOT|O_UNSZ,"not",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x15,0xff, }}}, -{73,'m','E','!','E',O_NOT|O_UNSZ,"not",1,{ABS16,0},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x15,0xff, }}}, -{73,'m','E','!','E',O_NOT|O_UNSZ,"not",1,{IMM16,0},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x15,0xff, }}}, -{73,'m','E','!','E',O_NOT|O_UNSZ,"not",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x15,0xff, }}}, -{74,'-','!','!','!',O_NOP|O_UNSZ,"nop",0,{0,0},1, {{0x00,0xff, }}}, -{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x14,0xff, }}}, -{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x14,0xff, }}}, -{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x14,0xff, }}}, -{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x14,0xff, }}}, -{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{ABS8,0},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x14,0xff, }}}, -{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x14,0xff, }}}, -{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{ABS16,0},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x14,0xff, }}}, -{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{IMM16,0},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x14,0xff, }}}, -{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x14,0xff, }}}, -{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x14,0xff, }}}, -{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x14,0xff, }}}, -{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x14,0xff, }}}, -{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x14,0xff, }}}, -{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{IMM8,0},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x14,0xff, }}}, -{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{ABS8,0},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x14,0xff, }}}, -{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x14,0xff, }}}, -{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{ABS16,0},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x14,0xff, }}}, -{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x14,0xff, }}}, -{77,'a','E','!','E',O_NEG|O_UNSZ,"neg",1,{RN,0},2, {{0xa8,0xf8,RN },{0x14,0xff, }}}, -{77,'a','E','!','E',O_NEG|O_UNSZ,"neg",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x14,0xff, }}}, -{77,'a','E','!','E',O_NEG|O_UNSZ,"neg",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x14,0xff, }}}, -{77,'a','E','!','E',O_NEG|O_UNSZ,"neg",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x14,0xff, }}}, -{77,'a','E','!','E',O_NEG|O_UNSZ,"neg",1,{ABS8,0},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x14,0xff, }}}, -{77,'a','E','!','E',O_NEG|O_UNSZ,"neg",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x14,0xff, }}}, -{77,'a','E','!','E',O_NEG|O_UNSZ,"neg",1,{ABS16,0},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x14,0xff, }}}, -{77,'a','E','!','E',O_NEG|O_UNSZ,"neg",1,{IMM16,0},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x14,0xff, }}}, -{77,'a','E','!','E',O_NEG|O_UNSZ,"neg",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x14,0xff, }}}, -{78,'s','E','!','D',O_MULXU|O_WORD,"mulxu.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0xa8,0xf8,RD }}}, -{78,'s','E','!','D',O_MULXU|O_WORD,"mulxu.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0xa8,0xf8,RD }}}, -{78,'s','E','!','D',O_MULXU|O_WORD,"mulxu.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0xa8,0xf8,RD }}}, -{78,'s','E','!','D',O_MULXU|O_WORD,"mulxu.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0xa8,0xf8,RD }}}, -{78,'s','E','!','D',O_MULXU|O_WORD,"mulxu.w",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0xa8,0xf8,RD }}}, -{78,'s','E','!','D',O_MULXU|O_WORD,"mulxu.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0xa8,0xf8,RD }}}, -{78,'s','E','!','D',O_MULXU|O_WORD,"mulxu.w",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0xa8,0xf8,RD }}}, -{78,'s','E','!','D',O_MULXU|O_WORD,"mulxu.w",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0xa8,0xf8,RD }}}, -{78,'s','E','!','D',O_MULXU|O_WORD,"mulxu.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0xa8,0xf8,RD }}}, -{79,'s','E','!','D',O_MULXU|O_BYTE,"mulxu.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0xa8,0xf8,RD }}}, -{79,'s','E','!','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0xa8,0xf8,RD }}}, -{79,'s','E','!','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0xa8,0xf8,RD }}}, -{79,'s','E','!','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0xa8,0xf8,RD }}}, -{79,'s','E','!','D',O_MULXU|O_BYTE,"mulxu.b",2,{IMM8,RD},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0xa8,0xf8,RD }}}, -{79,'s','E','!','D',O_MULXU|O_BYTE,"mulxu.b",2,{ABS8,RD},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0xa8,0xf8,RD }}}, -{79,'s','E','!','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0xa8,0xf8,RD }}}, -{79,'s','E','!','D',O_MULXU|O_BYTE,"mulxu.b",2,{ABS16,RD},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0xa8,0xf8,RD }}}, -{79,'s','E','!','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0xa8,0xf8,RD }}}, -{80,'s','E','!','D',O_MULXU|O_UNSZ,"mulxu",2,{RN,RD},2, {{0xa8,0xf8,RN },{0xa8,0xf8,RD }}}, -{80,'s','E','!','D',O_MULXU|O_UNSZ,"mulxu",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0xa8,0xf8,RD }}}, -{80,'s','E','!','D',O_MULXU|O_UNSZ,"mulxu",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0xa8,0xf8,RD }}}, -{80,'s','E','!','D',O_MULXU|O_UNSZ,"mulxu",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0xa8,0xf8,RD }}}, -{80,'s','E','!','D',O_MULXU|O_UNSZ,"mulxu",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0xa8,0xf8,RD }}}, -{80,'s','E','!','D',O_MULXU|O_UNSZ,"mulxu",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0xa8,0xf8,RD }}}, -{80,'s','E','!','D',O_MULXU|O_UNSZ,"mulxu",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0xa8,0xf8,RD }}}, -{80,'s','E','!','D',O_MULXU|O_UNSZ,"mulxu",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0xa8,0xf8,RD }}}, -{80,'s','E','!','D',O_MULXU|O_UNSZ,"mulxu",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0xa8,0xf8,RD }}}, -{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RN},3, {{0xa0,0xf8,RN },{0x00,0xff, },{0x90,0xf8,RS }}}, -{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNDEC},3, {{0xb0,0xf8,RN },{0x00,0xff, },{0x90,0xf8,RS }}}, -{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNINC},3, {{0xc0,0xf8,RN },{0x00,0xff, },{0x90,0xf8,RS }}}, -{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNIND},3, {{0xd0,0xf8,RN },{0x00,0xff, },{0x90,0xf8,RS }}}, -{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,ABS8},4, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x00,0xff, },{0x90,0xf8,RS }}}, -{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x00,0xff, },{0x90,0xf8,RS }}}, -{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,ABS16},5, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x00,0xff, },{0x90,0xf8,RS }}}, -{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x00,0xff, },{0x90,0xf8,RS }}}, -{82,'-','S','!','E',O_MOVTPE|O_UNSZ,"movtpe",2,{RS,RN},3, {{0xa0,0xf8,RN },{0x00,0xff, },{0x90,0xf8,RS }}}, -{82,'-','S','!','E',O_MOVTPE|O_UNSZ,"movtpe",2,{RS,RNDEC},3, {{0xb0,0xf8,RN },{0x00,0xff, },{0x90,0xf8,RS }}}, -{82,'-','S','!','E',O_MOVTPE|O_UNSZ,"movtpe",2,{RS,RNIND},3, {{0xd0,0xf8,RN },{0x00,0xff, },{0x90,0xf8,RS }}}, -{82,'-','S','!','E',O_MOVTPE|O_UNSZ,"movtpe",2,{RS,RNINC},3, {{0xc0,0xf8,RN },{0x00,0xff, },{0x90,0xf8,RS }}}, -{82,'-','S','!','E',O_MOVTPE|O_UNSZ,"movtpe",2,{RS,ABS8},4, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x00,0xff, },{0x90,0xf8,RS }}}, -{82,'-','S','!','E',O_MOVTPE|O_UNSZ,"movtpe",2,{RS,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x00,0xff, },{0x90,0xf8,RS }}}, -{82,'-','S','!','E',O_MOVTPE|O_UNSZ,"movtpe",2,{RS,ABS16},5, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x00,0xff, },{0x90,0xf8,RS }}}, -{82,'-','S','!','E',O_MOVTPE|O_UNSZ,"movtpe",2,{RS,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x00,0xff, },{0x90,0xf8,RS }}}, -{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RN,RD},3, {{0xa0,0xf8,RN },{0x00,0xff, },{0x80,0xf8,RD }}}, -{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNINC,RD},3, {{0xc0,0xf8,RN },{0x00,0xff, },{0x80,0xf8,RD }}}, -{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNIND,RD},3, {{0xd0,0xf8,RN },{0x00,0xff, },{0x80,0xf8,RD }}}, -{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNDEC,RD},3, {{0xb0,0xf8,RN },{0x00,0xff, },{0x80,0xf8,RD }}}, -{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{IMM8,RD},4, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x00,0xff, },{0x80,0xf8,RD }}}, -{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{ABS8,RD},4, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x00,0xff, },{0x80,0xf8,RD }}}, -{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNIND_D8,RD},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x00,0xff, },{0x80,0xf8,RD }}}, -{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{ABS16,RD},5, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x00,0xff, },{0x80,0xf8,RD }}}, -{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNIND_D16,RD},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x00,0xff, },{0x80,0xf8,RD }}}, -{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{RN,RD},3, {{0xa0,0xf8,RN },{0x00,0xff, },{0x80,0xf8,RD }}}, -{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{RNINC,RD},3, {{0xc0,0xf8,RN },{0x00,0xff, },{0x80,0xf8,RD }}}, -{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{RNIND,RD},3, {{0xd0,0xf8,RN },{0x00,0xff, },{0x80,0xf8,RD }}}, -{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{RNDEC,RD},3, {{0xb0,0xf8,RN },{0x00,0xff, },{0x80,0xf8,RD }}}, -{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{IMM8,RD},4, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x00,0xff, },{0x80,0xf8,RD }}}, -{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{ABS8,RD},4, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x00,0xff, },{0x80,0xf8,RD }}}, -{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{RNIND_D8,RD},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x00,0xff, },{0x80,0xf8,RD }}}, -{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{ABS16,RD},5, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x00,0xff, },{0x80,0xf8,RD }}}, -{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{RNIND_D16,RD},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x00,0xff, },{0x80,0xf8,RD }}}, -{85,'m','S','!','E',O_MOV|O_WORD,"mov:s.w",2,{RS,ABS8},2, {{0x78,0xf8,RS },{0x00,0x00,ABS8 }}}, -{86,'m','S','!','E',O_MOV|O_BYTE,"mov:s.b",2,{RS,ABS8},2, {{0x70,0xf8,RS },{0x00,0x00,ABS8 }}}, -{87,'m','S','!','E',O_MOV|O_UNSZ,"mov:s",2,{RS,ABS8},2, {{0x78,0xf8,RS },{0x00,0x00,ABS8 }}}, -{88,'m','E','!','D',O_MOV|O_WORD,"mov:l.w",2,{ABS8,RD},2, {{0x68,0xf8,RD },{0x00,0x00,ABS8 }}}, -{89,'m','E','!','D',O_MOV|O_BYTE,"mov:l.b",2,{ABS8,RD},2, {{0x60,0xf8,RD },{0x00,0x00,ABS8 }}}, -{90,'m','E','!','D',O_MOV|O_UNSZ,"mov:l",2,{ABS8,RD},2, {{0x68,0xf8,RD },{0x00,0x00,ABS8 }}}, -{91,'m','I','!','D',O_MOV|O_WORD,"mov:i.w",2,{IMM16,RD},3, {{0x58,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{92,'m','I','!','D',O_MOV|O_UNSZ,"mov:i",2,{IMM16,RD},3, {{0x58,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNIND},2, {{0xd8,0xf8,RN },{0x90,0xf8,RS }}}, -{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x80,0xf8,RD }}}, -{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNDEC},2, {{0xb8,0xf8,RN },{0x90,0xf8,RS }}}, -{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNINC},2, {{0xc8,0xf8,RN },{0x90,0xf8,RS }}}, -{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x80,0xf8,RD }}}, -{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x80,0xf8,RD }}}, -{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x80,0xf8,RD }}}, -{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,ABS8},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x90,0xf8,RS }}}, -{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNIND_D8},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x90,0xf8,RS }}}, -{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x80,0xf8,RD }}}, -{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x80,0xf8,RD }}}, -{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNIND},4, {{0xd0,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x90,0xf8,RS }}}, -{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNDEC},4, {{0xb0,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x80,0xf8,RD }}}, -{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,ABS16},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x90,0xf8,RS }}}, -{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNINC},4, {{0xc0,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x80,0xf8,RD }}}, -{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x80,0xf8,RD }}}, -{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNIND_D8},5, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,ABS8},5, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNIND_D16},6, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,ABS16},6, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNINC},2, {{0xc0,0xf8,RN },{0x90,0xf8,RS }}}, -{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x80,0xf8,RD }}}, -{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNIND},2, {{0xd0,0xf8,RN },{0x90,0xf8,RS }}}, -{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x80,0xf8,RD }}}, -{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNDEC},2, {{0xb0,0xf8,RN },{0x90,0xf8,RS }}}, -{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x80,0xf8,RD }}}, -{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x80,0xf8,RD }}}, -{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,ABS8},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x90,0xf8,RS }}}, -{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNIND_D8},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x90,0xf8,RS }}}, -{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RD},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x80,0xf8,RD }}}, -{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x80,0xf8,RD }}}, -{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNIND},3, {{0xd0,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNINC},3, {{0xc0,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNDEC},3, {{0xb0,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{ABS8,RD},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x80,0xf8,RD }}}, -{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,ABS8},4, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{ABS16,RD},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x80,0xf8,RD }}}, -{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNIND_D16},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x90,0xf8,RS }}}, -{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,ABS16},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x90,0xf8,RS }}}, -{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x80,0xf8,RD }}}, -{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,ABS16},5, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{95,'m','S','!','E',O_MOV|O_UNSZ,"mov:g",2,{RS,RNINC},2, {{0xc8,0xf8,RN },{0x90,0xf8,RS }}}, -{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x80,0xf8,RD }}}, -{95,'m','S','!','E',O_MOV|O_UNSZ,"mov:g",2,{RS,RNIND},2, {{0xd8,0xf8,RN },{0x90,0xf8,RS }}}, -{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x80,0xf8,RD }}}, -{95,'m','S','!','E',O_MOV|O_UNSZ,"mov:g",2,{RS,RNDEC},2, {{0xb8,0xf8,RN },{0x90,0xf8,RS }}}, -{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x80,0xf8,RD }}}, -{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x80,0xf8,RD }}}, -{95,'m','S','!','E',O_MOV|O_UNSZ,"mov:g",2,{RS,RNIND_D8},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x90,0xf8,RS }}}, -{95,'m','S','!','E',O_MOV|O_UNSZ,"mov:g",2,{RS,ABS8},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x90,0xf8,RS }}}, -{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x80,0xf8,RD }}}, -{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM8,RNIND},3, {{0xd0,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x80,0xf8,RD }}}, -{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM8,RNDEC},3, {{0xb0,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM8,RNINC},3, {{0xc0,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM8,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM8,ABS8},4, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{95,'m','S','!','E',O_MOV|O_UNSZ,"mov:g",2,{RS,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x90,0xf8,RS }}}, -{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x80,0xf8,RD }}}, -{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM16,RNIND},4, {{0xd0,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM16,RNINC},4, {{0xc0,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM16,RNDEC},4, {{0xb0,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{95,'m','S','!','E',O_MOV|O_UNSZ,"mov:g",2,{RS,ABS16},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x90,0xf8,RS }}}, -{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x80,0xf8,RD }}}, -{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x80,0xf8,RD }}}, -{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM16,RNIND_D8},5, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM8,ABS16},5, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM16,ABS8},5, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM8,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM16,ABS16},6, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM16,RNIND_D16},6, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{96,'m','S','!','E',O_MOV|O_WORD,"mov:f.w",2,{RS,FPIND_D8},2, {{0x98,0xf8,RS },{0x00,0x00,FPIND_D8 }}}, -{96,'m','E','!','D',O_MOV|O_WORD,"mov:f.w",2,{FPIND_D8,RD},2, {{0x88,0xf8,RD },{0x00,0x00,FPIND_D8 }}}, -{97,'m','S','!','E',O_MOV|O_BYTE,"mov:f.b",2,{RS,FPIND_D8},2, {{0x90,0xf8,RS },{0x00,0x00,FPIND_D8 }}}, -{97,'m','E','!','D',O_MOV|O_BYTE,"mov:f.b",2,{FPIND_D8,RD},2, {{0x80,0xf8,RD },{0x00,0x00,FPIND_D8 }}}, -{98,'m','S','!','E',O_MOV|O_UNSZ,"mov:f",2,{RS,FPIND_D8},2, {{0x98,0xf8,RS },{0x00,0x00,FPIND_D8 }}}, -{98,'m','E','!','D',O_MOV|O_UNSZ,"mov:f",2,{FPIND_D8,RD},2, {{0x88,0xf8,RD },{0x00,0x00,FPIND_D8 }}}, -{99,'m','I','!','D',O_MOV|O_BYTE,"mov:e.b",2,{IMM8,RD},2, {{0x50,0xf8,RD },{0x00,0x00,IMM8 }}}, -{100,'m','I','!','D',O_MOV|O_UNSZ,"mov:e",2,{IMM8,RD},2, {{0x50,0xf8,RD },{0x00,0x00,IMM8 }}}, -{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,FPIND_D8},2, {{0x98,0xf8,RS },{0x00,0x00,FPIND_D8 }}}, -{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,ABS8},2, {{0x78,0xf8,RS },{0x00,0x00,ABS8 }}}, -{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{ABS8,RD},2, {{0x68,0xf8,RD },{0x00,0x00,ABS8 }}}, -{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,RNIND},2, {{0xd8,0xf8,RN },{0x90,0xf8,RS }}}, -{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,RNINC},2, {{0xc8,0xf8,RN },{0x90,0xf8,RS }}}, -{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,RNDEC},2, {{0xb8,0xf8,RN },{0x90,0xf8,RS }}}, -{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x80,0xf8,RD }}}, -{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{FPIND_D8,RD},2, {{0x88,0xf8,RD },{0x00,0x00,FPIND_D8 }}}, -{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x80,0xf8,RD }}}, -{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x80,0xf8,RD }}}, -{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x80,0xf8,RD }}}, -{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,ABS8},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x90,0xf8,RS }}}, -{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x80,0xf8,RD }}}, -{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,RNIND_D8},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x90,0xf8,RS }}}, -{101,'m','I','!','D',O_MOV|O_WORD,"mov.w",2,{IMM16,RD},3, {{0x58,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x80,0xf8,RD }}}, -{101,'m','I','!','E',O_MOV|O_WORD,"mov.w",2,{IMM16,RNINC},4, {{0xc0,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{101,'m','I','!','E',O_MOV|O_WORD,"mov.w",2,{IMM16,RNDEC},4, {{0xb0,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{101,'m','I','!','E',O_MOV|O_WORD,"mov.w",2,{IMM16,RNIND},4, {{0xd0,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x90,0xf8,RS }}}, -{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,ABS16},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x90,0xf8,RS }}}, -{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x80,0xf8,RD }}}, -{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x80,0xf8,RD }}}, -{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x80,0xf8,RD }}}, -{101,'m','I','!','E',O_MOV|O_WORD,"mov.w",2,{IMM16,RNIND_D8},5, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{101,'m','I','!','E',O_MOV|O_WORD,"mov.w",2,{IMM16,ABS8},5, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{101,'m','I','!','E',O_MOV|O_WORD,"mov.w",2,{IMM16,RNIND_D16},6, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{101,'m','I','!','E',O_MOV|O_WORD,"mov.w",2,{IMM16,ABS16},6, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{FPIND_D8,RD},2, {{0x80,0xf8,RD },{0x00,0x00,FPIND_D8 }}}, -{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,ABS8},2, {{0x70,0xf8,RS },{0x00,0x00,ABS8 }}}, -{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x80,0xf8,RD }}}, -{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,RNIND},2, {{0xd0,0xf8,RN },{0x90,0xf8,RS }}}, -{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,RNINC},2, {{0xc0,0xf8,RN },{0x90,0xf8,RS }}}, -{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,RNDEC},2, {{0xb0,0xf8,RN },{0x90,0xf8,RS }}}, -{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x80,0xf8,RD }}}, -{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,FPIND_D8},2, {{0x90,0xf8,RS },{0x00,0x00,FPIND_D8 }}}, -{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x80,0xf8,RD }}}, -{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x80,0xf8,RD }}}, -{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{ABS8,RD},2, {{0x60,0xf8,RD },{0x00,0x00,ABS8 }}}, -{102,'m','I','!','D',O_MOV|O_BYTE,"mov.b",2,{IMM8,RD},2, {{0x50,0xf8,RD },{0x00,0x00,IMM8 }}}, -{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{IMM8,RD},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x80,0xf8,RD }}}, -{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,ABS8},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x90,0xf8,RS }}}, -{102,'m','I','!','E',O_MOV|O_BYTE,"mov.b",2,{IMM8,RNIND},3, {{0xd0,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{102,'m','I','!','E',O_MOV|O_BYTE,"mov.b",2,{IMM8,RNINC},3, {{0xc0,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{102,'m','I','!','E',O_MOV|O_BYTE,"mov.b",2,{IMM8,RNDEC},3, {{0xb0,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x80,0xf8,RD }}}, -{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{ABS8,RD},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x80,0xf8,RD }}}, -{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,RNIND_D8},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x90,0xf8,RS }}}, -{102,'m','I','!','E',O_MOV|O_BYTE,"mov.b",2,{IMM8,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{ABS16,RD},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x80,0xf8,RD }}}, -{102,'m','I','!','E',O_MOV|O_BYTE,"mov.b",2,{IMM8,ABS8},4, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,ABS16},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x90,0xf8,RS }}}, -{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,RNIND_D16},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x90,0xf8,RS }}}, -{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x80,0xf8,RD }}}, -{102,'m','I','!','E',O_MOV|O_BYTE,"mov.b",2,{IMM8,ABS16},5, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{102,'m','I','!','E',O_MOV|O_BYTE,"mov.b",2,{IMM8,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{ABS8,RD},2, {{0x68,0xf8,RD },{0x00,0x00,ABS8 }}}, -{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,ABS8},2, {{0x78,0xf8,RS },{0x00,0x00,ABS8 }}}, -{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x80,0xf8,RD }}}, -{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,RNIND},2, {{0xd8,0xf8,RN },{0x90,0xf8,RS }}}, -{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,RNINC},2, {{0xc8,0xf8,RN },{0x90,0xf8,RS }}}, -{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,RNDEC},2, {{0xb8,0xf8,RN },{0x90,0xf8,RS }}}, -{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x80,0xf8,RD }}}, -{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,FPIND_D8},2, {{0x98,0xf8,RS },{0x00,0x00,FPIND_D8 }}}, -{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x80,0xf8,RD }}}, -{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{FPIND_D8,RD},2, {{0x88,0xf8,RD },{0x00,0x00,FPIND_D8 }}}, -{103,'m','I','!','D',O_MOV|O_UNSZ,"mov",2,{IMM8,RD},2, {{0x50,0xf8,RD },{0x00,0x00,IMM8 }}}, -{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x80,0xf8,RD }}}, -{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,RNIND_D8},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x90,0xf8,RS }}}, -{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM8,RNIND},3, {{0xd0,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM8,RNINC},3, {{0xc0,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM8,RNDEC},3, {{0xb0,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x80,0xf8,RD }}}, -{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,ABS8},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x90,0xf8,RS }}}, -{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x80,0xf8,RD }}}, -{103,'m','I','!','D',O_MOV|O_UNSZ,"mov",2,{IMM16,RD},3, {{0x58,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM8,ABS8},4, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x90,0xf8,RS }}}, -{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM16,RNIND},4, {{0xd0,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM16,RNINC},4, {{0xc0,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM16,RNDEC},4, {{0xb0,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,ABS16},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x90,0xf8,RS }}}, -{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x80,0xf8,RD }}}, -{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM8,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x80,0xf8,RD }}}, -{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x80,0xf8,RD }}}, -{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM16,RNIND_D8},5, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM8,ABS16},5, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM16,ABS8},5, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM8,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM16,ABS16},6, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM16,RNIND_D16},6, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{104,'-','S','I','!',O_LINK|O_UNSZ,"link",2,{FP,IMM8},2, {{0x17,0xff, },{0x00,0x00,IMM8 }}}, -{104,'-','S','I','!',O_LINK|O_UNSZ,"link",2,{FP,IMM16},3, {{0x1f,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{105,'-','E','!','C',O_LDM|O_UNSZ,"ldm",2,{SPINC,RLIST},2, {{0x02,0xff, },{0x00,0x00,RLIST }}}, -{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{RN,CRW},2, {{0xa0,0xf8,RN },{0x88,0xf8,CRW }}}, -{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{RNIND,CRW},2, {{0xd0,0xf8,RN },{0x88,0xf8,CRW }}}, -{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{RNINC,CRW},2, {{0xc0,0xf8,RN },{0x88,0xf8,CRW }}}, -{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{RNDEC,CRW},2, {{0xb0,0xf8,RN },{0x88,0xf8,CRW }}}, -{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{ABS8,CRW},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x88,0xf8,CRW }}}, -{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{RNIND_D8,CRW},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x88,0xf8,CRW }}}, -{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{IMM16,CRW},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x88,0xf8,CRW }}}, -{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{ABS16,CRW},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x88,0xf8,CRW }}}, -{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{RNIND_D16,CRW},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x88,0xf8,CRW }}}, -{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RN,CRB},2, {{0xa0,0xf8,RN },{0x88,0xf8,CRB }}}, -{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNDEC,CRB},2, {{0xb0,0xf8,RN },{0x88,0xf8,CRB }}}, -{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNINC,CRB},2, {{0xc0,0xf8,RN },{0x88,0xf8,CRB }}}, -{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNIND,CRB},2, {{0xd0,0xf8,RN },{0x88,0xf8,CRB }}}, -{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{IMM8,CRB},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x88,0xf8,CRB }}}, -{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{ABS8,CRB},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x88,0xf8,CRB }}}, -{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNIND_D8,CRB},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x88,0xf8,CRB }}}, -{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{ABS16,CRB},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x88,0xf8,CRB }}}, -{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNIND_D16,CRB},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x88,0xf8,CRB }}}, -{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RN,CRW},2, {{0xa0,0xf8,RN },{0x88,0xf8,CRW }}}, -{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RN,CRB},2, {{0xa0,0xf8,RN },{0x88,0xf8,CRB }}}, -{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RNINC,CRW},2, {{0xc0,0xf8,RN },{0x88,0xf8,CRW }}}, -{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RNIND,CRB},2, {{0xd0,0xf8,RN },{0x88,0xf8,CRB }}}, -{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RNDEC,CRW},2, {{0xb0,0xf8,RN },{0x88,0xf8,CRW }}}, -{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RNIND,CRW},2, {{0xd0,0xf8,RN },{0x88,0xf8,CRW }}}, -{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RNDEC,CRB},2, {{0xb0,0xf8,RN },{0x88,0xf8,CRB }}}, -{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RNINC,CRB},2, {{0xc0,0xf8,RN },{0x88,0xf8,CRB }}}, -{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{ABS8,CRW},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x88,0xf8,CRW }}}, -{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{ABS8,CRB},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x88,0xf8,CRB }}}, -{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{IMM8,CRB},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x88,0xf8,CRB }}}, -{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RNIND_D8,CRW},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x88,0xf8,CRW }}}, -{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RNIND_D8,CRB},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x88,0xf8,CRB }}}, -{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{ABS16,CRB},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x88,0xf8,CRB }}}, -{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{ABS16,CRW},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x88,0xf8,CRW }}}, -{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{IMM16,CRW},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x88,0xf8,CRW }}}, -{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RNIND_D16,CRW},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x88,0xf8,CRW }}}, -{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RNIND_D16,CRB},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x88,0xf8,CRB }}}, -{109,'-','B','!','!',O_JSR|O_UNSZ,"jsr",1,{RDIND,0},2, {{0x11,0xff, },{0xd8,0xf8,RDIND }}}, -{109,'-','B','!','!',O_JSR|O_UNSZ,"jsr",1,{ABS16,0},3, {{0x18,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, }}}, -{109,'-','B','!','!',O_JSR|O_UNSZ,"jsr",1,{RDIND_D8,0},3, {{0x11,0xff, },{0xe8,0xf8,RDIND_D8 },{0x00,0x00, }}}, -{109,'-','B','!','!',O_JSR|O_UNSZ,"jsr",1,{RDIND_D16,0},4, {{0x11,0xff, },{0xf8,0xf8,RDIND_D16 },{0x00,0x00, },{0x00,0x00, }}}, -{110,'-','B','!','!',O_JMP|O_UNSZ,"jmp",1,{RDIND,0},2, {{0x11,0xff, },{0xd0,0xf8,RDIND }}}, -{110,'-','B','!','!',O_JMP|O_UNSZ,"jmp",1,{ABS16,0},3, {{0x10,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, }}}, -{110,'-','B','!','!',O_JMP|O_UNSZ,"jmp",1,{RDIND_D8,0},3, {{0x11,0xff, },{0xe0,0xf8,RDIND_D8 },{0x00,0x00, }}}, -{110,'-','B','!','!',O_JMP|O_UNSZ,"jmp",1,{RDIND_D16,0},4, {{0x11,0xff, },{0xf0,0xf8,RDIND_D16 },{0x00,0x00, },{0x00,0x00, }}}, -{111,'s','D','!','D',O_EXTU|O_BYTE,"extu.b",1,{RD,0},2, {{0xa0,0xf8,RD },{0x12,0xff, }}}, -{112,'s','D','!','D',O_EXTU|O_UNSZ,"extu",1,{RD,0},2, {{0xa0,0xf8,RD },{0x12,0xff, }}}, -{113,'s','D','!','D',O_EXTS|O_BYTE,"exts.b",1,{RD,0},2, {{0xa0,0xf8,RD },{0x11,0xff, }}}, -{114,'s','D','!','D',O_EXTS|O_UNSZ,"exts",1,{RD,0},2, {{0xa0,0xf8,RD },{0x11,0xff, }}}, -{115,'s','D','!','!',O_DSUB|O_UNSZ,"dsub",2,{RS,RD},3, {{0xa0,0xf8,RS },{0x00,0xff, },{0xb0,0xf8,RD }}}, -{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0xb8,0xf8,RD }}}, -{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0xb8,0xf8,RD }}}, -{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0xb8,0xf8,RD }}}, -{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0xb8,0xf8,RD }}}, -{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0xb8,0xf8,RD }}}, -{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0xb8,0xf8,RD }}}, -{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0xb8,0xf8,RD }}}, -{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0xb8,0xf8,RD }}}, -{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0xb8,0xf8,RD }}}, -{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0xb8,0xf8,RD }}}, -{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0xb8,0xf8,RD }}}, -{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0xb8,0xf8,RD }}}, -{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0xb8,0xf8,RD }}}, -{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{IMM8,RD},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0xb8,0xf8,RD }}}, -{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0xb8,0xf8,RD }}}, -{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{ABS8,RD},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0xb8,0xf8,RD }}}, -{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{ABS16,RD},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0xb8,0xf8,RD }}}, -{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0xb8,0xf8,RD }}}, -{118,'s','E','D','D',O_DIVXU|O_UNSZ,"divxu",2,{RN,RD},2, {{0xa8,0xf8,RN },{0xb8,0xf8,RD }}}, -{118,'s','E','D','D',O_DIVXU|O_UNSZ,"divxu",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0xb8,0xf8,RD }}}, -{118,'s','E','D','D',O_DIVXU|O_UNSZ,"divxu",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0xb8,0xf8,RD }}}, -{118,'s','E','D','D',O_DIVXU|O_UNSZ,"divxu",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0xb8,0xf8,RD }}}, -{118,'s','E','D','D',O_DIVXU|O_UNSZ,"divxu",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0xb8,0xf8,RD }}}, -{118,'s','E','D','D',O_DIVXU|O_UNSZ,"divxu",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0xb8,0xf8,RD }}}, -{118,'s','E','D','D',O_DIVXU|O_UNSZ,"divxu",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0xb8,0xf8,RD }}}, -{118,'s','E','D','D',O_DIVXU|O_UNSZ,"divxu",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0xb8,0xf8,RD }}}, -{118,'s','E','D','D',O_DIVXU|O_UNSZ,"divxu",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0xb8,0xf8,RD }}}, -{119,'s','D','!','!',O_DAAD|O_UNSZ,"daad",2,{RS,RD},3, {{0xa0,0xf8,RS },{0x00,0xff, },{0xa0,0xf8,RD }}}, -{120,'a','D','I','!',O_CMP|O_WORD,"cmp:i.w",2,{IMM16,RD},3, {{0x48,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{121,'a','D','I','!',O_CMP|O_UNSZ,"cmp:i",2,{IMM16,RD},3, {{0x48,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x70,0xf8,RD }}}, -{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x70,0xf8,RD }}}, -{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x70,0xf8,RD }}}, -{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x70,0xf8,RD }}}, -{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x70,0xf8,RD }}}, -{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x70,0xf8,RD }}}, -{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RNINC},4, {{0xc0,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RNDEC},4, {{0xb0,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RN},4, {{0xa0,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RNIND},4, {{0xd0,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x70,0xf8,RD }}}, -{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x70,0xf8,RD }}}, -{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x70,0xf8,RD }}}, -{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RNIND_D8},5, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,ABS8},5, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RNIND_D16},6, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,ABS16},6, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x70,0xf8,RD }}}, -{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x70,0xf8,RD }}}, -{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x70,0xf8,RD }}}, -{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x70,0xf8,RD }}}, -{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RN},3, {{0xa0,0xf8,RN },{0x04,0xff, },{0x00,0x00,IMM8 }}}, -{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RNIND},3, {{0xd0,0xf8,RN },{0x04,0xff, },{0x00,0x00,IMM8 }}}, -{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RNINC},3, {{0xc0,0xf8,RN },{0x04,0xff, },{0x00,0x00,IMM8 }}}, -{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RNDEC},3, {{0xb0,0xf8,RN },{0x04,0xff, },{0x00,0x00,IMM8 }}}, -{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RD},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x70,0xf8,RD }}}, -{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x70,0xf8,RD }}}, -{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{ABS8,RD},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x70,0xf8,RD }}}, -{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{ABS16,RD},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x70,0xf8,RD }}}, -{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x04,0xff, },{0x00,0x00,IMM8 }}}, -{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,ABS8},4, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x04,0xff, },{0x00,0x00,IMM8 }}}, -{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x70,0xf8,RD }}}, -{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,ABS16},5, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x04,0xff, },{0x00,0x00,IMM8 }}}, -{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x04,0xff, },{0x00,0x00,IMM8 }}}, -{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x70,0xf8,RD }}}, -{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x70,0xf8,RD }}}, -{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x70,0xf8,RD }}}, -{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x70,0xf8,RD }}}, -{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x70,0xf8,RD }}}, -{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x70,0xf8,RD }}}, -{124,'a','E','I','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,RNINC},4, {{0xc0,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{124,'a','E','I','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,RNIND},4, {{0xd0,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{124,'a','E','I','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,RN},4, {{0xa0,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{124,'a','E','I','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,RNDEC},4, {{0xb0,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x70,0xf8,RD }}}, -{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x70,0xf8,RD }}}, -{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x70,0xf8,RD }}}, -{124,'a','E','I','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,RNIND_D8},5, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{124,'a','E','I','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,ABS8},5, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{124,'a','E','I','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,RNIND_D16},6, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{124,'a','E','I','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,ABS16},6, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{125,'a','D','I','!',O_CMP|O_BYTE,"cmp:e.b",2,{IMM8,RD},2, {{0x40,0xf8,RD },{0x00,0x00,IMM8 }}}, -{126,'a','D','I','!',O_CMP|O_UNSZ,"cmp:e",2,{IMM8,RD},2, {{0x40,0xf8,RD },{0x00,0x00,IMM8 }}}, -{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x70,0xf8,RD }}}, -{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x70,0xf8,RD }}}, -{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x70,0xf8,RD }}}, -{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x70,0xf8,RD }}}, -{127,'a','D','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,RD},3, {{0x48,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x70,0xf8,RD }}}, -{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x70,0xf8,RD }}}, -{127,'a','E','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,RNINC},4, {{0xc0,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{127,'a','E','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,RNDEC},4, {{0xb0,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{127,'a','E','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,RNIND},4, {{0xd0,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x70,0xf8,RD }}}, -{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x70,0xf8,RD }}}, -{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x70,0xf8,RD }}}, -{127,'a','E','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,RN},4, {{0xa0,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{127,'a','E','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,RNIND_D8},5, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{127,'a','E','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,ABS8},5, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{127,'a','E','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,RNIND_D16},6, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{127,'a','E','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,ABS16},6, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x70,0xf8,RD }}}, -{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x70,0xf8,RD }}}, -{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x70,0xf8,RD }}}, -{128,'a','D','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,RD},2, {{0x40,0xf8,RD },{0x00,0x00,IMM8 }}}, -{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x70,0xf8,RD }}}, -{128,'a','E','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,RN},3, {{0xa0,0xf8,RN },{0x04,0xff, },{0x00,0x00,IMM8 }}}, -{128,'a','E','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,RNIND},3, {{0xd0,0xf8,RN },{0x04,0xff, },{0x00,0x00,IMM8 }}}, -{128,'a','E','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,RNINC},3, {{0xc0,0xf8,RN },{0x04,0xff, },{0x00,0x00,IMM8 }}}, -{128,'a','E','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,RNDEC},3, {{0xb0,0xf8,RN },{0x04,0xff, },{0x00,0x00,IMM8 }}}, -{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{ABS8,RD},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x70,0xf8,RD }}}, -{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x70,0xf8,RD }}}, -{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,RD},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x70,0xf8,RD }}}, -{128,'a','E','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,ABS8},4, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x04,0xff, },{0x00,0x00,IMM8 }}}, -{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{ABS16,RD},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x70,0xf8,RD }}}, -{128,'a','E','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x04,0xff, },{0x00,0x00,IMM8 }}}, -{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x70,0xf8,RD }}}, -{128,'a','E','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,ABS16},5, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x04,0xff, },{0x00,0x00,IMM8 }}}, -{128,'a','E','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x04,0xff, },{0x00,0x00,IMM8 }}}, -{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x70,0xf8,RD }}}, -{129,'a','D','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM8,RD},2, {{0x40,0xf8,RD },{0x00,0x00,IMM8 }}}, -{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x70,0xf8,RD }}}, -{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x70,0xf8,RD }}}, -{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x70,0xf8,RD }}}, -{129,'a','D','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,RD},3, {{0x48,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x70,0xf8,RD }}}, -{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x70,0xf8,RD }}}, -{129,'a','E','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,RN},4, {{0xa0,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{129,'a','E','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,RNDEC},4, {{0xb0,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{129,'a','E','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,RNIND},4, {{0xd0,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x70,0xf8,RD }}}, -{129,'a','E','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,RNINC},4, {{0xc0,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x70,0xf8,RD }}}, -{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x70,0xf8,RD }}}, -{129,'a','E','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,ABS8},5, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{129,'a','E','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,RNIND_D8},5, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{129,'a','E','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,ABS16},6, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{129,'a','E','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,RNIND_D16},6, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x13,0xff, }}}, -{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x13,0xff, }}}, -{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x13,0xff, }}}, -{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x13,0xff, }}}, -{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{ABS8,0},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x13,0xff, }}}, -{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x13,0xff, }}}, -{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{ABS16,0},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x13,0xff, }}}, -{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{IMM16,0},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x13,0xff, }}}, -{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x13,0xff, }}}, -{131,'c','!','!','E',O_CLR|O_BYTE,"clr.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x13,0xff, }}}, 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{{0xd8,0xf8,RN },{0x13,0xff, }}}, -{132,'c','!','!','E',O_CLR|O_UNSZ,"clr",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x13,0xff, }}}, -{132,'c','!','!','E',O_CLR|O_UNSZ,"clr",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x13,0xff, }}}, -{132,'c','!','!','E',O_CLR|O_UNSZ,"clr",1,{ABS8,0},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x13,0xff, }}}, -{132,'c','!','!','E',O_CLR|O_UNSZ,"clr",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x13,0xff, }}}, -{132,'c','!','!','E',O_CLR|O_UNSZ,"clr",1,{IMM16,0},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x13,0xff, }}}, -{132,'c','!','!','E',O_CLR|O_UNSZ,"clr",1,{ABS16,0},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x13,0xff, }}}, -{132,'c','!','!','E',O_CLR|O_UNSZ,"clr",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x13,0xff, }}}, -{133,'-','B','!','!',O_BVS|O_WORD,"bvs.w",1,{PCREL16,0},3, {{0x39,0xff, },{0x00,0x00,PCREL16 },{0x00,0x00, }}}, -{134,'-','B','!','!',O_BVS|O_BYTE,"bvs.b",1,{PCREL8,0},2, {{0x29,0xff, },{0x00,0x00,PCREL8 }}}, -{135,'-','B','!','!',O_BVS|O_UNSZ,"bvs",1,{PCREL8,0},2, {{0x29,0xff, },{0x00,0x00,PCREL8 }}}, -{135,'-','B','!','!',O_BVS|O_UNSZ,"bvs",1,{PCREL16,0},3, {{0x39,0xff, },{0x00,0x00,PCREL16 },{0x00,0x00, }}}, -{136,'-','B','!','!',O_BVC|O_WORD,"bvc.w",1,{PCREL16,0},3, {{0x38,0xff, },{0x00,0x00,PCREL16 },{0x00,0x00, }}}, -{137,'-','B','!','!',O_BVC|O_BYTE,"bvc.b",1,{PCREL8,0},2, {{0x28,0xff, },{0x00,0x00,PCREL8 }}}, -{138,'-','B','!','!',O_BVC|O_UNSZ,"bvc",1,{PCREL8,0},2, {{0x28,0xff, },{0x00,0x00,PCREL8 }}}, -{138,'-','B','!','!',O_BVC|O_UNSZ,"bvc",1,{PCREL16,0},3, {{0x38,0xff, },{0x00,0x00,PCREL16 },{0x00,0x00, }}}, -{139,'b','E','S','E',O_BTST|O_WORD,"btst.w",2,{RS,RN},2, {{0xa8,0xf8,RN },{0x78,0xf8,RS }}}, -{139,'b','E','I','E',O_BTST|O_WORD,"btst.w",2,{IMM4,RNDEC},2, {{0xb8,0xf8,RN },{0xf0,0xf0,IMM4 }}}, -{139,'b','E','I','E',O_BTST|O_WORD,"btst.w",2,{IMM4,RNINC},2, {{0xc8,0xf8,RN },{0xf0,0xf0,IMM4 }}}, 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-{229,'a','I','E','E',O_ADD|O_UNSZ,"add",2,{QIM,RNDEC},2, {{0xb8,0xf8,RN },{0x08,0xf8,QIM }}}, -{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x20,0xf8,RD }}}, -{229,'a','I','E','E',O_ADD|O_UNSZ,"add",2,{QIM,RNIND},2, {{0xd8,0xf8,RN },{0x08,0xf8,QIM }}}, -{229,'a','I','E','E',O_ADD|O_UNSZ,"add",2,{QIM,RNINC},2, {{0xc8,0xf8,RN },{0x08,0xf8,QIM }}}, -{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x20,0xf8,RD }}}, -{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x20,0xf8,RD }}}, -{229,'a','I','E','E',O_ADD|O_UNSZ,"add",2,{QIM,ABS8},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x08,0xf8,QIM }}}, -{229,'a','I','E','E',O_ADD|O_UNSZ,"add",2,{QIM,RNIND_D8},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x08,0xf8,QIM }}}, -{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x20,0xf8,RD }}}, -{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x20,0xf8,RD }}}, -{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x20,0xf8,RD }}}, -{229,'a','I','E','E',O_ADD|O_UNSZ,"add",2,{QIM,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x08,0xf8,QIM }}}, -{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x20,0xf8,RD }}}, -{229,'a','I','E','E',O_ADD|O_UNSZ,"add",2,{QIM,ABS16},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x08,0xf8,QIM }}}, -{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x20,0xf8,RD }}}, -0,0,0} -#endif -; -#endif -#ifdef DISASSEMBLER_TABLE -#ifdef DEFINE_TABLE -={ -{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x60,0xf8,RD }}}, -{29,'s','C','!','E',O_STC|O_BYTE,"stc.b",2,{CRB,RN},2, {{0xa0,0xf8,RN },{0x98,0xf8,CRB }}}, -{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x60,0xf8,RD }}}, -{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x60,0xf8,RD }}}, -{29,'s','C','!','E',O_STC|O_BYTE,"stc.b",2,{CRB,RNDEC},2, {{0xb0,0xf8,RN },{0x98,0xf8,CRB }}}, -{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x60,0xf8,RD }}}, -{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x60,0xf8,RD }}}, -{29,'s','C','!','E',O_STC|O_BYTE,"stc.b",2,{CRB,RNINC},2, {{0xc0,0xf8,RN },{0x98,0xf8,CRB }}}, -{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x60,0xf8,RD }}}, -{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x60,0xf8,RD }}}, -{29,'s','C','!','E',O_STC|O_BYTE,"stc.b",2,{CRB,RNIND},2, {{0xd0,0xf8,RN },{0x98,0xf8,CRB }}}, -{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x60,0xf8,RD }}}, -{25,'a','E','D','D',O_SUB|O_BYTE,"sub.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x30,0xf8,RD }}}, -{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x60,0xf8,RD }}}, -{29,'s','C','!','E',O_STC|O_BYTE,"stc.b",2,{CRB,RNIND_D8},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x98,0xf8,CRB }}}, -{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x60,0xf8,RD }}}, -{25,'a','E','D','D',O_SUB|O_BYTE,"sub.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x30,0xf8,RD }}}, -{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x60,0xf8,RD }}}, -{29,'s','C','!','E',O_STC|O_BYTE,"stc.b",2,{CRB,RNIND_D16},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x98,0xf8,CRB }}}, -{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x60,0xf8,RD }}}, -{25,'a','E','D','D',O_SUB|O_BYTE,"sub.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x30,0xf8,RD }}}, -{10,'m','E','!','!',O_TST|O_BYTE,"tst.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x16,0xff, }}}, -{6,'-','X','!','!',O_XCH|O_WORD,"xch.w",2,{RS,RD},2, {{0xa8,0xf8,RS },{0x90,0xf8,RD }}}, -{9,'m','E','!','!',O_TST|O_WORD,"tst.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x16,0xff, }}}, -{25,'a','E','D','D',O_SUB|O_BYTE,"sub.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x30,0xf8,RD }}}, -{10,'m','E','!','!',O_TST|O_BYTE,"tst.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x16,0xff, }}}, -{24,'a','E','D','D',O_SUB|O_WORD,"sub.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x30,0xf8,RD }}}, -{9,'m','E','!','!',O_TST|O_WORD,"tst.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x16,0xff, }}}, -{25,'a','E','D','D',O_SUB|O_BYTE,"sub.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x30,0xf8,RD }}}, -{10,'m','E','!','!',O_TST|O_BYTE,"tst.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x16,0xff, }}}, -{9,'m','E','!','!',O_TST|O_WORD,"tst.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x16,0xff, }}}, -{25,'a','E','D','D',O_SUB|O_BYTE,"sub.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x30,0xf8,RD }}}, -{10,'m','E','!','!',O_TST|O_BYTE,"tst.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x16,0xff, }}}, -{24,'a','E','D','D',O_SUB|O_WORD,"sub.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x30,0xf8,RD }}}, -{9,'m','E','!','!',O_TST|O_WORD,"tst.w",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x16,0xff, }}}, -{10,'m','E','!','!',O_TST|O_BYTE,"tst.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x16,0xff, }}}, -{24,'a','E','D','D',O_SUB|O_WORD,"sub.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x30,0xf8,RD }}}, -{9,'m','E','!','!',O_TST|O_WORD,"tst.w",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x16,0xff, }}}, -{10,'m','E','!','!',O_TST|O_BYTE,"tst.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x16,0xff, }}}, -{24,'a','E','D','D',O_SUB|O_WORD,"sub.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x30,0xf8,RD }}}, -{16,'m','D','!','D',O_SWAP|O_BYTE,"swap.b",1,{RD,0},2, {{0xa0,0xf8,RD },{0x10,0xff, }}}, -{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x17,0xff, }}}, -{24,'a','E','D','D',O_SUB|O_WORD,"sub.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x30,0xf8,RD }}}, -{18,'a','E','D','D',O_SUBX|O_WORD,"subx.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0xb0,0xf8,RD }}}, -{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x17,0xff, }}}, -{18,'a','E','D','D',O_SUBX|O_WORD,"subx.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0xb0,0xf8,RD }}}, -{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x17,0xff, }}}, -{24,'a','E','D','D',O_SUB|O_WORD,"sub.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x30,0xf8,RD }}}, -{22,'-','E','D','D',O_SUBS|O_BYTE,"subs.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x38,0xf8,RD }}}, -{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x17,0xff, }}}, -{18,'a','E','D','D',O_SUBX|O_WORD,"subx.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0xb0,0xf8,RD }}}, -{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x17,0xff, }}}, -{22,'-','E','D','D',O_SUBS|O_BYTE,"subs.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x38,0xf8,RD }}}, -{22,'-','E','D','D',O_SUBS|O_BYTE,"subs.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x38,0xf8,RD }}}, -{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x17,0xff, }}}, -{22,'-','E','D','D',O_SUBS|O_BYTE,"subs.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x38,0xf8,RD }}}, -{19,'a','E','D','D',O_SUBX|O_BYTE,"subx.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0xb0,0xf8,RD }}}, -{21,'-','E','D','D',O_SUBS|O_WORD,"subs.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x38,0xf8,RD }}}, -{22,'-','E','D','D',O_SUBS|O_BYTE,"subs.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x38,0xf8,RD }}}, -{19,'a','E','D','D',O_SUBX|O_BYTE,"subx.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0xb0,0xf8,RD }}}, -{21,'-','E','D','D',O_SUBS|O_WORD,"subs.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x38,0xf8,RD }}}, -{22,'-','E','D','D',O_SUBS|O_BYTE,"subs.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x38,0xf8,RD }}}, -{19,'a','E','D','D',O_SUBX|O_BYTE,"subx.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0xb0,0xf8,RD }}}, -{21,'-','E','D','D',O_SUBS|O_WORD,"subs.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x38,0xf8,RD }}}, -{18,'a','E','D','D',O_SUBX|O_WORD,"subx.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0xb0,0xf8,RD }}}, -{19,'a','E','D','D',O_SUBX|O_BYTE,"subx.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0xb0,0xf8,RD }}}, -{19,'a','E','D','D',O_SUBX|O_BYTE,"subx.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0xb0,0xf8,RD }}}, -{21,'-','E','D','D',O_SUBS|O_WORD,"subs.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x38,0xf8,RD }}}, -{19,'a','E','D','D',O_SUBX|O_BYTE,"subx.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0xb0,0xf8,RD }}}, -{21,'-','E','D','D',O_SUBS|O_WORD,"subs.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x38,0xf8,RD }}}, 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-{32,'s','E','!','E',O_SHLR|O_WORD,"shlr.w",1,{ABS16,0},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x1b,0xff, }}}, -{42,'s','E','!','E',O_SHAL|O_BYTE,"shal.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x18,0xff, }}}, -{41,'s','E','!','E',O_SHAL|O_WORD,"shal.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x18,0xff, }}}, -{42,'s','E','!','E',O_SHAL|O_BYTE,"shal.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x18,0xff, }}}, -{41,'s','E','!','E',O_SHAL|O_WORD,"shal.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x18,0xff, }}}, -{52,'s','E','!','E',O_ROTXL|O_WORD,"rotxl.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x1e,0xff, }}}, -{42,'s','E','!','E',O_SHAL|O_BYTE,"shal.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x18,0xff, }}}, -{41,'s','E','!','E',O_SHAL|O_WORD,"shal.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x18,0xff, }}}, -{42,'s','E','!','E',O_SHAL|O_BYTE,"shal.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x18,0xff, }}}, -{41,'s','E','!','E',O_SHAL|O_WORD,"shal.w",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x18,0xff, }}}, -{42,'s','E','!','E',O_SHAL|O_BYTE,"shal.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x18,0xff, }}}, -{53,'s','E','!','E',O_ROTXL|O_BYTE,"rotxl.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x1e,0xff, }}}, -{41,'s','E','!','E',O_SHAL|O_WORD,"shal.w",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x18,0xff, }}}, -{52,'s','E','!','E',O_ROTXL|O_WORD,"rotxl.w",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x1e,0xff, }}}, -{42,'s','E','!','E',O_SHAL|O_BYTE,"shal.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x18,0xff, }}}, -{53,'s','E','!','E',O_ROTXL|O_BYTE,"rotxl.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x1e,0xff, }}}, -{41,'s','E','!','E',O_SHAL|O_WORD,"shal.w",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x18,0xff, }}}, -{52,'s','E','!','E',O_ROTXL|O_WORD,"rotxl.w",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x1e,0xff, }}}, -{42,'s','E','!','E',O_SHAL|O_BYTE,"shal.b",1,{IMM8,0},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x18,0xff, }}}, -{50,'s','E','!','E',O_ROTXR|O_BYTE,"rotxr.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x1f,0xff, }}}, -{53,'s','E','!','E',O_ROTXL|O_BYTE,"rotxl.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x1e,0xff, }}}, -{50,'s','E','!','E',O_ROTXR|O_BYTE,"rotxr.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x1f,0xff, }}}, -{52,'s','E','!','E',O_ROTXL|O_WORD,"rotxl.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x1e,0xff, }}}, -{49,'s','E','!','E',O_ROTXR|O_WORD,"rotxr.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x1f,0xff, }}}, -{53,'s','E','!','E',O_ROTXL|O_BYTE,"rotxl.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x1e,0xff, }}}, -{49,'s','E','!','E',O_ROTXR|O_WORD,"rotxr.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x1f,0xff, }}}, -{53,'s','E','!','E',O_ROTXL|O_BYTE,"rotxl.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x1e,0xff, }}}, -{50,'s','E','!','E',O_ROTXR|O_BYTE,"rotxr.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x1f,0xff, }}}, -{52,'s','E','!','E',O_ROTXL|O_WORD,"rotxl.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x1e,0xff, }}}, -{49,'s','E','!','E',O_ROTXR|O_WORD,"rotxr.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x1f,0xff, }}}, -{53,'s','E','!','E',O_ROTXL|O_BYTE,"rotxl.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x1e,0xff, }}}, -{50,'s','E','!','E',O_ROTXR|O_BYTE,"rotxr.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x1f,0xff, }}}, -{52,'s','E','!','E',O_ROTXL|O_WORD,"rotxl.w",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x1e,0xff, }}}, -{49,'s','E','!','E',O_ROTXR|O_WORD,"rotxr.w",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x1f,0xff, }}}, -{50,'s','E','!','E',O_ROTXR|O_BYTE,"rotxr.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x1f,0xff, }}}, -{49,'s','E','!','E',O_ROTXR|O_WORD,"rotxr.w",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x1f,0xff, }}}, -{50,'s','E','!','E',O_ROTXR|O_BYTE,"rotxr.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x1f,0xff, }}}, -{49,'s','E','!','E',O_ROTXR|O_WORD,"rotxr.w",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x1f,0xff, }}}, -{45,'-','B','S','S',O_SCB_F|O_UNSZ,"scb/f",2,{RS,PCREL8},3, {{0x01,0xff, },{0xb8,0xf8,RS },{0x00,0x00,PCREL8 }}}, -{53,'s','E','!','E',O_ROTXL|O_BYTE,"rotxl.b",1,{IMM8,0},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x1e,0xff, }}}, -{50,'s','E','!','E',O_ROTXR|O_BYTE,"rotxr.b",1,{IMM8,0},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x1f,0xff, }}}, -{50,'s','E','!','E',O_ROTXR|O_BYTE,"rotxr.b",1,{ABS8,0},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x1f,0xff, }}}, -{49,'s','E','!','E',O_ROTXR|O_WORD,"rotxr.w",1,{IMM16,0},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x1f,0xff, }}}, -{42,'s','E','!','E',O_SHAL|O_BYTE,"shal.b",1,{ABS8,0},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x18,0xff, }}}, -{53,'s','E','!','E',O_ROTXL|O_BYTE,"rotxl.b",1,{ABS8,0},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x1e,0xff, }}}, -{44,'-','B','S','S',O_SCB_NE|O_UNSZ,"scb/ne",2,{RS,PCREL8},3, {{0x06,0xff, },{0xb8,0xf8,RS },{0x00,0x00,PCREL8 }}}, -{46,'-','B','S','S',O_SCB_EQ|O_UNSZ,"scb/eq",2,{RS,PCREL8},3, {{0x07,0xff, },{0xb8,0xf8,RS },{0x00,0x00,PCREL8 }}}, -{41,'s','E','!','E',O_SHAL|O_WORD,"shal.w",1,{IMM16,0},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x18,0xff, }}}, -{52,'s','E','!','E',O_ROTXL|O_WORD,"rotxl.w",1,{IMM16,0},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x1e,0xff, }}}, -{41,'s','E','!','E',O_SHAL|O_WORD,"shal.w",1,{ABS8,0},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x18,0xff, }}}, -{52,'s','E','!','E',O_ROTXL|O_WORD,"rotxl.w",1,{ABS8,0},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x1e,0xff, }}}, -{49,'s','E','!','E',O_ROTXR|O_WORD,"rotxr.w",1,{ABS8,0},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x1f,0xff, }}}, -{48,'-','B','!','!',O_RTD|O_UNSZ,"rtd",1,{IMM16,0},3, {{0x14,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{48,'-','B','!','!',O_RTD|O_UNSZ,"rtd",1,{IMM8,0},2, {{0x14,0xff, },{0x00,0x00,IMM8 }}}, -{42,'s','E','!','E',O_SHAL|O_BYTE,"shal.b",1,{ABS16,0},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x18,0xff, }}}, -{53,'s','E','!','E',O_ROTXL|O_BYTE,"rotxl.b",1,{ABS16,0},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x1e,0xff, }}}, -{50,'s','E','!','E',O_ROTXR|O_BYTE,"rotxr.b",1,{ABS16,0},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x1f,0xff, }}}, -{47,'-','B','!','!',O_RTS|O_UNSZ,"rts",0,{0,0},1, {{0x19,0xff, }}}, -{41,'s','E','!','E',O_SHAL|O_WORD,"shal.w",1,{ABS16,0},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x18,0xff, }}}, -{52,'s','E','!','E',O_ROTXL|O_WORD,"rotxl.w",1,{ABS16,0},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x1e,0xff, }}}, -{49,'s','E','!','E',O_ROTXR|O_WORD,"rotxr.w",1,{ABS16,0},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x1f,0xff, }}}, -{99,'m','I','!','D',O_MOV|O_BYTE,"mov:e.b",2,{IMM8,RD},2, {{0x50,0xf8,RD },{0x00,0x00,IMM8 }}}, -{97,'m','E','!','D',O_MOV|O_BYTE,"mov:f.b",2,{FPIND_D8,RD},2, {{0x80,0xf8,RD },{0x00,0x00,FPIND_D8 }}}, -{96,'m','E','!','D',O_MOV|O_WORD,"mov:f.w",2,{FPIND_D8,RD},2, {{0x88,0xf8,RD },{0x00,0x00,FPIND_D8 }}}, -{97,'m','S','!','E',O_MOV|O_BYTE,"mov:f.b",2,{RS,FPIND_D8},2, {{0x90,0xf8,RS },{0x00,0x00,FPIND_D8 }}}, -{96,'m','S','!','E',O_MOV|O_WORD,"mov:f.w",2,{RS,FPIND_D8},2, {{0x98,0xf8,RS },{0x00,0x00,FPIND_D8 }}}, -{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x80,0xf8,RD }}}, -{55,'s','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x1d,0xff, }}}, -{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNDEC},2, {{0xb0,0xf8,RN },{0x90,0xf8,RS }}}, -{91,'m','I','!','D',O_MOV|O_WORD,"mov:i.w",2,{IMM16,RD},3, {{0x58,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{89,'m','E','!','D',O_MOV|O_BYTE,"mov:l.b",2,{ABS8,RD},2, {{0x60,0xf8,RD },{0x00,0x00,ABS8 }}}, -{88,'m','E','!','D',O_MOV|O_WORD,"mov:l.w",2,{ABS8,RD},2, {{0x68,0xf8,RD },{0x00,0x00,ABS8 }}}, -{86,'m','S','!','E',O_MOV|O_BYTE,"mov:s.b",2,{RS,ABS8},2, {{0x70,0xf8,RS },{0x00,0x00,ABS8 }}}, -{85,'m','S','!','E',O_MOV|O_WORD,"mov:s.w",2,{RS,ABS8},2, {{0x78,0xf8,RS },{0x00,0x00,ABS8 }}}, -{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RN,RD},3, {{0xa0,0xf8,RN },{0x00,0xff, },{0x80,0xf8,RD }}}, -{56,'s','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x1d,0xff, }}}, -{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x80,0xf8,RD }}}, -{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x80,0xf8,RD }}}, -{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNDEC,RD},3, {{0xb0,0xf8,RN },{0x00,0xff, },{0x80,0xf8,RD }}}, -{79,'s','E','!','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0xa8,0xf8,RD }}}, -{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RN},3, {{0xa0,0xf8,RN },{0x00,0xff, },{0x90,0xf8,RS }}}, -{58,'s','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x1c,0xff, }}}, -{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x40,0xf8,RD }}}, -{79,'s','E','!','D',O_MULXU|O_BYTE,"mulxu.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0xa8,0xf8,RD }}}, -{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x14,0xff, }}}, -{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x15,0xff, }}}, -{59,'s','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x1c,0xff, }}}, -{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x40,0xf8,RD }}}, -{78,'s','E','!','D',O_MULXU|O_WORD,"mulxu.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0xa8,0xf8,RD }}}, -{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x14,0xff, }}}, -{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x15,0xff, }}}, -{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x40,0xf8,RD }}}, -{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNDEC},3, {{0xb0,0xf8,RN },{0x00,0xff, },{0x90,0xf8,RS }}}, -{59,'s','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x1c,0xff, }}}, -{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x14,0xff, }}}, -{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x40,0xf8,RD }}}, -{59,'s','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x1c,0xff, }}}, -{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x14,0xff, }}}, -{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x15,0xff, }}}, -{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x40,0xf8,RD }}}, -{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x15,0xff, }}}, -{55,'s','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x1d,0xff, }}}, -{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x14,0xff, }}}, -{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x15,0xff, }}}, -{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x40,0xf8,RD }}}, -{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x14,0xff, }}}, -{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x15,0xff, }}}, -{55,'s','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x1d,0xff, }}}, -{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x40,0xf8,RD }}}, -{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x14,0xff, }}}, -{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x15,0xff, }}}, -{59,'s','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x1c,0xff, }}}, -{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x40,0xf8,RD }}}, -{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x14,0xff, }}}, -{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x15,0xff, }}}, -{55,'s','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x1d,0xff, }}}, -{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x40,0xf8,RD }}}, -{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x14,0xff, }}}, -{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x15,0xff, }}}, -{59,'s','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x1c,0xff, }}}, -{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x40,0xf8,RD }}}, -{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x14,0xff, }}}, -{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x15,0xff, }}}, -{55,'s','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x1d,0xff, }}}, -{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x40,0xf8,RD }}}, -{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x40,0xf8,RD }}}, -{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x14,0xff, }}}, -{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x15,0xff, }}}, -{58,'s','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x1c,0xff, }}}, -{63,'-','J','!','!',O_PJSR|O_UNSZ,"pjsr",1,{ABS24,0},4, {{0x03,0xff, },{0x00,0x00,ABS24 },{0x00,0x00, },{0x00,0x00, }}}, -{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{IMM8,RD},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x40,0xf8,RD }}}, -{66,'s','I','C','C',O_ORC|O_BYTE,"orc.b",2,{IMM8,CRB},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x48,0xf8,CRB }}}, -{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{IMM8,0},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x14,0xff, }}}, -{59,'s','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{IMM8,0},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x1c,0xff, }}}, -{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{ABS8,RD},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x40,0xf8,RD }}}, -{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x80,0xf8,RD }}}, -{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x14,0xff, }}}, -{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x15,0xff, }}}, -{59,'s','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x1c,0xff, }}}, -{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{IMM8,0},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x15,0xff, }}}, -{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{ABS8,0},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x14,0xff, }}}, -{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{ABS8,0},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x15,0xff, }}}, -{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{74,'-','!','!','!',O_NOP|O_UNSZ,"nop",0,{0,0},1, {{0x00,0xff, }}}, -{59,'s','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{ABS8,0},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x1c,0xff, }}}, -{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x40,0xf8,RD }}}, -{65,'s','I','C','C',O_ORC|O_WORD,"orc.w",2,{IMM16,CRW},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x48,0xf8,CRW }}}, -{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{IMM16,0},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x14,0xff, }}}, -{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{IMM16,0},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x15,0xff, }}}, -{58,'s','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{IMM16,0},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x1c,0xff, }}}, -{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x40,0xf8,RD }}}, -{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{ABS8,0},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x14,0xff, }}}, -{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{ABS8,0},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x15,0xff, }}}, -{55,'s','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{ABS8,0},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x1d,0xff, }}}, -{64,'-','J','!','!',O_PJMP|O_UNSZ,"pjmp",1,{RDIND,0},2, {{0x11,0xff, },{0xc0,0xf8,RDIND }}}, -{63,'-','J','!','!',O_PJSR|O_UNSZ,"pjsr",1,{RDIND,0},2, {{0x11,0xff, },{0xc8,0xf8,RDIND }}}, -{62,'-','B','!','!',O_PRTD|O_UNSZ,"prtd",1,{IMM8,0},3, {{0x11,0xff, },{0x14,0xff, },{0x00,0x00,IMM8 }}}, -{61,'-','B','!','!',O_PRTS|O_UNSZ,"prts",0,{0,0},2, {{0x11,0xff, },{0x19,0xff, }}}, -{62,'-','B','!','!',O_PRTD|O_UNSZ,"prtd",1,{IMM16,0},4, {{0x11,0xff, },{0x1c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{64,'-','J','!','!',O_PJMP|O_UNSZ,"pjmp",1,{ABS24,0},4, {{0x13,0xff, },{0x00,0x00,ABS24 },{0x00,0x00, },{0x00,0x00, }}}, -{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{ABS16,RD},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x40,0xf8,RD }}}, -{78,'s','E','!','D',O_MULXU|O_WORD,"mulxu.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0xa8,0xf8,RD }}}, -{58,'s','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x1c,0xff, }}}, -{79,'s','E','!','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0xa8,0xf8,RD }}}, -{78,'s','E','!','D',O_MULXU|O_WORD,"mulxu.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0xa8,0xf8,RD }}}, -{79,'s','E','!','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0xa8,0xf8,RD }}}, -{78,'s','E','!','D',O_MULXU|O_WORD,"mulxu.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0xa8,0xf8,RD }}}, -{79,'s','E','!','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0xa8,0xf8,RD }}}, -{78,'s','E','!','D',O_MULXU|O_WORD,"mulxu.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0xa8,0xf8,RD }}}, -{58,'s','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x1c,0xff, }}}, -{79,'s','E','!','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0xa8,0xf8,RD }}}, -{78,'s','E','!','D',O_MULXU|O_WORD,"mulxu.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0xa8,0xf8,RD }}}, -{79,'s','E','!','D',O_MULXU|O_BYTE,"mulxu.b",2,{IMM8,RD},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0xa8,0xf8,RD }}}, -{79,'s','E','!','D',O_MULXU|O_BYTE,"mulxu.b",2,{ABS8,RD},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0xa8,0xf8,RD }}}, -{78,'s','E','!','D',O_MULXU|O_WORD,"mulxu.w",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0xa8,0xf8,RD }}}, -{78,'s','E','!','D',O_MULXU|O_WORD,"mulxu.w",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0xa8,0xf8,RD }}}, -{58,'s','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{ABS8,0},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x1c,0xff, }}}, -{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,ABS16},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x90,0xf8,RS }}}, -{79,'s','E','!','D',O_MULXU|O_BYTE,"mulxu.b",2,{ABS16,RD},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0xa8,0xf8,RD }}}, -{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNINC},3, {{0xc0,0xf8,RN },{0x00,0xff, },{0x90,0xf8,RS }}}, -{58,'s','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x1c,0xff, }}}, -{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNIND},3, {{0xd0,0xf8,RN },{0x00,0xff, },{0x90,0xf8,RS }}}, -{58,'s','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x1c,0xff, }}}, -{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x00,0xff, },{0x90,0xf8,RS }}}, -{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNIND_D16},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x90,0xf8,RS }}}, -{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x00,0xff, },{0x90,0xf8,RS }}}, -{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,ABS8},4, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x00,0xff, },{0x90,0xf8,RS }}}, -{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNIND,RD},3, {{0xd0,0xf8,RN },{0x00,0xff, },{0x80,0xf8,RD }}}, -{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNINC,RD},3, {{0xc0,0xf8,RN },{0x00,0xff, },{0x80,0xf8,RD }}}, -{56,'s','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x1d,0xff, }}}, -{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{ABS16,RD},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x80,0xf8,RD }}}, -{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNIND_D8,RD},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x00,0xff, },{0x80,0xf8,RD }}}, -{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNIND_D16,RD},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x00,0xff, },{0x80,0xf8,RD }}}, -{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{IMM8,RD},4, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x00,0xff, },{0x80,0xf8,RD }}}, -{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{ABS8,RD},4, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x00,0xff, },{0x80,0xf8,RD }}}, -{56,'s','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x1d,0xff, }}}, -{56,'s','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x1d,0xff, }}}, -{56,'s','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x1d,0xff, }}}, -{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x80,0xf8,RD }}}, -{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x80,0xf8,RD }}}, -{56,'s','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x1d,0xff, }}}, -{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNDEC},2, {{0xb8,0xf8,RN },{0x90,0xf8,RS }}}, -{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNINC},2, {{0xc8,0xf8,RN },{0x90,0xf8,RS }}}, -{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x80,0xf8,RD }}}, -{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNIND},2, {{0xd8,0xf8,RN },{0x90,0xf8,RS }}}, -{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x80,0xf8,RD }}}, -{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNIND_D8},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x90,0xf8,RS }}}, -{56,'s','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{IMM8,0},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x1d,0xff, }}}, -{56,'s','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{ABS8,0},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x1d,0xff, }}}, -{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,ABS8},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x90,0xf8,RS }}}, -{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNDEC},3, {{0xb0,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNDEC},4, {{0xb0,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x80,0xf8,RD }}}, -{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNINC},2, {{0xc0,0xf8,RN },{0x90,0xf8,RS }}}, -{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNINC},3, {{0xc0,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNINC},4, {{0xc0,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x80,0xf8,RD }}}, -{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNIND},2, {{0xd0,0xf8,RN },{0x90,0xf8,RS }}}, -{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNIND},3, {{0xd0,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNIND},4, {{0xd0,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x80,0xf8,RD }}}, -{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNIND_D8},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x90,0xf8,RS }}}, -{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNIND_D8},5, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNIND_D16},6, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x80,0xf8,RD }}}, -{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x90,0xf8,RS }}}, -{55,'s','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x1d,0xff, }}}, -{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RD},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x80,0xf8,RD }}}, -{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{ABS8,RD},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x80,0xf8,RD }}}, -{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,ABS8},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x90,0xf8,RS }}}, -{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,ABS8},4, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,ABS8},5, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x80,0xf8,RD }}}, -{55,'s','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{IMM16,0},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x1d,0xff, }}}, -{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x80,0xf8,RD }}}, -{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{ABS16,RD},5, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x00,0xff, },{0x80,0xf8,RD }}}, -{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,ABS16},5, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x00,0xff, },{0x90,0xf8,RS }}}, -{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,ABS16},5, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x06,0xff, },{0x00,0x00,IMM8 }}}, -{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,ABS16},6, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{ABS16,0},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x14,0xff, }}}, -{56,'s','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{ABS16,0},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x1d,0xff, }}}, -{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x80,0xf8,RD }}}, -{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,ABS16},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x90,0xf8,RS }}}, -{78,'s','E','!','D',O_MULXU|O_WORD,"mulxu.w",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0xa8,0xf8,RD }}}, -{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{ABS16,0},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x14,0xff, }}}, -{55,'s','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{ABS16,0},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x1d,0xff, }}}, -{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{ABS16,0},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x15,0xff, }}}, -{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x40,0xf8,RD }}}, -{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{ABS16,0},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x15,0xff, }}}, -{58,'s','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{ABS16,0},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x1c,0xff, }}}, -{59,'s','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{ABS16,0},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x1c,0xff, }}}, -{125,'a','D','I','!',O_CMP|O_BYTE,"cmp:e.b",2,{IMM8,RD},2, {{0x40,0xf8,RD },{0x00,0x00,IMM8 }}}, -{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x70,0xf8,RD }}}, -{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RN},3, {{0xa0,0xf8,RN },{0x04,0xff, },{0x00,0x00,IMM8 }}}, -{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x70,0xf8,RD }}}, -{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RN},4, {{0xa0,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RN,CRB},2, {{0xa0,0xf8,RN },{0x88,0xf8,CRB }}}, -{120,'a','D','I','!',O_CMP|O_WORD,"cmp:i.w",2,{IMM16,RD},3, {{0x48,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0xb8,0xf8,RD }}}, -{119,'s','D','!','!',O_DAAD|O_UNSZ,"daad",2,{RS,RD},3, {{0xa0,0xf8,RS },{0x00,0xff, },{0xa0,0xf8,RD }}}, -{115,'s','D','!','!',O_DSUB|O_UNSZ,"dsub",2,{RS,RD},3, {{0xa0,0xf8,RS },{0x00,0xff, },{0xb0,0xf8,RD }}}, -{113,'s','D','!','D',O_EXTS|O_BYTE,"exts.b",1,{RD,0},2, {{0xa0,0xf8,RD },{0x11,0xff, }}}, -{111,'s','D','!','D',O_EXTU|O_BYTE,"extu.b",1,{RD,0},2, {{0xa0,0xf8,RD },{0x12,0xff, }}}, -{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0xb8,0xf8,RD }}}, -{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNIND_D8,CRB},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x88,0xf8,CRB }}}, -{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNIND_D16,CRB},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x88,0xf8,CRB }}}, -{110,'-','B','!','!',O_JMP|O_UNSZ,"jmp",1,{ABS16,0},3, {{0x10,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, }}}, -{110,'-','B','!','!',O_JMP|O_UNSZ,"jmp",1,{RDIND,0},2, {{0x11,0xff, },{0xd0,0xf8,RDIND }}}, -{109,'-','B','!','!',O_JSR|O_UNSZ,"jsr",1,{RDIND,0},2, {{0x11,0xff, },{0xd8,0xf8,RDIND }}}, -{110,'-','B','!','!',O_JMP|O_UNSZ,"jmp",1,{RDIND_D8,0},3, {{0x11,0xff, },{0xe0,0xf8,RDIND_D8 },{0x00,0x00, }}}, -{109,'-','B','!','!',O_JSR|O_UNSZ,"jsr",1,{RDIND_D8,0},3, {{0x11,0xff, },{0xe8,0xf8,RDIND_D8 },{0x00,0x00, }}}, -{110,'-','B','!','!',O_JMP|O_UNSZ,"jmp",1,{RDIND_D16,0},4, {{0x11,0xff, },{0xf0,0xf8,RDIND_D16 },{0x00,0x00, },{0x00,0x00, }}}, -{109,'-','B','!','!',O_JSR|O_UNSZ,"jsr",1,{RDIND_D16,0},4, {{0x11,0xff, },{0xf8,0xf8,RDIND_D16 },{0x00,0x00, },{0x00,0x00, }}}, -{109,'-','B','!','!',O_JSR|O_UNSZ,"jsr",1,{ABS16,0},3, {{0x18,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, }}}, -{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{ABS16,CRB},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x88,0xf8,CRB }}}, -{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0xb8,0xf8,RD }}}, -{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0xb8,0xf8,RD }}}, -{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNINC,CRB},2, {{0xc0,0xf8,RN },{0x88,0xf8,CRB }}}, -{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0xb8,0xf8,RD }}}, -{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0xb8,0xf8,RD }}}, -{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNIND,CRB},2, {{0xd0,0xf8,RN },{0x88,0xf8,CRB }}}, -{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0xb8,0xf8,RD }}}, -{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0xb8,0xf8,RD }}}, -{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0xb8,0xf8,RD }}}, -{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0xb8,0xf8,RD }}}, -{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0xb8,0xf8,RD }}}, -{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0xb8,0xf8,RD }}}, -{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{IMM8,CRB},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x88,0xf8,CRB }}}, -{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{IMM8,RD},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0xb8,0xf8,RD }}}, -{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{ABS8,RD},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0xb8,0xf8,RD }}}, -{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0xb8,0xf8,RD }}}, -{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{ABS16,RD},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0xb8,0xf8,RD }}}, -{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0xb8,0xf8,RD }}}, -{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{ABS8,CRB},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x88,0xf8,CRB }}}, -{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0xb8,0xf8,RD }}}, -{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x70,0xf8,RD }}}, -{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNDEC,CRB},2, {{0xb0,0xf8,RN },{0x88,0xf8,CRB }}}, -{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RNDEC},3, {{0xb0,0xf8,RN },{0x04,0xff, },{0x00,0x00,IMM8 }}}, -{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RNDEC},4, {{0xb0,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x70,0xf8,RD }}}, -{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x70,0xf8,RD }}}, -{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RNINC},3, {{0xc0,0xf8,RN },{0x04,0xff, },{0x00,0x00,IMM8 }}}, -{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RNINC},4, {{0xc0,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x70,0xf8,RD }}}, -{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x70,0xf8,RD }}}, -{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RNIND},3, {{0xd0,0xf8,RN },{0x04,0xff, },{0x00,0x00,IMM8 }}}, -{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RNIND},4, {{0xd0,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, -{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x70,0xf8,RD }}}, -{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x70,0xf8,RD }}}, -{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x04,0xff, },{0x00,0x00,IMM8 }}}, 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{{0xb0,0xf8,RN },{0xf0,0xf0,IMM4 }}}, -{140,'b','E','S','E',O_BTST|O_BYTE,"btst.b",2,{RS,RNDEC},2, {{0xb0,0xf8,RN },{0x78,0xf8,RS }}}, -{139,'b','E','I','E',O_BTST|O_WORD,"btst.w",2,{IMM4,RNDEC},2, {{0xb8,0xf8,RN },{0xf0,0xf0,IMM4 }}}, -{139,'b','E','S','E',O_BTST|O_WORD,"btst.w",2,{RS,RNDEC},2, {{0xb8,0xf8,RN },{0x78,0xf8,RS }}}, -{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x13,0xff, }}}, -{140,'b','E','I','E',O_BTST|O_BYTE,"btst.b",2,{IMM4,RNINC},2, {{0xc0,0xf8,RN },{0xf0,0xf0,IMM4 }}}, -{140,'b','E','S','E',O_BTST|O_BYTE,"btst.b",2,{RS,RNINC},2, {{0xc0,0xf8,RN },{0x78,0xf8,RS }}}, -{139,'b','E','I','E',O_BTST|O_WORD,"btst.w",2,{IMM4,RNINC},2, {{0xc8,0xf8,RN },{0xf0,0xf0,IMM4 }}}, -{139,'b','E','S','E',O_BTST|O_WORD,"btst.w",2,{RS,RNINC},2, {{0xc8,0xf8,RN },{0x78,0xf8,RS }}}, -{140,'b','E','I','E',O_BTST|O_BYTE,"btst.b",2,{IMM4,RNIND},2, {{0xd0,0xf8,RN },{0xf0,0xf0,IMM4 }}}, -{140,'b','E','S','E',O_BTST|O_BYTE,"btst.b",2,{RS,RNIND},2, {{0xd0,0xf8,RN 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-{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{IMM16,0},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x13,0xff, }}}, -{139,'b','E','I','E',O_BTST|O_WORD,"btst.w",2,{IMM4,ABS8},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0xf0,0xf0,IMM4 }}}, -{139,'b','E','S','E',O_BTST|O_WORD,"btst.w",2,{RS,ABS8},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x78,0xf8,RS }}}, -{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{ABS8,0},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x13,0xff, }}}, -{140,'b','E','I','E',O_BTST|O_BYTE,"btst.b",2,{IMM4,ABS16},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0xf0,0xf0,IMM4 }}}, -{140,'b','E','S','E',O_BTST|O_BYTE,"btst.b",2,{RS,ABS16},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x78,0xf8,RS }}}, -{131,'c','!','!','E',O_CLR|O_BYTE,"clr.b",1,{ABS16,0},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x13,0xff, }}}, -{139,'b','E','I','E',O_BTST|O_WORD,"btst.w",2,{IMM4,ABS16},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0xf0,0xf0,IMM4 }}}, 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-{179,'-','B','!','!',O_BLE|O_WORD,"ble.w",1,{PCREL16,0},3, {{0x3f,0xff, },{0x00,0x00,PCREL16 },{0x00,0x00, }}}, -/* -RN,RD 'm','E','D','D' -CRB,RN 's','C','!','E' -RN,RD 'm','E','D','D' -RNDEC,RD 'm','E','D','D' -CRB,RNDEC 's','C','!','E' -RNDEC,RD 'm','E','D','D' -RNINC,RD 'm','E','D','D' -CRB,RNINC 's','C','!','E' -RNINC,RD 'm','E','D','D' -RNIND,RD 'm','E','D','D' -CRB,RNIND 's','C','!','E' -RNIND,RD 'm','E','D','D' -RNIND_D8,RD 'a','E','D','D' -RNIND_D8,RD 'm','E','D','D' -CRB,RNIND_D8 's','C','!','E' -RNIND_D8,RD 'm','E','D','D' -RNIND_D16,RD 'a','E','D','D' -RNIND_D16,RD 'm','E','D','D' -CRB,RNIND_D16 's','C','!','E' -RNIND_D16,RD 'm','E','D','D' -RN,RD 'm','E','D','D' -RNDEC,RD 'm','E','D','D' -RNIND,RD 'm','E','D','D' -RNINC,RD 'm','E','D','D' -RNIND_D8,RD 'm','E','D','D' -ABS8,RD 'm','E','D','D' -IMM16,RD 'm','E','D','D' -ABS16,RD 'm','E','D','D' -RNIND_D16,RD 'm','E','D','D' -RN,RD 'a','E','D','D' -RS,RD '-','X','!','!' -RN,0 'm','E','!','!' -RS,RD '-','X','!','!' -RN,0 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-IMM16,RD 's','E','D','D' -ABS16,RD 's','E','D','D' -RNIND_D16,RD 's','E','D','D' -ABS8,CRB 's','E','!','C' -ABS8,RD 's','E','D','D' -IMM16,RD 'a','D','I','!' -RNDEC,RD 'a','D','E','!' -RNDEC,CRB 's','E','!','C' -IMM8,RNDEC 'a','E','I','!' -IMM16,RNDEC 'a','E','I','!' -RNDEC,RD 'a','D','E','!' -RNINC,RD 'a','D','E','!' -IMM8,RNINC 'a','E','I','!' -IMM16,RNINC 'a','E','I','!' -RNINC,RD 'a','D','E','!' -RNIND,RD 'a','D','E','!' -IMM8,RNIND 'a','E','I','!' -IMM16,RNIND 'a','E','I','!' -RNIND,RD 'a','D','E','!' -RNIND_D8,RD 'a','D','E','!' -IMM8,RNIND_D8 'a','E','I','!' -IMM16,RNIND_D8 'a','E','I','!' -RNIND_D8,RD 'a','D','E','!' -RNIND_D16,RD 'a','D','E','!' -IMM8,RNIND_D16 'a','E','I','!' -IMM16,RNIND_D16 'a','E','I','!' -RNIND_D16,RD 'a','D','E','!' -SPINC,RLIST '-','E','!','C' -IMM8,RD 'a','D','E','!' -ABS8,RD 'a','D','E','!' -IMM8,ABS8 'a','E','I','!' -IMM16,ABS8 'a','E','I','!' -IMM16,RD 'a','D','E','!' -IMM16,CRW 's','E','!','C' -ABS8,RD 'a','D','E','!' -ABS16,RD 'a','D','E','!' -IMM8,ABS16 'a','E','I','!' -IMM16,ABS16 'a','E','I','!' -ABS16,RD 'a','D','E','!' -FP,IMM16 '-','S','I','!' -RN,RD 'a','D','E','!' -RNIND,RD 'a','D','E','!' -RNINC,RD 'a','D','E','!' -RNDEC,RD 'a','D','E','!' -RNIND_D8,RD 'a','D','E','!' -ABS8,RD 'a','D','E','!' -IMM16,RNINC 'a','E','I','!' -IMM16,RNIND 'a','E','I','!' -IMM16,RN 'a','E','I','!' -IMM16,RNDEC 'a','E','I','!' -IMM16,RD 'a','D','E','!' -ABS16,RD 'a','D','E','!' -RNIND_D16,RD 'a','D','E','!' -IMM16,RNIND_D8 'a','E','I','!' -IMM16,ABS8 'a','E','I','!' -IMM16,RNIND_D16 'a','E','I','!' -IMM16,ABS16 'a','E','I','!' -FP,IMM8 '-','S','I','!' -IMM8,RD 'a','D','I','!' -RN,RD 'a','D','E','!' -RNDEC,RD 'a','D','E','!' -RNINC,RD 'a','D','E','!' -RNIND,RD 'a','D','E','!' -IMM16,RD 'a','D','I','!' -RNIND_D8,RD 'a','D','E','!' -ABS8,RD 'a','D','E','!' -IMM16,RNINC 'a','E','I','!' -IMM16,RNDEC 'a','E','I','!' -IMM16,RNIND 'a','E','I','!' -RNIND_D16,RD 'a','D','E','!' -ABS16,RD 'a','D','E','!' -IMM16,RD 'a','D','E','!' -IMM16,RN 'a','E','I','!' -IMM16,RNIND_D8 'a','E','I','!' -IMM16,ABS8 'a','E','I','!' -IMM16,RNIND_D16 'a','E','I','!' -IMM16,ABS16 'a','E','I','!' -RN,RD 'a','D','E','!' -RNDEC,RD 'a','D','E','!' -RNINC,RD 'a','D','E','!' -IMM8,RD 'a','D','I','!' -RNIND,RD 'a','D','E','!' -IMM8,RN 'a','E','I','!' -IMM8,RNIND 'a','E','I','!' -IMM8,RNINC 'a','E','I','!' -IMM8,RNDEC 'a','E','I','!' -ABS8,RD 'a','D','E','!' -RNIND_D8,RD 'a','D','E','!' -IMM8,RD 'a','D','E','!' -IMM8,ABS8 'a','E','I','!' -ABS16,RD 'a','D','E','!' -IMM8,RNIND_D8 'a','E','I','!' -RNIND_D16,RD 'a','D','E','!' -IMM8,ABS16 'a','E','I','!' -IMM8,RNIND_D16 'a','E','I','!' -RN,RD 'a','D','E','!' -IMM8,RD 'a','D','I','!' -RNINC,RD 'a','D','E','!' -RNIND,RD 'a','D','E','!' -RNDEC,RD 'a','D','E','!' -IMM16,RD 'a','D','I','!' -RNIND_D8,RD 'a','D','E','!' -ABS8,RD 'a','D','E','!' -IMM16,RN 'a','E','I','!' -IMM16,RNDEC 'a','E','I','!' -IMM16,RNIND 'a','E','I','!' -RNIND_D16,RD 'a','D','E','!' -IMM16,RNINC 'a','E','I','!' -ABS16,RD 'a','D','E','!' -IMM16,RD 'a','D','E','!' -IMM16,ABS8 'a','E','I','!' -IMM16,RNIND_D8 'a','E','I','!' -IMM16,ABS16 'a','E','I','!' -IMM16,RNIND_D16 'a','E','I','!' -IMM4,RN 'b','E','I','E' -IMM4,RN 'b','E','I','E' -RS,RN 'b','E','S','E' -RS,RN 'b','E','S','E' -RN,0 'c','!','!','E' -IMM4,RN 'b','E','I','E' -IMM4,RN 'b','E','I','E' -RNDEC,0 'c','!','!','E' -RNINC,0 'c','!','!','E' -RNIND,0 'c','!','!','E' -RS,RNIND 'b','E','S','E' -RNIND_D8,0 'c','!','!','E' -IMM4,RNIND_D16 'b','E','I','E' -RS,RNIND_D16 'b','E','S','E' -RNIND_D16,0 'c','!','!','E' -RNIND_D16,0 'c','!','!','E' -IMM8,0 'c','!','!','E' -ABS8,0 'c','!','!','E' -RN,0 'c','!','!','E' -RNIND,0 'c','!','!','E' -RNINC,0 'c','!','!','E' -RNDEC,0 'c','!','!','E' -ABS8,0 'c','!','!','E' -RNIND_D8,0 'c','!','!','E' -IMM16,0 'c','!','!','E' -ABS16,0 'c','!','!','E' -RNIND_D16,0 'c','!','!','E' -IMM4,ABS8 'b','E','I','E' -RS,ABS8 'b','E','S','E' -PCREL8,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -RS,RN 'b','E','S','E' -IMM4,RNDEC 'b','E','I','E' -PCREL8,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -RS,RNDEC 'b','E','S','E' -IMM4,RNDEC 'b','E','I','E' -RS,RNDEC 'b','E','S','E' -RNDEC,0 'c','!','!','E' -IMM4,RNINC 'b','E','I','E' -RS,RNINC 'b','E','S','E' -IMM4,RNINC 'b','E','I','E' -RS,RNINC 'b','E','S','E' -IMM4,RNIND 'b','E','I','E' -RS,RNIND 'b','E','S','E' -IMM4,RNIND 'b','E','I','E' -IMM4,RNIND_D8 'b','E','I','E' -RS,RNIND_D8 'b','E','S','E' -IMM4,RNIND_D8 'b','E','I','E' -RS,RNIND_D8 'b','E','S','E' -RNIND_D8,0 'c','!','!','E' -IMM4,RNIND_D16 'b','E','I','E' -RS,RNIND_D16 'b','E','S','E' -IMM16,0 'c','!','!','E' -IMM4,ABS8 'b','E','I','E' -RS,ABS8 'b','E','S','E' -ABS8,0 'c','!','!','E' -IMM4,ABS16 'b','E','I','E' -RS,ABS16 'b','E','S','E' -ABS16,0 'c','!','!','E' -IMM4,ABS16 'b','E','I','E' -RS,ABS16 'b','E','S','E' -ABS16,0 'c','!','!','E' -PCREL8,0 '-','B','!','!' -PCREL8,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -RS,RN 'b','E','S','E' -IMM4,RNDEC 'b','E','I','E' -IMM4,RNIND 'b','E','I','E' -RS,RNIND 'b','E','S','E' -RS,RNINC 'b','E','S','E' -RS,RNDEC 'b','E','S','E' -IMM4,RN 'b','E','I','E' -IMM4,RNINC 'b','E','I','E' -RS,RNIND_D8 'b','E','S','E' -IMM4,ABS8 'b','E','I','E' -RS,ABS8 'b','E','S','E' -IMM4,RNIND_D8 'b','E','I','E' -IMM4,ABS16 'b','E','I','E' -RS,RNIND_D16 'b','E','S','E' -RS,ABS16 'b','E','S','E' -IMM4,RNDEC 'b','E','I','E' -PCREL16,0 '-','B','!','!' -PCREL8,0 '-','B','!','!' -PCREL8,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -IMM4,RNIND_D16 'b','E','I','E' -RS,RNDEC 'b','E','S','E' -PCREL8,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -RS,RN 'b','E','S','E' -RN,0 'c','!','!','E' -IMM4,RNDEC 'b','E','I','E' -RS,RNDEC 'b','E','S','E' -IMM4,RNINC 'b','E','I','E' -RS,RNINC 'b','E','S','E' -IMM4,RNINC 'b','E','I','E' -RS,RNINC 'b','E','S','E' -RNINC,0 'c','!','!','E' -IMM4,RNIND 'b','E','I','E' -RS,RNIND 'b','E','S','E' -IMM4,RNIND 'b','E','I','E' -RS,RNIND 'b','E','S','E' -RNIND,0 'c','!','!','E' -IMM4,RNIND_D8 'b','E','I','E' -RS,RNIND_D8 'b','E','S','E' -IMM4,RNIND_D8 'b','E','I','E' -RS,RNIND_D8 'b','E','S','E' -IMM4,RNIND_D16 'b','E','I','E' -RS,RNIND_D16 'b','E','S','E' -IMM4,RNIND_D16 'b','E','I','E' -RS,RNIND_D16 'b','E','S','E' -IMM4,ABS8 'b','E','I','E' -RS,ABS8 'b','E','S','E' -IMM4,ABS8 'b','E','I','E' -RS,ABS8 'b','E','S','E' -PCREL8,0 '-','B','!','!' -IMM4,ABS16 'b','E','I','E' -RS,ABS16 'b','E','S','E' -IMM4,ABS16 'b','E','I','E' -RS,ABS16 'b','E','S','E' -PCREL16,0 '-','B','!','!' -RS,RN 'b','E','S','E' -IMM4,RN 'b','E','I','E' -IMM4,RNIND 'b','E','I','E' -RS,RNIND 'b','E','S','E' -RS,RNINC 'b','E','S','E' -RS,RNDEC 'b','E','S','E' -IMM4,RNINC 'b','E','I','E' -IMM4,RNDEC 'b','E','I','E' -RS,RNIND_D8 'b','E','S','E' -IMM4,RNIND_D8 'b','E','I','E' -RS,ABS8 'b','E','S','E' -IMM4,ABS8 'b','E','I','E' -IMM4,ABS16 'b','E','I','E' -RS,RNIND_D16 'b','E','S','E' -RS,ABS16 'b','E','S','E' -IMM4,RNIND_D16 'b','E','I','E' -IMM4,RN 'b','E','I','E' -IMM4,RN 'b','E','I','E' -PCREL8,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -QIM,RN 'a','I','E','E' -RN,RD '-','E','D','D' -PCREL8,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -RN,RD 'a','E','D','D' -RN,RD 'm','E','D','D' -RS,RN 'b','E','S','E' -PCREL8,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -RS,RN 'b','E','S','E' -RN,RD 'a','E','D','D' -IMM4,RN 'b','E','I','E' -IMM4,RN 'b','E','I','E' -QIM,RN 'a','I','E','E' -RN,RD 'a','E','D','D' -RN,RD '-','E','D','D' -RN,RD 'm','E','D','D' -RS,RN 'b','E','S','E' -RS,RN 'b','E','S','E' -RN,RD 'a','E','D','D' -IMM4,RNDEC 'b','E','I','E' -IMM4,RNDEC 'b','E','I','E' -QIM,RNDEC 'a','I','E','E' -RNDEC,RD 'a','E','D','D' -RNDEC,RD '-','E','D','D' -RNDEC,RD 'm','E','D','D' -RS,RNDEC 'b','E','S','E' -RS,RNDEC 'b','E','S','E' -RNDEC,RD 'a','E','D','D' -IMM4,RNDEC 'b','E','I','E' -IMM4,RNDEC 'b','E','I','E' -QIM,RNDEC 'a','I','E','E' -RNDEC,RD 'a','E','D','D' -RNDEC,RD '-','E','D','D' -RNDEC,RD 'm','E','D','D' -RS,RNDEC 'b','E','S','E' -RS,RNDEC 'b','E','S','E' -RNDEC,RD 'a','E','D','D' -RNINC,RD 'a','E','D','D' -RNINC,RD 'm','E','D','D' -IMM4,RNINC 'b','E','I','E' -RS,RN 'b','E','S','E' -RS,RNIND 'b','E','S','E' -IMM4,RNIND 'b','E','I','E' -IMM4,RN 'b','E','I','E' -RS,RNINC 'b','E','S','E' -RS,RNDEC 'b','E','S','E' -IMM4,RNDEC 'b','E','I','E' -IMM4,RNINC 'b','E','I','E' -RS,ABS8 'b','E','S','E' -IMM4,ABS8 'b','E','I','E' -RS,RNIND_D8 'b','E','S','E' -IMM4,RNIND_D8 'b','E','I','E' -RS,RNIND_D16 'b','E','S','E' -IMM4,ABS16 'b','E','I','E' -RS,ABS16 'b','E','S','E' -IMM4,RNIND_D16 'b','E','I','E' -IMM4,RNINC 'b','E','I','E' -IMM4,RNINC 'b','E','I','E' -PCREL8,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -RNINC,RD '-','E','D','D' -RS,RNINC 'b','E','S','E' -PCREL8,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -QIM,RNINC 'a','I','E','E' -RS,RNINC 'b','E','S','E' -PCREL8,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -RNINC,RD 'a','E','D','D' -IMM4,RNINC 'b','E','I','E' -RNINC,RD 'a','E','D','D' -PCREL16,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -PCREL8,0 '-','B','!','!' -PCREL8,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -RS,RNINC 'b','E','S','E' -IMM4,RNIND 'b','E','I','E' -PCREL8,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -PCREL8,0 '-','B','!','!' -PCREL8,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -IMM4,RNIND 'b','E','I','E' -PCREL8,0 '-','B','!','!' -RNINC,RD 'a','E','D','D' -PCREL16,0 '-','B','!','!' -RNINC,RD '-','E','D','D' -RS,RNINC 'b','E','S','E' -PCREL8,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -RNINC,RD 'm','E','D','D' -PCREL8,0 '-','B','!','!' -PCREL8,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -PCREL8,0 '-','B','!','!' -PCREL8,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -QIM,RNINC 'a','I','E','E' -QIM,RNIND 'a','I','E','E' -PCREL8,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -RNIND,RD 'a','E','D','D' -RNIND,RD '-','E','D','D' -PCREL8,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -RNIND,RD 'm','E','D','D' -RS,RNIND 'b','E','S','E' -RS,RNIND 'b','E','S','E' -RNIND,RD 'a','E','D','D' -IMM4,RNIND 'b','E','I','E' -IMM4,RNIND 'b','E','I','E' -QIM,RNIND 'a','I','E','E' -RNIND,RD 'a','E','D','D' -RNIND,RD '-','E','D','D' -RNIND,RD 'm','E','D','D' -RS,RNIND 'b','E','S','E' -RS,RNIND 'b','E','S','E' -RNIND,RD 'a','E','D','D' -IMM4,RNIND_D8 'b','E','I','E' -IMM4,RNIND_D8 'b','E','I','E' -QIM,RNIND_D8 'a','I','E','E' -RNIND_D8,RD 'a','E','D','D' -RNIND_D8,RD '-','E','D','D' -RNIND_D8,RD 'm','E','D','D' -RS,RNIND_D8 'b','E','S','E' -RS,RNIND_D8 'b','E','S','E' -RNIND_D8,RD 'a','E','D','D' -IMM4,RNIND_D8 'b','E','I','E' -IMM4,RNIND_D8 'b','E','I','E' -QIM,RNIND_D8 'a','I','E','E' -RNIND_D8,RD 'a','E','D','D' -RNIND_D8,RD '-','E','D','D' -RNIND_D8,RD 'm','E','D','D' -RS,RNIND_D8 'b','E','S','E' -IMM4,RNIND_D16 'b','E','I','E' -QIM,RNIND_D16 'a','I','E','E' -RS,RNIND_D16 'b','E','S','E' -RS,RN 'b','E','S','E' -IMM4,RNDEC 'b','E','I','E' -IMM4,RNINC 'b','E','I','E' -RS,RNIND 'b','E','S','E' -RS,RNINC 'b','E','S','E' -RS,RNDEC 'b','E','S','E' -IMM4,RNIND 'b','E','I','E' -IMM4,RN 'b','E','I','E' -RS,RNIND_D8 'b','E','S','E' -IMM4,ABS8 'b','E','I','E' -RS,ABS8 'b','E','S','E' -IMM4,RNIND_D8 'b','E','I','E' -IMM4,ABS16 'b','E','I','E' -RS,RNIND_D16 'b','E','S','E' -RS,ABS16 'b','E','S','E' -IMM4,RNIND_D16 'b','E','I','E' -RS,RNIND_D8 'b','E','S','E' -RNIND_D16,RD 'a','E','D','D' -PCREL8,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -RNIND_D16,RD 'a','E','D','D' -RNIND_D16,RD 'a','E','D','D' -IMM8,CRB 's','I','S','S' -IMM16,CRW 's','I','S','S' -RNIND_D8,RD 'a','E','D','D' -IMM4,RNIND_D16 'b','E','I','E' -RNIND_D16,RD '-','E','D','D' -RNIND_D16,RD 'm','E','D','D' -RS,RNIND_D16 'b','E','S','E' -IMM4,RNIND_D16 'b','E','I','E' -IMM4,RNIND_D16 'b','E','I','E' -QIM,RNIND_D16 'a','I','E','E' -RNIND_D16,RD '-','E','D','D' -RNIND_D16,RD 'm','E','D','D' -RS,RNIND_D16 'b','E','S','E' -RS,RNIND_D16 'b','E','S','E' -RNIND_D16,RD 'a','E','D','D' -IMM8,RD 'a','E','D','D' -IMM8,RD '-','E','D','D' -IMM8,RD 'm','E','D','D' -IMM8,CRB 's','I','S','S' -IMM8,RD 'a','E','D','D' -RN,RD 'm','E','D','D' -RNDEC,RD 'm','E','D','D' -RNINC,RD 'm','E','D','D' -RNIND,RD 'm','E','D','D' -ABS8,RD 'm','E','D','D' -RNIND_D8,RD 'm','E','D','D' -IMM16,RD 'm','E','D','D' -ABS16,RD 'm','E','D','D' -RNIND_D16,RD 'm','E','D','D' -IMM4,ABS8 'b','E','I','E' -IMM4,ABS8 'b','E','I','E' -QIM,ABS8 'a','I','E','E' -ABS8,RD 'a','E','D','D' -ABS8,RD '-','E','D','D' -ABS8,RD 'm','E','D','D' -RS,ABS8 'b','E','S','E' -RS,ABS8 'b','E','S','E' -ABS8,RD 'a','E','D','D' -IMM16,RD 'a','E','D','D' -IMM16,RD '-','E','D','D' -IMM16,RD 'm','E','D','D' -IMM16,CRW 's','I','S','S' -IMM16,RD 'a','E','D','D' -IMM4,ABS8 'b','E','I','E' -QIM,ABS8 'a','I','E','E' -ABS8,RD 'a','E','D','D' -ABS8,RD '-','E','D','D' -RN,RD 'a','E','D','D' -RNINC,RD 'a','E','D','D' -RNIND,RD 'a','E','D','D' -RNDEC,RD 'a','E','D','D' -ABS8,RD 'a','E','D','D' -RNIND_D8,RD 'a','E','D','D' -ABS16,RD 'a','E','D','D' -IMM16,RD 'a','E','D','D' -RNIND_D16,RD 'a','E','D','D' -0,0 '-','!','!','!' -IMM4,ABS8 'b','E','I','E' -ABS8,RD 'm','E','D','D' -RS,ABS8 'b','E','S','E' -RS,ABS8 'b','E','S','E' -ABS8,RD 'a','E','D','D' -IMM4,ABS16 'b','E','I','E' -ABS16,RD 'a','E','D','D' -ABS16,RD '-','E','D','D' -ABS16,RD 'm','E','D','D' -RS,ABS16 'b','E','S','E' -ABS16,RD 'a','E','D','D' -IMM4,ABS16 'b','E','I','E' -ABS16,RD '-','E','D','D' -ABS16,RD 'm','E','D','D' -RS,ABS16 'b','E','S','E' -ABS16,RD 'a','E','D','D' -PCREL8,0 '-','B','!','!' -RN,RD '-','E','D','D' -RNIND,RD '-','E','D','D' -RNINC,RD '-','E','D','D' -RNDEC,RD '-','E','D','D' -ABS8,RD '-','E','D','D' -RNIND_D8,RD '-','E','D','D' -ABS16,RD '-','E','D','D' -IMM16,RD '-','E','D','D' -RNIND_D16,RD '-','E','D','D' -IMM4,ABS16 'b','E','I','E' -QIM,ABS16 'a','I','E','E' -RS,ABS16 'b','E','S','E' -IMM4,ABS16 'b','E','I','E' -QIM,ABS16 'a','I','E','E' -ABS16,RD 'a','E','D','D' -RS,ABS16 'b','E','S','E' -PCREL8,0 '-','B','!','!' -PCREL8,0 '-','B','!','!' -PCREL8,0 '-','B','!','!' -PCREL8,0 '-','B','!','!' -PCREL8,0 '-','B','!','!' -PCREL8,0 '-','B','!','!' -PCREL8,0 '-','B','!','!' -PCREL8,0 '-','B','!','!' -PCREL8,0 '-','B','!','!' -QIM,RN 'a','I','E','E' -QIM,RNDEC 'a','I','E','E' -QIM,RNINC 'a','I','E','E' -QIM,RNIND 'a','I','E','E' -QIM,ABS8 'a','I','E','E' -QIM,RNIND_D8 'a','I','E','E' -QIM,ABS16 'a','I','E','E' -QIM,RNIND_D16 'a','I','E','E' -PCREL8,0 '-','B','!','!' -PCREL8,0 '-','B','!','!' -PCREL8,0 '-','B','!','!' -PCREL8,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -PCREL16,0 '-','B','!','!' -RN,RD 'a','E','D','D' -RNDEC,RD 'a','E','D','D' -RNINC,RD 'a','E','D','D' -RNIND,RD 'a','E','D','D' -ABS8,RD 'a','E','D','D' -RNIND_D8,RD 'a','E','D','D' -ABS16,RD 'a','E','D','D' -IMM16,RD 'a','E','D','D' -RNIND_D16,RD 'a','E','D','D' -RN,RD 'a','E','D','D' -QIM,RN 'a','I','E','E' -QIM,RNIND 'a','I','E','E' -RNDEC,RD 'a','E','D','D' -QIM,RNDEC 'a','I','E','E' -QIM,RNINC 'a','I','E','E' -RNIND,RD 'a','E','D','D' -RNINC,RD 'a','E','D','D' -QIM,ABS8 'a','I','E','E' -QIM,RNIND_D8 'a','I','E','E' -ABS8,RD 'a','E','D','D' -RNIND_D8,RD 'a','E','D','D' -ABS16,RD 'a','E','D','D' -QIM,RNIND_D16 'a','I','E','E' -IMM16,RD 'a','E','D','D' -QIM,ABS16 'a','I','E','E' -RNIND_D16,RD 'a','E','D','D' -RN,RD 'a','E','D','D' -QIM,RN 'a','I','E','E' -QIM,RNINC 'a','I','E','E' -RNDEC,RD 'a','E','D','D' -QIM,RNIND 'a','I','E','E' -RNINC,RD 'a','E','D','D' -QIM,RNDEC 'a','I','E','E' -RNIND,RD 'a','E','D','D' -QIM,RNIND_D8 'a','I','E','E' -IMM8,RD 'a','E','D','D' -QIM,ABS8 'a','I','E','E' -ABS8,RD 'a','E','D','D' -RNIND_D8,RD 'a','E','D','D' -QIM,RNIND_D16 'a','I','E','E' -QIM,ABS16 'a','I','E','E' -ABS16,RD 'a','E','D','D' -RNIND_D16,RD 'a','E','D','D' -RN,RD 'a','E','D','D' -QIM,RN 'a','I','E','E' -QIM,RNDEC 'a','I','E','E' -RNDEC,RD 'a','E','D','D' -QIM,RNIND 'a','I','E','E' -QIM,RNINC 'a','I','E','E' -RNINC,RD 'a','E','D','D' -RNIND,RD 'a','E','D','D' -QIM,ABS8 'a','I','E','E' -QIM,RNIND_D8 'a','I','E','E' -RNIND_D8,RD 'a','E','D','D' -ABS8,RD 'a','E','D','D' -ABS16,RD 'a','E','D','D' -QIM,RNIND_D16 'a','I','E','E' -IMM16,RD 'a','E','D','D' -QIM,ABS16 'a','I','E','E' -RNIND_D16,RD 'a','E','D','D' -*/ -0,0,0} -#endif -; -#endif diff --git a/opcodes/hppa-dis.c b/opcodes/hppa-dis.c deleted file mode 100644 index f71221c75f1..00000000000 --- a/opcodes/hppa-dis.c +++ /dev/null @@ -1,989 +0,0 @@ -/* Disassembler for the PA-RISC. Somewhat derived from sparc-pinsn.c. - Copyright 1989, 1990, 1992, 1993 Free Software Foundation, Inc. - - Contributed by the Center for Software Science at the - University of Utah (pa-gdb-bugs@cs.utah.edu). - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -/* Define this name if you want to restrict the - disassembler to host-native formats. */ - -/* #define LOCAL_ONLY 1 */ - -#include <ansidecl.h> -#include "sysdep.h" -#include "dis-asm.h" -#include "libhppa.h" -#include "opcode/hppa.h" - -#ifdef LOCAL_ONLY -/* Needed for HP-specific architecture version numbers. */ -#include <unistd.h> -#endif - -/* Integer register names, indexed by the numbers which appear in the - opcodes. */ -static const char *const reg_names[] = - {"flags", - "r1", "rp", "r3", "r4", "r5", "r6", "r7", "r8", "r9", - "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", - "r20", "r21", "r22", "r23", "r24", "r25", "r26", "dp", "ret0", "ret1", - "sp", "r31"}; - -/* Floating point register names, indexed by the numbers which appear in the - opcodes. */ -static const char *const fp_reg_names[] = - {"fpsr", "fpe2", "fpe4", "fpe6", "fr4", "fr5", "fr6", "fr7", "fr8", "fr9", - "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", "fr16", "fr17", "fr18", "fr19", - "fr20", "fr21", "fr22", "fr23", "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", - "fr30", "fr31"}; - -/* (No longer) Format '-': Sign-extension completers */ -static const char *const sign_extension_names[] = { ",u", ",s" }; - -/* Format '/': Deposit completers */ -static const char *const deposit_names[] = { ",z", "" }; - -/* Format '}': Floating conversion types */ -static const char *const conversion_names[] = - { "ff", "xf", "fx", "fxt", "", "uxf", "fxu", "fxut" }; - -/* Format <none yet>: Kinds of floating point test */ -static const char *const float_test_names[] = - { "", ",acc", ",rej", "", "", ",acc8", ",rej8", "", - "", ",acc6", "", "", "", ",acc4", "", "", - "", ",acc2" }; - -typedef unsigned int CORE_ADDR; - -/* Get at various relevent fields of an instruction word. */ - -#define MASK_5 0x1f -#define MASK_11 0x7ff -#define MASK_14 0x3fff -#define MASK_21 0x1fffff - -/* These macros get bit fields using HP's numbering (MSB = 0) */ - -/* Now defined in "libhppa.h" - #define GET_FIELD(X, FROM, TO) \ - ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) - - #define GET_BIT( X, WHICH ) \ - GET_FIELD( X, WHICH, WHICH ) -*/ - -/* Some of these have been converted to 2-d arrays because they - consume less storage this way. If the maintenance becomes a - problem, convert them back to const 1-d pointer arrays. */ -static const char control_reg[][6] = -{ - "rctr", - "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", - "pidr1", "pidr2", "ccr", "sar", "pidr3", "pidr4", - "iva", "eiem", "itmr", "pcsq", "pcoq", "iir", "isr", - "ior", "ipsw", "eirr", - "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7" -}; - -static const char compare_cond_names[][5] = { - "", ",=", ",<", ",<=", ",<<", ",<<=", ",sv", - ",od", ",tr", ",<>", ",>=", ",>", ",>>=", - ",>>", ",nsv", ",ev" -}; - -static const char compare_cond_names_double[][6] = { - "*", ",*=", ",*<", ",*<=", ",*<<", ",*<<=", ",*sv", - ",*od", ",*tr", ",*<>", ",*>=", ",*>", ",*>>=", - ",*>>", ",*nsv", ",*ev" -}; - -static const char add_cond_names[][5] = { - "", ",=", ",<", ",<=", ",nuv", ",znv", ",sv", - ",od", ",tr", ",<>", ",>=", ",>", ",uv", - ",vnz", ",nsv", ",ev" -}; - -static const char add_cond_names_double[][6] = { - "*", ",*=", ",*<", ",*<=", ",*nuv", ",*znv", ",*sv", - ",*od", ",*tr", ",*<>", ",*>=", ",*>", ",*uv", - ",*vnz", ",*nsv", ",*ev" -}; - -static const char *const logical_cond_names[] = { - "", ",=", ",<", ",<=", 0, 0, 0, ",od", - ",tr", ",<>", ",>=", ",>", 0, 0, 0, ",ev" -}; - -static const char *const logical_cond_names_double[] = { - "*", ",*=", ",*<", ",*<=", 0, 0, 0, ",*od", - ",*tr", ",*<>", ",*>=", ",*>", 0, 0, 0, ",*ev" -}; -static const char *const unit_cond_names[] = { - "", 0, ",sbz", ",shz", ",sdc", 0, ",sbc", ",shc", - ",tr", 0, ",nbz", ",nhz", ",ndc", 0, ",nbc", ",nhc" -}; -static const char *const unit_cond_names_double[] = { - "*", 0, ",*sbz", ",*shz", ",*sdc", 0, ",*sbc", ",*shc", - ",*tr", 0, ",*nbz", ",*nhz", ",*ndc", 0, ",*nbc", ",*nhc" -}; -static const char shift_cond_names[][4] = { - "", ",=", ",<", ",od", ",tr", ",<>", ",>=", ",ev" -}; - -static const char shift_cond_names_double[][5] = { - "*", ",*=", ",*<", ",*od", ",*tr", ",*<>", ",*>=", ",*ev" -}; - -/* Format 'c' */ -static const char index_compl_names[][4] = {"", ",m", ",s", ",sm"}; - -/* Format 'C' */ -static const char short_ldst_compl_names[][4] = {"", ",ma", ",o", ",mb"}; - -/* Format 'Y' */ -static const char *const short_bytes_compl_names[] = { "", ",b,m", ",e", ",e,m" }; - -/* Format '$' */ -static const char *const branch_push_pop_names[] = { "", ",pop", ",l", ",l,push" }; - -/* Format '=' */ -static const char *const saturation_names[] = { ",us", ",ss", "", "" }; - -/* Format '3' */ -static const char *const shift_names[] = { "", "", ",u", ",s" }; - -/* Format 'e' */ -static const char *const mix_names[] = { ",l", "", ",r", "" }; - -static const char *const float_format_names[] = {",sgl", ",dbl", "", ",quad"}; - -static const char float_comp_names[][8] = -{ - ",false?", ",false", ",?", ",!<=>", ",=", ",=t", ",?=", ",!<>", - ",!?>=", ",<", ",?<", ",!>=", ",!?>", ",<=", ",?<=", ",!>", - ",!?<=", ",>", ",?>", ",!<=", ",!?<", ",>=", ",?>=", ",!<", - ",!?=", ",<>", ",!=", ",!=t", ",!?", ",<=>", ",true?", ",true" -}; - -/* For a bunch of different instructions form an index into a - completer name table. */ -#define GET_COMPL(insn) (GET_FIELD (insn, 26, 26) | \ - GET_FIELD (insn, 18, 18) << 1) - -/* Like GET_COMPL, but if the last five bits are 0 and the M bit is - * set, return "2" for ",o" */ -#define GET_COMPL_O(insn) ( (GET_COMPL(insn) == 1) \ - ? ((GET_FIELD (insn, 27, 31 ) == 0) ? 2 : 1 )\ - : GET_COMPL(insn)) - -#define GET_COND(insn) (GET_FIELD ((insn), 16, 18) + \ - (GET_FIELD ((insn), 19, 19) ? 8 : 0)) - -#define GET_PUSH_POP(insn) ((GET_BIT ((insn), 18) << 1) | GET_BIT((insn), 31)) - -/* Two-part register extract */ -#define MERGED_REG(insn) ((GET_FIELD((insn), 16, 18)) << 2 | GET_FIELD((insn), 21, 22)) - -/* Utility function to print registers. Put these first, so gcc's function - inlining can do its stuff. */ - -#define fputs_filtered(STR,F) (*info->fprintf_func) (info->stream, "%s", STR) - -static void -fput_reg (reg, info) - unsigned reg; - disassemble_info *info; -{ - (*info->fprintf_func) (info->stream, reg ? reg_names[reg] : "r0"); -} - -static void -fput_fp_reg (reg, info) - unsigned reg; - disassemble_info *info; -{ - (*info->fprintf_func) (info->stream, reg ? fp_reg_names[reg] : "fr0"); -} - -static void -fput_fp_reg_r (reg, info) - unsigned reg; - disassemble_info *info; -{ - /* Special case floating point exception registers. */ - if (reg < 4) - (*info->fprintf_func) (info->stream, "fpe%d", reg * 2 + 1); - else - (*info->fprintf_func) (info->stream, "%sR", reg ? fp_reg_names[reg] - : "fr0"); -} - -static void -fput_creg (reg, info) - unsigned reg; - disassemble_info *info; -{ - (*info->fprintf_func) (info->stream, control_reg[reg]); -} - -/* print constants in hex with sign */ - -static void -fput_hex_const (num, info) - unsigned num; - disassemble_info *info; -{ - /* Mark negative numbers as negative; only mark - numbers as hex if necessary. */ - if ((int)num < 0) - { - if ((int)num > -10) - (*info->fprintf_func) (info->stream, "-%d", -(int)num ); - else - (*info->fprintf_func) (info->stream, "-0x%x", -(int)num); - } - else if ((int)num < 10) - (*info->fprintf_func) (info->stream, "%d", num ); - else - (*info->fprintf_func) (info->stream, "0x%x", num); -} - -/* print constants in decimal with sign */ - -static void -fput_decimal_const (num, info) - unsigned num; - disassemble_info *info; -{ - if ((int)num < 0) - (*info->fprintf_func) (info->stream, "-%d", -(int)num); - else - (*info->fprintf_func) (info->stream, "%d", num); -} - -/* Routines to extract various sized constants out of hppa - instructions. */ - -/* extract a 3-bit space register number from a be, ble, - mtsp, pitlb or mfsp */ -static int -extract_3 (word) - unsigned word; -{ - return GET_FIELD (word, 18, 18) << 2 | GET_FIELD (word, 16, 17); -} - -static int -extract_5_load (word) - unsigned word; -{ - return low_sign_extend (word >> 16 & MASK_5, 5); -} - -/* extract the immediate field from a st{bhw}s instruction */ -static int -extract_5_store (word) - unsigned word; -{ - return low_sign_extend (word & MASK_5, 5); -} - -/* extract the immediate field from a break instruction */ -static unsigned -extract_5r_store (word) - unsigned word; -{ - return (word & MASK_5); -} - -/* extract the immediate field from a {sr}sm instruction */ -static unsigned -extract_5R_store (word) - unsigned word; -{ - return (word >> 16 & MASK_5); -} - -/* extract the immediate field from a bb instruction */ -static unsigned -extract_5Q_store (word) - unsigned word; -{ - return (word >> 21 & MASK_5); -} - -/* extract an 11 bit immediate field */ -static int -extract_11 (word) - unsigned word; -{ - return low_sign_extend (word & MASK_11, 11); -} - -/* extract a 14 bit immediate field */ -static int -extract_14 (word) - unsigned word; -{ - return low_sign_extend (word & MASK_14, 14); -} - -/* extract a 21 bit constant */ - -static int -extract_21 (word) - unsigned word; -{ - int val; - - word &= MASK_21; - word <<= 11; - val = GET_FIELD (word, 20, 20); - val <<= 11; - val |= GET_FIELD (word, 9, 19); - val <<= 2; - val |= GET_FIELD (word, 5, 6); - val <<= 5; - val |= GET_FIELD (word, 0, 4); - val <<= 2; - val |= GET_FIELD (word, 7, 8); - return sign_extend (val, 21) << 11; -} - -/* extract a 12 bit constant from branch instructions */ - -static int -extract_12 (word) - unsigned word; -{ - return sign_extend (GET_FIELD (word, 19, 28) | - GET_FIELD (word, 29, 29) << 10 | - (word & 0x1) << 11, 12) << 2; -} - -/* extract a 17 bit constant from branch instructions, returning the - 19 bit signed value. */ - -static int -extract_17 (word) - unsigned word; -{ - return sign_extend (GET_FIELD (word, 19, 28) | - GET_FIELD (word, 29, 29) << 10 | - GET_FIELD (word, 11, 15) << 11 | - (word & 0x1) << 16, 17) << 2; -} - -/* Print one instruction. */ -int -print_insn_hppa (memaddr, info) - bfd_vma memaddr; - disassemble_info *info; -{ - bfd_byte buffer[4]; - unsigned int insn, i; - -#ifdef LOCAL_ONLY - static int got_version_id = 0; - static enum pa_arch pa_version; -#endif - - /* Get the instruction to disassemble. - */ - { - int status = - (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - } - insn = bfd_getb32 (buffer); - -#ifdef LOCAL_ONLY - /* Get the architecture version of this machine, and assume - it's the same as our target (this won't work for remote - or core debugging, nor for looking at PA2.0 binaries from - a 1.x machine, which is not only legal but part of our - test system!). Values are: - - CPU_PA_RISC1_0 0x20B - CPU_PA_RISC1_1 0x210 - CPU_PA_RISC1_2 0x211 - CPU_PA_RISC2_0 0x214 - - What we really want is a way to query the bfd for the - architecture the binary was compiled/assembled for. */ - if(!got_version_id) - { - int version_id; - - got_version_id = 1; - version_id = sysconf (_SC_CPU_VERSION); - switch (version_id) - { - case CPU_PA_RISC1_0 : - case CPU_PA_RISC1_1 : - case CPU_PA_RISC1_2 : - pa_version = pa10; - break; - - case CPU_PA_RISC2_0 : - pa_version = pa20; - break; - - default: - /* Now what? */ - break; - } - } -#endif - - /* This linear search through the opcode table is potentially - a bottleneck. If it becomes one, we can use the six-bit actual - opcode as an index into a table of pointers to smaller tables. - - A better organization might use the fact that there are only - about 40 distinct formats for instructions, rather than looking - at the hundred-plus kinds of operands. */ - for (i = 0; i < NUMOPCODES; ++i) - { - const struct pa_opcode *opcode = &pa_opcodes[i]; - if ((insn & opcode->mask) == opcode->match) - { - register const char *s; - int added_space = 0; - -#ifdef LOCAL_ONLY - if (opcode->arch == pa20 - && pa_version == pa10) - /* Target file has new architecture, host is old. - This can't be a correct match, can it? - NOTE: the other way is ok. */ - continue; -#endif - - fputs_filtered (opcode->name, info); - - for (s = opcode->args; *s != '\0'; ++s) - { - if (!added_space - && 0 == strchr(completer_chars, *s)) - { - /* This is the first non-completer. - Print a space here, after all completers, - before any regular operands. */ - fputs_filtered (" ", info); - added_space = 1; - } - - /* '*s' describes either an extraction and a format, - or is a literal string to dump to the disassembly. */ - switch (*s) - { - case 'x': - fput_reg (GET_FIELD (insn, 11, 15), info); - break; - - case 'X': - if (GET_FIELD (insn, 25, 25)) - fput_fp_reg_r (GET_FIELD (insn, 11, 15), info); - else - fput_fp_reg (GET_FIELD (insn, 11, 15), info); - break; - - case 'g': - if (GET_FIELD (insn, 30, 30)) - fput_fp_reg_r (GET_FIELD (insn, 11, 15), info); - else - fput_fp_reg (GET_FIELD (insn, 11, 15), info); - break; - - case 'b': - fput_reg (GET_FIELD (insn, 6, 10), info); - break; - - case '^': - fput_creg (GET_FIELD (insn, 6, 10), info); - break; - - case 'E': - if (GET_FIELD (insn, 25, 25)) - fput_fp_reg_r (GET_FIELD (insn, 6, 10), info); - else - fput_fp_reg (GET_FIELD (insn, 6, 10), info); - break; - - case 't': - fput_reg (GET_FIELD (insn, 27, 31), info); - break; - - case 'v': - if (GET_FIELD (insn, 25, 25)) - fput_fp_reg_r (GET_FIELD (insn, 27, 31), info); - else - fput_fp_reg (GET_FIELD (insn, 27, 31), info); - break; - - case 'y': - fput_fp_reg (GET_FIELD (insn, 27, 31), info); - break; - - case 'B': - fput_fp_reg (GET_FIELD (insn, 11, 15), info); - break; - - case '4': - { - int reg = GET_FIELD (insn, 6, 10); - - reg |= (GET_FIELD (insn, 26, 26) << 4); - fput_fp_reg (reg, info); - break; - } - - case '6': - { - int reg = GET_FIELD (insn, 11, 15); - - reg |= (GET_FIELD (insn, 26, 26) << 4); - fput_fp_reg (reg, info); - break; - } - - case '7': - { - int reg = GET_FIELD (insn, 27, 31); - - reg |= (GET_FIELD (insn, 26, 26) << 4); - fput_fp_reg (reg, info); - break; - } - - case '8': - { - int reg = GET_FIELD (insn, 16, 20); - - reg |= (GET_FIELD (insn, 26, 26) << 4); - fput_fp_reg (reg, info); - break; - } - - case '9': - { - int reg = GET_FIELD (insn, 21, 25); - - reg |= (GET_FIELD (insn, 26, 26) << 4); - fput_fp_reg (reg, info); - break; - } - - case '5': - fput_hex_const (extract_5_load (insn), info); - break; - - case 's': - (*info->fprintf_func) (info->stream, - "sr%d", GET_FIELD (insn, 16, 17)); - break; - - case 'S': - /* Used when 'assemble_3' is specified. - */ - (*info->fprintf_func) (info->stream, "sr%d", - extract_3 (insn)); - break; - - case 'c': - fputs_filtered (index_compl_names[GET_COMPL (insn)], info); - break; - - case 'C': - fputs_filtered (short_ldst_compl_names[GET_COMPL_O (insn)], info); - break; - - case 'm': - fputs_filtered (short_ldst_compl_names[ - (GET_BIT(insn,29) << 1 | GET_BIT(insn,28)) ], - info); - break; - - case 'Y': - fputs_filtered (short_bytes_compl_names[GET_COMPL (insn)], info); - break; - - /* these four conditions are for the set of instructions - which distinguish true/false conditions by opcode rather - than by the 'f' bit (sigh): comb, comib, addb, addib */ - case '<': - fputs_filtered (compare_cond_names[GET_FIELD (insn, 16, 18)], - info); - break; - - case '?': - fputs_filtered (compare_cond_names[GET_FIELD (insn, 16, 18) - + GET_FIELD (insn, 4, 4) * 8], info); - break; - - case '@': - fputs_filtered (add_cond_names[GET_FIELD (insn, 16, 18) - + GET_FIELD (insn, 4, 4) * 8], info); - break; - - case 'a': - fputs_filtered (compare_cond_names[GET_COND (insn)], info); - break; - - case 'd': - fputs_filtered (add_cond_names[GET_COND (insn)], info); - break; - - case '!': - fputs_filtered (add_cond_names[GET_FIELD (insn, 16, 18)], info); - break; - - case '&': - fputs_filtered (logical_cond_names[GET_COND (insn)], info); - break; - - case 'U': - fputs_filtered (unit_cond_names[GET_COND (insn)], info); - break; - - case '|': - case '>': - case '~': - fputs_filtered (shift_cond_names[GET_FIELD (insn, 16, 18)], info); - break; - - case 'V': - fput_hex_const (extract_5_store (insn), info); - break; - - case 'r': - fput_hex_const (extract_5r_store (insn), info); - break; - - case 'R': - fput_hex_const (extract_5R_store (insn), info); - break; - - case 'Q': - fput_hex_const (extract_5Q_store (insn), info); - break; - - case 'i': - fput_hex_const (extract_11 (insn), info); - break; - - case 'j': - fput_hex_const (extract_14 (insn), info); - break; - - case 'k': - fput_hex_const (extract_21 (insn), info); - break; - - case 'n': - if (insn & 0x2) - fputs_filtered (",n", info); - break; - - case 'N': - if ((insn & 0x20) && s[1]) - fputs_filtered (",n", info); - else if (insn & 0x20) - fputs_filtered (",n", info); - break; - - case 'w': - (*info->print_address_func) (memaddr + 8 + extract_12 (insn), - info); - break; - - case 'W': - /* 17 bit PC-relative branch. */ - (*info->print_address_func) ((memaddr + 8 - + extract_17 (insn)), - info); - break; - - case 'z': - /* 17 bit displacement. This is an offset from a register - so it gets disasssembled as just a number, not any sort - of address. */ - fput_hex_const (extract_17 (insn), info); - break; - - case 'p': - if( pa20 != opcode->arch ) { - fput_decimal_const (31 - GET_FIELD (insn, 22, 26), info); - } - else { - fput_decimal_const (63 - CATENATE (GET_BIT (insn, 20), 1, - GET_FIELD (insn, 22, 26), 5), - info); - } - break; - - case 'P': - fput_decimal_const (GET_FIELD (insn, 22, 26), info); - break; - - case 'T': - fput_decimal_const (32 - GET_FIELD (insn, 27, 31), info); - break; - - case 'A': - fput_hex_const (GET_FIELD (insn, 6, 18), info); - break; - - case 'Z': - if (GET_FIELD (insn, 26, 26)) - fputs_filtered (",m", info); - break; - - case 'D': - fput_hex_const (GET_FIELD (insn, 6, 31), info); - break; - - case 'f': - fput_decimal_const (GET_FIELD (insn, 23, 25), info); - break; - - case 'O': - fput_hex_const ((GET_FIELD (insn, 6,20) << 5 | - GET_FIELD (insn, 27, 31)), info); - break; - - case 'o': - fput_hex_const (GET_FIELD (insn, 6, 20), info); - break; - - case '2': - fput_hex_const ((GET_FIELD (insn, 6, 22) << 5 | - GET_FIELD (insn, 27, 31)), info); - break; - - case '1': - fput_hex_const ((GET_FIELD (insn, 11, 20) << 5 | - GET_FIELD (insn, 27, 31)), info); - break; - - case '0': - fput_hex_const ((GET_FIELD (insn, 16, 20) << 5 | - GET_FIELD (insn, 27, 31)), info); - break; - - case 'u': - fput_decimal_const (GET_FIELD (insn, 23, 25), info); - break; - - case 'F': - fputs_filtered (float_format_names[GET_FIELD (insn, 19, 20)], - info); - break; - - case 'G': - fputs_filtered (float_format_names[GET_FIELD (insn, 17, 18)], - info); - break; - - case 'H': - if (GET_FIELD (insn, 26, 26) == 1) - fputs_filtered (float_format_names[0], info); - else - fputs_filtered (float_format_names[1], info); - break; - - case 'I': - /* if no destination completer and not before a completer - for fcmp, need a space here */ - fputs_filtered (float_format_names[GET_FIELD (insn, 20, 20)], - info); - break; - - case 'J': - if (GET_FIELD (insn, 24, 24)) - fput_fp_reg_r (GET_FIELD (insn, 6, 10), info); - else - fput_fp_reg (GET_FIELD (insn, 6, 10), info); - break; - - case 'K': - if (GET_FIELD (insn, 19, 19)) - fput_fp_reg_r (GET_FIELD (insn, 11, 15), info); - else - fput_fp_reg (GET_FIELD (insn, 11, 15), info); - break; - - case 'M': - fputs_filtered (float_comp_names[GET_FIELD (insn, 27, 31)], - info); - break; - - case 'L': { - long temp; - - temp = GET_FIELD (insn, 18, 27) << 1; - temp = assemble_16a (GET_FIELD (insn, 16, 17), - temp, - GET_BIT (insn, 31)); - fput_hex_const (temp, info); - break; - } - - case 'l': { - long temp; - - temp = assemble_16a (s, - GET_FIELD (insn, 18, 28), - GET_BIT (insn, 31)); - fput_hex_const (temp, info); - break; - } - - case 'q': - -/* TEMP HACK - FIXME - edie */ - fput_hex_const (sign_extend (GET_FIELD (insn, 20, 30), 0), info); - break; - - case '#': - fput_decimal_const (GET_FIELD (insn, 20, 28), info); - break; - - case '$': - fputs_filtered (branch_push_pop_names[GET_PUSH_POP(insn)], info); - break; - - case '.': - fput_creg( 11, info ); /* %cr11, printed by gdb as "sar" */ - break; - - case '-': - /* 22 bit PC-relative branch. */ - (*info->print_address_func) (memaddr + 8 + - (assemble_22 (GET_FIELD (insn, 6, 10), - GET_FIELD (insn, 11, 15), - GET_FIELD (insn, 19, 29), - GET_FIELD (insn, 31, 31)) << 2), - info); - break; - - case '/': - fputs_filtered (deposit_names[GET_BIT(insn,21)], info); - break; - - case '*': -/* TEMP HACK - FIXME - edie */ - fput_decimal_const (sign_extend (assemble_6 (GET_BIT (insn, 23), - GET_FIELD (insn, 27, 31)), 0), - info); - break; - - case '[': -/* TEMP HACK - FIXME - edie */ - fput_decimal_const (sign_extend (CATENATE (GET_BIT (insn, 20), 1, - GET_FIELD (insn, 22, 26), 5), - 0), - info); - break; - - case ']': -/* TEMP HACK - FIXME - edie */ - fput_decimal_const (sign_extend (assemble_6 (GET_BIT (insn, 19), GET_FIELD (insn, 27, 31)), 0), info); - break; - - case '=': - fputs_filtered (saturation_names[GET_FIELD(insn,24,25)], info); - break; - - case ';': - /* Always positive */ - fput_decimal_const (GET_FIELD (insn, 24, 25), info); - break; - - case ':': - /* Always positive */ - fput_decimal_const (GET_FIELD (insn, 22, 25), info); - break; - - case '3': - fputs_filtered (shift_names[GET_FIELD(insn,20,21)], info); - break; - - case '%': - fputs_filtered (",", info); - fput_decimal_const (GET_FIELD (insn, 17, 18), info ); - fput_decimal_const (GET_FIELD (insn, 20, 21), info ); - fput_decimal_const (GET_FIELD (insn, 22, 23), info ); - fput_decimal_const (GET_FIELD (insn, 24, 25), info ); - break; - - case 'e': - fputs_filtered (mix_names[GET_FIELD(insn,17,18)], info); - break; - - case '}': - fputs_filtered (conversion_names[GET_FIELD(insn,14,16)], info); - break; - - case 'h': - fput_hex_const (GET_FIELD (insn, 6, 15), info); - break; - - case '_': - fput_decimal_const ((GET_FIELD (insn, 16, 18) - 1), info); - break; - - case '+': { - int temp = GET_FIELD (insn, 16, 18) ^ 1; - - if (temp == 0) - /* shouldn't happen, as spec says that if - this field is "1", then it's a different - format. */ - fput_decimal_const (7, info); - else - fput_decimal_const (temp - 1, info); - break; - } - - case '{': - /* Funky two-part six-bit register specifier */ - if (GET_BIT (insn, 23)) - fput_fp_reg_r (MERGED_REG (insn), info); - else - fput_fp_reg (MERGED_REG (insn), info); - break; - - default: - (*info->fprintf_func) (info->stream, "%c", *s); - break; - } - } /* For each operand */ - - return sizeof (insn); - } /* If matched */ - } /* For each opcode */ - - (*info->fprintf_func) (info->stream, "#%8x", insn); - return sizeof(insn); -} - diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c deleted file mode 100644 index eea4c00cf51..00000000000 --- a/opcodes/i386-dis.c +++ /dev/null @@ -1,2370 +0,0 @@ -/* Print i386 instructions for GDB, the GNU debugger. - Copyright (C) 1988, 89, 91, 93, 94, 95, 96, 97, 1998 - Free Software Foundation, Inc. - -This file is part of GDB. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -/* - * 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) - * July 1988 - * modified by John Hassey (hassey@dg-rtp.dg.com) - */ - -/* - * The main tables describing the instructions is essentially a copy - * of the "Opcode Map" chapter (Appendix A) of the Intel 80386 - * Programmers Manual. Usually, there is a capital letter, followed - * by a small letter. The capital letter tell the addressing mode, - * and the small letter tells about the operand size. Refer to - * the Intel manual for details. - */ - -#include "dis-asm.h" -#include "sysdep.h" -#include "opintl.h" - -#define MAXLEN 20 - -#include <setjmp.h> - -#ifndef UNIXWARE_COMPAT -/* Set non-zero for broken, compatible instructions. Set to zero for - non-broken opcodes. */ -#define UNIXWARE_COMPAT 1 -#endif - - -static int fetch_data PARAMS ((struct disassemble_info *, bfd_byte *)); - -struct dis_private -{ - /* Points to first byte not fetched. */ - bfd_byte *max_fetched; - bfd_byte the_buffer[MAXLEN]; - bfd_vma insn_start; - jmp_buf bailout; -}; - -/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) - to ADDR (exclusive) are valid. Returns 1 for success, longjmps - on error. */ -#define FETCH_DATA(info, addr) \ - ((addr) <= ((struct dis_private *)(info->private_data))->max_fetched \ - ? 1 : fetch_data ((info), (addr))) - -static int -fetch_data (info, addr) - struct disassemble_info *info; - bfd_byte *addr; -{ - int status; - struct dis_private *priv = (struct dis_private *)info->private_data; - bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); - - status = (*info->read_memory_func) (start, - priv->max_fetched, - addr - priv->max_fetched, - info); - if (status != 0) - { - (*info->memory_error_func) (status, start, info); - longjmp (priv->bailout, 1); - } - else - priv->max_fetched = addr; - return 1; -} - -#define Eb OP_E, b_mode -#define indirEb OP_indirE, b_mode -#define Gb OP_G, b_mode -#define Ev OP_E, v_mode -#define indirEv OP_indirE, v_mode -#define Ew OP_E, w_mode -#define Ma OP_E, v_mode -#define M OP_E, 0 -#define Mp OP_E, 0 /* ? */ -#define Gv OP_G, v_mode -#define Gw OP_G, w_mode -#define Rw OP_rm, w_mode -#define Rd OP_rm, d_mode -#define Ib OP_I, b_mode -#define sIb OP_sI, b_mode /* sign extened byte */ -#define Iv OP_I, v_mode -#define Iw OP_I, w_mode -#define Jb OP_J, b_mode -#define Jv OP_J, v_mode -#if 0 -#define ONE OP_ONE, 0 -#endif -#define Cd OP_C, d_mode -#define Dd OP_D, d_mode -#define Td OP_T, d_mode - -#define eAX OP_REG, eAX_reg -#define eBX OP_REG, eBX_reg -#define eCX OP_REG, eCX_reg -#define eDX OP_REG, eDX_reg -#define eSP OP_REG, eSP_reg -#define eBP OP_REG, eBP_reg -#define eSI OP_REG, eSI_reg -#define eDI OP_REG, eDI_reg -#define AL OP_REG, al_reg -#define CL OP_REG, cl_reg -#define DL OP_REG, dl_reg -#define BL OP_REG, bl_reg -#define AH OP_REG, ah_reg -#define CH OP_REG, ch_reg -#define DH OP_REG, dh_reg -#define BH OP_REG, bh_reg -#define AX OP_REG, ax_reg -#define DX OP_REG, dx_reg -#define indirDX OP_REG, indir_dx_reg - -#define Sw OP_SEG, w_mode -#define Ap OP_DIR, lptr -#define Av OP_DIR, v_mode -#define Ob OP_OFF, b_mode -#define Ov OP_OFF, v_mode -#define Xb OP_DSreg, eSI_reg -#define Xv OP_DSreg, eSI_reg -#define Yb OP_ESreg, eDI_reg -#define Yv OP_ESreg, eDI_reg -#define DSBX OP_DSreg, eBX_reg - -#define es OP_REG, es_reg -#define ss OP_REG, ss_reg -#define cs OP_REG, cs_reg -#define ds OP_REG, ds_reg -#define fs OP_REG, fs_reg -#define gs OP_REG, gs_reg - -#define MX OP_MMX, 0 -#define EM OP_EM, v_mode -#define MS OP_MS, b_mode - -/* bits in sizeflag */ -#if 0 /* leave undefined until someone adds the extra flag to objdump */ -#define SUFFIX_ALWAYS 4 -#endif -#define AFLAG 2 -#define DFLAG 1 - -typedef void (*op_rtn) PARAMS ((int bytemode, int sizeflag)); - -static void OP_E PARAMS ((int, int)); -static void OP_G PARAMS ((int, int)); -static void OP_I PARAMS ((int, int)); -static void OP_indirE PARAMS ((int, int)); -static void OP_sI PARAMS ((int, int)); -static void OP_REG PARAMS ((int, int)); -static void OP_J PARAMS ((int, int)); -static void OP_DIR PARAMS ((int, int)); -static void OP_OFF PARAMS ((int, int)); -static void OP_ESreg PARAMS ((int, int)); -static void OP_DSreg PARAMS ((int, int)); -static void OP_SEG PARAMS ((int, int)); -static void OP_C PARAMS ((int, int)); -static void OP_D PARAMS ((int, int)); -static void OP_T PARAMS ((int, int)); -static void OP_rm PARAMS ((int, int)); -static void OP_ST PARAMS ((int, int)); -static void OP_STi PARAMS ((int, int)); -#if 0 -static void OP_ONE PARAMS ((int, int)); -#endif -static void OP_MMX PARAMS ((int, int)); -static void OP_EM PARAMS ((int, int)); -static void OP_MS PARAMS ((int, int)); - -static void append_seg PARAMS ((void)); -static void set_op PARAMS ((unsigned int op)); -static void putop PARAMS ((char *template, int sizeflag)); -static void dofloat PARAMS ((int sizeflag)); -static int get16 PARAMS ((void)); -static int get32 PARAMS ((void)); -static void ckprefix PARAMS ((void)); -static void ptr_reg PARAMS ((int, int)); - -#define b_mode 1 -#define v_mode 2 -#define w_mode 3 -#define d_mode 4 - -#define es_reg 100 -#define cs_reg 101 -#define ss_reg 102 -#define ds_reg 103 -#define fs_reg 104 -#define gs_reg 105 -#define eAX_reg 107 -#define eCX_reg 108 -#define eDX_reg 109 -#define eBX_reg 110 -#define eSP_reg 111 -#define eBP_reg 112 -#define eSI_reg 113 -#define eDI_reg 114 - -#define lptr 115 - -#define al_reg 116 -#define cl_reg 117 -#define dl_reg 118 -#define bl_reg 119 -#define ah_reg 120 -#define ch_reg 121 -#define dh_reg 122 -#define bh_reg 123 - -#define ax_reg 124 -#define cx_reg 125 -#define dx_reg 126 -#define bx_reg 127 -#define sp_reg 128 -#define bp_reg 129 -#define si_reg 130 -#define di_reg 131 - -#define indir_dx_reg 150 - -#define GRP1b NULL, NULL, 0 -#define GRP1S NULL, NULL, 1 -#define GRP1Ss NULL, NULL, 2 -#define GRP2b NULL, NULL, 3 -#define GRP2S NULL, NULL, 4 -#define GRP2b_one NULL, NULL, 5 -#define GRP2S_one NULL, NULL, 6 -#define GRP2b_cl NULL, NULL, 7 -#define GRP2S_cl NULL, NULL, 8 -#define GRP3b NULL, NULL, 9 -#define GRP3S NULL, NULL, 10 -#define GRP4 NULL, NULL, 11 -#define GRP5 NULL, NULL, 12 -#define GRP6 NULL, NULL, 13 -#define GRP7 NULL, NULL, 14 -#define GRP8 NULL, NULL, 15 -#define GRP9 NULL, NULL, 16 -#define GRP10 NULL, NULL, 17 -#define GRP11 NULL, NULL, 18 -#define GRP12 NULL, NULL, 19 - -#define FLOATCODE 50 -#define FLOAT NULL, NULL, FLOATCODE - -struct dis386 { - char *name; - op_rtn op1; - int bytemode1; - op_rtn op2; - int bytemode2; - op_rtn op3; - int bytemode3; -}; - -/* Upper case letters in the instruction names here are macros. - 'A' => print 'b' if no register operands or suffix_always is true - 'B' => print 'b' if suffix_always is true - 'E' => print 'e' if 32-bit form of jcxz - 'L' => print 'l' if suffix_always is true - 'N' => print 'n' if instruction has no wait "prefix" - 'P' => print 'w' or 'l' if instruction has an operand size prefix, - or suffix_always is true - 'Q' => print 'w' or 'l' if no register operands or suffix_always is true - 'R' => print 'w' or 'l' - 'S' => print 'w' or 'l' if suffix_always is true - 'W' => print 'b' or 'w' -*/ - -static struct dis386 dis386[] = { - /* 00 */ - { "addB", Eb, Gb }, - { "addS", Ev, Gv }, - { "addB", Gb, Eb }, - { "addS", Gv, Ev }, - { "addB", AL, Ib }, - { "addS", eAX, Iv }, - { "pushP", es }, - { "popP", es }, - /* 08 */ - { "orB", Eb, Gb }, - { "orS", Ev, Gv }, - { "orB", Gb, Eb }, - { "orS", Gv, Ev }, - { "orB", AL, Ib }, - { "orS", eAX, Iv }, - { "pushP", cs }, - { "(bad)" }, /* 0x0f extended opcode escape */ - /* 10 */ - { "adcB", Eb, Gb }, - { "adcS", Ev, Gv }, - { "adcB", Gb, Eb }, - { "adcS", Gv, Ev }, - { "adcB", AL, Ib }, - { "adcS", eAX, Iv }, - { "pushP", ss }, - { "popP", ss }, - /* 18 */ - { "sbbB", Eb, Gb }, - { "sbbS", Ev, Gv }, - { "sbbB", Gb, Eb }, - { "sbbS", Gv, Ev }, - { "sbbB", AL, Ib }, - { "sbbS", eAX, Iv }, - { "pushP", ds }, - { "popP", ds }, - /* 20 */ - { "andB", Eb, Gb }, - { "andS", Ev, Gv }, - { "andB", Gb, Eb }, - { "andS", Gv, Ev }, - { "andB", AL, Ib }, - { "andS", eAX, Iv }, - { "(bad)" }, /* SEG ES prefix */ - { "daa" }, - /* 28 */ - { "subB", Eb, Gb }, - { "subS", Ev, Gv }, - { "subB", Gb, Eb }, - { "subS", Gv, Ev }, - { "subB", AL, Ib }, - { "subS", eAX, Iv }, - { "(bad)" }, /* SEG CS prefix */ - { "das" }, - /* 30 */ - { "xorB", Eb, Gb }, - { "xorS", Ev, Gv }, - { "xorB", Gb, Eb }, - { "xorS", Gv, Ev }, - { "xorB", AL, Ib }, - { "xorS", eAX, Iv }, - { "(bad)" }, /* SEG SS prefix */ - { "aaa" }, - /* 38 */ - { "cmpB", Eb, Gb }, - { "cmpS", Ev, Gv }, - { "cmpB", Gb, Eb }, - { "cmpS", Gv, Ev }, - { "cmpB", AL, Ib }, - { "cmpS", eAX, Iv }, - { "(bad)" }, /* SEG DS prefix */ - { "aas" }, - /* 40 */ - { "incS", eAX }, - { "incS", eCX }, - { "incS", eDX }, - { "incS", eBX }, - { "incS", eSP }, - { "incS", eBP }, - { "incS", eSI }, - { "incS", eDI }, - /* 48 */ - { "decS", eAX }, - { "decS", eCX }, - { "decS", eDX }, - { "decS", eBX }, - { "decS", eSP }, - { "decS", eBP }, - { "decS", eSI }, - { "decS", eDI }, - /* 50 */ - { "pushS", eAX }, - { "pushS", eCX }, - { "pushS", eDX }, - { "pushS", eBX }, - { "pushS", eSP }, - { "pushS", eBP }, - { "pushS", eSI }, - { "pushS", eDI }, - /* 58 */ - { "popS", eAX }, - { "popS", eCX }, - { "popS", eDX }, - { "popS", eBX }, - { "popS", eSP }, - { "popS", eBP }, - { "popS", eSI }, - { "popS", eDI }, - /* 60 */ - { "pushaP" }, - { "popaP" }, - { "boundS", Gv, Ma }, - { "arpl", Ew, Gw }, - { "(bad)" }, /* seg fs */ - { "(bad)" }, /* seg gs */ - { "(bad)" }, /* op size prefix */ - { "(bad)" }, /* adr size prefix */ - /* 68 */ - { "pushP", Iv }, /* 386 book wrong */ - { "imulS", Gv, Ev, Iv }, - { "pushP", sIb }, /* push of byte really pushes 2 or 4 bytes */ - { "imulS", Gv, Ev, sIb }, - { "insb", Yb, indirDX }, - { "insR", Yv, indirDX }, - { "outsb", indirDX, Xb }, - { "outsR", indirDX, Xv }, - /* 70 */ - { "jo", Jb }, - { "jno", Jb }, - { "jb", Jb }, - { "jae", Jb }, - { "je", Jb }, - { "jne", Jb }, - { "jbe", Jb }, - { "ja", Jb }, - /* 78 */ - { "js", Jb }, - { "jns", Jb }, - { "jp", Jb }, - { "jnp", Jb }, - { "jl", Jb }, - { "jge", Jb }, - { "jle", Jb }, - { "jg", Jb }, - /* 80 */ - { GRP1b }, - { GRP1S }, - { "(bad)" }, - { GRP1Ss }, - { "testB", Eb, Gb }, - { "testS", Ev, Gv }, - { "xchgB", Eb, Gb }, - { "xchgS", Ev, Gv }, - /* 88 */ - { "movB", Eb, Gb }, - { "movS", Ev, Gv }, - { "movB", Gb, Eb }, - { "movS", Gv, Ev }, - { "movQ", Ev, Sw }, - { "leaS", Gv, M }, - { "movQ", Sw, Ev }, - { "popQ", Ev }, - /* 90 */ - { "nop" }, - { "xchgS", eCX, eAX }, - { "xchgS", eDX, eAX }, - { "xchgS", eBX, eAX }, - { "xchgS", eSP, eAX }, - { "xchgS", eBP, eAX }, - { "xchgS", eSI, eAX }, - { "xchgS", eDI, eAX }, - /* 98 */ - { "cWtR" }, - { "cRtd" }, - { "lcallP", Ap }, - { "(bad)" }, /* fwait */ - { "pushfP" }, - { "popfP" }, - { "sahf" }, - { "lahf" }, - /* a0 */ - { "movB", AL, Ob }, - { "movS", eAX, Ov }, - { "movB", Ob, AL }, - { "movS", Ov, eAX }, - { "movsb", Yb, Xb }, - { "movsR", Yv, Xv }, - { "cmpsb", Xb, Yb }, - { "cmpsR", Xv, Yv }, - /* a8 */ - { "testB", AL, Ib }, - { "testS", eAX, Iv }, - { "stosB", Yb, AL }, - { "stosS", Yv, eAX }, - { "lodsB", AL, Xb }, - { "lodsS", eAX, Xv }, - { "scasB", AL, Yb }, - { "scasS", eAX, Yv }, - /* b0 */ - { "movB", AL, Ib }, - { "movB", CL, Ib }, - { "movB", DL, Ib }, - { "movB", BL, Ib }, - { "movB", AH, Ib }, - { "movB", CH, Ib }, - { "movB", DH, Ib }, - { "movB", BH, Ib }, - /* b8 */ - { "movS", eAX, Iv }, - { "movS", eCX, Iv }, - { "movS", eDX, Iv }, - { "movS", eBX, Iv }, - { "movS", eSP, Iv }, - { "movS", eBP, Iv }, - { "movS", eSI, Iv }, - { "movS", eDI, Iv }, - /* c0 */ - { GRP2b }, - { GRP2S }, - { "retP", Iw }, - { "retP" }, - { "lesS", Gv, Mp }, - { "ldsS", Gv, Mp }, - { "movA", Eb, Ib }, - { "movQ", Ev, Iv }, - /* c8 */ - { "enterP", Iw, Ib }, - { "leaveP" }, - { "lretP", Iw }, - { "lretP" }, - { "int3" }, - { "int", Ib }, - { "into" }, - { "iretP" }, - /* d0 */ - { GRP2b_one }, - { GRP2S_one }, - { GRP2b_cl }, - { GRP2S_cl }, - { "aam", sIb }, - { "aad", sIb }, - { "(bad)" }, - { "xlat", DSBX }, - /* d8 */ - { FLOAT }, - { FLOAT }, - { FLOAT }, - { FLOAT }, - { FLOAT }, - { FLOAT }, - { FLOAT }, - { FLOAT }, - /* e0 */ - { "loopne", Jb }, - { "loope", Jb }, - { "loop", Jb }, - { "jEcxz", Jb }, - { "inB", AL, Ib }, - { "inS", eAX, Ib }, - { "outB", Ib, AL }, - { "outS", Ib, eAX }, - /* e8 */ - { "callP", Av }, - { "jmpP", Jv }, - { "ljmpP", Ap }, - { "jmp", Jb }, - { "inB", AL, indirDX }, - { "inS", eAX, indirDX }, - { "outB", indirDX, AL }, - { "outS", indirDX, eAX }, - /* f0 */ - { "(bad)" }, /* lock prefix */ - { "(bad)" }, - { "(bad)" }, /* repne */ - { "(bad)" }, /* repz */ - { "hlt" }, - { "cmc" }, - { GRP3b }, - { GRP3S }, - /* f8 */ - { "clc" }, - { "stc" }, - { "cli" }, - { "sti" }, - { "cld" }, - { "std" }, - { GRP4 }, - { GRP5 }, -}; - -static struct dis386 dis386_twobyte[] = { - /* 00 */ - { GRP6 }, - { GRP7 }, - { "larS", Gv, Ew }, - { "lslS", Gv, Ew }, - { "(bad)" }, - { "(bad)" }, - { "clts" }, - { "(bad)" }, - /* 08 */ - { "invd" }, - { "wbinvd" }, - { "(bad)" }, - { "ud2a" }, - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" }, - /* 10 */ - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" }, - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" }, - /* 18 */ - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" }, - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" }, - /* 20 */ - /* these are all backward in appendix A of the intel book */ - { "movL", Rd, Cd }, - { "movL", Rd, Dd }, - { "movL", Cd, Rd }, - { "movL", Dd, Rd }, - { "movL", Rd, Td }, - { "(bad)" }, - { "movL", Td, Rd }, - { "(bad)" }, - /* 28 */ - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" }, - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" }, - /* 30 */ - { "wrmsr" }, { "rdtsc" }, { "rdmsr" }, { "rdpmc" }, - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" }, - /* 38 */ - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" }, - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" }, - /* 40 */ - { "cmovo", Gv,Ev }, { "cmovno", Gv,Ev }, { "cmovb", Gv,Ev }, { "cmovae", Gv,Ev }, - { "cmove", Gv,Ev }, { "cmovne", Gv,Ev }, { "cmovbe", Gv,Ev }, { "cmova", Gv,Ev }, - /* 48 */ - { "cmovs", Gv,Ev }, { "cmovns", Gv,Ev }, { "cmovp", Gv,Ev }, { "cmovnp", Gv,Ev }, - { "cmovl", Gv,Ev }, { "cmovge", Gv,Ev }, { "cmovle", Gv,Ev }, { "cmovg", Gv,Ev }, - /* 50 */ - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" }, - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" }, - /* 58 */ - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" }, - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" }, - /* 60 */ - { "punpcklbw", MX, EM }, - { "punpcklwd", MX, EM }, - { "punpckldq", MX, EM }, - { "packsswb", MX, EM }, - { "pcmpgtb", MX, EM }, - { "pcmpgtw", MX, EM }, - { "pcmpgtd", MX, EM }, - { "packuswb", MX, EM }, - /* 68 */ - { "punpckhbw", MX, EM }, - { "punpckhwd", MX, EM }, - { "punpckhdq", MX, EM }, - { "packssdw", MX, EM }, - { "(bad)" }, { "(bad)" }, - { "movd", MX, Ev }, - { "movq", MX, EM }, - /* 70 */ - { "(bad)" }, - { GRP10 }, - { GRP11 }, - { GRP12 }, - { "pcmpeqb", MX, EM }, - { "pcmpeqw", MX, EM }, - { "pcmpeqd", MX, EM }, - { "emms" }, - /* 78 */ - { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" }, - { "(bad)" }, { "(bad)" }, - { "movd", Ev, MX }, - { "movq", EM, MX }, - /* 80 */ - { "jo", Jv }, - { "jno", Jv }, - { "jb", Jv }, - { "jae", Jv }, - { "je", Jv }, - { "jne", Jv }, - { "jbe", Jv }, - { "ja", Jv }, - /* 88 */ - { "js", Jv }, - { "jns", Jv }, - { "jp", Jv }, - { "jnp", Jv }, - { "jl", Jv }, - { "jge", Jv }, - { "jle", Jv }, - { "jg", Jv }, - /* 90 */ - { "seto", Eb }, - { "setno", Eb }, - { "setb", Eb }, - { "setae", Eb }, - { "sete", Eb }, - { "setne", Eb }, - { "setbe", Eb }, - { "seta", Eb }, - /* 98 */ - { "sets", Eb }, - { "setns", Eb }, - { "setp", Eb }, - { "setnp", Eb }, - { "setl", Eb }, - { "setge", Eb }, - { "setle", Eb }, - { "setg", Eb }, - /* a0 */ - { "pushP", fs }, - { "popP", fs }, - { "cpuid" }, - { "btS", Ev, Gv }, - { "shldS", Ev, Gv, Ib }, - { "shldS", Ev, Gv, CL }, - { "(bad)" }, - { "(bad)" }, - /* a8 */ - { "pushP", gs }, - { "popP", gs }, - { "rsm" }, - { "btsS", Ev, Gv }, - { "shrdS", Ev, Gv, Ib }, - { "shrdS", Ev, Gv, CL }, - { "(bad)" }, - { "imulS", Gv, Ev }, - /* b0 */ - { "cmpxchgB", Eb, Gb }, - { "cmpxchgS", Ev, Gv }, - { "lssS", Gv, Mp }, /* 386 lists only Mp */ - { "btrS", Ev, Gv }, - { "lfsS", Gv, Mp }, /* 386 lists only Mp */ - { "lgsS", Gv, Mp }, /* 386 lists only Mp */ - { "movzbR", Gv, Eb }, - { "movzwR", Gv, Ew }, /* yes, there really is movzww ! */ - /* b8 */ - { "(bad)" }, - { "ud2b" }, - { GRP8 }, - { "btcS", Ev, Gv }, - { "bsfS", Gv, Ev }, - { "bsrS", Gv, Ev }, - { "movsbR", Gv, Eb }, - { "movswR", Gv, Ew }, /* yes, there really is movsww ! */ - /* c0 */ - { "xaddB", Eb, Gb }, - { "xaddS", Ev, Gv }, - { "(bad)" }, - { "(bad)" }, - { "(bad)" }, - { "(bad)" }, - { "(bad)" }, - { GRP9 }, - /* c8 */ - { "bswap", eAX }, /* bswap doesn't support 16 bit regs */ - { "bswap", eCX }, - { "bswap", eDX }, - { "bswap", eBX }, - { "bswap", eSP }, - { "bswap", eBP }, - { "bswap", eSI }, - { "bswap", eDI }, - /* d0 */ - { "(bad)" }, - { "psrlw", MX, EM }, - { "psrld", MX, EM }, - { "psrlq", MX, EM }, - { "(bad)" }, - { "pmullw", MX, EM }, - { "(bad)" }, { "(bad)" }, - /* d8 */ - { "psubusb", MX, EM }, - { "psubusw", MX, EM }, - { "(bad)" }, - { "pand", MX, EM }, - { "paddusb", MX, EM }, - { "paddusw", MX, EM }, - { "(bad)" }, - { "pandn", MX, EM }, - /* e0 */ - { "(bad)" }, - { "psraw", MX, EM }, - { "psrad", MX, EM }, - { "(bad)" }, - { "(bad)" }, - { "pmulhw", MX, EM }, - { "(bad)" }, { "(bad)" }, - /* e8 */ - { "psubsb", MX, EM }, - { "psubsw", MX, EM }, - { "(bad)" }, - { "por", MX, EM }, - { "paddsb", MX, EM }, - { "paddsw", MX, EM }, - { "(bad)" }, - { "pxor", MX, EM }, - /* f0 */ - { "(bad)" }, - { "psllw", MX, EM }, - { "pslld", MX, EM }, - { "psllq", MX, EM }, - { "(bad)" }, - { "pmaddwd", MX, EM }, - { "(bad)" }, { "(bad)" }, - /* f8 */ - { "psubb", MX, EM }, - { "psubw", MX, EM }, - { "psubd", MX, EM }, - { "(bad)" }, - { "paddb", MX, EM }, - { "paddw", MX, EM }, - { "paddd", MX, EM }, - { "(bad)" } -}; - -static const unsigned char onebyte_has_modrm[256] = { - 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, - 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, - 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, - 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, - 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 -}; - -static const unsigned char twobyte_has_modrm[256] = { - /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */ - /* 10 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 1f */ - /* 20 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 2f */ - /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */ - /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ - /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 5f */ - /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,0,0,1,1, /* 6f */ - /* 70 */ 0,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1, /* 7f */ - /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ - /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ - /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ - /* b0 */ 1,1,1,1,1,1,1,1,0,0,1,1,1,1,1,1, /* bf */ - /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ - /* d0 */ 0,1,1,1,0,1,0,0,1,1,0,1,1,1,0,1, /* df */ - /* e0 */ 0,1,1,0,0,1,0,0,1,1,0,1,1,1,0,1, /* ef */ - /* f0 */ 0,1,1,1,0,1,0,0,1,1,1,0,1,1,1,0 /* ff */ -}; - -static char obuf[100]; -static char *obufp; -static char scratchbuf[100]; -static unsigned char *start_codep; -static unsigned char *codep; -static disassemble_info *the_info; -static int mod; -static int rm; -static int reg; -static void oappend PARAMS ((char *s)); - -static char *names32[]={ - "%eax","%ecx","%edx","%ebx", "%esp","%ebp","%esi","%edi", -}; -static char *names16[] = { - "%ax","%cx","%dx","%bx","%sp","%bp","%si","%di", -}; -static char *names8[] = { - "%al","%cl","%dl","%bl","%ah","%ch","%dh","%bh", -}; -static char *names_seg[] = { - "%es","%cs","%ss","%ds","%fs","%gs","%?","%?", -}; -static char *index16[] = { - "bx+si","bx+di","bp+si","bp+di","si","di","bp","bx" -}; - -static struct dis386 grps[][8] = { - /* GRP1b */ - { - { "addA", Eb, Ib }, - { "orA", Eb, Ib }, - { "adcA", Eb, Ib }, - { "sbbA", Eb, Ib }, - { "andA", Eb, Ib }, - { "subA", Eb, Ib }, - { "xorA", Eb, Ib }, - { "cmpA", Eb, Ib } - }, - /* GRP1S */ - { - { "addQ", Ev, Iv }, - { "orQ", Ev, Iv }, - { "adcQ", Ev, Iv }, - { "sbbQ", Ev, Iv }, - { "andQ", Ev, Iv }, - { "subQ", Ev, Iv }, - { "xorQ", Ev, Iv }, - { "cmpQ", Ev, Iv } - }, - /* GRP1Ss */ - { - { "addQ", Ev, sIb }, - { "orQ", Ev, sIb }, - { "adcQ", Ev, sIb }, - { "sbbQ", Ev, sIb }, - { "andQ", Ev, sIb }, - { "subQ", Ev, sIb }, - { "xorQ", Ev, sIb }, - { "cmpQ", Ev, sIb } - }, - /* GRP2b */ - { - { "rolA", Eb, Ib }, - { "rorA", Eb, Ib }, - { "rclA", Eb, Ib }, - { "rcrA", Eb, Ib }, - { "shlA", Eb, Ib }, - { "shrA", Eb, Ib }, - { "(bad)" }, - { "sarA", Eb, Ib }, - }, - /* GRP2S */ - { - { "rolQ", Ev, Ib }, - { "rorQ", Ev, Ib }, - { "rclQ", Ev, Ib }, - { "rcrQ", Ev, Ib }, - { "shlQ", Ev, Ib }, - { "shrQ", Ev, Ib }, - { "(bad)" }, - { "sarQ", Ev, Ib }, - }, - /* GRP2b_one */ - { - { "rolA", Eb }, - { "rorA", Eb }, - { "rclA", Eb }, - { "rcrA", Eb }, - { "shlA", Eb }, - { "shrA", Eb }, - { "(bad)" }, - { "sarA", Eb }, - }, - /* GRP2S_one */ - { - { "rolQ", Ev }, - { "rorQ", Ev }, - { "rclQ", Ev }, - { "rcrQ", Ev }, - { "shlQ", Ev }, - { "shrQ", Ev }, - { "(bad)" }, - { "sarQ", Ev }, - }, - /* GRP2b_cl */ - { - { "rolA", Eb, CL }, - { "rorA", Eb, CL }, - { "rclA", Eb, CL }, - { "rcrA", Eb, CL }, - { "shlA", Eb, CL }, - { "shrA", Eb, CL }, - { "(bad)" }, - { "sarA", Eb, CL }, - }, - /* GRP2S_cl */ - { - { "rolQ", Ev, CL }, - { "rorQ", Ev, CL }, - { "rclQ", Ev, CL }, - { "rcrQ", Ev, CL }, - { "shlQ", Ev, CL }, - { "shrQ", Ev, CL }, - { "(bad)" }, - { "sarQ", Ev, CL } - }, - /* GRP3b */ - { - { "testA", Eb, Ib }, - { "(bad)", Eb }, - { "notA", Eb }, - { "negA", Eb }, - { "mulB", AL, Eb }, - { "imulB", AL, Eb }, - { "divB", AL, Eb }, - { "idivB", AL, Eb } - }, - /* GRP3S */ - { - { "testQ", Ev, Iv }, - { "(bad)" }, - { "notQ", Ev }, - { "negQ", Ev }, - { "mulS", eAX, Ev }, - { "imulS", eAX, Ev }, - { "divS", eAX, Ev }, - { "idivS", eAX, Ev }, - }, - /* GRP4 */ - { - { "incA", Eb }, - { "decA", Eb }, - { "(bad)" }, - { "(bad)" }, - { "(bad)" }, - { "(bad)" }, - { "(bad)" }, - { "(bad)" }, - }, - /* GRP5 */ - { - { "incQ", Ev }, - { "decQ", Ev }, - { "callP", indirEv }, - { "lcallP", indirEv }, - { "jmpP", indirEv }, - { "ljmpP", indirEv }, - { "pushQ", Ev }, - { "(bad)" }, - }, - /* GRP6 */ - { - { "sldt", Ew }, - { "str", Ew }, - { "lldt", Ew }, - { "ltr", Ew }, - { "verr", Ew }, - { "verw", Ew }, - { "(bad)" }, - { "(bad)" } - }, - /* GRP7 */ - { - { "sgdt", Ew }, - { "sidt", Ew }, - { "lgdt", Ew }, - { "lidt", Ew }, - { "smsw", Ew }, - { "(bad)" }, - { "lmsw", Ew }, - { "invlpg", Ew }, - }, - /* GRP8 */ - { - { "(bad)" }, - { "(bad)" }, - { "(bad)" }, - { "(bad)" }, - { "btQ", Ev, Ib }, - { "btsQ", Ev, Ib }, - { "btrQ", Ev, Ib }, - { "btcQ", Ev, Ib }, - }, - /* GRP9 */ - { - { "(bad)" }, - { "cmpxchg8b", Ev }, - { "(bad)" }, - { "(bad)" }, - { "(bad)" }, - { "(bad)" }, - { "(bad)" }, - { "(bad)" }, - }, - /* GRP10 */ - { - { "(bad)" }, - { "(bad)" }, - { "psrlw", MS, Ib }, - { "(bad)" }, - { "psraw", MS, Ib }, - { "(bad)" }, - { "psllw", MS, Ib }, - { "(bad)" }, - }, - /* GRP11 */ - { - { "(bad)" }, - { "(bad)" }, - { "psrld", MS, Ib }, - { "(bad)" }, - { "psrad", MS, Ib }, - { "(bad)" }, - { "pslld", MS, Ib }, - { "(bad)" }, - }, - /* GRP12 */ - { - { "(bad)" }, - { "(bad)" }, - { "psrlq", MS, Ib }, - { "(bad)" }, - { "(bad)" }, - { "(bad)" }, - { "psllq", MS, Ib }, - { "(bad)" }, - } -}; - -#define PREFIX_REPZ 1 -#define PREFIX_REPNZ 2 -#define PREFIX_LOCK 4 -#define PREFIX_CS 8 -#define PREFIX_SS 0x10 -#define PREFIX_DS 0x20 -#define PREFIX_ES 0x40 -#define PREFIX_FS 0x80 -#define PREFIX_GS 0x100 -#define PREFIX_DATA 0x200 -#define PREFIX_ADDR 0x400 -#define PREFIX_FWAIT 0x800 - -static int prefixes; - -static void -ckprefix () -{ - prefixes = 0; - while (1) - { - FETCH_DATA (the_info, codep + 1); - switch (*codep) - { - case 0xf3: - prefixes |= PREFIX_REPZ; - break; - case 0xf2: - prefixes |= PREFIX_REPNZ; - break; - case 0xf0: - prefixes |= PREFIX_LOCK; - break; - case 0x2e: - prefixes |= PREFIX_CS; - break; - case 0x36: - prefixes |= PREFIX_SS; - break; - case 0x3e: - prefixes |= PREFIX_DS; - break; - case 0x26: - prefixes |= PREFIX_ES; - break; - case 0x64: - prefixes |= PREFIX_FS; - break; - case 0x65: - prefixes |= PREFIX_GS; - break; - case 0x66: - prefixes |= PREFIX_DATA; - break; - case 0x67: - prefixes |= PREFIX_ADDR; - break; - case 0x9b: - prefixes |= PREFIX_FWAIT; - codep++; /* fwait is really an instruction */ - return; /* so stop accumulating prefixes */ - default: - return; - } - codep++; - } -} - -static char op1out[100], op2out[100], op3out[100]; -static int op_ad, op_index[3]; -static unsigned int op_address[3]; -static unsigned int start_pc; - - -/* - * On the 386's of 1988, the maximum length of an instruction is 15 bytes. - * (see topic "Redundant prefixes" in the "Differences from 8086" - * section of the "Virtual 8086 Mode" chapter.) - * 'pc' should be the address of this instruction, it will - * be used to print the target address if this is a relative jump or call - * The function returns the length of this instruction in bytes. - */ - -int print_insn_x86 PARAMS ((bfd_vma pc, disassemble_info *info, int sizeflag)); - -int -print_insn_i386 (pc, info) - bfd_vma pc; - disassemble_info *info; -{ - int flags; - if (info->mach == bfd_mach_i386_i386) - flags = AFLAG|DFLAG; - else if (info->mach == bfd_mach_i386_i8086) - flags = 0; - else - abort (); - return print_insn_x86 (pc, info, flags); -} - -int -print_insn_x86 (pc, info, sizeflag) - bfd_vma pc; - disassemble_info *info; - int sizeflag; -{ - struct dis386 *dp; - int i; - int two_source_ops; - char *first, *second, *third; - int needcomma; - unsigned char need_modrm; - - struct dis_private priv; - bfd_byte *inbuf = priv.the_buffer; - - /* The output looks better if we put 5 bytes on a line, since that - puts long word instructions on a single line. */ - info->bytes_per_line = 5; - - info->private_data = (PTR) &priv; - priv.max_fetched = priv.the_buffer; - priv.insn_start = pc; - if (setjmp (priv.bailout) != 0) - /* Error return. */ - return -1; - - obuf[0] = 0; - op1out[0] = 0; - op2out[0] = 0; - op3out[0] = 0; - - op_index[0] = op_index[1] = op_index[2] = -1; - - the_info = info; - start_pc = pc; - start_codep = inbuf; - codep = inbuf; - - ckprefix (); - - FETCH_DATA (info, codep + 1); - two_source_ops = (*codep == 0x62) || (*codep == 0xc8); - - obufp = obuf; - - if ((prefixes & PREFIX_FWAIT) - && ((*codep < 0xd8) || (*codep > 0xdf))) - { - /* fwait not followed by floating point instruction. */ - (*info->fprintf_func) (info->stream, "fwait"); - /* There may be other prefixes. Skip any before the fwait. */ - return codep - inbuf; - } - - if (prefixes & PREFIX_REPZ) - oappend ("repz "); - if (prefixes & PREFIX_REPNZ) - oappend ("repnz "); - if (prefixes & PREFIX_LOCK) - oappend ("lock "); - - if (prefixes & PREFIX_DATA) - sizeflag ^= DFLAG; - - if (prefixes & PREFIX_ADDR) - { - sizeflag ^= AFLAG; - if (sizeflag & AFLAG) - oappend ("addr32 "); - else - oappend ("addr16 "); - } - - if (*codep == 0x0f) - { - FETCH_DATA (info, codep + 2); - dp = &dis386_twobyte[*++codep]; - need_modrm = twobyte_has_modrm[*codep]; - } - else - { - dp = &dis386[*codep]; - need_modrm = onebyte_has_modrm[*codep]; - } - codep++; - - if (need_modrm) - { - FETCH_DATA (info, codep + 1); - mod = (*codep >> 6) & 3; - reg = (*codep >> 3) & 7; - rm = *codep & 7; - } - - if (dp->name == NULL && dp->bytemode1 == FLOATCODE) - { - dofloat (sizeflag); - } - else - { - if (dp->name == NULL) - dp = &grps[dp->bytemode1][reg]; - - putop (dp->name, sizeflag); - - obufp = op1out; - op_ad = 2; - if (dp->op1) - (*dp->op1)(dp->bytemode1, sizeflag); - - obufp = op2out; - op_ad = 1; - if (dp->op2) - (*dp->op2)(dp->bytemode2, sizeflag); - - obufp = op3out; - op_ad = 0; - if (dp->op3) - (*dp->op3)(dp->bytemode3, sizeflag); - } - - obufp = obuf + strlen (obuf); - for (i = strlen (obuf); i < 6; i++) - oappend (" "); - oappend (" "); - (*info->fprintf_func) (info->stream, "%s", obuf); - - /* The enter and bound instructions are printed with operands in the same - order as the intel book; everything else is printed in reverse order. */ - if (two_source_ops) - { - first = op1out; - second = op2out; - third = op3out; - op_ad = op_index[0]; - op_index[0] = op_index[2]; - op_index[2] = op_ad; - } - else - { - first = op3out; - second = op2out; - third = op1out; - } - needcomma = 0; - if (*first) - { - if (op_index[0] != -1) - (*info->print_address_func) ((bfd_vma) op_address[op_index[0]], info); - else - (*info->fprintf_func) (info->stream, "%s", first); - needcomma = 1; - } - if (*second) - { - if (needcomma) - (*info->fprintf_func) (info->stream, ","); - if (op_index[1] != -1) - (*info->print_address_func) ((bfd_vma) op_address[op_index[1]], info); - else - (*info->fprintf_func) (info->stream, "%s", second); - needcomma = 1; - } - if (*third) - { - if (needcomma) - (*info->fprintf_func) (info->stream, ","); - if (op_index[2] != -1) - (*info->print_address_func) ((bfd_vma) op_address[op_index[2]], info); - else - (*info->fprintf_func) (info->stream, "%s", third); - } - return codep - inbuf; -} - -static char *float_mem[] = { - /* d8 */ - "fadds", - "fmuls", - "fcoms", - "fcomps", - "fsubs", - "fsubrs", - "fdivs", - "fdivrs", - /* d9 */ - "flds", - "(bad)", - "fsts", - "fstps", - "fldenv", - "fldcw", - "fNstenv", - "fNstcw", - /* da */ - "fiaddl", - "fimull", - "ficoml", - "ficompl", - "fisubl", - "fisubrl", - "fidivl", - "fidivrl", - /* db */ - "fildl", - "(bad)", - "fistl", - "fistpl", - "(bad)", - "fldt", - "(bad)", - "fstpt", - /* dc */ - "faddl", - "fmull", - "fcoml", - "fcompl", - "fsubl", - "fsubrl", - "fdivl", - "fdivrl", - /* dd */ - "fldl", - "(bad)", - "fstl", - "fstpl", - "frstor", - "(bad)", - "fNsave", - "fNstsw", - /* de */ - "fiadd", - "fimul", - "ficom", - "ficomp", - "fisub", - "fisubr", - "fidiv", - "fidivr", - /* df */ - "fild", - "(bad)", - "fist", - "fistp", - "fbld", - "fildll", - "fbstp", - "fistpll", -}; - -#define ST OP_ST, 0 -#define STi OP_STi, 0 - -#define FGRPd9_2 NULL, NULL, 0 -#define FGRPd9_4 NULL, NULL, 1 -#define FGRPd9_5 NULL, NULL, 2 -#define FGRPd9_6 NULL, NULL, 3 -#define FGRPd9_7 NULL, NULL, 4 -#define FGRPda_5 NULL, NULL, 5 -#define FGRPdb_4 NULL, NULL, 6 -#define FGRPde_3 NULL, NULL, 7 -#define FGRPdf_4 NULL, NULL, 8 - -static struct dis386 float_reg[][8] = { - /* d8 */ - { - { "fadd", ST, STi }, - { "fmul", ST, STi }, - { "fcom", STi }, - { "fcomp", STi }, - { "fsub", ST, STi }, - { "fsubr", ST, STi }, - { "fdiv", ST, STi }, - { "fdivr", ST, STi }, - }, - /* d9 */ - { - { "fld", STi }, - { "fxch", STi }, - { FGRPd9_2 }, - { "(bad)" }, - { FGRPd9_4 }, - { FGRPd9_5 }, - { FGRPd9_6 }, - { FGRPd9_7 }, - }, - /* da */ - { - { "fcmovb", ST, STi }, - { "fcmove", ST, STi }, - { "fcmovbe",ST, STi }, - { "fcmovu", ST, STi }, - { "(bad)" }, - { FGRPda_5 }, - { "(bad)" }, - { "(bad)" }, - }, - /* db */ - { - { "fcmovnb",ST, STi }, - { "fcmovne",ST, STi }, - { "fcmovnbe",ST, STi }, - { "fcmovnu",ST, STi }, - { FGRPdb_4 }, - { "fucomi", ST, STi }, - { "fcomi", ST, STi }, - { "(bad)" }, - }, - /* dc */ - { - { "fadd", STi, ST }, - { "fmul", STi, ST }, - { "(bad)" }, - { "(bad)" }, -#if UNIXWARE_COMPAT - { "fsub", STi, ST }, - { "fsubr", STi, ST }, - { "fdiv", STi, ST }, - { "fdivr", STi, ST }, -#else - { "fsubr", STi, ST }, - { "fsub", STi, ST }, - { "fdivr", STi, ST }, - { "fdiv", STi, ST }, -#endif - }, - /* dd */ - { - { "ffree", STi }, - { "(bad)" }, - { "fst", STi }, - { "fstp", STi }, - { "fucom", STi }, - { "fucomp", STi }, - { "(bad)" }, - { "(bad)" }, - }, - /* de */ - { - { "faddp", STi, ST }, - { "fmulp", STi, ST }, - { "(bad)" }, - { FGRPde_3 }, -#if UNIXWARE_COMPAT - { "fsubp", STi, ST }, - { "fsubrp", STi, ST }, - { "fdivp", STi, ST }, - { "fdivrp", STi, ST }, -#else - { "fsubrp", STi, ST }, - { "fsubp", STi, ST }, - { "fdivrp", STi, ST }, - { "fdivp", STi, ST }, -#endif - }, - /* df */ - { - { "(bad)" }, - { "(bad)" }, - { "(bad)" }, - { "(bad)" }, - { FGRPdf_4 }, - { "fucomip",ST, STi }, - { "fcomip", ST, STi }, - { "(bad)" }, - }, -}; - - -static char *fgrps[][8] = { - /* d9_2 0 */ - { - "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", - }, - - /* d9_4 1 */ - { - "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", - }, - - /* d9_5 2 */ - { - "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", - }, - - /* d9_6 3 */ - { - "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", - }, - - /* d9_7 4 */ - { - "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", - }, - - /* da_5 5 */ - { - "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", - }, - - /* db_4 6 */ - { - "feni(287 only)","fdisi(287 only)","fNclex","fNinit", - "fNsetpm(287 only)","(bad)","(bad)","(bad)", - }, - - /* de_3 7 */ - { - "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", - }, - - /* df_4 8 */ - { - "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", - }, -}; - -static void -dofloat (sizeflag) - int sizeflag; -{ - struct dis386 *dp; - unsigned char floatop; - - floatop = codep[-1]; - - if (mod != 3) - { - putop (float_mem[(floatop - 0xd8) * 8 + reg], sizeflag); - obufp = op1out; - OP_E (v_mode, sizeflag); - return; - } - codep++; - - dp = &float_reg[floatop - 0xd8][reg]; - if (dp->name == NULL) - { - putop (fgrps[dp->bytemode1][rm], sizeflag); - /* instruction fnstsw is only one with strange arg */ - if (floatop == 0xdf - && FETCH_DATA (the_info, codep + 1) - && *codep == 0xe0) - strcpy (op1out, "%eax"); - } - else - { - putop (dp->name, sizeflag); - obufp = op1out; - if (dp->op1) - (*dp->op1)(dp->bytemode1, sizeflag); - obufp = op2out; - if (dp->op2) - (*dp->op2)(dp->bytemode2, sizeflag); - } -} - -/* ARGSUSED */ -static void -OP_ST (ignore, sizeflag) - int ignore; - int sizeflag; -{ - oappend ("%st"); -} - -/* ARGSUSED */ -static void -OP_STi (ignore, sizeflag) - int ignore; - int sizeflag; -{ - sprintf (scratchbuf, "%%st(%d)", rm); - oappend (scratchbuf); -} - - -/* capital letters in template are macros */ -static void -putop (template, sizeflag) - char *template; - int sizeflag; -{ - char *p; - - for (p = template; *p; p++) - { - switch (*p) - { - default: - *obufp++ = *p; - break; - case 'A': - if (mod != 3 -#ifdef SUFFIX_ALWAYS - || (sizeflag & SUFFIX_ALWAYS) -#endif - ) - *obufp++ = 'b'; - break; - case 'B': -#ifdef SUFFIX_ALWAYS - if (sizeflag & SUFFIX_ALWAYS) - *obufp++ = 'b'; -#endif - break; - case 'E': /* For jcxz/jecxz */ - if (sizeflag & AFLAG) - *obufp++ = 'e'; - break; - case 'L': -#ifdef SUFFIX_ALWAYS - if (sizeflag & SUFFIX_ALWAYS) - *obufp++ = 'l'; -#endif - break; - case 'N': - if ((prefixes & PREFIX_FWAIT) == 0) - *obufp++ = 'n'; - break; - case 'P': - if ((prefixes & PREFIX_DATA) -#ifdef SUFFIX_ALWAYS - || (sizeflag & SUFFIX_ALWAYS) -#endif - ) - { - if (sizeflag & DFLAG) - *obufp++ = 'l'; - else - *obufp++ = 'w'; - } - break; - case 'Q': - if (mod != 3 -#ifdef SUFFIX_ALWAYS - || (sizeflag & SUFFIX_ALWAYS) -#endif - ) - { - if (sizeflag & DFLAG) - *obufp++ = 'l'; - else - *obufp++ = 'w'; - } - break; - case 'R': - if (sizeflag & DFLAG) - *obufp++ = 'l'; - else - *obufp++ = 'w'; - break; - case 'S': -#ifdef SUFFIX_ALWAYS - if (sizeflag & SUFFIX_ALWAYS) - { - if (sizeflag & DFLAG) - *obufp++ = 'l'; - else - *obufp++ = 'w'; - } -#endif - break; - case 'W': - /* operand size flag for cwtl, cbtw */ - if (sizeflag & DFLAG) - *obufp++ = 'w'; - else - *obufp++ = 'b'; - break; - } - } - *obufp = 0; -} - -static void -oappend (s) - char *s; -{ - strcpy (obufp, s); - obufp += strlen (s); -} - -static void -append_seg () -{ - if (prefixes & PREFIX_CS) - oappend ("%cs:"); - if (prefixes & PREFIX_DS) - oappend ("%ds:"); - if (prefixes & PREFIX_SS) - oappend ("%ss:"); - if (prefixes & PREFIX_ES) - oappend ("%es:"); - if (prefixes & PREFIX_FS) - oappend ("%fs:"); - if (prefixes & PREFIX_GS) - oappend ("%gs:"); -} - -static void -OP_indirE (bytemode, sizeflag) - int bytemode; - int sizeflag; -{ - oappend ("*"); - OP_E (bytemode, sizeflag); -} - -static void -OP_E (bytemode, sizeflag) - int bytemode; - int sizeflag; -{ - int disp; - - /* skip mod/rm byte */ - codep++; - - if (mod == 3) - { - switch (bytemode) - { - case b_mode: - oappend (names8[rm]); - break; - case w_mode: - oappend (names16[rm]); - break; - case v_mode: - if (sizeflag & DFLAG) - oappend (names32[rm]); - else - oappend (names16[rm]); - break; - default: - oappend ("<bad dis table>"); - break; - } - return; - } - - disp = 0; - append_seg (); - - if (sizeflag & AFLAG) /* 32 bit address mode */ - { - int havesib; - int havebase; - int base; - int index = 0; - int scale = 0; - - havesib = 0; - havebase = 1; - base = rm; - - if (base == 4) - { - havesib = 1; - FETCH_DATA (the_info, codep + 1); - scale = (*codep >> 6) & 3; - index = (*codep >> 3) & 7; - base = *codep & 7; - codep++; - } - - switch (mod) - { - case 0: - if (base == 5) - { - havebase = 0; - disp = get32 (); - } - break; - case 1: - FETCH_DATA (the_info, codep + 1); - disp = *codep++; - if ((disp & 0x80) != 0) - disp -= 0x100; - break; - case 2: - disp = get32 (); - break; - } - - if (mod != 0 || base == 5) - { - sprintf (scratchbuf, "0x%x", disp); - oappend (scratchbuf); - } - - if (havebase || (havesib && (index != 4 || scale != 0))) - { - oappend ("("); - if (havebase) - oappend (names32[base]); - if (havesib) - { - if (index != 4) - { - sprintf (scratchbuf, ",%s", names32[index]); - oappend (scratchbuf); - } - sprintf (scratchbuf, ",%d", 1 << scale); - oappend (scratchbuf); - } - oappend (")"); - } - } - else - { /* 16 bit address mode */ - switch (mod) - { - case 0: - if (rm == 6) - { - disp = get16 (); - if ((disp & 0x8000) != 0) - disp -= 0x10000; - } - break; - case 1: - FETCH_DATA (the_info, codep + 1); - disp = *codep++; - if ((disp & 0x80) != 0) - disp -= 0x100; - break; - case 2: - disp = get16 (); - if ((disp & 0x8000) != 0) - disp -= 0x10000; - break; - } - - if (mod != 0 || rm == 6) - { - sprintf (scratchbuf, "0x%x", disp); - oappend (scratchbuf); - } - - if (mod != 0 || rm != 6) - { - oappend ("("); - oappend (index16[rm]); - oappend (")"); - } - } -} - -#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") - -static void -OP_G (bytemode, sizeflag) - int bytemode; - int sizeflag; -{ - switch (bytemode) - { - case b_mode: - oappend (names8[reg]); - break; - case w_mode: - oappend (names16[reg]); - break; - case d_mode: - oappend (names32[reg]); - break; - case v_mode: - if (sizeflag & DFLAG) - oappend (names32[reg]); - else - oappend (names16[reg]); - break; - default: - oappend (INTERNAL_DISASSEMBLER_ERROR); - break; - } -} - -static int -get32 () -{ - int x = 0; - - FETCH_DATA (the_info, codep + 4); - x = *codep++ & 0xff; - x |= (*codep++ & 0xff) << 8; - x |= (*codep++ & 0xff) << 16; - x |= (*codep++ & 0xff) << 24; - return x; -} - -static int -get16 () -{ - int x = 0; - - FETCH_DATA (the_info, codep + 2); - x = *codep++ & 0xff; - x |= (*codep++ & 0xff) << 8; - return x; -} - -static void -set_op (op) - unsigned int op; -{ - op_index[op_ad] = op_ad; - op_address[op_ad] = op; -} - -static void -OP_REG (code, sizeflag) - int code; - int sizeflag; -{ - char *s; - - switch (code) - { - case indir_dx_reg: s = "(%dx)"; break; - case ax_reg: case cx_reg: case dx_reg: case bx_reg: - case sp_reg: case bp_reg: case si_reg: case di_reg: - s = names16[code - ax_reg]; - break; - case es_reg: case ss_reg: case cs_reg: - case ds_reg: case fs_reg: case gs_reg: - s = names_seg[code - es_reg]; - break; - case al_reg: case ah_reg: case cl_reg: case ch_reg: - case dl_reg: case dh_reg: case bl_reg: case bh_reg: - s = names8[code - al_reg]; - break; - case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: - case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: - if (sizeflag & DFLAG) - s = names32[code - eAX_reg]; - else - s = names16[code - eAX_reg]; - break; - default: - s = INTERNAL_DISASSEMBLER_ERROR; - break; - } - oappend (s); -} - -static void -OP_I (bytemode, sizeflag) - int bytemode; - int sizeflag; -{ - int op; - - switch (bytemode) - { - case b_mode: - FETCH_DATA (the_info, codep + 1); - op = *codep++ & 0xff; - break; - case v_mode: - if (sizeflag & DFLAG) - op = get32 (); - else - op = get16 (); - break; - case w_mode: - op = get16 (); - break; - default: - oappend (INTERNAL_DISASSEMBLER_ERROR); - return; - } - sprintf (scratchbuf, "$0x%x", op); - oappend (scratchbuf); -} - -static void -OP_sI (bytemode, sizeflag) - int bytemode; - int sizeflag; -{ - int op; - - switch (bytemode) - { - case b_mode: - FETCH_DATA (the_info, codep + 1); - op = *codep++; - if ((op & 0x80) != 0) - op -= 0x100; - break; - case v_mode: - if (sizeflag & DFLAG) - op = get32 (); - else - { - op = get16(); - if ((op & 0x8000) != 0) - op -= 0x10000; - } - break; - case w_mode: - op = get16 (); - if ((op & 0x8000) != 0) - op -= 0x10000; - break; - default: - oappend (INTERNAL_DISASSEMBLER_ERROR); - return; - } - sprintf (scratchbuf, "$0x%x", op); - oappend (scratchbuf); -} - -static void -OP_J (bytemode, sizeflag) - int bytemode; - int sizeflag; -{ - int disp; - int mask = -1; - - switch (bytemode) - { - case b_mode: - FETCH_DATA (the_info, codep + 1); - disp = *codep++; - if ((disp & 0x80) != 0) - disp -= 0x100; - break; - case v_mode: - if (sizeflag & DFLAG) - disp = get32 (); - else - { - disp = get16 (); - if ((disp & 0x8000) != 0) - disp -= 0x10000; - /* for some reason, a data16 prefix on a jump instruction - means that the pc is masked to 16 bits after the - displacement is added! */ - mask = 0xffff; - } - break; - default: - oappend (INTERNAL_DISASSEMBLER_ERROR); - return; - } - disp = (start_pc + codep - start_codep + disp) & mask; - set_op (disp); - sprintf (scratchbuf, "0x%x", disp); - oappend (scratchbuf); -} - -/* ARGSUSED */ -static void -OP_SEG (dummy, sizeflag) - int dummy; - int sizeflag; -{ - static char *sreg[] = { - "%es","%cs","%ss","%ds","%fs","%gs","%?","%?", - }; - - oappend (sreg[reg]); -} - -static void -OP_DIR (size, sizeflag) - int size; - int sizeflag; -{ - int seg, offset; - - switch (size) - { - case lptr: - if (sizeflag & DFLAG) - { - offset = get32 (); - seg = get16 (); - } - else - { - offset = get16 (); - seg = get16 (); - } - sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); - oappend (scratchbuf); - break; - case v_mode: - if (sizeflag & DFLAG) - offset = get32 (); - else - { - offset = get16 (); - if ((offset & 0x8000) != 0) - offset -= 0x10000; - } - - offset = start_pc + codep - start_codep + offset; - set_op (offset); - sprintf (scratchbuf, "0x%x", offset); - oappend (scratchbuf); - break; - default: - oappend (INTERNAL_DISASSEMBLER_ERROR); - break; - } -} - -/* ARGSUSED */ -static void -OP_OFF (ignore, sizeflag) - int ignore; - int sizeflag; -{ - int off; - - append_seg (); - - if (sizeflag & AFLAG) - off = get32 (); - else - off = get16 (); - - sprintf (scratchbuf, "0x%x", off); - oappend (scratchbuf); -} - -static void -ptr_reg (code, sizeflag) - int code; - int sizeflag; -{ - char *s; - oappend ("("); - if (sizeflag & AFLAG) - s = names32[code - eAX_reg]; - else - s = names16[code - eAX_reg]; - oappend (s); - oappend (")"); -} - -static void -OP_ESreg (code, sizeflag) - int code; - int sizeflag; -{ - oappend ("%es:"); - ptr_reg (code, sizeflag); -} - -static void -OP_DSreg (code, sizeflag) - int code; - int sizeflag; -{ - if ((prefixes - & (PREFIX_CS - | PREFIX_DS - | PREFIX_SS - | PREFIX_ES - | PREFIX_FS - | PREFIX_GS)) == 0) - prefixes |= PREFIX_DS; - append_seg(); - ptr_reg (code, sizeflag); -} - -#if 0 -/* Not used. */ - -/* ARGSUSED */ -static void -OP_ONE (dummy, sizeflag) - int dummy; - int sizeflag; -{ - oappend ("1"); -} - -#endif - -/* ARGSUSED */ -static void -OP_C (dummy, sizeflag) - int dummy; - int sizeflag; -{ - codep++; /* skip mod/rm */ - sprintf (scratchbuf, "%%cr%d", reg); - oappend (scratchbuf); -} - -/* ARGSUSED */ -static void -OP_D (dummy, sizeflag) - int dummy; - int sizeflag; -{ - codep++; /* skip mod/rm */ - sprintf (scratchbuf, "%%db%d", reg); - oappend (scratchbuf); -} - -/* ARGSUSED */ -static void -OP_T (dummy, sizeflag) - int dummy; - int sizeflag; -{ - codep++; /* skip mod/rm */ - sprintf (scratchbuf, "%%tr%d", reg); - oappend (scratchbuf); -} - -static void -OP_rm (bytemode, sizeflag) - int bytemode; - int sizeflag; -{ - switch (bytemode) - { - case d_mode: - oappend (names32[rm]); - break; - case w_mode: - oappend (names16[rm]); - break; - } -} - -static void -OP_MMX (ignore, sizeflag) - int ignore; - int sizeflag; -{ - sprintf (scratchbuf, "%%mm%d", reg); - oappend (scratchbuf); -} - -static void -OP_EM (bytemode, sizeflag) - int bytemode; - int sizeflag; -{ - if (mod != 3) - { - OP_E (bytemode, sizeflag); - return; - } - - codep++; - sprintf (scratchbuf, "%%mm%d", rm); - oappend (scratchbuf); -} - -static void -OP_MS (ignore, sizeflag) - int ignore; - int sizeflag; -{ - ++codep; - sprintf (scratchbuf, "%%mm%d", rm); - oappend (scratchbuf); -} diff --git a/opcodes/i960-dis.c b/opcodes/i960-dis.c deleted file mode 100644 index 0612d04efb4..00000000000 --- a/opcodes/i960-dis.c +++ /dev/null @@ -1,914 +0,0 @@ -/* Disassemble i80960 instructions. - Copyright (C) 1990, 1991 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; see the file COPYING. If not, write to -the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ - -#include "dis-asm.h" - -static const char *const reg_names[] = { -/* 0 */ "pfp", "sp", "rip", "r3", "r4", "r5", "r6", "r7", -/* 8 */ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", -/* 16 */ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", -/* 24 */ "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp", -/* 32 */ "pc", "ac", "ip", "tc", "fp0", "fp1", "fp2", "fp3" -}; - - -static FILE *stream; /* Output goes here */ -static struct disassemble_info *info; -static void print_addr(); -static void ctrl(); -static void cobr(); -static void reg(); -static int mem(); -static void ea(); -static void dstop(); -static void regop(); -static void invalid(); -static int pinsn(); -static void put_abs(); - - -/* Print the i960 instruction at address 'memaddr' in debugged memory, - on INFO->STREAM. Returns length of the instruction, in bytes. */ - -int -print_insn_i960 (memaddr, info_arg) - bfd_vma memaddr; - struct disassemble_info *info_arg; -{ - unsigned int word1, word2 = 0xdeadbeef; - bfd_byte buffer[8]; - int status; - - info = info_arg; - stream = info->stream; - - /* Read word1. Only read word2 if the instruction - needs it, to prevent reading past the end of a section. */ - - status = (*info->read_memory_func) (memaddr, (bfd_byte *) buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - - word1 = bfd_getl32 (buffer); - - /* Divide instruction set into classes based on high 4 bits of opcode. */ - switch ( (word1 >> 28) & 0xf ) - { - default: - break; - case 0x8: - case 0x9: - case 0xa: - case 0xb: - case 0xc: - /* Read word2. */ - status = (*info->read_memory_func) - (memaddr + 4, (bfd_byte *) (buffer + 4), 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - word2 = bfd_getl32 (buffer + 4); - break; - } - - return pinsn( memaddr, word1, word2 ); -} - -#define IN_GDB - -/***************************************************************************** - * All code below this point should be identical with that of - * the disassembler in gdmp960. - - A noble sentiment, but at least in cosmetic ways (info->fprintf_func), it - just ain't so. -kingdon, 31 Mar 93 - *****************************************************************************/ - -struct tabent { - char *name; - signed char numops; -}; - -struct sparse_tabent { - int opcode; - char *name; - signed char numops; -}; - -static int -pinsn( memaddr, word1, word2 ) - unsigned long memaddr; - unsigned long word1, word2; -{ - int instr_len; - - instr_len = 4; - put_abs( word1, word2 ); - - /* Divide instruction set into classes based on high 4 bits of opcode*/ - switch ( (word1 >> 28) & 0xf ){ - case 0x0: - case 0x1: - ctrl( memaddr, word1, word2 ); - break; - case 0x2: - case 0x3: - cobr( memaddr, word1, word2 ); - break; - case 0x5: - case 0x6: - case 0x7: - reg( word1 ); - break; - case 0x8: - case 0x9: - case 0xa: - case 0xb: - case 0xc: - instr_len = mem( memaddr, word1, word2, 0 ); - break; - default: - /* invalid instruction, print as data word */ - invalid( word1 ); - break; - } - return instr_len; -} - -/****************************************/ -/* CTRL format */ -/****************************************/ -static void -ctrl( memaddr, word1, word2 ) - unsigned long memaddr; - unsigned long word1, word2; -{ - int i; - static const struct tabent ctrl_tab[] = { - NULL, 0, /* 0x00 */ - NULL, 0, /* 0x01 */ - NULL, 0, /* 0x02 */ - NULL, 0, /* 0x03 */ - NULL, 0, /* 0x04 */ - NULL, 0, /* 0x05 */ - NULL, 0, /* 0x06 */ - NULL, 0, /* 0x07 */ - "b", 1, /* 0x08 */ - "call", 1, /* 0x09 */ - "ret", 0, /* 0x0a */ - "bal", 1, /* 0x0b */ - NULL, 0, /* 0x0c */ - NULL, 0, /* 0x0d */ - NULL, 0, /* 0x0e */ - NULL, 0, /* 0x0f */ - "bno", 1, /* 0x10 */ - "bg", 1, /* 0x11 */ - "be", 1, /* 0x12 */ - "bge", 1, /* 0x13 */ - "bl", 1, /* 0x14 */ - "bne", 1, /* 0x15 */ - "ble", 1, /* 0x16 */ - "bo", 1, /* 0x17 */ - "faultno", 0, /* 0x18 */ - "faultg", 0, /* 0x19 */ - "faulte", 0, /* 0x1a */ - "faultge", 0, /* 0x1b */ - "faultl", 0, /* 0x1c */ - "faultne", 0, /* 0x1d */ - "faultle", 0, /* 0x1e */ - "faulto", 0, /* 0x1f */ - }; - - i = (word1 >> 24) & 0xff; - if ( (ctrl_tab[i].name == NULL) || ((word1 & 1) != 0) ){ - invalid( word1 ); - return; - } - - (*info->fprintf_func) ( stream, ctrl_tab[i].name ); - if ( word1 & 2 ){ /* Predicts branch not taken */ - (*info->fprintf_func) ( stream, ".f" ); - } - - if ( ctrl_tab[i].numops == 1 ){ - /* EXTRACT DISPLACEMENT AND CONVERT TO ADDRESS */ - word1 &= 0x00ffffff; - if ( word1 & 0x00800000 ){ /* Sign bit is set */ - word1 |= (-1 & ~0xffffff); /* Sign extend */ - } - (*info->fprintf_func)( stream, "\t" ); - print_addr( word1 + memaddr ); - } -} - -/****************************************/ -/* COBR format */ -/****************************************/ -static void -cobr( memaddr, word1, word2 ) - unsigned long memaddr; - unsigned long word1, word2; -{ - int src1; - int src2; - int i; - - static const struct tabent cobr_tab[] = { - "testno", 1, /* 0x20 */ - "testg", 1, /* 0x21 */ - "teste", 1, /* 0x22 */ - "testge", 1, /* 0x23 */ - "testl", 1, /* 0x24 */ - "testne", 1, /* 0x25 */ - "testle", 1, /* 0x26 */ - "testo", 1, /* 0x27 */ - NULL, 0, /* 0x28 */ - NULL, 0, /* 0x29 */ - NULL, 0, /* 0x2a */ - NULL, 0, /* 0x2b */ - NULL, 0, /* 0x2c */ - NULL, 0, /* 0x2d */ - NULL, 0, /* 0x2e */ - NULL, 0, /* 0x2f */ - "bbc", 3, /* 0x30 */ - "cmpobg", 3, /* 0x31 */ - "cmpobe", 3, /* 0x32 */ - "cmpobge", 3, /* 0x33 */ - "cmpobl", 3, /* 0x34 */ - "cmpobne", 3, /* 0x35 */ - "cmpoble", 3, /* 0x36 */ - "bbs", 3, /* 0x37 */ - "cmpibno", 3, /* 0x38 */ - "cmpibg", 3, /* 0x39 */ - "cmpibe", 3, /* 0x3a */ - "cmpibge", 3, /* 0x3b */ - "cmpibl", 3, /* 0x3c */ - "cmpibne", 3, /* 0x3d */ - "cmpible", 3, /* 0x3e */ - "cmpibo", 3, /* 0x3f */ - }; - - i = ((word1 >> 24) & 0xff) - 0x20; - if ( cobr_tab[i].name == NULL ){ - invalid( word1 ); - return; - } - - (*info->fprintf_func) ( stream, cobr_tab[i].name ); - if ( word1 & 2 ){ /* Predicts branch not taken */ - (*info->fprintf_func) ( stream, ".f" ); - } - (*info->fprintf_func)( stream, "\t" ); - - src1 = (word1 >> 19) & 0x1f; - src2 = (word1 >> 14) & 0x1f; - - if ( word1 & 0x02000 ){ /* M1 is 1 */ - (*info->fprintf_func)( stream, "%d", src1 ); - } else { /* M1 is 0 */ - (*info->fprintf_func)( stream, reg_names[src1] ); - } - - if ( cobr_tab[i].numops > 1 ){ - if ( word1 & 1 ){ /* S2 is 1 */ - (*info->fprintf_func)( stream, ",sf%d,", src2 ); - } else { /* S1 is 0 */ - (*info->fprintf_func)( stream, ",%s,", reg_names[src2] ); - } - - /* Extract displacement and convert to address - */ - word1 &= 0x00001ffc; - if ( word1 & 0x00001000 ){ /* Negative displacement */ - word1 |= (-1 & ~0x1fff); /* Sign extend */ - } - print_addr( memaddr + word1 ); - } -} - -/****************************************/ -/* MEM format */ -/****************************************/ -static int /* returns instruction length: 4 or 8 */ -mem( memaddr, word1, word2, noprint ) - unsigned long memaddr; - unsigned long word1, word2; - int noprint; /* If TRUE, return instruction length, but - * don't output any text. - */ -{ - int i, j; - int len; - int mode; - int offset; - const char *reg1, *reg2, *reg3; - - /* This lookup table is too sparse to make it worth typing in, but not - so large as to make a sparse array necessary. We create the table - at runtime. */ - - /* - * NOTE: In this table, the meaning of 'numops' is: - * 1: single operand - * 2: 2 operands, load instruction - * -2: 2 operands, store instruction - */ - static struct tabent *mem_tab; -/* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */ -#define MEM_MIN 0x80 -#define MEM_MAX 0xcf -#define MEM_SIZ ( * sizeof(struct tabent)) - - static const struct sparse_tabent mem_init[] = { - 0x80, "ldob", 2, - 0x82, "stob", -2, - 0x84, "bx", 1, - 0x85, "balx", 2, - 0x86, "callx", 1, - 0x88, "ldos", 2, - 0x8a, "stos", -2, - 0x8c, "lda", 2, - 0x90, "ld", 2, - 0x92, "st", -2, - 0x98, "ldl", 2, - 0x9a, "stl", -2, - 0xa0, "ldt", 2, - 0xa2, "stt", -2, - 0xb0, "ldq", 2, - 0xb2, "stq", -2, - 0xc0, "ldib", 2, - 0xc2, "stib", -2, - 0xc8, "ldis", 2, - 0xca, "stis", -2, - 0, NULL, 0 - }; - static struct tabent mem_tab_buf[MEM_MAX - MEM_MIN + 1]; - - if ( mem_tab == NULL ){ - mem_tab = mem_tab_buf; - for ( i = 0; mem_init[i].opcode != 0; i++ ){ - j = mem_init[i].opcode - MEM_MIN; - mem_tab[j].name = mem_init[i].name; - mem_tab[j].numops = mem_init[i].numops; - } - } - - i = ((word1 >> 24) & 0xff) - MEM_MIN; - mode = (word1 >> 10) & 0xf; - - if ( (mem_tab[i].name != NULL) /* Valid instruction */ - && ((mode == 5) || (mode >=12)) ){ /* With 32-bit displacement */ - len = 8; - } else { - len = 4; - } - - if ( noprint ){ - return len; - } - - if ( (mem_tab[i].name == NULL) || (mode == 6) ){ - invalid( word1 ); - return len; - } - - (*info->fprintf_func)( stream, "%s\t", mem_tab[i].name ); - - reg1 = reg_names[ (word1 >> 19) & 0x1f ]; /* MEMB only */ - reg2 = reg_names[ (word1 >> 14) & 0x1f ]; - reg3 = reg_names[ word1 & 0x1f ]; /* MEMB only */ - offset = word1 & 0xfff; /* MEMA only */ - - switch ( mem_tab[i].numops ){ - - case 2: /* LOAD INSTRUCTION */ - if ( mode & 4 ){ /* MEMB FORMAT */ - ea( memaddr, mode, reg2, reg3, word1, word2 ); - (*info->fprintf_func)( stream, ",%s", reg1 ); - } else { /* MEMA FORMAT */ - (*info->fprintf_func)( stream, "0x%x", (unsigned) offset ); - if (mode & 8) { - (*info->fprintf_func)( stream, "(%s)", reg2 ); - } - (*info->fprintf_func)( stream, ",%s", reg1 ); - } - break; - - case -2: /* STORE INSTRUCTION */ - if ( mode & 4 ){ /* MEMB FORMAT */ - (*info->fprintf_func)( stream, "%s,", reg1 ); - ea( memaddr, mode, reg2, reg3, word1, word2 ); - } else { /* MEMA FORMAT */ - (*info->fprintf_func)( stream, "%s,0x%x", reg1, (unsigned) offset ); - if (mode & 8) { - (*info->fprintf_func)( stream, "(%s)", reg2 ); - } - } - break; - - case 1: /* BX/CALLX INSTRUCTION */ - if ( mode & 4 ){ /* MEMB FORMAT */ - ea( memaddr, mode, reg2, reg3, word1, word2 ); - } else { /* MEMA FORMAT */ - (*info->fprintf_func)( stream, "0x%x", (unsigned) offset ); - if (mode & 8) { - (*info->fprintf_func)( stream, "(%s)", reg2 ); - } - } - break; - } - - return len; -} - -/****************************************/ -/* REG format */ -/****************************************/ -static void -reg( word1 ) - unsigned long word1; -{ - int i, j; - int opcode; - int fp; - int m1, m2, m3; - int s1, s2; - int src, src2, dst; - char *mnemp; - - /* This lookup table is too sparse to make it worth typing in, but not - so large as to make a sparse array necessary. We create the table - at runtime. */ - - /* - * NOTE: In this table, the meaning of 'numops' is: - * 1: single operand, which is NOT a destination. - * -1: single operand, which IS a destination. - * 2: 2 operands, the 2nd of which is NOT a destination. - * -2: 2 operands, the 2nd of which IS a destination. - * 3: 3 operands - * - * If an opcode mnemonic begins with "F", it is a floating-point - * opcode (the "F" is not printed). - */ - - static struct tabent *reg_tab; - static const struct sparse_tabent reg_init[] = { -#define REG_MIN 0x580 - 0x580, "notbit", 3, - 0x581, "and", 3, - 0x582, "andnot", 3, - 0x583, "setbit", 3, - 0x584, "notand", 3, - 0x586, "xor", 3, - 0x587, "or", 3, - 0x588, "nor", 3, - 0x589, "xnor", 3, - 0x58a, "not", -2, - 0x58b, "ornot", 3, - 0x58c, "clrbit", 3, - 0x58d, "notor", 3, - 0x58e, "nand", 3, - 0x58f, "alterbit", 3, - 0x590, "addo", 3, - 0x591, "addi", 3, - 0x592, "subo", 3, - 0x593, "subi", 3, - 0x594, "cmpob", 2, /* xl */ - 0x595, "cmpib", 2, /* xl */ - 0x596, "cmpos", 2, /* xl */ - 0x597, "cmpis", 2, /* xl */ - 0x598, "shro", 3, - 0x59a, "shrdi", 3, - 0x59b, "shri", 3, - 0x59c, "shlo", 3, - 0x59d, "rotate", 3, - 0x59e, "shli", 3, - 0x5a0, "cmpo", 2, - 0x5a1, "cmpi", 2, - 0x5a2, "concmpo", 2, - 0x5a3, "concmpi", 2, - 0x5a4, "cmpinco", 3, - 0x5a5, "cmpinci", 3, - 0x5a6, "cmpdeco", 3, - 0x5a7, "cmpdeci", 3, - 0x5ac, "scanbyte", 2, - 0x5ad, "bswap", -2, /* xl */ - 0x5ae, "chkbit", 2, - 0x5b0, "addc", 3, - 0x5b2, "subc", 3, - 0x5b4, "intdis", 0, /* xl */ - 0x5b5, "inten", 0, /* xl */ - 0x5cc, "mov", -2, - 0x5d8, "eshro", 3, - 0x5dc, "movl", -2, - 0x5ec, "movt", -2, - 0x5fc, "movq", -2, - 0x600, "synmov", 2, - 0x601, "synmovl", 2, - 0x602, "synmovq", 2, - 0x603, "cmpstr", 3, - 0x604, "movqstr", 3, - 0x605, "movstr", 3, - 0x610, "atmod", 3, - 0x612, "atadd", 3, - 0x613, "inspacc", -2, - 0x614, "ldphy", -2, - 0x615, "synld", -2, - 0x617, "fill", 3, - 0x630, "sdma", 3, - 0x631, "udma", 0, - 0x640, "spanbit", -2, - 0x641, "scanbit", -2, - 0x642, "daddc", 3, - 0x643, "dsubc", 3, - 0x644, "dmovt", -2, - 0x645, "modac", 3, - 0x646, "condrec", -2, - 0x650, "modify", 3, - 0x651, "extract", 3, - 0x654, "modtc", 3, - 0x655, "modpc", 3, - 0x656, "receive", -2, - 0x658, "intctl", -2, /* xl */ - 0x659, "sysctl", 3, - 0x65b, "icctl", 3, /* xl */ - 0x65c, "dcctl", 3, /* xl */ - 0x65d, "halt", 0, /* xl */ - 0x660, "calls", 1, - 0x662, "send", 3, - 0x663, "sendserv", 1, - 0x664, "resumprcs", 1, - 0x665, "schedprcs", 1, - 0x666, "saveprcs", 0, - 0x668, "condwait", 1, - 0x669, "wait", 1, - 0x66a, "signal", 1, - 0x66b, "mark", 0, - 0x66c, "fmark", 0, - 0x66d, "flushreg", 0, - 0x66f, "syncf", 0, - 0x670, "emul", 3, - 0x671, "ediv", 3, - 0x673, "ldtime", -1, - 0x674, "Fcvtir", -2, - 0x675, "Fcvtilr", -2, - 0x676, "Fscalerl", 3, - 0x677, "Fscaler", 3, - 0x680, "Fatanr", 3, - 0x681, "Flogepr", 3, - 0x682, "Flogr", 3, - 0x683, "Fremr", 3, - 0x684, "Fcmpor", 2, - 0x685, "Fcmpr", 2, - 0x688, "Fsqrtr", -2, - 0x689, "Fexpr", -2, - 0x68a, "Flogbnr", -2, - 0x68b, "Froundr", -2, - 0x68c, "Fsinr", -2, - 0x68d, "Fcosr", -2, - 0x68e, "Ftanr", -2, - 0x68f, "Fclassr", 1, - 0x690, "Fatanrl", 3, - 0x691, "Flogeprl", 3, - 0x692, "Flogrl", 3, - 0x693, "Fremrl", 3, - 0x694, "Fcmporl", 2, - 0x695, "Fcmprl", 2, - 0x698, "Fsqrtrl", -2, - 0x699, "Fexprl", -2, - 0x69a, "Flogbnrl", -2, - 0x69b, "Froundrl", -2, - 0x69c, "Fsinrl", -2, - 0x69d, "Fcosrl", -2, - 0x69e, "Ftanrl", -2, - 0x69f, "Fclassrl", 1, - 0x6c0, "Fcvtri", -2, - 0x6c1, "Fcvtril", -2, - 0x6c2, "Fcvtzri", -2, - 0x6c3, "Fcvtzril", -2, - 0x6c9, "Fmovr", -2, - 0x6d9, "Fmovrl", -2, - 0x6e1, "Fmovre", -2, - 0x6e2, "Fcpysre", 3, - 0x6e3, "Fcpyrsre", 3, - 0x701, "mulo", 3, - 0x708, "remo", 3, - 0x70b, "divo", 3, - 0x741, "muli", 3, - 0x748, "remi", 3, - 0x749, "modi", 3, - 0x74b, "divi", 3, - 0x780, "addono", 3, /* xl */ - 0x781, "addino", 3, /* xl */ - 0x782, "subono", 3, /* xl */ - 0x783, "subino", 3, /* xl */ - 0x784, "selno", 3, /* xl */ - 0x78b, "Fdivr", 3, - 0x78c, "Fmulr", 3, - 0x78d, "Fsubr", 3, - 0x78f, "Faddr", 3, - 0x790, "addog", 3, /* xl */ - 0x791, "addig", 3, /* xl */ - 0x792, "subog", 3, /* xl */ - 0x793, "subig", 3, /* xl */ - 0x794, "selg", 3, /* xl */ - 0x79b, "Fdivrl", 3, - 0x79c, "Fmulrl", 3, - 0x79d, "Fsubrl", 3, - 0x79f, "Faddrl", 3, -#define REG_MAX 0x79f - 0x7a0, "addoe", 3, /* xl */ - 0x7a1, "addie", 3, /* xl */ - 0x7a2, "suboe", 3, /* xl */ - 0x7a3, "subie", 3, /* xl */ - 0x7a4, "sele", 3, /* xl */ - 0x7b0, "addoge", 3, /* xl */ - 0x7b1, "addige", 3, /* xl */ - 0x7b2, "suboge", 3, /* xl */ - 0x7b3, "subige", 3, /* xl */ - 0x7b4, "selge", 3, /* xl */ - 0x7c0, "addol", 3, /* xl */ - 0x7c1, "addil", 3, /* xl */ - 0x7c2, "subol", 3, /* xl */ - 0x7c3, "subil", 3, /* xl */ - 0x7c4, "sell", 3, /* xl */ - 0x7d0, "addone", 3, /* xl */ - 0x7d1, "addine", 3, /* xl */ - 0x7d2, "subone", 3, /* xl */ - 0x7d3, "subine", 3, /* xl */ - 0x7d4, "selne", 3, /* xl */ - 0x7e0, "addole", 3, /* xl */ - 0x7e1, "addile", 3, /* xl */ - 0x7e2, "subole", 3, /* xl */ - 0x7e3, "subile", 3, /* xl */ - 0x7e4, "selle", 3, /* xl */ - 0x7f0, "addoo", 3, /* xl */ - 0x7f1, "addio", 3, /* xl */ - 0x7f2, "suboo", 3, /* xl */ - 0x7f3, "subio", 3, /* xl */ - 0x7f4, "selo", 3, /* xl */ -#undef REG_MAX /* xl */ -#define REG_MAX 0x7f4 /* xl */ - 0, NULL, 0 - }; - static struct tabent reg_tab_buf[REG_MAX - REG_MIN + 1]; - - if ( reg_tab == NULL ){ - reg_tab = reg_tab_buf; - for ( i = 0; reg_init[i].opcode != 0; i++ ){ - j = reg_init[i].opcode - REG_MIN; - reg_tab[j].name = reg_init[i].name; - reg_tab[j].numops = reg_init[i].numops; - } - } - - opcode = ((word1 >> 20) & 0xff0) | ((word1 >> 7) & 0xf); - i = opcode - REG_MIN; - - if ( (opcode<REG_MIN) || (opcode>REG_MAX) || (reg_tab[i].name==NULL) ){ - invalid( word1 ); - return; - } - - mnemp = reg_tab[i].name; - if ( *mnemp == 'F' ){ - fp = 1; - mnemp++; - } else { - fp = 0; - } - - (*info->fprintf_func)( stream, mnemp ); - - s1 = (word1 >> 5) & 1; - s2 = (word1 >> 6) & 1; - m1 = (word1 >> 11) & 1; - m2 = (word1 >> 12) & 1; - m3 = (word1 >> 13) & 1; - src = word1 & 0x1f; - src2 = (word1 >> 14) & 0x1f; - dst = (word1 >> 19) & 0x1f; - - if ( reg_tab[i].numops != 0 ){ - (*info->fprintf_func)( stream, "\t" ); - - switch ( reg_tab[i].numops ){ - case 1: - regop( m1, s1, src, fp ); - break; - case -1: - dstop( m3, dst, fp ); - break; - case 2: - regop( m1, s1, src, fp ); - (*info->fprintf_func)( stream, "," ); - regop( m2, s2, src2, fp ); - break; - case -2: - regop( m1, s1, src, fp ); - (*info->fprintf_func)( stream, "," ); - dstop( m3, dst, fp ); - break; - case 3: - regop( m1, s1, src, fp ); - (*info->fprintf_func)( stream, "," ); - regop( m2, s2, src2, fp ); - (*info->fprintf_func)( stream, "," ); - dstop( m3, dst, fp ); - break; - } - } -} - - -/* - * Print out effective address for memb instructions. - */ -static void -ea( memaddr, mode, reg2, reg3, word1, word2 ) - unsigned long memaddr; - int mode; - char *reg2, *reg3; - int word1; - unsigned int word2; -{ - int scale; - static const int scale_tab[] = { 1, 2, 4, 8, 16 }; - - scale = (word1 >> 7) & 0x07; - if ( (scale > 4) || ((word1 >> 5) & 0x03 != 0) ){ - invalid( word1 ); - return; - } - scale = scale_tab[scale]; - - switch (mode) { - case 4: /* (reg) */ - (*info->fprintf_func)( stream, "(%s)", reg2 ); - break; - case 5: /* displ+8(ip) */ - print_addr( word2+8+memaddr ); - break; - case 7: /* (reg)[index*scale] */ - if (scale == 1) { - (*info->fprintf_func)( stream, "(%s)[%s]", reg2, reg3 ); - } else { - (*info->fprintf_func)( stream, "(%s)[%s*%d]",reg2,reg3,scale); - } - break; - case 12: /* displacement */ - print_addr( word2 ); - break; - case 13: /* displ(reg) */ - print_addr( word2 ); - (*info->fprintf_func)( stream, "(%s)", reg2 ); - break; - case 14: /* displ[index*scale] */ - print_addr( word2 ); - if (scale == 1) { - (*info->fprintf_func)( stream, "[%s]", reg3 ); - } else { - (*info->fprintf_func)( stream, "[%s*%d]", reg3, scale ); - } - break; - case 15: /* displ(reg)[index*scale] */ - print_addr( word2 ); - if (scale == 1) { - (*info->fprintf_func)( stream, "(%s)[%s]", reg2, reg3 ); - } else { - (*info->fprintf_func)( stream, "(%s)[%s*%d]",reg2,reg3,scale ); - } - break; - default: - invalid( word1 ); - return; - } -} - - -/************************************************/ -/* Register Instruction Operand */ -/************************************************/ -static void -regop( mode, spec, reg, fp ) - int mode, spec, reg, fp; -{ - if ( fp ){ /* FLOATING POINT INSTRUCTION */ - if ( mode == 1 ){ /* FP operand */ - switch ( reg ){ - case 0: (*info->fprintf_func)( stream, "fp0" ); - break; - case 1: (*info->fprintf_func)( stream, "fp1" ); - break; - case 2: (*info->fprintf_func)( stream, "fp2" ); - break; - case 3: (*info->fprintf_func)( stream, "fp3" ); - break; - case 16: (*info->fprintf_func)( stream, "0f0.0" ); - break; - case 22: (*info->fprintf_func)( stream, "0f1.0" ); - break; - default: (*info->fprintf_func)( stream, "?" ); - break; - } - } else { /* Non-FP register */ - (*info->fprintf_func)( stream, reg_names[reg] ); - } - } else { /* NOT FLOATING POINT */ - if ( mode == 1 ){ /* Literal */ - (*info->fprintf_func)( stream, "%d", reg ); - } else { /* Register */ - if ( spec == 0 ){ - (*info->fprintf_func)( stream, reg_names[reg] ); - } else { - (*info->fprintf_func)( stream, "sf%d", reg ); - } - } - } -} - -/************************************************/ -/* Register Instruction Destination Operand */ -/************************************************/ -static void -dstop( mode, reg, fp ) - int mode, reg, fp; -{ - /* 'dst' operand can't be a literal. On non-FP instructions, register - * mode is assumed and "m3" acts as if were "s3"; on FP-instructions, - * sf registers are not allowed so m3 acts normally. - */ - if ( fp ){ - regop( mode, 0, reg, fp ); - } else { - regop( 0, mode, reg, fp ); - } -} - - -static void -invalid( word1 ) - int word1; -{ - (*info->fprintf_func)( stream, ".word\t0x%08x", (unsigned) word1 ); -} - -static void -print_addr(a) -int a; -{ - (*info->print_address_func) ((bfd_vma) a, info); -} - -static void -put_abs( word1, word2 ) - unsigned long word1, word2; -{ -#ifdef IN_GDB - return; -#else - int len; - - switch ( (word1 >> 28) & 0xf ){ - case 0x8: - case 0x9: - case 0xa: - case 0xb: - case 0xc: - /* MEM format instruction */ - len = mem( 0, word1, word2, 1 ); - break; - default: - len = 4; - break; - } - - if ( len == 8 ){ - (*info->fprintf_func)( stream, "%08x %08x\t", word1, word2 ); - } else { - (*info->fprintf_func)( stream, "%08x \t", word1 ); - } -; - -#endif -} diff --git a/opcodes/m10200-dis.c b/opcodes/m10200-dis.c deleted file mode 100644 index 9572f9ea85e..00000000000 --- a/opcodes/m10200-dis.c +++ /dev/null @@ -1,340 +0,0 @@ -/* Disassemble MN10200 instructions. - Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - - -#include <stdio.h> - -#include "ansidecl.h" -#include "opcode/mn10200.h" -#include "dis-asm.h" -#include "opintl.h" - -static void disassemble PARAMS ((bfd_vma, struct disassemble_info *, - unsigned long insn, unsigned long, - unsigned int)); - -int -print_insn_mn10200 (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - int status; - bfd_byte buffer[4]; - unsigned long insn; - unsigned long extension = 0; - unsigned int consume; - - /* First figure out how big the opcode is. */ - status = (*info->read_memory_func) (memaddr, buffer, 1, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn = *(unsigned char *) buffer; - - /* These are one byte insns. */ - if ((insn & 0xf0) == 0x00 - || (insn & 0xf0) == 0x10 - || (insn & 0xf0) == 0x20 - || (insn & 0xf0) == 0x30 - || ((insn & 0xf0) == 0x80 - && (insn & 0x0c) >> 2 != (insn & 0x03)) - || (insn & 0xf0) == 0x90 - || (insn & 0xf0) == 0xa0 - || (insn & 0xf0) == 0xb0 - || (insn & 0xff) == 0xeb - || (insn & 0xff) == 0xf6 - || (insn & 0xff) == 0xfe - || (insn & 0xff) == 0xff) - { - extension = 0; - consume = 1; - } - - /* These are two byte insns. */ - else if ((insn & 0xf0) == 0x40 - || (insn & 0xf0) == 0x50 - || (insn & 0xf0) == 0x60 - || (insn & 0xf0) == 0x70 - || (insn & 0xf0) == 0x80 - || (insn & 0xfc) == 0xd0 - || (insn & 0xfc) == 0xd4 - || (insn & 0xfc) == 0xd8 - || (insn & 0xfc) == 0xe0 - || (insn & 0xfc) == 0xe4 - || (insn & 0xff) == 0xe8 - || (insn & 0xff) == 0xe9 - || (insn & 0xff) == 0xea - || (insn & 0xff) == 0xf0 - || (insn & 0xff) == 0xf1 - || (insn & 0xff) == 0xf2 - || (insn & 0xff) == 0xf3) - { - status = (*info->read_memory_func) (memaddr, buffer, 2, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn = bfd_getb16 (buffer); - consume = 2; - } - - /* These are three byte insns with a 16bit operand in little - endian form. */ - else if ((insn & 0xf0) == 0xc0 - || (insn & 0xfc) == 0xdc - || (insn & 0xfc) == 0xec - || (insn & 0xff) == 0xf8 - || (insn & 0xff) == 0xf9 - || (insn & 0xff) == 0xfa - || (insn & 0xff) == 0xfb - || (insn & 0xff) == 0xfc - || (insn & 0xff) == 0xfd) - { - status = (*info->read_memory_func) (memaddr + 1, buffer, 2, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn <<= 16; - insn |= bfd_getl16 (buffer); - extension = 0; - consume = 3; - } - /* These are three byte insns too, but we don't have to mess with - endianness stuff. */ - else if ((insn & 0xff) == 0xf5) - { - status = (*info->read_memory_func) (memaddr + 1, buffer, 2, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn <<= 16; - insn |= bfd_getb16 (buffer); - extension = 0; - consume = 3; - } - - /* These are four byte insns. */ - else if ((insn & 0xff) == 0xf7) - { - status = (*info->read_memory_func) (memaddr, buffer, 2, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn = bfd_getb16 (buffer); - insn <<= 16; - status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn |= bfd_getl16 (buffer); - extension = 0; - consume = 4; - } - - /* These are five byte insns. */ - else if ((insn & 0xff) == 0xf4) - { - status = (*info->read_memory_func) (memaddr, buffer, 2, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn = bfd_getb16 (buffer); - insn <<= 16; - - status = (*info->read_memory_func) (memaddr + 4, buffer, 1, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn |= *(unsigned char *)buffer << 8; - - status = (*info->read_memory_func) (memaddr + 3, buffer, 1, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn |= *(unsigned char *)buffer; - - status = (*info->read_memory_func) (memaddr + 2, buffer, 1, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - extension = *(unsigned char *)buffer; - consume = 5; - } - else - { - (*info->fprintf_func) (info->stream, _("unknown\t0x%02x"), insn); - return 1; - } - - disassemble (memaddr, info, insn, extension, consume); - - return consume; -} - -static void -disassemble (memaddr, info, insn, extension, size) - bfd_vma memaddr; - struct disassemble_info *info; - unsigned long insn; - unsigned long extension; - unsigned int size; -{ - struct mn10200_opcode *op = (struct mn10200_opcode *)mn10200_opcodes; - const struct mn10200_operand *operand; - int match = 0; - - /* Find the opcode. */ - while (op->name) - { - int mysize, extra_shift; - - if (op->format == FMT_1) - mysize = 1; - else if (op->format == FMT_2 - || op->format == FMT_4) - mysize = 2; - else if (op->format == FMT_3 - || op->format == FMT_5) - mysize = 3; - else if (op->format == FMT_6) - mysize = 4; - else if (op->format == FMT_7) - mysize = 5; - else - abort (); - - if (op->format == FMT_2 || op->format == FMT_5) - extra_shift = 8; - else if (op->format == FMT_3 - || op->format == FMT_6 - || op->format == FMT_7) - extra_shift = 16; - else - extra_shift = 0; - - if ((op->mask & insn) == op->opcode - && size == (unsigned int) mysize) - { - const unsigned char *opindex_ptr; - unsigned int nocomma; - int paren = 0; - - match = 1; - (*info->fprintf_func) (info->stream, "%s\t", op->name); - - /* Now print the operands. */ - for (opindex_ptr = op->operands, nocomma = 1; - *opindex_ptr != 0; - opindex_ptr++) - { - unsigned long value; - - operand = &mn10200_operands[*opindex_ptr]; - - if ((operand->flags & MN10200_OPERAND_EXTENDED) != 0) - { - value = (insn & 0xffff) << 8; - value |= extension; - } - else - { - value = ((insn >> (operand->shift)) - & ((1 << operand->bits) - 1)); - } - - if ((operand->flags & MN10200_OPERAND_SIGNED) != 0) - value = ((long)(value << (32 - operand->bits)) - >> (32 - operand->bits)); - - if (!nocomma - && (!paren - || ((operand->flags & MN10200_OPERAND_PAREN) == 0))) - (*info->fprintf_func) (info->stream, ","); - - nocomma = 0; - - if ((operand->flags & MN10200_OPERAND_DREG) != 0) - { - value = ((insn >> (operand->shift + extra_shift)) - & ((1 << operand->bits) - 1)); - (*info->fprintf_func) (info->stream, "d%d", value); - } - - else if ((operand->flags & MN10200_OPERAND_AREG) != 0) - { - value = ((insn >> (operand->shift + extra_shift)) - & ((1 << operand->bits) - 1)); - (*info->fprintf_func) (info->stream, "a%d", value); - } - - else if ((operand->flags & MN10200_OPERAND_PSW) != 0) - (*info->fprintf_func) (info->stream, "psw"); - - else if ((operand->flags & MN10200_OPERAND_MDR) != 0) - (*info->fprintf_func) (info->stream, "mdr"); - - else if ((operand->flags & MN10200_OPERAND_PAREN) != 0) - { - if (paren) - (*info->fprintf_func) (info->stream, ")"); - else - { - (*info->fprintf_func) (info->stream, "("); - nocomma = 1; - } - paren = !paren; - } - - else if ((operand->flags & MN10200_OPERAND_PCREL) != 0) - (*info->print_address_func) ((value + memaddr + mysize) & 0xffffff, info); - - else if ((operand->flags & MN10200_OPERAND_MEMADDR) != 0) - (*info->print_address_func) (value, info); - - else - (*info->fprintf_func) (info->stream, "%d", value); - } - /* All done. */ - break; - } - op++; - } - - if (!match) - { - (*info->fprintf_func) (info->stream, _("unknown\t0x%04x"), insn); - } -} diff --git a/opcodes/m10200-opc.c b/opcodes/m10200-opc.c deleted file mode 100644 index 2f70b9081ae..00000000000 --- a/opcodes/m10200-opc.c +++ /dev/null @@ -1,360 +0,0 @@ -/* Assemble Matsushita MN10200 instructions. - Copyright (C) 1996, 1997 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "ansidecl.h" -#include "opcode/mn10200.h" - - -const struct mn10200_operand mn10200_operands[] = { -#define UNUSED 0 - {0, 0, 0}, - -/* dn register in the first register operand position. */ -#define DN0 (UNUSED+1) - {2, 0, MN10200_OPERAND_DREG}, - -/* dn register in the second register operand position. */ -#define DN1 (DN0+1) - {2, 2, MN10200_OPERAND_DREG}, - -/* dm register in the first register operand position. */ -#define DM0 (DN1+1) - {2, 0, MN10200_OPERAND_DREG}, - -/* dm register in the second register operand position. */ -#define DM1 (DM0+1) - {2, 2, MN10200_OPERAND_DREG}, - -/* an register in the first register operand position. */ -#define AN0 (DM1+1) - {2, 0, MN10200_OPERAND_AREG}, - -/* an register in the second register operand position. */ -#define AN1 (AN0+1) - {2, 2, MN10200_OPERAND_AREG}, - -/* am register in the first register operand position. */ -#define AM0 (AN1+1) - {2, 0, MN10200_OPERAND_AREG}, - -/* am register in the second register operand position. */ -#define AM1 (AM0+1) - {2, 2, MN10200_OPERAND_AREG}, - -/* 8 bit unsigned immediate which may promote to a 16bit - unsigned immediate. */ -#define IMM8 (AM1+1) - {8, 0, MN10200_OPERAND_PROMOTE}, - -/* 16 bit unsigned immediate which may promote to a 32bit - unsigned immediate. */ -#define IMM16 (IMM8+1) - {16, 0, MN10200_OPERAND_PROMOTE}, - -/* 16 bit pc-relative immediate which may promote to a 16bit - pc-relative immediate. */ -#define IMM16_PCREL (IMM16+1) - {16, 0, MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX | MN10200_OPERAND_SIGNED}, - -/* 16bit unsigned dispacement in a memory operation which - may promote to a 32bit displacement. */ -#define IMM16_MEM (IMM16_PCREL+1) - {16, 0, MN10200_OPERAND_PROMOTE | MN10200_OPERAND_MEMADDR}, - -/* 24 immediate, low 16 bits in the main instruction - word, 8 in the extension word. */ - -#define IMM24 (IMM16_MEM+1) - {24, 0, MN10200_OPERAND_EXTENDED}, - -/* 32bit pc-relative offset. */ -#define IMM24_PCREL (IMM24+1) - {24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_PCREL | MN10200_OPERAND_SIGNED}, - -/* 32bit memory offset. */ -#define IMM24_MEM (IMM24_PCREL+1) - {24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_MEMADDR}, - -/* Processor status word. */ -#define PSW (IMM24_MEM+1) - {0, 0, MN10200_OPERAND_PSW}, - -/* MDR register. */ -#define MDR (PSW+1) - {0, 0, MN10200_OPERAND_MDR}, - -/* Index register. */ -#define DI (MDR+1) - {2, 4, MN10200_OPERAND_DREG}, - -/* 8 bit signed displacement, may promote to 16bit signed dispacement. */ -#define SD8 (DI+1) - {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE}, - -/* 16 bit signed displacement, may promote to 32bit dispacement. */ -#define SD16 (SD8+1) - {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE}, - -/* 8 bit pc-relative displacement. */ -#define SD8N_PCREL (SD16+1) - {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX}, - -/* 8 bit signed immediate which may promote to 16bit signed immediate. */ -#define SIMM8 (SD8N_PCREL+1) - {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE}, - -/* 16 bit signed immediate which may promote to 32bit immediate. */ -#define SIMM16 (SIMM8+1) - {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE}, - -/* 16 bit signed immediate which may not promote. */ -#define SIMM16N (SIMM16+1) - {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_NOCHECK}, - -/* Either an open paren or close paren. */ -#define PAREN (SIMM16N+1) - {0, 0, MN10200_OPERAND_PAREN}, - -/* dn register that appears in the first and second register positions. */ -#define DN01 (PAREN+1) - {2, 0, MN10200_OPERAND_DREG | MN10200_OPERAND_REPEATED}, - -/* an register that appears in the first and second register positions. */ -#define AN01 (DN01+1) - {2, 0, MN10200_OPERAND_AREG | MN10200_OPERAND_REPEATED}, -} ; - -#define MEM(ADDR) PAREN, ADDR, PAREN -#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN - -/* The opcode table. - - The format of the opcode table is: - - NAME OPCODE MASK { OPERANDS } - - NAME is the name of the instruction. - OPCODE is the instruction opcode. - MASK is the opcode mask; this is used to tell the disassembler - which bits in the actual opcode must match OPCODE. - OPERANDS is the list of operands. - - The disassembler reads the table in order and prints the first - instruction which matches, so this table is sorted to put more - specific instructions before more general instructions. It is also - sorted by major opcode. */ - -const struct mn10200_opcode mn10200_opcodes[] = { -{ "mov", 0x8000, 0xf000, FMT_2, {SIMM8, DN01}}, -{ "mov", 0x80, 0xf0, FMT_1, {DN1, DM0}}, -{ "mov", 0xf230, 0xfff0, FMT_4, {DM1, AN0}}, -{ "mov", 0xf2f0, 0xfff0, FMT_4, {AN1, DM0}}, -{ "mov", 0xf270, 0xfff0, FMT_4, {AN1, AM0}}, -{ "mov", 0xf3f0, 0xfffc, FMT_4, {PSW, DN0}}, -{ "mov", 0xf3d0, 0xfff3, FMT_4, {DN1, PSW}}, -{ "mov", 0xf3e0, 0xfffc, FMT_4, {MDR, DN0}}, -{ "mov", 0xf3c0, 0xfff3, FMT_4, {DN1, MDR}}, -{ "mov", 0x20, 0xf0, FMT_1, {MEM(AN1), DM0}}, -{ "mov", 0x6000, 0xf000, FMT_2, {MEM2(SD8, AN1), DM0}}, -{ "mov", 0xf7c00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, -{ "mov", 0xf4800000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, -{ "mov", 0xf140, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}}, -{ "mov", 0xc80000, 0xfc0000, FMT_3, {MEM(IMM16_MEM), DN0}}, -{ "mov", 0xf4c00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}}, -{ "mov", 0x7000, 0xf000, FMT_2, {MEM2(SD8,AN1), AM0}}, -{ "mov", 0x7000, 0xf000, FMT_2, {MEM(AN1), AM0}}, -{ "mov", 0xf7b00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), AM0}}, -{ "mov", 0xf4f00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), AM0}}, -{ "mov", 0xf100, 0xffc0, FMT_4, {MEM2(DI, AN1), AM0}}, -{ "mov", 0xf7300000, 0xfffc0000, FMT_6, {MEM(IMM16_MEM), AN0}}, -{ "mov", 0xf4d00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), AN0}}, -{ "mov", 0x00, 0xf0, FMT_1, {DM0, MEM(AN1)}}, -{ "mov", 0x4000, 0xf000, FMT_2, {DM0, MEM2(SD8, AN1)}}, -{ "mov", 0xf7800000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}}, -{ "mov", 0xf4000000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}}, -{ "mov", 0xf1c0, 0xffc0, FMT_4, {DM0, MEM2(DI, AN1)}}, -{ "mov", 0xc00000, 0xfc0000, FMT_3, {DN0, MEM(IMM16_MEM)}}, -{ "mov", 0xf4400000, 0xfffc0000, FMT_7, {DN0, MEM(IMM24_MEM)}}, -{ "mov", 0x5000, 0xf000, FMT_2, {AM0, MEM2(SD8, AN1)}}, -{ "mov", 0x5000, 0xf000, FMT_2, {AM0, MEM(AN1)}}, -{ "mov", 0xf7a00000, 0xfff00000, FMT_6, {AM0, MEM2(SD16, AN1)}}, -{ "mov", 0xf4100000, 0xfff00000, FMT_7, {AM0, MEM2(IMM24,AN1)}}, -{ "mov", 0xf180, 0xffc0, FMT_4, {AM0, MEM2(DI, AN1)}}, -{ "mov", 0xf7200000, 0xfffc0000, FMT_6, {AN0, MEM(IMM16_MEM)}}, -{ "mov", 0xf4500000, 0xfffc0000, FMT_7, {AN0, MEM(IMM24_MEM)}}, -{ "mov", 0xf80000, 0xfc0000, FMT_3, {SIMM16, DN0}}, -{ "mov", 0xf4700000, 0xfffc0000, FMT_7, {IMM24, DN0}}, -{ "mov", 0xdc0000, 0xfc0000, FMT_3, {IMM16, AN0}}, -{ "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}}, - -{ "movx", 0xf57000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}}, -{ "movx", 0xf7700000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, -{ "movx", 0xf4b00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, -{ "movx", 0xf55000, 0xfff000, FMT_5, {DM0, MEM2(SD8, AN1)}}, -{ "movx", 0xf7600000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}}, -{ "movx", 0xf4300000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}}, - -{ "movb", 0xf52000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}}, -{ "movb", 0xf7d00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, -{ "movb", 0xf4a00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, -{ "movb", 0xf040, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}}, -{ "movb", 0xf4c40000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}}, -{ "movb", 0x10, 0xf0, FMT_1, {DM0, MEM(AN1)}}, -{ "movb", 0xf51000, 0xfff000, FMT_5, {DM0, MEM2(SD8, AN1)}}, -{ "movb", 0xf7900000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}}, -{ "movb", 0xf4200000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}}, -{ "movb", 0xf0c0, 0xffc0, FMT_4, {DM0, MEM2(DI, AN1)}}, -{ "movb", 0xc40000, 0xfc0000, FMT_3, {DN0, MEM(IMM16_MEM)}}, -{ "movb", 0xf4440000, 0xfffc0000, FMT_7, {DN0, MEM(IMM24_MEM)}}, - -{ "movbu", 0x30, 0xf0, FMT_1, {MEM(AN1), DM0}}, -{ "movbu", 0xf53000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}}, -{ "movbu", 0xf7500000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, -{ "movbu", 0xf4900000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, -{ "movbu", 0xf080, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}}, -{ "movbu", 0xcc0000, 0xfc0000, FMT_3, {MEM(IMM16_MEM), DN0}}, -{ "movbu", 0xf4c80000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}}, - -{ "ext", 0xf3c1, 0xfff3, FMT_4, {DN1}}, -{ "extx", 0xb0, 0xfc, FMT_1, {DN0}}, -{ "extxu", 0xb4, 0xfc, FMT_1, {DN0}}, -{ "extxb", 0xb8, 0xfc, FMT_1, {DN0}}, -{ "extxbu", 0xbc, 0xfc, FMT_1, {DN0}}, - -{ "add", 0x90, 0xf0, FMT_1, {DN1, DM0}}, -{ "add", 0xf200, 0xfff0, FMT_4, {DM1, AN0}}, -{ "add", 0xf2c0, 0xfff0, FMT_4, {AN1, DM0}}, -{ "add", 0xf240, 0xfff0, FMT_4, {AN1, AM0}}, -{ "add", 0xd400, 0xfc00, FMT_2, {SIMM8, DN0}}, -{ "add", 0xf7180000, 0xfffc0000, FMT_6, {SIMM16, DN0}}, -{ "add", 0xf4600000, 0xfffc0000, FMT_7, {IMM24, DN0}}, -{ "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}}, -{ "add", 0xf7080000, 0xfffc0000, FMT_6, {SIMM16, AN0}}, -{ "add", 0xf4640000, 0xfffc0000, FMT_7, {IMM24, AN0}}, -{ "addc", 0xf280, 0xfff0, FMT_4, {DN1, DM0}}, -{ "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}}, - -{ "sub", 0xa0, 0xf0, FMT_1, {DN1, DM0}}, -{ "sub", 0xf210, 0xfff0, FMT_4, {DN1, AN0}}, -{ "sub", 0xf2d0, 0xfff0, FMT_4, {AN1, DM0}}, -{ "sub", 0xf250, 0xfff0, FMT_4, {AN1, AM0}}, -{ "sub", 0xf71c0000, 0xfffc0000, FMT_6, {IMM16, DN0}}, -{ "sub", 0xf4680000, 0xfffc0000, FMT_7, {IMM24, DN0}}, -{ "sub", 0xf70c0000, 0xfffc0000, FMT_6, {IMM16, AN0}}, -{ "sub", 0xf46c0000, 0xfffc0000, FMT_7, {IMM24, AN0}}, -{ "subc", 0xf290, 0xfff0, FMT_4, {DN1, DM0}}, - -{ "mul", 0xf340, 0xfff0, FMT_4, {DN1, DM0}}, -{ "mulu", 0xf350, 0xfff0, FMT_4, {DN1, DM0}}, - -{ "divu", 0xf360, 0xfff0, FMT_4, {DN1, DM0}}, - -{ "cmp", 0xf390, 0xfff0, FMT_4, {DN1, DM0}}, -{ "cmp", 0xf220, 0xfff0, FMT_4, {DM1, AN0}}, -{ "cmp", 0xf2e0, 0xfff0, FMT_4, {AN1, DM0}}, -{ "cmp", 0xf260, 0xfff0, FMT_4, {AN1, AM0}}, -{ "cmp", 0xd800, 0xfc00, FMT_2, {SIMM8, DN0}}, -{ "cmp", 0xf7480000, 0xfffc0000, FMT_6, {SIMM16, DN0}}, -{ "cmp", 0xf4780000, 0xfffc0000, FMT_7, {IMM24, DN0}}, -{ "cmp", 0xec0000, 0xfc0000, FMT_3, {IMM16, AN0}}, -{ "cmp", 0xf47c0000, 0xfffc0000, FMT_7, {IMM24, AN0}}, - -{ "and", 0xf300, 0xfff0, FMT_4, {DN1, DM0}}, -{ "and", 0xf50000, 0xfffc00, FMT_5, {IMM8, DN0}}, -{ "and", 0xf7000000, 0xfffc0000, FMT_6, {SIMM16N, DN0}}, -{ "and", 0xf7100000, 0xffff0000, FMT_6, {SIMM16N, PSW}}, -{ "or", 0xf310, 0xfff0, FMT_4, {DN1, DM0}}, -{ "or", 0xf50800, 0xfffc00, FMT_5, {IMM8, DN0}}, -{ "or", 0xf7400000, 0xfffc0000, FMT_6, {SIMM16N, DN0}}, -{ "or", 0xf7140000, 0xffff0000, FMT_6, {SIMM16N, PSW}}, -{ "xor", 0xf320, 0xfff0, FMT_4, {DN1, DM0}}, -{ "xor", 0xf74c0000, 0xfffc0000, FMT_6, {SIMM16N, DN0}}, -{ "not", 0xf3e4, 0xfffc, FMT_4, {DN0}}, - -{ "asr", 0xf338, 0xfffc, FMT_4, {DN0}}, -{ "lsr", 0xf33c, 0xfffc, FMT_4, {DN0}}, -{ "ror", 0xf334, 0xfffc, FMT_4, {DN0}}, -{ "rol", 0xf330, 0xfffc, FMT_4, {DN0}}, - -{ "btst", 0xf50400, 0xfffc00, FMT_5, {IMM8, DN0}}, -{ "btst", 0xf7040000, 0xfffc0000, FMT_6, {SIMM16N, DN0}}, -{ "bset", 0xf020, 0xfff0, FMT_4, {DM0, MEM(AN1)}}, -{ "bclr", 0xf030, 0xfff0, FMT_4, {DM0, MEM(AN1)}}, - -{ "beq", 0xe800, 0xff00, FMT_2, {SD8N_PCREL}}, -{ "bne", 0xe900, 0xff00, FMT_2, {SD8N_PCREL}}, -{ "blt", 0xe000, 0xff00, FMT_2, {SD8N_PCREL}}, -{ "ble", 0xe300, 0xff00, FMT_2, {SD8N_PCREL}}, -{ "bge", 0xe200, 0xff00, FMT_2, {SD8N_PCREL}}, -{ "bgt", 0xe100, 0xff00, FMT_2, {SD8N_PCREL}}, -{ "bcs", 0xe400, 0xff00, FMT_2, {SD8N_PCREL}}, -{ "bls", 0xe700, 0xff00, FMT_2, {SD8N_PCREL}}, -{ "bcc", 0xe600, 0xff00, FMT_2, {SD8N_PCREL}}, -{ "bhi", 0xe500, 0xff00, FMT_2, {SD8N_PCREL}}, -{ "bvc", 0xf5fc00, 0xffff00, FMT_5, {SD8N_PCREL}}, -{ "bvs", 0xf5fd00, 0xffff00, FMT_5, {SD8N_PCREL}}, -{ "bnc", 0xf5fe00, 0xffff00, FMT_5, {SD8N_PCREL}}, -{ "bns", 0xf5ff00, 0xffff00, FMT_5, {SD8N_PCREL}}, -{ "bra", 0xea00, 0xff00, FMT_2, {SD8N_PCREL}}, - -{ "beqx", 0xf5e800, 0xffff00, FMT_5, {SD8N_PCREL}}, -{ "bnex", 0xf5e900, 0xffff00, FMT_5, {SD8N_PCREL}}, -{ "bltx", 0xf5e000, 0xffff00, FMT_5, {SD8N_PCREL}}, -{ "blex", 0xf5e300, 0xffff00, FMT_5, {SD8N_PCREL}}, -{ "bgex", 0xf5e200, 0xffff00, FMT_5, {SD8N_PCREL}}, -{ "bgtx", 0xf5e100, 0xffff00, FMT_5, {SD8N_PCREL}}, -{ "bcsx", 0xf5e400, 0xffff00, FMT_5, {SD8N_PCREL}}, -{ "blsx", 0xf5e700, 0xffff00, FMT_5, {SD8N_PCREL}}, -{ "bccx", 0xf5e600, 0xffff00, FMT_5, {SD8N_PCREL}}, -{ "bhix", 0xf5e500, 0xffff00, FMT_5, {SD8N_PCREL}}, -{ "bvcx", 0xf5ec00, 0xffff00, FMT_5, {SD8N_PCREL}}, -{ "bvsx", 0xf5ed00, 0xffff00, FMT_5, {SD8N_PCREL}}, -{ "bncx", 0xf5ee00, 0xffff00, FMT_5, {SD8N_PCREL}}, -{ "bnsx", 0xf5ef00, 0xffff00, FMT_5, {SD8N_PCREL}}, - -{ "jmp", 0xfc0000, 0xff0000, FMT_3, {IMM16_PCREL}}, -{ "jmp", 0xf4e00000, 0xffff0000, FMT_7, {IMM24_PCREL}}, -{ "jmp", 0xf000, 0xfff3, FMT_4, {PAREN,AN1,PAREN}}, -{ "jsr", 0xfd0000, 0xff0000, FMT_3, {IMM16_PCREL}}, -{ "jsr", 0xf4e10000, 0xffff0000, FMT_7, {IMM24_PCREL}}, -{ "jsr", 0xf001, 0xfff3, FMT_4, {PAREN,AN1,PAREN}}, - -{ "nop", 0xf6, 0xff, FMT_1, {UNUSED}}, - -{ "rts", 0xfe, 0xff, FMT_1, {UNUSED}}, -{ "rti", 0xeb, 0xff, FMT_1, {UNUSED}}, - -/* Extension. We need some instruction to trigger "emulated syscalls" - for our simulator. */ -{ "syscall", 0xf010, 0xffff, FMT_4, {UNUSED}}, - -/* Extension. When talking to the simulator, gdb requires some instruction - that will trigger a "breakpoint" (really just an instruction that isn't - otherwise used by the tools. This instruction must be the same size - as the smallest instruction on the target machine. In the case of the - mn10x00 the "break" instruction must be one byte. 0xff is available on - both mn10x00 architectures. */ -{ "break", 0xff, 0xff, FMT_1, {UNUSED}}, - -{ 0, 0, 0, 0, {0}}, - -} ; - -const int mn10200_num_opcodes = - sizeof (mn10200_opcodes) / sizeof (mn10200_opcodes[0]); - - diff --git a/opcodes/m10300-dis.c b/opcodes/m10300-dis.c deleted file mode 100644 index cdba83bd1ca..00000000000 --- a/opcodes/m10300-dis.c +++ /dev/null @@ -1,693 +0,0 @@ -/* Disassemble MN10300 instructions. - Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - - -#include <stdio.h> - -#include "ansidecl.h" -#include "opcode/mn10300.h" -#include "dis-asm.h" -#include "opintl.h" - -static void disassemble PARAMS ((bfd_vma, struct disassemble_info *, - unsigned long insn, unsigned int)); - -int -print_insn_mn10300 (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - int status; - bfd_byte buffer[4]; - unsigned long insn; - unsigned int consume; - - /* First figure out how big the opcode is. */ - status = (*info->read_memory_func) (memaddr, buffer, 1, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn = *(unsigned char *) buffer; - - /* These are one byte insns. */ - if ((insn & 0xf3) == 0x00 - || (insn & 0xf0) == 0x10 - || (insn & 0xfc) == 0x3c - || (insn & 0xf3) == 0x41 - || (insn & 0xf3) == 0x40 - || (insn & 0xfc) == 0x50 - || (insn & 0xfc) == 0x54 - || (insn & 0xf0) == 0x60 - || (insn & 0xf0) == 0x70 - || ((insn & 0xf0) == 0x80 - && (insn & 0x0c) >> 2 != (insn & 0x03)) - || ((insn & 0xf0) == 0x90 - && (insn & 0x0c) >> 2 != (insn & 0x03)) - || ((insn & 0xf0) == 0xa0 - && (insn & 0x0c) >> 2 != (insn & 0x03)) - || ((insn & 0xf0) == 0xb0 - && (insn & 0x0c) >> 2 != (insn & 0x03)) - || (insn & 0xff) == 0xcb - || (insn & 0xfc) == 0xd0 - || (insn & 0xfc) == 0xd4 - || (insn & 0xfc) == 0xd8 - || (insn & 0xf0) == 0xe0 - || (insn & 0xff) == 0xff) - { - consume = 1; - } - - /* These are two byte insns. */ - else if ((insn & 0xf0) == 0x80 - || (insn & 0xf0) == 0x90 - || (insn & 0xf0) == 0xa0 - || (insn & 0xf0) == 0xb0 - || (insn & 0xfc) == 0x20 - || (insn & 0xfc) == 0x28 - || (insn & 0xf3) == 0x43 - || (insn & 0xf3) == 0x42 - || (insn & 0xfc) == 0x58 - || (insn & 0xfc) == 0x5c - || ((insn & 0xf0) == 0xc0 - && (insn & 0xff) != 0xcb - && (insn & 0xff) != 0xcc - && (insn & 0xff) != 0xcd) - || (insn & 0xff) == 0xf0 - || (insn & 0xff) == 0xf1 - || (insn & 0xff) == 0xf2 - || (insn & 0xff) == 0xf3 - || (insn & 0xff) == 0xf4 - || (insn & 0xff) == 0xf5 - || (insn & 0xff) == 0xf6) - { - status = (*info->read_memory_func) (memaddr, buffer, 2, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn = bfd_getb16 (buffer); - consume = 2; - } - - /* These are three byte insns. */ - else if ((insn & 0xff) == 0xf8 - || (insn & 0xff) == 0xcc - || (insn & 0xff) == 0xf9 - || (insn & 0xf3) == 0x01 - || (insn & 0xf3) == 0x02 - || (insn & 0xf3) == 0x03 - || (insn & 0xfc) == 0x24 - || (insn & 0xfc) == 0x2c - || (insn & 0xfc) == 0x30 - || (insn & 0xfc) == 0x34 - || (insn & 0xfc) == 0x38 - || (insn & 0xff) == 0xde - || (insn & 0xff) == 0xdf - /* start-sanitize-am33 */ - || (insn & 0xff) == 0xf9 - /* end-sanitize-am33 */ - || (insn & 0xff) == 0xcc) - { - status = (*info->read_memory_func) (memaddr, buffer, 2, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn = bfd_getb16 (buffer); - insn <<= 8; - status = (*info->read_memory_func) (memaddr + 2, buffer, 1, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn |= *(unsigned char *)buffer; - consume = 3; - } - - /* These are four byte insns. */ - else if ((insn & 0xff) == 0xfa - /* start-sanitize-am33 */ - || (insn & 0xff) == 0xf7 - /* end-sanitize-am33 */ - || (insn & 0xff) == 0xfb) - { - status = (*info->read_memory_func) (memaddr, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn = bfd_getb32 (buffer); - consume = 4; - } - - /* These are five byte insns. */ - else if ((insn & 0xff) == 0xcd - || (insn & 0xff) == 0xdc) - { - status = (*info->read_memory_func) (memaddr, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn = bfd_getb32 (buffer); - consume = 5; - } - - /* These are six byte insns. */ - else if ((insn & 0xff) == 0xfd - || (insn & 0xff) == 0xfc) - { - status = (*info->read_memory_func) (memaddr, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - - insn = bfd_getb32 (buffer); - consume = 6; - } - - /* Else its a seven byte insns (in theory). */ - else - { - status = (*info->read_memory_func) (memaddr, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - - insn = bfd_getb32 (buffer); - consume = 7; - } - - disassemble (memaddr, info, insn, consume); - - return consume; -} - -static void -disassemble (memaddr, info, insn, size) - bfd_vma memaddr; - struct disassemble_info *info; - unsigned long insn; - unsigned int size; -{ - struct mn10300_opcode *op = (struct mn10300_opcode *)mn10300_opcodes; - const struct mn10300_operand *operand; - bfd_byte buffer[4]; - unsigned long extension = 0; - int status, match = 0; - - /* Find the opcode. */ - while (op->name) - { - int mysize, extra_shift; - - if (op->format == FMT_S0) - mysize = 1; - else if (op->format == FMT_S1 - || op->format == FMT_D0) - mysize = 2; - else if (op->format == FMT_S2 - || op->format == FMT_D1) - mysize = 3; - else if (op->format == FMT_S4) - mysize = 5; - else if (op->format == FMT_D2) - mysize = 4; - else if (op->format == FMT_D4) - mysize = 6; - /* start-sanitize-am33 */ - else if (op->format == FMT_D6) - mysize = 3; - else if (op->format == FMT_D7 || op->format == FMT_D10) - mysize = 4; - else if (op->format == FMT_D8) - mysize = 6; - else if (op->format == FMT_D9) - mysize = 7; - /* end-sanitize-am33 */ - else - mysize = 7; - - if ((op->mask & insn) == op->opcode - && size == (unsigned int) mysize - && (op->machine == 0 - || op->machine == info->mach)) - { - const unsigned char *opindex_ptr; - unsigned int nocomma; - int paren = 0; - - if (op->format == FMT_D1 || op->format == FMT_S1) - extra_shift = 8; - else if (op->format == FMT_D2 || op->format == FMT_D4 - || op->format == FMT_S2 || op->format == FMT_S4 - || op->format == FMT_S6 || op->format == FMT_D5) - extra_shift = 16; - /* start-sanitize-am33 */ - else if (op->format == FMT_D7 - || op->format == FMT_D8 - || op->format == FMT_D9) - extra_shift = 8; - /* end-sanitize-am33 */ - else - extra_shift = 0; - - if (size == 1 || size == 2) - { - extension = 0; - } - else if (size == 3 - && (op->format == FMT_D1 - || op->opcode == 0xdf0000 - || op->opcode == 0xde0000)) - { - extension = 0; - } - /* start-sanitize-am33 */ - else if (size == 3 - && op->format == FMT_D6) - { - extension = 0; - } - /* end-sanitize-am33 */ - else if (size == 3) - { - insn &= 0xff0000; - status = (*info->read_memory_func) (memaddr + 1, buffer, 2, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return; - } - - insn |= bfd_getl16 (buffer); - extension = 0; - } - else if (size == 4 - && (op->opcode == 0xfaf80000 - || op->opcode == 0xfaf00000 - || op->opcode == 0xfaf40000)) - { - extension = 0; - } - /* start-sanitize-am33 */ - else if (size == 4 - && (op->format == FMT_D7 - || op->format == FMT_D10)) - { - extension = 0; - } - /* end-sanitize-am33 */ - else if (size == 4) - { - insn &= 0xffff0000; - status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return; - } - - insn |= bfd_getl16 (buffer); - extension = 0; - } - else if (size == 5 && op->opcode == 0xdc000000) - { - unsigned long temp = 0; - status = (*info->read_memory_func) (memaddr + 1, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return; - } - temp |= bfd_getl32 (buffer); - - insn &= 0xff000000; - insn |= (temp & 0xffffff00) >> 8; - extension = temp & 0xff; - } - else if (size == 5) - { - unsigned long temp = 0; - status = (*info->read_memory_func) (memaddr + 1, buffer, 2, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return; - } - temp |= bfd_getl16 (buffer); - - insn &= 0xff0000ff; - insn |= temp << 8; - - status = (*info->read_memory_func) (memaddr + 4, buffer, 1, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return; - } - extension = *(unsigned char *)buffer; - } - /* start-sanitize-am33 */ - else if (size == 6 && op->format == FMT_D8) - { - insn &= 0xffffff00; - status = (*info->read_memory_func) (memaddr + 5, buffer, 1, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return; - } - insn |= *(unsigned char *)buffer; - - status = (*info->read_memory_func) (memaddr + 3, buffer, 2, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return; - } - extension = bfd_getl16 (buffer); - } - /* end-sanitize-am33 */ - else if (size == 6) - { - unsigned long temp = 0; - status = (*info->read_memory_func) (memaddr + 2, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return; - } - temp |= bfd_getl32 (buffer); - - insn &= 0xffff0000; - insn |= (temp >> 16) & 0xffff; - extension = temp & 0xffff; - } - /* start-sanitize-am33 */ - else if (size == 7 && op->format == FMT_D9) - { - insn &= 0xffffff00; - status = (*info->read_memory_func) (memaddr + 3, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return; - } - extension = bfd_getl32 (buffer); - insn |= (extension & 0xff000000) >> 24; - extension &= 0xffffff; - } - /* end-sanitize-am33 */ - else if (size == 7 && op->opcode == 0xdd000000) - { - unsigned long temp = 0; - status = (*info->read_memory_func) (memaddr + 1, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return; - } - temp |= bfd_getl32 (buffer); - - insn &= 0xff000000; - insn |= (temp >> 8) & 0xffffff; - extension = (temp & 0xff) << 16; - - status = (*info->read_memory_func) (memaddr + 5, buffer, 2, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return; - } - extension |= bfd_getb16 (buffer); - } - else if (size == 7) - { - unsigned long temp = 0; - status = (*info->read_memory_func) (memaddr + 2, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return; - } - temp |= bfd_getl32 (buffer); - - insn &= 0xffff0000; - insn |= (temp >> 16) & 0xffff; - extension = (temp & 0xffff) << 8; - - status = (*info->read_memory_func) (memaddr + 6, buffer, 1, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return; - } - extension |= *(unsigned char *)buffer; - } - - match = 1; - (*info->fprintf_func) (info->stream, "%s\t", op->name); - - /* Now print the operands. */ - for (opindex_ptr = op->operands, nocomma = 1; - *opindex_ptr != 0; - opindex_ptr++) - { - unsigned long value; - - operand = &mn10300_operands[*opindex_ptr]; - - if ((operand->flags & MN10300_OPERAND_SPLIT) != 0) - { - unsigned long temp; - value = insn & ((1 << operand->bits) - 1); - value <<= (32 - operand->bits); - temp = extension >> operand->shift; - temp &= ((1 << (32 - operand->bits)) - 1); - value |= temp; - } - /* start-sanitize-am33 */ - else if ((operand->flags & MN10300_OPERAND_24BIT) != 0) - { - unsigned long temp; - value = insn & ((1 << operand->bits) - 1); - value <<= (24 - operand->bits); - temp = extension >> operand->shift; - temp &= ((1 << (24 - operand->bits)) - 1); - value |= temp; - if ((operand->flags & MN10300_OPERAND_SIGNED) != 0) - value = ((value & 0xffffff) ^ (~0x7fffff)) + 0x800000; - } - /* end-sanitize-am33 */ - else if ((operand->flags & MN10300_OPERAND_EXTENDED) != 0) - { - value = ((extension >> (operand->shift)) - & ((1 << operand->bits) - 1)); - } - else - { - value = ((insn >> (operand->shift)) - & ((1 << operand->bits) - 1)); - } - - if ((operand->flags & MN10300_OPERAND_SIGNED) != 0 - /* start-sanitize-am33 */ - /* These are properly extended by the code above. */ - && ((operand->flags & MN10300_OPERAND_24BIT) == 0) - /* end-sanitize-am33 */ - ) - value = ((long)(value << (32 - operand->bits)) - >> (32 - operand->bits)); - - if (!nocomma - && (!paren - || ((operand->flags & MN10300_OPERAND_PAREN) == 0))) - (*info->fprintf_func) (info->stream, ","); - - nocomma = 0; - - if ((operand->flags & MN10300_OPERAND_DREG) != 0) - { - value = ((insn >> (operand->shift + extra_shift)) - & ((1 << operand->bits) - 1)); - (*info->fprintf_func) (info->stream, "d%d", value); - } - - else if ((operand->flags & MN10300_OPERAND_AREG) != 0) - { - value = ((insn >> (operand->shift + extra_shift)) - & ((1 << operand->bits) - 1)); - (*info->fprintf_func) (info->stream, "a%d", value); - } - - else if ((operand->flags & MN10300_OPERAND_SP) != 0) - (*info->fprintf_func) (info->stream, "sp"); - - else if ((operand->flags & MN10300_OPERAND_PSW) != 0) - (*info->fprintf_func) (info->stream, "psw"); - - else if ((operand->flags & MN10300_OPERAND_MDR) != 0) - (*info->fprintf_func) (info->stream, "mdr"); - - /* start-sanitize-am33 */ - else if ((operand->flags & MN10300_OPERAND_RREG) != 0) - { - value = ((insn >> (operand->shift + extra_shift)) - & ((1 << operand->bits) - 1)); - (*info->fprintf_func) (info->stream, "r%d", value); - } - - else if ((operand->flags & MN10300_OPERAND_XRREG) != 0) - { - value = ((insn >> (operand->shift + extra_shift)) - & ((1 << operand->bits) - 1)); - (*info->fprintf_func) (info->stream, "xr%d", value); - } - - else if ((operand->flags & MN10300_OPERAND_USP) != 0) - (*info->fprintf_func) (info->stream, "usp"); - - else if ((operand->flags & MN10300_OPERAND_SSP) != 0) - (*info->fprintf_func) (info->stream, "ssp"); - - else if ((operand->flags & MN10300_OPERAND_MSP) != 0) - (*info->fprintf_func) (info->stream, "msp"); - - else if ((operand->flags & MN10300_OPERAND_PC) != 0) - (*info->fprintf_func) (info->stream, "pc"); - - else if ((operand->flags & MN10300_OPERAND_EPSW) != 0) - (*info->fprintf_func) (info->stream, "epsw"); - - else if ((operand->flags & MN10300_OPERAND_PLUS) != 0) - (*info->fprintf_func) (info->stream, "+"); - /* end-sanitize-am33 */ - - else if ((operand->flags & MN10300_OPERAND_PAREN) != 0) - { - if (paren) - (*info->fprintf_func) (info->stream, ")"); - else - { - (*info->fprintf_func) (info->stream, "("); - nocomma = 1; - } - paren = !paren; - } - - else if ((operand->flags & MN10300_OPERAND_PCREL) != 0) - (*info->print_address_func) ((long) value + memaddr, info); - - else if ((operand->flags & MN10300_OPERAND_MEMADDR) != 0) - (*info->print_address_func) (value, info); - - else if ((operand->flags & MN10300_OPERAND_REG_LIST) != 0) - { - int comma = 0; - - (*info->fprintf_func) (info->stream, "["); - if (value & 0x80) - { - (*info->fprintf_func) (info->stream, "d2"); - comma = 1; - } - - if (value & 0x40) - { - if (comma) - (*info->fprintf_func) (info->stream, ","); - (*info->fprintf_func) (info->stream, "d3"); - comma = 1; - } - - if (value & 0x20) - { - if (comma) - (*info->fprintf_func) (info->stream, ","); - (*info->fprintf_func) (info->stream, "a2"); - comma = 1; - } - - if (value & 0x10) - { - if (comma) - (*info->fprintf_func) (info->stream, ","); - (*info->fprintf_func) (info->stream, "a3"); - comma = 1; - } - - if (value & 0x08) - { - if (comma) - (*info->fprintf_func) (info->stream, ","); - (*info->fprintf_func) (info->stream, "other"); - comma = 1; - } - - /* start-sanitize-am33 */ - if (value & 0x04) - { - if (comma) - (*info->fprintf_func) (info->stream, ","); - (*info->fprintf_func) (info->stream, "exreg0"); - comma = 1; - } - if (value & 0x02) - { - if (comma) - (*info->fprintf_func) (info->stream, ","); - (*info->fprintf_func) (info->stream, "exreg1"); - comma = 1; - } - if (value & 0x01) - { - if (comma) - (*info->fprintf_func) (info->stream, ","); - (*info->fprintf_func) (info->stream, "exother"); - comma = 1; - } - /* end-sanitize-am33 */ - (*info->fprintf_func) (info->stream, "]"); - } - - else - (*info->fprintf_func) (info->stream, "%d", value); - } - /* All done. */ - break; - } - op++; - } - - if (!match) - { - /* xgettext:c-format */ - (*info->fprintf_func) (info->stream, _("unknown\t0x%04x"), insn); - } -} diff --git a/opcodes/m10300-opc.c b/opcodes/m10300-opc.c deleted file mode 100644 index bb385b827a6..00000000000 --- a/opcodes/m10300-opc.c +++ /dev/null @@ -1,1565 +0,0 @@ -/* Assemble Matsushita MN10300 instructions. - Copyright (C) 1996, 1997 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -/* This file is formatted at > 80 columns. Attempting to read it on a - screeen with less than 80 columns will be difficult. */ -#include "ansidecl.h" -#include "opcode/mn10300.h" - - -const struct mn10300_operand mn10300_operands[] = { -#define UNUSED 0 - {0, 0, 0}, - -/* dn register in the first register operand position. */ -#define DN0 (UNUSED+1) - {2, 0, MN10300_OPERAND_DREG}, - -/* dn register in the second register operand position. */ -#define DN1 (DN0+1) - {2, 2, MN10300_OPERAND_DREG}, - -/* dn register in the third register operand position. */ -#define DN2 (DN1+1) - {2, 4, MN10300_OPERAND_DREG}, - -/* dm register in the first register operand position. */ -#define DM0 (DN2+1) - {2, 0, MN10300_OPERAND_DREG}, - -/* dm register in the second register operand position. */ -#define DM1 (DM0+1) - {2, 2, MN10300_OPERAND_DREG}, - -/* dm register in the third register operand position. */ -#define DM2 (DM1+1) - {2, 4, MN10300_OPERAND_DREG}, - -/* an register in the first register operand position. */ -#define AN0 (DM2+1) - {2, 0, MN10300_OPERAND_AREG}, - -/* an register in the second register operand position. */ -#define AN1 (AN0+1) - {2, 2, MN10300_OPERAND_AREG}, - -/* an register in the third register operand position. */ -#define AN2 (AN1+1) - {2, 4, MN10300_OPERAND_AREG}, - -/* am register in the first register operand position. */ -#define AM0 (AN2+1) - {2, 0, MN10300_OPERAND_AREG}, - -/* am register in the second register operand position. */ -#define AM1 (AM0+1) - {2, 2, MN10300_OPERAND_AREG}, - -/* am register in the third register operand position. */ -#define AM2 (AM1+1) - {2, 4, MN10300_OPERAND_AREG}, - -/* 8 bit unsigned immediate which may promote to a 16bit - unsigned immediate. */ -#define IMM8 (AM2+1) - {8, 0, MN10300_OPERAND_PROMOTE}, - -/* 16 bit unsigned immediate which may promote to a 32bit - unsigned immediate. */ -#define IMM16 (IMM8+1) - {16, 0, MN10300_OPERAND_PROMOTE}, - -/* 16 bit pc-relative immediate which may promote to a 16bit - pc-relative immediate. */ -#define IMM16_PCREL (IMM16+1) - {16, 0, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED}, - -/* 16bit unsigned dispacement in a memory operation which - may promote to a 32bit displacement. */ -#define IMM16_MEM (IMM16_PCREL+1) - {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR}, - -/* 32bit immediate, high 16 bits in the main instruction - word, 16bits in the extension word. - - The "bits" field indicates how many bits are in the - main instruction word for MN10300_OPERAND_SPLIT! */ -#define IMM32 (IMM16_MEM+1) - {16, 0, MN10300_OPERAND_SPLIT}, - -/* 32bit pc-relative offset. */ -#define IMM32_PCREL (IMM32+1) - {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL}, - -/* 32bit memory offset. */ -#define IMM32_MEM (IMM32_PCREL+1) - {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR}, - -/* 32bit immediate, high 16 bits in the main instruction - word, 16bits in the extension word, low 16bits are left - shifted 8 places. - - The "bits" field indicates how many bits are in the - main instruction word for MN10300_OPERAND_SPLIT! */ -#define IMM32_LOWSHIFT8 (IMM32_MEM+1) - {16, 8, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR}, - -/* 32bit immediate, high 24 bits in the main instruction - word, 8 in the extension word. - - The "bits" field indicates how many bits are in the - main instruction word for MN10300_OPERAND_SPLIT! */ -#define IMM32_HIGH24 (IMM32_LOWSHIFT8+1) - {24, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL}, - -/* 32bit immediate, high 24 bits in the main instruction - word, 8 in the extension word, low 8 bits are left - shifted 16 places. - - The "bits" field indicates how many bits are in the - main instruction word for MN10300_OPERAND_SPLIT! */ -#define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1) - {24, 16, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL}, - -/* Stack pointer. */ -#define SP (IMM32_HIGH24_LOWSHIFT16+1) - {8, 0, MN10300_OPERAND_SP}, - -/* Processor status word. */ -#define PSW (SP+1) - {0, 0, MN10300_OPERAND_PSW}, - -/* MDR register. */ -#define MDR (PSW+1) - {0, 0, MN10300_OPERAND_MDR}, - -/* Index register. */ -#define DI (MDR+1) - {2, 2, MN10300_OPERAND_DREG}, - -/* 8 bit signed displacement, may promote to 16bit signed dispacement. */ -#define SD8 (DI+1) - {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, - -/* 16 bit signed displacement, may promote to 32bit dispacement. */ -#define SD16 (SD8+1) - {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, - -/* 8 bit signed displacement that can not promote. */ -#define SD8N (SD16+1) - {8, 0, MN10300_OPERAND_SIGNED}, - -/* 8 bit pc-relative displacement. */ -#define SD8N_PCREL (SD8N+1) - {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX}, - -/* 8 bit signed displacement shifted left 8 bits in the instruction. */ -#define SD8N_SHIFT8 (SD8N_PCREL+1) - {8, 8, MN10300_OPERAND_SIGNED}, - -/* 8 bit signed immediate which may promote to 16bit signed immediate. */ -#define SIMM8 (SD8N_SHIFT8+1) - {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, - -/* 16 bit signed immediate which may promote to 32bit immediate. */ -#define SIMM16 (SIMM8+1) - {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, - -/* Either an open paren or close paren. */ -#define PAREN (SIMM16+1) - {0, 0, MN10300_OPERAND_PAREN}, - -/* dn register that appears in the first and second register positions. */ -#define DN01 (PAREN+1) - {2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED}, - -/* an register that appears in the first and second register positions. */ -#define AN01 (DN01+1) - {2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED}, - -/* 16bit pc-relative displacement which may promote to 32bit pc-relative - displacement. */ -#define D16_SHIFT (AN01+1) - {16, 8, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED}, - -/* 8 bit immediate found in the extension word. */ -#define IMM8E (D16_SHIFT+1) - {8, 0, MN10300_OPERAND_EXTENDED}, - -/* Register list found in the extension word shifted 8 bits left. */ -#define REGSE_SHIFT8 (IMM8E+1) - {8, 8, MN10300_OPERAND_EXTENDED | MN10300_OPERAND_REG_LIST}, - -/* Register list shifted 8 bits left. */ -#define REGS_SHIFT8 (REGSE_SHIFT8 + 1) - {8, 8, MN10300_OPERAND_REG_LIST}, - -/* Reigster list. */ -#define REGS (REGS_SHIFT8+1) - {8, 0, MN10300_OPERAND_REG_LIST}, - -/* start-sanitize-am33 */ -/* UStack pointer. */ -#define USP (REGS+1) - {0, 0, MN10300_OPERAND_USP}, - -/* SStack pointer. */ -#define SSP (USP+1) - {0, 0, MN10300_OPERAND_SSP}, - -/* MStack pointer. */ -#define MSP (SSP+1) - {0, 0, MN10300_OPERAND_MSP}, - -/* PC . */ -#define PC (MSP+1) - {0, 0, MN10300_OPERAND_PC}, - -/* 4 bit immediate for syscall. */ -#define IMM4 (PC+1) - {4, 0, 0}, - -/* Processor status word. */ -#define EPSW (IMM4+1) - {0, 0, MN10300_OPERAND_EPSW}, - -/* rn register in the first register operand position. */ -#define RN0 (EPSW+1) - {4, 0, MN10300_OPERAND_RREG}, - -/* rn register in the fourth register operand position. */ -#define RN2 (RN0+1) - {4, 4, MN10300_OPERAND_RREG}, - -/* rm register in the first register operand position. */ -#define RM0 (RN2+1) - {4, 0, MN10300_OPERAND_RREG}, - -/* rm register in the second register operand position. */ -#define RM1 (RM0+1) - {4, 2, MN10300_OPERAND_RREG}, - -/* rm register in the third register operand position. */ -#define RM2 (RM1+1) - {4, 4, MN10300_OPERAND_RREG}, - -#define RN02 (RM2+1) - {4, 0, MN10300_OPERAND_RREG | MN10300_OPERAND_REPEATED}, - -#define XRN0 (RN02+1) - {4, 0, MN10300_OPERAND_XRREG}, - -#define XRM2 (XRN0+1) - {4, 4, MN10300_OPERAND_XRREG}, - -/* + for autoincrement */ -#define PLUS (XRM2+1) - {0, 0, MN10300_OPERAND_PLUS}, - -#define XRN02 (PLUS+1) - {4, 0, MN10300_OPERAND_XRREG | MN10300_OPERAND_REPEATED}, - -/* Ick */ -#define RD0 (XRN02+1) - {4, -8, MN10300_OPERAND_RREG}, - -#define RD2 (RD0+1) - {4, -4, MN10300_OPERAND_RREG}, - -/* 8 unsigned dispacement in a memory operation which - may promote to a 32bit displacement. */ -#define IMM8_MEM (RD2+1) - {8, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR}, - -/* Index register. */ -#define RI (IMM8_MEM+1) - {4, 4, MN10300_OPERAND_RREG}, - -/* 24 bit signed displacement, may promote to 32bit dispacement. */ -#define SD24 (RI+1) - {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, - -/* 24 bit unsigned immediate which may promote to a 32bit - unsigned immediate. */ -#define IMM24 (SD24+1) - {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE}, - -/* 24 bit signed immediate which may promote to a 32bit - signed immediate. */ -#define SIMM24 (IMM24+1) - {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_SIGNED}, - -/* 16bit unsigned dispacement in a memory operation which - may promote to a 32bit displacement. */ -#define IMM24_MEM (SIMM24+1) - {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR}, -/* 32bit immediate, high 24 bits in the main instruction - word, 8 in the extension word. - - The "bits" field indicates how many bits are in the - main instruction word for MN10300_OPERAND_SPLIT! */ -#define IMM32_HIGH8 (IMM24_MEM+1) - {8, 0, MN10300_OPERAND_SPLIT}, - -/* Similarly, but a memory address. */ -#define IMM32_HIGH8_MEM (IMM32_HIGH8+1) - {8, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR}, - -/* rm register in the seventh register operand position. */ -#define RM6 (IMM32_HIGH8_MEM+1) - {4, 12, MN10300_OPERAND_RREG}, - -/* rm register in the fifth register operand position. */ -#define RN4 (RM6+1) - {4, 8, MN10300_OPERAND_RREG}, - -/* 4 bit immediate for dsp instructions. */ -#define IMM4_2 (RN4+1) - {4, 4, 0}, - -/* 4 bit immediate for dsp instructions. */ -#define SIMM4_2 (IMM4_2+1) - {4, 4, MN10300_OPERAND_SIGNED}, - -/* 4 bit immediate for dsp instructions. */ -#define SIMM4_6 (SIMM4_2+1) - {4, 12, MN10300_OPERAND_SIGNED}, -/* end-sanitize-am33 */ - -} ; - -#define MEM(ADDR) PAREN, ADDR, PAREN -#define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN -#define MEMINC2(ADDR,INC) PAREN, ADDR, PLUS, INC, PAREN -#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN - -/* The opcode table. - - The format of the opcode table is: - - NAME OPCODE MASK MATCH_MASK, FORMAT, PROCESSOR { OPERANDS } - - NAME is the name of the instruction. - OPCODE is the instruction opcode. - MASK is the opcode mask; this is used to tell the disassembler - which bits in the actual opcode must match OPCODE. - OPERANDS is the list of operands. - - The disassembler reads the table in order and prints the first - instruction which matches, so this table is sorted to put more - specific instructions before more general instructions. It is also - sorted by major opcode. */ - -const struct mn10300_opcode mn10300_opcodes[] = { -{ "mov", 0x8000, 0xf000, 0, FMT_S1, 0, {SIMM8, DN01}}, -{ "mov", 0x80, 0xf0, 0x3, FMT_S0, 0, {DM1, DN0}}, -{ "mov", 0xf1e0, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}}, -{ "mov", 0xf1d0, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}}, -{ "mov", 0x9000, 0xf000, 0, FMT_S1, 0, {IMM8, AN01}}, -{ "mov", 0x90, 0xf0, 0x3, FMT_S0, 0, {AM1, AN0}}, -{ "mov", 0x3c, 0xfc, 0, FMT_S0, 0, {SP, AN0}}, -{ "mov", 0xf2f0, 0xfff3, 0, FMT_D0, 0, {AM1, SP}}, -{ "mov", 0xf2e4, 0xfffc, 0, FMT_D0, 0, {PSW, DN0}}, -{ "mov", 0xf2f3, 0xfff3, 0, FMT_D0, 0, {DM1, PSW}}, -{ "mov", 0xf2e0, 0xfffc, 0, FMT_D0, 0, {MDR, DN0}}, -{ "mov", 0xf2f2, 0xfff3, 0, FMT_D0, 0, {DM1, MDR}}, -{ "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}}, -{ "mov", 0x5800, 0xfcff, 0, FMT_S1, 0, {MEM(SP), DN0}}, -{ "mov", 0x300000, 0xfc0000, 0, FMT_S2, 0, {MEM(IMM16_MEM), DN0}}, -{ "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}}, -{ "mov", 0x5c00, 0xfcff, 0, FMT_S1, 0, {MEM(SP), AN0}}, -{ "mov", 0xfaa00000, 0xfffc0000, 0, FMT_D2, 0, {MEM(IMM16_MEM), AN0}}, -{ "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}}, -{ "mov", 0x4200, 0xf3ff, 0, FMT_S1, 0, {DM1, MEM(SP)}}, -{ "mov", 0x010000, 0xf30000, 0, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}}, -{ "mov", 0xf010, 0xfff0, 0, FMT_D0, 0, {AM1, MEM(AN0)}}, -{ "mov", 0x4300, 0xf3ff, 0, FMT_S1, 0, {AM1, MEM(SP)}}, -{ "mov", 0xfa800000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM(IMM16_MEM)}}, -{ "mov", 0x5c00, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), AN0}}, -{ "mov", 0xf80000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}}, -{ "mov", 0xfa000000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}}, -{ "mov", 0x5800, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), DN0}}, -{ "mov", 0xfab40000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}}, -{ "mov", 0xf300, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}}, -{ "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}}, -{ "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}}, -{ "mov", 0xfab00000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), AN0}}, -{ "mov", 0xf380, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), AN2}}, -{ "mov", 0x4300, 0xf300, 0, FMT_S1, 0, {AM1, MEM2(IMM8, SP)}}, -{ "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, -{ "mov", 0xfa100000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, -{ "mov", 0x4200, 0xf300, 0, FMT_S1, 0, {DM1, MEM2(IMM8, SP)}}, -{ "mov", 0xfa910000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}}, -{ "mov", 0xf340, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}}, -{ "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}}, -{ "mov", 0xfa300000, 0xfff00000, 0, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}}, -{ "mov", 0xfa900000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM2(IMM16, SP)}}, -{ "mov", 0xf3c0, 0xffc0, 0, FMT_D0, 0, {AM2, MEM2(DI, AN0)}}, - -/* start-sanitize-am33 */ -{ "mov", 0xf020, 0xfffc, 0, FMT_D0, AM33, {USP, AN0}}, -{ "mov", 0xf024, 0xfffc, 0, FMT_D0, AM33, {SSP, AN0}}, -{ "mov", 0xf028, 0xfffc, 0, FMT_D0, AM33, {MSP, AN0}}, -{ "mov", 0xf02c, 0xfffc, 0, FMT_D0, AM33, {PC, AN0}}, -{ "mov", 0xf030, 0xfff3, 0, FMT_D0, AM33, {AN1, USP}}, -{ "mov", 0xf031, 0xfff3, 0, FMT_D0, AM33, {AN1, SSP}}, -{ "mov", 0xf032, 0xfff3, 0, FMT_D0, AM33, {AN1, MSP}}, -{ "mov", 0xf2ec, 0xfffc, 0, FMT_D0, AM33, {EPSW, DN0}}, -{ "mov", 0xf2f1, 0xfff3, 0, FMT_D0, AM33, {DM1, EPSW}}, -{ "mov", 0xf500, 0xffc0, 0, FMT_D0, AM33, {AM2, RN0}}, -{ "mov", 0xf540, 0xffc0, 0, FMT_D0, AM33, {DM2, RN0}}, -{ "mov", 0xf580, 0xffc0, 0, FMT_D0, AM33, {RM1, AN0}}, -{ "mov", 0xf5c0, 0xffc0, 0, FMT_D0, AM33, {RM1, DN0}}, -{ "mov", 0xf90800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -{ "mov", 0xf9e800, 0xffff00, 0, FMT_D6, AM33, {XRM2, RN0}}, -{ "mov", 0xf9f800, 0xffff00, 0, FMT_D6, AM33, {RM2, XRN0}}, -{ "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, -{ "mov", 0xf98a00, 0xffff0f, 0, FMT_D6, AM33, {MEM(SP), RN2}}, -{ "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}}, -{ "mov", 0xfb0e0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}}, -{ "mov", 0xfd0e0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}}, -{ "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, -{ "mov", 0xf99a00, 0xffff0f, 0, FMT_D6, AM33, {RM2, MEM(SP)}}, -{ "mov", 0xf97a00, 0xffff00, 0x5, FMT_D6, AM33, {RM2, MEMINC(RN0)}}, -{ "mov", 0xfb1e0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}}, -{ "mov", 0xfd1e0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}}, -{ "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, -{ "mov", 0xfd0a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, -{ "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, -{ "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, -{ "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, -{ "mov", 0xfb8a0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(SD8, SP), RN2}}, -{ "mov", 0xfd8a0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(SD24, SP), RN2}}, -{ "mov", 0xfb9a0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(SD8, SP)}}, -{ "mov", 0xfd9a0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(SD24, SP)}}, -{ "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, -{ "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, -{ "mov", 0xfb7a0000, 0xffff0000, 0x5, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, -{ "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}}, -{ "mov", 0xfd7a0000, 0xffff0000, 0x5, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}}, -{ "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}}, -{ "mov", 0xfe7a0000, 0xffff0000, 0x5, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}}, -/* end-sanitize-am33 */ -/* These must come after most of the other move instructions to avoid matching - a symbolic name with IMMxx operands. Ugh. */ -{ "mov", 0x2c0000, 0xfc0000, 0, FMT_S2, 0, {SIMM16, DN0}}, -{ "mov", 0xfccc0000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "mov", 0x240000, 0xfc0000, 0, FMT_S2, 0, {IMM16, AN0}}, -{ "mov", 0xfcdc0000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}}, -{ "mov", 0xfca40000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}}, -{ "mov", 0xfca00000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), AN0}}, -{ "mov", 0xfc810000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}}, -{ "mov", 0xfc800000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM(IMM32_MEM)}}, -{ "mov", 0xfc000000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, -{ "mov", 0xfcb40000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}}, -{ "mov", 0xfc200000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}}, -{ "mov", 0xfcb00000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), AN0}}, -{ "mov", 0xfc100000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, -{ "mov", 0xfc910000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}}, -{ "mov", 0xfc300000, 0xfff00000, 0, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}}, -{ "mov", 0xfc900000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM2(IMM32, SP)}}, -/* These non-promoting variants need to come after all the other memory - moves. */ -{ "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM30, {MEM2(SD8N, AM0), SP}}, -{ "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM30, {SP, MEM2(SD8N, AN0)}}, -/* start-sanitize-am33 */ -/* These are the same as the previous non-promoting versions. The am33 - does not have restrictions on the offsets used to load/store the stack - pointer. */ -{ "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM33, {MEM2(SD8, AM0), SP}}, -{ "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM33, {SP, MEM2(SD8, AN0)}}, -/* These must come last so that we favor shorter move instructions for - loading immediates into d0-d3/a0-a3. */ -{ "mov", 0xfb080000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, -{ "mov", 0xfd080000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, -{ "mov", 0xfe080000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -{ "mov", 0xfbf80000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, XRN02}}, -{ "mov", 0xfdf80000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, XRN02}}, -{ "mov", 0xfef80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, XRN02}}, -{ "mov", 0xfe0e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}}, -{ "mov", 0xfe1e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}}, -{ "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, -{ "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, -{ "mov", 0xfe8a0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}}, -{ "mov", 0xfe9a0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}}, -/* end-sanitize-am33 */ - -/* start-sanitize-am33 */ -{ "movu", 0xfb180000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, -{ "movu", 0xfd180000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, -{ "movu", 0xfe180000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -/* end-sanitize-am33 */ - -/* start-sanitize-am33 */ -{ "mcst9", 0xf630, 0xfff0, 0, FMT_D0, AM33, {DN01}}, -{ "mcst48", 0xf660, 0xfff0, 0, FMT_D0, AM33, {DN01}}, -{ "swap", 0xf680, 0xfff0, 0, FMT_D0, AM33, {DM1, DN0}}, -{ "swap", 0xf9cb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -{ "swaph", 0xf690, 0xfff0, 0, FMT_D0, AM33, {DM1, DN0}}, -{ "swaph", 0xf9db00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -{ "getchx", 0xf6c0, 0xfff0, 0, FMT_D0, AM33, {DN01}}, -{ "getclx", 0xf6d0, 0xfff0, 0, FMT_D0, AM33, {DN01}}, -{ "mac", 0xfb0f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, -{ "mac", 0xf90b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -{ "mac", 0xfb0b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, -{ "mac", 0xfd0b0000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, -{ "mac", 0xfe0b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -{ "macu", 0xfb1f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, -{ "macu", 0xf91b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -{ "macu", 0xfb1b0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, -{ "macu", 0xfd1b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, -{ "macu", 0xfe1b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -{ "macb", 0xfb2f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, -{ "macb", 0xf92b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -{ "macb", 0xfb2b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, -{ "macb", 0xfd2b0000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, -{ "macb", 0xfe2b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -{ "macbu", 0xfb3f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, -{ "macbu", 0xf93b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -{ "macbu", 0xfb3b0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, -{ "macbu", 0xfd3b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, -{ "macbu", 0xfe3b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -{ "mach", 0xfb4f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, -{ "mach", 0xf94b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -{ "mach", 0xfb4b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, -{ "mach", 0xfd4b0000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, -{ "mach", 0xfe4b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -{ "machu", 0xfb5f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, -{ "machu", 0xf95b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -{ "machu", 0xfb5b0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, -{ "machu", 0xfd5b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, -{ "machu", 0xfe5b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -{ "dmach", 0xfb6f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, -{ "dmach", 0xf96b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -{ "dmach", 0xfe6b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -{ "dmachu", 0xfb7f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, -{ "dmachu", 0xf97b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -{ "dmachu", 0xfe7b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -{ "dmulh", 0xfb8f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, -{ "dmulh", 0xf98b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -{ "dmulh", 0xfe8b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -{ "dmulhu", 0xfb9f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, -{ "dmulhu", 0xf99b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -{ "dmulhu", 0xfe9b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -{ "mcste", 0xf9bb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -{ "mcste", 0xfbbb0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, -{ "swhw", 0xf9eb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -/* end-sanitize-am33 */ - -{ "movbu", 0xf040, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}}, -{ "movbu", 0xf84000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}}, -{ "movbu", 0xfa400000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}}, -{ "movbu", 0xf8b800, 0xfffcff, 0, FMT_D1, 0, {MEM(SP), DN0}}, -{ "movbu", 0xf8b800, 0xfffc00, 0, FMT_D1, 0, {MEM2(IMM8, SP), DN0}}, -{ "movbu", 0xfab80000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}}, -{ "movbu", 0xf400, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}}, -{ "movbu", 0x340000, 0xfc0000, 0, FMT_S2, 0, {MEM(IMM16_MEM), DN0}}, -{ "movbu", 0xf050, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, -{ "movbu", 0xf85000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, -{ "movbu", 0xfa500000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, -{ "movbu", 0xf89200, 0xfff3ff, 0, FMT_D1, 0, {DM1, MEM(SP)}}, -{ "movbu", 0xf89200, 0xfff300, 0, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}}, -{ "movbu", 0xfa920000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}}, -{ "movbu", 0xf440, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}}, -{ "movbu", 0x020000, 0xf30000, 0, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}}, -/* start-sanitize-am33 */ -{ "movbu", 0xf92a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, -{ "movbu", 0xf93a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, -{ "movbu", 0xf9aa00, 0xffff0f, 0, FMT_D6, AM33, {MEM(SP), RN2}}, -{ "movbu", 0xf9ba00, 0xffff0f, 0, FMT_D6, AM33, {RM2, MEM(SP)}}, -{ "movbu", 0xfb2a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, -{ "movbu", 0xfd2a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, -{ "movbu", 0xfb3a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, -{ "movbu", 0xfd3a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, -{ "movbu", 0xfbaa0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(SD8, SP), RN2}}, -{ "movbu", 0xfdaa0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(SD24, SP), RN2}}, -{ "movbu", 0xfbba0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(SD8, SP)}}, -{ "movbu", 0xfdba0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(SD24, SP)}}, -{ "movbu", 0xfb2e0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}}, -{ "movbu", 0xfd2e0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}}, -{ "movbu", 0xfb3e0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}}, -{ "movbu", 0xfd3e0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}}, -{ "movbu", 0xfbae0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, -{ "movbu", 0xfbbe0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, -/* end-sanitize-am33 */ -{ "movbu", 0xfc400000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, -{ "movbu", 0xfcb80000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}}, -{ "movbu", 0xfca80000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}}, -{ "movbu", 0xfc500000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, -{ "movbu", 0xfc920000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}}, -{ "movbu", 0xfc820000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}}, -/* start-sanitize-am33 */ -{ "movbu", 0xfe2a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, -{ "movbu", 0xfe3a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, -{ "movbu", 0xfeaa0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,SP), RN2}}, -{ "movbu", 0xfeba0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}}, -{ "movbu", 0xfe2e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}}, -{ "movbu", 0xfe3e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}}, -/* end-sanitize-am33 */ - -{ "movhu", 0xf060, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}}, -{ "movhu", 0xf86000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}}, -{ "movhu", 0xfa600000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}}, -{ "movhu", 0xf8bc00, 0xfffcff, 0, FMT_D1, 0, {MEM(SP), DN0}}, -{ "movhu", 0xf8bc00, 0xfffc00, 0, FMT_D1, 0, {MEM2(IMM8, SP), DN0}}, -{ "movhu", 0xfabc0000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}}, -{ "movhu", 0xf480, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}}, -{ "movhu", 0x380000, 0xfc0000, 0, FMT_S2, 0, {MEM(IMM16_MEM), DN0}}, -{ "movhu", 0xf070, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, -{ "movhu", 0xf87000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, -{ "movhu", 0xfa700000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, -{ "movhu", 0xf89300, 0xfff3ff, 0, FMT_D1, 0, {DM1, MEM(SP)}}, -{ "movhu", 0xf89300, 0xfff300, 0, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}}, -{ "movhu", 0xfa930000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}}, -{ "movhu", 0xf4c0, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}}, -{ "movhu", 0x030000, 0xf30000, 0, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}}, -/* start-sanitize-am33 */ -{ "movhu", 0xf94a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, -{ "movhu", 0xf95a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, -{ "movhu", 0xf9ca00, 0xffff0f, 0, FMT_D6, AM33, {MEM(SP), RN2}}, -{ "movhu", 0xf9da00, 0xffff0f, 0, FMT_D6, AM33, {RM2, MEM(SP)}}, -{ "movhu", 0xf9ea00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}}, -{ "movhu", 0xf9fa00, 0xffff00, 0x5, FMT_D6, AM33, {RM2, MEMINC(RN0)}}, -{ "movhu", 0xfb4a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, -{ "movhu", 0xfd4a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, -{ "movhu", 0xfb5a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, -{ "movhu", 0xfd5a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, -{ "movhu", 0xfbca0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(SD8, SP), RN2}}, -{ "movhu", 0xfdca0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(SD24, SP), RN2}}, -{ "movhu", 0xfbda0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(SD8, SP)}}, -{ "movhu", 0xfdda0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(SD24, SP)}}, -{ "movhu", 0xfb4e0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}}, -{ "movhu", 0xfd4e0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}}, -{ "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, -{ "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, -/* end-sanitize-am33 */ -{ "movhu", 0xfc600000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, -{ "movhu", 0xfcbc0000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}}, -{ "movhu", 0xfcac0000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}}, -{ "movhu", 0xfc700000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, -{ "movhu", 0xfc930000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}}, -{ "movhu", 0xfc830000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}}, -/* start-sanitize-am33 */ -{ "movhu", 0xfe4a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, -{ "movhu", 0xfe5a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, -{ "movhu", 0xfeca0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}}, -{ "movhu", 0xfeda0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}}, -{ "movhu", 0xfe4e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}}, -{ "movhu", 0xfb5e0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}}, -{ "movhu", 0xfd5e0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}}, -{ "movhu", 0xfe5e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}}, -{ "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, -{ "movhu", 0xfbfa0000, 0xffff0000, 0x5, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, -{ "movhu", 0xfdea0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}}, -{ "movhu", 0xfdfa0000, 0xffff0000, 0x5, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}}, -{ "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}}, -{ "movhu", 0xfefa0000, 0xffff0000, 0x5, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}}, -/* end-sanitize-am33 */ - -{ "ext", 0xf2d0, 0xfffc, 0, FMT_D0, 0, {DN0}}, -/* start-sanitize-am33 */ -{ "ext", 0xf91800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, -/* end-sanitize-am33 */ - -/* start-sanitize-am33 */ -{ "extb", 0xf92800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -/* end-sanitize-am33 */ -{ "extb", 0x10, 0xfc, 0, FMT_S0, 0, {DN0}}, -/* start-sanitize-am33 */ -{ "extb", 0xf92800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, -/* end-sanitize-am33 */ - -/* start-sanitize-am33 */ -{ "extbu", 0xf93800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -/* end-sanitize-am33 */ -{ "extbu", 0x14, 0xfc, 0, FMT_S0, 0, {DN0}}, -/* start-sanitize-am33 */ -{ "extbu", 0xf93800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, -/* end-sanitize-am33 */ - -/* start-sanitize-am33 */ -{ "exth", 0xf94800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -/* end-sanitize-am33 */ -{ "exth", 0x18, 0xfc, 0, FMT_S0, 0, {DN0}}, -/* start-sanitize-am33 */ -{ "exth", 0xf94800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, -/* end-sanitize-am33 */ - -/* start-sanitize-am33 */ -{ "exthu", 0xf95800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -/* end-sanitize-am33 */ -{ "exthu", 0x1c, 0xfc, 0, FMT_S0, 0, {DN0}}, -/* start-sanitize-am33 */ -{ "exthu", 0xf95800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, -/* end-sanitize-am33 */ - -{ "movm", 0xce00, 0xff00, 0, FMT_S1, 0, {MEM(SP), REGS}}, -{ "movm", 0xcf00, 0xff00, 0, FMT_S1, 0, {REGS, MEM(SP)}}, -/* start-sanitize-am33 */ -{ "movm", 0xf8ce00, 0xffff00, 0, FMT_D1, AM33, {MEM(USP), REGS}}, -{ "movm", 0xf8cf00, 0xffff00, 0, FMT_D1, AM33, {REGS, MEM(USP)}}, -/* end-sanitize-am33 */ - -{ "clr", 0x00, 0xf3, 0, FMT_S0, 0, {DN1}}, -/* start-sanitize-am33 */ -{ "clr", 0xf96800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, -/* end-sanitize-am33 */ - -/* start-sanitize-am33 */ -{ "add", 0xfb7c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, -/* end-sanitize-am33 */ -{ "add", 0xe0, 0xf0, 0, FMT_S0, 0, {DM1, DN0}}, -{ "add", 0xf160, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}}, -{ "add", 0xf150, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}}, -{ "add", 0xf170, 0xfff0, 0, FMT_D0, 0, {AM1, AN0}}, -{ "add", 0x2800, 0xfc00, 0, FMT_S1, 0, {SIMM8, DN0}}, -{ "add", 0xfac00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, -{ "add", 0x2000, 0xfc00, 0, FMT_S1, 0, {SIMM8, AN0}}, -{ "add", 0xfad00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, AN0}}, -{ "add", 0xf8fe00, 0xffff00, 0, FMT_D1, 0, {SIMM8, SP}}, -{ "add", 0xfafe0000, 0xffff0000, 0, FMT_D2, 0, {SIMM16, SP}}, -/* start-sanitize-am33 */ -{ "add", 0xf97800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -/* end-sanitize-am33 */ -{ "add", 0xfcc00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "add", 0xfcd00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}}, -{ "add", 0xfcfe0000, 0xffff0000, 0, FMT_D4, 0, {IMM32, SP}}, -/* start-sanitize-am33 */ -{ "add", 0xfb780000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, -{ "add", 0xfd780000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, -{ "add", 0xfe780000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -/* end-sanitize-am33 */ - -/* start-sanitize-am33 */ -{ "addc", 0xfb8c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, -/* end-sanitize-am33 */ -{ "addc", 0xf140, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -/* start-sanitize-am33 */ -{ "addc", 0xf98800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -{ "addc", 0xfb880000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, -{ "addc", 0xfd880000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, -{ "addc", 0xfe880000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -/* end-sanitize-am33 */ - -/* start-sanitize-am33 */ -{ "sub", 0xfb9c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, -/* end-sanitize-am33 */ -{ "sub", 0xf100, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "sub", 0xf120, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}}, -{ "sub", 0xf110, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}}, -{ "sub", 0xf130, 0xfff0, 0, FMT_D0, 0, {AM1, AN0}}, -/* start-sanitize-am33 */ -{ "sub", 0xf99800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -/* end-sanitize-am33 */ -{ "sub", 0xfcc40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "sub", 0xfcd40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}}, -/* start-sanitize-am33 */ -{ "sub", 0xfb980000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, -{ "sub", 0xfd980000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, -{ "sub", 0xfe980000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -/* end-sanitize-am33 */ - -/* start-sanitize-am33 */ -{ "subc", 0xfa8c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, -/* end-sanitize-am33 */ -{ "subc", 0xf180, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -/* start-sanitize-am33 */ -{ "subc", 0xf9a800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -{ "subc", 0xfba80000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, -{ "subc", 0xfda80000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, -{ "subc", 0xfea80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -/* end-sanitize-am33 */ - -/* start-sanitize-am33 */ -{ "mul", 0xfbad0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, -/* end-sanitize-am33 */ -{ "mul", 0xf240, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -/* start-sanitize-am33 */ -{ "mul", 0xf9a900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -{ "mul", 0xfba90000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, -{ "mul", 0xfda90000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, -{ "mul", 0xfea90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -/* end-sanitize-am33 */ - -/* start-sanitize-am33 */ -{ "mulu", 0xfbbd0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, -/* end-sanitize-am33 */ -{ "mulu", 0xf250, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -/* start-sanitize-am33 */ -{ "mulu", 0xf9b900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -{ "mulu", 0xfbb90000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, -{ "mulu", 0xfdb90000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, -{ "mulu", 0xfeb90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -/* end-sanitize-am33 */ - -{ "div", 0xf260, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -/* start-sanitize-am33 */ -{ "div", 0xf9c900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -/* end-sanitize-am33 */ - -{ "divu", 0xf270, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -/* start-sanitize-am33 */ -{ "divu", 0xf9d900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -/* end-sanitize-am33 */ - -{ "inc", 0x40, 0xf3, 0, FMT_S0, 0, {DN1}}, -{ "inc", 0x41, 0xf3, 0, FMT_S0, 0, {AN1}}, -/* start-sanitize-am33 */ -{ "inc", 0xf9b800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, -/* end-sanitize-am33 */ - -{ "inc4", 0x50, 0xfc, 0, FMT_S0, 0, {AN0}}, -/* start-sanitize-am33 */ -{ "inc4", 0xf9c800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, -/* end-sanitize-am33 */ - -{ "cmp", 0xa000, 0xf000, 0, FMT_S1, 0, {SIMM8, DN01}}, -{ "cmp", 0xa0, 0xf0, 0x3, FMT_S0, 0, {DM1, DN0}}, -{ "cmp", 0xf1a0, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}}, -{ "cmp", 0xf190, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}}, -{ "cmp", 0xb000, 0xf000, 0, FMT_S1, 0, {IMM8, AN01}}, -{ "cmp", 0xb0, 0xf0, 0x3, FMT_S0, 0, {AM1, AN0}}, -{ "cmp", 0xfac80000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, -{ "cmp", 0xfad80000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, AN0}}, -/* start-sanitize-am33 */ -{ "cmp", 0xf9d800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -/* end-sanitize-am33 */ -{ "cmp", 0xfcc80000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "cmp", 0xfcd80000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}}, -/* start-sanitize-am33 */ -{ "cmp", 0xfbd80000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, -{ "cmp", 0xfdd80000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, -{ "cmp", 0xfed80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -/* end-sanitize-am33 */ - -/* start-sanitize-am33 */ -{ "and", 0xfb0d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, -/* end-sanitize-am33 */ -{ "and", 0xf200, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "and", 0xf8e000, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, -{ "and", 0xfae00000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, -{ "and", 0xfafc0000, 0xffff0000, 0, FMT_D2, 0, {IMM16, PSW}}, -/* start-sanitize-am33 */ -{ "and", 0xfcfc0000, 0xffff0000, 0, FMT_D4, AM33, {IMM32, EPSW}}, -{ "and", 0xf90900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -/* end-sanitize-am33 */ -{ "and", 0xfce00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -/* start-sanitize-am33 */ -{ "and", 0xfb090000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, -{ "and", 0xfd090000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, -{ "and", 0xfe090000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -/* end-sanitize-am33 */ - -/* start-sanitize-am33 */ -{ "or", 0xfb1d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, -/* end-sanitize-am33 */ -{ "or", 0xf210, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "or", 0xf8e400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, -{ "or", 0xfae40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, -{ "or", 0xfafd0000, 0xffff0000, 0, FMT_D2, 0, {IMM16, PSW}}, -/* start-sanitize-am33 */ -{ "or", 0xfcfd0000, 0xffff0000, 0, FMT_D4, AM33, {IMM32, EPSW}}, -{ "or", 0xf91900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -/* end-sanitize-am33 */ -{ "or", 0xfce40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -/* start-sanitize-am33 */ -{ "or", 0xfb190000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, -{ "or", 0xfd190000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, -{ "or", 0xfe190000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -/* end-sanitize-am33 */ - -/* start-sanitize-am33 */ -{ "xor", 0xfb2d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, -/* end-sanitize-am33 */ -{ "xor", 0xf220, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "xor", 0xfae80000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, -/* start-sanitize-am33 */ -{ "xor", 0xf92900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -/* end-sanitize-am33 */ -{ "xor", 0xfce80000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -/* start-sanitize-am33 */ -{ "xor", 0xfb290000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, -{ "xor", 0xfd290000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, -{ "xor", 0xfe290000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -/* end-sanitize-am33 */ - -{ "not", 0xf230, 0xfffc, 0, FMT_D0, 0, {DN0}}, -/* start-sanitize-am33 */ -{ "not", 0xf93900, 0xffff00, 0, FMT_D6, AM33, {RN02}}, -/* end-sanitize-am33 */ - -{ "btst", 0xf8ec00, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, -{ "btst", 0xfaec0000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, -{ "btst", 0xfcec0000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -/* start-sanitize-am33 */ -/* Place these before the ones with IMM8E and SD8N_SHIFT8 since we want the - them to match last since they do not promote. */ -{ "btst", 0xfbe90000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, -{ "btst", 0xfde90000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, -{ "btst", 0xfee90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -/* end-sanitize-am33 */ -{ "btst", 0xfe020000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}}, -{ "btst", 0xfaf80000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8, AN0)}}, - -{ "bset", 0xf080, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, -{ "bset", 0xfe000000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}}, -{ "bset", 0xfaf00000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8, AN0)}}, - -{ "bclr", 0xf090, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, -{ "bclr", 0xfe010000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}}, -{ "bclr", 0xfaf40000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8,AN0)}}, - -/* start-sanitize-am33 */ -{ "asr", 0xfb4d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, -/* end-sanitize-am33 */ -{ "asr", 0xf2b0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "asr", 0xf8c800, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, -/* start-sanitize-am33 */ -{ "asr", 0xf94900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -{ "asr", 0xfb490000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, -{ "asr", 0xfd490000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, -{ "asr", 0xfe490000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -/* end-sanitize-am33 */ -{ "asr", 0xf8c801, 0xfffcff, 0, FMT_D1, 0, {DN0}}, -/* start-sanitize-am33 */ -{ "asr", 0xfb490001, 0xffff00ff, 0, FMT_D7, AM33, {RN02}}, -/* end-sanitize-am33 */ - -/* start-sanitize-am33 */ -{ "lsr", 0xfb5d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, -/* end-sanitize-am33 */ -{ "lsr", 0xf2a0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "lsr", 0xf8c400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, -/* start-sanitize-am33 */ -{ "lsr", 0xf95900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -{ "lsr", 0xfb590000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, -{ "lsr", 0xfd590000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, -{ "lsr", 0xfe590000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -/* end-sanitize-am33 */ -{ "lsr", 0xf8c401, 0xfffcff, 0, FMT_D1, 0, {DN0}}, -/* start-sanitize-am33 */ -{ "lsr", 0xfb590001, 0xffff00ff, 0, FMT_D7, AM33, {RN02}}, -/* end-sanitize-am33 */ - -/* start-sanitize-am33 */ -{ "asl", 0xfb6d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, -/* end-sanitize-am33 */ -{ "asl", 0xf290, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "asl", 0xf8c000, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, -/* start-sanitize-am33 */ -{ "asl", 0xf96900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -{ "asl", 0xfb690000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, -{ "asl", 0xfd690000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, -{ "asl", 0xfe690000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -/* end-sanitize-am33 */ -{ "asl", 0xf8c001, 0xfffcff, 0, FMT_D1, 0, {DN0}}, -/* start-sanitize-am33 */ -{ "asl", 0xfb690001, 0xffff00ff, 0, FMT_D7, AM33, {RN02}}, -/* end-sanitize-am33 */ - -{ "asl2", 0x54, 0xfc, 0, FMT_S0, 0, {DN0}}, -/* start-sanitize-am33 */ -{ "asl2", 0xf97900, 0xffff00, 0, FMT_D6, AM33, {RN02}}, -/* end-sanitize-am33 */ - -{ "ror", 0xf284, 0xfffc, 0, FMT_D0, 0, {DN0}}, -/* start-sanitize-am33 */ -{ "ror", 0xf98900, 0xffff00, 0, FMT_D6, AM33, {RN02}}, -/* end-sanitize-am33 */ - -{ "rol", 0xf280, 0xfffc, 0, FMT_D0, 0, {DN0}}, -/* start-sanitize-am33 */ -{ "rol", 0xf99900, 0xffff00, 0, FMT_D6, AM33, {RN02}}, -/* end-sanitize-am33 */ - -{ "beq", 0xc800, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, -{ "bne", 0xc900, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, -{ "bgt", 0xc100, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, -{ "bge", 0xc200, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, -{ "ble", 0xc300, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, -{ "blt", 0xc000, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, -{ "bhi", 0xc500, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, -{ "bcc", 0xc600, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, -{ "bls", 0xc700, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, -{ "bcs", 0xc400, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, -{ "bvc", 0xf8e800, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}}, -{ "bvs", 0xf8e900, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}}, -{ "bnc", 0xf8ea00, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}}, -{ "bns", 0xf8eb00, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}}, -{ "bra", 0xca00, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, - -{ "leq", 0xd8, 0xff, 0, FMT_S0, 0, {UNUSED}}, -{ "lne", 0xd9, 0xff, 0, FMT_S0, 0, {UNUSED}}, -{ "lgt", 0xd1, 0xff, 0, FMT_S0, 0, {UNUSED}}, -{ "lge", 0xd2, 0xff, 0, FMT_S0, 0, {UNUSED}}, -{ "lle", 0xd3, 0xff, 0, FMT_S0, 0, {UNUSED}}, -{ "llt", 0xd0, 0xff, 0, FMT_S0, 0, {UNUSED}}, -{ "lhi", 0xd5, 0xff, 0, FMT_S0, 0, {UNUSED}}, -{ "lcc", 0xd6, 0xff, 0, FMT_S0, 0, {UNUSED}}, -{ "lls", 0xd7, 0xff, 0, FMT_S0, 0, {UNUSED}}, -{ "lcs", 0xd4, 0xff, 0, FMT_S0, 0, {UNUSED}}, -{ "lra", 0xda, 0xff, 0, FMT_S0, 0, {UNUSED}}, -{ "setlb", 0xdb, 0xff, 0, FMT_S0, 0, {UNUSED}}, - -{ "jmp", 0xf0f4, 0xfffc, 0, FMT_D0, 0, {PAREN,AN0,PAREN}}, -{ "jmp", 0xcc0000, 0xff0000, 0, FMT_S2, 0, {IMM16_PCREL}}, -{ "jmp", 0xdc000000, 0xff000000, 0, FMT_S4, 0, {IMM32_HIGH24}}, -{ "call", 0xcd000000, 0xff000000, 0, FMT_S4, 0, {D16_SHIFT,REGS,IMM8E}}, -{ "call", 0xdd000000, 0xff000000, 0, FMT_S6, 0, {IMM32_HIGH24_LOWSHIFT16, REGSE_SHIFT8,IMM8E}}, -{ "calls", 0xf0f0, 0xfffc, 0, FMT_D0, 0, {PAREN,AN0,PAREN}}, -{ "calls", 0xfaff0000, 0xffff0000, 0, FMT_D2, 0, {IMM16_PCREL}}, -{ "calls", 0xfcff0000, 0xffff0000, 0, FMT_D4, 0, {IMM32_PCREL}}, - -{ "ret", 0xdf0000, 0xff0000, 0, FMT_S2, 0, {REGS_SHIFT8, IMM8}}, -{ "retf", 0xde0000, 0xff0000, 0, FMT_S2, 0, {REGS_SHIFT8, IMM8}}, -{ "rets", 0xf0fc, 0xffff, 0, FMT_D0, 0, {UNUSED}}, -{ "rti", 0xf0fd, 0xffff, 0, FMT_D0, 0, {UNUSED}}, -{ "trap", 0xf0fe, 0xffff, 0, FMT_D0, 0, {UNUSED}}, -{ "rtm", 0xf0ff, 0xffff, 0, FMT_D0, 0, {UNUSED}}, -{ "nop", 0xcb, 0xff, 0, FMT_S0, 0, {UNUSED}}, - -/* UDF instructions. */ -{ "udf00", 0xf600, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf00", 0xf90000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, -{ "udf00", 0xfb000000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, -{ "udf00", 0xfd000000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udf01", 0xf610, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf01", 0xf91000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, -{ "udf01", 0xfb100000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, -{ "udf01", 0xfd100000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udf02", 0xf620, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf02", 0xf92000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, -{ "udf02", 0xfb200000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, -{ "udf02", 0xfd200000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udf03", 0xf630, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf03", 0xf93000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, -{ "udf03", 0xfb300000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, -{ "udf03", 0xfd300000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udf04", 0xf640, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf04", 0xf94000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, -{ "udf04", 0xfb400000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, -{ "udf04", 0xfd400000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udf05", 0xf650, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf05", 0xf95000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, -{ "udf05", 0xfb500000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, -{ "udf05", 0xfd500000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udf06", 0xf660, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf06", 0xf96000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, -{ "udf06", 0xfb600000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, -{ "udf06", 0xfd600000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udf07", 0xf670, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf07", 0xf97000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, -{ "udf07", 0xfb700000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, -{ "udf07", 0xfd700000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udf08", 0xf680, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf08", 0xf98000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, -{ "udf08", 0xfb800000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, -{ "udf08", 0xfd800000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udf09", 0xf690, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf09", 0xf99000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, -{ "udf09", 0xfb900000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, -{ "udf09", 0xfd900000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udf10", 0xf6a0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf10", 0xf9a000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, -{ "udf10", 0xfba00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, -{ "udf10", 0xfda00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udf11", 0xf6b0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf11", 0xf9b000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, -{ "udf11", 0xfbb00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, -{ "udf11", 0xfdb00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udf12", 0xf6c0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf12", 0xf9c000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, -{ "udf12", 0xfbc00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, -{ "udf12", 0xfdc00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udf13", 0xf6d0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf13", 0xf9d000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, -{ "udf13", 0xfbd00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, -{ "udf13", 0xfdd00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udf14", 0xf6e0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf14", 0xf9e000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, -{ "udf14", 0xfbe00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, -{ "udf14", 0xfde00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udf15", 0xf6f0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf15", 0xf9f000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, -{ "udf15", 0xfbf00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, -{ "udf15", 0xfdf00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udf20", 0xf500, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf21", 0xf510, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf22", 0xf520, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf23", 0xf530, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf24", 0xf540, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf25", 0xf550, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf26", 0xf560, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf27", 0xf570, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf28", 0xf580, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf29", 0xf590, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf30", 0xf5a0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf31", 0xf5b0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf32", 0xf5c0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf33", 0xf5d0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf34", 0xf5e0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udf35", 0xf5f0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, -{ "udfu00", 0xf90400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, -{ "udfu00", 0xfb040000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, -{ "udfu00", 0xfd040000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udfu01", 0xf91400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, -{ "udfu01", 0xfb140000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, -{ "udfu01", 0xfd140000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udfu02", 0xf92400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, -{ "udfu02", 0xfb240000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, -{ "udfu02", 0xfd240000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udfu03", 0xf93400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, -{ "udfu03", 0xfb340000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, -{ "udfu03", 0xfd340000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udfu04", 0xf94400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, -{ "udfu04", 0xfb440000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, -{ "udfu04", 0xfd440000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udfu05", 0xf95400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, -{ "udfu05", 0xfb540000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, -{ "udfu05", 0xfd540000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udfu06", 0xf96400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, -{ "udfu06", 0xfb640000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, -{ "udfu06", 0xfd640000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udfu07", 0xf97400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, -{ "udfu07", 0xfb740000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, -{ "udfu07", 0xfd740000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udfu08", 0xf98400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, -{ "udfu08", 0xfb840000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, -{ "udfu08", 0xfd840000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udfu09", 0xf99400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, -{ "udfu09", 0xfb940000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, -{ "udfu09", 0xfd940000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udfu10", 0xf9a400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, -{ "udfu10", 0xfba40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, -{ "udfu10", 0xfda40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udfu11", 0xf9b400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, -{ "udfu11", 0xfbb40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, -{ "udfu11", 0xfdb40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udfu12", 0xf9c400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, -{ "udfu12", 0xfbc40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, -{ "udfu12", 0xfdc40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udfu13", 0xf9d400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, -{ "udfu13", 0xfbd40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, -{ "udfu13", 0xfdd40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udfu14", 0xf9e400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, -{ "udfu14", 0xfbe40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, -{ "udfu14", 0xfde40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, -{ "udfu15", 0xf9f400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, -{ "udfu15", 0xfbf40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, -{ "udfu15", 0xfdf40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, - -{ "putx", 0xf500, 0xfff0, 0, FMT_D0, AM30, {DN01}}, -{ "getx", 0xf6f0, 0xfff0, 0, FMT_D0, AM30, {DN01}}, -{ "mulq", 0xf600, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, -{ "mulq", 0xf90000, 0xfffc00, 0, FMT_D1, AM30, {SIMM8, DN0}}, -{ "mulq", 0xfb000000, 0xfffc0000, 0, FMT_D2, AM30, {SIMM16, DN0}}, -{ "mulq", 0xfd000000, 0xfffc0000, 0, FMT_D4, AM30, {IMM32, DN0}}, -{ "mulqu", 0xf610, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, -{ "mulqu", 0xf91400, 0xfffc00, 0, FMT_D1, AM30, {SIMM8, DN0}}, -{ "mulqu", 0xfb140000, 0xfffc0000, 0, FMT_D2, AM30, {SIMM16, DN0}}, -{ "mulqu", 0xfd140000, 0xfffc0000, 0, FMT_D4, AM30, {IMM32, DN0}}, -{ "sat16", 0xf640, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, -/* start-sanitize-am33 */ -{ "sat16", 0xf9ab00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -/* end-sanitize-am33 */ - -{ "sat24", 0xf650, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, -/* start-sanitize-am33 */ -{ "sat24", 0xfbaf0000, 0xffff00ff, 0, FMT_D7, AM33, {RM2, RN0}}, -/* end-sanitize-am33 */ - -/* start-sanitize-am33 */ -{ "bsch", 0xfbff0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, -/* end-sanitize-am33 */ -{ "bsch", 0xf670, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, -/* start-sanitize-am33 */ -{ "bsch", 0xf9fb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, -/* end-sanitize-am33 */ - -/* Extension. We need some instruction to trigger "emulated syscalls" - for our simulator. */ -/* start-sanitize-am33 */ -{ "syscall", 0xf0e0, 0xfff0, 0, FMT_D0, AM33, {IMM4}}, -/* end-sanitize-am33 */ -{ "syscall", 0xf0c0, 0xffff, 0, FMT_D0, 0, {UNUSED}}, - -/* Extension. When talking to the simulator, gdb requires some instruction - that will trigger a "breakpoint" (really just an instruction that isn't - otherwise used by the tools. This instruction must be the same size - as the smallest instruction on the target machine. In the case of the - mn10x00 the "break" instruction must be one byte. 0xff is available on - both mn10x00 architectures. */ -{ "break", 0xff, 0xff, 0, FMT_S0, 0, {UNUSED}}, - -/* start-sanitize-am33 */ -{ "add_add", 0xf7000000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "add_add", 0xf7100000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "add_add", 0xf7040000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "add_add", 0xf7140000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, -{ "add_sub", 0xf7200000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "add_sub", 0xf7300000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "add_sub", 0xf7240000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "add_sub", 0xf7340000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, -{ "add_cmp", 0xf7400000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "add_cmp", 0xf7500000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "add_cmp", 0xf7440000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "add_cmp", 0xf7540000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, -{ "add_mov", 0xf7600000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "add_mov", 0xf7700000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "add_mov", 0xf7640000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "add_mov", 0xf7740000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, -{ "add_asr", 0xf7800000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "add_asr", 0xf7900000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "add_asr", 0xf7840000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "add_asr", 0xf7940000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, -{ "add_lsr", 0xf7a00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "add_lsr", 0xf7b00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "add_lsr", 0xf7a40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "add_lsr", 0xf7b40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, -{ "add_asl", 0xf7c00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "add_asl", 0xf7d00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "add_asl", 0xf7c40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "add_asl", 0xf7d40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, -{ "cmp_add", 0xf7010000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "cmp_add", 0xf7110000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "cmp_add", 0xf7050000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "cmp_add", 0xf7150000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, -{ "cmp_sub", 0xf7210000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "cmp_sub", 0xf7310000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "cmp_sub", 0xf7250000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "cmp_sub", 0xf7350000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, -{ "cmp_mov", 0xf7610000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "cmp_mov", 0xf7710000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "cmp_mov", 0xf7650000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "cmp_mov", 0xf7750000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, -{ "cmp_asr", 0xf7810000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "cmp_asr", 0xf7910000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "cmp_asr", 0xf7850000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "cmp_asr", 0xf7950000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, -{ "cmp_lsr", 0xf7a10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "cmp_lsr", 0xf7b10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "cmp_lsr", 0xf7a50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "cmp_lsr", 0xf7b50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, -{ "cmp_asl", 0xf7c10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "cmp_asl", 0xf7d10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "cmp_asl", 0xf7c50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "cmp_asl", 0xf7d50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, -{ "sub_add", 0xf7020000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "sub_add", 0xf7120000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "sub_add", 0xf7060000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "sub_add", 0xf7160000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, -{ "sub_sub", 0xf7220000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "sub_sub", 0xf7320000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "sub_sub", 0xf7260000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "sub_sub", 0xf7360000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, -{ "sub_cmp", 0xf7420000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "sub_cmp", 0xf7520000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "sub_cmp", 0xf7460000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "sub_cmp", 0xf7560000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, -{ "sub_mov", 0xf7620000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "sub_mov", 0xf7720000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "sub_mov", 0xf7660000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "sub_mov", 0xf7760000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, -{ "sub_asr", 0xf7820000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "sub_asr", 0xf7920000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "sub_asr", 0xf7860000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "sub_asr", 0xf7960000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, -{ "sub_lsr", 0xf7a20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "sub_lsr", 0xf7b20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "sub_lsr", 0xf7a60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "sub_lsr", 0xf7b60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, -{ "sub_asl", 0xf7c20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "sub_asl", 0xf7d20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "sub_asl", 0xf7c60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "sub_asl", 0xf7d60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, -{ "mov_add", 0xf7030000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "mov_add", 0xf7130000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "mov_add", 0xf7070000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "mov_add", 0xf7170000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, -{ "mov_sub", 0xf7230000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "mov_sub", 0xf7330000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "mov_sub", 0xf7270000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "mov_sub", 0xf7370000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, -{ "mov_cmp", 0xf7430000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "mov_cmp", 0xf7530000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "mov_cmp", 0xf7470000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "mov_cmp", 0xf7570000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, -{ "mov_mov", 0xf7630000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "mov_mov", 0xf7730000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "mov_mov", 0xf7670000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "mov_mov", 0xf7770000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, -{ "mov_asr", 0xf7830000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "mov_asr", 0xf7930000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "mov_asr", 0xf7870000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "mov_asr", 0xf7970000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, -{ "mov_lsr", 0xf7a30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "mov_lsr", 0xf7b30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "mov_lsr", 0xf7a70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "mov_lsr", 0xf7b70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, -{ "mov_asl", 0xf7c30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "mov_asl", 0xf7d30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "mov_asl", 0xf7c70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, -{ "mov_asl", 0xf7d70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, -{ "and_add", 0xf7080000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "and_add", 0xf7180000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "and_sub", 0xf7280000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "and_sub", 0xf7380000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "and_cmp", 0xf7480000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "and_cmp", 0xf7580000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "and_mov", 0xf7680000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "and_mov", 0xf7780000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "and_asr", 0xf7880000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "and_asr", 0xf7980000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "and_lsr", 0xf7a80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "and_lsr", 0xf7b80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "and_asl", 0xf7c80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "and_asl", 0xf7d80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "dmach_add", 0xf7090000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "dmach_add", 0xf7190000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "dmach_sub", 0xf7290000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "dmach_sub", 0xf7390000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "dmach_cmp", 0xf7490000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "dmach_cmp", 0xf7590000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "dmach_mov", 0xf7690000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "dmach_mov", 0xf7790000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "dmach_asr", 0xf7890000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "dmach_asr", 0xf7990000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "dmach_lsr", 0xf7a90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "dmach_lsr", 0xf7b90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "dmach_asl", 0xf7c90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "dmach_asl", 0xf7d90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "xor_add", 0xf70a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "xor_add", 0xf71a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "xor_sub", 0xf72a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "xor_sub", 0xf73a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "xor_cmp", 0xf74a0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "xor_cmp", 0xf75a0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "xor_mov", 0xf76a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "xor_mov", 0xf77a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "xor_asr", 0xf78a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "xor_asr", 0xf79a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "xor_lsr", 0xf7aa0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "xor_lsr", 0xf7ba0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "xor_asl", 0xf7ca0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "xor_asl", 0xf7da0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "swhw_add", 0xf70b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "swhw_add", 0xf71b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "swhw_sub", 0xf72b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "swhw_sub", 0xf73b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "swhw_cmp", 0xf74b0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "swhw_cmp", 0xf75b0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "swhw_mov", 0xf76b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "swhw_mov", 0xf77b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "swhw_asr", 0xf78b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "swhw_asr", 0xf79b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "swhw_lsr", 0xf7ab0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "swhw_lsr", 0xf7bb0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "swhw_asl", 0xf7cb0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "swhw_asl", 0xf7db0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "or_add", 0xf70c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "or_add", 0xf71c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "or_sub", 0xf72c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "or_sub", 0xf73c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "or_cmp", 0xf74c0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "or_cmp", 0xf75c0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "or_mov", 0xf76c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "or_mov", 0xf77c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "or_asr", 0xf78c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "or_asr", 0xf79c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "or_lsr", 0xf7ac0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "or_lsr", 0xf7bc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "or_asl", 0xf7cc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "or_asl", 0xf7dc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "sat16_add", 0xf70d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "sat16_add", 0xf71d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "sat16_sub", 0xf72d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "sat16_sub", 0xf73d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "sat16_cmp", 0xf74d0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "sat16_cmp", 0xf75d0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "sat16_mov", 0xf76d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "sat16_mov", 0xf77d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, -{ "sat16_asr", 0xf78d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "sat16_asr", 0xf79d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "sat16_lsr", 0xf7ad0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "sat16_lsr", 0xf7bd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -{ "sat16_asl", 0xf7cd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, -{ "sat16_asl", 0xf7dd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, -/* Ugh. Synthetic instructions. */ -{ "add_and", 0xf7080000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "add_and", 0xf7180000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, -{ "add_dmach", 0xf7090000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "add_dmach", 0xf7190000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, -{ "add_or", 0xf70c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "add_or", 0xf71c0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, -{ "add_sat16", 0xf70d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "add_sat16", 0xf71d0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, -{ "add_swhw", 0xf70b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "add_swhw", 0xf71b0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, -{ "add_xor", 0xf70a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "add_xor", 0xf71a0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, -{ "asl_add", 0xf7c00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "asl_add", 0xf7d00000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "asl_add", 0xf7c40000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, -{ "asl_add", 0xf7d40000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, -{ "asl_and", 0xf7c80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "asl_and", 0xf7d80000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "asl_cmp", 0xf7c10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "asl_cmp", 0xf7d10000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4, }}, -{ "asl_cmp", 0xf7c50000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, -{ "asl_cmp", 0xf7d50000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, -{ "asl_dmach", 0xf7c90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "asl_dmach", 0xf7d90000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "asl_mov", 0xf7c30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "asl_mov", 0xf7d30000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "asl_mov", 0xf7c70000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, -{ "asl_mov", 0xf7d70000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, -{ "asl_or", 0xf7cc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "asl_or", 0xf7dc0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "asl_sat16", 0xf7cd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "asl_sat16", 0xf7dd0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "asl_sub", 0xf7c20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "asl_sub", 0xf7d20000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "asl_sub", 0xf7c60000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, -{ "asl_sub", 0xf7d60000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, -{ "asl_swhw", 0xf7cb0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "asl_swhw", 0xf7db0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "asl_xor", 0xf7ca0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "asl_xor", 0xf7da0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "asr_add", 0xf7800000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "asr_add", 0xf7900000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "asr_add", 0xf7840000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, -{ "asr_add", 0xf7940000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, -{ "asr_and", 0xf7880000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "asr_and", 0xf7980000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "asr_cmp", 0xf7810000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "asr_cmp", 0xf7910000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4, }}, -{ "asr_cmp", 0xf7850000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, -{ "asr_cmp", 0xf7950000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, -{ "asr_dmach", 0xf7890000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "asr_dmach", 0xf7990000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "asr_mov", 0xf7830000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "asr_mov", 0xf7930000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "asr_mov", 0xf7870000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, -{ "asr_mov", 0xf7970000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, -{ "asr_or", 0xf78c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "asr_or", 0xf79c0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "asr_sat16", 0xf78d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "asr_sat16", 0xf79d0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "asr_sub", 0xf7820000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "asr_sub", 0xf7920000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "asr_sub", 0xf7860000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, -{ "asr_sub", 0xf7960000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, -{ "asr_swhw", 0xf78b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "asr_swhw", 0xf79b0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "asr_xor", 0xf78a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "asr_xor", 0xf79a0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "cmp_and", 0xf7480000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "cmp_and", 0xf7580000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, -{ "cmp_dmach", 0xf7490000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "cmp_dmach", 0xf7590000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, -{ "cmp_or", 0xf74c0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "cmp_or", 0xf75c0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, -{ "cmp_sat16", 0xf74d0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "cmp_sat16", 0xf75d0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, -{ "cmp_swhw", 0xf74b0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "cmp_swhw", 0xf75b0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, -{ "cmp_xor", 0xf74a0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "cmp_xor", 0xf75a0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, -{ "lsr_add", 0xf7a00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "lsr_add", 0xf7b00000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "lsr_add", 0xf7a40000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, -{ "lsr_add", 0xf7b40000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, -{ "lsr_and", 0xf7a80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "lsr_and", 0xf7b80000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "lsr_cmp", 0xf7a10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "lsr_cmp", 0xf7b10000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4, }}, -{ "lsr_cmp", 0xf7a50000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, -{ "lsr_cmp", 0xf7b50000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, -{ "lsr_dmach", 0xf7a90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "lsr_dmach", 0xf7b90000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "lsr_mov", 0xf7a30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "lsr_mov", 0xf7b30000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "lsr_mov", 0xf7a70000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, -{ "lsr_mov", 0xf7b70000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, -{ "lsr_or", 0xf7ac0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "lsr_or", 0xf7bc0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "lsr_sat16", 0xf7ad0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "lsr_sat16", 0xf7bd0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "lsr_sub", 0xf7a20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "lsr_sub", 0xf7b20000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "lsr_sub", 0xf7a60000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, -{ "lsr_sub", 0xf7b60000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, -{ "lsr_swhw", 0xf7ab0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "lsr_swhw", 0xf7bb0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "lsr_xor", 0xf7aa0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "lsr_xor", 0xf7ba0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, -{ "mov_and", 0xf7680000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "mov_and", 0xf7780000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, -{ "mov_dmach", 0xf7690000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "mov_dmach", 0xf7790000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, -{ "mov_or", 0xf76c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "mov_or", 0xf77c0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, -{ "mov_sat16", 0xf76d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "mov_sat16", 0xf77d0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, -{ "mov_swhw", 0xf76b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "mov_swhw", 0xf77b0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, -{ "mov_xor", 0xf76a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "mov_xor", 0xf77a0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, -{ "sub_and", 0xf7280000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "sub_and", 0xf7380000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, -{ "sub_dmach", 0xf7290000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "sub_dmach", 0xf7390000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, -{ "sub_or", 0xf72c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "sub_or", 0xf73c0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, -{ "sub_sat16", 0xf72d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "sub_sat16", 0xf73d0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, -{ "sub_swhw", 0xf72b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "sub_swhw", 0xf73b0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, -{ "sub_xor", 0xf72a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, -{ "sub_xor", 0xf73a0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, -{ "mov_llt", 0xf7e00000, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "mov_lgt", 0xf7e00001, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "mov_lge", 0xf7e00002, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "mov_lle", 0xf7e00003, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "mov_lcs", 0xf7e00004, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "mov_lhi", 0xf7e00005, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "mov_lcc", 0xf7e00006, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "mov_lls", 0xf7e00007, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "mov_leq", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "mov_lne", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "mov_lra", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "llt_mov", 0xf7e00000, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "lgt_mov", 0xf7e00001, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "lge_mov", 0xf7e00002, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "lle_mov", 0xf7e00003, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "lcs_mov", 0xf7e00004, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "lhi_mov", 0xf7e00005, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "lcc_mov", 0xf7e00006, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "lls_mov", 0xf7e00007, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "leq_mov", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "lne_mov", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -{ "lra_mov", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, -/* end-sanitize-am33 */ - -{ 0, 0, 0, 0, 0, 0, {0}}, - -} ; - -const int mn10300_num_opcodes = - sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]); - - diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c deleted file mode 100644 index 6d77db05597..00000000000 --- a/opcodes/m32r-asm.c +++ /dev/null @@ -1,962 +0,0 @@ -/* Assembler interface for targets using CGEN. -*- C -*- - CGEN: Cpu tools GENerator - -THIS FILE IS USED TO GENERATE m32r-asm.c. - -Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. - -This file is part of the GNU Binutils and GDB, the GNU debugger. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include <ctype.h> -#include <stdio.h> -#include "ansidecl.h" -#include "bfd.h" -#include "symcat.h" -#include "m32r-opc.h" -#include "opintl.h" - -#undef min -#define min(a,b) ((a) < (b) ? (a) : (b)) -#undef max -#define max(a,b) ((a) > (b) ? (a) : (b)) - -#undef INLINE -#ifdef __GNUC__ -#define INLINE __inline__ -#else -#define INLINE -#endif - -/* Used by the ifield rtx function. */ -#define FLD(f) (fields->f) - -static const char * insert_normal - PARAMS ((CGEN_OPCODE_DESC, long, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); -static const char * parse_insn_normal - PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *, - const char **, CGEN_FIELDS *)); -static const char * insert_insn_normal - PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *, - CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); - -/* -- assembler routines inserted here */ -/* -- asm.c */ - -/* Handle '#' prefixes (i.e. skip over them). */ - -static const char * -parse_hash (od, strp, opindex, valuep) - CGEN_OPCODE_DESC od; - const char **strp; - int opindex; - unsigned long *valuep; -{ - if (**strp == '#') - ++*strp; - return NULL; -} - -/* Handle shigh(), high(). */ - -static const char * -parse_hi16 (od, strp, opindex, valuep) - CGEN_OPCODE_DESC od; - const char **strp; - int opindex; - unsigned long *valuep; -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - if (**strp == '#') - ++*strp; - - if (strncasecmp (*strp, "high(", 5) == 0) - { - *strp += 5; - errmsg = cgen_parse_address (od, strp, opindex, BFD_RELOC_M32R_HI16_ULO, - &result_type, &value); - if (**strp != ')') - return "missing `)'"; - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value >>= 16; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp, "shigh(", 6) == 0) - { - *strp += 6; - errmsg = cgen_parse_address (od, strp, opindex, BFD_RELOC_M32R_HI16_SLO, - &result_type, &value); - if (**strp != ')') - return "missing `)'"; - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value = (value >> 16) + (value & 0x8000 ? 1 : 0); - *valuep = value; - return errmsg; - } - - return cgen_parse_unsigned_integer (od, strp, opindex, valuep); -} - -/* Handle low() in a signed context. Also handle sda(). - The signedness of the value doesn't matter to low(), but this also - handles the case where low() isn't present. */ - -static const char * -parse_slo16 (od, strp, opindex, valuep) - CGEN_OPCODE_DESC od; - const char **strp; - int opindex; - long *valuep; -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - if (**strp == '#') - ++*strp; - - if (strncasecmp (*strp, "low(", 4) == 0) - { - *strp += 4; - errmsg = cgen_parse_address (od, strp, opindex, BFD_RELOC_M32R_LO16, - &result_type, &value); - if (**strp != ')') - return "missing `)'"; - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value &= 0xffff; - *valuep = value; - return errmsg; - } - - if (strncasecmp (*strp, "sda(", 4) == 0) - { - *strp += 4; - errmsg = cgen_parse_address (od, strp, opindex, BFD_RELOC_M32R_SDA16, - NULL, &value); - if (**strp != ')') - return "missing `)'"; - ++*strp; - *valuep = value; - return errmsg; - } - - return cgen_parse_signed_integer (od, strp, opindex, valuep); -} - -/* Handle low() in an unsigned context. - The signedness of the value doesn't matter to low(), but this also - handles the case where low() isn't present. */ - -static const char * -parse_ulo16 (od, strp, opindex, valuep) - CGEN_OPCODE_DESC od; - const char **strp; - int opindex; - unsigned long *valuep; -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - if (**strp == '#') - ++*strp; - - if (strncasecmp (*strp, "low(", 4) == 0) - { - *strp += 4; - errmsg = cgen_parse_address (od, strp, opindex, BFD_RELOC_M32R_LO16, - &result_type, &value); - if (**strp != ')') - return "missing `)'"; - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value &= 0xffff; - *valuep = value; - return errmsg; - } - - return cgen_parse_unsigned_integer (od, strp, opindex, valuep); -} - -/* -- */ - -/* Main entry point for operand parsing. - - This function is basically just a big switch statement. Earlier versions - used tables to look up the function to use, but - - if the table contains both assembler and disassembler functions then - the disassembler contains much of the assembler and vice-versa, - - there's a lot of inlining possibilities as things grow, - - using a switch statement avoids the function call overhead. - - This function could be moved into `parse_insn_normal', but keeping it - separate makes clear the interface between `parse_insn_normal' and each of - the handlers. -*/ - -const char * -m32r_cgen_parse_operand (od, opindex, strp, fields) - CGEN_OPCODE_DESC od; - int opindex; - const char ** strp; - CGEN_FIELDS * fields; -{ - const char * errmsg; - - switch (opindex) - { - case M32R_OPERAND_SR : - errmsg = cgen_parse_keyword (od, strp, & m32r_cgen_opval_h_gr, & fields->f_r2); - break; - case M32R_OPERAND_DR : - errmsg = cgen_parse_keyword (od, strp, & m32r_cgen_opval_h_gr, & fields->f_r1); - break; - case M32R_OPERAND_SRC1 : - errmsg = cgen_parse_keyword (od, strp, & m32r_cgen_opval_h_gr, & fields->f_r1); - break; - case M32R_OPERAND_SRC2 : - errmsg = cgen_parse_keyword (od, strp, & m32r_cgen_opval_h_gr, & fields->f_r2); - break; - case M32R_OPERAND_SCR : - errmsg = cgen_parse_keyword (od, strp, & m32r_cgen_opval_h_cr, & fields->f_r2); - break; - case M32R_OPERAND_DCR : - errmsg = cgen_parse_keyword (od, strp, & m32r_cgen_opval_h_cr, & fields->f_r1); - break; - case M32R_OPERAND_SIMM8 : - errmsg = cgen_parse_signed_integer (od, strp, M32R_OPERAND_SIMM8, &fields->f_simm8); - break; - case M32R_OPERAND_SIMM16 : - errmsg = cgen_parse_signed_integer (od, strp, M32R_OPERAND_SIMM16, &fields->f_simm16); - break; - case M32R_OPERAND_UIMM4 : - errmsg = cgen_parse_unsigned_integer (od, strp, M32R_OPERAND_UIMM4, &fields->f_uimm4); - break; - case M32R_OPERAND_UIMM5 : - errmsg = cgen_parse_unsigned_integer (od, strp, M32R_OPERAND_UIMM5, &fields->f_uimm5); - break; - case M32R_OPERAND_UIMM16 : - errmsg = cgen_parse_unsigned_integer (od, strp, M32R_OPERAND_UIMM16, &fields->f_uimm16); - break; -/* start-sanitize-m32rx */ - case M32R_OPERAND_IMM1 : - errmsg = cgen_parse_unsigned_integer (od, strp, M32R_OPERAND_IMM1, &fields->f_imm1); - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACCD : - errmsg = cgen_parse_keyword (od, strp, & m32r_cgen_opval_h_accums, & fields->f_accd); - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACCS : - errmsg = cgen_parse_keyword (od, strp, & m32r_cgen_opval_h_accums, & fields->f_accs); - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACC : - errmsg = cgen_parse_keyword (od, strp, & m32r_cgen_opval_h_accums, & fields->f_acc); - break; -/* end-sanitize-m32rx */ - case M32R_OPERAND_HASH : - errmsg = parse_hash (od, strp, M32R_OPERAND_HASH, &fields->f_nil); - break; - case M32R_OPERAND_HI16 : - errmsg = parse_hi16 (od, strp, M32R_OPERAND_HI16, &fields->f_hi16); - break; - case M32R_OPERAND_SLO16 : - errmsg = parse_slo16 (od, strp, M32R_OPERAND_SLO16, &fields->f_simm16); - break; - case M32R_OPERAND_ULO16 : - errmsg = parse_ulo16 (od, strp, M32R_OPERAND_ULO16, &fields->f_uimm16); - break; - case M32R_OPERAND_UIMM24 : - { - bfd_vma value; - errmsg = cgen_parse_address (od, strp, M32R_OPERAND_UIMM24, 0, NULL, & value); - fields->f_uimm24 = value; - } - break; - case M32R_OPERAND_DISP8 : - { - bfd_vma value; - errmsg = cgen_parse_address (od, strp, M32R_OPERAND_DISP8, 0, NULL, & value); - fields->f_disp8 = value; - } - break; - case M32R_OPERAND_DISP16 : - { - bfd_vma value; - errmsg = cgen_parse_address (od, strp, M32R_OPERAND_DISP16, 0, NULL, & value); - fields->f_disp16 = value; - } - break; - case M32R_OPERAND_DISP24 : - { - bfd_vma value; - errmsg = cgen_parse_address (od, strp, M32R_OPERAND_DISP24, 0, NULL, & value); - fields->f_disp24 = value; - } - break; - - default : - /* xgettext:c-format */ - fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); - abort (); - } - - return errmsg; -} - -/* Main entry point for operand insertion. - - This function is basically just a big switch statement. Earlier versions - used tables to look up the function to use, but - - if the table contains both assembler and disassembler functions then - the disassembler contains much of the assembler and vice-versa, - - there's a lot of inlining possibilities as things grow, - - using a switch statement avoids the function call overhead. - - This function could be moved into `parse_insn_normal', but keeping it - separate makes clear the interface between `parse_insn_normal' and each of - the handlers. It's also needed by GAS to insert operands that couldn't be - resolved during parsing. -*/ - -const char * -m32r_cgen_insert_operand (od, opindex, fields, buffer, pc) - CGEN_OPCODE_DESC od; - int opindex; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc; -{ - const char * errmsg; - unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); - - switch (opindex) - { - case M32R_OPERAND_SR : - errmsg = insert_normal (od, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 32, total_length, buffer); - break; - case M32R_OPERAND_DR : - errmsg = insert_normal (od, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 4, 32, total_length, buffer); - break; - case M32R_OPERAND_SRC1 : - errmsg = insert_normal (od, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 4, 32, total_length, buffer); - break; - case M32R_OPERAND_SRC2 : - errmsg = insert_normal (od, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 32, total_length, buffer); - break; - case M32R_OPERAND_SCR : - errmsg = insert_normal (od, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 32, total_length, buffer); - break; - case M32R_OPERAND_DCR : - errmsg = insert_normal (od, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 4, 32, total_length, buffer); - break; - case M32R_OPERAND_SIMM8 : - errmsg = insert_normal (od, fields->f_simm8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 8, 8, 32, total_length, buffer); - break; - case M32R_OPERAND_SIMM16 : - errmsg = insert_normal (od, fields->f_simm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 16, 16, 32, total_length, buffer); - break; - case M32R_OPERAND_UIMM4 : - errmsg = insert_normal (od, fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 32, total_length, buffer); - break; - case M32R_OPERAND_UIMM5 : - errmsg = insert_normal (od, fields->f_uimm5, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 11, 5, 32, total_length, buffer); - break; - case M32R_OPERAND_UIMM16 : - errmsg = insert_normal (od, fields->f_uimm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 16, 16, 32, total_length, buffer); - break; -/* start-sanitize-m32rx */ - case M32R_OPERAND_IMM1 : - { - long value = fields->f_imm1; - value = ((value) - (1)); - errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 15, 1, 32, total_length, buffer); - } - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACCD : - errmsg = insert_normal (od, fields->f_accd, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 2, 32, total_length, buffer); - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACCS : - errmsg = insert_normal (od, fields->f_accs, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 2, 32, total_length, buffer); - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACC : - errmsg = insert_normal (od, fields->f_acc, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 1, 32, total_length, buffer); - break; -/* end-sanitize-m32rx */ - case M32R_OPERAND_HASH : - errmsg = insert_normal (od, fields->f_nil, 0, 0, 0, 0, 0, total_length, buffer); - break; - case M32R_OPERAND_HI16 : - errmsg = insert_normal (od, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 0, 16, 16, 32, total_length, buffer); - break; - case M32R_OPERAND_SLO16 : - errmsg = insert_normal (od, fields->f_simm16, 0, 0, 16, 16, 32, total_length, buffer); - break; - case M32R_OPERAND_ULO16 : - errmsg = insert_normal (od, fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 16, 16, 32, total_length, buffer); - break; - case M32R_OPERAND_UIMM24 : - errmsg = insert_normal (od, fields->f_uimm24, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 24, 32, total_length, buffer); - break; - case M32R_OPERAND_DISP8 : - { - long value = fields->f_disp8; - value = ((int) (((value) - (((pc) & (-4))))) >> (2)); - errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 8, 8, 32, total_length, buffer); - } - break; - case M32R_OPERAND_DISP16 : - { - long value = fields->f_disp16; - value = ((int) (((value) - (pc))) >> (2)); - errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 16, 16, 32, total_length, buffer); - } - break; - case M32R_OPERAND_DISP24 : - { - long value = fields->f_disp24; - value = ((int) (((value) - (pc))) >> (2)); - errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 8, 24, 32, total_length, buffer); - } - break; - - default : - /* xgettext:c-format */ - fprintf (stderr, _("Unrecognized field %d while building insn.\n"), - opindex); - abort (); - } - - return errmsg; -} - -cgen_parse_fn * const m32r_cgen_parse_handlers[] = -{ - 0, /* default */ - parse_insn_normal, -}; - -cgen_insert_fn * const m32r_cgen_insert_handlers[] = -{ - 0, /* default */ - insert_insn_normal, -}; - -void -m32r_cgen_init_asm (od) - CGEN_OPCODE_DESC od; -{ -} - - -#if ! CGEN_INT_INSN_P - -/* Subroutine of insert_normal. */ - -static INLINE void -insert_1 (od, value, start, length, word_length, bufp) - CGEN_OPCODE_DESC od; - unsigned long value; - int start,length,word_length; - unsigned char *bufp; -{ - unsigned long x,mask; - int shift; - int big_p = CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG; - - switch (word_length) - { - case 8: - x = *bufp; - break; - case 16: - if (big_p) - x = bfd_getb16 (bufp); - else - x = bfd_getl16 (bufp); - break; - case 24: - /* ??? This may need reworking as these cases don't necessarily - want the first byte and the last two bytes handled like this. */ - if (big_p) - x = (bufp[0] << 16) | bfd_getb16 (bufp + 1); - else - x = bfd_getl16 (bufp) | (bufp[2] << 16); - break; - case 32: - if (big_p) - x = bfd_getb32 (bufp); - else - x = bfd_getl32 (bufp); - break; - default : - abort (); - } - - /* Written this way to avoid undefined behaviour. */ - mask = (((1L << (length - 1)) - 1) << 1) | 1; - if (CGEN_INSN_LSB0_P) - shift = (start + 1) - length; - else - shift = (word_length - (start + length)); - x = (x & ~(mask << shift)) | ((value & mask) << shift); - - switch (word_length) - { - case 8: - *bufp = x; - break; - case 16: - if (big_p) - bfd_putb16 (x, bufp); - else - bfd_putl16 (x, bufp); - break; - case 24: - /* ??? This may need reworking as these cases don't necessarily - want the first byte and the last two bytes handled like this. */ - if (big_p) - { - bufp[0] = x >> 16; - bfd_putb16 (x, bufp + 1); - } - else - { - bfd_putl16 (x, bufp); - bufp[2] = x >> 16; - } - break; - case 32: - if (big_p) - bfd_putb32 (x, bufp); - else - bfd_putl32 (x, bufp); - break; - default : - abort (); - } -} - -#endif /* ! CGEN_INT_INSN_P */ - -/* Default insertion routine. - - ATTRS is a mask of the boolean attributes. - WORD_OFFSET is the offset in bits from the start of the insn of the value. - WORD_LENGTH is the length of the word in bits in which the value resides. - START is the starting bit number in the word, architecture origin. - LENGTH is the length of VALUE in bits. - TOTAL_LENGTH is the total length of the insn in bits. - - The result is an error message or NULL if success. */ - -/* ??? This duplicates functionality with bfd's howto table and - bfd_install_relocation. */ -/* ??? This doesn't handle bfd_vma's. Create another function when - necessary. */ - -static const char * -insert_normal (od, value, attrs, word_offset, start, length, word_length, - total_length, buffer) - CGEN_OPCODE_DESC od; - long value; - unsigned int attrs; - unsigned int word_offset, start, length, word_length, total_length; - CGEN_INSN_BYTES_PTR buffer; -{ - static char errbuf[100]; - /* Written this way to avoid undefined behaviour. */ - unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; - - /* If LENGTH is zero, this operand doesn't contribute to the value. */ - if (length == 0) - return NULL; - - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); - - if (word_length > 32) - abort (); - - /* For architectures with insns smaller than the insn-base-bitsize, - word_length may be too big. */ -#if CGEN_MIN_INSN_BITSIZE < CGEN_BASE_INSN_BITSIZE - if (word_offset == 0 - && word_length > total_length) - word_length = total_length; -#endif - - /* Ensure VALUE will fit. */ - if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED)) - { - unsigned long maxval = mask; - if ((unsigned long) value > maxval) - { - /* xgettext:c-format */ - sprintf (errbuf, - _("operand out of range (%lu not between 0 and %lu)"), - value, maxval); - return errbuf; - } - } - else - { - long minval = - (1L << (length - 1)); - long maxval = (1L << (length - 1)) - 1; - if (value < minval || value > maxval) - { - sprintf - /* xgettext:c-format */ - (errbuf, _("operand out of range (%ld not between %ld and %ld)"), - value, minval, maxval); - return errbuf; - } - } - -#if CGEN_INT_INSN_P - - { - int shift; - - if (CGEN_INSN_LSB0_P) - shift = (start + 1) - length; - else - shift = word_length - (start + length); - *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); - } - -#else /* ! CGEN_INT_INSN_P */ - - { - unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; - - insert_1 (od, value, start, length, word_length, bufp); - } - -#endif /* ! CGEN_INT_INSN_P */ - - return NULL; -} - -/* Default insn parser. - - The syntax string is scanned and operands are parsed and stored in FIELDS. - Relocs are queued as we go via other callbacks. - - ??? Note that this is currently an all-or-nothing parser. If we fail to - parse the instruction, we return 0 and the caller will start over from - the beginning. Backtracking will be necessary in parsing subexpressions, - but that can be handled there. Not handling backtracking here may get - expensive in the case of the m68k. Deal with later. - - Returns NULL for success, an error message for failure. -*/ - -static const char * -parse_insn_normal (od, insn, strp, fields) - CGEN_OPCODE_DESC od; - const CGEN_INSN * insn; - const char ** strp; - CGEN_FIELDS * fields; -{ - const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn); - const char * str = *strp; - const char * errmsg; - const char * p; - const unsigned char * syn; -#ifdef CGEN_MNEMONIC_OPERANDS - /* FIXME: wip */ - int past_opcode_p; -#endif - - /* For now we assume the mnemonic is first (there are no leading operands). - We can parse it without needing to set up operand parsing. - GAS's input scrubber will ensure mnemonics are lowercase, but we may - not be called from GAS. */ - p = CGEN_INSN_MNEMONIC (insn); - while (*p && tolower (*p) == tolower (*str)) - ++p, ++str; - - if (* p || (* str && !isspace (* str))) - return _("unrecognized instruction"); - - CGEN_INIT_PARSE (od); - cgen_init_parse_operand (od); -#ifdef CGEN_MNEMONIC_OPERANDS - past_opcode_p = 0; -#endif - - /* We don't check for (*str != '\0') here because we want to parse - any trailing fake arguments in the syntax string. */ - syn = CGEN_SYNTAX_STRING (syntax); - - /* Mnemonics come first for now, ensure valid string. */ - if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) - abort (); - - ++syn; - - while (* syn != 0) - { - /* Non operand chars must match exactly. */ - if (CGEN_SYNTAX_CHAR_P (* syn)) - { - if (*str == CGEN_SYNTAX_CHAR (* syn)) - { -#ifdef CGEN_MNEMONIC_OPERANDS - if (* syn == ' ') - past_opcode_p = 1; -#endif - ++ syn; - ++ str; - } - else - { - /* Syntax char didn't match. Can't be this insn. */ - /* FIXME: would like to return something like - "expected char `c'" */ - return _("syntax error"); - } - continue; - } - - /* We have an operand of some sort. */ - errmsg = m32r_cgen_parse_operand (od, CGEN_SYNTAX_FIELD (*syn), - &str, fields); - if (errmsg) - return errmsg; - - /* Done with this operand, continue with next one. */ - ++ syn; - } - - /* If we're at the end of the syntax string, we're done. */ - if (* syn == '\0') - { - /* FIXME: For the moment we assume a valid `str' can only contain - blanks now. IE: We needn't try again with a longer version of - the insn and it is assumed that longer versions of insns appear - before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ - while (isspace (* str)) - ++ str; - - if (* str != '\0') - return _("junk at end of line"); /* FIXME: would like to include `str' */ - - return NULL; - } - - /* We couldn't parse it. */ - return _("unrecognized instruction"); -} - -/* Default insn builder (insert handler). - The instruction is recorded in CGEN_INT_INSN_P byte order - (meaning that if CGEN_INT_INSN_P BUFFER is an int * and thus the value is - recorded in host byte order, otherwise BUFFER is an array of bytes and the - value is recorded in target byte order). - The result is an error message or NULL if success. */ - -static const char * -insert_insn_normal (od, insn, fields, buffer, pc) - CGEN_OPCODE_DESC od; - const CGEN_INSN * insn; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc; -{ - const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn); - unsigned long value; - const unsigned char * syn; - - CGEN_INIT_INSERT (od); - value = CGEN_INSN_BASE_VALUE (insn); - - /* If we're recording insns as numbers (rather than a string of bytes), - target byte order handling is deferred until later. */ - -#if CGEN_INT_INSN_P - - *buffer = value; - -#else - - cgen_put_insn_value (od, buffer, min (CGEN_BASE_INSN_BITSIZE, - CGEN_FIELDS_BITSIZE (fields)), - value); - -#endif /* ! CGEN_INT_INSN_P */ - - /* ??? It would be better to scan the format's fields. - Still need to be able to insert a value based on the operand though; - e.g. storing a branch displacement that got resolved later. - Needs more thought first. */ - - for (syn = CGEN_SYNTAX_STRING (syntax); * syn != '\0'; ++ syn) - { - const char *errmsg; - - if (CGEN_SYNTAX_CHAR_P (* syn)) - continue; - - errmsg = m32r_cgen_insert_operand (od, CGEN_SYNTAX_FIELD (*syn), - fields, buffer, pc); - if (errmsg) - return errmsg; - } - - return NULL; -} - -/* Main entry point. - This routine is called for each instruction to be assembled. - STR points to the insn to be assembled. - We assume all necessary tables have been initialized. - The assembled instruction, less any fixups, is stored in BUF. - Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value - still needs to be converted to target byte order, otherwise BUF is an array - of bytes in target byte order. - The result is a pointer to the insn's entry in the opcode table, - or NULL if an error occured (an error message will have already been - printed). - - Note that when processing (non-alias) macro-insns, - this function recurses. */ - -const CGEN_INSN * -m32r_cgen_assemble_insn (od, str, fields, buf, errmsg) - CGEN_OPCODE_DESC od; - const char * str; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buf; - char ** errmsg; -{ - const char * start; - CGEN_INSN_LIST * ilist; - - /* Skip leading white space. */ - while (isspace (* str)) - ++ str; - - /* The instructions are stored in hashed lists. - Get the first in the list. */ - ilist = CGEN_ASM_LOOKUP_INSN (od, str); - - /* Keep looking until we find a match. */ - - start = str; - for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) - { - const CGEN_INSN *insn = ilist->insn; - -#if 0 /* not needed as unsupported opcodes shouldn't be in the hash lists */ - /* Is this insn supported by the selected cpu? */ - if (! m32r_cgen_insn_supported (od, insn)) - continue; -#endif - - /* If the RELAX attribute is set, this is an insn that shouldn't be - chosen immediately. Instead, it is used during assembler/linker - relaxation if possible. */ - if (CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX) != 0) - continue; - - str = start; - - /* Allow parse/insert handlers to obtain length of insn. */ - CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); - - if (! CGEN_PARSE_FN (insn) (od, insn, & str, fields)) - { - /* ??? 0 is passed for `pc' */ - if (CGEN_INSERT_FN (insn) (od, insn, fields, buf, (bfd_vma) 0) != NULL) - continue; - /* It is up to the caller to actually output the insn and any - queued relocs. */ - return insn; - } - - /* Try the next entry. */ - } - - /* FIXME: We can return a better error message than this. - Need to track why it failed and pick the right one. */ - { - static char errbuf[100]; - if (strlen (start) > 50) - /* xgettext:c-format */ - sprintf (errbuf, _("bad instruction `%.50s...'"), start); - else - /* xgettext:c-format */ - sprintf (errbuf, _("bad instruction `%.50s'"), start); - - *errmsg = errbuf; - return NULL; - } -} - -#if 0 /* This calls back to GAS which we can't do without care. */ - -/* Record each member of OPVALS in the assembler's symbol table. - This lets GAS parse registers for us. - ??? Interesting idea but not currently used. */ - -/* Record each member of OPVALS in the assembler's symbol table. - FIXME: Not currently used. */ - -void -m32r_cgen_asm_hash_keywords (od, opvals) - CGEN_OPCODE_DESC od; - CGEN_KEYWORD * opvals; -{ - CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); - const CGEN_KEYWORD_ENTRY * ke; - - while ((ke = cgen_keyword_search_next (& search)) != NULL) - { -#if 0 /* Unnecessary, should be done in the search routine. */ - if (! m32r_cgen_opval_supported (ke)) - continue; -#endif - cgen_asm_record_register (od, ke->name, ke->value); - } -} - -#endif /* 0 */ diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c deleted file mode 100644 index 606c77cb55c..00000000000 --- a/opcodes/m32r-dis.c +++ /dev/null @@ -1,929 +0,0 @@ -/* Disassembler interface for targets using CGEN. -*- C -*- - CGEN: Cpu tools GENerator - -THIS FILE IS USED TO GENERATE m32r-dis.c. - -Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. - -This file is part of the GNU Binutils and GDB, the GNU debugger. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include <stdio.h> -#include "ansidecl.h" -#include "dis-asm.h" -#include "bfd.h" -#include "symcat.h" -#include "m32r-opc.h" -#include "opintl.h" - -#undef INLINE -#ifdef __GNUC__ -#define INLINE __inline__ -#else -#define INLINE -#endif - -/* Default text to print if an instruction isn't recognized. */ -#define UNKNOWN_INSN_MSG _("*unknown*") - -/* Used by the ifield rtx function. */ -#define FLD(f) (fields->f) - -static int extract_normal - PARAMS ((CGEN_OPCODE_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - unsigned int, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, bfd_vma, long *)); -static void print_normal - PARAMS ((CGEN_OPCODE_DESC, PTR, long, unsigned int, bfd_vma, int)); -static void print_address - PARAMS ((CGEN_OPCODE_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); -static void print_keyword - PARAMS ((CGEN_OPCODE_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); -static int extract_insn_normal - PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, - CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); -static void print_insn_normal - PARAMS ((CGEN_OPCODE_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, - bfd_vma, int)); -static int print_insn PARAMS ((CGEN_OPCODE_DESC, bfd_vma, - disassemble_info *, char *, int)); -static int default_print_insn - PARAMS ((CGEN_OPCODE_DESC, bfd_vma, disassemble_info *)); - -/* -- disassembler routines inserted here */ -/* -- dis.c */ - -/* Immediate values are prefixed with '#'. */ - -#define CGEN_PRINT_NORMAL(od, info, value, attrs, pc, length) \ -do { \ - if ((attrs) & (1 << CGEN_OPERAND_HASH_PREFIX)) \ - (*info->fprintf_func) (info->stream, "#"); \ -} while (0) - -/* Handle '#' prefixes as operands. */ - -static void -print_hash (od, dis_info, value, attrs, pc, length) - CGEN_OPCODE_DESC od; - PTR dis_info; - long value; - unsigned int attrs; - bfd_vma pc; - int length; -{ - disassemble_info *info = (disassemble_info *) dis_info; - (*info->fprintf_func) (info->stream, "#"); -} - -#undef CGEN_PRINT_INSN -#define CGEN_PRINT_INSN my_print_insn - -static int -my_print_insn (od, pc, info) - CGEN_OPCODE_DESC od; - bfd_vma pc; - disassemble_info *info; -{ - char buffer[CGEN_MAX_INSN_SIZE]; - char *buf = buffer; - int status; - int buflen = (pc & 3) == 0 ? 4 : 2; - - /* Read the base part of the insn. */ - - status = (*info->read_memory_func) (pc, buf, buflen, info); - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return -1; - } - - /* 32 bit insn? */ - if ((pc & 3) == 0 && (buf[0] & 0x80) != 0) - return print_insn (od, pc, info, buf, buflen); - - /* Print the first insn. */ - if ((pc & 3) == 0) - { - if (print_insn (od, pc, info, buf, 2) == 0) - (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); - buf += 2; - } - - if (buf[0] & 0x80) - { - /* Parallel. */ - (*info->fprintf_func) (info->stream, " || "); - buf[0] &= 0x7f; - } - else - (*info->fprintf_func) (info->stream, " -> "); - - /* The "& 3" is to pass a consistent address. - Parallel insns arguably both begin on the word boundary. - Also, branch insns are calculated relative to the word boundary. */ - if (print_insn (od, pc & ~ (bfd_vma) 3, info, buf, 2) == 0) - (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); - - return (pc & 3) ? 2 : 4; -} - -/* -- */ - -/* Main entry point for operand extraction. - - This function is basically just a big switch statement. Earlier versions - used tables to look up the function to use, but - - if the table contains both assembler and disassembler functions then - the disassembler contains much of the assembler and vice-versa, - - there's a lot of inlining possibilities as things grow, - - using a switch statement avoids the function call overhead. - - This function could be moved into `print_insn_normal', but keeping it - separate makes clear the interface between `print_insn_normal' and each of - the handlers. -*/ - -int -m32r_cgen_extract_operand (od, opindex, ex_info, insn_value, fields, pc) - CGEN_OPCODE_DESC od; - int opindex; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - CGEN_FIELDS * fields; - bfd_vma pc; -{ - int length; - unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); - - switch (opindex) - { - case M32R_OPERAND_SR : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 32, total_length, pc, & fields->f_r2); - break; - case M32R_OPERAND_DR : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 4, 32, total_length, pc, & fields->f_r1); - break; - case M32R_OPERAND_SRC1 : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 4, 32, total_length, pc, & fields->f_r1); - break; - case M32R_OPERAND_SRC2 : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 32, total_length, pc, & fields->f_r2); - break; - case M32R_OPERAND_SCR : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 32, total_length, pc, & fields->f_r2); - break; - case M32R_OPERAND_DCR : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 4, 32, total_length, pc, & fields->f_r1); - break; - case M32R_OPERAND_SIMM8 : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 8, 8, 32, total_length, pc, & fields->f_simm8); - break; - case M32R_OPERAND_SIMM16 : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 16, 16, 32, total_length, pc, & fields->f_simm16); - break; - case M32R_OPERAND_UIMM4 : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 32, total_length, pc, & fields->f_uimm4); - break; - case M32R_OPERAND_UIMM5 : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 11, 5, 32, total_length, pc, & fields->f_uimm5); - break; - case M32R_OPERAND_UIMM16 : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_uimm16); - break; -/* start-sanitize-m32rx */ - case M32R_OPERAND_IMM1 : - { - long value; - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 15, 1, 32, total_length, pc, & value); - value = ((value) + (1)); - fields->f_imm1 = value; - } - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACCD : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 2, 32, total_length, pc, & fields->f_accd); - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACCS : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 2, 32, total_length, pc, & fields->f_accs); - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACC : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 1, 32, total_length, pc, & fields->f_acc); - break; -/* end-sanitize-m32rx */ - case M32R_OPERAND_HASH : - length = extract_normal (od, ex_info, insn_value, 0, 0, 0, 0, 0, total_length, pc, & fields->f_nil); - break; - case M32R_OPERAND_HI16 : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_hi16); - break; - case M32R_OPERAND_SLO16 : - length = extract_normal (od, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_simm16); - break; - case M32R_OPERAND_ULO16 : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_uimm16); - break; - case M32R_OPERAND_UIMM24 : - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 24, 32, total_length, pc, & fields->f_uimm24); - break; - case M32R_OPERAND_DISP8 : - { - long value; - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 8, 8, 32, total_length, pc, & value); - value = ((((value) << (2))) + (((pc) & (-4)))); - fields->f_disp8 = value; - } - break; - case M32R_OPERAND_DISP16 : - { - long value; - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 16, 16, 32, total_length, pc, & value); - value = ((((value) << (2))) + (pc)); - fields->f_disp16 = value; - } - break; - case M32R_OPERAND_DISP24 : - { - long value; - length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 8, 24, 32, total_length, pc, & value); - value = ((((value) << (2))) + (pc)); - fields->f_disp24 = value; - } - break; - - default : - /* xgettext:c-format */ - fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), - opindex); - abort (); - } - - return length; -} - -/* Main entry point for printing operands. - - This function is basically just a big switch statement. Earlier versions - used tables to look up the function to use, but - - if the table contains both assembler and disassembler functions then - the disassembler contains much of the assembler and vice-versa, - - there's a lot of inlining possibilities as things grow, - - using a switch statement avoids the function call overhead. - - This function could be moved into `print_insn_normal', but keeping it - separate makes clear the interface between `print_insn_normal' and each of - the handlers. -*/ - -void -m32r_cgen_print_operand (od, opindex, info, fields, attrs, pc, length) - CGEN_OPCODE_DESC od; - int opindex; - disassemble_info * info; - CGEN_FIELDS * fields; - void const * attrs; - bfd_vma pc; - int length; -{ - switch (opindex) - { - case M32R_OPERAND_SR : - print_keyword (od, info, & m32r_cgen_opval_h_gr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED)); - break; - case M32R_OPERAND_DR : - print_keyword (od, info, & m32r_cgen_opval_h_gr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED)); - break; - case M32R_OPERAND_SRC1 : - print_keyword (od, info, & m32r_cgen_opval_h_gr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED)); - break; - case M32R_OPERAND_SRC2 : - print_keyword (od, info, & m32r_cgen_opval_h_gr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED)); - break; - case M32R_OPERAND_SCR : - print_keyword (od, info, & m32r_cgen_opval_h_cr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED)); - break; - case M32R_OPERAND_DCR : - print_keyword (od, info, & m32r_cgen_opval_h_cr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED)); - break; - case M32R_OPERAND_SIMM8 : - print_normal (od, info, fields->f_simm8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); - break; - case M32R_OPERAND_SIMM16 : - print_normal (od, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); - break; - case M32R_OPERAND_UIMM4 : - print_normal (od, info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length); - break; - case M32R_OPERAND_UIMM5 : - print_normal (od, info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length); - break; - case M32R_OPERAND_UIMM16 : - print_normal (od, info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length); - break; -/* start-sanitize-m32rx */ - case M32R_OPERAND_IMM1 : - print_normal (od, info, fields->f_imm1, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length); - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACCD : - print_keyword (od, info, & m32r_cgen_opval_h_accums, fields->f_accd, 0|(1<<CGEN_OPERAND_UNSIGNED)); - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACCS : - print_keyword (od, info, & m32r_cgen_opval_h_accums, fields->f_accs, 0|(1<<CGEN_OPERAND_UNSIGNED)); - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACC : - print_keyword (od, info, & m32r_cgen_opval_h_accums, fields->f_acc, 0|(1<<CGEN_OPERAND_UNSIGNED)); - break; -/* end-sanitize-m32rx */ - case M32R_OPERAND_HASH : - print_hash (od, info, fields->f_nil, 0, pc, length); - break; - case M32R_OPERAND_HI16 : - print_normal (od, info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), pc, length); - break; - case M32R_OPERAND_SLO16 : - print_normal (od, info, fields->f_simm16, 0, pc, length); - break; - case M32R_OPERAND_ULO16 : - print_normal (od, info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length); - break; - case M32R_OPERAND_UIMM24 : - print_address (od, info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), pc, length); - break; - case M32R_OPERAND_DISP8 : - print_address (od, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); - break; - case M32R_OPERAND_DISP16 : - print_address (od, info, fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); - break; - case M32R_OPERAND_DISP24 : - print_address (od, info, fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); - break; - - default : - /* xgettext:c-format */ - fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), - opindex); - abort (); - } -} - -cgen_extract_fn * const m32r_cgen_extract_handlers[] = -{ - 0, /* default */ - extract_insn_normal, -}; - -cgen_print_fn * const m32r_cgen_print_handlers[] = -{ - 0, /* default */ - print_insn_normal, -}; - - -void -m32r_cgen_init_dis (od) - CGEN_OPCODE_DESC od; -{ -} - - -#if ! CGEN_INT_INSN_P - -/* Subroutine of extract_normal. - Ensure sufficient bytes are cached in EX_INFO. - OFFSET is the offset in bytes from the start of the insn of the value. - BYTES is the length of the needed value. - Returns 1 for success, 0 for failure. */ - -static INLINE int -fill_cache (od, ex_info, offset, bytes, pc) - CGEN_OPCODE_DESC od; - CGEN_EXTRACT_INFO *ex_info; - int offset, bytes; - bfd_vma pc; -{ - /* It's doubtful that the middle part has already been fetched so - we don't optimize that case. kiss. */ - int mask; - disassemble_info *info = (disassemble_info *) ex_info->dis_info; - - /* First do a quick check. */ - mask = (1 << bytes) - 1; - if (((ex_info->valid >> offset) & mask) == mask) - return 1; - - /* Search for the first byte we need to read. */ - for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) - if (! (mask & ex_info->valid)) - break; - - if (bytes) - { - int status; - - pc += offset; - status = (*info->read_memory_func) - (pc, ex_info->insn_bytes + offset, bytes, info); - - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return 0; - } - - ex_info->valid |= ((1 << bytes) - 1) << offset; - } - - return 1; -} - -/* Subroutine of extract_normal. */ - -static INLINE long -extract_1 (od, ex_info, start, length, word_length, bufp, pc) - CGEN_OPCODE_DESC od; - CGEN_EXTRACT_INFO *ex_info; - int start,length,word_length; - unsigned char *bufp; - bfd_vma pc; -{ - unsigned long x,mask; - int shift; - int big_p = CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG; - - switch (word_length) - { - case 8: - x = *bufp; - break; - case 16: - if (big_p) - x = bfd_getb16 (bufp); - else - x = bfd_getl16 (bufp); - break; - case 24: - /* ??? This may need reworking as these cases don't necessarily - want the first byte and the last two bytes handled like this. */ - if (big_p) - x = (bufp[0] << 16) | bfd_getb16 (bufp + 1); - else - x = bfd_getl16 (bufp) | (bufp[2] << 16); - break; - case 32: - if (big_p) - x = bfd_getb32 (bufp); - else - x = bfd_getl32 (bufp); - break; - default : - abort (); - } - - /* Written this way to avoid undefined behaviour. */ - mask = (((1L << (length - 1)) - 1) << 1) | 1; - if (CGEN_INSN_LSB0_P) - shift = (start + 1) - length; - else - shift = (word_length - (start + length)); - return (x >> shift) & mask; -} - -#endif /* ! CGEN_INT_INSN_P */ - -/* Default extraction routine. - - INSN_VALUE is the first CGEN_BASE_INSN_SIZE bits of the insn in host order, - or sometimes less for cases like the m32r where the base insn size is 32 - but some insns are 16 bits. - ATTRS is a mask of the boolean attributes. We only need `UNSIGNED', - but for generality we take a bitmask of all of them. - WORD_OFFSET is the offset in bits from the start of the insn of the value. - WORD_LENGTH is the length of the word in bits in which the value resides. - START is the starting bit number in the word, architecture origin. - LENGTH is the length of VALUE in bits. - TOTAL_LENGTH is the total length of the insn in bits. - - Returns 1 for success, 0 for failure. */ - -/* ??? The return code isn't properly used. wip. */ - -/* ??? This doesn't handle bfd_vma's. Create another function when - necessary. */ - -static int -extract_normal (od, ex_info, insn_value, attrs, word_offset, start, length, - word_length, total_length, pc, valuep) - CGEN_OPCODE_DESC od; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - unsigned int attrs; - unsigned int word_offset, start, length, word_length, total_length; - bfd_vma pc; - long *valuep; -{ - CGEN_INSN_INT value; - - /* If LENGTH is zero, this operand doesn't contribute to the value - so give it a standard value of zero. */ - if (length == 0) - { - *valuep = 0; - return 1; - } - - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); - - if (word_length > 32) - abort (); - - /* For architectures with insns smaller than the insn-base-bitsize, - word_length may be too big. */ -#if CGEN_MIN_INSN_BITSIZE < CGEN_BASE_INSN_BITSIZE - if (word_offset == 0 - && word_length > total_length) - word_length = total_length; -#endif - - /* Does the value reside in INSN_VALUE? */ - - if (word_offset == 0) - { - /* Written this way to avoid undefined behaviour. */ - CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; - - if (CGEN_INSN_LSB0_P) - value = insn_value >> ((start + 1) - length); - else - value = insn_value >> (word_length - (start + length)); - value &= mask; - /* sign extend? */ - if (! CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED) - && (value & (1L << (length - 1)))) - value |= ~mask; - } - -#if ! CGEN_INT_INSN_P - - else - { - unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; - - if (word_length > 32) - abort (); - - if (fill_cache (od, ex_info, word_offset / 8, word_length / 8, pc) == 0) - return 0; - - value = extract_1 (od, ex_info, start, length, word_length, bufp, pc); - } - -#endif /* ! CGEN_INT_INSN_P */ - - *valuep = value; - - return 1; -} - -/* Default print handler. */ - -static void -print_normal (od, dis_info, value, attrs, pc, length) - CGEN_OPCODE_DESC od; - PTR dis_info; - long value; - unsigned int attrs; - bfd_vma pc; - int length; -{ - disassemble_info *info = (disassemble_info *) dis_info; - -#ifdef CGEN_PRINT_NORMAL - CGEN_PRINT_NORMAL (od, info, value, attrs, pc, length); -#endif - - /* Print the operand as directed by the attributes. */ - if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) - ; /* nothing to do */ - else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED)) - (*info->fprintf_func) (info->stream, "0x%lx", value); - else - (*info->fprintf_func) (info->stream, "%ld", value); -} - -/* Default address handler. */ - -static void -print_address (od, dis_info, value, attrs, pc, length) - CGEN_OPCODE_DESC od; - PTR dis_info; - bfd_vma value; - unsigned int attrs; - bfd_vma pc; - int length; -{ - disassemble_info *info = (disassemble_info *) dis_info; - -#ifdef CGEN_PRINT_ADDRESS - CGEN_PRINT_ADDRESS (od, info, value, attrs, pc, length); -#endif - - /* Print the operand as directed by the attributes. */ - if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) - ; /* nothing to do */ - else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) - (*info->print_address_func) (value, info); - else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) - (*info->print_address_func) (value, info); - else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED)) - (*info->fprintf_func) (info->stream, "0x%lx", (long) value); - else - (*info->fprintf_func) (info->stream, "%ld", (long) value); -} - -/* Keyword print handler. */ - -static void -print_keyword (od, dis_info, keyword_table, value, attrs) - CGEN_OPCODE_DESC od; - PTR dis_info; - CGEN_KEYWORD *keyword_table; - long value; - unsigned int attrs; -{ - disassemble_info *info = (disassemble_info *) dis_info; - const CGEN_KEYWORD_ENTRY *ke; - - ke = cgen_keyword_lookup_value (keyword_table, value); - if (ke != NULL) - (*info->fprintf_func) (info->stream, "%s", ke->name); - else - (*info->fprintf_func) (info->stream, "???"); -} - -/* Default insn extractor. - - INSN_VALUE is the first CGEN_BASE_INSN_SIZE bytes, translated to host order. - The extracted fields are stored in FIELDS. - EX_INFO is used to handle reading variable length insns. - Return the length of the insn in bits, or 0 if no match, - or -1 if an error occurs fetching data (memory_error_func will have - been called). */ - -static int -extract_insn_normal (od, insn, ex_info, insn_value, fields, pc) - CGEN_OPCODE_DESC od; - const CGEN_INSN *insn; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - CGEN_FIELDS *fields; - bfd_vma pc; -{ - const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); - const unsigned char *syn; - - CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); - - CGEN_INIT_EXTRACT (od); - - for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) - { - int length; - - if (CGEN_SYNTAX_CHAR_P (*syn)) - continue; - - length = m32r_cgen_extract_operand (od, CGEN_SYNTAX_FIELD (*syn), - ex_info, insn_value, fields, pc); - if (length <= 0) - return length; - } - - /* We recognized and successfully extracted this insn. */ - return CGEN_INSN_BITSIZE (insn); -} - -/* Default insn printer. - - DIS_INFO is defined as `PTR' so the disassembler needn't know anything - about disassemble_info. */ - -static void -print_insn_normal (od, dis_info, insn, fields, pc, length) - CGEN_OPCODE_DESC od; - PTR dis_info; - const CGEN_INSN *insn; - CGEN_FIELDS *fields; - bfd_vma pc; - int length; -{ - const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); - disassemble_info *info = (disassemble_info *) dis_info; - const unsigned char *syn; - - CGEN_INIT_PRINT (od); - - for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) - { - if (CGEN_SYNTAX_MNEMONIC_P (*syn)) - { - (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); - continue; - } - if (CGEN_SYNTAX_CHAR_P (*syn)) - { - (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); - continue; - } - - /* We have an operand. */ - m32r_cgen_print_operand (od, CGEN_SYNTAX_FIELD (*syn), info, - fields, CGEN_INSN_ATTRS (insn), pc, length); - } -} - -/* Utility to print an insn. - BUF is the base part of the insn, target byte order, BUFLEN bytes long. - The result is the size of the insn in bytes or zero for an unknown insn - or -1 if an error occurs fetching data (memory_error_func will have - been called). */ - -static int -print_insn (od, pc, info, buf, buflen) - CGEN_OPCODE_DESC od; - bfd_vma pc; - disassemble_info *info; - char *buf; - int buflen; -{ - unsigned long insn_value; - const CGEN_INSN_LIST *insn_list; - CGEN_EXTRACT_INFO ex_info; - - ex_info.dis_info = info; - ex_info.valid = (1 << CGEN_BASE_INSN_SIZE) - 1; - ex_info.insn_bytes = buf; - - switch (buflen) - { - case 1: - insn_value = buf[0]; - break; - case 2: - insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf); - break; - case 4: - insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf); - break; - default: - abort (); - } - - /* The instructions are stored in hash lists. - Pick the first one and keep trying until we find the right one. */ - - insn_list = CGEN_DIS_LOOKUP_INSN (od, buf, insn_value); - while (insn_list != NULL) - { - const CGEN_INSN *insn = insn_list->insn; - CGEN_FIELDS fields; - int length; - -#if 0 /* not needed as insn shouldn't be in hash lists if not supported */ - /* Supported by this cpu? */ - if (! m32r_cgen_insn_supported (od, insn)) - continue; -#endif - - /* Basic bit mask must be correct. */ - /* ??? May wish to allow target to defer this check until the extract - handler. */ - if ((insn_value & CGEN_INSN_BASE_MASK (insn)) - == CGEN_INSN_BASE_VALUE (insn)) - { - /* Printing is handled in two passes. The first pass parses the - machine insn and extracts the fields. The second pass prints - them. */ - - length = (*CGEN_EXTRACT_FN (insn)) (od, insn, &ex_info, insn_value, - &fields, pc); - /* length < 0 -> error */ - if (length < 0) - return length; - if (length > 0) - { - (*CGEN_PRINT_FN (insn)) (od, info, insn, &fields, pc, length); - /* length is in bits, result is in bytes */ - return length / 8; - } - } - - insn_list = CGEN_DIS_NEXT_INSN (insn_list); - } - - return 0; -} - -/* Default value for CGEN_PRINT_INSN. - The result is the size of the insn in bytes or zero for an unknown insn - or -1 if an error occured fetching bytes. */ - -#ifndef CGEN_PRINT_INSN -#define CGEN_PRINT_INSN default_print_insn -#endif - -static int -default_print_insn (od, pc, info) - CGEN_OPCODE_DESC od; - bfd_vma pc; - disassemble_info *info; -{ - char buf[CGEN_MAX_INSN_SIZE]; - int status; - - /* Read the base part of the insn. */ - - status = (*info->read_memory_func) (pc, buf, CGEN_BASE_INSN_SIZE, info); - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return -1; - } - - return print_insn (od, pc, info, buf, CGEN_BASE_INSN_SIZE); -} - -/* Main entry point. - Print one instruction from PC on INFO->STREAM. - Return the size of the instruction (in bytes). */ - -int -print_insn_m32r (pc, info) - bfd_vma pc; - disassemble_info *info; -{ - int length; - static CGEN_OPCODE_DESC od = 0; - int mach = info->mach; - int big_p = info->endian == BFD_ENDIAN_BIG; - - /* If we haven't initialized yet, initialize the opcode table. */ - if (! od) - { - od = m32r_cgen_opcode_open (mach, - big_p ? - CGEN_ENDIAN_BIG - : CGEN_ENDIAN_LITTLE); - m32r_cgen_init_dis (od); - } - /* If we've switched cpu's, re-initialize. */ - /* ??? Perhaps we should use BFD_ENDIAN. */ - else if (mach != CGEN_OPCODE_MACH (od) - || (CGEN_OPCODE_ENDIAN (od) - != (big_p ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE))) - { - cgen_set_cpu (od, mach, big_p ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); - } - - /* We try to have as much common code as possible. - But at this point some targets need to take over. */ - /* ??? Some targets may need a hook elsewhere. Try to avoid this, - but if not possible try to move this hook elsewhere rather than - have two hooks. */ - length = CGEN_PRINT_INSN (od, pc, info); - if (length > 0) - return length; - if (length < 0) - return -1; - - (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); - return CGEN_DEFAULT_INSN_SIZE; -} diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c deleted file mode 100644 index e9c1f7430cf..00000000000 --- a/opcodes/m32r-opc.c +++ /dev/null @@ -1,3626 +0,0 @@ -/* Generic opcode table support for targets using CGEN. -*- C -*- - CGEN: Cpu tools GENerator - -THIS FILE IS USED TO GENERATE m32r-opc.c. - -Copyright (C) 1998, 1999 Free Software Foundation, Inc. - -This file is part of the GNU Binutils and GDB, the GNU debugger. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include <stdio.h> -#include "ansidecl.h" -#include "libiberty.h" -#include "bfd.h" -#include "symcat.h" -#include "m32r-opc.h" -#include "opintl.h" - -/* Used by the ifield rtx function. */ -#define FLD(f) (fields->f) - -/* The hash functions are recorded here to help keep assembler code out of - the disassembler and vice versa. */ - -static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int asm_hash_insn PARAMS ((const char *)); -static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); - -/* Look up instruction INSN_VALUE and extract its fields. - INSN, if non-null, is the insn table entry. - Otherwise INSN_VALUE is examined to compute it. - LENGTH is the bit length of INSN_VALUE if known, otherwise 0. - 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'. - If INSN != NULL, LENGTH must be valid. - ALIAS_P is non-zero if alias insns are to be included in the search. - - The result is a pointer to the insn table entry, or NULL if the instruction - wasn't recognized. */ - -const CGEN_INSN * -m32r_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p) - CGEN_OPCODE_DESC od; - const CGEN_INSN *insn; - CGEN_INSN_BYTES insn_value; - int length; - CGEN_FIELDS *fields; - int alias_p; -{ - unsigned char buf[CGEN_MAX_INSN_SIZE]; - unsigned char *bufp; - CGEN_INSN_INT base_insn; -#if CGEN_INT_INSN_P - CGEN_EXTRACT_INFO *info = NULL; -#else - CGEN_EXTRACT_INFO ex_info; - CGEN_EXTRACT_INFO *info = &ex_info; -#endif - -#if CGEN_INT_INSN_P - cgen_put_insn_value (od, buf, length, insn_value); - bufp = buf; - base_insn = insn_value; /*???*/ -#else - ex_info.dis_info = NULL; - ex_info.insn_bytes = insn_value; - ex_info.valid = -1; - base_insn = cgen_get_insn_value (od, buf, length); - bufp = insn_value; -#endif - - if (!insn) - { - const CGEN_INSN_LIST *insn_list; - - /* The instructions are stored in hash lists. - Pick the first one and keep trying until we find the right one. */ - - insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn); - while (insn_list != NULL) - { - insn = insn_list->insn; - - if (alias_p - || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS)) - { - /* Basic bit mask must be correct. */ - /* ??? May wish to allow target to defer this check until the - extract handler. */ - if ((base_insn & CGEN_INSN_BASE_MASK (insn)) - == CGEN_INSN_BASE_VALUE (insn)) - { - /* ??? 0 is passed for `pc' */ - int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, - base_insn, fields, - (bfd_vma) 0); - if (elength > 0) - { - /* sanity check */ - if (length != 0 && length != elength) - abort (); - return insn; - } - } - } - - insn_list = CGEN_DIS_NEXT_INSN (insn_list); - } - } - else - { - /* Sanity check: can't pass an alias insn if ! alias_p. */ - if (! alias_p - && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS)) - abort (); - /* Sanity check: length must be correct. */ - if (length != CGEN_INSN_BITSIZE (insn)) - abort (); - - /* ??? 0 is passed for `pc' */ - length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields, - (bfd_vma) 0); - /* Sanity check: must succeed. - Could relax this later if it ever proves useful. */ - if (length == 0) - abort (); - return insn; - } - - return NULL; -} - -/* Fill in the operand instances used by INSN whose operands are FIELDS. - INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled - in. */ - -void -m32r_cgen_get_insn_operands (od, insn, fields, indices) - CGEN_OPCODE_DESC od; - const CGEN_INSN * insn; - const CGEN_FIELDS * fields; - int *indices; -{ - const CGEN_OPERAND_INSTANCE *opinst; - int i; - - for (i = 0, opinst = CGEN_INSN_OPERANDS (insn); - opinst != NULL - && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END; - ++i, ++opinst) - { - const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst); - if (op == NULL) - indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst); - else - indices[i] = m32r_cgen_get_int_operand (CGEN_OPERAND_INDEX (op), - fields); - } -} - -/* Cover function to m32r_cgen_get_insn_operands when either INSN or FIELDS - isn't known. - The INSN, INSN_VALUE, and LENGTH arguments are passed to - m32r_cgen_lookup_insn unchanged. - - The result is the insn table entry or NULL if the instruction wasn't - recognized. */ - -const CGEN_INSN * -m32r_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices) - CGEN_OPCODE_DESC od; - const CGEN_INSN *insn; - CGEN_INSN_BYTES insn_value; - int length; - int *indices; -{ - CGEN_FIELDS fields; - - /* Pass non-zero for ALIAS_P only if INSN != NULL. - If INSN == NULL, we want a real insn. */ - insn = m32r_cgen_lookup_insn (od, insn, insn_value, length, &fields, - insn != NULL); - if (! insn) - return NULL; - - m32r_cgen_get_insn_operands (od, insn, &fields, indices); - return insn; -} -/* Attributes. */ - -static const CGEN_ATTR_ENTRY bool_attr[] = -{ - { "#f", 0 }, - { "#t", 1 }, - { 0, 0 } -}; - -static const CGEN_ATTR_ENTRY MACH_attr[] = -{ - { "base", MACH_BASE }, - { "m32r", MACH_M32R }, -/* start-sanitize-m32rx */ - { "m32rx", MACH_M32RX }, -/* end-sanitize-m32rx */ - { "max", MACH_MAX }, - { 0, 0 } -}; - -/* start-sanitize-m32rx */ -static const CGEN_ATTR_ENTRY PIPE_attr[] = -{ - { "NONE", PIPE_NONE }, - { "O", PIPE_O }, - { "S", PIPE_S }, - { "OS", PIPE_OS }, - { 0, 0 } -}; - -/* end-sanitize-m32rx */ -const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] = -{ - { "MACH", & MACH_attr[0] }, - { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, - { "UNSIGNED", &bool_attr[0], &bool_attr[0] }, - { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, - { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, - { "RESERVED", &bool_attr[0], &bool_attr[0] }, - { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, - { "RELOC", &bool_attr[0], &bool_attr[0] }, - { 0, 0, 0 } -}; - -const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] = -{ - { "MACH", & MACH_attr[0] }, - { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, - { "UNSIGNED", &bool_attr[0], &bool_attr[0] }, - { "SIGNED", &bool_attr[0], &bool_attr[0] }, - { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, - { "FUN-ACCESS", &bool_attr[0], &bool_attr[0] }, - { "PC", &bool_attr[0], &bool_attr[0] }, - { "PROFILE", &bool_attr[0], &bool_attr[0] }, - { 0, 0, 0 } -}; - -const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] = -{ - { "MACH", & MACH_attr[0] }, - { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, - { "UNSIGNED", &bool_attr[0], &bool_attr[0] }, - { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, - { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, - { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, - { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, - { "RELAX", &bool_attr[0], &bool_attr[0] }, - { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, - { "RELOC", &bool_attr[0], &bool_attr[0] }, - { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] }, - { 0, 0, 0 } -}; - -const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] = -{ - { "MACH", & MACH_attr[0] }, -/* start-sanitize-m32rx */ - { "PIPE", & PIPE_attr[0] }, -/* end-sanitize-m32rx */ - { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, - { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, - { "COND-CTI", &bool_attr[0], &bool_attr[0] }, - { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, - { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, - { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, - { "RELAX", &bool_attr[0], &bool_attr[0] }, - { "ALIAS", &bool_attr[0], &bool_attr[0] }, - { "NO-DIS", &bool_attr[0], &bool_attr[0] }, - { "PBB", &bool_attr[0], &bool_attr[0] }, - { "FILL-SLOT", &bool_attr[0], &bool_attr[0] }, -/* start-sanitize-m32rx */ - { "SPECIAL", &bool_attr[0], &bool_attr[0] }, -/* end-sanitize-m32rx */ - { 0, 0, 0 } -}; - -CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] = -{ - { "fp", 13 }, - { "lr", 14 }, - { "sp", 15 }, - { "r0", 0 }, - { "r1", 1 }, - { "r2", 2 }, - { "r3", 3 }, - { "r4", 4 }, - { "r5", 5 }, - { "r6", 6 }, - { "r7", 7 }, - { "r8", 8 }, - { "r9", 9 }, - { "r10", 10 }, - { "r11", 11 }, - { "r12", 12 }, - { "r13", 13 }, - { "r14", 14 }, - { "r15", 15 } -}; - -CGEN_KEYWORD m32r_cgen_opval_h_gr = -{ - & m32r_cgen_opval_h_gr_entries[0], - 19 -}; - -CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] = -{ - { "psw", 0 }, - { "cbr", 1 }, - { "spi", 2 }, - { "spu", 3 }, - { "bpc", 6 }, - { "bbpsw", 8 }, - { "bbpc", 14 }, - { "cr0", 0 }, - { "cr1", 1 }, - { "cr2", 2 }, - { "cr3", 3 }, - { "cr4", 4 }, - { "cr5", 5 }, - { "cr6", 6 }, - { "cr7", 7 }, - { "cr8", 8 }, - { "cr9", 9 }, - { "cr10", 10 }, - { "cr11", 11 }, - { "cr12", 12 }, - { "cr13", 13 }, - { "cr14", 14 }, - { "cr15", 15 } -}; - -CGEN_KEYWORD m32r_cgen_opval_h_cr = -{ - & m32r_cgen_opval_h_cr_entries[0], - 23 -}; - -/* start-sanitize-m32rx */ -CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] = -{ - { "a0", 0 }, - { "a1", 1 } -}; - -CGEN_KEYWORD m32r_cgen_opval_h_accums = -{ - & m32r_cgen_opval_h_accums_entries[0], - 2 -}; - -/* end-sanitize-m32rx */ - -/* The hardware table. */ - -#define HW_ENT(n) m32r_cgen_hw_entries[n] -static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] = -{ - { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { (1<<MACH_BASE) } } }, - { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { (1<<MACH_BASE) } } }, - { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } }, - { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } }, -/* start-sanitize-m32rx */ - { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_M32RX) } } }, -/* end-sanitize-m32rx */ - { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_PSW, & HW_ENT (HW_H_PSW + 1), "h-psw", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } }, - { HW_H_BPSW, & HW_ENT (HW_H_BPSW + 1), "h-bpsw", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_BBPSW, & HW_ENT (HW_H_BBPSW + 1), "h-bbpsw", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_LOCK, & HW_ENT (HW_H_LOCK + 1), "h-lock", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { 0 } -}; - -/* The instruction field table. */ - -static const CGEN_IFLD m32r_cgen_ifld_table[] = -{ - { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { M32R_F_COND, "f-cond", 0, 32, 4, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { M32R_F_R1, "f-r1", 0, 32, 4, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { M32R_F_R2, "f-r2", 0, 32, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR)|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_SIGN_OPT)|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, - { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } }, - { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } }, - { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } }, -/* start-sanitize-m32rx */ - { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } }, -/* end-sanitize-m32rx */ - { 0 } -}; - -/* The operand table. */ - -#define OPERAND(op) CONCAT2 (M32R_OPERAND_,op) -#define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)] - -const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] = -{ -/* pc: program counter */ - { "pc", & HW_ENT (HW_H_PC), 0, 0, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } }, -/* sr: source register */ - { "sr", & HW_ENT (HW_H_GR), 12, 4, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* dr: destination register */ - { "dr", & HW_ENT (HW_H_GR), 4, 4, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* src1: source register 1 */ - { "src1", & HW_ENT (HW_H_GR), 4, 4, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* src2: source register 2 */ - { "src2", & HW_ENT (HW_H_GR), 12, 4, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* scr: source control register */ - { "scr", & HW_ENT (HW_H_CR), 12, 4, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* dcr: destination control register */ - { "dcr", & HW_ENT (HW_H_CR), 4, 4, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* simm8: 8 bit signed immediate */ - { "simm8", & HW_ENT (HW_H_SINT), 8, 8, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } }, -/* simm16: 16 bit signed immediate */ - { "simm16", & HW_ENT (HW_H_SINT), 16, 16, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } }, -/* uimm4: 4 bit trap number */ - { "uimm4", & HW_ENT (HW_H_UINT), 12, 4, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* uimm5: 5 bit shift count */ - { "uimm5", & HW_ENT (HW_H_UINT), 11, 5, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* uimm16: 16 bit unsigned immediate */ - { "uimm16", & HW_ENT (HW_H_UINT), 16, 16, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* start-sanitize-m32rx */ -/* imm1: 1 bit immediate */ - { "imm1", & HW_ENT (HW_H_UINT), 15, 1, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -/* accd: accumulator destination register */ - { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -/* accs: accumulator source register */ - { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -/* acc: accumulator reg (d) */ - { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* end-sanitize-m32rx */ -/* hash: # prefix */ - { "hash", & HW_ENT (HW_H_SINT), 0, 0, - { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, -/* hi16: high 16 bit immediate, sign optional */ - { "hi16", & HW_ENT (HW_H_HI16), 16, 16, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* slo16: 16 bit signed immediate, for low() */ - { "slo16", & HW_ENT (HW_H_SLO16), 16, 16, - { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, -/* ulo16: 16 bit unsigned immediate, for low() */ - { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* uimm24: 24 bit address */ - { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } }, -/* disp8: 8 bit displacement */ - { "disp8", & HW_ENT (HW_H_IADDR), 8, 8, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } }, -/* disp16: 16 bit displacement */ - { "disp16", & HW_ENT (HW_H_IADDR), 16, 16, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } }, -/* disp24: 24 bit displacement */ - { "disp24", & HW_ENT (HW_H_IADDR), 8, 24, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } }, -/* condbit: condition bit */ - { "condbit", & HW_ENT (HW_H_COND), 0, 0, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } }, -/* accum: accumulator */ - { "accum", & HW_ENT (HW_H_ACCUM), 0, 0, - { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } }, -}; - -/* Operand references. */ - -#define INPUT CGEN_OPERAND_INSTANCE_INPUT -#define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT -#define COND_REF CGEN_OPERAND_INSTANCE_COND_REF - -static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = { - { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_add3_ops[] = { - { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 }, - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_and3_ops[] = { - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, - { INPUT, "uimm16", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_or3_ops[] = { - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, - { INPUT, "ulo16", & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = { - { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { INPUT, "simm8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_addv_ops[] = { - { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, - { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_addv3_ops[] = { - { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0, 0 }, - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, - { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_addx_ops[] = { - { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, - { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, - { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_bc8_ops[] = { - { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, - { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0, COND_REF }, - { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_bc24_ops[] = { - { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, - { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0, COND_REF }, - { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_beq_ops[] = { - { INPUT, "disp16", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0, COND_REF }, - { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, - { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_beqz_ops[] = { - { INPUT, "disp16", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0, COND_REF }, - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, - { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_bl8_ops[] = { - { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0, 0 }, - { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, - { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 }, - { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_bl24_ops[] = { - { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0, 0 }, - { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, - { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 }, - { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, - { 0 } -}; - -/* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_bcl8_ops[] = { - { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, - { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0, COND_REF }, - { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF }, - { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, COND_REF }, - { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF }, - { 0 } -}; - -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_bcl24_ops[] = { - { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, - { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0, COND_REF }, - { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF }, - { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, COND_REF }, - { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF }, - { 0 } -}; - -/* end-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_bra8_ops[] = { - { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0, 0 }, - { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_bra24_ops[] = { - { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0, 0 }, - { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = { - { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, - { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = { - { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0, 0 }, - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, - { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, - { 0 } -}; - -/* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_cmpeq_ops[] = { - { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, - { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, - { 0 } -}; - -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_cmpz_ops[] = { - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, - { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, - { 0 } -}; - -/* end-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_div_ops[] = { - { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, COND_REF }, - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, COND_REF }, - { 0 } -}; - -/* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_divh_ops[] = { - { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, COND_REF }, - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, COND_REF }, - { 0 } -}; - -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_jc_ops[] = { - { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, COND_REF }, - { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF }, - { 0 } -}; - -/* end-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_jl_ops[] = { - { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, - { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 }, - { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = { - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, - { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = { - { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_ld_d_ops[] = { - { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, - { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 }, - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_ldb_ops[] = { - { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 }, - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_ldb_d_ops[] = { - { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 }, - { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 }, - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_ldh_ops[] = { - { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 }, - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_ldh_d_ops[] = { - { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 }, - { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 }, - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_ld_plus_ops[] = { - { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { OUTPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_ld24_ops[] = { - { INPUT, "uimm24", & HW_ENT (HW_H_ADDR), CGEN_MODE_USI, & OP_ENT (UIMM24), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = { - { INPUT, "simm8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_ldi16_ops[] = { - { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_lock_ops[] = { - { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { OUTPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_machi_ops[] = { - { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 }, - { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, - { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 }, - { 0 } -}; - -/* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_machi_a_ops[] = { - { INPUT, "acc", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0, 0 }, - { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, - { OUTPUT, "acc", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0, 0 }, - { 0 } -}; - -/* end-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_mulhi_ops[] = { - { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, - { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 }, - { 0 } -}; - -/* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_mulhi_a_ops[] = { - { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, - { OUTPUT, "acc", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0, 0 }, - { 0 } -}; - -/* end-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_mv_ops[] = { - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_mvfachi_ops[] = { - { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -/* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_mvfachi_a_ops[] = { - { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -/* end-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_mvfc_ops[] = { - { INPUT, "scr", & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_mvtachi_ops[] = { - { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 }, - { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, - { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 }, - { 0 } -}; - -/* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_mvtachi_a_ops[] = { - { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0, 0 }, - { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, - { OUTPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0, 0 }, - { 0 } -}; - -/* end-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_mvtc_ops[] = { - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, - { OUTPUT, "dcr", & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_rac_ops[] = { - { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 }, - { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 }, - { 0 } -}; - -/* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_rac_dsi_ops[] = { - { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0, 0 }, - { INPUT, "imm1", & HW_ENT (HW_H_UINT), CGEN_MODE_INT, & OP_ENT (IMM1), 0, 0 }, - { OUTPUT, "accd", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0, 0 }, - { 0 } -}; - -/* end-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_rte_ops[] = { - { INPUT, "h_bbpsw_0", & HW_ENT (HW_H_BBPSW), CGEN_MODE_UQI, 0, 0, 0 }, - { INPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 }, - { INPUT, "h_cr_14", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 14, 0 }, - { INPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 }, - { OUTPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 }, - { OUTPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 }, - { OUTPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0, 0 }, - { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_seth_ops[] = { - { INPUT, "hi16", & HW_ENT (HW_H_HI16), CGEN_MODE_SI, & OP_ENT (HI16), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_sll3_ops[] = { - { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0, 0 }, - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_slli_ops[] = { - { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { INPUT, "uimm5", & HW_ENT (HW_H_UINT), CGEN_MODE_INT, & OP_ENT (UIMM5), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = { - { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, 0 }, - { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_st_d_ops[] = { - { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 }, - { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, - { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = { - { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0, 0 }, - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, 0 }, - { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_stb_d_ops[] = { - { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 }, - { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0, 0 }, - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, - { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = { - { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0, 0 }, - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, 0 }, - { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_sth_d_ops[] = { - { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 }, - { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0, 0 }, - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, - { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_st_plus_ops[] = { - { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, - { OUTPUT, "h_memory_new_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, - { OUTPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_trap_ops[] = { - { INPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 }, - { INPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 }, - { INPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0, 0 }, - { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, - { INPUT, "uimm4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM4), 0, 0 }, - { OUTPUT, "h_bbpsw_0", & HW_ENT (HW_H_BBPSW), CGEN_MODE_UQI, 0, 0, 0 }, - { OUTPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 }, - { OUTPUT, "h_cr_14", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 14, 0 }, - { OUTPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 }, - { OUTPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0, 0 }, - { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 }, - { 0 } -}; - -static const CGEN_OPERAND_INSTANCE fmt_unlock_ops[] = { - { INPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0, 0 }, - { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, COND_REF }, - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, COND_REF }, - { OUTPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0, 0 }, - { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF }, - { 0 } -}; - -/* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_satb_ops[] = { - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_sat_ops[] = { - { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, COND_REF }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { 0 } -}; - -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_sadd_ops[] = { - { INPUT, "h_accums_0", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0, 0 }, - { INPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1, 0 }, - { OUTPUT, "h_accums_0", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0, 0 }, - { 0 } -}; - -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_macwu1_ops[] = { - { INPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1, 0 }, - { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, - { OUTPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1, 0 }, - { 0 } -}; - -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_msblo_ops[] = { - { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 }, - { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, - { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 }, - { 0 } -}; - -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_mulwu1_ops[] = { - { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, - { OUTPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1, 0 }, - { 0 } -}; - -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_sc_ops[] = { - { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, - { 0 } -}; - -/* end-sanitize-m32rx */ -#undef INPUT -#undef OUTPUT -#undef COND_REF - -/* Instruction formats. */ - -#define F(f) & m32r_cgen_ifld_table[CONCAT2 (M32R_,f)] - -static const CGEN_IFMT ifmt_empty = { - 0, 0, 0x0, { 0 } -}; - -static const CGEN_IFMT ifmt_add = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT ifmt_add3 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } -}; - -static const CGEN_IFMT ifmt_and3 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 } -}; - -static const CGEN_IFMT ifmt_or3 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 } -}; - -static const CGEN_IFMT ifmt_addi = { - 16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 } -}; - -static const CGEN_IFMT ifmt_addv3 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } -}; - -static const CGEN_IFMT ifmt_bc8 = { - 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } -}; - -static const CGEN_IFMT ifmt_bc24 = { - 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } -}; - -static const CGEN_IFMT ifmt_beq = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_DISP16), 0 } -}; - -static const CGEN_IFMT ifmt_beqz = { - 32, 32, 0xfff00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_DISP16), 0 } -}; - -/* start-sanitize-m32rx */ -static const CGEN_IFMT ifmt_bcl8 = { - 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } -}; - -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -static const CGEN_IFMT ifmt_bcl24 = { - 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } -}; - -/* end-sanitize-m32rx */ -static const CGEN_IFMT ifmt_cmp = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT ifmt_cmpi = { - 32, 32, 0xfff00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } -}; - -/* start-sanitize-m32rx */ -static const CGEN_IFMT ifmt_cmpeq = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -static const CGEN_IFMT ifmt_cmpz = { - 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -/* end-sanitize-m32rx */ -static const CGEN_IFMT ifmt_div = { - 32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } -}; - -/* start-sanitize-m32rx */ -static const CGEN_IFMT ifmt_divh = { - 32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } -}; - -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -static const CGEN_IFMT ifmt_jc = { - 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -/* end-sanitize-m32rx */ -static const CGEN_IFMT ifmt_jl = { - 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT ifmt_ld24 = { - 32, 32, 0xf0000000, { F (F_OP1), F (F_R1), F (F_UIMM24), 0 } -}; - -static const CGEN_IFMT ifmt_ldi16 = { - 32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } -}; - -/* start-sanitize-m32rx */ -static const CGEN_IFMT ifmt_machi_a = { - 16, 16, 0xf070, { F (F_OP1), F (F_R1), F (F_ACC), F (F_OP23), F (F_R2), 0 } -}; - -/* end-sanitize-m32rx */ -static const CGEN_IFMT ifmt_mvfachi = { - 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -/* start-sanitize-m32rx */ -static const CGEN_IFMT ifmt_mvfachi_a = { - 16, 16, 0xf0f3, { F (F_OP1), F (F_R1), F (F_OP2), F (F_ACCS), F (F_OP3), 0 } -}; - -/* end-sanitize-m32rx */ -static const CGEN_IFMT ifmt_mvfc = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT ifmt_mvtachi = { - 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -/* start-sanitize-m32rx */ -static const CGEN_IFMT ifmt_mvtachi_a = { - 16, 16, 0xf0f3, { F (F_OP1), F (F_R1), F (F_OP2), F (F_ACCS), F (F_OP3), 0 } -}; - -/* end-sanitize-m32rx */ -static const CGEN_IFMT ifmt_mvtc = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT ifmt_nop = { - 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -/* start-sanitize-m32rx */ -static const CGEN_IFMT ifmt_rac_dsi = { - 16, 16, 0xf3f2, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 } -}; - -/* end-sanitize-m32rx */ -static const CGEN_IFMT ifmt_seth = { - 32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_HI16), 0 } -}; - -static const CGEN_IFMT ifmt_slli = { - 16, 16, 0xf0e0, { F (F_OP1), F (F_R1), F (F_SHIFT_OP2), F (F_UIMM5), 0 } -}; - -static const CGEN_IFMT ifmt_st_d = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } -}; - -static const CGEN_IFMT ifmt_trap = { - 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_UIMM4), 0 } -}; - -/* start-sanitize-m32rx */ -static const CGEN_IFMT ifmt_satb = { - 32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 } -}; - -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -static const CGEN_IFMT ifmt_sadd = { - 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -/* end-sanitize-m32rx */ -#undef F - -#define A(a) (1 << CONCAT2 (CGEN_INSN_,a)) -#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ -#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) - -/* The instruction table. - This is currently non-static because the simulator accesses it - directly. */ - -const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = -{ - /* Special null first entry. - A `num' value of zero is thus invalid. - Also, the special `invalid' insn resides here. */ - { { 0 }, 0 }, -/* add $dr,$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_ADD, "add", "add", - { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & ifmt_add, { 0xa0 }, - (PTR) & fmt_add_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } - }, -/* add3 $dr,$sr,$hash$slo16 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_ADD3, "add3", "add3", - { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } }, - & ifmt_add3, { 0x80a00000 }, - (PTR) & fmt_add3_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* and $dr,$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_AND, "and", "and", - { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & ifmt_add, { 0xc0 }, - (PTR) & fmt_add_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } - }, -/* and3 $dr,$sr,$uimm16 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_AND3, "and3", "and3", - { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } }, - & ifmt_and3, { 0x80c00000 }, - (PTR) & fmt_and3_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* or $dr,$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_OR, "or", "or", - { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & ifmt_add, { 0xe0 }, - (PTR) & fmt_add_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } - }, -/* or3 $dr,$sr,$hash$ulo16 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_OR3, "or3", "or3", - { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } }, - & ifmt_or3, { 0x80e00000 }, - (PTR) & fmt_or3_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* xor $dr,$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_XOR, "xor", "xor", - { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & ifmt_add, { 0xd0 }, - (PTR) & fmt_add_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } - }, -/* xor3 $dr,$sr,$uimm16 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_XOR3, "xor3", "xor3", - { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } }, - & ifmt_and3, { 0x80d00000 }, - (PTR) & fmt_and3_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* addi $dr,$simm8 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_ADDI, "addi", "addi", - { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, - & ifmt_addi, { 0x4000 }, - (PTR) & fmt_addi_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } - }, -/* addv $dr,$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_ADDV, "addv", "addv", - { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & ifmt_add, { 0x80 }, - (PTR) & fmt_addv_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } - }, -/* addv3 $dr,$sr,$simm16 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_ADDV3, "addv3", "addv3", - { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, - & ifmt_addv3, { 0x80800000 }, - (PTR) & fmt_addv3_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* addx $dr,$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_ADDX, "addx", "addx", - { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & ifmt_add, { 0x90 }, - (PTR) & fmt_addx_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } - }, -/* bc.s $disp8 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_BC8, "bc8", "bc.s", - { { MNEM, ' ', OP (DISP8), 0 } }, - & ifmt_bc8, { 0x7c00 }, - (PTR) & fmt_bc8_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } } - }, -/* bc.l $disp24 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_BC24, "bc24", "bc.l", - { { MNEM, ' ', OP (DISP24), 0 } }, - & ifmt_bc24, { 0xfc000000 }, - (PTR) & fmt_bc24_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* beq $src1,$src2,$disp16 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_BEQ, "beq", "beq", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } }, - & ifmt_beq, { 0xb0000000 }, - (PTR) & fmt_beq_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* beqz $src2,$disp16 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_BEQZ, "beqz", "beqz", - { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, - & ifmt_beqz, { 0xb0800000 }, - (PTR) & fmt_beqz_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* bgez $src2,$disp16 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_BGEZ, "bgez", "bgez", - { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, - & ifmt_beqz, { 0xb0b00000 }, - (PTR) & fmt_beqz_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* bgtz $src2,$disp16 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_BGTZ, "bgtz", "bgtz", - { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, - & ifmt_beqz, { 0xb0d00000 }, - (PTR) & fmt_beqz_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* blez $src2,$disp16 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_BLEZ, "blez", "blez", - { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, - & ifmt_beqz, { 0xb0c00000 }, - (PTR) & fmt_beqz_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* bltz $src2,$disp16 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_BLTZ, "bltz", "bltz", - { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, - & ifmt_beqz, { 0xb0a00000 }, - (PTR) & fmt_beqz_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* bnez $src2,$disp16 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_BNEZ, "bnez", "bnez", - { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, - & ifmt_beqz, { 0xb0900000 }, - (PTR) & fmt_beqz_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* bl.s $disp8 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_BL8, "bl8", "bl.s", - { { MNEM, ' ', OP (DISP8), 0 } }, - & ifmt_bc8, { 0x7e00 }, - (PTR) & fmt_bl8_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } } - }, -/* bl.l $disp24 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_BL24, "bl24", "bl.l", - { { MNEM, ' ', OP (DISP24), 0 } }, - & ifmt_bc24, { 0xfe000000 }, - (PTR) & fmt_bl24_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* start-sanitize-m32rx */ -/* bcl.s $disp8 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_BCL8, "bcl8", "bcl.s", - { { MNEM, ' ', OP (DISP8), 0 } }, - & ifmt_bcl8, { 0x7800 }, - (PTR) & fmt_bcl8_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } } - }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -/* bcl.l $disp24 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_BCL24, "bcl24", "bcl.l", - { { MNEM, ' ', OP (DISP24), 0 } }, - & ifmt_bcl24, { 0xf8000000 }, - (PTR) & fmt_bcl24_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } } - }, -/* end-sanitize-m32rx */ -/* bnc.s $disp8 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_BNC8, "bnc8", "bnc.s", - { { MNEM, ' ', OP (DISP8), 0 } }, - & ifmt_bc8, { 0x7d00 }, - (PTR) & fmt_bc8_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } } - }, -/* bnc.l $disp24 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_BNC24, "bnc24", "bnc.l", - { { MNEM, ' ', OP (DISP24), 0 } }, - & ifmt_bc24, { 0xfd000000 }, - (PTR) & fmt_bc24_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* bne $src1,$src2,$disp16 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_BNE, "bne", "bne", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } }, - & ifmt_beq, { 0xb0100000 }, - (PTR) & fmt_beq_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* bra.s $disp8 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_BRA8, "bra8", "bra.s", - { { MNEM, ' ', OP (DISP8), 0 } }, - & ifmt_bc8, { 0x7f00 }, - (PTR) & fmt_bra8_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } } - }, -/* bra.l $disp24 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_BRA24, "bra24", "bra.l", - { { MNEM, ' ', OP (DISP24), 0 } }, - & ifmt_bc24, { 0xff000000 }, - (PTR) & fmt_bra24_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* start-sanitize-m32rx */ -/* bncl.s $disp8 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_BNCL8, "bncl8", "bncl.s", - { { MNEM, ' ', OP (DISP8), 0 } }, - & ifmt_bcl8, { 0x7900 }, - (PTR) & fmt_bcl8_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } } - }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -/* bncl.l $disp24 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_BNCL24, "bncl24", "bncl.l", - { { MNEM, ' ', OP (DISP24), 0 } }, - & ifmt_bcl24, { 0xf9000000 }, - (PTR) & fmt_bcl24_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } } - }, -/* end-sanitize-m32rx */ -/* cmp $src1,$src2 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_CMP, "cmp", "cmp", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & ifmt_cmp, { 0x40 }, - (PTR) & fmt_cmp_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } - }, -/* cmpi $src2,$simm16 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_CMPI, "cmpi", "cmpi", - { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } }, - & ifmt_cmpi, { 0x80400000 }, - (PTR) & fmt_cmpi_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* cmpu $src1,$src2 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_CMPU, "cmpu", "cmpu", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & ifmt_cmp, { 0x50 }, - (PTR) & fmt_cmp_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } - }, -/* cmpui $src2,$simm16 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_CMPUI, "cmpui", "cmpui", - { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } }, - & ifmt_cmpi, { 0x80500000 }, - (PTR) & fmt_cmpi_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* start-sanitize-m32rx */ -/* cmpeq $src1,$src2 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_CMPEQ, "cmpeq", "cmpeq", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & ifmt_cmpeq, { 0x60 }, - (PTR) & fmt_cmpeq_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } } - }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -/* cmpz $src2 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_CMPZ, "cmpz", "cmpz", - { { MNEM, ' ', OP (SRC2), 0 } }, - & ifmt_cmpz, { 0x70 }, - (PTR) & fmt_cmpz_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } } - }, -/* end-sanitize-m32rx */ -/* div $dr,$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_DIV, "div", "div", - { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & ifmt_div, { 0x90000000 }, - (PTR) & fmt_div_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* divu $dr,$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_DIVU, "divu", "divu", - { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & ifmt_div, { 0x90100000 }, - (PTR) & fmt_div_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* rem $dr,$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_REM, "rem", "rem", - { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & ifmt_div, { 0x90200000 }, - (PTR) & fmt_div_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* remu $dr,$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_REMU, "remu", "remu", - { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & ifmt_div, { 0x90300000 }, - (PTR) & fmt_div_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* start-sanitize-m32rx */ -/* divh $dr,$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_DIVH, "divh", "divh", - { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & ifmt_divh, { 0x90000010 }, - (PTR) & fmt_divh_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } } - }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -/* jc $sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_JC, "jc", "jc", - { { MNEM, ' ', OP (SR), 0 } }, - & ifmt_jc, { 0x1cc0 }, - (PTR) & fmt_jc_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } } - }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -/* jnc $sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_JNC, "jnc", "jnc", - { { MNEM, ' ', OP (SR), 0 } }, - & ifmt_jc, { 0x1dc0 }, - (PTR) & fmt_jc_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } } - }, -/* end-sanitize-m32rx */ -/* jl $sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_JL, "jl", "jl", - { { MNEM, ' ', OP (SR), 0 } }, - & ifmt_jl, { 0x1ec0 }, - (PTR) & fmt_jl_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } } - }, -/* jmp $sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_JMP, "jmp", "jmp", - { { MNEM, ' ', OP (SR), 0 } }, - & ifmt_jl, { 0x1fc0 }, - (PTR) & fmt_jmp_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } } - }, -/* ld $dr,@$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_LD, "ld", "ld", - { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, - & ifmt_add, { 0x20c0 }, - (PTR) & fmt_ld_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } - }, -/* ld $dr,@($slo16,$sr) */ - { - { 1, 1, 1, 1 }, - M32R_INSN_LD_D, "ld-d", "ld", - { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, - & ifmt_add3, { 0xa0c00000 }, - (PTR) & fmt_ld_d_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* ldb $dr,@$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_LDB, "ldb", "ldb", - { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, - & ifmt_add, { 0x2080 }, - (PTR) & fmt_ldb_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } - }, -/* ldb $dr,@($slo16,$sr) */ - { - { 1, 1, 1, 1 }, - M32R_INSN_LDB_D, "ldb-d", "ldb", - { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, - & ifmt_add3, { 0xa0800000 }, - (PTR) & fmt_ldb_d_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* ldh $dr,@$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_LDH, "ldh", "ldh", - { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, - & ifmt_add, { 0x20a0 }, - (PTR) & fmt_ldh_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } - }, -/* ldh $dr,@($slo16,$sr) */ - { - { 1, 1, 1, 1 }, - M32R_INSN_LDH_D, "ldh-d", "ldh", - { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, - & ifmt_add3, { 0xa0a00000 }, - (PTR) & fmt_ldh_d_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* ldub $dr,@$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_LDUB, "ldub", "ldub", - { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, - & ifmt_add, { 0x2090 }, - (PTR) & fmt_ldb_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } - }, -/* ldub $dr,@($slo16,$sr) */ - { - { 1, 1, 1, 1 }, - M32R_INSN_LDUB_D, "ldub-d", "ldub", - { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, - & ifmt_add3, { 0xa0900000 }, - (PTR) & fmt_ldb_d_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* lduh $dr,@$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_LDUH, "lduh", "lduh", - { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, - & ifmt_add, { 0x20b0 }, - (PTR) & fmt_ldh_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } - }, -/* lduh $dr,@($slo16,$sr) */ - { - { 1, 1, 1, 1 }, - M32R_INSN_LDUH_D, "lduh-d", "lduh", - { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, - & ifmt_add3, { 0xa0b00000 }, - (PTR) & fmt_ldh_d_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* ld $dr,@$sr+ */ - { - { 1, 1, 1, 1 }, - M32R_INSN_LD_PLUS, "ld-plus", "ld", - { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } }, - & ifmt_add, { 0x20e0 }, - (PTR) & fmt_ld_plus_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } - }, -/* ld24 $dr,$uimm24 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_LD24, "ld24", "ld24", - { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } }, - & ifmt_ld24, { 0xe0000000 }, - (PTR) & fmt_ld24_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* ldi8 $dr,$simm8 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_LDI8, "ldi8", "ldi8", - { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, - & ifmt_addi, { 0x6000 }, - (PTR) & fmt_ldi8_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } - }, -/* ldi16 $dr,$hash$slo16 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_LDI16, "ldi16", "ldi16", - { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } }, - & ifmt_ldi16, { 0x90f00000 }, - (PTR) & fmt_ldi16_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* lock $dr,@$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_LOCK, "lock", "lock", - { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, - & ifmt_add, { 0x20d0 }, - (PTR) & fmt_lock_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } - }, -/* machi $src1,$src2 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MACHI, "machi", "machi", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & ifmt_cmp, { 0x3040 }, - (PTR) & fmt_machi_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } - }, -/* start-sanitize-m32rx */ -/* machi $src1,$src2,$acc */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MACHI_A, "machi-a", "machi", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, - & ifmt_machi_a, { 0x3040 }, - (PTR) & fmt_machi_a_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } - }, -/* end-sanitize-m32rx */ -/* maclo $src1,$src2 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MACLO, "maclo", "maclo", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & ifmt_cmp, { 0x3050 }, - (PTR) & fmt_machi_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } - }, -/* start-sanitize-m32rx */ -/* maclo $src1,$src2,$acc */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MACLO_A, "maclo-a", "maclo", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, - & ifmt_machi_a, { 0x3050 }, - (PTR) & fmt_machi_a_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } - }, -/* end-sanitize-m32rx */ -/* macwhi $src1,$src2 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MACWHI, "macwhi", "macwhi", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & ifmt_cmp, { 0x3060 }, - (PTR) & fmt_machi_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } - }, -/* start-sanitize-m32rx */ -/* macwhi $src1,$src2,$acc */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, - & ifmt_machi_a, { 0x3060 }, - (PTR) & fmt_machi_a_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } } - }, -/* end-sanitize-m32rx */ -/* macwlo $src1,$src2 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MACWLO, "macwlo", "macwlo", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & ifmt_cmp, { 0x3070 }, - (PTR) & fmt_machi_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } - }, -/* start-sanitize-m32rx */ -/* macwlo $src1,$src2,$acc */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, - & ifmt_machi_a, { 0x3070 }, - (PTR) & fmt_machi_a_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } } - }, -/* end-sanitize-m32rx */ -/* mul $dr,$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MUL, "mul", "mul", - { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & ifmt_add, { 0x1060 }, - (PTR) & fmt_add_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_S } } - }, -/* mulhi $src1,$src2 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MULHI, "mulhi", "mulhi", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & ifmt_cmp, { 0x3000 }, - (PTR) & fmt_mulhi_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } - }, -/* start-sanitize-m32rx */ -/* mulhi $src1,$src2,$acc */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MULHI_A, "mulhi-a", "mulhi", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, - & ifmt_machi_a, { 0x3000 }, - (PTR) & fmt_mulhi_a_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } - }, -/* end-sanitize-m32rx */ -/* mullo $src1,$src2 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MULLO, "mullo", "mullo", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & ifmt_cmp, { 0x3010 }, - (PTR) & fmt_mulhi_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } - }, -/* start-sanitize-m32rx */ -/* mullo $src1,$src2,$acc */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MULLO_A, "mullo-a", "mullo", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, - & ifmt_machi_a, { 0x3010 }, - (PTR) & fmt_mulhi_a_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } - }, -/* end-sanitize-m32rx */ -/* mulwhi $src1,$src2 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MULWHI, "mulwhi", "mulwhi", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & ifmt_cmp, { 0x3020 }, - (PTR) & fmt_mulhi_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } - }, -/* start-sanitize-m32rx */ -/* mulwhi $src1,$src2,$acc */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, - & ifmt_machi_a, { 0x3020 }, - (PTR) & fmt_mulhi_a_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } } - }, -/* end-sanitize-m32rx */ -/* mulwlo $src1,$src2 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MULWLO, "mulwlo", "mulwlo", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & ifmt_cmp, { 0x3030 }, - (PTR) & fmt_mulhi_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } - }, -/* start-sanitize-m32rx */ -/* mulwlo $src1,$src2,$acc */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, - & ifmt_machi_a, { 0x3030 }, - (PTR) & fmt_mulhi_a_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } } - }, -/* end-sanitize-m32rx */ -/* mv $dr,$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MV, "mv", "mv", - { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & ifmt_add, { 0x1080 }, - (PTR) & fmt_mv_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } - }, -/* mvfachi $dr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MVFACHI, "mvfachi", "mvfachi", - { { MNEM, ' ', OP (DR), 0 } }, - & ifmt_mvfachi, { 0x50f0 }, - (PTR) & fmt_mvfachi_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } - }, -/* start-sanitize-m32rx */ -/* mvfachi $dr,$accs */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", - { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } }, - & ifmt_mvfachi_a, { 0x50f0 }, - (PTR) & fmt_mvfachi_a_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } - }, -/* end-sanitize-m32rx */ -/* mvfaclo $dr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo", - { { MNEM, ' ', OP (DR), 0 } }, - & ifmt_mvfachi, { 0x50f1 }, - (PTR) & fmt_mvfachi_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } - }, -/* start-sanitize-m32rx */ -/* mvfaclo $dr,$accs */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", - { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } }, - & ifmt_mvfachi_a, { 0x50f1 }, - (PTR) & fmt_mvfachi_a_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } - }, -/* end-sanitize-m32rx */ -/* mvfacmi $dr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi", - { { MNEM, ' ', OP (DR), 0 } }, - & ifmt_mvfachi, { 0x50f2 }, - (PTR) & fmt_mvfachi_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } - }, -/* start-sanitize-m32rx */ -/* mvfacmi $dr,$accs */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", - { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } }, - & ifmt_mvfachi_a, { 0x50f2 }, - (PTR) & fmt_mvfachi_a_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } - }, -/* end-sanitize-m32rx */ -/* mvfc $dr,$scr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MVFC, "mvfc", "mvfc", - { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } }, - & ifmt_mvfc, { 0x1090 }, - (PTR) & fmt_mvfc_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } - }, -/* mvtachi $src1 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MVTACHI, "mvtachi", "mvtachi", - { { MNEM, ' ', OP (SRC1), 0 } }, - & ifmt_mvtachi, { 0x5070 }, - (PTR) & fmt_mvtachi_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } - }, -/* start-sanitize-m32rx */ -/* mvtachi $src1,$accs */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", - { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } }, - & ifmt_mvtachi_a, { 0x5070 }, - (PTR) & fmt_mvtachi_a_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } - }, -/* end-sanitize-m32rx */ -/* mvtaclo $src1 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo", - { { MNEM, ' ', OP (SRC1), 0 } }, - & ifmt_mvtachi, { 0x5071 }, - (PTR) & fmt_mvtachi_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } - }, -/* start-sanitize-m32rx */ -/* mvtaclo $src1,$accs */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", - { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } }, - & ifmt_mvtachi_a, { 0x5071 }, - (PTR) & fmt_mvtachi_a_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } - }, -/* end-sanitize-m32rx */ -/* mvtc $sr,$dcr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MVTC, "mvtc", "mvtc", - { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } }, - & ifmt_mvtc, { 0x10a0 }, - (PTR) & fmt_mvtc_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } - }, -/* neg $dr,$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_NEG, "neg", "neg", - { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & ifmt_add, { 0x30 }, - (PTR) & fmt_mv_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } - }, -/* nop */ - { - { 1, 1, 1, 1 }, - M32R_INSN_NOP, "nop", "nop", - { { MNEM, 0 } }, - & ifmt_nop, { 0x7000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } - }, -/* not $dr,$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_NOT, "not", "not", - { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & ifmt_add, { 0xb0 }, - (PTR) & fmt_mv_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } - }, -/* rac */ - { - { 1, 1, 1, 1 }, - M32R_INSN_RAC, "rac", "rac", - { { MNEM, 0 } }, - & ifmt_nop, { 0x5090 }, - (PTR) & fmt_rac_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } - }, -/* start-sanitize-m32rx */ -/* rac $accd,$accs,$imm1 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_RAC_DSI, "rac-dsi", "rac", - { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } }, - & ifmt_rac_dsi, { 0x5090 }, - (PTR) & fmt_rac_dsi_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } - }, -/* end-sanitize-m32rx */ -/* rach */ - { - { 1, 1, 1, 1 }, - M32R_INSN_RACH, "rach", "rach", - { { MNEM, 0 } }, - & ifmt_nop, { 0x5080 }, - (PTR) & fmt_rac_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } - }, -/* start-sanitize-m32rx */ -/* rach $accd,$accs,$imm1 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_RACH_DSI, "rach-dsi", "rach", - { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } }, - & ifmt_rac_dsi, { 0x5080 }, - (PTR) & fmt_rac_dsi_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } - }, -/* end-sanitize-m32rx */ -/* rte */ - { - { 1, 1, 1, 1 }, - M32R_INSN_RTE, "rte", "rte", - { { MNEM, 0 } }, - & ifmt_nop, { 0x10d6 }, - (PTR) & fmt_rte_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } } - }, -/* seth $dr,$hash$hi16 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_SETH, "seth", "seth", - { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } }, - & ifmt_seth, { 0xd0c00000 }, - (PTR) & fmt_seth_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* sll $dr,$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_SLL, "sll", "sll", - { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & ifmt_add, { 0x1040 }, - (PTR) & fmt_add_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } - }, -/* sll3 $dr,$sr,$simm16 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_SLL3, "sll3", "sll3", - { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, - & ifmt_addv3, { 0x90c00000 }, - (PTR) & fmt_sll3_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* slli $dr,$uimm5 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_SLLI, "slli", "slli", - { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } }, - & ifmt_slli, { 0x5040 }, - (PTR) & fmt_slli_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } - }, -/* sra $dr,$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_SRA, "sra", "sra", - { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & ifmt_add, { 0x1020 }, - (PTR) & fmt_add_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } - }, -/* sra3 $dr,$sr,$simm16 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_SRA3, "sra3", "sra3", - { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, - & ifmt_addv3, { 0x90a00000 }, - (PTR) & fmt_sll3_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* srai $dr,$uimm5 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_SRAI, "srai", "srai", - { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } }, - & ifmt_slli, { 0x5020 }, - (PTR) & fmt_slli_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } - }, -/* srl $dr,$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_SRL, "srl", "srl", - { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & ifmt_add, { 0x1000 }, - (PTR) & fmt_add_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } - }, -/* srl3 $dr,$sr,$simm16 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_SRL3, "srl3", "srl3", - { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, - & ifmt_addv3, { 0x90800000 }, - (PTR) & fmt_sll3_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* srli $dr,$uimm5 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_SRLI, "srli", "srli", - { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } }, - & ifmt_slli, { 0x5000 }, - (PTR) & fmt_slli_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } - }, -/* st $src1,@$src2 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_ST, "st", "st", - { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, - & ifmt_cmp, { 0x2040 }, - (PTR) & fmt_st_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } - }, -/* st $src1,@($slo16,$src2) */ - { - { 1, 1, 1, 1 }, - M32R_INSN_ST_D, "st-d", "st", - { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } }, - & ifmt_st_d, { 0xa0400000 }, - (PTR) & fmt_st_d_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* stb $src1,@$src2 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_STB, "stb", "stb", - { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, - & ifmt_cmp, { 0x2000 }, - (PTR) & fmt_stb_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } - }, -/* stb $src1,@($slo16,$src2) */ - { - { 1, 1, 1, 1 }, - M32R_INSN_STB_D, "stb-d", "stb", - { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } }, - & ifmt_st_d, { 0xa0000000 }, - (PTR) & fmt_stb_d_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* sth $src1,@$src2 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_STH, "sth", "sth", - { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, - & ifmt_cmp, { 0x2020 }, - (PTR) & fmt_sth_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } - }, -/* sth $src1,@($slo16,$src2) */ - { - { 1, 1, 1, 1 }, - M32R_INSN_STH_D, "sth-d", "sth", - { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } }, - & ifmt_st_d, { 0xa0200000 }, - (PTR) & fmt_sth_d_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } - }, -/* st $src1,@+$src2 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_ST_PLUS, "st-plus", "st", - { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } }, - & ifmt_cmp, { 0x2060 }, - (PTR) & fmt_st_plus_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } - }, -/* st $src1,@-$src2 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_ST_MINUS, "st-minus", "st", - { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } }, - & ifmt_cmp, { 0x2070 }, - (PTR) & fmt_st_plus_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } - }, -/* sub $dr,$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_SUB, "sub", "sub", - { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & ifmt_add, { 0x20 }, - (PTR) & fmt_add_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } - }, -/* subv $dr,$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_SUBV, "subv", "subv", - { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & ifmt_add, { 0x0 }, - (PTR) & fmt_addv_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } - }, -/* subx $dr,$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_SUBX, "subx", "subx", - { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & ifmt_add, { 0x10 }, - (PTR) & fmt_addx_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } - }, -/* trap $uimm4 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_TRAP, "trap", "trap", - { { MNEM, ' ', OP (UIMM4), 0 } }, - & ifmt_trap, { 0x10f0 }, - (PTR) & fmt_trap_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } } - }, -/* unlock $src1,@$src2 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_UNLOCK, "unlock", "unlock", - { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, - & ifmt_cmp, { 0x2050 }, - (PTR) & fmt_unlock_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } - }, -/* start-sanitize-m32rx */ -/* satb $dr,$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_SATB, "satb", "satb", - { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & ifmt_satb, { 0x80600300 }, - (PTR) & fmt_satb_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } } - }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -/* sath $dr,$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_SATH, "sath", "sath", - { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & ifmt_satb, { 0x80600200 }, - (PTR) & fmt_satb_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } } - }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -/* sat $dr,$sr */ - { - { 1, 1, 1, 1 }, - M32R_INSN_SAT, "sat", "sat", - { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & ifmt_satb, { 0x80600000 }, - (PTR) & fmt_sat_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } } - }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -/* pcmpbz $src2 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", - { { MNEM, ' ', OP (SRC2), 0 } }, - & ifmt_cmpz, { 0x370 }, - (PTR) & fmt_cmpz_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } } - }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -/* sadd */ - { - { 1, 1, 1, 1 }, - M32R_INSN_SADD, "sadd", "sadd", - { { MNEM, 0 } }, - & ifmt_sadd, { 0x50e4 }, - (PTR) & fmt_sadd_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } - }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -/* macwu1 $src1,$src2 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MACWU1, "macwu1", "macwu1", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & ifmt_cmpeq, { 0x50b0 }, - (PTR) & fmt_macwu1_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } - }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -/* msblo $src1,$src2 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MSBLO, "msblo", "msblo", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & ifmt_cmpeq, { 0x50d0 }, - (PTR) & fmt_msblo_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } - }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -/* mulwu1 $src1,$src2 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MULWU1, "mulwu1", "mulwu1", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & ifmt_cmpeq, { 0x50a0 }, - (PTR) & fmt_mulwu1_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } - }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -/* maclh1 $src1,$src2 */ - { - { 1, 1, 1, 1 }, - M32R_INSN_MACLH1, "maclh1", "maclh1", - { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & ifmt_cmpeq, { 0x50c0 }, - (PTR) & fmt_macwu1_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } - }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -/* sc */ - { - { 1, 1, 1, 1 }, - M32R_INSN_SC, "sc", "sc", - { { MNEM, 0 } }, - & ifmt_sadd, { 0x7401 }, - (PTR) & fmt_sc_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } } - }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -/* snc */ - { - { 1, 1, 1, 1 }, - M32R_INSN_SNC, "snc", "snc", - { { MNEM, 0 } }, - & ifmt_sadd, { 0x7501 }, - (PTR) & fmt_sc_ops[0], - { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } } - }, -/* end-sanitize-m32rx */ -}; - -#undef A -#undef MNEM -#undef OP - -static const CGEN_INSN_TABLE insn_table = -{ - & m32r_cgen_insn_table_entries[0], - sizeof (CGEN_INSN), - MAX_INSNS, - NULL -}; - -/* Formats for ALIAS macro-insns. */ - -#define F(f) & m32r_cgen_ifld_table[CONCAT2 (M32R_,f)] - -static const CGEN_IFMT ifmt_bc8r = { - 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } -}; - -static const CGEN_IFMT ifmt_bc24r = { - 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } -}; - -static const CGEN_IFMT ifmt_bl8r = { - 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } -}; - -static const CGEN_IFMT ifmt_bl24r = { - 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } -}; - -/* start-sanitize-m32rx */ -static const CGEN_IFMT ifmt_bcl8r = { - 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } -}; - -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -static const CGEN_IFMT ifmt_bcl24r = { - 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } -}; - -/* end-sanitize-m32rx */ -static const CGEN_IFMT ifmt_bnc8r = { - 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } -}; - -static const CGEN_IFMT ifmt_bnc24r = { - 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } -}; - -static const CGEN_IFMT ifmt_bra8r = { - 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } -}; - -static const CGEN_IFMT ifmt_bra24r = { - 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } -}; - -/* start-sanitize-m32rx */ -static const CGEN_IFMT ifmt_bncl8r = { - 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } -}; - -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -static const CGEN_IFMT ifmt_bncl24r = { - 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } -}; - -/* end-sanitize-m32rx */ -static const CGEN_IFMT ifmt_ld_2 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT ifmt_ld_d2 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } -}; - -static const CGEN_IFMT ifmt_ldb_2 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT ifmt_ldb_d2 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } -}; - -static const CGEN_IFMT ifmt_ldh_2 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT ifmt_ldh_d2 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } -}; - -static const CGEN_IFMT ifmt_ldub_2 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT ifmt_ldub_d2 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } -}; - -static const CGEN_IFMT ifmt_lduh_2 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT ifmt_lduh_d2 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } -}; - -static const CGEN_IFMT ifmt_pop = { - 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT ifmt_ldi8a = { - 16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 } -}; - -static const CGEN_IFMT ifmt_ldi16a = { - 32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } -}; - -/* start-sanitize-m32rx */ -static const CGEN_IFMT ifmt_rac_d = { - 16, 16, 0xf3ff, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 } -}; - -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -static const CGEN_IFMT ifmt_rac_ds = { - 16, 16, 0xf3f3, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 } -}; - -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -static const CGEN_IFMT ifmt_rach_d = { - 16, 16, 0xf3ff, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 } -}; - -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -static const CGEN_IFMT ifmt_rach_ds = { - 16, 16, 0xf3f3, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 } -}; - -/* end-sanitize-m32rx */ -static const CGEN_IFMT ifmt_st_2 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT ifmt_st_d2 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } -}; - -static const CGEN_IFMT ifmt_stb_2 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT ifmt_stb_d2 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } -}; - -static const CGEN_IFMT ifmt_sth_2 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT ifmt_sth_d2 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } -}; - -static const CGEN_IFMT ifmt_push = { - 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -#undef F - -/* Each non-simple macro entry points to an array of expansion possibilities. */ - -#define A(a) (1 << CONCAT2 (CGEN_INSN_,a)) -#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ -#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) - -/* The macro instruction table. */ - -static const CGEN_INSN macro_insn_table_entries[] = -{ -/* bc $disp8 */ - { - { 1, 1, 1, 1 }, - -1, "bc8r", "bc", - { { MNEM, ' ', OP (DISP8), 0 } }, - & ifmt_bc8r, { 0x7c00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } - }, -/* bc $disp24 */ - { - { 1, 1, 1, 1 }, - -1, "bc24r", "bc", - { { MNEM, ' ', OP (DISP24), 0 } }, - & ifmt_bc24r, { 0xfc000000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* bl $disp8 */ - { - { 1, 1, 1, 1 }, - -1, "bl8r", "bl", - { { MNEM, ' ', OP (DISP8), 0 } }, - & ifmt_bl8r, { 0x7e00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } - }, -/* bl $disp24 */ - { - { 1, 1, 1, 1 }, - -1, "bl24r", "bl", - { { MNEM, ' ', OP (DISP24), 0 } }, - & ifmt_bl24r, { 0xfe000000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* start-sanitize-m32rx */ -/* bcl $disp8 */ - { - { 1, 1, 1, 1 }, - -1, "bcl8r", "bcl", - { { MNEM, ' ', OP (DISP8), 0 } }, - & ifmt_bcl8r, { 0x7800 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } } - }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -/* bcl $disp24 */ - { - { 1, 1, 1, 1 }, - -1, "bcl24r", "bcl", - { { MNEM, ' ', OP (DISP24), 0 } }, - & ifmt_bcl24r, { 0xf8000000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } } - }, -/* end-sanitize-m32rx */ -/* bnc $disp8 */ - { - { 1, 1, 1, 1 }, - -1, "bnc8r", "bnc", - { { MNEM, ' ', OP (DISP8), 0 } }, - & ifmt_bnc8r, { 0x7d00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } - }, -/* bnc $disp24 */ - { - { 1, 1, 1, 1 }, - -1, "bnc24r", "bnc", - { { MNEM, ' ', OP (DISP24), 0 } }, - & ifmt_bnc24r, { 0xfd000000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* bra $disp8 */ - { - { 1, 1, 1, 1 }, - -1, "bra8r", "bra", - { { MNEM, ' ', OP (DISP8), 0 } }, - & ifmt_bra8r, { 0x7f00 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } - }, -/* bra $disp24 */ - { - { 1, 1, 1, 1 }, - -1, "bra24r", "bra", - { { MNEM, ' ', OP (DISP24), 0 } }, - & ifmt_bra24r, { 0xff000000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* start-sanitize-m32rx */ -/* bncl $disp8 */ - { - { 1, 1, 1, 1 }, - -1, "bncl8r", "bncl", - { { MNEM, ' ', OP (DISP8), 0 } }, - & ifmt_bncl8r, { 0x7900 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } } - }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -/* bncl $disp24 */ - { - { 1, 1, 1, 1 }, - -1, "bncl24r", "bncl", - { { MNEM, ' ', OP (DISP24), 0 } }, - & ifmt_bncl24r, { 0xf9000000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } } - }, -/* end-sanitize-m32rx */ -/* ld $dr,@($sr) */ - { - { 1, 1, 1, 1 }, - -1, "ld-2", "ld", - { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, - & ifmt_ld_2, { 0x20c0 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } - }, -/* ld $dr,@($sr,$slo16) */ - { - { 1, 1, 1, 1 }, - -1, "ld-d2", "ld", - { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, - & ifmt_ld_d2, { 0xa0c00000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* ldb $dr,@($sr) */ - { - { 1, 1, 1, 1 }, - -1, "ldb-2", "ldb", - { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, - & ifmt_ldb_2, { 0x2080 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } - }, -/* ldb $dr,@($sr,$slo16) */ - { - { 1, 1, 1, 1 }, - -1, "ldb-d2", "ldb", - { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, - & ifmt_ldb_d2, { 0xa0800000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* ldh $dr,@($sr) */ - { - { 1, 1, 1, 1 }, - -1, "ldh-2", "ldh", - { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, - & ifmt_ldh_2, { 0x20a0 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } - }, -/* ldh $dr,@($sr,$slo16) */ - { - { 1, 1, 1, 1 }, - -1, "ldh-d2", "ldh", - { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, - & ifmt_ldh_d2, { 0xa0a00000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* ldub $dr,@($sr) */ - { - { 1, 1, 1, 1 }, - -1, "ldub-2", "ldub", - { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, - & ifmt_ldub_2, { 0x2090 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } - }, -/* ldub $dr,@($sr,$slo16) */ - { - { 1, 1, 1, 1 }, - -1, "ldub-d2", "ldub", - { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, - & ifmt_ldub_d2, { 0xa0900000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* lduh $dr,@($sr) */ - { - { 1, 1, 1, 1 }, - -1, "lduh-2", "lduh", - { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, - & ifmt_lduh_2, { 0x20b0 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } - }, -/* lduh $dr,@($sr,$slo16) */ - { - { 1, 1, 1, 1 }, - -1, "lduh-d2", "lduh", - { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, - & ifmt_lduh_d2, { 0xa0b00000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* pop $dr */ - { - { 1, 1, 1, 1 }, - -1, "pop", "pop", - { { MNEM, ' ', OP (DR), 0 } }, - & ifmt_pop, { 0x20ef }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* ldi $dr,$simm8 */ - { - { 1, 1, 1, 1 }, - -1, "ldi8a", "ldi", - { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, - & ifmt_ldi8a, { 0x6000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_OS } } - }, -/* ldi $dr,$hash$slo16 */ - { - { 1, 1, 1, 1 }, - -1, "ldi16a", "ldi", - { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } }, - & ifmt_ldi16a, { 0x90f00000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* start-sanitize-m32rx */ -/* rac $accd */ - { - { 1, 1, 1, 1 }, - -1, "rac-d", "rac", - { { MNEM, ' ', OP (ACCD), 0 } }, - & ifmt_rac_d, { 0x5090 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } } - }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -/* rac $accd,$accs */ - { - { 1, 1, 1, 1 }, - -1, "rac-ds", "rac", - { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } }, - & ifmt_rac_ds, { 0x5090 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } } - }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -/* rach $accd */ - { - { 1, 1, 1, 1 }, - -1, "rach-d", "rach", - { { MNEM, ' ', OP (ACCD), 0 } }, - & ifmt_rach_d, { 0x5080 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } } - }, -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -/* rach $accd,$accs */ - { - { 1, 1, 1, 1 }, - -1, "rach-ds", "rach", - { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } }, - & ifmt_rach_ds, { 0x5080 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } } - }, -/* end-sanitize-m32rx */ -/* st $src1,@($src2) */ - { - { 1, 1, 1, 1 }, - -1, "st-2", "st", - { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } }, - & ifmt_st_2, { 0x2040 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } - }, -/* st $src1,@($src2,$slo16) */ - { - { 1, 1, 1, 1 }, - -1, "st-d2", "st", - { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } }, - & ifmt_st_d2, { 0xa0400000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* stb $src1,@($src2) */ - { - { 1, 1, 1, 1 }, - -1, "stb-2", "stb", - { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } }, - & ifmt_stb_2, { 0x2000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } - }, -/* stb $src1,@($src2,$slo16) */ - { - { 1, 1, 1, 1 }, - -1, "stb-d2", "stb", - { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } }, - & ifmt_stb_d2, { 0xa0000000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* sth $src1,@($src2) */ - { - { 1, 1, 1, 1 }, - -1, "sth-2", "sth", - { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } }, - & ifmt_sth_2, { 0x2020 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } - }, -/* sth $src1,@($src2,$slo16) */ - { - { 1, 1, 1, 1 }, - -1, "sth-d2", "sth", - { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } }, - & ifmt_sth_d2, { 0xa0200000 }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } - }, -/* push $src1 */ - { - { 1, 1, 1, 1 }, - -1, "push", "push", - { { MNEM, ' ', OP (SRC1), 0 } }, - & ifmt_push, { 0x207f }, - (PTR) 0, - { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } - }, -}; - -#undef A -#undef MNEM -#undef OP - -static const CGEN_INSN_TABLE macro_insn_table = -{ - & macro_insn_table_entries[0], - sizeof (CGEN_INSN), - (sizeof (macro_insn_table_entries) / - sizeof (macro_insn_table_entries[0])), - NULL -}; - -static void -init_tables () -{ -} - -/* Return non-zero if INSN is to be added to the hash table. - Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */ - -static int -asm_hash_insn_p (insn) - const CGEN_INSN * insn; -{ - return CGEN_ASM_HASH_P (insn); -} - -static int -dis_hash_insn_p (insn) - const CGEN_INSN * insn; -{ - /* If building the hash table and the NO-DIS attribute is present, - ignore. */ - if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS)) - return 0; - return CGEN_DIS_HASH_P (insn); -} - -/* The result is the hash value of the insn. - Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */ - -static unsigned int -asm_hash_insn (mnem) - const char * mnem; -{ - return CGEN_ASM_HASH (mnem); -} - -/* BUF is a pointer to the insn's bytes in target order. - VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits, - host order. */ - -static unsigned int -dis_hash_insn (buf, value) - const char * buf; - CGEN_INSN_INT value; -{ - return CGEN_DIS_HASH (buf, value); -} - -/* Initialize an opcode table and return a descriptor. - It's much like opening a file, and must be the first function called. */ - -CGEN_OPCODE_DESC -m32r_cgen_opcode_open (mach, endian) - int mach; - enum cgen_endian endian; -{ - CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE)); - static int init_p; - - if (! init_p) - { - init_tables (); - init_p = 1; - } - - memset (table, 0, sizeof (*table)); - - CGEN_OPCODE_MACH (table) = mach; - CGEN_OPCODE_ENDIAN (table) = endian; - /* FIXME: for the sparc case we can determine insn-endianness statically. - The worry here is where both data and insn endian can be independently - chosen, in which case this function will need another argument. - Actually, will want to allow for more arguments in the future anyway. */ - CGEN_OPCODE_INSN_ENDIAN (table) = endian; - - CGEN_OPCODE_HW_LIST (table) = & m32r_cgen_hw_entries[0]; - - CGEN_OPCODE_IFLD_TABLE (table) = & m32r_cgen_ifld_table[0]; - - CGEN_OPCODE_OPERAND_TABLE (table) = & m32r_cgen_operand_table[0]; - - * CGEN_OPCODE_INSN_TABLE (table) = insn_table; - - * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table; - - CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p; - CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn; - CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE; - - CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p; - CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn; - CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE; - - return (CGEN_OPCODE_DESC) table; -} - -/* Close an opcode table. */ - -void -m32r_cgen_opcode_close (desc) - CGEN_OPCODE_DESC desc; -{ - free (desc); -} - -/* Getting values from cgen_fields is handled by a collection of functions. - They are distinguished by the type of the VALUE argument they return. - TODO: floating point, inlining support, remove cases where result type - not appropriate. */ - -int -m32r_cgen_get_int_operand (opindex, fields) - int opindex; - const CGEN_FIELDS * fields; -{ - int value; - - switch (opindex) - { - case M32R_OPERAND_SR : - value = fields->f_r2; - break; - case M32R_OPERAND_DR : - value = fields->f_r1; - break; - case M32R_OPERAND_SRC1 : - value = fields->f_r1; - break; - case M32R_OPERAND_SRC2 : - value = fields->f_r2; - break; - case M32R_OPERAND_SCR : - value = fields->f_r2; - break; - case M32R_OPERAND_DCR : - value = fields->f_r1; - break; - case M32R_OPERAND_SIMM8 : - value = fields->f_simm8; - break; - case M32R_OPERAND_SIMM16 : - value = fields->f_simm16; - break; - case M32R_OPERAND_UIMM4 : - value = fields->f_uimm4; - break; - case M32R_OPERAND_UIMM5 : - value = fields->f_uimm5; - break; - case M32R_OPERAND_UIMM16 : - value = fields->f_uimm16; - break; -/* start-sanitize-m32rx */ - case M32R_OPERAND_IMM1 : - value = fields->f_imm1; - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACCD : - value = fields->f_accd; - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACCS : - value = fields->f_accs; - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACC : - value = fields->f_acc; - break; -/* end-sanitize-m32rx */ - case M32R_OPERAND_HASH : - value = fields->f_nil; - break; - case M32R_OPERAND_HI16 : - value = fields->f_hi16; - break; - case M32R_OPERAND_SLO16 : - value = fields->f_simm16; - break; - case M32R_OPERAND_ULO16 : - value = fields->f_uimm16; - break; - case M32R_OPERAND_UIMM24 : - value = fields->f_uimm24; - break; - case M32R_OPERAND_DISP8 : - value = fields->f_disp8; - break; - case M32R_OPERAND_DISP16 : - value = fields->f_disp16; - break; - case M32R_OPERAND_DISP24 : - value = fields->f_disp24; - break; - - default : - /* xgettext:c-format */ - fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), - opindex); - abort (); - } - - return value; -} - -bfd_vma -m32r_cgen_get_vma_operand (opindex, fields) - int opindex; - const CGEN_FIELDS * fields; -{ - bfd_vma value; - - switch (opindex) - { - case M32R_OPERAND_SR : - value = fields->f_r2; - break; - case M32R_OPERAND_DR : - value = fields->f_r1; - break; - case M32R_OPERAND_SRC1 : - value = fields->f_r1; - break; - case M32R_OPERAND_SRC2 : - value = fields->f_r2; - break; - case M32R_OPERAND_SCR : - value = fields->f_r2; - break; - case M32R_OPERAND_DCR : - value = fields->f_r1; - break; - case M32R_OPERAND_SIMM8 : - value = fields->f_simm8; - break; - case M32R_OPERAND_SIMM16 : - value = fields->f_simm16; - break; - case M32R_OPERAND_UIMM4 : - value = fields->f_uimm4; - break; - case M32R_OPERAND_UIMM5 : - value = fields->f_uimm5; - break; - case M32R_OPERAND_UIMM16 : - value = fields->f_uimm16; - break; -/* start-sanitize-m32rx */ - case M32R_OPERAND_IMM1 : - value = fields->f_imm1; - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACCD : - value = fields->f_accd; - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACCS : - value = fields->f_accs; - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACC : - value = fields->f_acc; - break; -/* end-sanitize-m32rx */ - case M32R_OPERAND_HASH : - value = fields->f_nil; - break; - case M32R_OPERAND_HI16 : - value = fields->f_hi16; - break; - case M32R_OPERAND_SLO16 : - value = fields->f_simm16; - break; - case M32R_OPERAND_ULO16 : - value = fields->f_uimm16; - break; - case M32R_OPERAND_UIMM24 : - value = fields->f_uimm24; - break; - case M32R_OPERAND_DISP8 : - value = fields->f_disp8; - break; - case M32R_OPERAND_DISP16 : - value = fields->f_disp16; - break; - case M32R_OPERAND_DISP24 : - value = fields->f_disp24; - break; - - default : - /* xgettext:c-format */ - fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), - opindex); - abort (); - } - - return value; -} - -/* Stuffing values in cgen_fields is handled by a collection of functions. - They are distinguished by the type of the VALUE argument they accept. - TODO: floating point, inlining support, remove cases where argument type - not appropriate. */ - -void -m32r_cgen_set_int_operand (opindex, fields, value) - int opindex; - CGEN_FIELDS * fields; - int value; -{ - switch (opindex) - { - case M32R_OPERAND_SR : - fields->f_r2 = value; - break; - case M32R_OPERAND_DR : - fields->f_r1 = value; - break; - case M32R_OPERAND_SRC1 : - fields->f_r1 = value; - break; - case M32R_OPERAND_SRC2 : - fields->f_r2 = value; - break; - case M32R_OPERAND_SCR : - fields->f_r2 = value; - break; - case M32R_OPERAND_DCR : - fields->f_r1 = value; - break; - case M32R_OPERAND_SIMM8 : - fields->f_simm8 = value; - break; - case M32R_OPERAND_SIMM16 : - fields->f_simm16 = value; - break; - case M32R_OPERAND_UIMM4 : - fields->f_uimm4 = value; - break; - case M32R_OPERAND_UIMM5 : - fields->f_uimm5 = value; - break; - case M32R_OPERAND_UIMM16 : - fields->f_uimm16 = value; - break; -/* start-sanitize-m32rx */ - case M32R_OPERAND_IMM1 : - fields->f_imm1 = value; - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACCD : - fields->f_accd = value; - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACCS : - fields->f_accs = value; - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACC : - fields->f_acc = value; - break; -/* end-sanitize-m32rx */ - case M32R_OPERAND_HASH : - fields->f_nil = value; - break; - case M32R_OPERAND_HI16 : - fields->f_hi16 = value; - break; - case M32R_OPERAND_SLO16 : - fields->f_simm16 = value; - break; - case M32R_OPERAND_ULO16 : - fields->f_uimm16 = value; - break; - case M32R_OPERAND_UIMM24 : - fields->f_uimm24 = value; - break; - case M32R_OPERAND_DISP8 : - fields->f_disp8 = value; - break; - case M32R_OPERAND_DISP16 : - fields->f_disp16 = value; - break; - case M32R_OPERAND_DISP24 : - fields->f_disp24 = value; - break; - - default : - /* xgettext:c-format */ - fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), - opindex); - abort (); - } -} - -void -m32r_cgen_set_vma_operand (opindex, fields, value) - int opindex; - CGEN_FIELDS * fields; - bfd_vma value; -{ - switch (opindex) - { - case M32R_OPERAND_SR : - fields->f_r2 = value; - break; - case M32R_OPERAND_DR : - fields->f_r1 = value; - break; - case M32R_OPERAND_SRC1 : - fields->f_r1 = value; - break; - case M32R_OPERAND_SRC2 : - fields->f_r2 = value; - break; - case M32R_OPERAND_SCR : - fields->f_r2 = value; - break; - case M32R_OPERAND_DCR : - fields->f_r1 = value; - break; - case M32R_OPERAND_SIMM8 : - fields->f_simm8 = value; - break; - case M32R_OPERAND_SIMM16 : - fields->f_simm16 = value; - break; - case M32R_OPERAND_UIMM4 : - fields->f_uimm4 = value; - break; - case M32R_OPERAND_UIMM5 : - fields->f_uimm5 = value; - break; - case M32R_OPERAND_UIMM16 : - fields->f_uimm16 = value; - break; -/* start-sanitize-m32rx */ - case M32R_OPERAND_IMM1 : - fields->f_imm1 = value; - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACCD : - fields->f_accd = value; - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACCS : - fields->f_accs = value; - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACC : - fields->f_acc = value; - break; -/* end-sanitize-m32rx */ - case M32R_OPERAND_HASH : - fields->f_nil = value; - break; - case M32R_OPERAND_HI16 : - fields->f_hi16 = value; - break; - case M32R_OPERAND_SLO16 : - fields->f_simm16 = value; - break; - case M32R_OPERAND_ULO16 : - fields->f_uimm16 = value; - break; - case M32R_OPERAND_UIMM24 : - fields->f_uimm24 = value; - break; - case M32R_OPERAND_DISP8 : - fields->f_disp8 = value; - break; - case M32R_OPERAND_DISP16 : - fields->f_disp16 = value; - break; - case M32R_OPERAND_DISP24 : - fields->f_disp24 = value; - break; - - default : - /* xgettext:c-format */ - fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), - opindex); - abort (); - } -} - diff --git a/opcodes/m32r-opc.h b/opcodes/m32r-opc.h deleted file mode 100644 index 072dd0d0b79..00000000000 --- a/opcodes/m32r-opc.h +++ /dev/null @@ -1,502 +0,0 @@ -/* Instruction description for m32r. - -THIS FILE IS MACHINE GENERATED WITH CGEN. - -Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. - -This file is part of the GNU Binutils and/or GDB, the GNU debugger. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License along -with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - -*/ - -#ifndef M32R_OPC_H -#define M32R_OPC_H - -#define CGEN_ARCH m32r - -/* Given symbol S, return m32r_cgen_<S>. */ -#define CGEN_SYM(s) CONCAT3 (m32r,_cgen_,s) - -/* Selected cpu families. */ -#define HAVE_CPU_M32RBF -/* start-sanitize-m32rx */ -#define HAVE_CPU_M32RXF -/* end-sanitize-m32rx */ - -#define CGEN_INSN_LSB0_P 0 -#define CGEN_WORD_BITSIZE 32 -#define CGEN_DEFAULT_INSN_BITSIZE 32 -#define CGEN_BASE_INSN_BITSIZE 32 -#define CGEN_MIN_INSN_BITSIZE 16 -#define CGEN_MAX_INSN_BITSIZE 32 -#define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8) -#define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8) -#define CGEN_MIN_INSN_SIZE (CGEN_MIN_INSN_BITSIZE / 8) -#define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8) -#define CGEN_INT_INSN_P 1 - -/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */ - -/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. - e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands - we can't hash on everything up to the space. */ -#define CGEN_MNEMONIC_OPERANDS -/* Maximum number of operands any insn or macro-insn has. */ -#define CGEN_MAX_INSN_OPERANDS 16 - -/* Maximum number of fields in an instruction. */ -#define CGEN_MAX_IFMT_OPERANDS 7 - -/* Enums. */ - -/* Enum declaration for insn format enums. */ -typedef enum insn_op1 { - OP1_0, OP1_1, OP1_2, OP1_3 - , OP1_4, OP1_5, OP1_6, OP1_7 - , OP1_8, OP1_9, OP1_10, OP1_11 - , OP1_12, OP1_13, OP1_14, OP1_15 -} INSN_OP1; - -/* Enum declaration for op2 enums. */ -typedef enum insn_op2 { - OP2_0, OP2_1, OP2_2, OP2_3 - , OP2_4, OP2_5, OP2_6, OP2_7 - , OP2_8, OP2_9, OP2_10, OP2_11 - , OP2_12, OP2_13, OP2_14, OP2_15 -} INSN_OP2; - -/* Enum declaration for general registers. */ -typedef enum h_gr { - H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0 - , H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4 - , H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8 - , H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12 - , H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15 -} H_GR; - -/* Enum declaration for control registers. */ -typedef enum h_cr { - H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3 - , H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_CR0 = 0 - , H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3, H_CR_CR4 = 4 - , H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7, H_CR_CR8 = 8 - , H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11, H_CR_CR12 = 12 - , H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15 -} H_CR; - -/* start-sanitize-m32rx */ -/* Enum declaration for accumulators. */ -typedef enum h_accums { - H_ACCUMS_A0, H_ACCUMS_A1 -} H_ACCUMS; - -/* end-sanitize-m32rx */ -/* Attributes. */ - -/* Enum declaration for machine type selection. */ -typedef enum mach_attr { - MACH_BASE, MACH_M32R -/* start-sanitize-m32rx */ - , MACH_M32RX -/* end-sanitize-m32rx */ - , MACH_MAX -} MACH_ATTR; - -/* start-sanitize-m32rx */ -/* Enum declaration for parallel execution pipeline selection. */ -typedef enum pipe_attr { - PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS -} PIPE_ATTR; - -/* end-sanitize-m32rx */ -/* Number of architecture variants. */ -#define MAX_MACHS ((int) MACH_MAX) - -/* Ifield attribute indices. */ - -/* Enum declaration for cgen_ifld attrs. */ -typedef enum cgen_ifld_attr { - CGEN_IFLD_MACH, CGEN_IFLD_VIRTUAL, CGEN_IFLD_UNSIGNED, CGEN_IFLD_PCREL_ADDR - , CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_RELOC -} CGEN_IFLD_ATTR; - -/* Number of non-boolean elements in cgen_ifld. */ -#define CGEN_IFLD_NBOOL_ATTRS ((int) CGEN_IFLD_VIRTUAL) - -/* Enum declaration for m32r ifield types. */ -typedef enum ifield_type { - M32R_F_NIL, M32R_F_OP1, M32R_F_OP2, M32R_F_COND - , M32R_F_R1, M32R_F_R2, M32R_F_SIMM8, M32R_F_SIMM16 - , M32R_F_SHIFT_OP2, M32R_F_UIMM4, M32R_F_UIMM5, M32R_F_UIMM16 - , M32R_F_UIMM24, M32R_F_HI16, M32R_F_DISP8, M32R_F_DISP16 - , M32R_F_DISP24 -/* start-sanitize-m32rx */ - , M32R_F_OP23 -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_F_OP3 -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_F_ACC -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_F_ACCS -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_F_ACCD -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_F_BITS67 -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_F_BIT14 -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_F_IMM1 -/* end-sanitize-m32rx */ - , M32R_F_MAX -} IFIELD_TYPE; - -#define MAX_IFLD ((int) M32R_F_MAX) - -/* Hardware attribute indices. */ - -/* Enum declaration for cgen_hw attrs. */ -typedef enum cgen_hw_attr { - CGEN_HW_MACH, CGEN_HW_VIRTUAL, CGEN_HW_UNSIGNED, CGEN_HW_SIGNED - , CGEN_HW_CACHE_ADDR, CGEN_HW_FUN_ACCESS, CGEN_HW_PC, CGEN_HW_PROFILE -} CGEN_HW_ATTR; - -/* Number of non-boolean elements in cgen_hw. */ -#define CGEN_HW_NBOOL_ATTRS ((int) CGEN_HW_VIRTUAL) - -/* Enum declaration for m32r hardware types. */ -typedef enum hw_type { - HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT - , HW_H_ADDR, HW_H_IADDR, HW_H_HI16, HW_H_SLO16 - , HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM -/* start-sanitize-m32rx */ - , HW_H_ACCUMS -/* end-sanitize-m32rx */ - , HW_H_COND, HW_H_PSW, HW_H_BPSW, HW_H_BBPSW - , HW_H_LOCK, HW_MAX -} HW_TYPE; - -#define MAX_HW ((int) HW_MAX) - -/* Operand attribute indices. */ - -/* Enum declaration for cgen_operand attrs. */ -typedef enum cgen_operand_attr { - CGEN_OPERAND_MACH, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_UNSIGNED, CGEN_OPERAND_PCREL_ADDR - , CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX - , CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_RELOC, CGEN_OPERAND_HASH_PREFIX -} CGEN_OPERAND_ATTR; - -/* Number of non-boolean elements in cgen_operand. */ -#define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_VIRTUAL) - -/* Enum declaration for m32r operand types. */ -typedef enum cgen_operand_type { - M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1 - , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8 - , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16 -/* start-sanitize-m32rx */ - , M32R_OPERAND_IMM1 -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_OPERAND_ACCD -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_OPERAND_ACCS -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_OPERAND_ACC -/* end-sanitize-m32rx */ - , M32R_OPERAND_HASH, M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16 - , M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24 - , M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM, M32R_OPERAND_MAX -} CGEN_OPERAND_TYPE; - -/* Number of operands types. */ -#define MAX_OPERANDS ((int) M32R_OPERAND_MAX) - -/* Maximum number of operands referenced by any insn. */ -#define MAX_OPERAND_INSTANCES 11 - -/* Insn attribute indices. */ - -/* Enum declaration for cgen_insn attrs. */ -typedef enum cgen_insn_attr { - CGEN_INSN_MACH -/* start-sanitize-m32rx */ - , CGEN_INSN_PIPE -/* end-sanitize-m32rx */ - , CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI - , CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX, CGEN_INSN_ALIAS - , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT -/* start-sanitize-m32rx */ - , CGEN_INSN_SPECIAL -/* end-sanitize-m32rx */ -} CGEN_INSN_ATTR; - -/* Number of non-boolean elements in cgen_insn. */ -#define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_VIRTUAL) - -/* Enum declaration for m32r instruction types. */ -typedef enum cgen_insn_type { - M32R_INSN_INVALID, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_AND - , M32R_INSN_AND3, M32R_INSN_OR, M32R_INSN_OR3, M32R_INSN_XOR - , M32R_INSN_XOR3, M32R_INSN_ADDI, M32R_INSN_ADDV, M32R_INSN_ADDV3 - , M32R_INSN_ADDX, M32R_INSN_BC8, M32R_INSN_BC24, M32R_INSN_BEQ - , M32R_INSN_BEQZ, M32R_INSN_BGEZ, M32R_INSN_BGTZ, M32R_INSN_BLEZ - , M32R_INSN_BLTZ, M32R_INSN_BNEZ, M32R_INSN_BL8, M32R_INSN_BL24 -/* start-sanitize-m32rx */ - , M32R_INSN_BCL8 -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_INSN_BCL24 -/* end-sanitize-m32rx */ - , M32R_INSN_BNC8, M32R_INSN_BNC24, M32R_INSN_BNE, M32R_INSN_BRA8 - , M32R_INSN_BRA24 -/* start-sanitize-m32rx */ - , M32R_INSN_BNCL8 -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_INSN_BNCL24 -/* end-sanitize-m32rx */ - , M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU, M32R_INSN_CMPUI -/* start-sanitize-m32rx */ - , M32R_INSN_CMPEQ -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_INSN_CMPZ -/* end-sanitize-m32rx */ - , M32R_INSN_DIV, M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU -/* start-sanitize-m32rx */ - , M32R_INSN_DIVH -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_INSN_JC -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_INSN_JNC -/* end-sanitize-m32rx */ - , M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD, M32R_INSN_LD_D - , M32R_INSN_LDB, M32R_INSN_LDB_D, M32R_INSN_LDH, M32R_INSN_LDH_D - , M32R_INSN_LDUB, M32R_INSN_LDUB_D, M32R_INSN_LDUH, M32R_INSN_LDUH_D - , M32R_INSN_LD_PLUS, M32R_INSN_LD24, M32R_INSN_LDI8, M32R_INSN_LDI16 - , M32R_INSN_LOCK, M32R_INSN_MACHI -/* start-sanitize-m32rx */ - , M32R_INSN_MACHI_A -/* end-sanitize-m32rx */ - , M32R_INSN_MACLO -/* start-sanitize-m32rx */ - , M32R_INSN_MACLO_A -/* end-sanitize-m32rx */ - , M32R_INSN_MACWHI -/* start-sanitize-m32rx */ - , M32R_INSN_MACWHI_A -/* end-sanitize-m32rx */ - , M32R_INSN_MACWLO -/* start-sanitize-m32rx */ - , M32R_INSN_MACWLO_A -/* end-sanitize-m32rx */ - , M32R_INSN_MUL, M32R_INSN_MULHI -/* start-sanitize-m32rx */ - , M32R_INSN_MULHI_A -/* end-sanitize-m32rx */ - , M32R_INSN_MULLO -/* start-sanitize-m32rx */ - , M32R_INSN_MULLO_A -/* end-sanitize-m32rx */ - , M32R_INSN_MULWHI -/* start-sanitize-m32rx */ - , M32R_INSN_MULWHI_A -/* end-sanitize-m32rx */ - , M32R_INSN_MULWLO -/* start-sanitize-m32rx */ - , M32R_INSN_MULWLO_A -/* end-sanitize-m32rx */ - , M32R_INSN_MV, M32R_INSN_MVFACHI -/* start-sanitize-m32rx */ - , M32R_INSN_MVFACHI_A -/* end-sanitize-m32rx */ - , M32R_INSN_MVFACLO -/* start-sanitize-m32rx */ - , M32R_INSN_MVFACLO_A -/* end-sanitize-m32rx */ - , M32R_INSN_MVFACMI -/* start-sanitize-m32rx */ - , M32R_INSN_MVFACMI_A -/* end-sanitize-m32rx */ - , M32R_INSN_MVFC, M32R_INSN_MVTACHI -/* start-sanitize-m32rx */ - , M32R_INSN_MVTACHI_A -/* end-sanitize-m32rx */ - , M32R_INSN_MVTACLO -/* start-sanitize-m32rx */ - , M32R_INSN_MVTACLO_A -/* end-sanitize-m32rx */ - , M32R_INSN_MVTC, M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT - , M32R_INSN_RAC -/* start-sanitize-m32rx */ - , M32R_INSN_RAC_DSI -/* end-sanitize-m32rx */ - , M32R_INSN_RACH -/* start-sanitize-m32rx */ - , M32R_INSN_RACH_DSI -/* end-sanitize-m32rx */ - , M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3 - , M32R_INSN_SLLI, M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI - , M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST - , M32R_INSN_ST_D, M32R_INSN_STB, M32R_INSN_STB_D, M32R_INSN_STH - , M32R_INSN_STH_D, M32R_INSN_ST_PLUS, M32R_INSN_ST_MINUS, M32R_INSN_SUB - , M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP, M32R_INSN_UNLOCK -/* start-sanitize-m32rx */ - , M32R_INSN_SATB -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_INSN_SATH -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_INSN_SAT -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_INSN_PCMPBZ -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_INSN_SADD -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_INSN_MACWU1 -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_INSN_MSBLO -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_INSN_MULWU1 -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_INSN_MACLH1 -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_INSN_SC -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - , M32R_INSN_SNC -/* end-sanitize-m32rx */ - , M32R_INSN_MAX -} CGEN_INSN_TYPE; - -/* Index of `invalid' insn place holder. */ -#define CGEN_INSN_INVALID M32R_INSN_INVALID -/* Total number of insns in table. */ -#define MAX_INSNS ((int) M32R_INSN_MAX) - -/* cgen.h uses things we just defined. */ -#include "opcode/cgen.h" - -/* This struct records data prior to insertion or after extraction. */ -struct cgen_fields -{ - long f_nil; - long f_op1; - long f_op2; - long f_cond; - long f_r1; - long f_r2; - long f_simm8; - long f_simm16; - long f_shift_op2; - long f_uimm4; - long f_uimm5; - long f_uimm16; - long f_uimm24; - long f_hi16; - long f_disp8; - long f_disp16; - long f_disp24; -/* start-sanitize-m32rx */ - long f_op23; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - long f_op3; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - long f_acc; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - long f_accs; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - long f_accd; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - long f_bits67; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - long f_bit14; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - long f_imm1; -/* end-sanitize-m32rx */ - int length; -}; - -/* Attributes. */ -extern const CGEN_ATTR_TABLE m32r_cgen_hw_attr_table[]; -extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[]; -extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[]; - -/* Hardware decls. */ - -extern CGEN_KEYWORD m32r_cgen_opval_h_gr; -extern CGEN_KEYWORD m32r_cgen_opval_h_cr; -/* start-sanitize-m32rx */ -extern CGEN_KEYWORD m32r_cgen_opval_h_accums; -/* end-sanitize-m32rx */ - -#define CGEN_INIT_PARSE(od) \ -{\ -} -#define CGEN_INIT_INSERT(od) \ -{\ -} -#define CGEN_INIT_EXTRACT(od) \ -{\ -} -#define CGEN_INIT_PRINT(od) \ -{\ -} - -/* -- opc.h */ - -#undef CGEN_DIS_HASH_SIZE -#define CGEN_DIS_HASH_SIZE 256 -#undef CGEN_DIS_HASH -#define X(b) (((unsigned char *) (b))[0] & 0xf0) -#define CGEN_DIS_HASH(buffer, value) \ -(X (buffer) | \ - (X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \ - : X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \ - : X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \ - : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4))) - -/* -- */ - - -#endif /* M32R_OPC_H */ diff --git a/opcodes/m68k-dis.c b/opcodes/m68k-dis.c deleted file mode 100644 index 619bcbcd762..00000000000 --- a/opcodes/m68k-dis.c +++ /dev/null @@ -1,1194 +0,0 @@ -/* Print Motorola 68k instructions. - Copyright 1986, 87, 89, 91, 92, 93, 94, 95, 96, 1997 - Free Software Foundation, Inc. - -This file is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "dis-asm.h" -#include "floatformat.h" -#include <libiberty.h> - -#include "opcode/m68k.h" - -/* Local function prototypes */ - -static int -fetch_data PARAMS ((struct disassemble_info *, bfd_byte *)); - -static void -dummy_print_address PARAMS ((bfd_vma, struct disassemble_info *)); - -static int -fetch_arg PARAMS ((unsigned char *, int, int, disassemble_info *)); - -static void -print_base PARAMS ((int, bfd_vma, disassemble_info*)); - -static unsigned char * -print_indexed PARAMS ((int, unsigned char *, bfd_vma, disassemble_info *)); - -static int -print_insn_arg PARAMS ((const char *, unsigned char *, unsigned char *, - bfd_vma, disassemble_info *)); - -CONST char * CONST fpcr_names[] = { - "", "%fpiar", "%fpsr", "%fpiar/%fpsr", "%fpcr", - "%fpiar/%fpcr", "%fpsr/%fpcr", "%fpiar/%fpsr/%fpcr"}; - -static char *const reg_names[] = { - "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", - "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp", - "%ps", "%pc"}; - -/* Sign-extend an (unsigned char). */ -#if __STDC__ == 1 -#define COERCE_SIGNED_CHAR(ch) ((signed char)(ch)) -#else -#define COERCE_SIGNED_CHAR(ch) ((int)(((ch) ^ 0x80) & 0xFF) - 128) -#endif - -/* Get a 1 byte signed integer. */ -#define NEXTBYTE(p) (p += 2, FETCH_DATA (info, p), COERCE_SIGNED_CHAR(p[-1])) - -/* Get a 2 byte signed integer. */ -#define COERCE16(x) ((int) (((x) ^ 0x8000) - 0x8000)) -#define NEXTWORD(p) \ - (p += 2, FETCH_DATA (info, p), \ - COERCE16 ((p[-2] << 8) + p[-1])) - -/* Get a 4 byte signed integer. */ -#define COERCE32(x) ((int) (((x) ^ 0x80000000) - 0x80000000)) -#define NEXTLONG(p) \ - (p += 4, FETCH_DATA (info, p), \ - (COERCE32 ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1]))) - -/* Get a single precision float. */ -#define NEXTSINGLE(val, p) \ - (p += 4, FETCH_DATA (info, p), \ - floatformat_to_double (&floatformat_ieee_single_big, (char *) p - 4, &val)) - -/* Get a double precision float. */ -#define NEXTDOUBLE(val, p) \ - (p += 8, FETCH_DATA (info, p), \ - floatformat_to_double (&floatformat_ieee_double_big, (char *) p - 8, &val)) - -/* Get an extended precision float. */ -#define NEXTEXTEND(val, p) \ - (p += 12, FETCH_DATA (info, p), \ - floatformat_to_double (&floatformat_m68881_ext, (char *) p - 12, &val)) - -/* Need a function to convert from packed to double - precision. Actually, it's easier to print a - packed number than a double anyway, so maybe - there should be a special case to handle this... */ -#define NEXTPACKED(p) \ - (p += 12, FETCH_DATA (info, p), 0.0) - - -/* Maximum length of an instruction. */ -#define MAXLEN 22 - -#include <setjmp.h> - -struct private -{ - /* Points to first byte not fetched. */ - bfd_byte *max_fetched; - bfd_byte the_buffer[MAXLEN]; - bfd_vma insn_start; - jmp_buf bailout; -}; - -/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) - to ADDR (exclusive) are valid. Returns 1 for success, longjmps - on error. */ -#define FETCH_DATA(info, addr) \ - ((addr) <= ((struct private *)(info->private_data))->max_fetched \ - ? 1 : fetch_data ((info), (addr))) - -static int -fetch_data (info, addr) - struct disassemble_info *info; - bfd_byte *addr; -{ - int status; - struct private *priv = (struct private *)info->private_data; - bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); - - status = (*info->read_memory_func) (start, - priv->max_fetched, - addr - priv->max_fetched, - info); - if (status != 0) - { - (*info->memory_error_func) (status, start, info); - longjmp (priv->bailout, 1); - } - else - priv->max_fetched = addr; - return 1; -} - -/* This function is used to print to the bit-bucket. */ -static int -#ifdef __STDC__ -dummy_printer (FILE * file, const char * format, ...) -#else -dummy_printer (file) FILE *file; -#endif - { return 0; } - -static void -dummy_print_address (vma, info) - bfd_vma vma; - struct disassemble_info *info; -{ -} - -/* Print the m68k instruction at address MEMADDR in debugged memory, - on INFO->STREAM. Returns length of the instruction, in bytes. */ - -int -print_insn_m68k (memaddr, info) - bfd_vma memaddr; - disassemble_info *info; -{ - register int i; - register unsigned char *p; - unsigned char *save_p; - register const char *d; - register unsigned long bestmask; - const struct m68k_opcode *best = 0; - struct private priv; - bfd_byte *buffer = priv.the_buffer; - fprintf_ftype save_printer = info->fprintf_func; - void (*save_print_address) PARAMS((bfd_vma, struct disassemble_info*)) - = info->print_address_func; - int major_opcode; - static int numopcodes[16]; - static const struct m68k_opcode **opcodes[16]; - - if (!opcodes[0]) - { - /* Speed up the matching by sorting the opcode table on the upper - four bits of the opcode. */ - const struct m68k_opcode **opc_pointer[16]; - - /* First count how many opcodes are in each of the sixteen buckets. */ - for (i = 0; i < m68k_numopcodes; i++) - numopcodes[(m68k_opcodes[i].opcode >> 28) & 15]++; - - /* Then create a sorted table of pointers that point into the - unsorted table. */ - opc_pointer[0] = ((const struct m68k_opcode **) - xmalloc (sizeof (struct m68k_opcode *) - * m68k_numopcodes)); - opcodes[0] = opc_pointer[0]; - for (i = 1; i < 16; i++) - { - opc_pointer[i] = opc_pointer[i - 1] + numopcodes[i - 1]; - opcodes[i] = opc_pointer[i]; - } - - for (i = 0; i < m68k_numopcodes; i++) - *opc_pointer[(m68k_opcodes[i].opcode >> 28) & 15]++ = &m68k_opcodes[i]; - - } - - info->private_data = (PTR) &priv; - /* Tell objdump to use two bytes per chunk and six bytes per line for - displaying raw data. */ - info->bytes_per_chunk = 2; - info->bytes_per_line = 6; - info->display_endian = BFD_ENDIAN_BIG; - priv.max_fetched = priv.the_buffer; - priv.insn_start = memaddr; - if (setjmp (priv.bailout) != 0) - /* Error return. */ - return -1; - - bestmask = 0; - FETCH_DATA (info, buffer + 2); - major_opcode = (buffer[0] >> 4) & 15; - for (i = 0; i < numopcodes[major_opcode]; i++) - { - const struct m68k_opcode *opc = opcodes[major_opcode][i]; - unsigned long opcode = opc->opcode; - unsigned long match = opc->match; - - if (((0xff & buffer[0] & (match >> 24)) == (0xff & (opcode >> 24))) - && ((0xff & buffer[1] & (match >> 16)) == (0xff & (opcode >> 16))) - /* Only fetch the next two bytes if we need to. */ - && (((0xffff & match) == 0) - || - (FETCH_DATA (info, buffer + 4) - && ((0xff & buffer[2] & (match >> 8)) == (0xff & (opcode >> 8))) - && ((0xff & buffer[3] & match) == (0xff & opcode))) - )) - { - /* Don't use for printout the variants of divul and divsl - that have the same register number in two places. - The more general variants will match instead. */ - for (d = opc->args; *d; d += 2) - if (d[1] == 'D') - break; - - /* Don't use for printout the variants of most floating - point coprocessor instructions which use the same - register number in two places, as above. */ - if (*d == '\0') - for (d = opc->args; *d; d += 2) - if (d[1] == 't') - break; - - /* Don't match fmovel with more than one register; wait for - fmoveml. */ - if (*d == '\0') - { - for (d = opc->args; *d; d += 2) - { - if (d[0] == 's' && d[1] == '8') - { - int val; - - val = fetch_arg (buffer, d[1], 3, info); - if ((val & (val - 1)) != 0) - break; - } - } - } - - if (*d == '\0' && match > bestmask) - { - best = opc; - bestmask = match; - } - } - } - - if (best == 0) - goto invalid; - - /* Point at first word of argument data, - and at descriptor for first argument. */ - p = buffer + 2; - - /* Figure out how long the fixed-size portion of the instruction is. - The only place this is stored in the opcode table is - in the arguments--look for arguments which specify fields in the 2nd - or 3rd words of the instruction. */ - for (d = best->args; *d; d += 2) - { - /* I don't think it is necessary to be checking d[0] here; I suspect - all this could be moved to the case statement below. */ - if (d[0] == '#') - { - if (d[1] == 'l' && p - buffer < 6) - p = buffer + 6; - else if (p - buffer < 4 && d[1] != 'C' && d[1] != '8' ) - p = buffer + 4; - } - if ((d[0] == 'L' || d[0] == 'l') && d[1] == 'w' && p - buffer < 4) - p = buffer + 4; - switch (d[1]) - { - case '1': - case '2': - case '3': - case '7': - case '8': - case '9': - case 'i': - if (p - buffer < 4) - p = buffer + 4; - break; - case '4': - case '5': - case '6': - if (p - buffer < 6) - p = buffer + 6; - break; - default: - break; - } - } - - /* pflusha is an exceptions. It takes no arguments but is two words - long. Recognize it by looking at the lower 16 bits of the mask. */ - if (p - buffer < 4 && (best->match & 0xFFFF) != 0) - p = buffer + 4; - - /* lpstop is another exception. It takes a one word argument but is - three words long. */ - if (p - buffer < 6 - && (best->match & 0xffff) == 0xffff - && best->args[0] == '#' - && best->args[1] == 'w') - { - /* Copy the one word argument into the usual location for a one - word argument, to simplify printing it. We can get away with - this because we know exactly what the second word is, and we - aren't going to print anything based on it. */ - p = buffer + 6; - FETCH_DATA (info, p); - buffer[2] = buffer[4]; - buffer[3] = buffer[5]; - } - - FETCH_DATA (info, p); - - d = best->args; - - /* We can the operands twice. The first time we don't print anything, - but look for errors. */ - - save_p = p; - info->print_address_func = dummy_print_address; - info->fprintf_func = (fprintf_ftype)dummy_printer; - for ( ; *d; d += 2) - { - int eaten = print_insn_arg (d, buffer, p, memaddr + p - buffer, info); - if (eaten >= 0) - p += eaten; - else if (eaten == -1) - goto invalid; - else - { - (*info->fprintf_func)(info->stream, - "<internal error in opcode table: %s %s>\n", - best->name, - best->args); - goto invalid; - } - - } - p = save_p; - info->fprintf_func = save_printer; - info->print_address_func = save_print_address; - - d = best->args; - - (*info->fprintf_func) (info->stream, "%s", best->name); - - if (*d) - (*info->fprintf_func) (info->stream, " "); - - while (*d) - { - p += print_insn_arg (d, buffer, p, memaddr + p - buffer, info); - d += 2; - if (*d && *(d - 2) != 'I' && *d != 'k') - (*info->fprintf_func) (info->stream, ","); - } - return p - buffer; - - invalid: - /* Handle undefined instructions. */ - info->fprintf_func = save_printer; - info->print_address_func = save_print_address; - (*info->fprintf_func) (info->stream, "0%o", - (buffer[0] << 8) + buffer[1]); - return 2; -} - -/* Returns number of bytes "eaten" by the operand, or - return -1 if an invalid operand was found, or -2 if - an opcode tabe error was found. */ - -static int -print_insn_arg (d, buffer, p0, addr, info) - const char *d; - unsigned char *buffer; - unsigned char *p0; - bfd_vma addr; /* PC for this arg to be relative to */ - disassemble_info *info; -{ - register int val = 0; - register int place = d[1]; - register unsigned char *p = p0; - int regno; - register CONST char *regname; - register unsigned char *p1; - double flval; - int flt_p; - - switch (*d) - { - case 'c': /* cache identifier */ - { - static char *const cacheFieldName[] = { "nc", "dc", "ic", "bc" }; - val = fetch_arg (buffer, place, 2, info); - (*info->fprintf_func) (info->stream, cacheFieldName[val]); - break; - } - - case 'a': /* address register indirect only. Cf. case '+'. */ - { - (*info->fprintf_func) - (info->stream, - "%s@", - reg_names [fetch_arg (buffer, place, 3, info) + 8]); - break; - } - - case '_': /* 32-bit absolute address for move16. */ - { - val = NEXTLONG (p); - (*info->print_address_func) (val, info); - break; - } - - case 'C': - (*info->fprintf_func) (info->stream, "%%ccr"); - break; - - case 'S': - (*info->fprintf_func) (info->stream, "%%sr"); - break; - - case 'U': - (*info->fprintf_func) (info->stream, "%%usp"); - break; - - case 'J': - { - static const struct { char *name; int value; } names[] - = {{"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002}, - {"%tc", 0x003}, {"%itt0",0x004}, {"%itt1", 0x005}, - {"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008}, - {"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802}, - {"%msp", 0x803}, {"%isp", 0x804}, - - /* Should we be calling this psr like we do in case 'Y'? */ - {"%mmusr",0x805}, - - {"%urp", 0x806}, {"%srp", 0x807}, {"%pcr", 0x808}}; - - val = fetch_arg (buffer, place, 12, info); - for (regno = sizeof names / sizeof names[0] - 1; regno >= 0; regno--) - if (names[regno].value == val) - { - (*info->fprintf_func) (info->stream, "%s", names[regno].name); - break; - } - if (regno < 0) - (*info->fprintf_func) (info->stream, "%d", val); - } - break; - - case 'Q': - val = fetch_arg (buffer, place, 3, info); - /* 0 means 8, except for the bkpt instruction... */ - if (val == 0 && d[1] != 's') - val = 8; - (*info->fprintf_func) (info->stream, "#%d", val); - break; - - case 'M': - val = fetch_arg (buffer, place, 8, info); - if (val & 0x80) - val = val - 0x100; - (*info->fprintf_func) (info->stream, "#%d", val); - break; - - case 'T': - val = fetch_arg (buffer, place, 4, info); - (*info->fprintf_func) (info->stream, "#%d", val); - break; - - case 'D': - (*info->fprintf_func) (info->stream, "%s", - reg_names[fetch_arg (buffer, place, 3, info)]); - break; - - case 'A': - (*info->fprintf_func) - (info->stream, "%s", - reg_names[fetch_arg (buffer, place, 3, info) + 010]); - break; - - case 'R': - (*info->fprintf_func) - (info->stream, "%s", - reg_names[fetch_arg (buffer, place, 4, info)]); - break; - - case 'r': - regno = fetch_arg (buffer, place, 4, info); - if (regno > 7) - (*info->fprintf_func) (info->stream, "%s@", reg_names[regno]); - else - (*info->fprintf_func) (info->stream, "@(%s)", reg_names[regno]); - break; - - case 'F': - (*info->fprintf_func) - (info->stream, "%%fp%d", - fetch_arg (buffer, place, 3, info)); - break; - - case 'O': - val = fetch_arg (buffer, place, 6, info); - if (val & 0x20) - (*info->fprintf_func) (info->stream, "%s", reg_names [val & 7]); - else - (*info->fprintf_func) (info->stream, "%d", val); - break; - - case '+': - (*info->fprintf_func) - (info->stream, "%s@+", - reg_names[fetch_arg (buffer, place, 3, info) + 8]); - break; - - case '-': - (*info->fprintf_func) - (info->stream, "%s@-", - reg_names[fetch_arg (buffer, place, 3, info) + 8]); - break; - - case 'k': - if (place == 'k') - (*info->fprintf_func) - (info->stream, "{%s}", - reg_names[fetch_arg (buffer, place, 3, info)]); - else if (place == 'C') - { - val = fetch_arg (buffer, place, 7, info); - if ( val > 63 ) /* This is a signed constant. */ - val -= 128; - (*info->fprintf_func) (info->stream, "{#%d}", val); - } - else - return -2; - break; - - case '#': - case '^': - p1 = buffer + (*d == '#' ? 2 : 4); - if (place == 's') - val = fetch_arg (buffer, place, 4, info); - else if (place == 'C') - val = fetch_arg (buffer, place, 7, info); - else if (place == '8') - val = fetch_arg (buffer, place, 3, info); - else if (place == '3') - val = fetch_arg (buffer, place, 8, info); - else if (place == 'b') - val = NEXTBYTE (p1); - else if (place == 'w' || place == 'W') - val = NEXTWORD (p1); - else if (place == 'l') - val = NEXTLONG (p1); - else - return -2; - (*info->fprintf_func) (info->stream, "#%d", val); - break; - - case 'B': - if (place == 'b') - val = NEXTBYTE (p); - else if (place == 'B') - val = COERCE_SIGNED_CHAR(buffer[1]); - else if (place == 'w' || place == 'W') - val = NEXTWORD (p); - else if (place == 'l' || place == 'L' || place == 'C') - val = NEXTLONG (p); - else if (place == 'g') - { - val = NEXTBYTE (buffer); - if (val == 0) - val = NEXTWORD (p); - else if (val == -1) - val = NEXTLONG (p); - } - else if (place == 'c') - { - if (buffer[1] & 0x40) /* If bit six is one, long offset */ - val = NEXTLONG (p); - else - val = NEXTWORD (p); - } - else - return -2; - - (*info->print_address_func) (addr + val, info); - break; - - case 'd': - val = NEXTWORD (p); - (*info->fprintf_func) - (info->stream, "%s@(%d)", - reg_names[fetch_arg (buffer, place, 3, info) + 8], val); - break; - - case 's': - (*info->fprintf_func) (info->stream, "%s", - fpcr_names[fetch_arg (buffer, place, 3, info)]); - break; - - case 'I': - /* Get coprocessor ID... */ - val = fetch_arg (buffer, 'd', 3, info); - - if (val != 1) /* Unusual coprocessor ID? */ - (*info->fprintf_func) (info->stream, "(cpid=%d) ", val); - break; - - case '*': - case '~': - case '%': - case ';': - case '@': - case '!': - case '$': - case '?': - case '/': - case '&': - case '|': - case '<': - case '>': - - if (place == 'd') - { - val = fetch_arg (buffer, 'x', 6, info); - val = ((val & 7) << 3) + ((val >> 3) & 7); - } - else - val = fetch_arg (buffer, 's', 6, info); - - /* Get register number assuming address register. */ - regno = (val & 7) + 8; - regname = reg_names[regno]; - switch (val >> 3) - { - case 0: - (*info->fprintf_func) (info->stream, "%s", reg_names[val]); - break; - - case 1: - (*info->fprintf_func) (info->stream, "%s", regname); - break; - - case 2: - (*info->fprintf_func) (info->stream, "%s@", regname); - break; - - case 3: - (*info->fprintf_func) (info->stream, "%s@+", regname); - break; - - case 4: - (*info->fprintf_func) (info->stream, "%s@-", regname); - break; - - case 5: - val = NEXTWORD (p); - (*info->fprintf_func) (info->stream, "%s@(%d)", regname, val); - break; - - case 6: - p = print_indexed (regno, p, addr, info); - break; - - case 7: - switch (val & 7) - { - case 0: - val = NEXTWORD (p); - (*info->print_address_func) (val, info); - break; - - case 1: - val = NEXTLONG (p); - (*info->print_address_func) (val, info); - break; - - case 2: - val = NEXTWORD (p); - (*info->fprintf_func) (info->stream, "%%pc@("); - (*info->print_address_func) (addr + val, info); - (*info->fprintf_func) (info->stream, ")"); - break; - - case 3: - p = print_indexed (-1, p, addr, info); - break; - - case 4: - flt_p = 1; /* Assume it's a float... */ - switch( place ) - { - case 'b': - val = NEXTBYTE (p); - flt_p = 0; - break; - - case 'w': - val = NEXTWORD (p); - flt_p = 0; - break; - - case 'l': - val = NEXTLONG (p); - flt_p = 0; - break; - - case 'f': - NEXTSINGLE(flval, p); - break; - - case 'F': - NEXTDOUBLE(flval, p); - break; - - case 'x': - NEXTEXTEND(flval, p); - break; - - case 'p': - flval = NEXTPACKED(p); - break; - - default: - return -1; - } - if ( flt_p ) /* Print a float? */ - (*info->fprintf_func) (info->stream, "#%g", flval); - else - (*info->fprintf_func) (info->stream, "#%d", val); - break; - - default: - return -1; - } - } - break; - - case 'L': - case 'l': - if (place == 'w') - { - char doneany; - p1 = buffer + 2; - val = NEXTWORD (p1); - /* Move the pointer ahead if this point is farther ahead - than the last. */ - p = p1 > p ? p1 : p; - if (val == 0) - { - (*info->fprintf_func) (info->stream, "#0"); - break; - } - if (*d == 'l') - { - register int newval = 0; - for (regno = 0; regno < 16; ++regno) - if (val & (0x8000 >> regno)) - newval |= 1 << regno; - val = newval; - } - val &= 0xffff; - doneany = 0; - for (regno = 0; regno < 16; ++regno) - if (val & (1 << regno)) - { - int first_regno; - if (doneany) - (*info->fprintf_func) (info->stream, "/"); - doneany = 1; - (*info->fprintf_func) (info->stream, "%s", reg_names[regno]); - first_regno = regno; - while (val & (1 << (regno + 1))) - ++regno; - if (regno > first_regno) - (*info->fprintf_func) (info->stream, "-%s", - reg_names[regno]); - } - } - else if (place == '3') - { - /* `fmovem' insn. */ - char doneany; - val = fetch_arg (buffer, place, 8, info); - if (val == 0) - { - (*info->fprintf_func) (info->stream, "#0"); - break; - } - if (*d == 'l') - { - register int newval = 0; - for (regno = 0; regno < 8; ++regno) - if (val & (0x80 >> regno)) - newval |= 1 << regno; - val = newval; - } - val &= 0xff; - doneany = 0; - for (regno = 0; regno < 8; ++regno) - if (val & (1 << regno)) - { - int first_regno; - if (doneany) - (*info->fprintf_func) (info->stream, "/"); - doneany = 1; - (*info->fprintf_func) (info->stream, "%%fp%d", regno); - first_regno = regno; - while (val & (1 << (regno + 1))) - ++regno; - if (regno > first_regno) - (*info->fprintf_func) (info->stream, "-%%fp%d", regno); - } - } - else if (place == '8') - { - /* fmoveml for FP status registers */ - (*info->fprintf_func) (info->stream, "%s", - fpcr_names[fetch_arg (buffer, place, 3, - info)]); - } - else - return -2; - break; - - case 'X': - place = '8'; - case 'Y': - case 'Z': - case 'W': - case '0': - case '1': - case '2': - case '3': - { - int val = fetch_arg (buffer, place, 5, info); - char *name = 0; - switch (val) - { - case 2: name = "%tt0"; break; - case 3: name = "%tt1"; break; - case 0x10: name = "%tc"; break; - case 0x11: name = "%drp"; break; - case 0x12: name = "%srp"; break; - case 0x13: name = "%crp"; break; - case 0x14: name = "%cal"; break; - case 0x15: name = "%val"; break; - case 0x16: name = "%scc"; break; - case 0x17: name = "%ac"; break; - case 0x18: name = "%psr"; break; - case 0x19: name = "%pcsr"; break; - case 0x1c: - case 0x1d: - { - int break_reg = ((buffer[3] >> 2) & 7); - (*info->fprintf_func) - (info->stream, val == 0x1c ? "%%bad%d" : "%%bac%d", - break_reg); - } - break; - default: - (*info->fprintf_func) (info->stream, "<mmu register %d>", val); - } - if (name) - (*info->fprintf_func) (info->stream, "%s", name); - } - break; - - case 'f': - { - int fc = fetch_arg (buffer, place, 5, info); - if (fc == 1) - (*info->fprintf_func) (info->stream, "%%dfc"); - else if (fc == 0) - (*info->fprintf_func) (info->stream, "%%sfc"); - else - (*info->fprintf_func) (info->stream, "<function code %d>", fc); - } - break; - - case 'V': - (*info->fprintf_func) (info->stream, "%%val"); - break; - - case 't': - { - int level = fetch_arg (buffer, place, 3, info); - (*info->fprintf_func) (info->stream, "%d", level); - } - break; - - default: - return -2; - } - - return p - p0; -} - -/* Fetch BITS bits from a position in the instruction specified by CODE. - CODE is a "place to put an argument", or 'x' for a destination - that is a general address (mode and register). - BUFFER contains the instruction. */ - -static int -fetch_arg (buffer, code, bits, info) - unsigned char *buffer; - int code; - int bits; - disassemble_info *info; -{ - register int val = 0; - switch (code) - { - case 's': - val = buffer[1]; - break; - - case 'd': /* Destination, for register or quick. */ - val = (buffer[0] << 8) + buffer[1]; - val >>= 9; - break; - - case 'x': /* Destination, for general arg */ - val = (buffer[0] << 8) + buffer[1]; - val >>= 6; - break; - - case 'k': - FETCH_DATA (info, buffer + 3); - val = (buffer[3] >> 4); - break; - - case 'C': - FETCH_DATA (info, buffer + 3); - val = buffer[3]; - break; - - case '1': - FETCH_DATA (info, buffer + 3); - val = (buffer[2] << 8) + buffer[3]; - val >>= 12; - break; - - case '2': - FETCH_DATA (info, buffer + 3); - val = (buffer[2] << 8) + buffer[3]; - val >>= 6; - break; - - case '3': - case 'j': - FETCH_DATA (info, buffer + 3); - val = (buffer[2] << 8) + buffer[3]; - break; - - case '4': - FETCH_DATA (info, buffer + 5); - val = (buffer[4] << 8) + buffer[5]; - val >>= 12; - break; - - case '5': - FETCH_DATA (info, buffer + 5); - val = (buffer[4] << 8) + buffer[5]; - val >>= 6; - break; - - case '6': - FETCH_DATA (info, buffer + 5); - val = (buffer[4] << 8) + buffer[5]; - break; - - case '7': - FETCH_DATA (info, buffer + 3); - val = (buffer[2] << 8) + buffer[3]; - val >>= 7; - break; - - case '8': - FETCH_DATA (info, buffer + 3); - val = (buffer[2] << 8) + buffer[3]; - val >>= 10; - break; - - case '9': - FETCH_DATA (info, buffer + 3); - val = (buffer[2] << 8) + buffer[3]; - val >>= 5; - break; - - case 'e': - val = (buffer[1] >> 6); - break; - - default: - abort (); - } - - switch (bits) - { - case 2: - return val & 3; - case 3: - return val & 7; - case 4: - return val & 017; - case 5: - return val & 037; - case 6: - return val & 077; - case 7: - return val & 0177; - case 8: - return val & 0377; - case 12: - return val & 07777; - default: - abort (); - } -} - -/* Print an indexed argument. The base register is BASEREG (-1 for pc). - P points to extension word, in buffer. - ADDR is the nominal core address of that extension word. */ - -static unsigned char * -print_indexed (basereg, p, addr, info) - int basereg; - unsigned char *p; - bfd_vma addr; - disassemble_info *info; -{ - register int word; - static char *const scales[] = {"", ":2", ":4", ":8"}; - bfd_vma base_disp; - bfd_vma outer_disp; - char buf[40]; - char vmabuf[50]; - - word = NEXTWORD (p); - - /* Generate the text for the index register. - Where this will be output is not yet determined. */ - sprintf (buf, "%s:%c%s", - reg_names[(word >> 12) & 0xf], - (word & 0x800) ? 'l' : 'w', - scales[(word >> 9) & 3]); - - /* Handle the 68000 style of indexing. */ - - if ((word & 0x100) == 0) - { - word &= 0xff; - if ((word & 0x80) != 0) - word -= 0x100; - if (basereg == -1) - word += addr; - print_base (basereg, word, info); - (*info->fprintf_func) (info->stream, ",%s)", buf); - return p; - } - - /* Handle the generalized kind. */ - /* First, compute the displacement to add to the base register. */ - - if (word & 0200) - { - if (basereg == -1) - basereg = -3; - else - basereg = -2; - } - if (word & 0100) - buf[0] = '\0'; - base_disp = 0; - switch ((word >> 4) & 3) - { - case 2: - base_disp = NEXTWORD (p); - break; - case 3: - base_disp = NEXTLONG (p); - } - if (basereg == -1) - base_disp += addr; - - /* Handle single-level case (not indirect) */ - - if ((word & 7) == 0) - { - print_base (basereg, base_disp, info); - if (buf[0] != '\0') - (*info->fprintf_func) (info->stream, ",%s", buf); - (*info->fprintf_func) (info->stream, ")"); - return p; - } - - /* Two level. Compute displacement to add after indirection. */ - - outer_disp = 0; - switch (word & 3) - { - case 2: - outer_disp = NEXTWORD (p); - break; - case 3: - outer_disp = NEXTLONG (p); - } - - print_base (basereg, base_disp, info); - if ((word & 4) == 0 && buf[0] != '\0') - { - (*info->fprintf_func) (info->stream, ",%s", buf); - buf[0] = '\0'; - } - sprintf_vma (vmabuf, outer_disp); - (*info->fprintf_func) (info->stream, ")@(%s", vmabuf); - if (buf[0] != '\0') - (*info->fprintf_func) (info->stream, ",%s", buf); - (*info->fprintf_func) (info->stream, ")"); - - return p; -} - -/* Print a base register REGNO and displacement DISP, on INFO->STREAM. - REGNO = -1 for pc, -2 for none (suppressed). */ - -static void -print_base (regno, disp, info) - int regno; - bfd_vma disp; - disassemble_info *info; -{ - if (regno == -1) - { - (*info->fprintf_func) (info->stream, "%%pc@("); - (*info->print_address_func) (disp, info); - } - else - { - char buf[50]; - - if (regno == -2) - (*info->fprintf_func) (info->stream, "@("); - else if (regno == -3) - (*info->fprintf_func) (info->stream, "%%zpc@("); - else - (*info->fprintf_func) (info->stream, "%s@(", reg_names[regno]); - - sprintf_vma (buf, disp); - (*info->fprintf_func) (info->stream, "%s", buf); - } -} diff --git a/opcodes/m68k-opc.c b/opcodes/m68k-opc.c deleted file mode 100644 index 33fcb16fa40..00000000000 --- a/opcodes/m68k-opc.c +++ /dev/null @@ -1,2130 +0,0 @@ -/* Opcode table for m680[012346]0/m6888[12]/m68851/mcf5200. - Copyright 1989, 91, 92, 93, 94, 95, 96, 1997 Free Software Foundation. - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA -02111-1307, USA. */ - -#include "ansidecl.h" -#include "opcode/m68k.h" - -#define one(x) ((unsigned int) (x) << 16) -#define two(x, y) (((unsigned int) (x) << 16) + (y)) - -/* The assembler requires that all instances of the same mnemonic must - be consecutive. If they aren't, the assembler will bomb at - runtime. */ - -const struct m68k_opcode m68k_opcodes[] = -{ -{"abcd", one(0140400), one(0170770), "DsDd", m68000up }, -{"abcd", one(0140410), one(0170770), "-s-d", m68000up }, - -{"addaw", one(0150300), one(0170700), "*wAd", m68000up }, -{"addal", one(0150700), one(0170700), "*lAd", m68000up | mcf5200 }, - -{"addib", one(0003000), one(0177700), "#b$s", m68000up }, -{"addiw", one(0003100), one(0177700), "#w$s", m68000up }, -{"addil", one(0003200), one(0177700), "#l$s", m68000up }, -{"addil", one(0003200), one(0177700), "#lDs", mcf5200 }, - -{"addqb", one(0050000), one(0170700), "Qd$b", m68000up }, -{"addqw", one(0050100), one(0170700), "Qd%w", m68000up }, -{"addql", one(0050200), one(0170700), "Qd%l", m68000up | mcf5200 }, - -/* The add opcode can generate the adda, addi, and addq instructions. */ -{"addb", one(0050000), one(0170700), "Qd$b", m68000up }, -{"addb", one(0003000), one(0177700), "#b$s", m68000up }, -{"addb", one(0150000), one(0170700), ";bDd", m68000up }, -{"addb", one(0150400), one(0170700), "Dd~b", m68000up }, -{"addw", one(0050100), one(0170700), "Qd%w", m68000up }, -{"addw", one(0150300), one(0170700), "*wAd", m68000up }, -{"addw", one(0003100), one(0177700), "#w$s", m68000up }, -{"addw", one(0150100), one(0170700), "*wDd", m68000up }, -{"addw", one(0150500), one(0170700), "Dd~w", m68000up }, -{"addl", one(0050200), one(0170700), "Qd%l", m68000up | mcf5200 }, -{"addl", one(0003200), one(0177700), "#l$s", m68000up }, -{"addl", one(0003200), one(0177700), "#lDs", mcf5200 }, -{"addl", one(0150700), one(0170700), "*lAd", m68000up | mcf5200 }, -{"addl", one(0150200), one(0170700), "*lDd", m68000up | mcf5200 }, -{"addl", one(0150600), one(0170700), "Dd~l", m68000up | mcf5200 }, - -{"addxb", one(0150400), one(0170770), "DsDd", m68000up }, -{"addxb", one(0150410), one(0170770), "-s-d", m68000up }, -{"addxw", one(0150500), one(0170770), "DsDd", m68000up }, -{"addxw", one(0150510), one(0170770), "-s-d", m68000up }, -{"addxl", one(0150600), one(0170770), "DsDd", m68000up | mcf5200 }, -{"addxl", one(0150610), one(0170770), "-s-d", m68000up }, - -{"andib", one(0001000), one(0177700), "#b$s", m68000up }, -{"andib", one(0001074), one(0177777), "#bCs", m68000up }, -{"andiw", one(0001100), one(0177700), "#w$s", m68000up }, -{"andiw", one(0001174), one(0177777), "#wSs", m68000up }, -{"andil", one(0001200), one(0177700), "#l$s", m68000up }, -{"andil", one(0001200), one(0177700), "#lDs", mcf5200 }, -{"andi", one(0001100), one(0177700), "#w$s", m68000up }, -{"andi", one(0001074), one(0177777), "#bCs", m68000up }, -{"andi", one(0001174), one(0177777), "#wSs", m68000up }, - -/* The and opcode can generate the andi instruction. */ -{"andb", one(0001000), one(0177700), "#b$s", m68000up }, -{"andb", one(0001074), one(0177777), "#bCs", m68000up }, -{"andb", one(0140000), one(0170700), ";bDd", m68000up }, -{"andb", one(0140400), one(0170700), "Dd~b", m68000up }, -{"andw", one(0001100), one(0177700), "#w$s", m68000up }, -{"andw", one(0001174), one(0177777), "#wSs", m68000up }, -{"andw", one(0140100), one(0170700), ";wDd", m68000up }, -{"andw", one(0140500), one(0170700), "Dd~w", m68000up }, -{"andl", one(0001200), one(0177700), "#l$s", m68000up }, -{"andl", one(0001200), one(0177700), "#lDs", mcf5200 }, -{"andl", one(0140200), one(0170700), ";lDd", m68000up | mcf5200 }, -{"andl", one(0140600), one(0170700), "Dd~l", m68000up | mcf5200 }, -{"and", one(0001100), one(0177700), "#w$w", m68000up }, -{"and", one(0001074), one(0177777), "#bCs", m68000up }, -{"and", one(0001174), one(0177777), "#wSs", m68000up }, -{"and", one(0140100), one(0170700), ";wDd", m68000up }, -{"and", one(0140500), one(0170700), "Dd~w", m68000up }, - -{"aslb", one(0160400), one(0170770), "QdDs", m68000up }, -{"aslb", one(0160440), one(0170770), "DdDs", m68000up }, -{"aslw", one(0160500), one(0170770), "QdDs", m68000up }, -{"aslw", one(0160540), one(0170770), "DdDs", m68000up }, -{"aslw", one(0160700), one(0177700), "~s", m68000up }, -{"asll", one(0160600), one(0170770), "QdDs", m68000up | mcf5200 }, -{"asll", one(0160640), one(0170770), "DdDs", m68000up | mcf5200 }, - -{"asrb", one(0160000), one(0170770), "QdDs", m68000up }, -{"asrb", one(0160040), one(0170770), "DdDs", m68000up }, -{"asrw", one(0160100), one(0170770), "QdDs", m68000up }, -{"asrw", one(0160140), one(0170770), "DdDs", m68000up }, -{"asrw", one(0160300), one(0177700), "~s", m68000up }, -{"asrl", one(0160200), one(0170770), "QdDs", m68000up | mcf5200 }, -{"asrl", one(0160240), one(0170770), "DdDs", m68000up | mcf5200 }, - -{"bhiw", one(0061000), one(0177777), "BW", m68000up | mcf5200 }, -{"blsw", one(0061400), one(0177777), "BW", m68000up | mcf5200 }, -{"bccw", one(0062000), one(0177777), "BW", m68000up | mcf5200 }, -{"bcsw", one(0062400), one(0177777), "BW", m68000up | mcf5200 }, -{"bnew", one(0063000), one(0177777), "BW", m68000up | mcf5200 }, -{"beqw", one(0063400), one(0177777), "BW", m68000up | mcf5200 }, -{"bvcw", one(0064000), one(0177777), "BW", m68000up | mcf5200 }, -{"bvsw", one(0064400), one(0177777), "BW", m68000up | mcf5200 }, -{"bplw", one(0065000), one(0177777), "BW", m68000up | mcf5200 }, -{"bmiw", one(0065400), one(0177777), "BW", m68000up | mcf5200 }, -{"bgew", one(0066000), one(0177777), "BW", m68000up | mcf5200 }, -{"bltw", one(0066400), one(0177777), "BW", m68000up | mcf5200 }, -{"bgtw", one(0067000), one(0177777), "BW", m68000up | mcf5200 }, -{"blew", one(0067400), one(0177777), "BW", m68000up | mcf5200 }, - -{"bhil", one(0061377), one(0177777), "BL", m68020up | cpu32 }, -{"blsl", one(0061777), one(0177777), "BL", m68020up | cpu32 }, -{"bccl", one(0062377), one(0177777), "BL", m68020up | cpu32 }, -{"bcsl", one(0062777), one(0177777), "BL", m68020up | cpu32 }, -{"bnel", one(0063377), one(0177777), "BL", m68020up | cpu32 }, -{"beql", one(0063777), one(0177777), "BL", m68020up | cpu32 }, -{"bvcl", one(0064377), one(0177777), "BL", m68020up | cpu32 }, -{"bvsl", one(0064777), one(0177777), "BL", m68020up | cpu32 }, -{"bpll", one(0065377), one(0177777), "BL", m68020up | cpu32 }, -{"bmil", one(0065777), one(0177777), "BL", m68020up | cpu32 }, -{"bgel", one(0066377), one(0177777), "BL", m68020up | cpu32 }, -{"bltl", one(0066777), one(0177777), "BL", m68020up | cpu32 }, -{"bgtl", one(0067377), one(0177777), "BL", m68020up | cpu32 }, -{"blel", one(0067777), one(0177777), "BL", m68020up | cpu32 }, - -{"bhis", one(0061000), one(0177400), "BB", m68000up | mcf5200 }, -{"blss", one(0061400), one(0177400), "BB", m68000up | mcf5200 }, -{"bccs", one(0062000), one(0177400), "BB", m68000up | mcf5200 }, -{"bcss", one(0062400), one(0177400), "BB", m68000up | mcf5200 }, -{"bnes", one(0063000), one(0177400), "BB", m68000up | mcf5200 }, -{"beqs", one(0063400), one(0177400), "BB", m68000up | mcf5200 }, -{"bvcs", one(0064000), one(0177400), "BB", m68000up | mcf5200 }, -{"bvss", one(0064400), one(0177400), "BB", m68000up | mcf5200 }, -{"bpls", one(0065000), one(0177400), "BB", m68000up | mcf5200 }, -{"bmis", one(0065400), one(0177400), "BB", m68000up | mcf5200 }, -{"bges", one(0066000), one(0177400), "BB", m68000up | mcf5200 }, -{"blts", one(0066400), one(0177400), "BB", m68000up | mcf5200 }, -{"bgts", one(0067000), one(0177400), "BB", m68000up | mcf5200 }, -{"bles", one(0067400), one(0177400), "BB", m68000up | mcf5200 }, - -{"jhi", one(0061000), one(0177400), "Bg", m68000up | mcf5200 }, -{"jls", one(0061400), one(0177400), "Bg", m68000up | mcf5200 }, -{"jcc", one(0062000), one(0177400), "Bg", m68000up | mcf5200 }, -{"jcs", one(0062400), one(0177400), "Bg", m68000up | mcf5200 }, -{"jne", one(0063000), one(0177400), "Bg", m68000up | mcf5200 }, -{"jeq", one(0063400), one(0177400), "Bg", m68000up | mcf5200 }, -{"jvc", one(0064000), one(0177400), "Bg", m68000up | mcf5200 }, -{"jvs", one(0064400), one(0177400), "Bg", m68000up | mcf5200 }, -{"jpl", one(0065000), one(0177400), "Bg", m68000up | mcf5200 }, -{"jmi", one(0065400), one(0177400), "Bg", m68000up | mcf5200 }, -{"jge", one(0066000), one(0177400), "Bg", m68000up | mcf5200 }, -{"jlt", one(0066400), one(0177400), "Bg", m68000up | mcf5200 }, -{"jgt", one(0067000), one(0177400), "Bg", m68000up | mcf5200 }, -{"jle", one(0067400), one(0177400), "Bg", m68000up | mcf5200 }, - -{"bchg", one(0000500), one(0170700), "Dd$s", m68000up | mcf5200 }, -{"bchg", one(0004100), one(0177700), "#b$s", m68000up }, -{"bchg", one(0004100), one(0177700), "#bqs", mcf5200 }, - -{"bclr", one(0000600), one(0170700), "Dd$s", m68000up }, -{"bclr", one(0000600), one(0170700), "Ddvs", mcf5200 }, -{"bclr", one(0004200), one(0177700), "#b$s", m68000up }, -{"bclr", one(0004200), one(0177700), "#bqs", mcf5200 }, - -{"bfchg", two(0165300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, -{"bfclr", two(0166300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, -{"bfexts", two(0165700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up }, -{"bfextu", two(0164700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up }, -{"bfffo", two(0166700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up }, -{"bfins", two(0167700, 0), two(0177700, 0100000), "D1?sO2O3", m68020up }, -{"bfset", two(0167300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, -{"bftst", two(0164300, 0), two(0177700, 0170000), "/sO2O3", m68020up }, - -{"bgnd", one(0045372), one(0177777), "", cpu32 }, - -{"bkpt", one(0044110), one(0177770), "ts", m68010up }, - -{"braw", one(0060000), one(0177777), "BW", m68000up | mcf5200 }, -{"bral", one(0060377), one(0177777), "BL", m68020up | cpu32 }, -{"bras", one(0060000), one(0177400), "BB", m68000up | mcf5200 }, - -{"bset", one(0000700), one(0170700), "Dd$s", m68000up }, -{"bset", one(0000700), one(0170700), "Ddvs", mcf5200 }, -{"bset", one(0004300), one(0177700), "#b$s", m68000up }, -{"bset", one(0004300), one(0177700), "#bqs", mcf5200 }, - -{"bsrw", one(0060400), one(0177777), "BW", m68000up | mcf5200 }, -{"bsrl", one(0060777), one(0177777), "BL", m68020up | cpu32 }, -{"bsrs", one(0060400), one(0177400), "BB", m68000up | mcf5200 }, - -{"btst", one(0000400), one(0170700), "Dd@s", m68000up | mcf5200 }, -{"btst", one(0004000), one(0177700), "#b@s", m68000up }, -{"btst", one(0004000), one(0177700), "#bqs", mcf5200 }, - -{"callm", one(0003300), one(0177700), "#b!s", m68020 }, - -{"cas2w", two(0006374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up }, -{"cas2w", two(0006374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up }, -{"cas2l", two(0007374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up }, -{"cas2l", two(0007374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up }, - -{"casb", two(0005300, 0), two(0177700, 0177070), "D3D2~s", m68020up }, -{"casw", two(0006300, 0), two(0177700, 0177070), "D3D2~s", m68020up }, -{"casl", two(0007300, 0), two(0177700, 0177070), "D3D2~s", m68020up }, - -{"chk2b", two(0000300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 }, -{"chk2w", two(0001300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 }, -{"chk2l", two(0002300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 }, - -{"chkl", one(0040400), one(0170700), ";lDd", m68000up }, -{"chkw", one(0040600), one(0170700), ";wDd", m68000up }, - -#define SCOPE_LINE (0x1 << 3) -#define SCOPE_PAGE (0x2 << 3) -#define SCOPE_ALL (0x3 << 3) - -{"cinva", one(0xf400|SCOPE_ALL), one(0xff38), "ce", m68040up }, -{"cinvl", one(0xf400|SCOPE_LINE), one(0xff38), "ceas", m68040up }, -{"cinvp", one(0xf400|SCOPE_PAGE), one(0xff38), "ceas", m68040up }, - -{"cpusha", one(0xf420|SCOPE_ALL), one(0xff38), "ce", m68040up }, -{"cpushl", one(0xf420|SCOPE_LINE), one(0xff38), "ceas", m68040up }, -{"cpushl", one(0x04e8), one(0xfff8), "as", mcf5200 }, -{"cpushp", one(0xf420|SCOPE_PAGE), one(0xff38), "ceas", m68040up }, - -#undef SCOPE_LINE -#undef SCOPE_PAGE -#undef SCOPE_ALL - -{"clrb", one(0041000), one(0177700), "$s", m68000up | mcf5200 }, -{"clrw", one(0041100), one(0177700), "$s", m68000up | mcf5200 }, -{"clrl", one(0041200), one(0177700), "$s", m68000up | mcf5200 }, - -{"cmp2b", two(0000300,0), two(0177700,07777), "!sR1", m68020up | cpu32 }, -{"cmp2w", two(0001300,0), two(0177700,07777), "!sR1", m68020up | cpu32 }, -{"cmp2l", two(0002300,0), two(0177700,07777), "!sR1", m68020up | cpu32 }, - -{"cmpaw", one(0130300), one(0170700), "*wAd", m68000up }, -{"cmpal", one(0130700), one(0170700), "*lAd", m68000up | mcf5200 }, - -{"cmpib", one(0006000), one(0177700), "#b;s", m68000up }, -{"cmpiw", one(0006100), one(0177700), "#w;s", m68000up }, -{"cmpil", one(0006200), one(0177700), "#l;s", m68000up }, -{"cmpil", one(0006200), one(0177700), "#lDs", mcf5200 }, - -{"cmpmb", one(0130410), one(0170770), "+s+d", m68000up }, -{"cmpmw", one(0130510), one(0170770), "+s+d", m68000up }, -{"cmpml", one(0130610), one(0170770), "+s+d", m68000up }, - -/* The cmp opcode can generate the cmpa, cmpm, and cmpi instructions. */ -{"cmpb", one(0006000), one(0177700), "#b;s", m68000up }, -{"cmpb", one(0130410), one(0170770), "+s+d", m68000up }, -{"cmpb", one(0130000), one(0170700), ";bDd", m68000up }, -{"cmpw", one(0130300), one(0170700), "*wAd", m68000up }, -{"cmpw", one(0006100), one(0177700), "#w;s", m68000up }, -{"cmpw", one(0130510), one(0170770), "+s+d", m68000up }, -{"cmpw", one(0130100), one(0170700), "*wDd", m68000up }, -{"cmpl", one(0130700), one(0170700), "*lAd", m68000up | mcf5200 }, -{"cmpl", one(0006200), one(0177700), "#l;s", m68000up }, -{"cmpl", one(0006200), one(0177700), "#lDs", mcf5200 }, -{"cmpl", one(0130610), one(0170770), "+s+d", m68000up }, -{"cmpl", one(0130200), one(0170700), "*lDd", m68000up | mcf5200 }, - -{"dbcc", one(0052310), one(0177770), "DsBw", m68000up }, -{"dbcs", one(0052710), one(0177770), "DsBw", m68000up }, -{"dbeq", one(0053710), one(0177770), "DsBw", m68000up }, -{"dbf", one(0050710), one(0177770), "DsBw", m68000up }, -{"dbge", one(0056310), one(0177770), "DsBw", m68000up }, -{"dbgt", one(0057310), one(0177770), "DsBw", m68000up }, -{"dbhi", one(0051310), one(0177770), "DsBw", m68000up }, -{"dble", one(0057710), one(0177770), "DsBw", m68000up }, -{"dbls", one(0051710), one(0177770), "DsBw", m68000up }, -{"dblt", one(0056710), one(0177770), "DsBw", m68000up }, -{"dbmi", one(0055710), one(0177770), "DsBw", m68000up }, -{"dbne", one(0053310), one(0177770), "DsBw", m68000up }, -{"dbpl", one(0055310), one(0177770), "DsBw", m68000up }, -{"dbt", one(0050310), one(0177770), "DsBw", m68000up }, -{"dbvc", one(0054310), one(0177770), "DsBw", m68000up }, -{"dbvs", one(0054710), one(0177770), "DsBw", m68000up }, - -{"divsw", one(0100700), one(0170700), ";wDd", m68000up }, -/* start-sanitize-coldfire */ -{"divsw", one(0100700), one(0170700), ";wDd", m68000up|mcfdiv }, -/* end-sanitize-coldfire */ - -{"divsl", two(0046100,0006000),two(0177700,0107770),";lD3D1", m68020up|cpu32 }, -{"divsl", two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 }, -/* start-sanitize-coldfire */ -{"divsl", two(0046100,0004000),two(0177700,0107770),"DsDD", mcfdiv }, -{"divsl", two(0046100,0004000),two(0177700,0107770),"asDD", mcfdiv }, -{"divsl", two(0046100,0004000),two(0177700,0107770),"+sDD", mcfdiv }, -{"divsl", two(0046100,0004000),two(0177700,0107770),"-sDD", mcfdiv }, -{"divsl", two(0046100,0004000),two(0177700,0107770),"dsDD", mcfdiv }, -/* end-sanitize-coldfire */ - -{"divsll", two(0046100,0004000),two(0177700,0107770),";lD3D1",m68020up|cpu32 }, -{"divsll", two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 }, - -{"divuw", one(0100300), one(0170700), ";wDd", m68000up }, -/* start-sanitize-coldfire */ -{"divuw", one(0100300), one(0170700), ";wDd", m68000up|mcfdiv }, -/* end-sanitize-coldfire */ - -{"divul", two(0046100,0002000),two(0177700,0107770),";lD3D1", m68020up|cpu32 }, -{"divul", two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 }, -/* start-sanitize-coldfire */ -{"divul", two(0046100,0000000),two(0177700,0107770),"DsDD", mcfdiv }, -{"divul", two(0046100,0000000),two(0177700,0107770),"asDD", mcfdiv }, -{"divul", two(0046100,0000000),two(0177700,0107770),"+sDD", mcfdiv }, -{"divul", two(0046100,0000000),two(0177700,0107770),"-sDD", mcfdiv }, -{"divul", two(0046100,0000000),two(0177700,0107770),"dsDD", mcfdiv }, -/* end-sanitize-coldfire */ - -{"divull", two(0046100,0000000),two(0177700,0107770),";lD3D1",m68020up|cpu32 }, -{"divull", two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 }, - -{"eorib", one(0005000), one(0177700), "#b$s", m68000up }, -{"eorib", one(0005074), one(0177777), "#bCs", m68000up }, -{"eoriw", one(0005100), one(0177700), "#w$s", m68000up }, -{"eoriw", one(0005174), one(0177777), "#wSs", m68000up }, -{"eoril", one(0005200), one(0177700), "#l$s", m68000up }, -{"eoril", one(0005200), one(0177700), "#lDs", mcf5200 }, -{"eori", one(0005074), one(0177777), "#bCs", m68000up }, -{"eori", one(0005174), one(0177777), "#wSs", m68000up }, -{"eori", one(0005100), one(0177700), "#w$s", m68000up }, - -/* The eor opcode can generate the eori instruction. */ -{"eorb", one(0005000), one(0177700), "#b$s", m68000up }, -{"eorb", one(0005074), one(0177777), "#bCs", m68000up }, -{"eorb", one(0130400), one(0170700), "Dd$s", m68000up }, -{"eorw", one(0005100), one(0177700), "#w$s", m68000up }, -{"eorw", one(0005174), one(0177777), "#wSs", m68000up }, -{"eorw", one(0130500), one(0170700), "Dd$s", m68000up }, -{"eorl", one(0005200), one(0177700), "#l$s", m68000up }, -{"eorl", one(0005200), one(0177700), "#lDs", mcf5200 }, -{"eorl", one(0130600), one(0170700), "Dd$s", m68000up | mcf5200 }, -{"eor", one(0005074), one(0177777), "#bCs", m68000up }, -{"eor", one(0005174), one(0177777), "#wSs", m68000up }, -{"eor", one(0005100), one(0177700), "#w$s", m68000up }, -{"eor", one(0130500), one(0170700), "Dd$s", m68000up }, - -{"exg", one(0140500), one(0170770), "DdDs", m68000up }, -{"exg", one(0140510), one(0170770), "AdAs", m68000up }, -{"exg", one(0140610), one(0170770), "DdAs", m68000up }, -{"exg", one(0140610), one(0170770), "AsDd", m68000up }, - -{"extw", one(0044200), one(0177770), "Ds", m68000up|mcf5200 }, -{"extl", one(0044300), one(0177770), "Ds", m68000up|mcf5200 }, -{"extbl", one(0044700), one(0177770), "Ds", m68020up|cpu32|mcf5200 }, - -/* float stuff starts here */ - -{"fabsb", two(0xF000, 0x5818), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fabsd", two(0xF000, 0x5418), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fabsl", two(0xF000, 0x4018), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fabsp", two(0xF000, 0x4C18), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fabss", two(0xF000, 0x4418), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fabsw", two(0xF000, 0x5018), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fabsx", two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fabsx", two(0xF000, 0x4818), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fabsx", two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"fsabsb", two(0xF000, 0x5858), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fsabsd", two(0xF000, 0x5458), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fsabsl", two(0xF000, 0x4058), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fsabsp", two(0xF000, 0x4C58), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fsabss", two(0xF000, 0x4458), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fsabsw", two(0xF000, 0x5058), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fsabsx", two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fsabsx", two(0xF000, 0x4858), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, -{"fsabsx", two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiFt", m68040up }, - -{"fdabsb", two(0xF000, 0x585c), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up}, -{"fdabsd", two(0xF000, 0x545c), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up}, -{"fdabsl", two(0xF000, 0x405c), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up}, -{"fdabsp", two(0xF000, 0x4C5c), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up}, -{"fdabss", two(0xF000, 0x445c), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up}, -{"fdabsw", two(0xF000, 0x505c), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up}, -{"fdabsx", two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiF8F7", m68040up}, -{"fdabsx", two(0xF000, 0x485c), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up}, -{"fdabsx", two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiFt", m68040up}, - -{"facosb", two(0xF000, 0x581C), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"facosd", two(0xF000, 0x541C), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"facosl", two(0xF000, 0x401C), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"facosp", two(0xF000, 0x4C1C), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"facoss", two(0xF000, 0x441C), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"facosw", two(0xF000, 0x501C), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"facosx", two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"facosx", two(0xF000, 0x481C), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"facosx", two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"faddb", two(0xF000, 0x5822), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"faddd", two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"faddl", two(0xF000, 0x4022), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"faddp", two(0xF000, 0x4C22), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fadds", two(0xF000, 0x4422), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"faddw", two(0xF000, 0x5022), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"faddx", two(0xF000, 0x0022), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"faddx", two(0xF000, 0x4822), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, - -{"fsaddb", two(0xF000, 0x5862), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fsaddd", two(0xF000, 0x5462), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fsaddl", two(0xF000, 0x4062), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fsaddp", two(0xF000, 0x4C62), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fsadds", two(0xF000, 0x4462), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fsaddw", two(0xF000, 0x5062), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fsaddx", two(0xF000, 0x0062), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fsaddx", two(0xF000, 0x4862), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, - -{"fdaddb", two(0xF000, 0x5866), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fdaddd", two(0xF000, 0x5466), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fdaddl", two(0xF000, 0x4066), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fdaddp", two(0xF000, 0x4C66), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fdadds", two(0xF000, 0x4466), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fdaddw", two(0xF000, 0x5066), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fdaddx", two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fdaddx", two(0xF000, 0x4866), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, - -{"fasinb", two(0xF000, 0x580C), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fasind", two(0xF000, 0x540C), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fasinl", two(0xF000, 0x400C), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fasinp", two(0xF000, 0x4C0C), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fasins", two(0xF000, 0x440C), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fasinw", two(0xF000, 0x500C), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fasinx", two(0xF000, 0x000C), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fasinx", two(0xF000, 0x480C), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fasinx", two(0xF000, 0x000C), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"fatanb", two(0xF000, 0x580A), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fatand", two(0xF000, 0x540A), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fatanl", two(0xF000, 0x400A), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fatanp", two(0xF000, 0x4C0A), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fatans", two(0xF000, 0x440A), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fatanw", two(0xF000, 0x500A), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fatanx", two(0xF000, 0x000A), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fatanx", two(0xF000, 0x480A), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fatanx", two(0xF000, 0x000A), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"fatanhb", two(0xF000, 0x580D), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fatanhd", two(0xF000, 0x540D), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fatanhl", two(0xF000, 0x400D), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fatanhp", two(0xF000, 0x4C0D), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fatanhs", two(0xF000, 0x440D), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fatanhw", two(0xF000, 0x500D), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fatanhx", two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fatanhx", two(0xF000, 0x480D), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fatanhx", two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"fbeq", one(0xF081), one(0xF1FF), "IdBW", mfloat }, -{"fbf", one(0xF080), one(0xF1FF), "IdBW", mfloat }, -{"fbge", one(0xF093), one(0xF1FF), "IdBW", mfloat }, -{"fbgl", one(0xF096), one(0xF1FF), "IdBW", mfloat }, -{"fbgle", one(0xF097), one(0xF1FF), "IdBW", mfloat }, -{"fbgt", one(0xF092), one(0xF1FF), "IdBW", mfloat }, -{"fble", one(0xF095), one(0xF1FF), "IdBW", mfloat }, -{"fblt", one(0xF094), one(0xF1FF), "IdBW", mfloat }, -{"fbne", one(0xF08E), one(0xF1FF), "IdBW", mfloat }, -{"fbnge", one(0xF09C), one(0xF1FF), "IdBW", mfloat }, -{"fbngl", one(0xF099), one(0xF1FF), "IdBW", mfloat }, -{"fbngle", one(0xF098), one(0xF1FF), "IdBW", mfloat }, -{"fbngt", one(0xF09D), one(0xF1FF), "IdBW", mfloat }, -{"fbnle", one(0xF09A), one(0xF1FF), "IdBW", mfloat }, -{"fbnlt", one(0xF09B), one(0xF1FF), "IdBW", mfloat }, -{"fboge", one(0xF083), one(0xF1FF), "IdBW", mfloat }, -{"fbogl", one(0xF086), one(0xF1FF), "IdBW", mfloat }, -{"fbogt", one(0xF082), one(0xF1FF), "IdBW", mfloat }, -{"fbole", one(0xF085), one(0xF1FF), "IdBW", mfloat }, -{"fbolt", one(0xF084), one(0xF1FF), "IdBW", mfloat }, -{"fbor", one(0xF087), one(0xF1FF), "IdBW", mfloat }, -{"fbseq", one(0xF091), one(0xF1FF), "IdBW", mfloat }, -{"fbsf", one(0xF090), one(0xF1FF), "IdBW", mfloat }, -{"fbsne", one(0xF09E), one(0xF1FF), "IdBW", mfloat }, -{"fbst", one(0xF09F), one(0xF1FF), "IdBW", mfloat }, -{"fbt", one(0xF08F), one(0xF1FF), "IdBW", mfloat }, -{"fbueq", one(0xF089), one(0xF1FF), "IdBW", mfloat }, -{"fbuge", one(0xF08B), one(0xF1FF), "IdBW", mfloat }, -{"fbugt", one(0xF08A), one(0xF1FF), "IdBW", mfloat }, -{"fbule", one(0xF08D), one(0xF1FF), "IdBW", mfloat }, -{"fbult", one(0xF08C), one(0xF1FF), "IdBW", mfloat }, -{"fbun", one(0xF088), one(0xF1FF), "IdBW", mfloat }, - -{"fbeql", one(0xF0C1), one(0xF1FF), "IdBC", mfloat }, -{"fbfl", one(0xF0C0), one(0xF1FF), "IdBC", mfloat }, -{"fbgel", one(0xF0D3), one(0xF1FF), "IdBC", mfloat }, -{"fbgll", one(0xF0D6), one(0xF1FF), "IdBC", mfloat }, -{"fbglel", one(0xF0D7), one(0xF1FF), "IdBC", mfloat }, -{"fbgtl", one(0xF0D2), one(0xF1FF), "IdBC", mfloat }, -{"fblel", one(0xF0D5), one(0xF1FF), "IdBC", mfloat }, -{"fbltl", one(0xF0D4), one(0xF1FF), "IdBC", mfloat }, -{"fbnel", one(0xF0CE), one(0xF1FF), "IdBC", mfloat }, -{"fbngel", one(0xF0DC), one(0xF1FF), "IdBC", mfloat }, -{"fbngll", one(0xF0D9), one(0xF1FF), "IdBC", mfloat }, -{"fbnglel", one(0xF0D8), one(0xF1FF), "IdBC", mfloat }, -{"fbngtl", one(0xF0DD), one(0xF1FF), "IdBC", mfloat }, -{"fbnlel", one(0xF0DA), one(0xF1FF), "IdBC", mfloat }, -{"fbnltl", one(0xF0DB), one(0xF1FF), "IdBC", mfloat }, -{"fbogel", one(0xF0C3), one(0xF1FF), "IdBC", mfloat }, -{"fbogll", one(0xF0C6), one(0xF1FF), "IdBC", mfloat }, -{"fbogtl", one(0xF0C2), one(0xF1FF), "IdBC", mfloat }, -{"fbolel", one(0xF0C5), one(0xF1FF), "IdBC", mfloat }, -{"fboltl", one(0xF0C4), one(0xF1FF), "IdBC", mfloat }, -{"fborl", one(0xF0C7), one(0xF1FF), "IdBC", mfloat }, -{"fbseql", one(0xF0D1), one(0xF1FF), "IdBC", mfloat }, -{"fbsfl", one(0xF0D0), one(0xF1FF), "IdBC", mfloat }, -{"fbsnel", one(0xF0DE), one(0xF1FF), "IdBC", mfloat }, -{"fbstl", one(0xF0DF), one(0xF1FF), "IdBC", mfloat }, -{"fbtl", one(0xF0CF), one(0xF1FF), "IdBC", mfloat }, -{"fbueql", one(0xF0C9), one(0xF1FF), "IdBC", mfloat }, -{"fbugel", one(0xF0CB), one(0xF1FF), "IdBC", mfloat }, -{"fbugtl", one(0xF0CA), one(0xF1FF), "IdBC", mfloat }, -{"fbulel", one(0xF0CD), one(0xF1FF), "IdBC", mfloat }, -{"fbultl", one(0xF0CC), one(0xF1FF), "IdBC", mfloat }, -{"fbunl", one(0xF0C8), one(0xF1FF), "IdBC", mfloat }, - -{"fjeq", one(0xF081), one(0xF1BF), "IdBc", mfloat }, -{"fjf", one(0xF080), one(0xF1BF), "IdBc", mfloat }, -{"fjge", one(0xF093), one(0xF1BF), "IdBc", mfloat }, -{"fjgl", one(0xF096), one(0xF1BF), "IdBc", mfloat }, -{"fjgle", one(0xF097), one(0xF1BF), "IdBc", mfloat }, -{"fjgt", one(0xF092), one(0xF1BF), "IdBc", mfloat }, -{"fjle", one(0xF095), one(0xF1BF), "IdBc", mfloat }, -{"fjlt", one(0xF094), one(0xF1BF), "IdBc", mfloat }, -{"fjne", one(0xF08E), one(0xF1BF), "IdBc", mfloat }, -{"fjnge", one(0xF09C), one(0xF1BF), "IdBc", mfloat }, -{"fjngl", one(0xF099), one(0xF1BF), "IdBc", mfloat }, -{"fjngle", one(0xF098), one(0xF1BF), "IdBc", mfloat }, -{"fjngt", one(0xF09D), one(0xF1BF), "IdBc", mfloat }, -{"fjnle", one(0xF09A), one(0xF1BF), "IdBc", mfloat }, -{"fjnlt", one(0xF09B), one(0xF1BF), "IdBc", mfloat }, -{"fjoge", one(0xF083), one(0xF1BF), "IdBc", mfloat }, -{"fjogl", one(0xF086), one(0xF1BF), "IdBc", mfloat }, -{"fjogt", one(0xF082), one(0xF1BF), "IdBc", mfloat }, -{"fjole", one(0xF085), one(0xF1BF), "IdBc", mfloat }, -{"fjolt", one(0xF084), one(0xF1BF), "IdBc", mfloat }, -{"fjor", one(0xF087), one(0xF1BF), "IdBc", mfloat }, -{"fjseq", one(0xF091), one(0xF1BF), "IdBc", mfloat }, -{"fjsf", one(0xF090), one(0xF1BF), "IdBc", mfloat }, -{"fjsne", one(0xF09E), one(0xF1BF), "IdBc", mfloat }, -{"fjst", one(0xF09F), one(0xF1BF), "IdBc", mfloat }, -{"fjt", one(0xF08F), one(0xF1BF), "IdBc", mfloat }, -{"fjueq", one(0xF089), one(0xF1BF), "IdBc", mfloat }, -{"fjuge", one(0xF08B), one(0xF1BF), "IdBc", mfloat }, -{"fjugt", one(0xF08A), one(0xF1BF), "IdBc", mfloat }, -{"fjule", one(0xF08D), one(0xF1BF), "IdBc", mfloat }, -{"fjult", one(0xF08C), one(0xF1BF), "IdBc", mfloat }, -{"fjun", one(0xF088), one(0xF1BF), "IdBc", mfloat }, - -{"fcmpb", two(0xF000, 0x5838), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fcmpd", two(0xF000, 0x5438), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fcmpl", two(0xF000, 0x4038), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fcmpp", two(0xF000, 0x4C38), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fcmps", two(0xF000, 0x4438), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fcmpw", two(0xF000, 0x5038), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fcmpx", two(0xF000, 0x0038), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fcmpx", two(0xF000, 0x4838), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, - -{"fcosb", two(0xF000, 0x581D), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fcosd", two(0xF000, 0x541D), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fcosl", two(0xF000, 0x401D), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fcosp", two(0xF000, 0x4C1D), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fcoss", two(0xF000, 0x441D), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fcosw", two(0xF000, 0x501D), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fcosx", two(0xF000, 0x001D), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fcosx", two(0xF000, 0x481D), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fcosx", two(0xF000, 0x001D), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"fcoshb", two(0xF000, 0x5819), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fcoshd", two(0xF000, 0x5419), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fcoshl", two(0xF000, 0x4019), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fcoshp", two(0xF000, 0x4C19), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fcoshs", two(0xF000, 0x4419), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fcoshw", two(0xF000, 0x5019), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fcoshx", two(0xF000, 0x0019), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fcoshx", two(0xF000, 0x4819), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fcoshx", two(0xF000, 0x0019), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"fdbeq", two(0xF048, 0x0001), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbf", two(0xF048, 0x0000), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbge", two(0xF048, 0x0013), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbgl", two(0xF048, 0x0016), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbgle", two(0xF048, 0x0017), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbgt", two(0xF048, 0x0012), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdble", two(0xF048, 0x0015), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdblt", two(0xF048, 0x0014), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbne", two(0xF048, 0x000E), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbnge", two(0xF048, 0x001C), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbngl", two(0xF048, 0x0019), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbngle", two(0xF048, 0x0018), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbngt", two(0xF048, 0x001D), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbnle", two(0xF048, 0x001A), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbnlt", two(0xF048, 0x001B), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdboge", two(0xF048, 0x0003), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbogl", two(0xF048, 0x0006), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbogt", two(0xF048, 0x0002), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbole", two(0xF048, 0x0005), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbolt", two(0xF048, 0x0004), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbor", two(0xF048, 0x0007), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbseq", two(0xF048, 0x0011), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbsf", two(0xF048, 0x0010), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbsne", two(0xF048, 0x001E), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbst", two(0xF048, 0x001F), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbt", two(0xF048, 0x000F), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbueq", two(0xF048, 0x0009), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbuge", two(0xF048, 0x000B), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbugt", two(0xF048, 0x000A), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbule", two(0xF048, 0x000D), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbult", two(0xF048, 0x000C), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, -{"fdbun", two(0xF048, 0x0008), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, - -{"fdivb", two(0xF000, 0x5820), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fdivd", two(0xF000, 0x5420), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fdivl", two(0xF000, 0x4020), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fdivp", two(0xF000, 0x4C20), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fdivs", two(0xF000, 0x4420), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fdivw", two(0xF000, 0x5020), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fdivx", two(0xF000, 0x0020), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fdivx", two(0xF000, 0x4820), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, - -{"fsdivb", two(0xF000, 0x5860), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fsdivd", two(0xF000, 0x5460), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fsdivl", two(0xF000, 0x4060), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fsdivp", two(0xF000, 0x4C60), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fsdivs", two(0xF000, 0x4460), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fsdivw", two(0xF000, 0x5060), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fsdivx", two(0xF000, 0x0060), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fsdivx", two(0xF000, 0x4860), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, - -{"fddivb", two(0xF000, 0x5864), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fddivd", two(0xF000, 0x5464), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fddivl", two(0xF000, 0x4064), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fddivp", two(0xF000, 0x4C64), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fddivs", two(0xF000, 0x4464), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fddivw", two(0xF000, 0x5064), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fddivx", two(0xF000, 0x0064), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fddivx", two(0xF000, 0x4864), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, - -{"fetoxb", two(0xF000, 0x5810), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fetoxd", two(0xF000, 0x5410), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fetoxl", two(0xF000, 0x4010), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fetoxp", two(0xF000, 0x4C10), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fetoxs", two(0xF000, 0x4410), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fetoxw", two(0xF000, 0x5010), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fetoxx", two(0xF000, 0x0010), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fetoxx", two(0xF000, 0x4810), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fetoxx", two(0xF000, 0x0010), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"fetoxm1b", two(0xF000, 0x5808), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fetoxm1d", two(0xF000, 0x5408), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fetoxm1l", two(0xF000, 0x4008), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fetoxm1p", two(0xF000, 0x4C08), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fetoxm1s", two(0xF000, 0x4408), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fetoxm1w", two(0xF000, 0x5008), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fetoxm1x", two(0xF000, 0x0008), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fetoxm1x", two(0xF000, 0x4808), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fetoxm1x", two(0xF000, 0x0008), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"fgetexpb", two(0xF000, 0x581E), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fgetexpd", two(0xF000, 0x541E), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fgetexpl", two(0xF000, 0x401E), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fgetexpp", two(0xF000, 0x4C1E), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fgetexps", two(0xF000, 0x441E), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fgetexpw", two(0xF000, 0x501E), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fgetexpx", two(0xF000, 0x001E), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fgetexpx", two(0xF000, 0x481E), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fgetexpx", two(0xF000, 0x001E), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"fgetmanb", two(0xF000, 0x581F), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fgetmand", two(0xF000, 0x541F), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fgetmanl", two(0xF000, 0x401F), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fgetmanp", two(0xF000, 0x4C1F), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fgetmans", two(0xF000, 0x441F), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fgetmanw", two(0xF000, 0x501F), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fgetmanx", two(0xF000, 0x001F), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fgetmanx", two(0xF000, 0x481F), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fgetmanx", two(0xF000, 0x001F), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"fintb", two(0xF000, 0x5801), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fintd", two(0xF000, 0x5401), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fintl", two(0xF000, 0x4001), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fintp", two(0xF000, 0x4C01), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fints", two(0xF000, 0x4401), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fintw", two(0xF000, 0x5001), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fintx", two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fintx", two(0xF000, 0x4801), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fintx", two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"fintrzb", two(0xF000, 0x5803), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fintrzd", two(0xF000, 0x5403), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fintrzl", two(0xF000, 0x4003), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fintrzp", two(0xF000, 0x4C03), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fintrzs", two(0xF000, 0x4403), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fintrzw", two(0xF000, 0x5003), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fintrzx", two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fintrzx", two(0xF000, 0x4803), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fintrzx", two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"flog10b", two(0xF000, 0x5815), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"flog10d", two(0xF000, 0x5415), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"flog10l", two(0xF000, 0x4015), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"flog10p", two(0xF000, 0x4C15), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"flog10s", two(0xF000, 0x4415), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"flog10w", two(0xF000, 0x5015), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"flog10x", two(0xF000, 0x0015), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"flog10x", two(0xF000, 0x4815), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"flog10x", two(0xF000, 0x0015), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"flog2b", two(0xF000, 0x5816), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"flog2d", two(0xF000, 0x5416), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"flog2l", two(0xF000, 0x4016), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"flog2p", two(0xF000, 0x4C16), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"flog2s", two(0xF000, 0x4416), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"flog2w", two(0xF000, 0x5016), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"flog2x", two(0xF000, 0x0016), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"flog2x", two(0xF000, 0x4816), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"flog2x", two(0xF000, 0x0016), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"flognb", two(0xF000, 0x5814), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"flognd", two(0xF000, 0x5414), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"flognl", two(0xF000, 0x4014), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"flognp", two(0xF000, 0x4C14), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"flogns", two(0xF000, 0x4414), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"flognw", two(0xF000, 0x5014), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"flognx", two(0xF000, 0x0014), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"flognx", two(0xF000, 0x4814), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"flognx", two(0xF000, 0x0014), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"flognp1b", two(0xF000, 0x5806), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"flognp1d", two(0xF000, 0x5406), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"flognp1l", two(0xF000, 0x4006), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"flognp1p", two(0xF000, 0x4C06), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"flognp1s", two(0xF000, 0x4406), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"flognp1w", two(0xF000, 0x5006), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"flognp1x", two(0xF000, 0x0006), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"flognp1x", two(0xF000, 0x4806), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"flognp1x", two(0xF000, 0x0006), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"fmodb", two(0xF000, 0x5821), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fmodd", two(0xF000, 0x5421), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fmodl", two(0xF000, 0x4021), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fmodp", two(0xF000, 0x4C21), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fmods", two(0xF000, 0x4421), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fmodw", two(0xF000, 0x5021), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fmodx", two(0xF000, 0x0021), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fmodx", two(0xF000, 0x4821), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, - -{"fmoveb", two(0xF000, 0x5800), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fmoveb", two(0xF000, 0x7800), two(0xF1C0, 0xFC7F), "IiF7$b", mfloat }, -{"fmoved", two(0xF000, 0x5400), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fmoved", two(0xF000, 0x7400), two(0xF1C0, 0xFC7F), "IiF7~F", mfloat }, -{"fmovel", two(0xF000, 0x4000), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fmovel", two(0xF000, 0x6000), two(0xF1C0, 0xFC7F), "IiF7$l", mfloat }, -/* FIXME: the next two variants should not permit moving an address - register to anything but the floating point instruction register. */ -{"fmovel", two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat }, -{"fmovel", two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*ls8", mfloat }, -{"fmovep", two(0xF000, 0x4C00), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fmovep", two(0xF000, 0x6C00), two(0xF1C0, 0xFC00), "IiF7~pkC", mfloat }, -{"fmovep", two(0xF000, 0x7C00), two(0xF1C0, 0xFC0F), "IiF7~pDk", mfloat }, -{"fmoves", two(0xF000, 0x4400), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fmoves", two(0xF000, 0x6400), two(0xF1C0, 0xFC7F), "IiF7$f", mfloat }, -{"fmovew", two(0xF000, 0x5000), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fmovew", two(0xF000, 0x7000), two(0xF1C0, 0xFC7F), "IiF7$w", mfloat }, -{"fmovex", two(0xF000, 0x0000), two(0xF1FF, 0xE07F), "IiF8F7", mfloat }, -{"fmovex", two(0xF000, 0x4800), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fmovex", two(0xF000, 0x6800), two(0xF1C0, 0xFC7F), "IiF7~x", mfloat }, - -{"fsmoveb", two(0xF000, 0x5840), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fsmoved", two(0xF000, 0x5440), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fsmovel", two(0xF000, 0x4040), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fsmoves", two(0xF000, 0x4440), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fsmovew", two(0xF000, 0x5040), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fsmovex", two(0xF000, 0x0040), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fsmovex", two(0xF000, 0x4840), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, -{"fsmovep", two(0xF000, 0x4C40), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, - -{"fdmoveb", two(0xF000, 0x5844), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fdmoved", two(0xF000, 0x5444), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fdmovel", two(0xF000, 0x4044), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fdmoves", two(0xF000, 0x4444), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fdmovew", two(0xF000, 0x5044), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fdmovex", two(0xF000, 0x0044), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fdmovex", two(0xF000, 0x4844), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, -{"fdmovep", two(0xF000, 0x4C44), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, - -{"fmovecrx", two(0xF000, 0x5C00), two(0xF1FF, 0xFC00), "Ii#CF7", mfloat }, - -{"fmovemx", two(0xF000, 0xF800), two(0xF1C0, 0xFF8F), "IiDk&s", mfloat }, -{"fmovemx", two(0xF020, 0xE800), two(0xF1F8, 0xFF8F), "IiDk-s", mfloat }, -{"fmovemx", two(0xF000, 0xD800), two(0xF1C0, 0xFF8F), "Ii&sDk", mfloat }, -{"fmovemx", two(0xF018, 0xD800), two(0xF1F8, 0xFF8F), "Ii+sDk", mfloat }, -{"fmovemx", two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Idl3&s", mfloat }, -{"fmovemx", two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Id#3&s", mfloat }, -{"fmovemx", two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&sl3", mfloat }, -{"fmovemx", two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&s#3", mfloat }, -{"fmovemx", two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "IdL3-s", mfloat }, -{"fmovemx", two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "Id#3-s", mfloat }, -{"fmovemx", two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+sl3", mfloat }, -{"fmovemx", two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+s#3", mfloat }, - -{"fmoveml", two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat }, -{"fmoveml", two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "IiL8~s", mfloat }, -/* FIXME: In the next instruction, we should only permit %dn if the - target is a single register. We should only permit %an if the - target is a single %fpiar. */ -{"fmoveml", two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*lL8", mfloat }, - -{"fmovem", two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "IdL3-s", mfloat }, -{"fmovem", two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Idl3&s", mfloat }, -{"fmovem", two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+sl3", mfloat }, -{"fmovem", two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&sl3", mfloat }, -{"fmovem", two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "Id#3-s", mfloat }, -{"fmovem", two(0xF020, 0xE800), two(0xF1F8, 0xFF8F), "IiDk-s", mfloat }, -{"fmovem", two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Id#3&s", mfloat }, -{"fmovem", two(0xF000, 0xF800), two(0xF1C0, 0xFF8F), "IiDk&s", mfloat }, -{"fmovem", two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+s#3", mfloat }, -{"fmovem", two(0xF018, 0xD800), two(0xF1F8, 0xFF8F), "Ii+sDk", mfloat }, -{"fmovem", two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&s#3", mfloat }, -{"fmovem", two(0xF000, 0xD800), two(0xF1C0, 0xFF8F), "Ii&sDk", mfloat }, -{"fmovem", two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat }, -{"fmovem", two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*ss8", mfloat }, -{"fmovem", two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "IiL8~s", mfloat }, -{"fmovem", two(0xF000, 0x8000), two(0xF2C0, 0xE3FF), "Ii*sL8", mfloat }, - -{"fmulb", two(0xF000, 0x5823), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fmuld", two(0xF000, 0x5423), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fmull", two(0xF000, 0x4023), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fmulp", two(0xF000, 0x4C23), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fmuls", two(0xF000, 0x4423), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fmulw", two(0xF000, 0x5023), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fmulx", two(0xF000, 0x0023), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fmulx", two(0xF000, 0x4823), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, - -{"fsmulb", two(0xF000, 0x5863), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fsmuld", two(0xF000, 0x5463), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fsmull", two(0xF000, 0x4063), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fsmulp", two(0xF000, 0x4C63), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fsmuls", two(0xF000, 0x4463), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fsmulw", two(0xF000, 0x5063), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fsmulx", two(0xF000, 0x0063), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fsmulx", two(0xF000, 0x4863), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, - -{"fdmulb", two(0xF000, 0x5867), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fdmuld", two(0xF000, 0x5467), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fdmull", two(0xF000, 0x4067), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fdmulp", two(0xF000, 0x4C67), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fdmuls", two(0xF000, 0x4467), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fdmulw", two(0xF000, 0x5067), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fdmulx", two(0xF000, 0x0067), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fdmulx", two(0xF000, 0x4867), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, - -{"fnegb", two(0xF000, 0x581A), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fnegd", two(0xF000, 0x541A), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fnegl", two(0xF000, 0x401A), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fnegp", two(0xF000, 0x4C1A), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fnegs", two(0xF000, 0x441A), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fnegw", two(0xF000, 0x501A), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fnegx", two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fnegx", two(0xF000, 0x481A), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fnegx", two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"fsnegb", two(0xF000, 0x585A), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fsnegd", two(0xF000, 0x545A), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fsnegl", two(0xF000, 0x405A), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fsnegp", two(0xF000, 0x4C5A), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fsnegs", two(0xF000, 0x445A), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fsnegw", two(0xF000, 0x505A), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fsnegx", two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fsnegx", two(0xF000, 0x485A), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, -{"fsnegx", two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiFt", m68040up }, - -{"fdnegb", two(0xF000, 0x585E), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fdnegd", two(0xF000, 0x545E), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fdnegl", two(0xF000, 0x405E), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fdnegp", two(0xF000, 0x4C5E), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fdnegs", two(0xF000, 0x445E), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fdnegw", two(0xF000, 0x505E), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fdnegx", two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fdnegx", two(0xF000, 0x485E), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, -{"fdnegx", two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiFt", m68040up }, - -{"fnop", two(0xF280, 0x0000), two(0xFFFF, 0xFFFF), "Ii", mfloat }, - -{"fremb", two(0xF000, 0x5825), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fremd", two(0xF000, 0x5425), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"freml", two(0xF000, 0x4025), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fremp", two(0xF000, 0x4C25), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"frems", two(0xF000, 0x4425), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fremw", two(0xF000, 0x5025), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fremx", two(0xF000, 0x0025), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fremx", two(0xF000, 0x4825), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, - -{"frestore", one(0xF140), one(0xF1C0), "Id<s", mfloat }, - -{"fsave", one(0xF100), one(0xF1C0), "Id>s", mfloat }, - -{"fscaleb", two(0xF000, 0x5826), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fscaled", two(0xF000, 0x5426), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fscalel", two(0xF000, 0x4026), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fscalep", two(0xF000, 0x4C26), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fscales", two(0xF000, 0x4426), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fscalew", two(0xF000, 0x5026), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fscalex", two(0xF000, 0x0026), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fscalex", two(0xF000, 0x4826), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, - -/* $ is necessary to prevent the assembler from using PC-relative. - If @ were used, "label: fseq label" could produce "ftrapeq", - because "label" became "pc@label". */ -{"fseq", two(0xF040, 0x0001), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsf", two(0xF040, 0x0000), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsge", two(0xF040, 0x0013), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsgl", two(0xF040, 0x0016), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsgle", two(0xF040, 0x0017), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsgt", two(0xF040, 0x0012), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsle", two(0xF040, 0x0015), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fslt", two(0xF040, 0x0014), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsne", two(0xF040, 0x000E), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsnge", two(0xF040, 0x001C), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsngl", two(0xF040, 0x0019), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsngle", two(0xF040, 0x0018), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsngt", two(0xF040, 0x001D), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsnle", two(0xF040, 0x001A), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsnlt", two(0xF040, 0x001B), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsoge", two(0xF040, 0x0003), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsogl", two(0xF040, 0x0006), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsogt", two(0xF040, 0x0002), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsole", two(0xF040, 0x0005), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsolt", two(0xF040, 0x0004), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsor", two(0xF040, 0x0007), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsseq", two(0xF040, 0x0011), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fssf", two(0xF040, 0x0010), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fssne", two(0xF040, 0x001E), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsst", two(0xF040, 0x001F), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fst", two(0xF040, 0x000F), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsueq", two(0xF040, 0x0009), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsuge", two(0xF040, 0x000B), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsugt", two(0xF040, 0x000A), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsule", two(0xF040, 0x000D), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsult", two(0xF040, 0x000C), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, -{"fsun", two(0xF040, 0x0008), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, - -{"fsgldivb", two(0xF000, 0x5824), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fsgldivd", two(0xF000, 0x5424), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fsgldivl", two(0xF000, 0x4024), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fsgldivp", two(0xF000, 0x4C24), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fsgldivs", two(0xF000, 0x4424), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fsgldivw", two(0xF000, 0x5024), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fsgldivx", two(0xF000, 0x0024), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fsgldivx", two(0xF000, 0x4824), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fsgldivx", two(0xF000, 0x0024), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"fsglmulb", two(0xF000, 0x5827), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fsglmuld", two(0xF000, 0x5427), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fsglmull", two(0xF000, 0x4027), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fsglmulp", two(0xF000, 0x4C27), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fsglmuls", two(0xF000, 0x4427), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fsglmulw", two(0xF000, 0x5027), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fsglmulx", two(0xF000, 0x0027), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fsglmulx", two(0xF000, 0x4827), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fsglmulx", two(0xF000, 0x0027), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"fsinb", two(0xF000, 0x580E), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fsind", two(0xF000, 0x540E), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fsinl", two(0xF000, 0x400E), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fsinp", two(0xF000, 0x4C0E), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fsins", two(0xF000, 0x440E), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fsinw", two(0xF000, 0x500E), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fsinx", two(0xF000, 0x000E), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fsinx", two(0xF000, 0x480E), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fsinx", two(0xF000, 0x000E), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"fsincosb", two(0xF000, 0x5830), two(0xF1C0, 0xFC78), "Ii;bF3F7", mfloat }, -{"fsincosd", two(0xF000, 0x5430), two(0xF1C0, 0xFC78), "Ii;FF3F7", mfloat }, -{"fsincosl", two(0xF000, 0x4030), two(0xF1C0, 0xFC78), "Ii;lF3F7", mfloat }, -{"fsincosp", two(0xF000, 0x4C30), two(0xF1C0, 0xFC78), "Ii;pF3F7", mfloat }, -{"fsincoss", two(0xF000, 0x4430), two(0xF1C0, 0xFC78), "Ii;fF3F7", mfloat }, -{"fsincosw", two(0xF000, 0x5030), two(0xF1C0, 0xFC78), "Ii;wF3F7", mfloat }, -{"fsincosx", two(0xF000, 0x0030), two(0xF1C0, 0xE078), "IiF8F3F7", mfloat }, -{"fsincosx", two(0xF000, 0x4830), two(0xF1C0, 0xFC78), "Ii;xF3F7", mfloat }, - -{"fsinhb", two(0xF000, 0x5802), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fsinhd", two(0xF000, 0x5402), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fsinhl", two(0xF000, 0x4002), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fsinhp", two(0xF000, 0x4C02), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fsinhs", two(0xF000, 0x4402), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fsinhw", two(0xF000, 0x5002), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fsinhx", two(0xF000, 0x0002), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fsinhx", two(0xF000, 0x4802), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fsinhx", two(0xF000, 0x0002), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"fsqrtb", two(0xF000, 0x5804), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fsqrtd", two(0xF000, 0x5404), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fsqrtl", two(0xF000, 0x4004), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fsqrtp", two(0xF000, 0x4C04), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fsqrts", two(0xF000, 0x4404), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fsqrtw", two(0xF000, 0x5004), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fsqrtx", two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fsqrtx", two(0xF000, 0x4804), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fsqrtx", two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"fssqrtb", two(0xF000, 0x5841), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fssqrtd", two(0xF000, 0x5441), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fssqrtl", two(0xF000, 0x4041), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fssqrtp", two(0xF000, 0x4C41), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fssqrts", two(0xF000, 0x4441), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fssqrtw", two(0xF000, 0x5041), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fssqrtx", two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fssqrtx", two(0xF000, 0x4841), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, -{"fssqrtx", two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiFt", m68040up }, - -{"fdsqrtb", two(0xF000, 0x5845), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fdsqrtd", two(0xF000, 0x5445), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fdsqrtl", two(0xF000, 0x4045), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fdsqrtp", two(0xF000, 0x4C45), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fdsqrts", two(0xF000, 0x4445), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fdsqrtw", two(0xF000, 0x5045), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fdsqrtx", two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fdsqrtx", two(0xF000, 0x4845), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, -{"fdsqrtx", two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiFt", m68040up }, - -{"fsubb", two(0xF000, 0x5828), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"fsubd", two(0xF000, 0x5428), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"fsubl", two(0xF000, 0x4028), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"fsubp", two(0xF000, 0x4C28), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"fsubs", two(0xF000, 0x4428), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"fsubw", two(0xF000, 0x5028), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"fsubx", two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"fsubx", two(0xF000, 0x4828), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"fsubx", two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"fssubb", two(0xF000, 0x5868), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fssubd", two(0xF000, 0x5468), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fssubl", two(0xF000, 0x4068), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fssubp", two(0xF000, 0x4C68), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fssubs", two(0xF000, 0x4468), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fssubw", two(0xF000, 0x5068), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fssubx", two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fssubx", two(0xF000, 0x4868), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, -{"fssubx", two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiFt", m68040up }, - -{"fdsubb", two(0xF000, 0x586c), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, -{"fdsubd", two(0xF000, 0x546c), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, -{"fdsubl", two(0xF000, 0x406c), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, -{"fdsubp", two(0xF000, 0x4C6c), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, -{"fdsubs", two(0xF000, 0x446c), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, -{"fdsubw", two(0xF000, 0x506c), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, -{"fdsubx", two(0xF000, 0x006c), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, -{"fdsubx", two(0xF000, 0x486c), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, -{"fdsubx", two(0xF000, 0x006c), two(0xF1C0, 0xE07F), "IiFt", m68040up }, - -{"ftanb", two(0xF000, 0x580F), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"ftand", two(0xF000, 0x540F), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"ftanl", two(0xF000, 0x400F), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"ftanp", two(0xF000, 0x4C0F), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"ftans", two(0xF000, 0x440F), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"ftanw", two(0xF000, 0x500F), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"ftanx", two(0xF000, 0x000F), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"ftanx", two(0xF000, 0x480F), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"ftanx", two(0xF000, 0x000F), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"ftanhb", two(0xF000, 0x5809), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"ftanhd", two(0xF000, 0x5409), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"ftanhl", two(0xF000, 0x4009), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"ftanhp", two(0xF000, 0x4C09), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"ftanhs", two(0xF000, 0x4409), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"ftanhw", two(0xF000, 0x5009), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"ftanhx", two(0xF000, 0x0009), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"ftanhx", two(0xF000, 0x4809), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"ftanhx", two(0xF000, 0x0009), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"ftentoxb", two(0xF000, 0x5812), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"ftentoxd", two(0xF000, 0x5412), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"ftentoxl", two(0xF000, 0x4012), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"ftentoxp", two(0xF000, 0x4C12), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"ftentoxs", two(0xF000, 0x4412), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"ftentoxw", two(0xF000, 0x5012), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"ftentoxx", two(0xF000, 0x0012), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"ftentoxx", two(0xF000, 0x4812), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"ftentoxx", two(0xF000, 0x0012), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"ftrapeq", two(0xF07C, 0x0001), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapf", two(0xF07C, 0x0000), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapge", two(0xF07C, 0x0013), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapgl", two(0xF07C, 0x0016), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapgle", two(0xF07C, 0x0017), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapgt", two(0xF07C, 0x0012), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftraple", two(0xF07C, 0x0015), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftraplt", two(0xF07C, 0x0014), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapne", two(0xF07C, 0x000E), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapnge", two(0xF07C, 0x001C), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapngl", two(0xF07C, 0x0019), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapngle", two(0xF07C, 0x0018), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapngt", two(0xF07C, 0x001D), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapnle", two(0xF07C, 0x001A), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapnlt", two(0xF07C, 0x001B), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapoge", two(0xF07C, 0x0003), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapogl", two(0xF07C, 0x0006), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapogt", two(0xF07C, 0x0002), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapole", two(0xF07C, 0x0005), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapolt", two(0xF07C, 0x0004), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapor", two(0xF07C, 0x0007), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapseq", two(0xF07C, 0x0011), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapsf", two(0xF07C, 0x0010), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapsne", two(0xF07C, 0x001E), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapst", two(0xF07C, 0x001F), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapt", two(0xF07C, 0x000F), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapueq", two(0xF07C, 0x0009), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapuge", two(0xF07C, 0x000B), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapugt", two(0xF07C, 0x000A), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapule", two(0xF07C, 0x000D), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapult", two(0xF07C, 0x000C), two(0xF1FF, 0xFFFF), "Ii", mfloat }, -{"ftrapun", two(0xF07C, 0x0008), two(0xF1FF, 0xFFFF), "Ii", mfloat }, - -{"ftrapeqw", two(0xF07A, 0x0001), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapfw", two(0xF07A, 0x0000), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapgew", two(0xF07A, 0x0013), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapglw", two(0xF07A, 0x0016), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapglew", two(0xF07A, 0x0017), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapgtw", two(0xF07A, 0x0012), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftraplew", two(0xF07A, 0x0015), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapltw", two(0xF07A, 0x0014), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapnew", two(0xF07A, 0x000E), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapngew", two(0xF07A, 0x001C), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapnglw", two(0xF07A, 0x0019), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapnglew", two(0xF07A, 0x0018), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapngtw", two(0xF07A, 0x001D), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapnlew", two(0xF07A, 0x001A), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapnltw", two(0xF07A, 0x001B), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapogew", two(0xF07A, 0x0003), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapoglw", two(0xF07A, 0x0006), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapogtw", two(0xF07A, 0x0002), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapolew", two(0xF07A, 0x0005), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapoltw", two(0xF07A, 0x0004), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftraporw", two(0xF07A, 0x0007), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapseqw", two(0xF07A, 0x0011), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapsfw", two(0xF07A, 0x0010), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapsnew", two(0xF07A, 0x001E), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapstw", two(0xF07A, 0x001F), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftraptw", two(0xF07A, 0x000F), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapueqw", two(0xF07A, 0x0009), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapugew", two(0xF07A, 0x000B), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapugtw", two(0xF07A, 0x000A), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapulew", two(0xF07A, 0x000D), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapultw", two(0xF07A, 0x000C), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, -{"ftrapunw", two(0xF07A, 0x0008), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, - -{"ftrapeql", two(0xF07B, 0x0001), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapfl", two(0xF07B, 0x0000), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapgel", two(0xF07B, 0x0013), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapgll", two(0xF07B, 0x0016), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapglel", two(0xF07B, 0x0017), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapgtl", two(0xF07B, 0x0012), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftraplel", two(0xF07B, 0x0015), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapltl", two(0xF07B, 0x0014), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapnel", two(0xF07B, 0x000E), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapngel", two(0xF07B, 0x001C), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapngll", two(0xF07B, 0x0019), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapnglel", two(0xF07B, 0x0018), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapngtl", two(0xF07B, 0x001D), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapnlel", two(0xF07B, 0x001A), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapnltl", two(0xF07B, 0x001B), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapogel", two(0xF07B, 0x0003), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapogll", two(0xF07B, 0x0006), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapogtl", two(0xF07B, 0x0002), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapolel", two(0xF07B, 0x0005), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapoltl", two(0xF07B, 0x0004), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftraporl", two(0xF07B, 0x0007), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapseql", two(0xF07B, 0x0011), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapsfl", two(0xF07B, 0x0010), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapsnel", two(0xF07B, 0x001E), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapstl", two(0xF07B, 0x001F), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftraptl", two(0xF07B, 0x000F), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapueql", two(0xF07B, 0x0009), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapugel", two(0xF07B, 0x000B), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapugtl", two(0xF07B, 0x000A), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapulel", two(0xF07B, 0x000D), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapultl", two(0xF07B, 0x000C), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, -{"ftrapunl", two(0xF07B, 0x0008), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, - -{"ftstb", two(0xF000, 0x583A), two(0xF1C0, 0xFC7F), "Ii;b", mfloat }, -{"ftstd", two(0xF000, 0x543A), two(0xF1C0, 0xFC7F), "Ii;F", mfloat }, -{"ftstl", two(0xF000, 0x403A), two(0xF1C0, 0xFC7F), "Ii;l", mfloat }, -{"ftstp", two(0xF000, 0x4C3A), two(0xF1C0, 0xFC7F), "Ii;p", mfloat }, -{"ftsts", two(0xF000, 0x443A), two(0xF1C0, 0xFC7F), "Ii;f", mfloat }, -{"ftstw", two(0xF000, 0x503A), two(0xF1C0, 0xFC7F), "Ii;w", mfloat }, -{"ftstx", two(0xF000, 0x003A), two(0xF1C0, 0xE07F), "IiF8", mfloat }, -{"ftstx", two(0xF000, 0x483A), two(0xF1C0, 0xFC7F), "Ii;x", mfloat }, - -{"ftwotoxb", two(0xF000, 0x5811), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, -{"ftwotoxd", two(0xF000, 0x5411), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, -{"ftwotoxl", two(0xF000, 0x4011), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, -{"ftwotoxp", two(0xF000, 0x4C11), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, -{"ftwotoxs", two(0xF000, 0x4411), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, -{"ftwotoxw", two(0xF000, 0x5011), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, -{"ftwotoxx", two(0xF000, 0x0011), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, -{"ftwotoxx", two(0xF000, 0x4811), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, -{"ftwotoxx", two(0xF000, 0x0011), two(0xF1C0, 0xE07F), "IiFt", mfloat }, - -{"halt", one(0045310), one(0177777), "", mcf5200 }, - -{"illegal", one(0045374), one(0177777), "", m68000up }, - -{"jmp", one(0047300), one(0177700), "!s", m68000up | mcf5200 }, - -{"jra", one(0060000), one(0177400), "Bg", m68000up | mcf5200 }, -{"jra", one(0047300), one(0177700), "!s", m68000up | mcf5200 }, - -{"jsr", one(0047200), one(0177700), "!s", m68000up | mcf5200 }, - -{"jbsr", one(0060400), one(0177400), "Bg", m68000up | mcf5200 }, -{"jbsr", one(0047200), one(0177700), "!s", m68000up | mcf5200 }, - -{"lea", one(0040700), one(0170700), "!sAd", m68000up | mcf5200 }, - -{"lpstop", two(0174000,0000700),two(0177777,0177777),"#w", cpu32|m68060 }, - -{"linkw", one(0047120), one(0177770), "As#w", m68000up | mcf5200 }, -{"linkl", one(0044010), one(0177770), "As#l", m68020up | cpu32 }, -{"link", one(0047120), one(0177770), "As#W", m68000up | mcf5200 }, -{"link", one(0044010), one(0177770), "As#l", m68020up | cpu32 }, - -{"lslb", one(0160410), one(0170770), "QdDs", m68000up }, -{"lslb", one(0160450), one(0170770), "DdDs", m68000up }, -{"lslw", one(0160510), one(0170770), "QdDs", m68000up }, -{"lslw", one(0160550), one(0170770), "DdDs", m68000up }, -{"lslw", one(0161700), one(0177700), "~s", m68000up }, -{"lsll", one(0160610), one(0170770), "QdDs", m68000up | mcf5200 }, -{"lsll", one(0160650), one(0170770), "DdDs", m68000up | mcf5200 }, - -{"lsrb", one(0160010), one(0170770), "QdDs", m68000up }, -{"lsrb", one(0160050), one(0170770), "DdDs", m68000up }, -{"lsrw", one(0160110), one(0170770), "QdDs", m68000up }, -{"lsrw", one(0160150), one(0170770), "DdDs", m68000up }, -{"lsrw", one(0161300), one(0177700), "~s", m68000up }, -{"lsrl", one(0160210), one(0170770), "QdDs", m68000up | mcf5200 }, -{"lsrl", one(0160250), one(0170770), "DdDs", m68000up | mcf5200 }, - -/* NOTE: The mcf5200 family programmer's reference manual does not - indicate the byte form of the movea instruction is invalid (as it - is on 68000 family cpus). However, experiments on the 5202 yeild - unexpected results. The value is copied, but it is not sign extended - (as is done with movea.w) and the top three bytes in the address - register are not disturbed. I don't know if this is the intended - behavior --- it could be a hole in instruction decoding (Motorola - decided not to trap all invalid instructions for performance reasons) - --- but I suspect that it is not. - - I reported this to Motorola ISD Technical Communications Support, - which replied that other coldfire assemblers reject movea.b. For - this reason I've decided to not allow moveab. - - jtc@cygnus.com - 97/01/24 - */ - -{"moveal", one(0020100), one(0170700), "*lAd", m68000up | mcf5200 }, -{"moveaw", one(0030100), one(0170700), "*wAd", m68000up | mcf5200 }, - -{"movec", one(0047173), one(0177777), "R1Jj", m68010up | mcf5200 }, -{"movec", one(0047173), one(0177777), "R1#j", m68010up | mcf5200 }, -{"movec", one(0047172), one(0177777), "JjR1", m68010up }, -{"movec", one(0047172), one(0177777), "#jR1", m68010up }, - -{"movemw", one(0044200), one(0177700), "Lw&s", m68000up }, -{"movemw", one(0044240), one(0177770), "lw-s", m68000up }, -{"movemw", one(0044200), one(0177700), "#w>s", m68000up }, -{"movemw", one(0046200), one(0177700), "<sLw", m68000up }, -{"movemw", one(0046200), one(0177700), "<s#w", m68000up }, -{"moveml", one(0044300), one(0177700), "Lw&s", m68000up }, -{"moveml", one(0044340), one(0177770), "lw-s", m68000up }, -{"moveml", one(0044300), one(0177700), "#w>s", m68000up }, -{"moveml", one(0046300), one(0177700), "<sLw", m68000up }, -{"moveml", one(0046300), one(0177700), "<s#w", m68000up }, -/* FIXME: need specifier for mode 2 and 5 to simplify below insn patterns */ -{"moveml", one(0044320), one(0177770), "Lwas", mcf5200 }, -{"moveml", one(0044320), one(0177770), "#was", mcf5200 }, -{"moveml", one(0044350), one(0177770), "Lwds", mcf5200 }, -{"moveml", one(0044350), one(0177770), "#wds", mcf5200 }, -{"moveml", one(0046320), one(0177770), "asLw", mcf5200 }, -{"moveml", one(0046320), one(0177770), "as#w", mcf5200 }, -{"moveml", one(0046350), one(0177770), "dsLw", mcf5200 }, -{"moveml", one(0046350), one(0177770), "ds#w", mcf5200 }, - -{"movepw", one(0000410), one(0170770), "dsDd", m68000up }, -{"movepw", one(0000610), one(0170770), "Ddds", m68000up }, -{"movepl", one(0000510), one(0170770), "dsDd", m68000up }, -{"movepl", one(0000710), one(0170770), "Ddds", m68000up }, - -{"moveq", one(0070000), one(0170400), "MsDd", m68000up | mcf5200 }, -{"moveq", one(0070000), one(0170400), "#BDd", m68000up | mcf5200 }, - -/* The move opcode can generate the movea and moveq instructions. */ -{"moveb", one(0010000), one(0170000), ";b$d", m68000up }, -{"moveb", one(0010000), one(0170000), "ms%d", mcf5200 }, -{"moveb", one(0010000), one(0170000), "nspd", mcf5200 }, -{"moveb", one(0010000), one(0170000), "obmd", mcf5200 }, - -{"movew", one(0030000), one(0170000), "*w%d", m68000up }, -{"movew", one(0030000), one(0170000), "ms%d", mcf5200 }, -{"movew", one(0030000), one(0170000), "nspd", mcf5200 }, -{"movew", one(0030000), one(0170000), "owmd", mcf5200 }, -{"movew", one(0040300), one(0177700), "Ss$s", m68000up }, -{"movew", one(0040300), one(0177770), "SsDs", mcf5200 }, -{"movew", one(0041300), one(0177700), "Cs$s", m68010up }, -{"movew", one(0041300), one(0177770), "CsDs", mcf5200 }, -{"movew", one(0042300), one(0177700), ";wCd", m68000up }, -{"movew", one(0042300), one(0177700), "DsCd", mcf5200 }, -{"movew", one(0042374), one(0177700), "#wCd", mcf5200 }, -{"movew", one(0043300), one(0177700), ";wSd", m68000up }, -{"movew", one(0043300), one(0177700), "DsSd", mcf5200 }, -{"movew", one(0043374), one(0177700), "#wSd", mcf5200 }, - -{"movel", one(0070000), one(0170400), "MsDd", m68000up | mcf5200 }, -{"movel", one(0020000), one(0170000), "*l%d", m68000up }, -{"movel", one(0020000), one(0170000), "ms%d", mcf5200 }, -{"movel", one(0020000), one(0170000), "nspd", mcf5200 }, -{"movel", one(0020000), one(0170000), "olmd", mcf5200 }, -{"movel", one(0047140), one(0177770), "AsUd", m68000up }, -{"movel", one(0047150), one(0177770), "UdAs", m68000up }, - -{"move", one(0030000), one(0170000), "*w%d", m68000up }, -{"move", one(0030000), one(0170000), "ms%d", mcf5200 }, -{"move", one(0030000), one(0170000), "nspd", mcf5200 }, -{"move", one(0030000), one(0170000), "owmd", mcf5200 }, -{"move", one(0040300), one(0177700), "Ss$s", m68000up }, -{"move", one(0040300), one(0177770), "SsDs", mcf5200 }, -{"move", one(0041300), one(0177700), "Cs$s", m68010up }, -{"move", one(0041300), one(0177770), "CsDs", mcf5200 }, -{"move", one(0042300), one(0177700), ";wCd", m68000up }, -{"move", one(0042300), one(0177700), "DsCd", mcf5200 }, -{"move", one(0042300), one(0177700), "#wCd", mcf5200 }, -{"move", one(0043300), one(0177700), ";wSd", m68000up }, -{"move", one(0043300), one(0177700), "DsSd", mcf5200 }, -{"move", one(0043300), one(0177700), "#wSd", mcf5200 }, - -{"move", one(0047140), one(0177770), "AsUd", m68000up }, -{"move", one(0047150), one(0177770), "UdAs", m68000up }, - -{"movesb", two(0007000, 0), two(0177700, 07777), "~sR1", m68010up }, -{"movesb", two(0007000, 04000), two(0177700, 07777), "R1~s", m68010up }, -{"movesw", two(0007100, 0), two(0177700, 07777), "~sR1", m68010up }, -{"movesw", two(0007100, 04000), two(0177700, 07777), "R1~s", m68010up }, -{"movesl", two(0007200, 0), two(0177700, 07777), "~sR1", m68010up }, -{"movesl", two(0007200, 04000), two(0177700, 07777), "R1~s", m68010up }, - -{"move16", two(0xf620, 0x8000), two(0xfff8, 0x8fff), "+s+1", m68040up }, -{"move16", one(0xf600), one(0xfff8), "+s_L", m68040up }, -{"move16", one(0xf608), one(0xfff8), "_L+s", m68040up }, -{"move16", one(0xf610), one(0xfff8), "as_L", m68040up }, -{"move16", one(0xf618), one(0xfff8), "_Las", m68040up }, - -{"mulsw", one(0140700), one(0170700), ";wDd", m68000up|mcf5200 }, -{"mulsl", two(0046000,004000), two(0177700,0107770), ";lD1", m68020up|cpu32 }, -{"mulsl", two(0046000,004000), two(0177700,0107770), "DsD1", mcf5200 }, -{"mulsl", two(0046000,004000), two(0177700,0107770), "asD1", mcf5200 }, -{"mulsl", two(0046000,004000), two(0177700,0107770), "+sD1", mcf5200 }, -{"mulsl", two(0046000,004000), two(0177700,0107770), "-sD1", mcf5200 }, -{"mulsl", two(0046000,004000), two(0177700,0107770), "dsD1", mcf5200 }, -{"mulsl", two(0046000,006000), two(0177700,0107770), ";lD3D1",m68020up|cpu32 }, - -{"muluw", one(0140300), one(0170700), ";wDd", m68000up|mcf5200 }, -{"mulul", two(0046000,000000), two(0177700,0107770), ";lD1", m68020up|cpu32 }, -{"mulul", two(0046000,000000), two(0177700,0107770), "DsD1", mcf5200 }, -{"mulul", two(0046000,000000), two(0177700,0107770), "asD1", mcf5200 }, -{"mulul", two(0046000,000000), two(0177700,0107770), "+sD1", mcf5200 }, -{"mulul", two(0046000,000000), two(0177700,0107770), "-sD1", mcf5200 }, -{"mulul", two(0046000,000000), two(0177700,0107770), "dsD1", mcf5200 }, -{"mulul", two(0046000,002000), two(0177700,0107770), ";lD3D1",m68020up|cpu32 }, - -{"nbcd", one(0044000), one(0177700), "$s", m68000up }, - -{"negb", one(0042000), one(0177700), "$s", m68000up }, -{"negw", one(0042100), one(0177700), "$s", m68000up }, -{"negl", one(0042200), one(0177700), "$s", m68000up }, -{"negl", one(0042200), one(0177700), "Ds", mcf5200}, - -{"negxb", one(0040000), one(0177700), "$s", m68000up }, -{"negxw", one(0040100), one(0177700), "$s", m68000up }, -{"negxl", one(0040200), one(0177700), "$s", m68000up }, -{"negxl", one(0040200), one(0177700), "Ds", mcf5200}, - -{"nop", one(0047161), one(0177777), "", m68000up | mcf5200}, - -{"notb", one(0043000), one(0177700), "$s", m68000up }, -{"notw", one(0043100), one(0177700), "$s", m68000up }, -{"notl", one(0043200), one(0177700), "$s", m68000up }, -{"notl", one(0043200), one(0177700), "Ds", mcf5200}, - -{"orib", one(0000000), one(0177700), "#b$s", m68000up }, -{"orib", one(0000074), one(0177777), "#bCs", m68000up }, -{"oriw", one(0000100), one(0177700), "#w$s", m68000up }, -{"oriw", one(0000174), one(0177777), "#wSs", m68000up }, -{"oril", one(0000200), one(0177700), "#l$s", m68000up }, -{"oril", one(0000200), one(0177700), "#lDs", mcf5200 }, -{"ori", one(0000074), one(0177777), "#bCs", m68000up }, -{"ori", one(0000100), one(0177700), "#w$s", m68000up }, -{"ori", one(0000174), one(0177777), "#wSs", m68000up }, - -/* The or opcode can generate the ori instruction. */ -{"orb", one(0000000), one(0177700), "#b$s", m68000up }, -{"orb", one(0000074), one(0177777), "#bCs", m68000up }, -{"orb", one(0100000), one(0170700), ";bDd", m68000up }, -{"orb", one(0100400), one(0170700), "Dd~s", m68000up }, -{"orw", one(0000100), one(0177700), "#w$s", m68000up }, -{"orw", one(0000174), one(0177777), "#wSs", m68000up }, -{"orw", one(0100100), one(0170700), ";wDd", m68000up }, -{"orw", one(0100500), one(0170700), "Dd~s", m68000up }, -{"orl", one(0000200), one(0177700), "#l$s", m68000up }, -{"orl", one(0000200), one(0177700), "#lDs", mcf5200 }, -{"orl", one(0100200), one(0170700), ";lDd", m68000up | mcf5200 }, -{"orl", one(0100600), one(0170700), "Dd~s", m68000up | mcf5200 }, -{"or", one(0000074), one(0177777), "#bCs", m68000up }, -{"or", one(0000100), one(0177700), "#w$s", m68000up }, -{"or", one(0000174), one(0177777), "#wSs", m68000up }, -{"or", one(0100100), one(0170700), ";wDd", m68000up }, -{"or", one(0100500), one(0170700), "Dd~s", m68000up }, - -{"pack", one(0100500), one(0170770), "DsDd#w", m68020up }, -{"pack", one(0100510), one(0170770), "-s-d#w", m68020up }, - -{"pbac", one(0xf087), one(0xffbf), "Bc", m68851 }, -{"pbacw", one(0xf087), one(0xffff), "BW", m68851 }, -{"pbas", one(0xf086), one(0xffbf), "Bc", m68851 }, -{"pbasw", one(0xf086), one(0xffff), "BW", m68851 }, -{"pbbc", one(0xf081), one(0xffbf), "Bc", m68851 }, -{"pbbcw", one(0xf081), one(0xffff), "BW", m68851 }, -{"pbbs", one(0xf080), one(0xffbf), "Bc", m68851 }, -{"pbbsw", one(0xf080), one(0xffff), "BW", m68851 }, -{"pbcc", one(0xf08f), one(0xffbf), "Bc", m68851 }, -{"pbccw", one(0xf08f), one(0xffff), "BW", m68851 }, -{"pbcs", one(0xf08e), one(0xffbf), "Bc", m68851 }, -{"pbcsw", one(0xf08e), one(0xffff), "BW", m68851 }, -{"pbgc", one(0xf08d), one(0xffbf), "Bc", m68851 }, -{"pbgcw", one(0xf08d), one(0xffff), "BW", m68851 }, -{"pbgs", one(0xf08c), one(0xffbf), "Bc", m68851 }, -{"pbgsw", one(0xf08c), one(0xffff), "BW", m68851 }, -{"pbic", one(0xf08b), one(0xffbf), "Bc", m68851 }, -{"pbicw", one(0xf08b), one(0xffff), "BW", m68851 }, -{"pbis", one(0xf08a), one(0xffbf), "Bc", m68851 }, -{"pbisw", one(0xf08a), one(0xffff), "BW", m68851 }, -{"pblc", one(0xf083), one(0xffbf), "Bc", m68851 }, -{"pblcw", one(0xf083), one(0xffff), "BW", m68851 }, -{"pbls", one(0xf082), one(0xffbf), "Bc", m68851 }, -{"pblsw", one(0xf082), one(0xffff), "BW", m68851 }, -{"pbsc", one(0xf085), one(0xffbf), "Bc", m68851 }, -{"pbscw", one(0xf085), one(0xffff), "BW", m68851 }, -{"pbss", one(0xf084), one(0xffbf), "Bc", m68851 }, -{"pbssw", one(0xf084), one(0xffff), "BW", m68851 }, -{"pbwc", one(0xf089), one(0xffbf), "Bc", m68851 }, -{"pbwcw", one(0xf089), one(0xffff), "BW", m68851 }, -{"pbws", one(0xf088), one(0xffbf), "Bc", m68851 }, -{"pbwsw", one(0xf088), one(0xffff), "BW", m68851 }, - -{"pdbac", two(0xf048, 0x0007), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbas", two(0xf048, 0x0006), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbbc", two(0xf048, 0x0001), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbbs", two(0xf048, 0x0000), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbcc", two(0xf048, 0x000f), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbcs", two(0xf048, 0x000e), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbgc", two(0xf048, 0x000d), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbgs", two(0xf048, 0x000c), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbic", two(0xf048, 0x000b), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbis", two(0xf048, 0x000a), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdblc", two(0xf048, 0x0003), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbls", two(0xf048, 0x0002), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbsc", two(0xf048, 0x0005), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbss", two(0xf048, 0x0004), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbwc", two(0xf048, 0x0009), two(0xfff8, 0xffff), "DsBw", m68851 }, -{"pdbws", two(0xf048, 0x0008), two(0xfff8, 0xffff), "DsBw", m68851 }, - -{"pea", one(0044100), one(0177700), "!s", m68000up|mcf5200 }, - -{"pflusha", one(0xf518), one(0xfff8), "", m68040up }, -{"pflusha", two(0xf000,0x2400), two(0xffff,0xffff), "", m68030 | m68851 }, - -{"pflush", two(0xf000,0x3010), two(0xffc0,0xfe10), "T3T9", m68030|m68851 }, -{"pflush", two(0xf000,0x3810), two(0xffc0,0xfe10), "T3T9&s", m68030|m68851 }, -{"pflush", two(0xf000,0x3008), two(0xffc0,0xfe18), "D3T9", m68030|m68851 }, -{"pflush", two(0xf000,0x3808), two(0xffc0,0xfe18), "D3T9&s", m68030|m68851 }, -{"pflush", two(0xf000,0x3000), two(0xffc0,0xfe1e), "f3T9", m68030|m68851 }, -{"pflush", two(0xf000,0x3800), two(0xffc0,0xfe1e), "f3T9&s", m68030|m68851 }, -{"pflush", one(0xf508), one(0xfff8), "as", m68040up }, -{"pflush", one(0xf508), one(0xfff8), "As", m68040up }, - -{"pflushan", one(0xf510), one(0xfff8), "", m68040up }, -{"pflushn", one(0xf500), one(0xfff8), "as", m68040up }, -{"pflushn", one(0xf500), one(0xfff8), "As", m68040up }, - -{"pflushr", two(0xf000, 0xa000), two(0xffc0, 0xffff), "|s", m68851 }, - -{"pflushs", two(0xf000, 0x3410), two(0xfff8, 0xfe10), "T3T9", m68851 }, -{"pflushs", two(0xf000, 0x3c10), two(0xfff8, 0xfe10), "T3T9&s", m68851 }, -{"pflushs", two(0xf000, 0x3408), two(0xfff8, 0xfe18), "D3T9", m68851 }, -{"pflushs", two(0xf000, 0x3c08), two(0xfff8, 0xfe18), "D3T9&s", m68851 }, -{"pflushs", two(0xf000, 0x3400), two(0xfff8, 0xfe1e), "f3T9", m68851 }, -{"pflushs", two(0xf000, 0x3c00), two(0xfff8, 0xfe1e), "f3T9&s", m68851 }, - -{"ploadr", two(0xf000,0x2210), two(0xffc0,0xfff0), "T3&s", m68030|m68851 }, -{"ploadr", two(0xf000,0x2208), two(0xffc0,0xfff8), "D3&s", m68030|m68851 }, -{"ploadr", two(0xf000,0x2200), two(0xffc0,0xfffe), "f3&s", m68030|m68851 }, -{"ploadw", two(0xf000,0x2010), two(0xffc0,0xfff0), "T3&s", m68030|m68851 }, -{"ploadw", two(0xf000,0x2008), two(0xffc0,0xfff8), "D3&s", m68030|m68851 }, -{"ploadw", two(0xf000,0x2000), two(0xffc0,0xfffe), "f3&s", m68030|m68851 }, - -{"plpar", one(0xf5c8), one(0xfff8), "as", m68060 }, -{"plpaw", one(0xf588), one(0xfff8), "as", m68060 }, - -{"pmove", two(0xf000,0x4000), two(0xffc0,0xffff), "*l08", m68030|m68851 }, -{"pmove", two(0xf000,0x5c00), two(0xffc0,0xffff), "*w18", m68851 }, -{"pmove", two(0xf000,0x4000), two(0xffc0,0xe3ff), "*b28", m68851 }, -{"pmove", two(0xf000,0x4200), two(0xffc0,0xffff), "08%s", m68030|m68851 }, -{"pmove", two(0xf000,0x5e00), two(0xffc0,0xffff), "18%s", m68851 }, -{"pmove", two(0xf000,0x4200), two(0xffc0,0xe3ff), "28%s", m68851 }, -{"pmove", two(0xf000,0x4000), two(0xffc0,0xe3ff), "|sW8", m68030|m68851 }, -{"pmove", two(0xf000,0x4200), two(0xffc0,0xe3ff), "W8~s", m68030|m68851 }, -{"pmove", two(0xf000,0x6200), two(0xffc0,0xe3e3), "*wX3", m68851 }, -{"pmove", two(0xf000,0x6000), two(0xffc0,0xe3e3), "X3%s", m68851 }, -{"pmove", two(0xf000,0x6000), two(0xffc0,0xffff), "*wY8", m68030|m68851 }, -{"pmove", two(0xf000,0x6200), two(0xffc0,0xffff), "Y8%s", m68030|m68851 }, -{"pmove", two(0xf000,0x6600), two(0xffc0,0xffff), "Z8%s", m68851 }, -{"pmove", two(0xf000,0x0800), two(0xffc0,0xfbff), "*l38", m68030 }, -{"pmove", two(0xf000,0x0a00), two(0xffc0,0xfbff), "38%s", m68030 }, - -{"pmovefd", two(0xf000, 0x4100), two(0xffc0, 0xe3ff), "*l08", m68030 }, -{"pmovefd", two(0xf000, 0x4100), two(0xffc0, 0xe3ff), "|sW8", m68030 }, -{"pmovefd", two(0xf000, 0x0900), two(0xffc0, 0xfbff), "*l38", m68030 }, - -{"prestore", one(0xf140), one(0xffc0), "<s", m68851 }, - -{"psave", one(0xf100), one(0xffc0), ">s", m68851 }, - -{"psac", two(0xf040, 0x0007), two(0xffc0, 0xffff), "$s", m68851 }, -{"psas", two(0xf040, 0x0006), two(0xffc0, 0xffff), "$s", m68851 }, -{"psbc", two(0xf040, 0x0001), two(0xffc0, 0xffff), "$s", m68851 }, -{"psbs", two(0xf040, 0x0000), two(0xffc0, 0xffff), "$s", m68851 }, -{"pscc", two(0xf040, 0x000f), two(0xffc0, 0xffff), "$s", m68851 }, -{"pscs", two(0xf040, 0x000e), two(0xffc0, 0xffff), "$s", m68851 }, -{"psgc", two(0xf040, 0x000d), two(0xffc0, 0xffff), "$s", m68851 }, -{"psgs", two(0xf040, 0x000c), two(0xffc0, 0xffff), "$s", m68851 }, -{"psic", two(0xf040, 0x000b), two(0xffc0, 0xffff), "$s", m68851 }, -{"psis", two(0xf040, 0x000a), two(0xffc0, 0xffff), "$s", m68851 }, -{"pslc", two(0xf040, 0x0003), two(0xffc0, 0xffff), "$s", m68851 }, -{"psls", two(0xf040, 0x0002), two(0xffc0, 0xffff), "$s", m68851 }, -{"pssc", two(0xf040, 0x0005), two(0xffc0, 0xffff), "$s", m68851 }, -{"psss", two(0xf040, 0x0004), two(0xffc0, 0xffff), "$s", m68851 }, -{"pswc", two(0xf040, 0x0009), two(0xffc0, 0xffff), "$s", m68851 }, -{"psws", two(0xf040, 0x0008), two(0xffc0, 0xffff), "$s", m68851 }, - -{"ptestr", two(0xf000,0x8210), two(0xffc0, 0xe3f0), "T3&st8", m68030|m68851 }, -{"ptestr", two(0xf000,0x8310), two(0xffc0,0xe310), "T3&st8A9", m68030|m68851 }, -{"ptestr", two(0xf000,0x8208), two(0xffc0,0xe3f8), "D3&st8", m68030|m68851 }, -{"ptestr", two(0xf000,0x8308), two(0xffc0,0xe318), "D3&st8A9", m68030|m68851 }, -{"ptestr", two(0xf000,0x8200), two(0xffc0,0xe3fe), "f3&st8", m68030|m68851 }, -{"ptestr", two(0xf000,0x8300), two(0xffc0,0xe31e), "f3&st8A9", m68030|m68851 }, -{"ptestr", one(0xf568), one(0xfff8), "as", m68040 }, - -{"ptestw", two(0xf000,0x8010), two(0xffc0,0xe3f0), "T3&st8", m68030|m68851 }, -{"ptestw", two(0xf000,0x8110), two(0xffc0,0xe310), "T3&st8A9", m68030|m68851 }, -{"ptestw", two(0xf000,0x8008), two(0xffc0,0xe3f8), "D3&st8", m68030|m68851 }, -{"ptestw", two(0xf000,0x8108), two(0xffc0,0xe318), "D3&st8A9", m68030|m68851 }, -{"ptestw", two(0xf000,0x8000), two(0xffc0,0xe3fe), "f3&st8", m68030|m68851 }, -{"ptestw", two(0xf000,0x8100), two(0xffc0,0xe31e), "f3&st8A9", m68030|m68851 }, -{"ptestw", one(0xf548), one(0xfff8), "as", m68040 }, - -{"ptrapacw", two(0xf07a, 0x0007), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapacl", two(0xf07b, 0x0007), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapac", two(0xf07c, 0x0007), two(0xffff, 0xffff), "", m68851 }, - -{"ptrapasw", two(0xf07a, 0x0006), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapasl", two(0xf07b, 0x0006), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapas", two(0xf07c, 0x0006), two(0xffff, 0xffff), "", m68851 }, - -{"ptrapbcw", two(0xf07a, 0x0001), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapbcl", two(0xf07b, 0x0001), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapbc", two(0xf07c, 0x0001), two(0xffff, 0xffff), "", m68851 }, - -{"ptrapbsw", two(0xf07a, 0x0000), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapbsl", two(0xf07b, 0x0000), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapbs", two(0xf07c, 0x0000), two(0xffff, 0xffff), "", m68851 }, - -{"ptrapccw", two(0xf07a, 0x000f), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapccl", two(0xf07b, 0x000f), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapcc", two(0xf07c, 0x000f), two(0xffff, 0xffff), "", m68851 }, - -{"ptrapcsw", two(0xf07a, 0x000e), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapcsl", two(0xf07b, 0x000e), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapcs", two(0xf07c, 0x000e), two(0xffff, 0xffff), "", m68851 }, - -{"ptrapgcw", two(0xf07a, 0x000d), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapgcl", two(0xf07b, 0x000d), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapgc", two(0xf07c, 0x000d), two(0xffff, 0xffff), "", m68851 }, - -{"ptrapgsw", two(0xf07a, 0x000c), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapgsl", two(0xf07b, 0x000c), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapgs", two(0xf07c, 0x000c), two(0xffff, 0xffff), "", m68851 }, - -{"ptrapicw", two(0xf07a, 0x000b), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapicl", two(0xf07b, 0x000b), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapic", two(0xf07c, 0x000b), two(0xffff, 0xffff), "", m68851 }, - -{"ptrapisw", two(0xf07a, 0x000a), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapisl", two(0xf07b, 0x000a), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapis", two(0xf07c, 0x000a), two(0xffff, 0xffff), "", m68851 }, - -{"ptraplcw", two(0xf07a, 0x0003), two(0xffff, 0xffff), "#w", m68851 }, -{"ptraplcl", two(0xf07b, 0x0003), two(0xffff, 0xffff), "#l", m68851 }, -{"ptraplc", two(0xf07c, 0x0003), two(0xffff, 0xffff), "", m68851 }, - -{"ptraplsw", two(0xf07a, 0x0002), two(0xffff, 0xffff), "#w", m68851 }, -{"ptraplsl", two(0xf07b, 0x0002), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapls", two(0xf07c, 0x0002), two(0xffff, 0xffff), "", m68851 }, - -{"ptrapscw", two(0xf07a, 0x0005), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapscl", two(0xf07b, 0x0005), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapsc", two(0xf07c, 0x0005), two(0xffff, 0xffff), "", m68851 }, - -{"ptrapssw", two(0xf07a, 0x0004), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapssl", two(0xf07b, 0x0004), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapss", two(0xf07c, 0x0004), two(0xffff, 0xffff), "", m68851 }, - -{"ptrapwcw", two(0xf07a, 0x0009), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapwcl", two(0xf07b, 0x0009), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapwc", two(0xf07c, 0x0009), two(0xffff, 0xffff), "", m68851 }, - -{"ptrapwsw", two(0xf07a, 0x0008), two(0xffff, 0xffff), "#w", m68851 }, -{"ptrapwsl", two(0xf07b, 0x0008), two(0xffff, 0xffff), "#l", m68851 }, -{"ptrapws", two(0xf07c, 0x0008), two(0xffff, 0xffff), "", m68851 }, - -{"pulse", one(0045314), one(0177777), "", mcf5200 }, - -{"pvalid", two(0xf000, 0x2800), two(0xffc0, 0xffff), "Vs&s", m68851 }, -{"pvalid", two(0xf000, 0x2c00), two(0xffc0, 0xfff8), "A3&s", m68851 }, - -/* start-sanitize-coldfire */ -{"remsl", two(0046100,0006000),two(0177700,0107770),"DsD3D1", mcfdiv }, -{"remsl", two(0046100,0006000),two(0177700,0107770),"asD3D1", mcfdiv }, -{"remsl", two(0046100,0006000),two(0177700,0107770),"+sD3D1", mcfdiv }, -{"remsl", two(0046100,0006000),two(0177700,0107770),"-sD3D1", mcfdiv }, -{"remsl", two(0046100,0006000),two(0177700,0107770),"dsD3D1", mcfdiv }, - -{"remul", two(0046100,0002000),two(0177700,0107770),"DsD3D1", mcfdiv }, -{"remul", two(0046100,0002000),two(0177700,0107770),"asD3D1", mcfdiv }, -{"remul", two(0046100,0002000),two(0177700,0107770),"+sD3D1", mcfdiv }, -{"remul", two(0046100,0002000),two(0177700,0107770),"-sD3D1", mcfdiv }, -{"remul", two(0046100,0002000),two(0177700,0107770),"dsD3D1", mcfdiv }, -/* end-sanitize-coldfire */ - -{"reset", one(0047160), one(0177777), "", m68000up }, - -{"rolb", one(0160430), one(0170770), "QdDs", m68000up }, -{"rolb", one(0160470), one(0170770), "DdDs", m68000up }, -{"rolw", one(0160530), one(0170770), "QdDs", m68000up }, -{"rolw", one(0160570), one(0170770), "DdDs", m68000up }, -{"rolw", one(0163700), one(0177700), "~s", m68000up }, -{"roll", one(0160630), one(0170770), "QdDs", m68000up }, -{"roll", one(0160670), one(0170770), "DdDs", m68000up }, - -{"rorb", one(0160030), one(0170770), "QdDs", m68000up }, -{"rorb", one(0160070), one(0170770), "DdDs", m68000up }, -{"rorw", one(0160130), one(0170770), "QdDs", m68000up }, -{"rorw", one(0160170), one(0170770), "DdDs", m68000up }, -{"rorw", one(0163300), one(0177700), "~s", m68000up }, -{"rorl", one(0160230), one(0170770), "QdDs", m68000up }, -{"rorl", one(0160270), one(0170770), "DdDs", m68000up }, - -{"roxlb", one(0160420), one(0170770), "QdDs", m68000up }, -{"roxlb", one(0160460), one(0170770), "DdDs", m68000up }, -{"roxlw", one(0160520), one(0170770), "QdDs", m68000up }, -{"roxlw", one(0160560), one(0170770), "DdDs", m68000up }, -{"roxlw", one(0162700), one(0177700), "~s", m68000up }, -{"roxll", one(0160620), one(0170770), "QdDs", m68000up }, -{"roxll", one(0160660), one(0170770), "DdDs", m68000up }, - -{"roxrb", one(0160020), one(0170770), "QdDs", m68000up }, -{"roxrb", one(0160060), one(0170770), "DdDs", m68000up }, -{"roxrw", one(0160120), one(0170770), "QdDs", m68000up }, -{"roxrw", one(0160160), one(0170770), "DdDs", m68000up }, -{"roxrw", one(0162300), one(0177700), "~s", m68000up }, -{"roxrl", one(0160220), one(0170770), "QdDs", m68000up }, -{"roxrl", one(0160260), one(0170770), "DdDs", m68000up }, - -{"rtd", one(0047164), one(0177777), "#w", m68010up }, - -{"rte", one(0047163), one(0177777), "", m68000up|mcf5200 }, - -{"rtm", one(0003300), one(0177760), "Rs", m68020 }, - -{"rtr", one(0047167), one(0177777), "", m68000up }, - -{"rts", one(0047165), one(0177777), "", m68000up|mcf5200 }, - -{"sbcd", one(0100400), one(0170770), "DsDd", m68000up }, -{"sbcd", one(0100410), one(0170770), "-s-d", m68000up }, - - -{"scc", one(0052300), one(0177700), "$s", m68000up }, -{"scc", one(0052300), one(0177700), "Ds", mcf5200 }, -{"scs", one(0052700), one(0177700), "$s", m68000up }, -{"scs", one(0052700), one(0177700), "Ds", mcf5200 }, -{"seq", one(0053700), one(0177700), "$s", m68000up }, -{"seq", one(0053700), one(0177700), "Ds", mcf5200 }, -{"sf", one(0050700), one(0177700), "$s", m68000up }, -{"sf", one(0050700), one(0177700), "Ds", mcf5200 }, -{"sge", one(0056300), one(0177700), "$s", m68000up }, -{"sge", one(0056300), one(0177700), "Ds", mcf5200 }, -{"sgt", one(0057300), one(0177700), "$s", m68000up }, -{"sgt", one(0057300), one(0177700), "Ds", mcf5200 }, -{"shi", one(0051300), one(0177700), "$s", m68000up }, -{"shi", one(0051300), one(0177700), "Ds", mcf5200 }, -{"sle", one(0057700), one(0177700), "$s", m68000up }, -{"sle", one(0057700), one(0177700), "Ds", mcf5200 }, -{"sls", one(0051700), one(0177700), "$s", m68000up }, -{"sls", one(0051700), one(0177700), "Ds", mcf5200 }, -{"slt", one(0056700), one(0177700), "$s", m68000up }, -{"slt", one(0056700), one(0177700), "Ds", mcf5200 }, -{"smi", one(0055700), one(0177700), "$s", m68000up }, -{"smi", one(0055700), one(0177700), "Ds", mcf5200 }, -{"sne", one(0053300), one(0177700), "$s", m68000up }, -{"sne", one(0053300), one(0177700), "Ds", mcf5200 }, -{"spl", one(0055300), one(0177700), "$s", m68000up }, -{"spl", one(0055300), one(0177700), "Ds", mcf5200 }, -{"st", one(0050300), one(0177700), "$s", m68000up }, -{"st", one(0050300), one(0177700), "Ds", mcf5200 }, -{"svc", one(0054300), one(0177700), "$s", m68000up }, -{"svc", one(0054300), one(0177700), "Ds", mcf5200 }, -{"svs", one(0054700), one(0177700), "$s", m68000up }, -{"svs", one(0054700), one(0177700), "Ds", mcf5200 }, - -{"stop", one(0047162), one(0177777), "#w", m68000up | mcf5200 }, - -{"subal", one(0110700), one(0170700), "*lAd", m68000up | mcf5200 }, -{"subaw", one(0110300), one(0170700), "*wAd", m68000up }, - -{"subib", one(0002000), one(0177700), "#b$s", m68000up }, -{"subiw", one(0002100), one(0177700), "#w$s", m68000up }, -{"subil", one(0002200), one(0177700), "#l$s", m68000up }, -{"subil", one(0002200), one(0177700), "#lDs", mcf5200 }, - -{"subqb", one(0050400), one(0170700), "Qd%s", m68000up }, -{"subqw", one(0050500), one(0170700), "Qd%s", m68000up }, -{"subql", one(0050600), one(0170700), "Qd%s", m68000up | mcf5200 }, - -/* The sub opcode can generate the suba, subi, and subq instructions. */ -{"subb", one(0050400), one(0170700), "Qd%s", m68000up }, -{"subb", one(0002000), one(0177700), "#b$s", m68000up }, -{"subb", one(0110000), one(0170700), ";bDd", m68000up }, -{"subb", one(0110400), one(0170700), "Dd~s", m68000up }, -{"subw", one(0050500), one(0170700), "Qd%s", m68000up }, -{"subw", one(0002100), one(0177700), "#w$s", m68000up }, -{"subw", one(0110300), one(0170700), "*wAd", m68000up }, -{"subw", one(0110100), one(0170700), "*wDd", m68000up }, -{"subw", one(0110500), one(0170700), "Dd~s", m68000up }, -{"subl", one(0050600), one(0170700), "Qd%s", m68000up | mcf5200 }, -{"subl", one(0002200), one(0177700), "#l$s", m68000up }, -{"subl", one(0002200), one(0177700), "#lDs", mcf5200 }, -{"subl", one(0110700), one(0170700), "*lAd", m68000up | mcf5200 }, -{"subl", one(0110200), one(0170700), "*lDd", m68000up | mcf5200 }, -{"subl", one(0110600), one(0170700), "Dd~s", m68000up | mcf5200 }, - -{"subxb", one(0110400), one(0170770), "DsDd", m68000up }, -{"subxb", one(0110410), one(0170770), "-s-d", m68000up }, -{"subxw", one(0110500), one(0170770), "DsDd", m68000up }, -{"subxw", one(0110510), one(0170770), "-s-d", m68000up }, -{"subxl", one(0110600), one(0170770), "DsDd", m68000up | mcf5200 }, -{"subxl", one(0110610), one(0170770), "-s-d", m68000up }, - -{"swap", one(0044100), one(0177770), "Ds", m68000up | mcf5200 }, - -/* swbeg and swbegl are magic constants used on sysV68. The compiler - generates them before a switch table. They tell the debugger and - disassembler that a switch table follows. The parameter is the - number of elements in the table. swbeg means that the entries in - the table are word (2 byte) sized, and swbegl means that the - entries in the table are longword (4 byte) sized. */ -{"swbeg", one(0045374), one(0177777), "#w", m68000up | mcf5200 }, -{"swbegl", one(0045375), one(0177777), "#l", m68000up | mcf5200 }, - -{"tas", one(0045300), one(0177700), "$s", m68000up }, - -#define TBL1(name,signed,round,size) \ - {name, two(0174000, (signed<<11)|(!round<<10)|(size<<6)|0000400), \ - two(0177700,0107777), "!sD1", cpu32 }, \ - {name, two(0174000, (signed<<11)|(!round<<10)|(size<<6)), \ - two(0177770,0107770), "DsD3D1", cpu32 } -#define TBL(name1, name2, name3, s, r) \ - TBL1(name1, s, r, 0), TBL1(name2, s, r, 1), TBL1(name3, s, r, 2) -TBL("tblsb", "tblsw", "tblsl", 1, 1), -TBL("tblsnb", "tblsnw", "tblsnl", 1, 0), -TBL("tblub", "tbluw", "tblul", 0, 1), -TBL("tblunb", "tblunw", "tblunl", 0, 0), - -{"trap", one(0047100), one(0177760), "Ts", m68000up | mcf5200 }, - -{"trapcc", one(0052374), one(0177777), "", m68020up | cpu32 }, -{"trapcs", one(0052774), one(0177777), "", m68020up | cpu32 }, -{"trapeq", one(0053774), one(0177777), "", m68020up | cpu32 }, -{"trapf", one(0050774), one(0177777), "", m68020up | cpu32 | mcf5200 }, -{"trapge", one(0056374), one(0177777), "", m68020up | cpu32 }, -{"trapgt", one(0057374), one(0177777), "", m68020up | cpu32 }, -{"traphi", one(0051374), one(0177777), "", m68020up | cpu32 }, -{"traple", one(0057774), one(0177777), "", m68020up | cpu32 }, -{"trapls", one(0051774), one(0177777), "", m68020up | cpu32 }, -{"traplt", one(0056774), one(0177777), "", m68020up | cpu32 }, -{"trapmi", one(0055774), one(0177777), "", m68020up | cpu32 }, -{"trapne", one(0053374), one(0177777), "", m68020up | cpu32 }, -{"trappl", one(0055374), one(0177777), "", m68020up | cpu32 }, -{"trapt", one(0050374), one(0177777), "", m68020up | cpu32 }, -{"trapvc", one(0054374), one(0177777), "", m68020up | cpu32 }, -{"trapvs", one(0054774), one(0177777), "", m68020up | cpu32 }, - -{"trapccw", one(0052372), one(0177777), "#w", m68020up|cpu32 }, -{"trapcsw", one(0052772), one(0177777), "#w", m68020up|cpu32 }, -{"trapeqw", one(0053772), one(0177777), "#w", m68020up|cpu32 }, -{"trapfw", one(0050772), one(0177777), "#w", m68020up|cpu32|mcf5200}, -{"trapgew", one(0056372), one(0177777), "#w", m68020up|cpu32 }, -{"trapgtw", one(0057372), one(0177777), "#w", m68020up|cpu32 }, -{"traphiw", one(0051372), one(0177777), "#w", m68020up|cpu32 }, -{"traplew", one(0057772), one(0177777), "#w", m68020up|cpu32 }, -{"traplsw", one(0051772), one(0177777), "#w", m68020up|cpu32 }, -{"trapltw", one(0056772), one(0177777), "#w", m68020up|cpu32 }, -{"trapmiw", one(0055772), one(0177777), "#w", m68020up|cpu32 }, -{"trapnew", one(0053372), one(0177777), "#w", m68020up|cpu32 }, -{"trapplw", one(0055372), one(0177777), "#w", m68020up|cpu32 }, -{"traptw", one(0050372), one(0177777), "#w", m68020up|cpu32 }, -{"trapvcw", one(0054372), one(0177777), "#w", m68020up|cpu32 }, -{"trapvsw", one(0054772), one(0177777), "#w", m68020up|cpu32 }, - -{"trapccl", one(0052373), one(0177777), "#l", m68020up|cpu32 }, -{"trapcsl", one(0052773), one(0177777), "#l", m68020up|cpu32 }, -{"trapeql", one(0053773), one(0177777), "#l", m68020up|cpu32 }, -{"trapfl", one(0050773), one(0177777), "#l", m68020up|cpu32|mcf5200}, -{"trapgel", one(0056373), one(0177777), "#l", m68020up|cpu32 }, -{"trapgtl", one(0057373), one(0177777), "#l", m68020up|cpu32 }, -{"traphil", one(0051373), one(0177777), "#l", m68020up|cpu32 }, -{"traplel", one(0057773), one(0177777), "#l", m68020up|cpu32 }, -{"traplsl", one(0051773), one(0177777), "#l", m68020up|cpu32 }, -{"trapltl", one(0056773), one(0177777), "#l", m68020up|cpu32 }, -{"trapmil", one(0055773), one(0177777), "#l", m68020up|cpu32 }, -{"trapnel", one(0053373), one(0177777), "#l", m68020up|cpu32 }, -{"trappll", one(0055373), one(0177777), "#l", m68020up|cpu32 }, -{"traptl", one(0050373), one(0177777), "#l", m68020up|cpu32 }, -{"trapvcl", one(0054373), one(0177777), "#l", m68020up|cpu32 }, -{"trapvsl", one(0054773), one(0177777), "#l", m68020up|cpu32 }, - -{"trapv", one(0047166), one(0177777), "", m68000up }, - -{"tstb", one(0045000), one(0177700), ";b", m68020up|cpu32|mcf5200 }, -{"tstb", one(0045000), one(0177700), "@b", m68000up }, -{"tstw", one(0045100), one(0177700), "*w", m68020up|cpu32|mcf5200 }, -{"tstw", one(0045100), one(0177700), "@w", m68000up }, -{"tstl", one(0045200), one(0177700), "*l", m68020up|cpu32|mcf5200 }, -{"tstl", one(0045200), one(0177700), "@l", m68000up }, - -{"unlk", one(0047130), one(0177770), "As", m68000up | mcf5200 }, - -{"unpk", one(0100600), one(0170770), "DsDd#w", m68020up }, -{"unpk", one(0100610), one(0170770), "-s-d#w", m68020up }, - -{"wddatab", one(0172000), one(0177700), "~s", mcf5200 }, -{"wddataw", one(0172100), one(0177700), "~s", mcf5200 }, -{"wddatal", one(0172200), one(0177700), "~s", mcf5200 }, - -}; - -const int m68k_numopcodes = sizeof m68k_opcodes / sizeof m68k_opcodes[0]; - -/* These aliases used to be in the above table, each one duplicating - all of the entries for its primary exactly. This table was - constructed by mechanical processing of the opcode table, with a - small number of tweaks done by hand. There are probably a lot more - aliases above that could be moved down here, except for very minor - differences. */ - -const struct m68k_opcode_alias m68k_opcode_aliases[] = -{ - { "add", "addw", }, - { "adda", "addaw", }, - { "addi", "addiw", }, - { "addq", "addqw", }, - { "addx", "addxw", }, - { "asl", "aslw", }, - { "asr", "asrw", }, - { "bhi", "bhiw", }, - { "bls", "blsw", }, - { "bcc", "bccw", }, - { "bcs", "bcsw", }, - { "bne", "bnew", }, - { "beq", "beqw", }, - { "bvc", "bvcw", }, - { "bvs", "bvsw", }, - { "bpl", "bplw", }, - { "bmi", "bmiw", }, - { "bge", "bgew", }, - { "blt", "bltw", }, - { "bgt", "bgtw", }, - { "ble", "blew", }, - { "bra", "braw", }, - { "bsr", "bsrw", }, - { "bhib", "bhis", }, - { "blsb", "blss", }, - { "bccb", "bccs", }, - { "bcsb", "bcss", }, - { "bneb", "bnes", }, - { "beqb", "beqs", }, - { "bvcb", "bvcs", }, - { "bvsb", "bvss", }, - { "bplb", "bpls", }, - { "bmib", "bmis", }, - { "bgeb", "bges", }, - { "bltb", "blts", }, - { "bgtb", "bgts", }, - { "bleb", "bles", }, - { "brab", "bras", }, - { "bsrb", "bsrs", }, - { "bhs", "bccw" }, - { "bhss", "bccs" }, - { "bhsb", "bccs" }, - { "bhsw", "bccw" }, - { "bhsl", "bccl" }, - { "blo", "bcsw" }, - { "blos", "bcss" }, - { "blob", "bcss" }, - { "blow", "bcsw" }, - { "blol", "bcsl" }, - { "br", "braw", }, - { "brs", "bras", }, - { "brb", "bras", }, - { "brw", "braw", }, - { "brl", "bral", }, - { "jfnlt", "bcc", }, /* apparently a sun alias */ - { "jfngt", "ble", }, /* apparently a sun alias */ - { "jfeq", "beqs", }, /* apparently a sun alias */ - { "bchgb", "bchg", }, - { "bchgl", "bchg", }, - { "bclrb", "bclr", }, - { "bclrl", "bclr", }, - { "bsetb", "bset", }, - { "bsetl", "bset", }, - { "btstb", "btst", }, - { "btstl", "btst", }, - { "cas2", "cas2w", }, - { "cas", "casw", }, - { "chk2", "chk2w", }, - { "chk", "chkw", }, - { "clr", "clrw", }, - { "cmp2", "cmp2w", }, - { "cmpa", "cmpaw", }, - { "cmpi", "cmpiw", }, - { "cmpm", "cmpmw", }, - { "cmp", "cmpw", }, - { "dbccw", "dbcc", }, - { "dbcsw", "dbcs", }, - { "dbeqw", "dbeq", }, - { "dbfw", "dbf", }, - { "dbgew", "dbge", }, - { "dbgtw", "dbgt", }, - { "dbhiw", "dbhi", }, - { "dblew", "dble", }, - { "dblsw", "dbls", }, - { "dbltw", "dblt", }, - { "dbmiw", "dbmi", }, - { "dbnew", "dbne", }, - { "dbplw", "dbpl", }, - { "dbtw", "dbt", }, - { "dbvcw", "dbvc", }, - { "dbvsw", "dbvs", }, - { "dbhs", "dbcc", }, - { "dbhsw", "dbcc", }, - { "dbra", "dbf", }, - { "dbraw", "dbf", }, - { "tdivsl", "divsl", }, - { "divs", "divsw", }, - { "divu", "divuw", }, - { "ext", "extw", }, - { "extbw", "extw", }, - { "extwl", "extl", }, - { "fbneq", "fbne", }, - { "fbsneq", "fbsne", }, - { "fdbneq", "fdbne", }, - { "fdbsneq", "fdbsne", }, - { "fmovecr", "fmovecrx", }, - { "fmovm", "fmovem", }, - { "fsneq", "fsne", }, - { "fssneq", "fssne", }, - { "ftrapneq", "ftrapne", }, - { "ftrapsneq", "ftrapsne", }, - { "fjneq", "fjne", }, - { "fjsneq", "fjsne", }, - { "jmpl", "jmp", }, - { "jmps", "jmp", }, - { "jsrl", "jsr", }, - { "jsrs", "jsr", }, - { "leal", "lea", }, - { "lsl", "lslw", }, - { "lsr", "lsrw", }, - { "movea", "moveaw", }, - { "movem", "movemw", }, - { "movml", "moveml", }, - { "movmw", "movemw", }, - { "movm", "movemw", }, - { "movep", "movepw", }, - { "movpw", "movepw", }, - { "moves", "movesw" }, - { "muls", "mulsw", }, - { "mulu", "muluw", }, - { "nbcdb", "nbcd" }, - { "neg", "negw", }, - { "negx", "negxw", }, - { "not", "notw", }, - { "peal", "pea", }, - { "rol", "rolw", }, - { "ror", "rorw", }, - { "roxl", "roxlw", }, - { "roxr", "roxrw", }, - { "sbcdb", "sbcd", }, - { "sccb", "scc", }, - { "scsb", "scs", }, - { "seqb", "seq", }, - { "sfb", "sf", }, - { "sgeb", "sge", }, - { "sgtb", "sgt", }, - { "shib", "shi", }, - { "sleb", "sle", }, - { "slsb", "sls", }, - { "sltb", "slt", }, - { "smib", "smi", }, - { "sneb", "sne", }, - { "splb", "spl", }, - { "stb", "st", }, - { "svcb", "svc", }, - { "svsb", "svs", }, - { "sfge", "sge", }, - { "sfgt", "sgt", }, - { "sfle", "sle", }, - { "sflt", "slt", }, - { "sfneq", "sne", }, - { "suba", "subaw", }, - { "subi", "subiw", }, - { "subq", "subqw", }, - { "sub", "subw", }, - { "subx", "subxw", }, - { "swapw", "swap", }, - { "tasb", "tas", }, - { "tpcc", "trapcc", }, - { "tcc", "trapcc", }, - { "tst", "tstw", }, - { "jbra", "jra", }, - { "jbhi", "jhi", }, - { "jbls", "jls", }, - { "jbcc", "jcc", }, - { "jbcs", "jcs", }, - { "jbne", "jne", }, - { "jbeq", "jeq", }, - { "jbvc", "jvc", }, - { "jbvs", "jvs", }, - { "jbpl", "jpl", }, - { "jbmi", "jmi", }, - { "jbge", "jge", }, - { "jblt", "jlt", }, - { "jbgt", "jgt", }, - { "jble", "jle", }, - { "movql", "moveq", }, - { "moveql", "moveq", }, - { "movl", "movel", }, - { "movq", "moveq", }, - { "moval", "moveal", }, - { "movaw", "moveaw", }, - { "movb", "moveb", }, - { "movc", "movec", }, - { "movecl", "movec", }, - { "movpl", "movepl", }, - { "movw", "movew", }, - { "movsb", "movesb", }, - { "movsl", "movesl", }, - { "movsw", "movesw", }, - - { "tdivul", "divul", }, /* for m68k-svr4 */ - { "fmovb", "fmoveb", }, - { "fsmovb", "fsmoveb", }, - { "fdmovb", "fdmoveb", }, - { "fmovd", "fmoved", }, - { "fsmovd", "fsmoved", }, - { "fmovl", "fmovel", }, - { "fsmovl", "fsmovel", }, - { "fdmovl", "fdmovel", }, - { "fmovp", "fmovep", }, - { "fsmovp", "fsmovep", }, - { "fdmovp", "fdmovep", }, - { "fmovs", "fmoves", }, - { "fsmovs", "fsmoves", }, - { "fdmovs", "fdmoves", }, - { "fmovw", "fmovew", }, - { "fsmovw", "fsmovew", }, - { "fdmovw", "fdmovew", }, - { "fmovx", "fmovex", }, - { "fsmovx", "fsmovex", }, - { "fdmovx", "fdmovex", }, - { "fmovcr", "fmovecr", }, - { "fmovcrx", "fmovecrx", }, - { "ftestb", "ftstb", }, - { "ftestd", "ftstd", }, - { "ftestl", "ftstl", }, - { "ftestp", "ftstp", }, - { "ftests", "ftsts", }, - { "ftestw", "ftstw", }, - { "ftestx", "ftstx", }, -}; - -const int m68k_numaliases = - sizeof m68k_opcode_aliases / sizeof m68k_opcode_aliases[0]; diff --git a/opcodes/m88k-dis.c b/opcodes/m88k-dis.c deleted file mode 100644 index fec9559a366..00000000000 --- a/opcodes/m88k-dis.c +++ /dev/null @@ -1,321 +0,0 @@ -/* Print instructions for the Motorola 88000, for GDB and GNU Binutils. - Copyright 1986, 1987, 1988, 1989, 1990, 1991, 1993 - Free Software Foundation, Inc. - Contributed by Data General Corporation, November 1989. - Partially derived from an earlier printcmd.c. - -This file is part of GDB and the GNU Binutils. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ - -#include "dis-asm.h" -#include "opcode/m88k.h" - -/* FIXME: Uses the internal bfd swapping routines. */ -#include "libbfd.h" - -INSTAB *hashtable[HASHVAL] = {0}; - -static int -m88kdis PARAMS ((bfd_vma, unsigned long, struct disassemble_info *)); - -static void -printop PARAMS ((struct disassemble_info *, OPSPEC *, - unsigned long, bfd_vma, int)); - -static void -init_disasm PARAMS ((void)); - -static void -install PARAMS ((INSTAB *instptr)); - -/* -* Disassemble an M88000 Instruction -* -* -* This module decodes the instruction at memaddr. -* -* Revision History -* -* Revision 1.0 11/08/85 Creation date by Motorola -* 05/11/89 R. Trawick adapted to GDB interface. -* 07/12/93 Ian Lance Taylor updated to -* binutils interface. -*/ - -int -print_insn_m88k (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - bfd_byte buffer[4]; - int status; - - /* Instruction addresses may have low two bits set. Clear them. */ - memaddr &=~ (bfd_vma) 3; - - status = (*info->read_memory_func) (memaddr, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - - return m88kdis (memaddr, _do_getb32 (buffer), info); -} - -/* - * disassemble the instruction in 'instruction'. - * 'pc' should be the address of this instruction, it will - * be used to print the target address if this is a relative jump or call - * the disassembled instruction is written to 'info'. - * The function returns the length of this instruction in bytes. - */ - -static int -m88kdis (pc, instruction, info) - bfd_vma pc; - unsigned long instruction; - struct disassemble_info *info; -{ - static int ihashtab_initialized = 0; - unsigned int opcode; - INSTAB *entry_ptr; - int opmask; - int class; - - if (! ihashtab_initialized) - init_disasm (); - - /* create a the appropriate mask to isolate the opcode */ - opmask = DEFMASK; - class = instruction & DEFMASK; - if ((class >= SFU0) && (class <= SFU7)) - { - if (instruction < SFU1) - opmask = CTRLMASK; - else - opmask = SFUMASK; - } - else if (class == RRR) - opmask = RRRMASK; - else if (class == RRI10) - opmask = RRI10MASK; - - /* isolate the opcode */ - opcode = instruction & opmask; - - /* search the hash table with the isolated opcode */ - for (entry_ptr = hashtable[opcode % HASHVAL]; - (entry_ptr != NULL) && (entry_ptr->opcode != opcode); - entry_ptr = entry_ptr->next) - ; - - if (entry_ptr == NULL) - (*info->fprintf_func) (info->stream, "word\t%08x", instruction); - else - { - (*info->fprintf_func) (info->stream, "%s ", entry_ptr->mnemonic); - printop (info, &(entry_ptr->op1), instruction, pc, 1); - printop (info, &(entry_ptr->op2), instruction, pc, 0); - printop (info, &(entry_ptr->op3), instruction, pc, 0); - } - - return 4; -} - -/* -* Decode an Operand of an Instruction -* -* Functional Description -* -* This module formats and writes an operand of an instruction to info -* based on the operand specification. When the first flag is set this -* is the first operand of an instruction. Undefined operand types -* cause a <dis error> message. -* -* Parameters -* disassemble_info where the operand may be printed -* OPSPEC *opptr Pointer to an operand specification -* UINT inst Instruction from which operand is extracted -* UINT pc PC of instruction; used for pc-relative disp. -* int first Flag which if nonzero indicates the first -* operand of an instruction -* -* Output -* -* The operand specified is extracted from the instruction and is -* written to buf in the format specified. The operand is preceded -* by a comma if it is not the first operand of an instruction and it -* is not a register indirect form. Registers are preceded by 'r' and -* hex values by '0x'. -* -* Revision History -* -* Revision 1.0 11/08/85 Creation date -*/ - -static void -printop (info, opptr, inst, pc, first) - struct disassemble_info *info; - OPSPEC *opptr; - unsigned long inst; - bfd_vma pc; - int first; -{ - int extracted_field; - char *cond_mask_sym; - - if (opptr->width == 0) - return; - - if (! first) - { - switch (opptr->type) - { - case REGSC: - case CONT: - break; - default: - (*info->fprintf_func) (info->stream, ","); - break; - } - } - - switch (opptr->type) - { - case CRREG: - (*info->fprintf_func) (info->stream, "cr%d", - UEXT (inst, opptr->offset, opptr->width)); - break; - - case FCRREG: - (*info->fprintf_func) (info->stream, "fcr%d", - UEXT (inst, opptr->offset, opptr->width)); - break; - - case REGSC: - (*info->fprintf_func) (info->stream, "[r%d]", - UEXT (inst, opptr->offset, opptr->width)); - break; - - case REG: - (*info->fprintf_func) (info->stream, "r%d", - UEXT (inst, opptr->offset, opptr->width)); - break; - - case HEX: - extracted_field = UEXT (inst, opptr->offset, opptr->width); - if (extracted_field == 0) - (*info->fprintf_func) (info->stream, "0"); - else - (*info->fprintf_func) (info->stream, "0x%02x", extracted_field); - break; - - case CONDMASK: - extracted_field = UEXT (inst, opptr->offset, opptr->width); - switch (extracted_field & 0x0f) - { - case 0x1: cond_mask_sym = "gt0"; break; - case 0x2: cond_mask_sym = "eq0"; break; - case 0x3: cond_mask_sym = "ge0"; break; - case 0xc: cond_mask_sym = "lt0"; break; - case 0xd: cond_mask_sym = "ne0"; break; - case 0xe: cond_mask_sym = "le0"; break; - default: cond_mask_sym = NULL; break; - } - if (cond_mask_sym != NULL) - (*info->fprintf_func) (info->stream, "%s", cond_mask_sym); - else - (*info->fprintf_func) (info->stream, "%x", extracted_field); - break; - - case PCREL: - (*info->print_address_func) - (pc + (4 * (SEXT (inst, opptr->offset, opptr->width))), - info); - break; - - case CONT: - (*info->fprintf_func) (info->stream, "%d,r%d", - UEXT (inst, opptr->offset, 5), - UEXT (inst, (opptr->offset) + 5, 5)); - break; - - case BF: - (*info->fprintf_func) (info->stream, "%d<%d>", - UEXT (inst, (opptr->offset) + 5, 5), - UEXT (inst, opptr->offset, 5)); - break; - - default: - (*info->fprintf_func) (info->stream, "# <dis error: %08x>", inst); - } -} - -/* -* Initialize the Disassembler Instruction Table -* -* Initialize the hash table and instruction table for the disassembler. -* This should be called once before the first call to disasm(). -* -* Parameters -* -* Output -* -* If the debug option is selected, certain statistics about the hashing -* distribution are written to stdout. -* -* Revision History -* -* Revision 1.0 11/08/85 Creation date -*/ - -static void -init_disasm () -{ - int i, size; - - for (i = 0; i < HASHVAL; i++) - hashtable[i] = NULL; - - size = sizeof (instructions) / sizeof (INSTAB); - for (i = 0; i < size; i++) - install (&instructions[i]); -} - -/* -* Insert an instruction into the disassembler table by hashing the -* opcode and inserting it into the linked list for that hash value. -* -* Parameters -* -* INSTAB *instptr Pointer to the entry in the instruction table -* to be installed -* -* Revision 1.0 11/08/85 Creation date -* 05/11/89 R. TRAWICK ADAPTED FROM MOTOROLA -*/ - -static void -install (instptr) - INSTAB *instptr; -{ - unsigned int i; - - i = (instptr->opcode) % HASHVAL; - instptr->next = hashtable[i]; - hashtable[i] = instptr; -} diff --git a/opcodes/makefile.vms b/opcodes/makefile.vms deleted file mode 100644 index 5a472a752c8..00000000000 --- a/opcodes/makefile.vms +++ /dev/null @@ -1,31 +0,0 @@ -# -# Makefile for libopcodes under openVMS/AXP -# -# For use with gnu-make for vms -# -# Created by Klaus Kaempf, kkaempf@progis.de -# -# -CC=gcc - -OBJS=alpha-dis.obj,dis-buf.obj,disassemble.obj - -ifeq ($(CC),gcc) -CFLAGS=/include=([],[-.include],[-.bfd])$(DEFS) -DEFS=/define=(VMS_ASMCODE=1) -else -CFLAGS=/noopt/debug/include=([],[-.include],[-.bfd])$(DEFS) -DEFS=/define=(VMS_ASMCODE=1) -endif - -libopcodes.olb: sysdep.h $(OBJS) - purge - lib/create libopcodes *.obj - -disassemble.obj: disassemble.c - $(CC)$(CFLAGS)/define=("ARCH_alpha") $< - -alpha-dis.obj: alpha-dis.c alpha-opc.h - -sysdep.h: [-.bfd.hosts]alphavms.h - $(CP) $< $@ diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c deleted file mode 100644 index 62eb63bd3e0..00000000000 --- a/opcodes/mips-dis.c +++ /dev/null @@ -1,1285 +0,0 @@ -/* Print mips instructions for GDB, the GNU debugger, or for objdump. - Copyright (c) 1989, 91-97, 1998 Free Software Foundation, Inc. - Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp). - -This file is part of GDB, GAS, and the GNU binutils. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include <ansidecl.h> -#include "sysdep.h" -#include "dis-asm.h" -#include "opcode/mips.h" -#include "opintl.h" - -/* FIXME: These are needed to figure out if the code is mips16 or - not. The low bit of the address is often a good indicator. No - symbol table is available when this code runs out in an embedded - system as when it is used for disassembler support in a monitor. */ - -#if !defined(EMBEDDED_ENV) -#define SYMTAB_AVAILABLE 1 -#include "elf-bfd.h" -#include "elf/mips.h" -#endif - -static int print_insn_mips16 PARAMS ((bfd_vma, struct disassemble_info *)); -static void print_mips16_insn_arg - PARAMS ((int, const struct mips_opcode *, int, boolean, int, bfd_vma, - struct disassemble_info *)); - -/* Mips instructions are never longer than this many bytes. */ -#define MAXLEN 4 - -static void print_insn_arg PARAMS ((const char *, unsigned long, bfd_vma, - struct disassemble_info *)); -static int _print_insn_mips PARAMS ((bfd_vma, unsigned long int, - struct disassemble_info *)); - - -/* FIXME: This should be shared with gdb somehow. */ -#define REGISTER_NAMES \ - { "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", \ - "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \ - "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \ - "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", \ - "sr", "lo", "hi", "bad", "cause","pc", \ - "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ - "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ - "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",\ - "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",\ - "fsr", "fir", "fp", "inx", "rand", "tlblo","ctxt", "tlbhi",\ - "epc", "prid"\ - } - -static CONST char * CONST reg_names[] = REGISTER_NAMES; - -/* The mips16 register names. */ -static const char * const mips16_reg_names[] = -{ - "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3" -}; - -/* subroutine */ -static void -print_insn_arg (d, l, pc, info) - const char *d; - register unsigned long int l; - bfd_vma pc; - struct disassemble_info *info; -{ - int delta; - - switch (*d) - { - case ',': - case '(': - case ')': - /* start-sanitize-cygnus */ - case '[': - case ']': - /* end-sanitize-cygnus */ - /* start-sanitize-r5900 */ - case '+': - case '-': - /* end-sanitize-r5900 */ - (*info->fprintf_func) (info->stream, "%c", *d); - break; - - case 's': - case 'b': - case 'r': - case 'v': - (*info->fprintf_func) (info->stream, "$%s", - reg_names[(l >> OP_SH_RS) & OP_MASK_RS]); - break; - - case 't': - case 'w': - (*info->fprintf_func) (info->stream, "$%s", - reg_names[(l >> OP_SH_RT) & OP_MASK_RT]); - break; - - case 'i': - case 'u': - (*info->fprintf_func) (info->stream, "0x%x", - (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE); - break; - - case 'j': /* same as i, but sign-extended */ - case 'o': - delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; - if (delta & 0x8000) - delta |= ~0xffff; - (*info->fprintf_func) (info->stream, "%d", - delta); - break; - - case 'h': - (*info->fprintf_func) (info->stream, "0x%x", - (unsigned int) ((l >> OP_SH_PREFX) - & OP_MASK_PREFX)); - break; - - case 'k': - (*info->fprintf_func) (info->stream, "0x%x", - (unsigned int) ((l >> OP_SH_CACHE) - & OP_MASK_CACHE)); - break; - - case 'a': - (*info->print_address_func) - (((pc & 0xF0000000) | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)), - info); - break; - - case 'p': - /* sign extend the displacement */ - delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; - if (delta & 0x8000) - delta |= ~0xffff; - (*info->print_address_func) - ((delta << 2) + pc + 4, - info); - break; - - case 'd': - (*info->fprintf_func) (info->stream, "$%s", - reg_names[(l >> OP_SH_RD) & OP_MASK_RD]); - break; - - case 'z': - (*info->fprintf_func) (info->stream, "$%s", reg_names[0]); - break; - - case '<': - (*info->fprintf_func) (info->stream, "0x%x", - (l >> OP_SH_SHAMT) & OP_MASK_SHAMT); - break; - - case 'c': - (*info->fprintf_func) (info->stream, "0x%x", - (l >> OP_SH_CODE) & OP_MASK_CODE); - break; - - - case 'q': - (*info->fprintf_func) (info->stream, "0x%x", - (l >> OP_SH_CODE2) & OP_MASK_CODE2); - break; - - case 'C': - (*info->fprintf_func) (info->stream, "0x%x", - (l >> OP_SH_COPZ) & OP_MASK_COPZ); - break; - - case 'B': - (*info->fprintf_func) (info->stream, "0x%x", - (l >> OP_SH_SYSCALL) & OP_MASK_SYSCALL); - break; - - case 'S': - case 'V': - (*info->fprintf_func) (info->stream, "$f%d", - (l >> OP_SH_FS) & OP_MASK_FS); - break; - - /* start-sanitize-r5900 */ - case '0': - (*info->fprintf_func) (info->stream, "0x%x", - (l >> 6) & 0x1f); - break; - - case '9': - (*info->fprintf_func) (info->stream, "vi27"); - break; - - case '1': - (*info->fprintf_func) (info->stream, "vf%d", - (l >> OP_SH_FT) & OP_MASK_FT); - break; - case '2': - (*info->fprintf_func) (info->stream, "vf%d", - (l >> OP_SH_FS) & OP_MASK_FS); - break; - case '3': - (*info->fprintf_func) (info->stream, "vf%d", - (l >> OP_SH_FD) & OP_MASK_FD); - break; - - case '4': - (*info->fprintf_func) (info->stream, "vi%d", - (l >> OP_SH_FT) & OP_MASK_FT); - break; - case '5': - (*info->fprintf_func) (info->stream, "vi%d", - (l >> OP_SH_FS) & OP_MASK_FS); - break; - case '6': - (*info->fprintf_func) (info->stream, "vi%d", - (l >> OP_SH_FD) & OP_MASK_FD); - break; - - case '7': - (*info->fprintf_func) (info->stream, "vf%d", - (l >> OP_SH_FT) & OP_MASK_FT); - switch ((l >> 23) & 0x3) - { - case 0: - (*info->fprintf_func) (info->stream, "x"); - break; - case 1: - (*info->fprintf_func) (info->stream, "y"); - break; - case 2: - (*info->fprintf_func) (info->stream, "z"); - break; - case 3: - (*info->fprintf_func) (info->stream, "w"); - break; - } - break; - case 'K': - break; - - case ';': - (*info->fprintf_func) (info->stream, ".xyz\t"); - break; - - case '&': - (*info->fprintf_func) (info->stream, "."); - if (l & (1 << 21)) - (*info->fprintf_func) (info->stream, "w"); - if (l & (1 << 24)) - (*info->fprintf_func) (info->stream, "x"); - if (l & (1 << 23)) - (*info->fprintf_func) (info->stream, "y"); - if (l & (1 << 22)) - (*info->fprintf_func) (info->stream, "z"); - (*info->fprintf_func) (info->stream, "\t"); - break; - - case '8': - (*info->fprintf_func) (info->stream, "vf%d", - (l >> OP_SH_FS) & OP_MASK_FS); - switch ((l >> 21) & 0x3) - { - case 0: - (*info->fprintf_func) (info->stream, "x"); - break; - case 1: - (*info->fprintf_func) (info->stream, "y"); - break; - case 2: - (*info->fprintf_func) (info->stream, "z"); - break; - case 3: - (*info->fprintf_func) (info->stream, "w"); - break; - } - break; - case 'J': - (*info->fprintf_func) (info->stream, "I"); - break; - - case 'Q': - (*info->fprintf_func) (info->stream, "Q"); - break; - - case 'X': - (*info->fprintf_func) (info->stream, "R"); - break; - - case 'U': - (*info->fprintf_func) (info->stream, "ACC"); - break; - - case 'O': - delta = (l >> 6) & 0x7fff; - delta <<= 3; - (*info->print_address_func) (delta, info); - break; - - /* end-sanitize-r5900 */ - - case 'T': - case 'W': - (*info->fprintf_func) (info->stream, "$f%d", - (l >> OP_SH_FT) & OP_MASK_FT); - break; - - case 'D': - (*info->fprintf_func) (info->stream, "$f%d", - (l >> OP_SH_FD) & OP_MASK_FD); - break; - - case 'R': - (*info->fprintf_func) (info->stream, "$f%d", - (l >> OP_SH_FR) & OP_MASK_FR); - break; - - case 'E': - (*info->fprintf_func) (info->stream, "$%d", - (l >> OP_SH_RT) & OP_MASK_RT); - break; - - case 'G': - (*info->fprintf_func) (info->stream, "$%d", - (l >> OP_SH_RD) & OP_MASK_RD); - break; - - case 'N': - (*info->fprintf_func) (info->stream, "$fcc%d", - (l >> OP_SH_BCC) & OP_MASK_BCC); - break; - - case 'M': - (*info->fprintf_func) (info->stream, "$fcc%d", - (l >> OP_SH_CCC) & OP_MASK_CCC); - break; - - case 'P': - (*info->fprintf_func) (info->stream, "%d", - (l >> OP_SH_PERFREG) & OP_MASK_PERFREG); - break; - - /* start-sanitize-cygnus */ - case 'e': - (*info->fprintf_func) (info->stream, "%d", - (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE); - break; - - case '%': - (*info->fprintf_func) (info->stream, "%d", - (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN); - break; - /* end-sanitize-cygnus */ - - default: - /* xgettext:c-format */ - (*info->fprintf_func) (info->stream, - _("# internal error, undefined modifier(%c)"), - *d); - break; - } -} - -#if SYMTAB_AVAILABLE - -/* Figure out the MIPS ISA and CPU based on the machine number. - FIXME: What does this have to do with SYMTAB_AVAILABLE? */ - -static void -set_mips_isa_type (mach, isa, cputype) - int mach; - int *isa; - int *cputype; -{ - int target_processor = 0; - int mips_isa = 0; - - switch (mach) - { - /* start-sanitize-tx19 */ - case bfd_mach_mips1900: - target_processor = 1900; - mips_isa = 1; - break; - /* end-sanitize-tx19 */ - case bfd_mach_mips3000: - target_processor = 3000; - mips_isa = 1; - break; - case bfd_mach_mips3900: - target_processor = 3900; - mips_isa = 1; - break; - case bfd_mach_mips4000: - target_processor = 4000; - mips_isa = 3; - break; - case bfd_mach_mips4010: - target_processor = 4010; - mips_isa = 2; - break; - case bfd_mach_mips4100: - target_processor = 4100; - mips_isa = 3; - break; - /* start-sanitize-vr4xxx */ - case bfd_mach_mips4121: - target_processor = 4121; - mips_isa = 3; - break; - /* end-sanitize-vr4xxx */ - case bfd_mach_mips4300: - target_processor = 4300; - mips_isa = 3; - break; - /* start-sanitize-vr4320 */ - case bfd_mach_mips4320: - target_processor = 4320; - mips_isa = 3; - break; - /* end-sanitize-vr4320 */ - case bfd_mach_mips4400: - target_processor = 4400; - mips_isa = 3; - break; - case bfd_mach_mips4600: - target_processor = 4600; - mips_isa = 3; - break; - case bfd_mach_mips4650: - target_processor = 4650; - mips_isa = 3; - break; - /* start-sanitize-tx49 */ - case bfd_mach_mips4900: - target_processor = 4900; - mips_isa = 3; - break; - /* end-sanitize-tx49 */ - case bfd_mach_mips5000: - target_processor = 5000; - mips_isa = 4; - break; - /* start-sanitize-cygnus */ - case bfd_mach_mips5400: - target_processor = 5400; - mips_isa = 3; - break; - /* end-sanitize-cygnus */ - /* start-sanitize-r5900 */ - case bfd_mach_mips5900: - target_processor = 5900; - mips_isa = 3; - break; - /* end-sanitize-r5900 */ - case bfd_mach_mips6000: - target_processor = 6000; - mips_isa = 2; - break; - case bfd_mach_mips8000: - target_processor = 8000; - mips_isa = 4; - break; - case bfd_mach_mips10000: - target_processor = 10000; - mips_isa = 4; - break; - case bfd_mach_mips16: - target_processor = 16; - mips_isa = 3; - break; - default: - target_processor = 3000; - mips_isa = 3; - break; - - } - - *isa = mips_isa; - *cputype = target_processor; -} - -#endif /* SYMTAB_AVAILABLE */ - -/* Print the mips instruction at address MEMADDR in debugged memory, - on using INFO. Returns length of the instruction, in bytes, which is - always 4. BIGENDIAN must be 1 if this is big-endian code, 0 if - this is little-endian code. */ - -static int -_print_insn_mips (memaddr, word, info) - bfd_vma memaddr; - unsigned long int word; - struct disassemble_info *info; -{ - register const struct mips_opcode *op; - int target_processor, mips_isa; - static boolean init = 0; - static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; - - /* Build a hash table to shorten the search time. */ - if (! init) - { - unsigned int i; - - for (i = 0; i <= OP_MASK_OP; i++) - { - for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++) - { - if (op->pinfo == INSN_MACRO) - continue; - if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) - { - mips_hash[i] = op; - break; - } - } - } - - init = 1; - } - -#if ! SYMTAB_AVAILABLE - /* This is running out on a target machine, not in a host tool. - FIXME: Where does mips_target_info come from? */ - target_processor = mips_target_info.processor; - mips_isa = mips_target_info.isa; -#else - set_mips_isa_type (info->mach, &mips_isa, &target_processor); -#endif - - info->bytes_per_chunk = 4; - info->display_endian = info->endian; - - op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP]; - if (op != NULL) - { - for (; op < &mips_opcodes[NUMOPCODES]; op++) - { - if (op->pinfo != INSN_MACRO && (word & op->mask) == op->match) - { - register const char *d; - int insn_isa; - - if ((op->membership & INSN_ISA) == INSN_ISA1) - insn_isa = 1; - else if ((op->membership & INSN_ISA) == INSN_ISA2) - insn_isa = 2; - else if ((op->membership & INSN_ISA) == INSN_ISA3) - insn_isa = 3; - else if ((op->membership & INSN_ISA) == INSN_ISA4) - insn_isa = 4; - else - insn_isa = 15; - - if (insn_isa > mips_isa - && (target_processor == 4650 - && op->membership & INSN_4650) == 0 - && (target_processor == 4010 - && op->membership & INSN_4010) == 0 - && (target_processor == 4100 - && op->membership & INSN_4100) == 0 - /* start-sanitize-vr4xxx */ - && (target_processor == 4121 - && op->membership & INSN_4121) == 0 - /* end-sanitize-vr4xxx */ - /* start-sanitize-vr4320 */ - && (target_processor == 4320 - && op->membership & INSN_4320) == 0 - /* end-sanitize-vr4320 */ - /* start-sanitize-cygnus */ - && (target_processor == 5400 - && op->membership & INSN_5400) == 0 - /* end-sanitize-cygnus */ - /* start-sanitize-r5900 */ - && (target_processor == 5900 - && op->membership & INSN_5900) == 0 - /* end-sanitize-r5900 */ - /* start-sanitize-tx49 */ - && (target_processor == 4900 - && op->membership & INSN_4900) == 0 - /* end-sanitize-tx49 */ - && (target_processor == 3900 - && op->membership & INSN_3900) == 0) - continue; - - (*info->fprintf_func) (info->stream, "%s", op->name); - - d = op->args; - if (d != NULL && *d != '\0') - { - /* start-sanitize-r5900 */ - /* If this is an opcode completer, then do not emit - a tab after the opcode. */ - if (*d != '&' && *d != ';') - /* end-sanitize-r5900 */ - (*info->fprintf_func) (info->stream, "\t"); - for (; *d != '\0'; d++) - /* start-sanitize-r5900 */ - /* If this is an escape character, go ahead and print the - next character in the arg string verbatim. */ - if (*d == '#') - { - d++; - (*info->fprintf_func) (info->stream, "%c", *d); - } - else - /* end-sanitize-r5900 */ - print_insn_arg (d, word, memaddr, info); - } - - return 4; - } - } - } - - /* Handle undefined instructions. */ - (*info->fprintf_func) (info->stream, "0x%x", word); - return 4; -} - - -/* In an environment where we do not know the symbol type of the - instruction we are forced to assume that the low order bit of the - instructions' address may mark it as a mips16 instruction. If we - are single stepping, or the pc is within the disassembled function, - this works. Otherwise, we need a clue. Sometimes. */ - -int -print_insn_big_mips (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - bfd_byte buffer[4]; - int status; - -#if 1 - /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */ - /* Only a few tools will work this way. */ - if (memaddr & 0x01) - return print_insn_mips16 (memaddr, info); -#endif - -#if SYMTAB_AVAILABLE - if (info->mach == 16 - || (info->flavour == bfd_target_elf_flavour - && info->symbols != NULL - && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other - == STO_MIPS16))) - return print_insn_mips16 (memaddr, info); -#endif - - status = (*info->read_memory_func) (memaddr, buffer, 4, info); - if (status == 0) - return _print_insn_mips (memaddr, (unsigned long) bfd_getb32 (buffer), - info); - else - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } -} - -int -print_insn_little_mips (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - bfd_byte buffer[4]; - int status; - - /* start-sanitize-sky */ -#ifdef ARCH_dvp - { - /* bfd_mach_dvp_p is a macro which may evaluate its arguments more than - once. Since dvp_mach_type is a function, ensure it's only called - once. */ - int mach = dvp_info_mach_type (info); - - if (bfd_mach_dvp_p (info->mach) - || bfd_mach_dvp_p (mach)) - return print_insn_dvp (memaddr, info); - } -#endif - /* end-sanitize-sky */ - -#if 1 - if (memaddr & 0x01) - return print_insn_mips16 (memaddr, info); -#endif - -#if SYMTAB_AVAILABLE - if (info->mach == 16 - || (info->flavour == bfd_target_elf_flavour - && info->symbols != NULL - && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other - == STO_MIPS16))) - return print_insn_mips16 (memaddr, info); -#endif - - status = (*info->read_memory_func) (memaddr, buffer, 4, info); - if (status == 0) - return _print_insn_mips (memaddr, (unsigned long) bfd_getl32 (buffer), - info); - else - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } -} - -/* Disassemble mips16 instructions. */ - -static int -print_insn_mips16 (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - int status; - bfd_byte buffer[2]; - int length; - int insn; - boolean use_extend; - int extend = 0; - const struct mips_opcode *op, *opend; - - info->bytes_per_chunk = 2; - info->display_endian = info->endian; - - info->insn_info_valid = 1; - info->branch_delay_insns = 0; - info->data_size = 0; - info->insn_type = dis_nonbranch; - info->target = 0; - info->target2 = 0; - - status = (*info->read_memory_func) (memaddr, buffer, 2, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - - length = 2; - - if (info->endian == BFD_ENDIAN_BIG) - insn = bfd_getb16 (buffer); - else - insn = bfd_getl16 (buffer); - - /* Handle the extend opcode specially. */ - use_extend = false; - if ((insn & 0xf800) == 0xf000) - { - use_extend = true; - extend = insn & 0x7ff; - - memaddr += 2; - - status = (*info->read_memory_func) (memaddr, buffer, 2, info); - if (status != 0) - { - (*info->fprintf_func) (info->stream, "extend 0x%x", - (unsigned int) extend); - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - - if (info->endian == BFD_ENDIAN_BIG) - insn = bfd_getb16 (buffer); - else - insn = bfd_getl16 (buffer); - - /* Check for an extend opcode followed by an extend opcode. */ - if ((insn & 0xf800) == 0xf000) - { - (*info->fprintf_func) (info->stream, "extend 0x%x", - (unsigned int) extend); - info->insn_type = dis_noninsn; - return length; - } - - length += 2; - } - - /* FIXME: Should probably use a hash table on the major opcode here. */ - - opend = mips16_opcodes + bfd_mips16_num_opcodes; - for (op = mips16_opcodes; op < opend; op++) - { - if (op->pinfo != INSN_MACRO && (insn & op->mask) == op->match) - { - const char *s; - - if (strchr (op->args, 'a') != NULL) - { - if (use_extend) - { - (*info->fprintf_func) (info->stream, "extend 0x%x", - (unsigned int) extend); - info->insn_type = dis_noninsn; - return length - 2; - } - - use_extend = false; - - memaddr += 2; - - status = (*info->read_memory_func) (memaddr, buffer, 2, - info); - if (status == 0) - { - use_extend = true; - if (info->endian == BFD_ENDIAN_BIG) - extend = bfd_getb16 (buffer); - else - extend = bfd_getl16 (buffer); - length += 2; - } - } - - (*info->fprintf_func) (info->stream, "%s", op->name); - if (op->args[0] != '\0') - (*info->fprintf_func) (info->stream, "\t"); - - for (s = op->args; *s != '\0'; s++) - { - if (*s == ',' - && s[1] == 'w' - && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) - == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY))) - { - /* Skip the register and the comma. */ - ++s; - continue; - } - if (*s == ',' - && s[1] == 'v' - && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ) - == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX))) - { - /* Skip the register and the comma. */ - ++s; - continue; - } - print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr, - info); - } - - if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) - { - info->branch_delay_insns = 1; - if (info->insn_type != dis_jsr) - info->insn_type = dis_branch; - } - - return length; - } - } - - if (use_extend) - (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000); - (*info->fprintf_func) (info->stream, "0x%x", insn); - info->insn_type = dis_noninsn; - - return length; -} - -/* Disassemble an operand for a mips16 instruction. */ - -static void -print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info) - int type; - const struct mips_opcode *op; - int l; - boolean use_extend; - int extend; - bfd_vma memaddr; - struct disassemble_info *info; -{ - switch (type) - { - case ',': - case '(': - case ')': - (*info->fprintf_func) (info->stream, "%c", type); - break; - - case 'y': - case 'w': - (*info->fprintf_func) (info->stream, "$%s", - mips16_reg_names[((l >> MIPS16OP_SH_RY) - & MIPS16OP_MASK_RY)]); - break; - - case 'x': - case 'v': - (*info->fprintf_func) (info->stream, "$%s", - mips16_reg_names[((l >> MIPS16OP_SH_RX) - & MIPS16OP_MASK_RX)]); - break; - - case 'z': - (*info->fprintf_func) (info->stream, "$%s", - mips16_reg_names[((l >> MIPS16OP_SH_RZ) - & MIPS16OP_MASK_RZ)]); - break; - - case 'Z': - (*info->fprintf_func) (info->stream, "$%s", - mips16_reg_names[((l >> MIPS16OP_SH_MOVE32Z) - & MIPS16OP_MASK_MOVE32Z)]); - break; - - case '0': - (*info->fprintf_func) (info->stream, "$%s", reg_names[0]); - break; - - case 'S': - (*info->fprintf_func) (info->stream, "$%s", reg_names[29]); - break; - - case 'P': - (*info->fprintf_func) (info->stream, "$pc"); - break; - - case 'R': - (*info->fprintf_func) (info->stream, "$%s", reg_names[31]); - break; - - case 'X': - (*info->fprintf_func) (info->stream, "$%s", - reg_names[((l >> MIPS16OP_SH_REGR32) - & MIPS16OP_MASK_REGR32)]); - break; - - case 'Y': - (*info->fprintf_func) (info->stream, "$%s", - reg_names[MIPS16OP_EXTRACT_REG32R (l)]); - break; - - case '<': - case '>': - case '[': - case ']': - case '4': - case '5': - case 'H': - case 'W': - case 'D': - case 'j': - case '6': - case '8': - case 'V': - case 'C': - case 'U': - case 'k': - case 'K': - case 'p': - case 'q': - case 'A': - case 'B': - case 'E': - { - int immed, nbits, shift, signedp, extbits, pcrel, extu, branch; - - shift = 0; - signedp = 0; - extbits = 16; - pcrel = 0; - extu = 0; - branch = 0; - switch (type) - { - case '<': - nbits = 3; - immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; - extbits = 5; - extu = 1; - break; - case '>': - nbits = 3; - immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; - extbits = 5; - extu = 1; - break; - case '[': - nbits = 3; - immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; - extbits = 6; - extu = 1; - break; - case ']': - nbits = 3; - immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; - extbits = 6; - extu = 1; - break; - case '4': - nbits = 4; - immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4; - signedp = 1; - extbits = 15; - break; - case '5': - nbits = 5; - immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; - info->insn_type = dis_dref; - info->data_size = 1; - break; - case 'H': - nbits = 5; - shift = 1; - immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; - info->insn_type = dis_dref; - info->data_size = 2; - break; - case 'W': - nbits = 5; - shift = 2; - immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; - if ((op->pinfo & MIPS16_INSN_READ_PC) == 0 - && (op->pinfo & MIPS16_INSN_READ_SP) == 0) - { - info->insn_type = dis_dref; - info->data_size = 4; - } - break; - case 'D': - nbits = 5; - shift = 3; - immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; - info->insn_type = dis_dref; - info->data_size = 8; - break; - case 'j': - nbits = 5; - immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; - signedp = 1; - break; - case '6': - nbits = 6; - immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; - break; - case '8': - nbits = 8; - immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; - break; - case 'V': - nbits = 8; - shift = 2; - immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; - /* FIXME: This might be lw, or it might be addiu to $sp or - $pc. We assume it's load. */ - info->insn_type = dis_dref; - info->data_size = 4; - break; - case 'C': - nbits = 8; - shift = 3; - immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; - info->insn_type = dis_dref; - info->data_size = 8; - break; - case 'U': - nbits = 8; - immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; - extu = 1; - break; - case 'k': - nbits = 8; - immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; - signedp = 1; - break; - case 'K': - nbits = 8; - shift = 3; - immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; - signedp = 1; - break; - case 'p': - nbits = 8; - immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; - signedp = 1; - pcrel = 1; - branch = 1; - info->insn_type = dis_condbranch; - break; - case 'q': - nbits = 11; - immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11; - signedp = 1; - pcrel = 1; - branch = 1; - info->insn_type = dis_branch; - break; - case 'A': - nbits = 8; - shift = 2; - immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; - pcrel = 1; - /* FIXME: This can be lw or la. We assume it is lw. */ - info->insn_type = dis_dref; - info->data_size = 4; - break; - case 'B': - nbits = 5; - shift = 3; - immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; - pcrel = 1; - info->insn_type = dis_dref; - info->data_size = 8; - break; - case 'E': - nbits = 5; - shift = 2; - immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; - pcrel = 1; - break; - default: - abort (); - } - - if (! use_extend) - { - if (signedp && immed >= (1 << (nbits - 1))) - immed -= 1 << nbits; - immed <<= shift; - if ((type == '<' || type == '>' || type == '[' || type == ']') - && immed == 0) - immed = 8; - } - else - { - if (extbits == 16) - immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0); - else if (extbits == 15) - immed |= ((extend & 0xf) << 11) | (extend & 0x7f0); - else - immed = ((extend >> 6) & 0x1f) | (extend & 0x20); - immed &= (1 << extbits) - 1; - if (! extu && immed >= (1 << (extbits - 1))) - immed -= 1 << extbits; - } - - if (! pcrel) - (*info->fprintf_func) (info->stream, "%d", immed); - else - { - bfd_vma baseaddr; - bfd_vma val; - - if (branch) - { - immed *= 2; - baseaddr = memaddr + 2; - } - else if (use_extend) - baseaddr = memaddr - 2; - else - { - int status; - bfd_byte buffer[2]; - - baseaddr = memaddr; - - /* If this instruction is in the delay slot of a jr - instruction, the base address is the address of the - jr instruction. If it is in the delay slot of jalr - instruction, the base address is the address of the - jalr instruction. This test is unreliable: we have - no way of knowing whether the previous word is - instruction or data. */ - status = (*info->read_memory_func) (memaddr - 4, buffer, 2, - info); - if (status == 0 - && (((info->endian == BFD_ENDIAN_BIG - ? bfd_getb16 (buffer) - : bfd_getl16 (buffer)) - & 0xf800) == 0x1800)) - baseaddr = memaddr - 4; - else - { - status = (*info->read_memory_func) (memaddr - 2, buffer, - 2, info); - if (status == 0 - && (((info->endian == BFD_ENDIAN_BIG - ? bfd_getb16 (buffer) - : bfd_getl16 (buffer)) - & 0xf81f) == 0xe800)) - baseaddr = memaddr - 2; - } - } - val = (baseaddr & ~ ((1 << shift) - 1)) + immed; - (*info->print_address_func) (val, info); - info->target = val; - } - } - break; - - case 'a': - if (! use_extend) - extend = 0; - l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); - (*info->print_address_func) ((memaddr & 0xf0000000) | l, info); - info->insn_type = dis_jsr; - info->target = (memaddr & 0xf0000000) | l; - info->branch_delay_insns = 1; - break; - - case 'l': - case 'L': - { - int need_comma, amask, smask; - - need_comma = 0; - - l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; - - amask = (l >> 3) & 7; - - if (amask > 0 && amask < 5) - { - (*info->fprintf_func) (info->stream, "$%s", reg_names[4]); - if (amask > 1) - (*info->fprintf_func) (info->stream, "-$%s", - reg_names[amask + 3]); - need_comma = 1; - } - - smask = (l >> 1) & 3; - if (smask == 3) - { - (*info->fprintf_func) (info->stream, "%s??", - need_comma ? "," : ""); - need_comma = 1; - } - else if (smask > 0) - { - (*info->fprintf_func) (info->stream, "%s$%s", - need_comma ? "," : "", - reg_names[16]); - if (smask > 1) - (*info->fprintf_func) (info->stream, "-$%s", - reg_names[smask + 15]); - need_comma = 1; - } - - if (l & 1) - { - (*info->fprintf_func) (info->stream, "%s$%s", - need_comma ? "," : "", - reg_names[31]); - need_comma = 1; - } - - if (amask == 5 || amask == 6) - { - (*info->fprintf_func) (info->stream, "%s$f0", - need_comma ? "," : ""); - if (amask == 6) - (*info->fprintf_func) (info->stream, "-$f1"); - } - } - break; - - default: - abort (); - } -} diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c deleted file mode 100644 index caf3d098d37..00000000000 --- a/opcodes/mips-opc.c +++ /dev/null @@ -1,1346 +0,0 @@ -/* mips.h. Mips opcode list for GDB, the GNU debugger. - Copyright 1993, 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc. - Contributed by Ralph Campbell and OSF - Commented and modified by Ian Lance Taylor, Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include <stdio.h> -#include "ansidecl.h" -#include "opcode/mips.h" - -/* Short hand so the lines aren't too long. */ - -#define LDD INSN_LOAD_MEMORY_DELAY -#define LCD INSN_LOAD_COPROC_DELAY -#define UBD INSN_UNCOND_BRANCH_DELAY -#define CBD INSN_COND_BRANCH_DELAY -#define COD INSN_COPROC_MOVE_DELAY -#define CLD INSN_COPROC_MEMORY_DELAY -#define CBL INSN_COND_BRANCH_LIKELY -#define TRAP INSN_TRAP -#define SM INSN_STORE_MEMORY - -#define WR_d INSN_WRITE_GPR_D -#define WR_t INSN_WRITE_GPR_T -#define WR_31 INSN_WRITE_GPR_31 -#define WR_D INSN_WRITE_FPR_D -#define WR_T INSN_WRITE_FPR_T -#define WR_S INSN_WRITE_FPR_S -#define RD_s INSN_READ_GPR_S -#define RD_b INSN_READ_GPR_S -#define RD_t INSN_READ_GPR_T -#define RD_S INSN_READ_FPR_S -#define RD_T INSN_READ_FPR_T -#define RD_R INSN_READ_FPR_R -#define WR_CC INSN_WRITE_COND_CODE -#define RD_CC INSN_READ_COND_CODE -#define RD_C0 INSN_COP -#define RD_C1 INSN_COP -#define RD_C2 INSN_COP -#define RD_C3 INSN_COP -#define WR_C0 INSN_COP -#define WR_C1 INSN_COP -#define WR_C2 INSN_COP -#define WR_C3 INSN_COP - -#define WR_HI INSN_WRITE_HI -#define RD_HI INSN_READ_HI -#define MOD_HI WR_HI|RD_HI - -#define WR_LO INSN_WRITE_LO -#define RD_LO INSN_READ_LO -#define MOD_LO WR_LO|RD_LO - -#define WR_HILO WR_HI|WR_LO -#define RD_HILO RD_HI|RD_LO -#define MOD_HILO WR_HILO|RD_HILO - -#define IS_M INSN_MULT - -#define I1 INSN_ISA1 -#define I2 INSN_ISA2 -#define I3 INSN_ISA3 -#define I4 INSN_ISA4 -#define P3 INSN_4650 -#define L1 INSN_4010 -#define V1 INSN_4100 -#define T3 INSN_3900 -/* start-sanitize-tx49 */ -#define T4 INSN_4900 -/* end-sanitize-tx49 */ -/* start-sanitize-vr4320 */ -#define N4 INSN_4320 -/* end-sanitize-vr4320 */ -/* start-sanitize-cygnus */ -#define N5 INSN_5400 -/* end-sanitize-cygnus */ -/* start-sanitize-r5900 */ -#define T5 INSN_5900 -/* end-sanitize-r5900 */ - -#define G1 (T3 \ -/* start-sanitize-tx49 */ \ - | T4 \ -/* end-sanitize-tx49 */ \ -/* start-sanitize-r5900 */ \ - | T5 \ -/* end-sanitize-r5900 */ \ - ) - -#define G2 (T3 \ -/* start-sanitize-tx49 */ \ - | T4 \ -/* end-sanitize-tx49 */ \ - ) - -#define G3 (I4 \ -/* start-sanitize-tx49 */ \ - | T4 \ -/* end-sanitize-tx49 */ \ -/* start-sanitize-r5900 */ \ - | T5 \ -/* end-sanitize-r5900 */ \ - ) - -/* The order of overloaded instructions matters. Label arguments and - register arguments look the same. Instructions that can have either - for arguments must apear in the correct order in this table for the - assembler to pick the right one. In other words, entries with - immediate operands must apear after the same instruction with - registers. - - Many instructions are short hand for other instructions (i.e., The - jal <register> instruction is short for jalr <register>). */ - -const struct mips_opcode mips_builtin_opcodes[] = { -/* These instructions appear first so that the disassembler will find - them first. The assemblers uses a hash table based on the - instruction name anyhow. */ -/* name, args, mask, match, pinfo */ -{"nop", "", 0x00000000, 0xffffffff, 0, I1 }, -{"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */ -{"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */ -{"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 }, -{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, I3 },/* daddu */ -{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, I1 },/* addu */ -{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1 },/* or */ -{"b", "p", 0x10000000, 0xffff0000, UBD, I1 },/* beq 0,0 */ -{"b", "p", 0x04010000, 0xffff0000, UBD, I1 },/* bgez 0 */ -{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, I1 },/* bgezal 0*/ - -/* start-sanitize-r5900 */ -{"cfc2.ni", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 }, -{"cfc2.i", "t,G", 0x48400001, 0xffe007ff, LCD|WR_t|RD_C2, I1 }, -{"ctc2.ni", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 }, -{"ctc2.i", "t,G", 0x48c00001, 0xffe007ff, COD|RD_t|WR_CC, I1 }, -{"lqc2", "1,o(b)", 0xd8000000, 0xfc000000, 0, T5}, -{"qmfc2", "t,2", 0x48200000, 0xffe007ff, 0, T5}, -{"qmfc2.ni", "t,2", 0x48200000, 0xffe007ff, 0, T5}, -{"qmfc2.i", "t,2", 0x48200001, 0xffe007ff, 0, T5}, -{"qmtc2", "t,2", 0x48a00000, 0xffe007ff, 0, T5}, -{"qmtc2.ni", "t,2", 0x48a00000, 0xffe007ff, 0, T5}, -{"qmtc2.i", "t,2", 0x48a00001, 0xffe007ff, 0, T5}, -{"sqc2", "1,o(b)", 0xf8000000, 0xfc000000, 0, T5}, -{"vabs", "&1K,2K", 0x4a0001fd, 0xfe0007ff, 0, T5}, -{"vadd", "&3K,2K,1K", 0x4a000028, 0xfe00003f, 0, T5}, -{"vaddi", "&3K,2K,J", 0x4a000022, 0xfe1f003f, 0, T5}, -{"vaddq", "&3K,2K,Q", 0x4a000020, 0xfe1f003f, 0, T5}, -{"vaddw", "&3K,2K,1#w", 0x4a000003, 0xfe00003f, 0, T5}, -{"vaddx", "&3K,2K,1#x", 0x4a000000, 0xfe00003f, 0, T5}, -{"vaddy", "&3K,2K,1#y", 0x4a000001, 0xfe00003f, 0, T5}, -{"vaddz", "&3K,2K,1#z", 0x4a000002, 0xfe00003f, 0, T5}, -{"vadda", "&UK,1K,2K", 0x4a0002bc, 0xfe0007ff, 0, T5}, -{"vaddai", "&UK,2K,J", 0x4a00023e, 0xfe1f07ff, 0, T5}, -{"vaddaq", "&UK,2K,Q", 0x4a00023c, 0xfe1f07ff, 0, T5}, -{"vaddaw", "&UK,2K,1#w", 0x4a00003f, 0xfe0007ff, 0, T5}, -{"vaddax", "&UK,2K,1#x", 0x4a00003c, 0xfe0007ff, 0, T5}, -{"vadday", "&UK,2K,1#y", 0x4a00003d, 0xfe0007ff, 0, T5}, -{"vaddaz", "&UK,2K,1#z", 0x4a00003e, 0xfe0007ff, 0, T5}, -{"vcallms","O", 0x4a000038, 0xffe0003f, 0, T5}, -{"vcallmsr", "9", 0x4a00d839, 0xffffffff, 0, T5}, -{"vclipw","&2K,1#w", 0x4a0001ff, 0xfe0007ff, 0, T5}, -{"vdiv","Q,8,7", 0x4a0003bc, 0xfe0007ff, 0, T5}, -{"vftoi0", "&1K,2K", 0x4a00017c, 0xfe0007ff, 0, T5}, -{"vftoi4", "&1K,2K", 0x4a00017d, 0xfe0007ff, 0, T5}, -{"vftoi12", "&1K,2K", 0x4a00017e, 0xfe0007ff, 0, T5}, -{"vftoi15", "&1K,2K", 0x4a00017f, 0xfe0007ff, 0, T5}, -{"viadd","6,5,4", 0x4a000030, 0xffe0003f, 0, T5}, -{"viaddi","4,5,0", 0x4a000032, 0xffe0003f, 0, T5}, -{"viand","6,5,4", 0x4a000034, 0xffe0003f, 0, T5}, -{"vilwr.w", "4,(5)", 0x4a2003fe, 0xffe007ff, 0, T5}, -{"vilwr.x", "4,(5)", 0x4b0003fe, 0xffe007ff, 0, T5}, -{"vilwr.y", "4,(5)", 0x4a8003fe, 0xffe007ff, 0, T5}, -{"vilwr.z", "4,(5)", 0x4a4003fe, 0xffe007ff, 0, T5}, -{"vior","6,5,4", 0x4a000035, 0xffe0003f, 0, T5}, -{"viswr.w", "4,(5)", 0x4a2003ff, 0xffe007ff, 0, T5}, -{"viswr.x", "4,(5)", 0x4b0003ff, 0xffe007ff, 0, T5}, -{"viswr.y", "4,(5)", 0x4a8003ff, 0xffe007ff, 0, T5}, -{"viswr.z", "4,(5)", 0x4a4003ff, 0xffe007ff, 0, T5}, -{"visub","6,5,4", 0x4a000031, 0xffe0003f, 0, T5}, -{"vitof0", "&1K,2K", 0x4a00013c, 0xfe0007ff, 0, T5}, -{"vitof4", "&1K,2K", 0x4a00013d, 0xfe0007ff, 0, T5}, -{"vitof12", "&1K,2K", 0x4a00013e, 0xfe0007ff, 0, T5}, -{"vitof15", "&1K,2K", 0x4a00013f, 0xfe0007ff, 0, T5}, -{"vlqd", "&1K,(--5)K", 0x4a00037e, 0xfe0007ff, 0, T5}, -{"vlqi", "&1K,(5++)K", 0x4a00037c, 0xfe0007ff, 0, T5}, -{"vmadd", "&3K,2K,1K", 0x4a000029, 0xfe00003f, 0, T5}, -{"vmaddi", "&3K,2K,J", 0x4a000023, 0xfe1f003f, 0, T5}, -{"vmaddq", "&3K,2K,Q", 0x4a000021, 0xfe1f003f, 0, T5}, -{"vmaddw", "&3K,2K,1#w", 0x4a00000b, 0xfe00003f, 0, T5}, -{"vmaddx", "&3K,2K,1#x", 0x4a000008, 0xfe00003f, 0, T5}, -{"vmaddy", "&3K,2K,1#y", 0x4a000009, 0xfe00003f, 0, T5}, -{"vmaddz", "&3K,2K,1#z", 0x4a00000a, 0xfe00003f, 0, T5}, -{"vmadda", "&UK,2K,1K", 0x4a0002bd, 0xfe0007ff, 0, T5}, -{"vmaddai", "&UK,2K,J", 0x4a00023f, 0xfe1f07ff, 0, T5}, -{"vmaddaq", "&UK,2K,Q", 0x4a00023d, 0xfe1f07ff, 0, T5}, -{"vmaddaw", "&UK,2K,1#w", 0x4a0000bf, 0xfe0007ff, 0, T5}, -{"vmaddax", "&UK,2K,1#x", 0x4a0000bc, 0xfe0007ff, 0, T5}, -{"vmadday", "&UK,2K,1#y", 0x4a0000bd, 0xfe0007ff, 0, T5}, -{"vmaddaz", "&UK,2K,1#z", 0x4a0000be, 0xfe0007ff, 0, T5}, -{"vmax", "&3K,2K,1K", 0x4a00002b, 0xfe00003f, 0, T5}, -{"vmaxi", "&3K,2K,J", 0x4a00001d, 0xfe1f003f, 0, T5}, -{"vmaxw", "&3K,2K,1#w", 0x4a000013, 0xfe00003f, 0, T5}, -{"vmaxx", "&3K,2K,1#x", 0x4a000010, 0xfe00003f, 0, T5}, -{"vmaxy", "&3K,2K,1#y", 0x4a000011, 0xfe00003f, 0, T5}, -{"vmaxz", "&3K,2K,1#z", 0x4a000012, 0xfe00003f, 0, T5}, -{"vmfir", "&1K,5", 0x4a0003fd, 0xfe0007ff, 0, T5}, -{"vmini", "&3K,2K,1K", 0x4a00002f, 0xfe00003f, 0, T5}, -{"vminii", "&3K,2K,J", 0x4a00001f, 0xfe1f003f, 0, T5}, -{"vminiw", "&3K,2K,1#w", 0x4a000017, 0xfe00003f, 0, T5}, -{"vminix", "&3K,2K,1#x", 0x4a000014, 0xfe00003f, 0, T5}, -{"vminiy", "&3K,2K,1#y", 0x4a000015, 0xfe00003f, 0, T5}, -{"vminiz", "&3K,2K,1#z", 0x4a000016, 0xfe00003f, 0, T5}, -{"vmove", "&1K,2K", 0x4a00033c, 0xfe0007ff, 0, T5}, -{"vmr32", "&1K,2K", 0x4a00033d, 0xfe0007ff, 0, T5}, -{"vmsub", "&3K,2K,1K", 0x4a00002d, 0xfe00003f, 0, T5}, -{"vmsubi", "&3K,2K,J", 0x4a000027, 0xfe1f003f, 0, T5}, -{"vmsubq", "&3K,2K,Q", 0x4a000025, 0xfe1f003f, 0, T5}, -{"vmsubw", "&3K,2K,1#w", 0x4a00000f, 0xfe00003f, 0, T5}, -{"vmsubx", "&3K,2K,1#x", 0x4a00000c, 0xfe00003f, 0, T5}, -{"vmsuby", "&3K,2K,1#y", 0x4a00000d, 0xfe00003f, 0, T5}, -{"vmsubz", "&3K,2K,1#z", 0x4a00000e, 0xfe00003f, 0, T5}, -{"vmsuba", "&UK,1K,2K", 0x4a0002fd, 0xfe0007ff, 0, T5}, -{"vmsubai", "&UK,2K,J", 0x4a00027f, 0xfe1f07ff, 0, T5}, -{"vmsubaq", "&UK,2K,Q", 0x4a00027d, 0xfe1f07ff, 0, T5}, -{"vmsubaw", "&UK,2K,1#w", 0x4a0000ff, 0xfe0007ff, 0, T5}, -{"vmsubax", "&UK,2K,1#x", 0x4a0000fc, 0xfe0007ff, 0, T5}, -{"vmsubay", "&UK,2K,1#y", 0x4a0000fd, 0xfe0007ff, 0, T5}, -{"vmsubaz", "&UK,2K,1#z", 0x4a0000fe, 0xfe0007ff, 0, T5}, -{"vmtir", "4,8", 0x4a0003fc, 0xff8007ff, 0, T5}, -{"vmul", "&3K,2K,1K", 0x4a00002a, 0xfe00003f, 0, T5}, -{"vmuli", "&3K,2K,J", 0x4a00001e, 0xfe1f003f, 0, T5}, -{"vmulq", "&3K,2K,Q", 0x4a00001c, 0xfe1f003f, 0, T5}, -{"vmulw", "&3K,2K,1#w", 0x4a00001b, 0xfe00003f, 0, T5}, -{"vmulx", "&3K,2K,1#x", 0x4a000018, 0xfe00003f, 0, T5}, -{"vmuly", "&3K,2K,1#y", 0x4a000019, 0xfe00003f, 0, T5}, -{"vmulz", "&3K,2K,1#z", 0x4a00001a, 0xfe00003f, 0, T5}, -{"vmula", "&UK,2K,1K", 0x4a0002be, 0xfe0007ff, 0, T5}, -{"vmulai", "&UK,2K,J", 0x4a0001fe, 0xfe1f07ff, 0, T5}, -{"vmulaq", "&UK,2K,Q", 0x4a0001fc, 0xfe1f07ff, 0, T5}, -{"vmulaw", "&UK,2K,1#w", 0x4a0001bf, 0xfe0007ff, 0, T5}, -{"vmulax", "&UK,2K,1#x", 0x4a0001bc, 0xfe0007ff, 0, T5}, -{"vmulay", "&UK,2K,1#y", 0x4a0001bd, 0xfe0007ff, 0, T5}, -{"vmulaz", "&UK,2K,1#z", 0x4a0001be, 0xfe0007ff, 0, T5}, -{"vnop","", 0x4a0002ff, 0xffffffff, 0, T5}, -{"vopmula", ";UK,2K,1K", 0x4bc002fe, 0xffe007ff, 0, T5}, -{"vopmsub", ";3K,2K,1K", 0x4bc0002e, 0xffe0003f, 0, T5}, -{"vrget", "&1K,X", 0x4a00043d, 0xfe00ffff, 0, T5}, -{"vrinit", "X,8", 0x4a00043e, 0xff9f07ff, 0, T5}, -{"vrnext", "&1K,X", 0x4a00043c, 0xfe00ffff, 0, T5}, -{"vrsqrt","Q,8,7", 0x4a0003be, 0xfe0007ff, 0, T5}, -{"vrxor", "X,8", 0x4a00043f, 0xff9f07ff, 0, T5}, -{"vsqd", "&2K,(--4)K", 0x4a00037f, 0xfe0007ff, 0, T5}, -{"vsqi", "&2K,(4++)K", 0x4a00037d, 0xfe0007ff, 0, T5}, -{"vsqrt", "Q,7", 0x4a2003bd, 0xfe60ffff, 0, T5}, -{"vsub", "&3K,2K,1K", 0x4a00002c, 0xfe00003f, 0, T5}, -{"vsubi", "&3K,2K,J", 0x4a000026, 0xfe1f003f, 0, T5}, -{"vsubq", "&3K,2K,Q", 0x4a000024, 0xfe1f003f, 0, T5}, -{"vsubw", "&3K,2K,1#w", 0x4a000007, 0xfe00003f, 0, T5}, -{"vsubx", "&3K,2K,1#x", 0x4a000004, 0xfe00003f, 0, T5}, -{"vsuby", "&3K,2K,1#y", 0x4a000005, 0xfe00003f, 0, T5}, -{"vsubz", "&3K,2K,1#z", 0x4a000006, 0xfe00003f, 0, T5}, -{"vsuba", "&UK,2K,1K", 0x4a0002fc, 0xfe0007ff, 0, T5}, -{"vsubai", "&UK,2K,J", 0x4a00027e, 0xfe1f07ff, 0, T5}, -{"vsubaq", "&UK,2K,Q", 0x4a00027c, 0xfe1f07ff, 0, T5}, -{"vsubaw", "&UK,2K,1#w", 0x4a00007f, 0xfe0007ff, 0, T5}, -{"vsubax", "&UK,2K,1#x", 0x4a00007c, 0xfe0007ff, 0, T5}, -{"vsubay", "&UK,2K,1#y", 0x4a00007d, 0xfe0007ff, 0, T5}, -{"vsubaz", "&UK,2K,1#z", 0x4a00007e, 0xfe0007ff, 0, T5}, -{"vwaitq","", 0x4a0003bf, 0xffffffff, 0, T5}, - -/* end-sanitize-r5900 */ -{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, I1 }, -{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, I1 }, -{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, I1 }, -{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, -{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, I1 }, -{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1}, -{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1}, -{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, I1 }, -{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, I1 }, -{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, -{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, I1 }, -{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, -{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, I1 }, -{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, I1 }, -/* b is at the top of the table. */ -/* bal is at the top of the table. */ -{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, I1 }, -{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, I2|T3 }, -{"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, I1 }, -{"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, I4 }, -{"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 }, -{"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, I4 }, -{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, I1 }, -{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, I2|T3 }, -{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, I1 }, -{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, I2|T3 }, -{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, I1 }, -{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, I2|T3 }, -{"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, I1 }, -{"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, I4 }, -{"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 }, -{"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, I4 }, -{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, I1 }, -{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, I2|T3 }, -{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, I1 }, -{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, I2|T3 }, -{"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, I1 }, -{"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, -{"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, I1 }, -{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, I1 }, -{"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 }, -{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, I2 }, -{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, I1 }, -{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, I1 }, -{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, I2 }, -{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, I2 }, -{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, I1 }, -{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, I1 }, -{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, I2 }, -{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, I2 }, -{"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, I1 }, -{"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, I2|T3 }, -{"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, I1 }, -{"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s, I2|T3 }, -{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, I1 }, -{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, I1 }, -{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, I2 }, -{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, I2 }, -{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, I1 }, -{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, I1 }, -{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, I2 }, -{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, I2 }, -{"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, I1 }, -{"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, -{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, I1 }, -{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, I1 }, -{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, I2 }, -{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, I2 }, -{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, I1 }, -{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, I1 }, -{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, I2 }, -{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, I2 }, -{"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, I1 }, -{"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, -{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, I1 }, -{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, I1 }, -{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, I2 }, -{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, I2 }, -{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, I1 }, -{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, I1 }, -{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, I2 }, -{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, I2 }, -{"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, I1 }, -{"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, I2|T3 }, -{"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, I1 }, -{"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s, I2|T3 }, -{"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, I1 }, -{"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, -{"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, I1 }, -{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, I1 }, -{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 }, -{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, I2 }, -{"break", "", 0x0000000d, 0xffffffff, TRAP, I1 }, -/* start-sanitize-r5900 */ -{"break", "B", 0x0000000d, 0xfc00003f, TRAP, T5 }, -/* end-sanitize-r5900 */ -{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, I1 }, -{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, I1 }, -{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, -{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, -{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, -{"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, -{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, -{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, -{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, -{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, -{"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, -{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, -{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, -{"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, -{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, -{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, -{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, -{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, -{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, -{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, -{"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, -{"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, -{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, -{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, -{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, -{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, -{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, -{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, -{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, -{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, -{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, -{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, -{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, -{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, -{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|T3 }, -{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3 }, -{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3 }, -{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, I2 }, -{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, I2 }, -{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, I1 }, -{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 }, -{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 }, -{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 }, -{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 }, - /* start-sanitize-vr4320 */ -{"clz", "d,s", 0x00000035, 0xfc1f07ff, WR_d|RD_s, N4 }, - /* end-sanitize-vr4320 */ -{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 }, -{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 }, -{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 }, -{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 }, -{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, I1 }, -{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, I3 }, -{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_D|FP_S, I1 }, -{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_D, I1 }, -{"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, I3 }, -{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S, I3 }, -{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S, I3 }, -{"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I1 }, -{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, I1 }, -{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_D, I1 }, -{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, I1 }, -{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, I3 }, -{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, -{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, I3 }, -{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, I3 }, -{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, I3 }, -{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, -{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, I3 }, - /* start-sanitize-cygnus */ -{"dbreak", "", 0x7000003f, 0xffffffff, 0, N5 }, - /* end-sanitize-cygnus */ - /* start-sanitize-vr4320 */ -{"dclz", "d,s", 0x0000003D, 0xfc1f07ff, WR_d|RD_s, N4 }, - /* end-sanitize-vr4320 */ -/* dctr and dctw are used on the r5000. */ -{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, I3 }, -{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, I3 }, -{"deret", "", 0x4200001f, 0xffffffff, 0, G2 }, -/* For ddiv, see the comments about div. */ -{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 }, -{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, I3 }, -{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, I3 }, -/* For ddivu, see the comments about div. */ -{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 }, -{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, I3 }, -{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, I3 }, -/* The MIPS assembler treats the div opcode with two operands as - though the first operand appeared twice (the first operand is both - a source and a destination). To get the div machine instruction, - you must use an explicit destination of $0. */ -{"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 }, -{"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HI|WR_LO, I1 }, -{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, I1 }, -{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, I1 }, - /* start-sanitize-r5900 */ -{"div1", "s,t", 0x7000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 }, - /* end-sanitize-r5900 */ -{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, -{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, -/* For divu, see the comments about div. */ -{"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 }, -{"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HI|WR_LO, I1 }, -{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, I1 }, -{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, I1 }, - /* start-sanitize-r5900 */ -{"divu1", "s,t", 0x7000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 }, - /* end-sanitize-r5900 */ -{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, I3 }, -{"dli", "t,j", 0x24000000, 0xffe00000, WR_t, I3 }, /* addiu */ -{"dli", "t,i", 0x34000000, 0xffe00000, WR_t, I3 }, /* ori */ -{"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, I3 }, -{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|WR_LO|RD_LO, V1 }, -{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, I3 }, -{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I3 }, -{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 }, -{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 }, -{"dmfc2", "t,S", 0x48200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 }, -{"dmtc2", "t,S", 0x48a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 }, -{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, I3 }, -{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, I3 }, -{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, I3 }, -{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, I3 }, -{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, I3 }, -{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, I3 }, -{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3}, - /* start-sanitize-tx49 */ -{"dmult", "d,s,t", 0x0000001c, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T4}, - /* end-sanitize-tx49 */ -{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3}, - /* start-sanitize-tx49 */ -{"dmultu", "d,s,t", 0x0000001d, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T4}, - /* end-sanitize-tx49 */ -{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, I3 }, /* dsub 0 */ -{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, I3 }, /* dsubu 0*/ -{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 }, -{"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, I3 }, -{"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, I3 }, -{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 }, -{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 }, -{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 }, - /* start-sanitize-cygnus */ -{"dret", "", 0x7000003e, 0xffffffff, 0, N5 }, -{"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, N5 }, -{"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, N5 }, -{"dror", "d,w,>", 0x0020003e, 0xffe0003f, WR_d|RD_t, N5 }, -{"dror", "d,w,<", 0x00200036, 0xffe0003f, WR_d|RD_t, N5 }, - /* end-sanitize-cygnus */ -{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, -{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 }, -{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */ -{"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 }, /* dsll32 */ -{"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, I3 }, -{"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, -{"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 }, -{"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrav */ -{"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 }, /* dsra32 */ -{"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, I3 }, -{"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, -{"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 }, -{"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrlv */ -{"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 }, /* dsrl32 */ -{"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, I3 }, -{"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, -{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, I3 }, -{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, -{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, I3 }, -{"eret", "", 0x42000018, 0xffffffff, 0, I3 }, -{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3 }, -{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3 }, -{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, I2 }, -{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, I2 }, -{"flushi", "", 0xbc010000, 0xffffffff, 0, L1 }, -{"flushd", "", 0xbc020000, 0xffffffff, 0, L1 }, -{"flushid", "", 0xbc030000, 0xffffffff, 0, L1 }, -{"hibernate","", 0x42000023, 0xffffffff, 0, V1 }, -{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 }, -{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 }, /* jr */ -/* SVR4 PIC code requires special handling for j, so it must be a - macro. */ -{"j", "a", 0, (int) M_J_A, INSN_MACRO, I1 }, -/* This form of j is used by the disassembler and internally by the - assembler, but will never match user input (because the line above - will match first). */ -{"j", "a", 0x08000000, 0xfc000000, UBD, I1 }, -{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, I1 }, -{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, I1 }, -/* SVR4 PIC code requires special handling for jal, so it must be a - macro. */ -{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, I1 }, -{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, I1 }, -{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, I1 }, -/* This form of jal is used by the disassembler and internally by the - assembler, but will never match user input (because the line above - will match first). */ -{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, I1 }, - /* jalx really should only be avaliable if mips16 is available, - but for now make it I1. */ -{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, I1 }, -{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, I1 }, -{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, -{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, I1 }, -{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, -{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, I1 }, -{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, I3 }, -{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, I1 }, -{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, I1 }, -{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, -{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, -{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 }, -{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 }, -{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, /* ldc1 */ -{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, I1 }, -{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, I1 }, -{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, I2 }, -{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, I2 }, -{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, I2 }, -{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, I2 }, -{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, I3 }, -{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, I3 }, -{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, I3 }, -{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, I3 }, -{"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 }, -{"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, -{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, I1 }, -{"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, -{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, I1 }, -/* li is at the start of the table. */ -{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, I1 }, -{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, I1 }, -{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, I1 }, -{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, I1 }, -{"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, -{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, I2 }, -{"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, I3 }, -{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, I3 }, -{"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, I1 }, - /* start-sanitize-r5900 */ -{"lq", "t,o(b)", 0x78000000, 0xfc000000, WR_t|RD_b, T5 }, - /* end-sanitize-r5900 */ -{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, -{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, I1 }, -{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, I1 }, -{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, I1 }, -{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, -{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, -{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 }, -{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 }, -{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, /* lwc1 */ -{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 }, -{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, I1 }, -{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, I1 }, -{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, I1 }, -{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, I1 }, -{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, -{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I1 }, -{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */ -{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I2 }, /* as lwl */ -{"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, -{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I1 }, -{"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */ -{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I2 }, /* as lwr */ -{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, I3 }, -{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, I3 }, -{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 }, - /* start-sanitize-vr4320 */ -{"mac", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, N4}, -{"dmac", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, N4}, - /* end-sanitize-vr4320 */ - /* start-sanitize-vr4320 */ -{"macc", "d,s,t", 0x000000A8, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N4}, - /* end-sanitize-vr4320 */ - /* start-sanitize-cygnus */ -{"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,N5}, - /* end-sanitize-cygnus */ - /* start-sanitize-vr4320 */ -{"maccu", "d,s,t", 0x000000E8, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N4}, - /* end-sanitize-vr4320 */ - /* start-sanitize-cygnus */ -{"maccu", "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,N5}, - /* end-sanitize-cygnus */ - /* start-sanitize-vr4320 */ -{"macchi", "d,s,t", 0x000002A8, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N4}, - /* end-sanitize-vr4320 */ - /* start-sanitize-cygnus */ -{"macchi", "d,s,t", 0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,N5}, - /* end-sanitize-cygnus */ - /* start-sanitize-vr4320 */ -{"macchiu", "d,s,t", 0x000002E8, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N4}, - /* end-sanitize-vr4320 */ - /* start-sanitize-cygnus */ -{"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,N5}, - /* end-sanitize-cygnus */ -{"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 }, -{"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 }, -{"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, -{"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, -/* start-sanitize-r5900 */ -{"madd.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, T5 }, - /* end-sanitize-r5900 */ -{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 }, -{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, G1 }, -{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1 }, - /* start-sanitize-r5900 */ -{"madd1", "s,t", 0x70000020, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 }, -{"madd1", "d,s,t", 0x70000020, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5 }, - /* end-sanitize-r5900 */ -{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 }, -{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, G1}, -{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1}, - /* start-sanitize-r5900 */ -{"maddu1", "s,t", 0x70000021, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 }, -{"maddu1", "d,s,t", 0x70000021, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5 }, -{"adda.s", "S,T", 0x46000018, 0xffe007ff, RD_S|RD_T|FP_S, T5 }, -{"madda.s", "S,T", 0x4600001e, 0xffe007ff, RD_S|RD_T|FP_S, T5 }, -{"max.s", "D,S,T", 0x46000028, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, T5 }, -{"min.s", "D,S,T", 0x46000029, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, T5 }, -{"msuba.s", "S,T", 0x4600001f, 0xffe007ff, RD_S|RD_T|FP_S, T5 }, -{"mula.s", "S,T", 0x4600001a, 0xffe007ff, RD_S|RD_T|FP_S, T5 }, -{"suba.s", "S,T", 0x46000019, 0xffe007ff, RD_S|RD_T|FP_S, T5 }, -{"di", "", 0x42000039, 0xffffffff, WR_C0, T5 }, -{"ei", "", 0x42000038, 0xffffffff, WR_C0, T5 }, -{"mfbpc", "t", 0x4000c000, 0xffe0ffff, RD_C0|WR_t, T5 }, -{"mfdab", "t", 0x4000c004, 0xffe0ffff, RD_C0|WR_t, T5 }, -{"mfdabm", "t", 0x4000c005, 0xffe0ffff, RD_C0|WR_t, T5 }, -{"mfdvb", "t", 0x4000c006, 0xffe0ffff, RD_C0|WR_t, T5 }, -{"mfdvbm", "t", 0x4000c007, 0xffe0ffff, RD_C0|WR_t, T5 }, -{"mfiab", "t", 0x4000c002, 0xffe0ffff, RD_C0|WR_t, T5 }, -{"mfiabm", "t", 0x4000c003, 0xffe0ffff, RD_C0|WR_t, T5 }, -{"mtbpc", "t", 0x4080c000, 0xffe0ffff, WR_C0|RD_t, T5 }, -{"mtdab", "t", 0x4080c004, 0xffe0ffff, WR_C0|RD_t, T5 }, -{"mtdabm", "t", 0x4080c005, 0xffe0ffff, WR_C0|RD_t, T5 }, -{"mtdvb", "t", 0x4080c006, 0xffe0ffff, WR_C0|RD_t, T5 }, -{"mtdvbm", "t", 0x4080c007, 0xffe0ffff, WR_C0|RD_t, T5 }, -{"mtiab", "t", 0x4080c002, 0xffe0ffff, WR_C0|RD_t, T5 }, -{"mtiabm", "t", 0x4080c003, 0xffe0ffff, WR_C0|RD_t, T5 }, - /* end-sanitize-r5900 */ -{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, V1 }, - /* start-sanitize-cygnus */ -{"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, RD_C0|WR_t, N5 }, - /* end-sanitize-cygnus */ - /* start-sanitize-r5900 */ -{"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, RD_C0|WR_t, T5 }, - /* end-sanitize-r5900 */ - /* start-sanitize-cygnus */ -{"mfps", "t,P", 0x4000c800, 0xffe0ffc1, RD_C0|WR_t, N5 }, - /* end-sanitize-cygnus */ - /* start-sanitize-r5900 */ -{"mfps", "t,P", 0x4000c800, 0xffe0ffc1, RD_C0|WR_t, T5 }, - /* end-sanitize-r5900 */ - /* start-sanitize-cygnus */ -{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, WR_C0|RD_t, N5 }, - /* end-sanitize-cygnus */ - /* start-sanitize-r5900 */ -{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, WR_C0|RD_t, T5 }, - /* end-sanitize-r5900 */ - /* start-sanitize-cygnus */ -{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, WR_C0|RD_t, N5 }, - /* end-sanitize-cygnus */ - /* start-sanitize-r5900 */ -{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, WR_C0|RD_t, T5 }, - /* end-sanitize-r5900 */ -{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 }, -{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 }, -{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 }, -{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 }, -{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 }, - /* start-sanitize-cygnus */ -{"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, N5 }, - /* end-sanitize-cygnus */ -{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 }, - /* start-sanitize-r5900 */ -{"mfhi1", "d", 0x70000010, 0xffff07ff, WR_d|RD_HI, T5 }, - /* end-sanitize-r5900 */ -{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, I1 }, - /* start-sanitize-r5900 */ -{"mflo1", "d", 0x70000012, 0xffff07ff, WR_d|RD_LO, T5 }, -{"mfsa", "d", 0x00000028, 0xffff07ff, WR_d, T5 }, - /* end-sanitize-r5900 */ -{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1 }, -{"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, I1 }, -{"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4 }, -{"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4 }, -{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4 }, -{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4 }, - /* start-sanitize-r5900 */ -{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, - /* end-sanitize-r5900 */ -{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s,L1 }, -{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4 }, -{"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4 }, -{"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC, I4 }, -{"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4 }, -{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4 }, -{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4 }, - /* start-sanitize-r5900 */ -{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, - /* end-sanitize-r5900 */ -{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s,L1 }, -{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4 }, -{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4 }, - /* start-sanitize-cygnus */ -{"msac", "d,s,t", 0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 }, -{"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 }, -{"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 }, -{"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 }, - /* end-sanitize-cygnus */ -/* move is at the top of the table. */ -{"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, -{"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, -/* start-sanitize-r5900 */ -{"msub.s", "D,S,T", 0x4600001d, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, T5 }, -/* end-sanitize-r5900 */ -{"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1 }, -{"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1 }, -{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I1 }, -{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 }, -{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 }, -{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 }, -{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 }, - /* start-sanitize-cygnus */ -{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, N5 }, - /* end-sanitize-cygnus */ -{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, I1 }, - /* start-sanitize-r5900 */ -{"mthi1", "s", 0x70000011, 0xfc1fffff, RD_s|WR_HI, T5 }, - /* end-sanitize-r5900 */ -{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, I1 }, - /* start-sanitize-r5900 */ -{"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_s|WR_LO, T5 }, -{"mtsa", "s", 0x00000029, 0xfc1fffff, RD_s, T5 }, -{"mtsab", "s,j", 0x04180000, 0xfc1f0000, RD_s, T5 }, -{"mtsah", "s,j", 0x04190000, 0xfc1f0000, RD_s, T5 }, - /* end-sanitize-r5900 */ -{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, -{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, -{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,P3}, - /* start-sanitize-vr4320 */ -{"mul", "d,s,t", 0x00000128, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N4}, - /* end-sanitize-vr4320 */ - /* start-sanitize-cygnus */ -{"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5}, - /* end-sanitize-cygnus */ -{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, I1 }, -{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, I1 }, -{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, I1 }, -{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, I1 }, -{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, I1 }, -{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, I1 }, - /* start-sanitize-vr4320 */ -{"mulu", "d,s,t", 0x00000168, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N4}, - /* end-sanitize-vr4320 */ - /* start-sanitize-cygnus */ -{"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5}, - /* end-sanitize-cygnus */ - /* start-sanitize-vr4320 */ -{"mulhi", "d,s,t", 0x00000328, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N4}, - /* end-sanitize-vr4320 */ - /* start-sanitize-cygnus */ -{"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5}, - /* end-sanitize-cygnus */ - /* start-sanitize-vr4320 */ -{"mulhiu", "d,s,t", 0x00000368, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N4}, - /* end-sanitize-vr4320 */ - /* start-sanitize-cygnus */ -{"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5}, - /* end-sanitize-cygnus */ - /* start-sanitize-cygnus */ -{"muls", "d,s,t", 0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 }, -{"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 }, -{"mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 }, -{"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 }, - /* end-sanitize-cygnus */ -{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, I1}, -{"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1}, - /* start-sanitize-r5900 */ -{"mult1", "s,t", 0x70000018, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5}, -{"mult1", "d,s,t", 0x70000018, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5}, - /* end-sanitize-r5900 */ -{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, I1}, -{"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1}, - /* start-sanitize-r5900 */ -{"multu1", "s,t", 0x70000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5}, -{"multu1", "d,s,t", 0x70000019, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5}, - /* end-sanitize-r5900 */ -{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, I1 }, /* sub 0 */ -{"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, I1 }, /* subu 0 */ -{"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, I1 }, -{"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, I1 }, -{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, -{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, -{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, -{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, -/* nop is at the start of the table. */ -{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, -{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, I1 }, -{"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, I1 },/*nor d,s,0*/ -{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, -{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, I1 }, -{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, I1 }, - - /* start-sanitize-r5900 */ -{"pabsh", "d,t", 0x70000168, 0xffe007ff, WR_d|RD_t, T5 }, -{"pabsw", "d,t", 0x70000068, 0xffe007ff, WR_d|RD_t, T5 }, -{"paddb", "d,v,t", 0x70000208, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"paddh", "d,v,t", 0x70000108, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"paddw", "d,v,t", 0x70000008, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"paddsb", "d,v,t", 0x70000608, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"paddsh", "d,v,t", 0x70000508, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"paddsw", "d,v,t", 0x70000408, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"paddub", "d,v,t", 0x70000628, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"padduh", "d,v,t", 0x70000528, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"padduw", "d,v,t", 0x70000428, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"padsbh", "d,v,t", 0x70000128, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"pand", "d,v,t", 0x70000489, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"pceqb", "d,v,t", 0x700002a8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"pceqh", "d,v,t", 0x700001a8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"pceqw", "d,v,t", 0x700000a8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, - -{"pcgtb", "d,v,t", 0x70000288, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"pcgth", "d,v,t", 0x70000188, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"pcgtw", "d,v,t", 0x70000088, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, - -{"pcpyh", "d,t", 0x700006e9, 0xffe007ff, WR_d|RD_t, T5 }, - -{"pcpyld", "d,v,t", 0x70000389, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"pcpyud", "d,v,t", 0x700003a9, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, - -{"pdivbw", "s,t", 0x70000749, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 }, -{"pdivuw", "s,t", 0x70000369, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 }, -{"pdivw", "s,t", 0x70000349, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 }, - -{"pexch", "d,t", 0x700006a9, 0xffe007ff, WR_d|RD_t, T5 }, -{"pexcw", "d,t", 0x700007a9, 0xffe007ff, WR_d|RD_t, T5 }, -{"pexeh", "d,t", 0x70000689, 0xffe007ff, WR_d|RD_t, T5 }, -{"pexoh", "d,t", 0x70000689, 0xffe007ff, WR_d|RD_t, T5 }, -{"pexew", "d,t", 0x70000789, 0xffe007ff, WR_d|RD_t, T5 }, -{"pexow", "d,t", 0x70000789, 0xffe007ff, WR_d|RD_t, T5 }, - -{"pext5", "d,t", 0x70000788, 0xffe007ff, WR_d|RD_t, T5 }, - -{"pextlb", "d,v,t", 0x70000688, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"pextlh", "d,v,t", 0x70000588, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"pextlw", "d,v,t", 0x70000488, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"pextub", "d,v,t", 0x700006a8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"pextuh", "d,v,t", 0x700005a8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"pextuw", "d,v,t", 0x700004a8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, - -{"phmadh", "d,v,t", 0x70000449, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 }, -{"phmsbh", "d,v,t", 0x70000549, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 }, -{"phmaddh", "d,v,t", 0x70000449, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 }, -{"phmsubh", "d,v,t", 0x70000549, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 }, - -{"pinth", "d,v,t", 0x70000289, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"pinteh", "d,v,t", 0x700002a9, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"pintoh", "d,v,t", 0x700002a9, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, - -{"plzcw", "d,v", 0x70000004, 0xfc1f07ff, WR_d|RD_s, T5 }, - -{"pmaddh", "d,v,t", 0x70000409, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 }, -{"pmadduw", "d,v,t", 0x70000029, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 }, -{"pmaddw", "d,v,t", 0x70000009, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 }, - -{"pmaxh", "d,v,t", 0x700001c8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"pmaxw", "d,v,t", 0x700000c8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, - -{"pmfhi", "d", 0x70000209, 0xffff07ff, WR_d|RD_HI, T5 }, -{"pmflo", "d", 0x70000249, 0xffff07ff, WR_d|RD_LO, T5 }, - -{"pmfhl.lw", "d", 0x70000030, 0xffff07ff, WR_d|RD_LO|RD_HI, T5 }, -{"pmfhl.uw", "d", 0x70000070, 0xffff07ff, WR_d|RD_LO|RD_HI, T5 }, -{"pmfhl.slw","d", 0x700000b0, 0xffff07ff, WR_d|RD_LO|RD_HI, T5 }, -{"pmfhl.lh", "d", 0x700000f0, 0xffff07ff, WR_d|RD_LO|RD_HI, T5 }, -{"pmfhl.sh", "d", 0x70000130, 0xffff07ff, WR_d|RD_LO|RD_HI, T5 }, - -{"pminh", "d,v,t", 0x700001e8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"pminw", "d,v,t", 0x700000e8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, - -{"pmsubh", "d,v,t", 0x70000509, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 }, -{"pmsubw", "d,v,t", 0x70000109, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 }, - -{"pmthi", "v", 0x70000229, 0xfc1fffff, WR_HI|RD_s, T5 }, -{"pmtlo", "v", 0x70000269, 0xfc1fffff, WR_LO|RD_s, T5 }, - -{"pmthl.lw", "v", 0x70000031, 0xfc1fffff, WR_HI|WR_LO|RD_s, T5 }, - -{"pmulth", "d,v,t", 0x70000709, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 }, -{"pmultuw", "d,v,t", 0x70000329, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 }, -{"pmultw", "d,v,t", 0x70000309, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, T5 }, - -{"pnor", "d,v,t", 0x700004e9, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"por", "d,v,t", 0x700004a9, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, - -{"ppac5", "d,t", 0x700007c8, 0xffe007ff, WR_d|RD_t, T5 }, - -{"ppacb", "d,v,t", 0x700006c8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"ppach", "d,v,t", 0x700005c8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"ppacw", "d,v,t", 0x700004c8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, - -{"prevh", "d,t", 0x700006c9, 0xffe007ff, WR_d|RD_t, T5 }, -{"prot3w", "d,t", 0x700007c9, 0xffe007ff, WR_d|RD_t, T5 }, - -{"psllh", "d,t,<", 0x70000034, 0xffe0003f, WR_d|RD_t, T5 }, -{"psllvw", "d,t,s", 0x70000089, 0xfc0007ff, WR_d|RD_t|RD_s, T5 }, -{"psllw", "d,t,<", 0x7000003c, 0xffe0003f, WR_d|RD_t, T5 }, - -{"psrah", "d,t,<", 0x70000037, 0xffe0003f, WR_d|RD_t, T5 }, -{"psravw", "d,t,s", 0x700000e9, 0xfc0007ff, WR_d|RD_t|RD_s, T5 }, -{"psraw", "d,t,<", 0x7000003f, 0xffe0003f, WR_d|RD_t, T5 }, - -{"psrlh", "d,t,<", 0x70000036, 0xffe0003f, WR_d|RD_t, T5 }, -{"psrlvw", "d,t,s", 0x700000c9, 0xfc0007ff, WR_d|RD_t|RD_s, T5 }, -{"psrlw", "d,t,<", 0x7000003e, 0xffe0003f, WR_d|RD_t, T5 }, - -{"psubb", "d,v,t", 0x70000248, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"psubh", "d,v,t", 0x70000148, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"psubsb", "d,v,t", 0x70000648, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"psubsh", "d,v,t", 0x70000548, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"psubsw", "d,v,t", 0x70000448, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"psubub", "d,v,t", 0x70000668, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"psubuh", "d,v,t", 0x70000568, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"psubuw", "d,v,t", 0x70000468, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, -{"psubw", "d,v,t", 0x70000048, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, - -{"pxor", "d,v,t", 0x700004c9, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, - /* end-sanitize-r5900 */ - -{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, G3 }, -{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 }, - - /* start-sanitize-r5900 */ -{"qfsrv", "d,v,t", 0x700006e8, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, - /* end-sanitize-r5900 */ - -{"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, I4 }, -{"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, I4 }, -{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 }, -{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, I1 }, -{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, I1 }, -{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 }, -{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, I1 }, -{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, I1 }, -{"rfe", "", 0x42000010, 0xffffffff, 0, I1|T3 }, -{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, I1 }, -{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, I1 }, - /* start-sanitize-cygnus */ -{"ror", "d,t,<", 0x00200002, 0xffe0003f, WR_d|RD_t, N5 }, - /* end-sanitize-cygnus */ -{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, I1 }, -{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, I1 }, - /* start-sanitize-cygnus */ -{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, N5 }, - /* end-sanitize-cygnus */ -{"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, I3 }, -{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S, I3 }, -{"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_D, I2 }, -{"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, I2 }, -{"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, I4 }, -{"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, I4 }, -/* start-sanitize-r5900 */ -{"rsqrt.s", "D,S,T", 0x46000016, 0xffe0003f, WR_D|RD_S|FP_S, T5 }, -/* end-sanitize-r5900 */ -{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, I1 }, -{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, I1 }, -{"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I2 }, -{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, I2 }, -{"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I3 }, -{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, I3 }, -{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, I3 }, -{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, I1 }, -{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, I1 }, -{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, G2 }, -{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, G2 }, -{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, G2 }, -{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 }, -{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 }, -{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 }, -{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 }, -{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, I2 }, -{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, I2 }, -{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, I2 }, -{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, I2 }, -{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 }, -{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, I1 }, -{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, I1 }, -{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, I3 }, -{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, I3 }, -{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, I3 }, -{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, I3 }, -{"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 }, -{"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t,L1 }, -{"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t,L1 }, -{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, I1 }, -{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, I1 }, -{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, I1 }, -{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, I1 }, -{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, I1 }, -{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, I1 }, -{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, I1 }, -{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, I1 }, -{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, I1 }, -{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, I1 }, -{"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, I1 }, -{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, I1 }, -{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, I1 }, -{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, I1 }, -{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, I1 }, -{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, I1 }, -{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, -{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* sllv */ -{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, I1 }, -{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, -{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, I1 }, -{"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, I1 }, -{"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, I1 }, -{"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, -{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, I1 }, -{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, I1 }, -{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, I1 }, - /* start-sanitize-r5900 */ -{"sq", "t,o(b)", 0x7c000000, 0xfc000000, SM|RD_t|RD_b, T5 }, - /* end-sanitize-r5900 */ -{"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, I2 }, -/* start-sanitize-r5900 */ -{"sqrt.s", "D,T", 0x46000004, 0xffe0f83f, WR_D|RD_S|FP_S, T5 }, -/* end-sanitize-r5900 */ -{"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, I2 }, -{"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, -{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srav */ -{"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, I1 }, -{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, -{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srlv */ -{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, I1 }, -{"standby", "", 0x42000021, 0xffffffff, 0, V1 }, -{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, -{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, I1 }, -{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, -{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, -{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, -{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, I1 }, -{"suspend", "", 0x42000022, 0xffffffff, 0, V1 }, -{"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, I1 }, -{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, I1 }, -{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, I1 }, -{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, I1 }, -{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, -{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, -{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 }, -{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 }, -{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, /* swc1 */ -{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 }, -{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, I1 }, -{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, I1 }, -{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, I1 }, -{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, I1 }, -{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, I1 }, -{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, I1 }, -{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */ -{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, I2 }, /* as swl */ -{"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, I1 }, -{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, I1 }, -{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */ -{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, I2 }, /* as swr */ -{"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 }, -{"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, I2|G1 }, -{"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, I2 }, -{"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, I2 }, -{"syscall", "", 0x0000000c, 0xffffffff, TRAP, I1 }, -{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, I1 }, -{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 }, -{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, -{"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, -{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* teqi */ -{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, I2 }, -{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 }, -{"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, -{"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, -{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgei */ -{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, I2 }, -{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 }, -{"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, -{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, -{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgeiu */ -{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, I2 }, -{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, I1 }, -{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, I1 }, -{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, I1 }, -{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, I1 }, -{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 }, -{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, -{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, -{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tlti */ -{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, I2 }, -{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 }, -{"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, -{"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, -{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tltiu */ -{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, I2 }, -{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 }, -{"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, -{"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, -{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tnei */ -{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, I2 }, -{"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, I3 }, -{"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S, I3 }, -{"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 }, -{"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 }, -{"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, I1 }, -{"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 }, -{"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 }, -{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, I1 }, -{"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, I3 }, -{"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, I3 }, -{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, I1 }, -{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, I1 }, -{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, I1 }, -{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, I1 }, -{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, I1 }, -{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, I1 }, -{"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, I3 }, -{"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, I3 }, -{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, I1 }, -{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, I1 }, -{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, I1 }, -{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, I1 }, -{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, -{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 }, -{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 }, -{"wait", "", 0x42000020, 0xffffffff, TRAP, I3 }, -{"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 }, -{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 }, - /* start-sanitize-cygnus */ -{"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"add.ob", "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T, N5 }, -{"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, N5 }, -{"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, N5 }, -{"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, N5 }, -{"c.eq.ob", "S,T[e]", 0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, N5 }, -{"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, N5 }, -{"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, N5 }, -{"c.le.ob", "S,T[e]", 0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, N5 }, -{"c.le.ob", "S,k", 0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, N5 }, -{"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, N5 }, -{"c.lt.ob", "S,T[e]", 0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, N5 }, -{"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, N5 }, -{"max.ob", "D,S,T", 0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"max.ob", "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T, N5 }, -{"max.ob", "D,S,k", 0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, N5 }, -{"min.ob", "D,S,k", 0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"mul.ob", "D,S,T", 0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"mul.ob", "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T, N5 }, -{"mul.ob", "D,S,k", 0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"mula.ob", "S,T", 0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T, N5 }, -{"mula.ob", "S,T[e]", 0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T, N5 }, -{"mula.ob", "S,k", 0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, N5 }, -{"mull.ob", "S,T", 0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T, N5 }, -{"mull.ob", "S,T[e]", 0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T, N5 }, -{"mull.ob", "S,k", 0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, N5 }, -{"muls.ob", "S,T", 0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T, N5 }, -{"muls.ob", "S,T[e]", 0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T, N5 }, -{"muls.ob", "S,k", 0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, N5 }, -{"mulsl.ob","S,T", 0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T, N5 }, -{"mulsl.ob","S,T[e]", 0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T, N5 }, -{"mulsl.ob","S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, N5 }, -{"nor.ob", "D,S,T", 0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"nor.ob", "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T, N5 }, -{"nor.ob", "D,S,k", 0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"or.ob", "D,S,T", 0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"or.ob", "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T, N5 }, -{"or.ob", "D,S,k", 0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"pickf.ob", "D,S,T", 0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"pickf.ob", "D,S,T[e]", 0x48000002, 0xfe20003f, WR_D|RD_S|RD_T, N5 }, -{"pickf.ob", "D,S,k", 0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"pickt.ob", "D,S,T", 0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"pickt.ob", "D,S,T[e]", 0x48000003, 0xfe20003f, WR_D|RD_S|RD_T, N5 }, -{"pickt.ob", "D,S,k", 0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, N5 }, -{"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, N5 }, -{"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, N5 }, -{"rzu.ob", "D,k", 0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, N5 }, -{"shfl.mixh.ob","D,S,T",0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"shfl.mixl.ob","D,S,T",0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"shfl.pach.ob","D,S,T",0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"shfl.pacl.ob","D,S,T",0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"sll.ob", "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T, N5 }, -{"sll.ob", "D,S,k", 0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"srl.ob", "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T, N5 }, -{"srl.ob", "D,S,k", 0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"sub.ob", "D,S,T", 0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"sub.ob", "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T, N5 }, -{"sub.ob", "D,S,k", 0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, N5 }, -{"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T, N5 }, -{"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, -{"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, N5 }, -{"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, N5 }, - /* end-sanitize-cygnus */ -/* No hazard protection on coprocessor instructions--they shouldn't - change the state of the processor and if they do it's up to the - user to put in nops as necessary. These are at the end so that the - disasembler recognizes more specific versions first. */ -{"c0", "C", 0x42000000, 0xfe000000, 0, I1 }, -{"c1", "C", 0x46000000, 0xfe000000, 0, I1 }, -{"c2", "C", 0x4a000000, 0xfe000000, 0, I1 }, -{"c3", "C", 0x4e000000, 0xfe000000, 0, I1 }, -{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, I1 }, -{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, I1 }, -{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, I1 }, -{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, I1 }, - - /* Conflicts with the 4650's "mul" instruction. Nobody's using the - 4010 any more, so move this insn out of the way. If the object - format gave us more info, we could do this right. */ -{"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s,L1 }, -}; - -#define MIPS_NUM_OPCODES \ - ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0]))) -const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES; - -/* const removed from the following to allow for dynamic extensions to the - * built-in instruction set. */ -struct mips_opcode *mips_opcodes = - (struct mips_opcode *) mips_builtin_opcodes; -int bfd_mips_num_opcodes = MIPS_NUM_OPCODES; -#undef MIPS_NUM_OPCODES - diff --git a/opcodes/mpw-config.in b/opcodes/mpw-config.in deleted file mode 100644 index ff9be9d72f4..00000000000 --- a/opcodes/mpw-config.in +++ /dev/null @@ -1,27 +0,0 @@ -# Configuration fragment for opcodes. - -Set target_arch `echo {target_canonical} | sed -e 's/-.*-.*//'` - -Set archname ARCH_{target_arch} - -If "{target_arch}" =~ /m68k/ - Set BFD_MACHINES '"{o}"m68k-dis.c.o "{o}"m68k-opc.c.o' -Else If "{target_arch}" =~ /powerpc/ - Set BFD_MACHINES '"{o}"ppc-dis.c.o "{o}"ppc-opc.c.o' -Else If "{target_arch}" =~ /i386/ - Set BFD_MACHINES '"{o}"i386-dis.c.o' -Else If "{target_arch}" =~ /mips/ - Set BFD_MACHINES '"{o}"mips-dis.c.o "{o}"mips-opc.c.o' -Else If "{target_arch}" =~ /sh/ - Set BFD_MACHINES '"{o}"sh-dis.c.o' -End If - -Echo '# Start from mpw-config.in' > "{o}"mk.tmp -Echo "BFD_MACHINES = " {BFD_MACHINES} >> "{o}"mk.tmp -Echo "ARCHDEFS = -d" {archname} >> "{o}"mk.tmp -Echo '# End from mpw-config.in' >> "{o}"mk.tmp - -Echo '/* config.h. Generated by mpw-configure. */' > "{o}"config.new -Echo '#include "mpw.h"' >> "{o}"config.new - -MoveIfChange "{o}"config.new "{o}"config.h diff --git a/opcodes/mpw-make.sed b/opcodes/mpw-make.sed deleted file mode 100644 index ee604862de6..00000000000 --- a/opcodes/mpw-make.sed +++ /dev/null @@ -1,25 +0,0 @@ -# Sed commands to finish translating the opcodes Makefile.in into MPW syntax. - -# Empty HDEFINES. -/HDEFINES/s/@HDEFINES@// - -# Fix pathnames to include directories. -/^INCDIR = /s/^INCDIR = .*$/INCDIR = "{topsrcdir}"include/ -/^CSEARCH = /s/$/ -i "{INCDIR}":mpw: -i ::extra-include:/ - -/BFD_MACHINES/s/@BFD_MACHINES@/{BFD_MACHINES}/ -/archdefs/s/@archdefs@/{ARCHDEFS}/ - -# No PIC foolery in this environment. -/@ALLLIBS@/s/@ALLLIBS@/{TARGETLIB}/ -/@PICLIST@/s/@PICLIST@// -/@PICFLAG@/s/@PICFLAG@// -/^{OFILES} \\Option-f stamp-picdir/,/^$/d - -# Remove the pic trickery from the default build rule. -/^\.c\.o \\Option-f /,/End If/c\ -.c.o \\Option-f .c - -# Remove pic trickery from other rules - aimed at the rule -# for disassemble.o in particular. -/-n "{PICFLAG}"/,/End If/d diff --git a/opcodes/ns32k-dis.c b/opcodes/ns32k-dis.c deleted file mode 100644 index 808fdd204e3..00000000000 --- a/opcodes/ns32k-dis.c +++ /dev/null @@ -1,846 +0,0 @@ -/* Print National Semiconductor 32000 instructions. - Copyright 1986, 1988, 1991, 1992, 1994 Free Software Foundation, Inc. - -This file is part of opcodes library. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ - - -#include "bfd.h" -#include "sysdep.h" -#include "dis-asm.h" -#if !defined(const) && !defined(__STDC__) -#define const -#endif -#include "opcode/ns32k.h" - -static disassemble_info *dis_info; - -/* - * Hacks to get it to compile <= READ THESE AS FIXES NEEDED - */ -#define CORE_ADDR unsigned long -#define INVALID_FLOAT(val, size) invalid_float((char *)val, size) - -static long read_memory_integer(addr, nr) - unsigned char *addr; - int nr; -{ - long val; - int i; - for (val = 0, i = nr - 1; i >= 0; i--) { - val = (val << 8); - val |= (0xff & *(addr + i)); - } - return val; -} - -/* 32000 instructions are never longer than this. */ -#define MAXLEN 62 - - -#include <setjmp.h> - -struct private -{ - /* Points to first byte not fetched. */ - bfd_byte *max_fetched; - bfd_byte the_buffer[MAXLEN]; - bfd_vma insn_start; - jmp_buf bailout; -}; - - -/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) - to ADDR (exclusive) are valid. Returns 1 for success, longjmps - on error. */ -#define FETCH_DATA(info, addr) \ - ((addr) <= ((struct private *)(info->private_data))->max_fetched \ - ? 1 : fetch_data ((info), (addr))) - -static int -fetch_data (info, addr) - struct disassemble_info *info; - bfd_byte *addr; -{ - int status; - struct private *priv = (struct private *)info->private_data; - bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); - - status = (*info->read_memory_func) (start, - priv->max_fetched, - addr - priv->max_fetched, - info); - if (status != 0) - { - (*info->memory_error_func) (status, start, info); - longjmp (priv->bailout, 1); - } - else - priv->max_fetched = addr; - return 1; -} -/* Number of elements in the opcode table. */ -#define NOPCODES (sizeof ns32k_opcodes / sizeof ns32k_opcodes[0]) - -#define NEXT_IS_ADDR '|' - - -struct option { - char *pattern; /* the option itself */ - unsigned long value; /* binary value of the option */ - unsigned long match; /* these bits must match */ -}; - - -static struct option opt_u[]= /* restore, exit */ -{ - { "r0", 0x80, 0x80 }, - { "r1", 0x40, 0x40 }, - { "r2", 0x20, 0x20 }, - { "r3", 0x10, 0x10 }, - { "r4", 0x08, 0x08 }, - { "r5", 0x04, 0x04 }, - { "r6", 0x02, 0x02 }, - { "r7", 0x01, 0x01 }, - { 0 , 0x00, 0x00 } -}; - -static struct option opt_U[]= /* save, enter */ -{ - { "r0", 0x01, 0x01 }, - { "r1", 0x02, 0x02 }, - { "r2", 0x04, 0x04 }, - { "r3", 0x08, 0x08 }, - { "r4", 0x10, 0x10 }, - { "r5", 0x20, 0x20 }, - { "r6", 0x40, 0x40 }, - { "r7", 0x80, 0x80 }, - { 0 , 0x00, 0x00 } -}; - -static struct option opt_O[]= /* setcfg */ -{ - { "c", 0x8, 0x8 }, - { "m", 0x4, 0x4 }, - { "f", 0x2, 0x2 }, - { "i", 0x1, 0x1 }, - { 0 , 0x0, 0x0 } -}; - -static struct option opt_C[]= /* cinv */ -{ - { "a", 0x4, 0x4 }, - { "i", 0x2, 0x2 }, - { "d", 0x1, 0x1 }, - { 0 , 0x0, 0x0 } -}; - -static struct option opt_S[]= /* string inst */ -{ - { "b", 0x1, 0x1 }, - { "u", 0x6, 0x6 }, - { "w", 0x2, 0x2 }, - { 0 , 0x0, 0x0 } -}; - -static struct option list_P532[]= /* lpr spr */ -{ - { "us", 0x0, 0xf }, - { "dcr", 0x1, 0xf }, - { "bpc", 0x2, 0xf }, - { "dsr", 0x3, 0xf }, - { "car", 0x4, 0xf }, - { "fp", 0x8, 0xf }, - { "sp", 0x9, 0xf }, - { "sb", 0xa, 0xf }, - { "usp", 0xb, 0xf }, - { "cfg", 0xc, 0xf }, - { "psr", 0xd, 0xf }, - { "intbase", 0xe, 0xf }, - { "mod", 0xf, 0xf }, - { 0 , 0x00, 0xf } -}; - -static struct option list_M532[]= /* lmr smr */ -{ - { "mcr", 0x9, 0xf }, - { "msr", 0xa, 0xf }, - { "tear", 0xb, 0xf }, - { "ptb0", 0xc, 0xf }, - { "ptb1", 0xd, 0xf }, - { "ivar0", 0xe, 0xf }, - { "ivar1", 0xf, 0xf }, - { 0 , 0x0, 0xf } -}; - -static struct option list_P032[]= /* lpr spr */ -{ - { "upsr", 0x0, 0xf }, - { "fp", 0x8, 0xf }, - { "sp", 0x9, 0xf }, - { "sb", 0xa, 0xf }, - { "psr", 0xb, 0xf }, - { "intbase", 0xe, 0xf }, - { "mod", 0xf, 0xf }, - { 0 , 0x0, 0xf } -}; - -static struct option list_M032[]= /* lmr smr */ -{ - { "bpr0", 0x0, 0xf }, - { "bpr1", 0x1, 0xf }, - { "pf0", 0x4, 0xf }, - { "pf1", 0x5, 0xf }, - { "sc", 0x8, 0xf }, - { "msr", 0xa, 0xf }, - { "bcnt", 0xb, 0xf }, - { "ptb0", 0xc, 0xf }, - { "ptb1", 0xd, 0xf }, - { "eia", 0xf, 0xf }, - { 0 , 0x0, 0xf } -}; - - -/* - * figure out which options are present - */ -static void -optlist(options, optionP, result) - int options; - struct option *optionP; - char *result; -{ - if (options == 0) { - sprintf(result, "[]"); - return; - } - sprintf(result, "["); - - for (; (options != 0) && optionP->pattern; optionP++) { - if ((options & optionP->match) == optionP->value) { - /* we found a match, update result and options */ - strcat(result, optionP->pattern); - options &= ~optionP->value; - if (options != 0) /* more options to come */ - strcat(result, ","); - } - } - if (options != 0) - strcat(result, "undefined"); - - strcat(result, "]"); -} - -static list_search(reg_value, optionP, result) - int reg_value; - struct option *optionP; - char *result; -{ - for (; optionP->pattern; optionP++) { - if ((reg_value & optionP->match) == optionP->value) { - sprintf(result, "%s", optionP->pattern); - return; - } - } - sprintf(result, "undefined"); -} - -/* - * extract "count" bits starting "offset" bits - * into buffer - */ - -static int -bit_extract (buffer, offset, count) - bfd_byte *buffer; - int offset; - int count; -{ - int result; - int mask; - int bit; - - buffer += offset >> 3; - offset &= 7; - bit = 1; - result = 0; - while (count--) - { - FETCH_DATA(dis_info, buffer + 1); - if ((*buffer & (1 << offset))) - result |= bit; - if (++offset == 8) - { - offset = 0; - buffer++; - } - bit <<= 1; - } - return result; -} - -static void -bit_copy (buffer, offset, count, to) - char *buffer; - int offset; - int count; - char *to; -{ - for(; count > 8; count -= 8, to++, offset += 8) - *to = bit_extract (buffer, offset, 8); - *to = bit_extract (buffer, offset, count); -} - - -static sign_extend (value, bits) - int value, bits; -{ - value = value & ((1 << bits) - 1); - return (value & (1 << (bits-1)) - ? value | (~((1 << bits) - 1)) - : value); -} - -static flip_bytes (ptr, count) - char *ptr; - int count; -{ - char tmp; - - while (count > 0) - { - tmp = ptr[0]; - ptr[0] = ptr[count-1]; - ptr[count-1] = tmp; - ptr++; - count -= 2; - } -} - -/* Given a character C, does it represent a general addressing mode? */ -#define Is_gen(c) \ - ((c) == 'F' || (c) == 'L' || (c) == 'B' \ - || (c) == 'W' || (c) == 'D' || (c) == 'A' || (c) == 'I' || (c) == 'Z') - -/* Adressing modes. */ -#define Adrmod_index_byte 0x1c -#define Adrmod_index_word 0x1d -#define Adrmod_index_doubleword 0x1e -#define Adrmod_index_quadword 0x1f - -/* Is MODE an indexed addressing mode? */ -#define Adrmod_is_index(mode) \ - (mode == Adrmod_index_byte \ - || mode == Adrmod_index_word \ - || mode == Adrmod_index_doubleword \ - || mode == Adrmod_index_quadword) - - -/* Print the 32000 instruction at address MEMADDR in debugged memory, - on STREAM. Returns length of the instruction, in bytes. */ - -int -print_insn_ns32k (memaddr, info) - bfd_vma memaddr; - disassemble_info *info; -{ - register int i; - register unsigned char *p; - register char *d; - unsigned short first_word; - int gen, disp; - int ioffset; /* bits into instruction */ - int aoffset; /* bits into arguments */ - char arg_bufs[MAX_ARGS+1][ARG_LEN]; - int argnum; - int maxarg; - struct private priv; - bfd_byte *buffer = priv.the_buffer; - dis_info = info; - - info->private_data = (PTR) &priv; - priv.max_fetched = priv.the_buffer; - priv.insn_start = memaddr; - if (setjmp (priv.bailout) != 0) - /* Error return. */ - return -1; - - /* Look for 8bit opcodes first. Other wise, fetching two bytes could take - * us over the end of accessible data unnecessarilly - */ - FETCH_DATA(info, buffer + 1); - for (i = 0; i < NOPCODES; i++) - if (ns32k_opcodes[i].opcode_id_size <= 8 - && ((buffer[0] & ((1 << ns32k_opcodes[i].opcode_id_size) - 1)) - == ns32k_opcodes[i].opcode_seed)) - break; - if (i == NOPCODES) { - /* Maybe it is 9 to 16 bits big */ - FETCH_DATA(info, buffer + 2); - first_word = read_memory_integer(buffer, 2); - - for (i = 0; i < NOPCODES; i++) - if ((first_word & ((1 << ns32k_opcodes[i].opcode_id_size) - 1)) - == ns32k_opcodes[i].opcode_seed) - break; - - /* Handle undefined instructions. */ - if (i == NOPCODES) - { - (*dis_info->fprintf_func)(dis_info->stream, "0%o", buffer[0]); - return 1; - } - } - - (*dis_info->fprintf_func)(dis_info->stream, "%s", ns32k_opcodes[i].name); - - ioffset = ns32k_opcodes[i].opcode_size; - aoffset = ns32k_opcodes[i].opcode_size; - d = ns32k_opcodes[i].operands; - - if (*d) - { - /* Offset in bits of the first thing beyond each index byte. - Element 0 is for operand A and element 1 is for operand B. - The rest are irrelevant, but we put them here so we don't - index outside the array. */ - int index_offset[MAX_ARGS]; - - /* 0 for operand A, 1 for operand B, greater for other args. */ - int whicharg = 0; - - (*dis_info->fprintf_func)(dis_info->stream, "\t"); - - maxarg = 0; - - /* First we have to find and keep track of the index bytes, - if we are using scaled indexed addressing mode, since the index - bytes occur right after the basic instruction, not as part - of the addressing extension. */ - if (Is_gen(d[1])) - { - int addr_mode = bit_extract (buffer, ioffset - 5, 5); - - if (Adrmod_is_index (addr_mode)) - { - aoffset += 8; - index_offset[0] = aoffset; - } - } - if (d[2] && Is_gen(d[3])) - { - int addr_mode = bit_extract (buffer, ioffset - 10, 5); - - if (Adrmod_is_index (addr_mode)) - { - aoffset += 8; - index_offset[1] = aoffset; - } - } - - while (*d) - { - argnum = *d - '1'; - d++; - if (argnum > maxarg && argnum < MAX_ARGS) - maxarg = argnum; - ioffset = print_insn_arg (*d, ioffset, &aoffset, buffer, - memaddr, arg_bufs[argnum], - index_offset[whicharg]); - d++; - whicharg++; - } - for (argnum = 0; argnum <= maxarg; argnum++) - { - CORE_ADDR addr; - char *ch; - for (ch = arg_bufs[argnum]; *ch;) - { - if (*ch == NEXT_IS_ADDR) - { - ++ch; - addr = atoi (ch); - (*dis_info->print_address_func) (addr, dis_info); - while (*ch && *ch != NEXT_IS_ADDR) - ++ch; - if (*ch) - ++ch; - } - else - (*dis_info->fprintf_func)(dis_info->stream, "%c", *ch++); - } - if (argnum < maxarg) - (*dis_info->fprintf_func)(dis_info->stream, ", "); - } - } - return aoffset / 8; -} - -/* Print an instruction operand of category given by d. IOFFSET is - the bit position below which small (<1 byte) parts of the operand can - be found (usually in the basic instruction, but for indexed - addressing it can be in the index byte). AOFFSETP is a pointer to the - bit position of the addressing extension. BUFFER contains the - instruction. ADDR is where BUFFER was read from. Put the disassembled - version of the operand in RESULT. INDEX_OFFSET is the bit position - of the index byte (it contains garbage if this operand is not a - general operand using scaled indexed addressing mode). */ - -print_insn_arg (d, ioffset, aoffsetp, buffer, addr, result, index_offset) - char d; - int ioffset, *aoffsetp; - char *buffer; - CORE_ADDR addr; - char *result; - int index_offset; -{ - int addr_mode; - float Fvalue; - double Lvalue; - int Ivalue; - int disp1, disp2; - int index; - int size; - - switch (d) - { - case 'f': - /* a "gen" operand but 5 bits from the end of instruction */ - ioffset -= 5; - case 'Z': - case 'F': - case 'L': - case 'I': - case 'B': - case 'W': - case 'D': - case 'A': - addr_mode = bit_extract (buffer, ioffset-5, 5); - ioffset -= 5; - switch (addr_mode) - { - case 0x0: case 0x1: case 0x2: case 0x3: - case 0x4: case 0x5: case 0x6: case 0x7: - /* register mode R0 -- R7 */ - switch (d) - { - case 'F': - case 'L': - case 'Z': - sprintf (result, "f%d", addr_mode); - break; - default: - sprintf (result, "r%d", addr_mode); - } - break; - case 0x8: case 0x9: case 0xa: case 0xb: - case 0xc: case 0xd: case 0xe: case 0xf: - /* Register relative disp(R0 -- R7) */ - disp1 = get_displacement (buffer, aoffsetp); - sprintf (result, "%d(r%d)", disp1, addr_mode & 7); - break; - case 0x10: - case 0x11: - case 0x12: - /* Memory relative disp2(disp1(FP, SP, SB)) */ - disp1 = get_displacement (buffer, aoffsetp); - disp2 = get_displacement (buffer, aoffsetp); - sprintf (result, "%d(%d(%s))", disp2, disp1, - addr_mode==0x10?"fp":addr_mode==0x11?"sp":"sb"); - break; - case 0x13: - /* reserved */ - sprintf (result, "reserved"); - break; - case 0x14: - /* Immediate */ - switch (d) - { - case 'I': case 'Z': case 'A': - /* I and Z are output operands and can`t be immediate - * A is an address and we can`t have the address of - * an immediate either. We don't know how much to increase - * aoffsetp by since whatever generated this is broken - * anyway! - */ - sprintf (result, "$<undefined>"); - break; - case 'B': - Ivalue = bit_extract (buffer, *aoffsetp, 8); - Ivalue = sign_extend (Ivalue, 8); - *aoffsetp += 8; - sprintf (result, "$%d", Ivalue); - break; - case 'W': - Ivalue = bit_extract (buffer, *aoffsetp, 16); - flip_bytes (&Ivalue, 2); - *aoffsetp += 16; - Ivalue = sign_extend (Ivalue, 16); - sprintf (result, "$%d", Ivalue); - break; - case 'D': - Ivalue = bit_extract (buffer, *aoffsetp, 32); - flip_bytes (&Ivalue, 4); - *aoffsetp += 32; - sprintf (result, "$%d", Ivalue); - break; - case 'F': - bit_copy (buffer, *aoffsetp, 32, (char *) &Fvalue); - flip_bytes (&Fvalue, 4); - *aoffsetp += 32; - if (INVALID_FLOAT (&Fvalue, 4)) - sprintf (result, "<<invalid float 0x%.8x>>", *(int *) &Fvalue); - else /* assume host has ieee float */ - sprintf (result, "$%g", Fvalue); - break; - case 'L': - bit_copy (buffer, *aoffsetp, 64, (char *) &Lvalue); - flip_bytes (&Lvalue, 8); - *aoffsetp += 64; - if (INVALID_FLOAT (&Lvalue, 8)) - sprintf (result, "<<invalid long 0x%.8x%.8x>>", - *(((int *) &Lvalue) + 1), *(int *) &Lvalue); - else /* assume host has ieee float */ - sprintf (result, "$%g", Lvalue); - break; - } - break; - case 0x15: - /* Absolute @disp */ - disp1 = get_displacement (buffer, aoffsetp); - sprintf (result, "@|%d|", disp1); - break; - case 0x16: - /* External EXT(disp1) + disp2 (Mod table stuff) */ - disp1 = get_displacement (buffer, aoffsetp); - disp2 = get_displacement (buffer, aoffsetp); - sprintf (result, "EXT(%d) + %d", disp1, disp2); - break; - case 0x17: - /* Top of stack tos */ - sprintf (result, "tos"); - break; - case 0x18: - /* Memory space disp(FP) */ - disp1 = get_displacement (buffer, aoffsetp); - sprintf (result, "%d(fp)", disp1); - break; - case 0x19: - /* Memory space disp(SP) */ - disp1 = get_displacement (buffer, aoffsetp); - sprintf (result, "%d(sp)", disp1); - break; - case 0x1a: - /* Memory space disp(SB) */ - disp1 = get_displacement (buffer, aoffsetp); - sprintf (result, "%d(sb)", disp1); - break; - case 0x1b: - /* Memory space disp(PC) */ - disp1 = get_displacement (buffer, aoffsetp); - sprintf (result, "|%d|", addr + disp1); - break; - case 0x1c: - case 0x1d: - case 0x1e: - case 0x1f: - /* Scaled index basemode[R0 -- R7:B,W,D,Q] */ - index = bit_extract (buffer, index_offset - 8, 3); - print_insn_arg (d, index_offset, aoffsetp, buffer, addr, - result, 0); - { - static char *ind[] = {"b", "w", "d", "q"}; - char *off; - - off = result + strlen (result); - sprintf (off, "[r%d:%s]", index, - ind[addr_mode & 3]); - } - break; - } - break; - case 'H': - case 'q': - Ivalue = bit_extract (buffer, ioffset-4, 4); - Ivalue = sign_extend (Ivalue, 4); - sprintf (result, "%d", Ivalue); - ioffset -= 4; - break; - case 'r': - Ivalue = bit_extract (buffer, ioffset-3, 3); - sprintf (result, "r%d", Ivalue&7); - ioffset -= 3; - break; - case 'd': - sprintf (result, "%d", get_displacement (buffer, aoffsetp)); - break; - case 'b': - Ivalue = get_displacement (buffer, aoffsetp); - /* - * Warning!! HACK ALERT! - * Operand type 'b' is only used by the cmp{b,w,d} and - * movm{b,w,d} instructions; we need to know whether - * it's a `b' or `w' or `d' instruction; and for both - * cmpm and movm it's stored at the same place so we - * just grab two bits of the opcode and look at it... - * - */ - size = bit_extract(buffer, ioffset-6, 2); - if (size == 0) /* 00 => b */ - size = 1; - else if (size == 1) /* 01 => w */ - size = 2; - else - size = 4; /* 11 => d */ - - sprintf (result, "%d", (Ivalue / size) + 1); - break; - case 'p': - sprintf (result, "%c%d%c", NEXT_IS_ADDR, - addr + get_displacement (buffer, aoffsetp), - NEXT_IS_ADDR); - break; - case 'i': - Ivalue = bit_extract (buffer, *aoffsetp, 8); - *aoffsetp += 8; - sprintf (result, "0x%x", Ivalue); - break; - case 'u': - Ivalue = bit_extract (buffer, *aoffsetp, 8); - optlist(Ivalue, opt_u, result); - *aoffsetp += 8; - break; - case 'U': - Ivalue = bit_extract(buffer, *aoffsetp, 8); - optlist(Ivalue, opt_U, result); - *aoffsetp += 8; - break; - case 'O': - Ivalue = bit_extract(buffer, ioffset-9, 9); - optlist(Ivalue, opt_O, result); - ioffset -= 9; - break; - case 'C': - Ivalue = bit_extract(buffer, ioffset-4, 4); - optlist(Ivalue, opt_C, result); - ioffset -= 4; - break; - case 'S': - Ivalue = bit_extract(buffer, ioffset - 8, 8); - optlist(Ivalue, opt_S, result); - ioffset -= 8; - break; - case 'M': - Ivalue = bit_extract(buffer, ioffset-4, 4); - list_search(Ivalue, 0 ? list_M032 : list_M532, result); - ioffset -= 4; - break; - case 'P': - Ivalue = bit_extract(buffer, ioffset-4, 4); - list_search(Ivalue, 0 ? list_P032 : list_P532, result); - ioffset -= 4; - break; - case 'g': - Ivalue = bit_extract(buffer, *aoffsetp, 3); - sprintf(result, "%d", Ivalue); - *aoffsetp += 3; - break; - case 'G': - Ivalue = bit_extract(buffer, *aoffsetp, 5); - sprintf(result, "%d", Ivalue + 1); - *aoffsetp += 5; - break; - } - return ioffset; -} - -get_displacement (buffer, aoffsetp) - char *buffer; - int *aoffsetp; -{ - int Ivalue; - short Ivalue2; - - Ivalue = bit_extract (buffer, *aoffsetp, 8); - switch (Ivalue & 0xc0) - { - case 0x00: - case 0x40: - Ivalue = sign_extend (Ivalue, 7); - *aoffsetp += 8; - break; - case 0x80: - Ivalue2 = bit_extract (buffer, *aoffsetp, 16); - flip_bytes (&Ivalue2, 2); - Ivalue = sign_extend (Ivalue2, 14); - *aoffsetp += 16; - break; - case 0xc0: - Ivalue = bit_extract (buffer, *aoffsetp, 32); - flip_bytes (&Ivalue, 4); - Ivalue = sign_extend (Ivalue, 30); - *aoffsetp += 32; - break; - } - return Ivalue; -} - - -#if 1 /* a version that should work on ns32k f's&d's on any machine */ -int invalid_float(p, len) - register char *p; - register int len; -{ - register val; - - if ( len == 4 ) - val = (bit_extract(p, 23, 8)/*exponent*/ == 0xff - || (bit_extract(p, 23, 8)/*exponent*/ == 0 && - bit_extract(p, 0, 23)/*mantisa*/ != 0)); - else if ( len == 8 ) - val = (bit_extract(p, 52, 11)/*exponent*/ == 0x7ff - || (bit_extract(p, 52, 11)/*exponent*/ == 0 - && (bit_extract(p, 0, 32)/*low mantisa*/ != 0 - || bit_extract(p, 32, 20)/*high mantisa*/ != 0))); - else - val = 1; - return (val); -} -#else - -/* assumes the bytes have been swapped to local order */ -typedef union { double d; - float f; - struct { unsigned m:23, e:8, :1;} sf; - struct { unsigned lm; unsigned m:20, e:11, :1;} sd; - } float_type_u; - -int invalid_float(p, len) - register float_type_u *p; - register int len; -{ - register int val; - if ( len == sizeof (float) ) - val = (p->sf.e == 0xff - || (p->sf.e == 0 && p->sf.m != 0)); - else if ( len == sizeof (double) ) - val = (p->sd.e == 0x7ff - || (p->sd.e == 0 && (p->sd.m != 0 || p->sd.lm != 0))); - else - val = 1; - return (val); -} -#endif diff --git a/opcodes/opintl.h b/opcodes/opintl.h deleted file mode 100644 index 8a5203f73ba..00000000000 --- a/opcodes/opintl.h +++ /dev/null @@ -1,34 +0,0 @@ -/* opintl.h - opcodes specific header for gettext code. - Copyright (C) 1998 Free Software Foundation, Inc. - - Written by Tom Tromey <tromey@cygnus.com> - - This file is part of the opcodes library used by GAS and the GNU binutils. - - You should have received a copy of the GNU General Public License - along with GAS; see the file COPYING. If not, write to the Free - Software Foundation, 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -#ifdef ENABLE_NLS -# include <libintl.h> -# define _(String) gettext (String) -# ifdef gettext_noop -# define N_(String) gettext_noop (String) -# else -# define N_(String) (String) -# endif -#else -/* Stubs that do something close enough. */ -# define textdomain(String) (String) -# define gettext(String) (String) -# define dgettext(Domain,Message) (Message) -# define dcgettext(Domain,Message,Type) (Message) -# define bindtextdomain(Domain,Directory) (Domain) -# define _(String) (String) -# define N_(String) (String) -/* In this case we don't care about the value. */ -# ifndef LC_MESSAGES -# define LC_MESSAGES 0 -# endif -#endif diff --git a/opcodes/po/.Sanitize b/opcodes/po/.Sanitize deleted file mode 100644 index f9af5795989..00000000000 --- a/opcodes/po/.Sanitize +++ /dev/null @@ -1,41 +0,0 @@ -# .Sanitize for devo/opcodes/po - -# Each directory to survive its way into a release will need a file -# like this one called "./.Sanitize". All keyword lines must exist, -# and must exist in the order specified by this file. Each directory -# in the tree will be processed, top down, in the following order. - -# Hash started lines like this one are comments and will be deleted -# before anything else is done. Blank lines will also be squashed -# out. - -# The lines between the "Do-first:" line and the "Things-to-keep:" -# line are executed as a /bin/sh shell script before anything else is -# done in this directory. - -Do-first: - - -# All files listed between the "Things-to-keep:" line and the -# "Do-last:" line will be kept. All other files will be removed. -# Directories listed in this section will have their own Sanitize -# called. Directories not listed will be removed in their entirety -# with rm -rf. - -Things-to-keep: - -Make-in -POTFILES.in -opcodes.pot - -Things-to-lose: - - - -# The lines between the "Do-last:" line and the end of the file -# are executed as a /bin/sh shell script after everything else is -# done. - -Do-last: - -# eof diff --git a/opcodes/po/Make-in b/opcodes/po/Make-in deleted file mode 100644 index b6e4bc99afc..00000000000 --- a/opcodes/po/Make-in +++ /dev/null @@ -1,250 +0,0 @@ -# Makefile for program source directory in GNU NLS utilities package. -# Copyright (C) 1995, 1996, 1997 by Ulrich Drepper <drepper@gnu.ai.mit.edu> -# -# This file file be copied and used freely without restrictions. It can -# be used in projects which are not available under the GNU Public License -# but which still want to provide support for the GNU gettext functionality. -# Please note that the actual code is *not* freely available. - -PACKAGE = @PACKAGE@ -VERSION = @VERSION@ - -SHELL = /bin/sh -@SET_MAKE@ - -srcdir = @srcdir@ -top_srcdir = @top_srcdir@ -VPATH = @srcdir@ - -prefix = @prefix@ -exec_prefix = @exec_prefix@ -datadir = $(prefix)/@DATADIRNAME@ -localedir = $(datadir)/locale -gnulocaledir = $(prefix)/share/locale -gettextsrcdir = $(prefix)/share/gettext/po -subdir = po - -INSTALL = @INSTALL@ -INSTALL_DATA = @INSTALL_DATA@ -MKINSTALLDIRS = @MKINSTALLDIRS@ - -CC = @CC@ -GENCAT = @GENCAT@ -GMSGFMT = PATH=../src:$$PATH @GMSGFMT@ -MSGFMT = @MSGFMT@ -XGETTEXT = PATH=../src:$$PATH @XGETTEXT@ -MSGMERGE = PATH=../src:$$PATH msgmerge - -DEFS = @DEFS@ -CFLAGS = @CFLAGS@ -CPPFLAGS = @CPPFLAGS@ - -INCLUDES = -I.. -I$(top_srcdir)/intl - -COMPILE = $(CC) -c $(DEFS) $(INCLUDES) $(CPPFLAGS) $(CFLAGS) $(XCFLAGS) - -SOURCES = cat-id-tbl.c -POFILES = @POFILES@ -GMOFILES = @GMOFILES@ -DISTFILES = ChangeLog Makefile.in.in POTFILES.in $(PACKAGE).pot \ -stamp-cat-id $(POFILES) $(GMOFILES) $(SOURCES) - -POTFILES = \ - -CATALOGS = @CATALOGS@ -CATOBJEXT = @CATOBJEXT@ -INSTOBJEXT = @INSTOBJEXT@ - -.SUFFIXES: -.SUFFIXES: .c .o .po .pox .gmo .mo .msg .cat - -.c.o: - $(COMPILE) $< - -.po.pox: - $(MAKE) $(PACKAGE).pot - $(MSGMERGE) $< $(srcdir)/$(PACKAGE).pot -o $*.pox - -.po.mo: - $(MSGFMT) -o $@ $< - -.po.gmo: - file=$(srcdir)/`echo $* | sed 's,.*/,,'`.gmo \ - && rm -f $$file && $(GMSGFMT) -o $$file $< - -.po.cat: - sed -f ../intl/po2msg.sed < $< > $*.msg \ - && rm -f $@ && $(GENCAT) $@ $*.msg - - -all: all-@USE_NLS@ - -all-yes: $(CATALOGS) -all-no: - -$(srcdir)/$(PACKAGE).pot: @MAINT@ $(POTFILES) - $(XGETTEXT) --default-domain=$(PACKAGE) --directory=$(top_srcdir) \ - --add-comments --keyword=_ --keyword=N_ \ - --files-from=$(srcdir)/POTFILES.in - rm -f $(srcdir)/$(PACKAGE).pot - mv $(PACKAGE).po $(srcdir)/$(PACKAGE).pot - -$(srcdir)/cat-id-tbl.c: stamp-cat-id; @: -$(srcdir)/stamp-cat-id: $(PACKAGE).pot - rm -f cat-id-tbl.tmp - sed -f ../intl/po2tbl.sed $(srcdir)/$(PACKAGE).pot \ - | sed -e "s/@PACKAGE NAME@/$(PACKAGE)/" > cat-id-tbl.tmp - if cmp -s cat-id-tbl.tmp $(srcdir)/cat-id-tbl.c; then \ - rm cat-id-tbl.tmp; \ - else \ - echo cat-id-tbl.c changed; \ - rm -f $(srcdir)/cat-id-tbl.c; \ - mv cat-id-tbl.tmp $(srcdir)/cat-id-tbl.c; \ - fi - cd $(srcdir) && rm -f stamp-cat-id && echo timestamp > stamp-cat-id - - -install: install-exec install-data -install-exec: -install-data: install-data-@USE_NLS@ -install-data-no: all -install-data-yes: all - if test -r $(MKINSTALLDIRS); then \ - $(MKINSTALLDIRS) $(datadir); \ - else \ - $(top_srcdir)/mkinstalldirs $(datadir); \ - fi - @catalogs='$(CATALOGS)'; \ - for cat in $$catalogs; do \ - cat=`basename $$cat`; \ - case "$$cat" in \ - *.gmo) destdir=$(gnulocaledir);; \ - *) destdir=$(localedir);; \ - esac; \ - lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ - dir=$$destdir/$$lang/LC_MESSAGES; \ - if test -r $(MKINSTALLDIRS); then \ - $(MKINSTALLDIRS) $$dir; \ - else \ - $(top_srcdir)/mkinstalldirs $$dir; \ - fi; \ - if test -r $$cat; then \ - $(INSTALL_DATA) $$cat $$dir/$(PACKAGE)$(INSTOBJEXT); \ - echo "installing $$cat as $$dir/$(PACKAGE)$(INSTOBJEXT)"; \ - else \ - $(INSTALL_DATA) $(srcdir)/$$cat $$dir/$(PACKAGE)$(INSTOBJEXT); \ - echo "installing $(srcdir)/$$cat as" \ - "$$dir/$(PACKAGE)$(INSTOBJEXT)"; \ - fi; \ - if test -r $$cat.m; then \ - $(INSTALL_DATA) $$cat.m $$dir/$(PACKAGE)$(INSTOBJEXT).m; \ - echo "installing $$cat.m as $$dir/$(PACKAGE)$(INSTOBJEXT).m"; \ - else \ - if test -r $(srcdir)/$$cat.m ; then \ - $(INSTALL_DATA) $(srcdir)/$$cat.m \ - $$dir/$(PACKAGE)$(INSTOBJEXT).m; \ - echo "installing $(srcdir)/$$cat as" \ - "$$dir/$(PACKAGE)$(INSTOBJEXT).m"; \ - else \ - true; \ - fi; \ - fi; \ - done - if test "$(PACKAGE)" = "gettext"; then \ - if test -r $(MKINSTALLDIRS); then \ - $(MKINSTALLDIRS) $(gettextsrcdir); \ - else \ - $(top_srcdir)/mkinstalldirs $(gettextsrcdir); \ - fi; \ - $(INSTALL_DATA) $(srcdir)/Makefile.in.in \ - $(gettextsrcdir)/Makefile.in.in; \ - else \ - : ; \ - fi - -# Define this as empty until I found a useful application. -installcheck: - -uninstall: - catalogs='$(CATALOGS)'; \ - for cat in $$catalogs; do \ - cat=`basename $$cat`; \ - lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ - rm -f $(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \ - rm -f $(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \ - rm -f $(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \ - rm -f $(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \ - done - rm -f $(gettextsrcdir)/po-Makefile.in.in - -check: all - -cat-id-tbl.o: ../intl/libgettext.h - -dvi info tags TAGS ID: - -mostlyclean: - rm -f core core.* *.pox $(PACKAGE).po *.old.po cat-id-tbl.tmp - rm -fr *.o - -clean: mostlyclean - -distclean: clean - rm -f Makefile Makefile.in POTFILES *.mo *.msg *.cat *.cat.m - -maintainer-clean: distclean - @echo "This command is intended for maintainers to use;" - @echo "it deletes files that may require special tools to rebuild." - rm -f $(GMOFILES) - -distdir = ../$(PACKAGE)-$(VERSION)/$(subdir) -dist distdir: update-po $(DISTFILES) - dists="$(DISTFILES)"; \ - for file in $$dists; do \ - ln $(srcdir)/$$file $(distdir) 2> /dev/null \ - || cp -p $(srcdir)/$$file $(distdir); \ - done - -update-po: Makefile - $(MAKE) $(PACKAGE).pot - PATH=`pwd`/../src:$$PATH; \ - cd $(srcdir); \ - catalogs='$(CATALOGS)'; \ - for cat in $$catalogs; do \ - cat=`basename $$cat`; \ - lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ - mv $$lang.po $$lang.old.po; \ - echo "$$lang:"; \ - if $(MSGMERGE) $$lang.old.po $(PACKAGE).pot -o $$lang.po; then \ - rm -f $$lang.old.po; \ - else \ - echo "msgmerge for $$cat failed!"; \ - rm -f $$lang.po; \ - mv $$lang.old.po $$lang.po; \ - fi; \ - done - -POTFILES: POTFILES.in - ( if test 'x$(srcdir)' != 'x.'; then \ - posrcprefix='$(top_srcdir)/'; \ - else \ - posrcprefix="../"; \ - fi; \ - rm -f $@-t $@ \ - && (sed -e '/^#/d' -e '/^[ ]*$$/d' \ - -e "s@.*@ $$posrcprefix& \\\\@" < $(srcdir)/$@.in \ - | sed -e '$$s/\\$$//') > $@-t \ - && chmod a-w $@-t \ - && mv $@-t $@ ) - -POTFILES.in: @MAINT@ ../Makefile - cd .. && $(MAKE) po/POTFILES.in - -Makefile: Make-in ../config.status POTFILES - cd .. \ - && CONFIG_FILES=$(subdir)/Makefile.in:$(subdir)/Make-in \ - CONFIG_HEADERS= $(SHELL) ./config.status - -# Tell versions [3.59,3.63) of GNU make not to export all variables. -# Otherwise a system limit (for SysV at least) may be exceeded. -.NOEXPORT: diff --git a/opcodes/po/POTFILES.in b/opcodes/po/POTFILES.in deleted file mode 100644 index a61f0f09de7..00000000000 --- a/opcodes/po/POTFILES.in +++ /dev/null @@ -1,51 +0,0 @@ -a29k-dis.c -alpha-dis.c -alpha-opc.c -arm-dis.c -arm-opc.h -cgen-asm.c -cgen-dis.c -cgen-opc.c -d10v-dis.c -d10v-opc.c -d30v-dis.c -d30v-opc.c -dis-buf.c -disassemble.c -h8300-dis.c -h8500-dis.c -h8500-opc.h -hppa-dis.c -i386-dis.c -i960-dis.c -i960c-asm.c -i960c-dis.c -i960c-opc.c -m10200-dis.c -m10200-opc.c -m10300-dis.c -m10300-opc.c -m32r-asm.c -m32r-dis.c -m32r-opc.c -m68k-dis.c -m68k-opc.c -m88k-dis.c -mips-dis.c -mips-opc.c -mips16-opc.c -ns32k-dis.c -ppc-dis.c -ppc-opc.c -sh-dis.c -sh-opc.h -sparc-dis.c -sparc-opc.c -sysdep.h -tic30-dis.c -vax-dis.c -w65-dis.c -w65-opc.h -z8k-dis.c -z8k-opc.h -z8kgen.c diff --git a/opcodes/po/opcodes.pot b/opcodes/po/opcodes.pot deleted file mode 100644 index fd755097c4d..00000000000 --- a/opcodes/po/opcodes.pot +++ /dev/null @@ -1,242 +0,0 @@ -# SOME DESCRIPTIVE TITLE. -# Copyright (C) YEAR Free Software Foundation, Inc. -# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR. -# -#, fuzzy -msgid "" -msgstr "" -"Project-Id-Version: PACKAGE VERSION\n" -"POT-Creation-Date: 1998-11-09 11:05-0500\n" -"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" -"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n" -"Language-Team: LANGUAGE <LL@li.org>\n" -"MIME-Version: 1.0\n" -"Content-Type: text/plain; charset=CHARSET\n" -"Content-Transfer-Encoding: ENCODING\n" - -#: alpha-opc.c:321 -msgid "branch operand unaligned" -msgstr "" - -#: alpha-opc.c:344 -msgid "jump hint unaligned" -msgstr "" - -#: arm-dis.c:362 -msgid "<illegal precision>" -msgstr "" - -#: cgen-asm.c:228 -msgid "unrecognized keyword/register name" -msgstr "" - -#: cgen-asm.c:336 m32r-asm.c:635 -#, c-format -msgid "operand out of range (%ld not between %ld and %ld)" -msgstr "" - -#: cgen-asm.c:357 -#, c-format -msgid "operand out of range (%lu not between %lu and %lu)" -msgstr "" - -#: d30v-dis.c:305 -#, c-format -msgid "<unknown register %d>" -msgstr "" - -#. Can't happen. -#: dis-buf.c:50 -#, c-format -msgid "Unknown error %d\n" -msgstr "" - -#: dis-buf.c:55 -#, c-format -msgid "Address 0x%x is out of bounds.\n" -msgstr "" - -#: h8300-dis.c:404 -#, c-format -msgid "Hmmmm %x" -msgstr "" - -#: h8300-dis.c:416 -#, c-format -msgid "Don't understand %x \n" -msgstr "" - -#: h8500-dis.c:139 -#, c-format -msgid "can't cope with insert %d\n" -msgstr "" - -#. Couldn't understand anything -#: h8500-dis.c:344 -#, c-format -msgid "%02x\t\t*unknown*" -msgstr "" - -#: m10200-dis.c:199 -#, c-format -msgid "unknown\t0x%02x" -msgstr "" - -#: m10200-dis.c:339 -#, c-format -msgid "unknown\t0x%04lx" -msgstr "" - -#: m10300-dis.c:706 -#, c-format -msgid "unknown\t0x%04x" -msgstr "" - -#: m32r-asm.c:327 -#, c-format -msgid "Unrecognized field %d while parsing.\n" -msgstr "" - -#: m32r-asm.c:457 -#, c-format -msgid "Unrecognized field %d while building insn.\n" -msgstr "" - -#: m32r-asm.c:622 -#, c-format -msgid "operand out of range (%lu not between 0 and %lu)" -msgstr "" - -#. We couldn't parse it. -#: m32r-asm.c:835 m32r-asm.c:904 -msgid "unrecognized instruction" -msgstr "" - -#. Syntax char didn't match. Can't be this insn. -#. FIXME: would like to return something like -#. "expected char `c'" -#: m32r-asm.c:872 -msgid "syntax error" -msgstr "" - -#: m32r-asm.c:898 -msgid "junk at end of line" -msgstr "" - -#: m32r-asm.c:1042 -#, c-format -msgid "bad instruction `%.50s...'" -msgstr "" - -#: m32r-asm.c:1045 -#, c-format -msgid "bad instruction `%.50s'" -msgstr "" - -#: m32r-dis.c:271 -#, c-format -msgid "Unrecognized field %d while decoding insn.\n" -msgstr "" - -#: m32r-dis.c:385 -#, c-format -msgid "Unrecognized field %d while printing insn.\n" -msgstr "" - -#: m32r-opc.c:2922 -#, c-format -msgid "Unrecognized field %d while getting int operand.\n" -msgstr "" - -#: m32r-opc.c:3019 -#, c-format -msgid "Unrecognized field %d while getting vma operand.\n" -msgstr "" - -#: m32r-opc.c:3120 -#, c-format -msgid "Unrecognized field %d while setting int operand.\n" -msgstr "" - -#: m32r-opc.c:3214 -#, c-format -msgid "Unrecognized field %d while setting vma operand.\n" -msgstr "" - -#: m68k-dis.c:410 -#, c-format -msgid "<internal error in opcode table: %s %s>\n" -msgstr "" - -#: m68k-dis.c:967 -#, c-format -msgid "<function code %d>" -msgstr "" - -#: m88k-dis.c:273 -#, c-format -msgid "# <dis error: %08x>" -msgstr "" - -#: mips-dis.c:373 -#, c-format -msgid "# internal error, undefined modifier(%c)" -msgstr "" - -#. I and Z are output operands and can`t be immediate -#. * A is an address and we can`t have the address of -#. * an immediate either. We don't know how much to increase -#. * aoffsetp by since whatever generated this is broken -#. * anyway! -#. -#: ns32k-dis.c:618 -msgid "$<undefined>" -msgstr "" - -#: ppc-opc.c:586 ppc-opc.c:617 -msgid "invalid conditional option" -msgstr "" - -#: ppc-opc.c:619 -msgid "attempt to set y bit when using + or - modifier" -msgstr "" - -#: ppc-opc.c:674 -msgid "ignoring least significant bits in branch offset" -msgstr "" - -#: ppc-opc.c:709 ppc-opc.c:746 -msgid "illegal bitmask" -msgstr "" - -#: ppc-opc.c:815 -msgid "value out of range" -msgstr "" - -#: ppc-opc.c:889 -msgid "index register in load range" -msgstr "" - -#: ppc-opc.c:904 -msgid "invalid register operand when updating" -msgstr "" - -#. Mark as non-valid instruction -#: sparc-dis.c:739 -msgid "unknown" -msgstr "" - -#: sparc-dis.c:811 -#, c-format -msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" -msgstr "" - -#: sparc-dis.c:822 -#, c-format -msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" -msgstr "" - -#: sparc-dis.c:871 -#, c-format -msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" -msgstr "" diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c deleted file mode 100644 index 19b16ef01e0..00000000000 --- a/opcodes/ppc-dis.c +++ /dev/null @@ -1,234 +0,0 @@ -/* ppc-dis.c -- Disassemble PowerPC instructions - Copyright 1994 Free Software Foundation, Inc. - Written by Ian Lance Taylor, Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -2, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ - -#include <stdio.h> -#include "ansidecl.h" -#include "sysdep.h" -#include "dis-asm.h" -#include "opcode/ppc.h" - -/* This file provides several disassembler functions, all of which use - the disassembler interface defined in dis-asm.h. Several functions - are provided because this file handles disassembly for the PowerPC - in both big and little endian mode and also for the POWER (RS/6000) - chip. */ - -static int print_insn_powerpc PARAMS ((bfd_vma, struct disassemble_info *, - int bigendian, int dialect)); - -/* Print a big endian PowerPC instruction. */ - -int -print_insn_big_powerpc (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_PPC); -} - -/* Print a little endian PowerPC instruction. */ - -int -print_insn_little_powerpc (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - return print_insn_powerpc (memaddr, info, 0, PPC_OPCODE_PPC); -} - -/* Print a POWER (RS/6000) instruction. */ - -int -print_insn_rs6000 (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER); -} - -/* Print a PowerPC or POWER instruction. */ - -static int -print_insn_powerpc (memaddr, info, bigendian, dialect) - bfd_vma memaddr; - struct disassemble_info *info; - int bigendian; - int dialect; -{ - bfd_byte buffer[4]; - int status; - unsigned long insn; - const struct powerpc_opcode *opcode; - const struct powerpc_opcode *opcode_end; - unsigned long op; - - status = (*info->read_memory_func) (memaddr, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - - if (bigendian) - insn = bfd_getb32 (buffer); - else - insn = bfd_getl32 (buffer); - - /* Get the major opcode of the instruction. */ - op = PPC_OP (insn); - - /* Find the first match in the opcode table. We could speed this up - a bit by doing a binary search on the major opcode. */ - opcode_end = powerpc_opcodes + powerpc_num_opcodes; - for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++) - { - unsigned long table_op; - const unsigned char *opindex; - const struct powerpc_operand *operand; - int invalid; - int need_comma; - int need_paren; - - table_op = PPC_OP (opcode->opcode); - if (op < table_op) - break; - if (op > table_op) - continue; - - if ((insn & opcode->mask) != opcode->opcode - || (opcode->flags & dialect) == 0) - continue; - - /* Make two passes over the operands. First see if any of them - have extraction functions, and, if they do, make sure the - instruction is valid. */ - invalid = 0; - for (opindex = opcode->operands; *opindex != 0; opindex++) - { - operand = powerpc_operands + *opindex; - if (operand->extract) - (*operand->extract) (insn, &invalid); - } - if (invalid) - continue; - - /* The instruction is valid. */ - (*info->fprintf_func) (info->stream, "%s", opcode->name); - if (opcode->operands[0] != 0) - (*info->fprintf_func) (info->stream, "\t"); - - /* Now extract and print the operands. */ - need_comma = 0; - need_paren = 0; - for (opindex = opcode->operands; *opindex != 0; opindex++) - { - long value; - - operand = powerpc_operands + *opindex; - - /* Operands that are marked FAKE are simply ignored. We - already made sure that the extract function considered - the instruction to be valid. */ - if ((operand->flags & PPC_OPERAND_FAKE) != 0) - continue; - - /* Extract the value from the instruction. */ - if (operand->extract) - value = (*operand->extract) (insn, (int *) NULL); - else - { - value = (insn >> operand->shift) & ((1 << operand->bits) - 1); - if (operand->signedp - && (value & (1 << (operand->bits - 1))) != 0) - value -= 1 << operand->bits; - } - - /* If the operand is optional, and the value is zero, don't - print anything. */ - if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 - && (operand->flags & PPC_OPERAND_NEXT) == 0 - && value == 0) - continue; - - if (need_comma) - { - (*info->fprintf_func) (info->stream, ","); - need_comma = 0; - } - - /* Print the operand as directed by the flags. */ - if ((operand->flags & PPC_OPERAND_GPR) != 0) - (*info->fprintf_func) (info->stream, "r%ld", value); - else if ((operand->flags & PPC_OPERAND_FPR) != 0) - (*info->fprintf_func) (info->stream, "f%ld", value); - else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) - (*info->print_address_func) (memaddr + value, info); - else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) - (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); - else if ((operand->flags & PPC_OPERAND_CR) == 0 - || (dialect & PPC_OPCODE_PPC) == 0) - (*info->fprintf_func) (info->stream, "%ld", value); - else - { - if (operand->bits == 3) - (*info->fprintf_func) (info->stream, "cr%d", value); - else - { - static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; - int cr; - int cc; - - cr = value >> 2; - if (cr != 0) - (*info->fprintf_func) (info->stream, "4*cr%d", cr); - cc = value & 3; - if (cc != 0) - { - if (cr != 0) - (*info->fprintf_func) (info->stream, "+"); - (*info->fprintf_func) (info->stream, "%s", cbnames[cc]); - } - } - } - - if (need_paren) - { - (*info->fprintf_func) (info->stream, ")"); - need_paren = 0; - } - - if ((operand->flags & PPC_OPERAND_PARENS) == 0) - need_comma = 1; - else - { - (*info->fprintf_func) (info->stream, "("); - need_paren = 1; - } - } - - /* We have found and printed an instruction; return. */ - return 4; - } - - /* We could not find a match. */ - (*info->fprintf_func) (info->stream, "0x%lx", insn); - - return 4; -} diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c deleted file mode 100644 index c7b8bd2bbc5..00000000000 --- a/opcodes/ppc-opc.c +++ /dev/null @@ -1,2830 +0,0 @@ -/* ppc-opc.c -- PowerPC opcode list - Copyright 1994 Free Software Foundation, Inc. - Written by Ian Lance Taylor, Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -2, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ - -#include <stdio.h> -#include "ansidecl.h" -#include "opcode/ppc.h" - -/* This file holds the PowerPC opcode table. The opcode table - includes almost all of the extended instruction mnemonics. This - permits the disassembler to use them, and simplifies the assembler - logic, at the cost of increasing the table size. The table is - strictly constant data, so the compiler should be able to put it in - the .text section. - - This file also holds the operand table. All knowledge about - inserting operands into instructions and vice-versa is kept in this - file. */ - -/* Local insertion and extraction functions. */ - -static unsigned long insert_bat PARAMS ((unsigned long, long, const char **)); -static long extract_bat PARAMS ((unsigned long, int *)); -static unsigned long insert_bba PARAMS ((unsigned long, long, const char **)); -static long extract_bba PARAMS ((unsigned long, int *)); -static unsigned long insert_bd PARAMS ((unsigned long, long, const char **)); -static long extract_bd PARAMS ((unsigned long, int *)); -static unsigned long insert_bdm PARAMS ((unsigned long, long, const char **)); -static long extract_bdm PARAMS ((unsigned long, int *)); -static unsigned long insert_bdp PARAMS ((unsigned long, long, const char **)); -static long extract_bdp PARAMS ((unsigned long, int *)); -static unsigned long insert_bo PARAMS ((unsigned long, long, const char **)); -static long extract_bo PARAMS ((unsigned long, int *)); -static unsigned long insert_boe PARAMS ((unsigned long, long, const char **)); -static long extract_boe PARAMS ((unsigned long, int *)); -static unsigned long insert_cr PARAMS ((unsigned long, long, const char **)); -static long extract_cr PARAMS ((unsigned long, int *)); -static unsigned long insert_ds PARAMS ((unsigned long, long, const char **)); -static long extract_ds PARAMS ((unsigned long, int *)); -static unsigned long insert_li PARAMS ((unsigned long, long, const char **)); -static long extract_li PARAMS ((unsigned long, int *)); -static unsigned long insert_mbe PARAMS ((unsigned long, long, const char **)); -static long extract_mbe PARAMS ((unsigned long, int *)); -static unsigned long insert_mb6 PARAMS ((unsigned long, long, const char **)); -static long extract_mb6 PARAMS ((unsigned long, int *)); -static unsigned long insert_nb PARAMS ((unsigned long, long, const char **)); -static long extract_nb PARAMS ((unsigned long, int *)); -static unsigned long insert_nsi PARAMS ((unsigned long, long, const char **)); -static long extract_nsi PARAMS ((unsigned long, int *)); -static unsigned long insert_ral PARAMS ((unsigned long, long, const char **)); -static unsigned long insert_ram PARAMS ((unsigned long, long, const char **)); -static unsigned long insert_ras PARAMS ((unsigned long, long, const char **)); -static unsigned long insert_rbs PARAMS ((unsigned long, long, const char **)); -static long extract_rbs PARAMS ((unsigned long, int *)); -static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char **)); -static long extract_sh6 PARAMS ((unsigned long, int *)); -static unsigned long insert_spr PARAMS ((unsigned long, long, const char **)); -static long extract_spr PARAMS ((unsigned long, int *)); -static unsigned long insert_tbr PARAMS ((unsigned long, long, const char **)); -static long extract_tbr PARAMS ((unsigned long, int *)); - -/* The operands table. - - The fields are bits, shift, signed, insert, extract, flags. */ - -const struct powerpc_operand powerpc_operands[] = -{ - /* The zero index is used to indicate the end of the list of - operands. */ -#define UNUSED (0) - { 0, 0, 0, 0, 0 }, - - /* The BA field in an XL form instruction. */ -#define BA (UNUSED + 1) -#define BA_MASK (0x1f << 16) - { 5, 16, 0, 0, PPC_OPERAND_CR }, - - /* The BA field in an XL form instruction when it must be the same - as the BT field in the same instruction. */ -#define BAT (BA + 1) - { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, - - /* The BB field in an XL form instruction. */ -#define BB (BAT + 1) -#define BB_MASK (0x1f << 11) - { 5, 11, 0, 0, PPC_OPERAND_CR }, - - /* The BB field in an XL form instruction when it must be the same - as the BA field in the same instruction. */ -#define BBA (BB + 1) - { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, - - /* The BD field in a B form instruction. The lower two bits are - forced to zero. */ -#define BD (BBA + 1) - { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when absolute addressing is - used. */ -#define BDA (BD + 1) - { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when the - modifier is used. - This sets the y bit of the BO field appropriately. */ -#define BDM (BDA + 1) - { 16, 0, insert_bdm, extract_bdm, - PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when the - modifier is used - and absolute address is used. */ -#define BDMA (BDM + 1) - { 16, 0, insert_bdm, extract_bdm, - PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when the + modifier is used. - This sets the y bit of the BO field appropriately. */ -#define BDP (BDMA + 1) - { 16, 0, insert_bdp, extract_bdp, - PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when the + modifier is used - and absolute addressing is used. */ -#define BDPA (BDP + 1) - { 16, 0, insert_bdp, extract_bdp, - PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, - - /* The BF field in an X or XL form instruction. */ -#define BF (BDPA + 1) - { 3, 23, 0, 0, PPC_OPERAND_CR }, - - /* An optional BF field. This is used for comparison instructions, - in which an omitted BF field is taken as zero. */ -#define OBF (BF + 1) - { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, - - /* The BFA field in an X or XL form instruction. */ -#define BFA (OBF + 1) - { 3, 18, 0, 0, PPC_OPERAND_CR }, - - /* The BI field in a B form or XL form instruction. */ -#define BI (BFA + 1) -#define BI_MASK (0x1f << 16) - { 5, 16, 0, 0, PPC_OPERAND_CR }, - - /* The BO field in a B form instruction. Certain values are - illegal. */ -#define BO (BI + 1) -#define BO_MASK (0x1f << 21) - { 5, 21, insert_bo, extract_bo, 0 }, - - /* The BO field in a B form instruction when the + or - modifier is - used. This is like the BO field, but it must be even. */ -#define BOE (BO + 1) - { 5, 21, insert_boe, extract_boe, 0 }, - - /* The BT field in an X or XL form instruction. */ -#define BT (BOE + 1) - { 5, 21, 0, 0, PPC_OPERAND_CR }, - - /* The condition register number portion of the BI field in a B form - or XL form instruction. This is used for the extended - conditional branch mnemonics, which set the lower two bits of the - BI field. This field is optional. */ -#define CR (BT + 1) - { 5, 16, insert_cr, extract_cr, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, - - /* The D field in a D form instruction. This is a displacement off - a register, and implies that the next operand is a register in - parentheses. */ -#define D (CR + 1) - { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, - - /* The DS field in a DS form instruction. This is like D, but the - lower two bits are forced to zero. */ -#define DS (D + 1) - { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, - - /* The FL1 field in a POWER SC form instruction. */ -#define FL1 (DS + 1) - { 4, 12, 0, 0, 0 }, - - /* The FL2 field in a POWER SC form instruction. */ -#define FL2 (FL1 + 1) - { 3, 2, 0, 0, 0 }, - - /* The FLM field in an XFL form instruction. */ -#define FLM (FL2 + 1) - { 8, 17, 0, 0, 0 }, - - /* The FRA field in an X or A form instruction. */ -#define FRA (FLM + 1) -#define FRA_MASK (0x1f << 16) - { 5, 16, 0, 0, PPC_OPERAND_FPR }, - - /* The FRB field in an X or A form instruction. */ -#define FRB (FRA + 1) -#define FRB_MASK (0x1f << 11) - { 5, 11, 0, 0, PPC_OPERAND_FPR }, - - /* The FRC field in an A form instruction. */ -#define FRC (FRB + 1) -#define FRC_MASK (0x1f << 6) - { 5, 6, 0, 0, PPC_OPERAND_FPR }, - - /* The FRS field in an X form instruction or the FRT field in a D, X - or A form instruction. */ -#define FRS (FRC + 1) -#define FRT (FRS) - { 5, 21, 0, 0, PPC_OPERAND_FPR }, - - /* The FXM field in an XFX instruction. */ -#define FXM (FRS + 1) -#define FXM_MASK (0xff << 12) - { 8, 12, 0, 0, 0 }, - - /* The L field in a D or X form instruction. */ -#define L (FXM + 1) - { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL }, - - /* The LEV field in a POWER SC form instruction. */ -#define LEV (L + 1) - { 7, 5, 0, 0, 0 }, - - /* The LI field in an I form instruction. The lower two bits are - forced to zero. */ -#define LI (LEV + 1) - { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, - - /* The LI field in an I form instruction when used as an absolute - address. */ -#define LIA (LI + 1) - { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, - - /* The MB field in an M form instruction. */ -#define MB (LIA + 1) -#define MB_MASK (0x1f << 6) - { 5, 6, 0, 0, 0 }, - - /* The ME field in an M form instruction. */ -#define ME (MB + 1) -#define ME_MASK (0x1f << 1) - { 5, 1, 0, 0, 0 }, - - /* The MB and ME fields in an M form instruction expressed a single - operand which is a bitmask indicating which bits to select. This - is a two operand form using PPC_OPERAND_NEXT. See the - description in opcode/ppc.h for what this means. */ -#define MBE (ME + 1) - { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, - { 32, 0, insert_mbe, extract_mbe, 0 }, - - /* The MB or ME field in an MD or MDS form instruction. The high - bit is wrapped to the low end. */ -#define MB6 (MBE + 2) -#define ME6 (MB6) -#define MB6_MASK (0x3f << 5) - { 6, 5, insert_mb6, extract_mb6, 0 }, - - /* The NB field in an X form instruction. The value 32 is stored as - 0. */ -#define NB (MB6 + 1) - { 6, 11, insert_nb, extract_nb, 0 }, - - /* The NSI field in a D form instruction. This is the same as the - SI field, only negated. */ -#define NSI (NB + 1) - { 16, 0, insert_nsi, extract_nsi, - PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, - - /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */ -#define RA (NSI + 1) -#define RA_MASK (0x1f << 16) - { 5, 16, 0, 0, PPC_OPERAND_GPR }, - - /* The RA field in a D or X form instruction which is an updating - load, which means that the RA field may not be zero and may not - equal the RT field. */ -#define RAL (RA + 1) - { 5, 16, insert_ral, 0, PPC_OPERAND_GPR }, - - /* The RA field in an lmw instruction, which has special value - restrictions. */ -#define RAM (RAL + 1) - { 5, 16, insert_ram, 0, PPC_OPERAND_GPR }, - - /* The RA field in a D or X form instruction which is an updating - store or an updating floating point load, which means that the RA - field may not be zero. */ -#define RAS (RAM + 1) - { 5, 16, insert_ras, 0, PPC_OPERAND_GPR }, - - /* The RB field in an X, XO, M, or MDS form instruction. */ -#define RB (RAS + 1) -#define RB_MASK (0x1f << 11) - { 5, 11, 0, 0, PPC_OPERAND_GPR }, - - /* The RB field in an X form instruction when it must be the same as - the RS field in the instruction. This is used for extended - mnemonics like mr. */ -#define RBS (RB + 1) - { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, - - /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form - instruction or the RT field in a D, DS, X, XFX or XO form - instruction. */ -#define RS (RBS + 1) -#define RT (RS) -#define RT_MASK (0x1f << 21) - { 5, 21, 0, 0, PPC_OPERAND_GPR }, - - /* The SH field in an X or M form instruction. */ -#define SH (RS + 1) -#define SH_MASK (0x1f << 11) - { 5, 11, 0, 0, 0 }, - - /* The SH field in an MD form instruction. This is split. */ -#define SH6 (SH + 1) -#define SH6_MASK ((0x1f << 11) | (1 << 1)) - { 6, 1, insert_sh6, extract_sh6, 0 }, - - /* The SI field in a D form instruction. */ -#define SI (SH6 + 1) - { 16, 0, 0, 0, PPC_OPERAND_SIGNED }, - - /* The SI field in a D form instruction when we accept a wide range - of positive values. */ -#define SISIGNOPT (SI + 1) - { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, - - /* The SPR field in an XFX form instruction. This is flipped--the - lower 5 bits are stored in the upper 5 and vice- versa. */ -#define SPR (SISIGNOPT + 1) -#define SPR_MASK (0x3ff << 11) - { 10, 11, insert_spr, extract_spr, 0 }, - - /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ -#define SPRBAT (SPR + 1) -#define SPRBAT_MASK (0x3 << 17) - { 2, 17, 0, 0, 0 }, - - /* The SPRG register number in an XFX form m[ft]sprg instruction. */ -#define SPRG (SPRBAT + 1) -#define SPRG_MASK (0x3 << 16) - { 2, 16, 0, 0, 0 }, - - /* The SR field in an X form instruction. */ -#define SR (SPRG + 1) - { 4, 16, 0, 0, 0 }, - - /* The SV field in a POWER SC form instruction. */ -#define SV (SR + 1) - { 14, 2, 0, 0, 0 }, - - /* The TBR field in an XFX form instruction. This is like the SPR - field, but it is optional. */ -#define TBR (SV + 1) - { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL }, - - /* The TO field in a D or X form instruction. */ -#define TO (TBR + 1) -#define TO_MASK (0x1f << 21) - { 5, 21, 0, 0, 0 }, - - /* The U field in an X form instruction. */ -#define U (TO + 1) - { 4, 12, 0, 0, 0 }, - - /* The UI field in a D form instruction. */ -#define UI (U + 1) - { 16, 0, 0, 0, 0 }, -}; - -/* The functions used to insert and extract complicated operands. */ - -/* The BA field in an XL form instruction when it must be the same as - the BT field in the same instruction. This operand is marked FAKE. - The insertion function just copies the BT field into the BA field, - and the extraction function just checks that the fields are the - same. */ - -/*ARGSUSED*/ -static unsigned long -insert_bat (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - return insn | (((insn >> 21) & 0x1f) << 16); -} - -static long -extract_bat (insn, invalid) - unsigned long insn; - int *invalid; -{ - if (invalid != (int *) NULL - && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) - *invalid = 1; - return 0; -} - -/* The BB field in an XL form instruction when it must be the same as - the BA field in the same instruction. This operand is marked FAKE. - The insertion function just copies the BA field into the BB field, - and the extraction function just checks that the fields are the - same. */ - -/*ARGSUSED*/ -static unsigned long -insert_bba (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - return insn | (((insn >> 16) & 0x1f) << 11); -} - -static long -extract_bba (insn, invalid) - unsigned long insn; - int *invalid; -{ - if (invalid != (int *) NULL - && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) - *invalid = 1; - return 0; -} - -/* The BD field in a B form instruction. The lower two bits are - forced to zero. */ - -/*ARGSUSED*/ -static unsigned long -insert_bd (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - return insn | (value & 0xfffc); -} - -/*ARGSUSED*/ -static long -extract_bd (insn, invalid) - unsigned long insn; - int *invalid; -{ - if ((insn & 0x8000) != 0) - return (insn & 0xfffc) - 0x10000; - else - return insn & 0xfffc; -} - -/* The BD field in a B form instruction when the - modifier is used. - This modifier means that the branch is not expected to be taken. - We must set the y bit of the BO field to 1 if the offset is - negative. When extracting, we require that the y bit be 1 and that - the offset be positive, since if the y bit is 0 we just want to - print the normal form of the instruction. */ - -/*ARGSUSED*/ -static unsigned long -insert_bdm (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - if ((value & 0x8000) != 0) - insn |= 1 << 21; - return insn | (value & 0xfffc); -} - -static long -extract_bdm (insn, invalid) - unsigned long insn; - int *invalid; -{ - if (invalid != (int *) NULL - && ((insn & (1 << 21)) == 0 - || (insn & (1 << 15) == 0))) - *invalid = 1; - if ((insn & 0x8000) != 0) - return (insn & 0xfffc) - 0x10000; - else - return insn & 0xfffc; -} - -/* The BD field in a B form instruction when the + modifier is used. - This is like BDM, above, except that the branch is expected to be - taken. */ - -/*ARGSUSED*/ -static unsigned long -insert_bdp (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - if ((value & 0x8000) == 0) - insn |= 1 << 21; - return insn | (value & 0xfffc); -} - -static long -extract_bdp (insn, invalid) - unsigned long insn; - int *invalid; -{ - if (invalid != (int *) NULL - && ((insn & (1 << 21)) == 0 - || (insn & (1 << 15)) != 0)) - *invalid = 1; - if ((insn & 0x8000) != 0) - return (insn & 0xfffc) - 0x10000; - else - return insn & 0xfffc; -} - -/* Check for legal values of a BO field. */ - -static int -valid_bo (value) - long value; -{ - /* Certain encodings have bits that are required to be zero. These - are (z must be zero, y may be anything): - 001zy - 011zy - 1z00y - 1z01y - 1z1zz - */ - switch (value & 0x14) - { - default: - case 0: - return 1; - case 0x4: - return (value & 0x2) == 0; - case 0x10: - return (value & 0x8) == 0; - case 0x14: - return value == 0x14; - } -} - -/* The BO field in a B form instruction. Warn about attempts to set - the field to an illegal value. */ - -static unsigned long -insert_bo (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - if (errmsg != (const char **) NULL - && ! valid_bo (value)) - *errmsg = "invalid conditional option"; - return insn | ((value & 0x1f) << 21); -} - -static long -extract_bo (insn, invalid) - unsigned long insn; - int *invalid; -{ - long value; - - value = (insn >> 21) & 0x1f; - if (invalid != (int *) NULL - && ! valid_bo (value)) - *invalid = 1; - return value; -} - -/* The BO field in a B form instruction when the + or - modifier is - used. This is like the BO field, but it must be even. When - extracting it, we force it to be even. */ - -static unsigned long -insert_boe (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - if (errmsg != (const char **) NULL) - { - if (! valid_bo (value)) - *errmsg = "invalid conditional option"; - else if ((value & 1) != 0) - *errmsg = "attempt to set y bit when using + or - modifier"; - } - return insn | ((value & 0x1f) << 21); -} - -static long -extract_boe (insn, invalid) - unsigned long insn; - int *invalid; -{ - long value; - - value = (insn >> 21) & 0x1f; - if (invalid != (int *) NULL - && ! valid_bo (value)) - *invalid = 1; - return value & 0x1e; -} - -/* The condition register number portion of the BI field in a B form - or XL form instruction. This is used for the extended conditional - branch mnemonics, which set the lower two bits of the BI field. It - is the BI field with the lower two bits ignored. */ - -/*ARGSUSED*/ -static unsigned long -insert_cr (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - return insn | ((value & 0x1c) << 16); -} - -/*ARGSUSED*/ -static long -extract_cr (insn, invalid) - unsigned long insn; - int *invalid; -{ - return (insn >> 16) & 0x1c; -} - -/* The DS field in a DS form instruction. This is like D, but the - lower two bits are forced to zero. */ - -/*ARGSUSED*/ -static unsigned long -insert_ds (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - return insn | (value & 0xfffc); -} - -/*ARGSUSED*/ -static long -extract_ds (insn, invalid) - unsigned long insn; - int *invalid; -{ - if ((insn & 0x8000) != 0) - return (insn & 0xfffc) - 0x10000; - else - return insn & 0xfffc; -} - -/* The LI field in an I form instruction. The lower two bits are - forced to zero. */ - -/*ARGSUSED*/ -static unsigned long -insert_li (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - return insn | (value & 0x3fffffc); -} - -/*ARGSUSED*/ -static long -extract_li (insn, invalid) - unsigned long insn; - int *invalid; -{ - if ((insn & 0x2000000) != 0) - return (insn & 0x3fffffc) - 0x4000000; - else - return insn & 0x3fffffc; -} - -/* The MB and ME fields in an M form instruction expressed as a single - operand which is itself a bitmask. The extraction function always - marks it as invalid, since we never want to recognize an - instruction which uses a field of this type. */ - -static unsigned long -insert_mbe (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - unsigned long uval; - int mb, me; - - uval = value; - - if (uval == 0) - { - if (errmsg != (const char **) NULL) - *errmsg = "illegal bitmask"; - return insn; - } - - me = 31; - while ((uval & 1) == 0) - { - uval >>= 1; - --me; - } - - mb = me; - uval >>= 1; - while ((uval & 1) != 0) - { - uval >>= 1; - --mb; - } - - if (uval != 0) - { - if (errmsg != (const char **) NULL) - *errmsg = "illegal bitmask"; - } - - return insn | (mb << 6) | (me << 1); -} - -static long -extract_mbe (insn, invalid) - unsigned long insn; - int *invalid; -{ - long ret; - int mb, me; - int i; - - if (invalid != (int *) NULL) - *invalid = 1; - - ret = 0; - mb = (insn >> 6) & 0x1f; - me = (insn >> 1) & 0x1f; - for (i = mb; i < me; i++) - ret |= 1 << (31 - i); - return ret; -} - -/* The MB or ME field in an MD or MDS form instruction. The high bit - is wrapped to the low end. */ - -/*ARGSUSED*/ -static unsigned long -insert_mb6 (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - return insn | ((value & 0x1f) << 6) | (value & 0x20); -} - -/*ARGSUSED*/ -static long -extract_mb6 (insn, invalid) - unsigned long insn; - int *invalid; -{ - return ((insn >> 6) & 0x1f) | (insn & 0x20); -} - -/* The NB field in an X form instruction. The value 32 is stored as - 0. */ - -static unsigned long -insert_nb (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - if (value < 0 || value > 32) - *errmsg = "value out of range"; - if (value == 32) - value = 0; - return insn | ((value & 0x1f) << 11); -} - -/*ARGSUSED*/ -static long -extract_nb (insn, invalid) - unsigned long insn; - int *invalid; -{ - long ret; - - ret = (insn >> 11) & 0x1f; - if (ret == 0) - ret = 32; - return ret; -} - -/* The NSI field in a D form instruction. This is the same as the SI - field, only negated. The extraction function always marks it as - invalid, since we never want to recognize an instruction which uses - a field of this type. */ - -/*ARGSUSED*/ -static unsigned long -insert_nsi (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - return insn | ((- value) & 0xffff); -} - -static long -extract_nsi (insn, invalid) - unsigned long insn; - int *invalid; -{ - if (invalid != (int *) NULL) - *invalid = 1; - if ((insn & 0x8000) != 0) - return - ((insn & 0xffff) - 0x10000); - else - return - (insn & 0xffff); -} - -/* The RA field in a D or X form instruction which is an updating - load, which means that the RA field may not be zero and may not - equal the RT field. */ - -static unsigned long -insert_ral (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - if (value == 0 - || value == ((insn >> 21) & 0x1f)) - *errmsg = "invalid register operand when updating"; - return insn | ((value & 0x1f) << 16); -} - -/* The RA field in an lmw instruction, which has special value - restrictions. */ - -static unsigned long -insert_ram (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - if (value >= ((insn >> 21) & 0x1f)) - *errmsg = "index register in load range"; - return insn | ((value & 0x1f) << 16); -} - -/* The RA field in a D or X form instruction which is an updating - store or an updating floating point load, which means that the RA - field may not be zero. */ - -static unsigned long -insert_ras (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - if (value == 0) - *errmsg = "invalid register operand when updating"; - return insn | ((value & 0x1f) << 16); -} - -/* The RB field in an X form instruction when it must be the same as - the RS field in the instruction. This is used for extended - mnemonics like mr. This operand is marked FAKE. The insertion - function just copies the BT field into the BA field, and the - extraction function just checks that the fields are the same. */ - -/*ARGSUSED*/ -static unsigned long -insert_rbs (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - return insn | (((insn >> 21) & 0x1f) << 11); -} - -static long -extract_rbs (insn, invalid) - unsigned long insn; - int *invalid; -{ - if (invalid != (int *) NULL - && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) - *invalid = 1; - return 0; -} - -/* The SH field in an MD form instruction. This is split. */ - -/*ARGSUSED*/ -static unsigned long -insert_sh6 (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); -} - -/*ARGSUSED*/ -static long -extract_sh6 (insn, invalid) - unsigned long insn; - int *invalid; -{ - return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); -} - -/* The SPR field in an XFX form instruction. This is flipped--the - lower 5 bits are stored in the upper 5 and vice- versa. */ - -static unsigned long -insert_spr (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); -} - -static long -extract_spr (insn, invalid) - unsigned long insn; - int *invalid; -{ - return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); -} - -/* The TBR field in an XFX instruction. This is just like SPR, but it - is optional. When TBR is omitted, it must be inserted as 268 (the - magic number of the TB register). These functions treat 0 - (indicating an omitted optional operand) as 268. This means that - ``mftb 4,0'' is not handled correctly. This does not matter very - much, since the architecture manual does not define mftb as - accepting any values other than 268 or 269. */ - -#define TB (268) - -static unsigned long -insert_tbr (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - if (value == 0) - value = TB; - return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); -} - -static long -extract_tbr (insn, invalid) - unsigned long insn; - int *invalid; -{ - long ret; - - ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); - if (ret == TB) - ret = 0; - return ret; -} - -/* Macros used to form opcodes. */ - -/* The main opcode. */ -#define OP(x) (((x) & 0x3f) << 26) -#define OP_MASK OP (0x3f) - -/* The main opcode combined with a trap code in the TO field of a D - form instruction. Used for extended mnemonics for the trap - instructions. */ -#define OPTO(x,to) (OP (x) | (((to) & 0x1f) << 21)) -#define OPTO_MASK (OP_MASK | TO_MASK) - -/* The main opcode combined with a comparison size bit in the L field - of a D form or X form instruction. Used for extended mnemonics for - the comparison instructions. */ -#define OPL(x,l) (OP (x) | (((l) & 1) << 21)) -#define OPL_MASK OPL (0x3f,1) - -/* An A form instruction. */ -#define A(op, xop, rc) (OP (op) | (((xop) & 0x1f) << 1) | ((rc) & 1)) -#define A_MASK A (0x3f, 0x1f, 1) - -/* An A_MASK with the FRB field fixed. */ -#define AFRB_MASK (A_MASK | FRB_MASK) - -/* An A_MASK with the FRC field fixed. */ -#define AFRC_MASK (A_MASK | FRC_MASK) - -/* An A_MASK with the FRA and FRC fields fixed. */ -#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) - -/* A B form instruction. */ -#define B(op, aa, lk) (OP (op) | (((aa) & 1) << 1) | ((lk) & 1)) -#define B_MASK B (0x3f, 1, 1) - -/* A B form instruction setting the BO field. */ -#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | (((bo) & 0x1f) << 21)) -#define BBO_MASK BBO (0x3f, 0x1f, 1, 1) - -/* A BBO_MASK with the y bit of the BO field removed. This permits - matching a conditional branch regardless of the setting of the y - bit. */ -#define Y_MASK (1 << 21) -#define BBOY_MASK (BBO_MASK &~ Y_MASK) - -/* A B form instruction setting the BO field and the condition bits of - the BI field. */ -#define BBOCB(op, bo, cb, aa, lk) \ - (BBO ((op), (bo), (aa), (lk)) | (((cb) & 0x3) << 16)) -#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) - -/* A BBOCB_MASK with the y bit of the BO field removed. */ -#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) - -/* A BBOYCB_MASK in which the BI field is fixed. */ -#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) - -/* The main opcode mask with the RA field clear. */ -#define DRA_MASK (OP_MASK | RA_MASK) - -/* A DS form instruction. */ -#define DSO(op, xop) (OP (op) | ((xop) & 0x3)) -#define DS_MASK DSO (0x3f, 3) - -/* An M form instruction. */ -#define M(op, rc) (OP (op) | ((rc) & 1)) -#define M_MASK M (0x3f, 1) - -/* An M form instruction with the ME field specified. */ -#define MME(op, me, rc) (M ((op), (rc)) | (((me) & 0x1f) << 1)) - -/* An M_MASK with the MB and ME fields fixed. */ -#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK) - -/* An M_MASK with the SH and ME fields fixed. */ -#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) - -/* An MD form instruction. */ -#define MD(op, xop, rc) (OP (op) | (((xop) & 0x7) << 2) | ((rc) & 1)) -#define MD_MASK MD (0x3f, 0x7, 1) - -/* An MD_MASK with the MB field fixed. */ -#define MDMB_MASK (MD_MASK | MB6_MASK) - -/* An MD_MASK with the SH field fixed. */ -#define MDSH_MASK (MD_MASK | SH6_MASK) - -/* An MDS form instruction. */ -#define MDS(op, xop, rc) (OP (op) | (((xop) & 0xf) << 1) | ((rc) & 1)) -#define MDS_MASK MDS (0x3f, 0xf, 1) - -/* An MDS_MASK with the MB field fixed. */ -#define MDSMB_MASK (MDS_MASK | MB6_MASK) - -/* An SC form instruction. */ -#define SC(op, sa, lk) (OP (op) | (((sa) & 1) << 1) | ((lk) & 1)) -#define SC_MASK (OP_MASK | (0x3ff << 16) | (1 << 1) | 1) - -/* An X form instruction. */ -#define X(op, xop) (OP (op) | (((xop) & 0x3ff) << 1)) - -/* An X form instruction with the RC bit specified. */ -#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) - -/* The mask for an X form instruction. */ -#define X_MASK XRC (0x3f, 0x3ff, 1) - -/* An X_MASK with the RA field fixed. */ -#define XRA_MASK (X_MASK | RA_MASK) - -/* An X_MASK with the RB field fixed. */ -#define XRB_MASK (X_MASK | RB_MASK) - -/* An X_MASK with the RT field fixed. */ -#define XRT_MASK (X_MASK | RT_MASK) - -/* An X_MASK with the RA and RB fields fixed. */ -#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) - -/* An X_MASK with the RT and RA fields fixed. */ -#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) - -/* An X form comparison instruction. */ -#define XCMPL(op, xop, l) (X ((op), (xop)) | (((l) & 1) << 21)) - -/* The mask for an X form comparison instruction. */ -#define XCMP_MASK (X_MASK | (1 << 22)) - -/* The mask for an X form comparison instruction with the L field - fixed. */ -#define XCMPL_MASK (XCMP_MASK | (1 << 21)) - -/* An X form trap instruction with the TO field specified. */ -#define XTO(op, xop, to) (X ((op), (xop)) | (((to) & 0x1f) << 21)) -#define XTO_MASK (X_MASK | TO_MASK) - -/* An XFL form instruction. */ -#define XFL(op, xop, rc) (OP (op) | (((xop) & 0x3ff) << 1) | ((rc) & 1)) -#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (1 << 25) | (1 << 16)) - -/* An XL form instruction with the LK field set to 0. */ -#define XL(op, xop) (OP (op) | (((xop) & 0x3ff) << 1)) - -/* An XL form instruction which uses the LK field. */ -#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) - -/* The mask for an XL form instruction. */ -#define XL_MASK XLLK (0x3f, 0x3ff, 1) - -/* An XL form instruction which explicitly sets the BO field. */ -#define XLO(op, bo, xop, lk) \ - (XLLK ((op), (xop), (lk)) | (((bo) & 0x1f) << 21)) -#define XLO_MASK (XL_MASK | BO_MASK) - -/* An XL form instruction which explicitly sets the y bit of the BO - field. */ -#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | (((y) & 1) << 21)) -#define XLYLK_MASK (XL_MASK | Y_MASK) - -/* An XL form instruction which sets the BO field and the condition - bits of the BI field. */ -#define XLOCB(op, bo, cb, xop, lk) \ - (XLO ((op), (bo), (xop), (lk)) | (((cb) & 3) << 16)) -#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) - -/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */ -#define XLBB_MASK (XL_MASK | BB_MASK) -#define XLYBB_MASK (XLYLK_MASK | BB_MASK) -#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) - -/* An XL_MASK with the BO and BB fields fixed. */ -#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK) - -/* An XL_MASK with the BO, BI and BB fields fixed. */ -#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) - -/* An XO form instruction. */ -#define XO(op, xop, oe, rc) \ - (OP (op) | (((xop) & 0x1ff) << 1) | (((oe) & 1) << 10) | ((rc) & 1)) -#define XO_MASK XO (0x3f, 0x1ff, 1, 1) - -/* An XO_MASK with the RB field fixed. */ -#define XORB_MASK (XO_MASK | RB_MASK) - -/* An XS form instruction. */ -#define XS(op, xop, rc) (OP (op) | (((xop) & 0x1ff) << 2) | ((rc) & 1)) -#define XS_MASK XS (0x3f, 0x1ff, 1) - -/* A mask for the FXM version of an XFX form instruction. */ -#define XFXFXM_MASK (X_MASK | (1 << 20) | (1 << 11)) - -/* An XFX form instruction with the FXM field filled in. */ -#define XFXM(op, xop, fxm) \ - (X ((op), (xop)) | (((fxm) & 0xff) << 12)) - -/* An XFX form instruction with the SPR field filled in. */ -#define XSPR(op, xop, spr) \ - (X ((op), (xop)) | (((spr) & 0x1f) << 16) | (((spr) & 0x3e0) << 6)) -#define XSPR_MASK (X_MASK | SPR_MASK) - -/* An XFX form instruction with the SPR field filled in except for the - SPRBAT field. */ -#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) - -/* An XFX form instruction with the SPR field filled in except for the - SPRG field. */ -#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK) - -/* The BO encodings used in extended conditional branch mnemonics. */ -#define BODNZF (0x0) -#define BODNZFP (0x1) -#define BODZF (0x2) -#define BODZFP (0x3) -#define BOF (0x4) -#define BOFP (0x5) -#define BODNZT (0x8) -#define BODNZTP (0x9) -#define BODZT (0xa) -#define BODZTP (0xb) -#define BOT (0xc) -#define BOTP (0xd) -#define BODNZ (0x10) -#define BODNZP (0x11) -#define BODZ (0x12) -#define BODZP (0x13) -#define BOU (0x14) - -/* The BI condition bit encodings used in extended conditional branch - mnemonics. */ -#define CBLT (0) -#define CBGT (1) -#define CBEQ (2) -#define CBSO (3) - -/* The TO encodings used in extended trap mnemonics. */ -#define TOLGT (0x1) -#define TOLLT (0x2) -#define TOEQ (0x4) -#define TOLGE (0x5) -#define TOLNL (0x5) -#define TOLLE (0x6) -#define TOLNG (0x6) -#define TOGT (0x8) -#define TOGE (0xc) -#define TONL (0xc) -#define TOLT (0x10) -#define TOLE (0x14) -#define TONG (0x14) -#define TONE (0x18) -#define TOU (0x1f) - -/* Smaller names for the flags so each entry in the opcodes table will - fit on a single line. */ -#define PPC PPC_OPCODE_PPC -#define POWER PPC_OPCODE_POWER -#define POWER2 PPC_OPCODE_POWER2 -#define B32 PPC_OPCODE_32 -#define B64 PPC_OPCODE_64 -#define M601 PPC_OPCODE_601 - -/* The opcode table. - - The format of the opcode table is: - - NAME OPCODE MASK FLAGS { OPERANDS } - - NAME is the name of the instruction. - OPCODE is the instruction opcode. - MASK is the opcode mask; this is used to tell the disassembler - which bits in the actual opcode must match OPCODE. - FLAGS are flags indicated what processors support the instruction. - OPERANDS is the list of operands. - - The disassembler reads the table in order and prints the first - instruction which matches, so this table is sorted to put more - specific instructions before more general instructions. It is also - sorted by major opcode. */ - -const struct powerpc_opcode powerpc_opcodes[] = { -{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC|B64, { RA, SI } }, -{ "tdi", OP(2), OP_MASK, PPC|B64, { TO, RA, SI } }, - -{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPC, { RA, SI } }, -{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, POWER, { RA, SI } }, -{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPC, { RA, SI } }, -{ "tllti", OPTO(3,TOLLT), OPTO_MASK, POWER, { RA, SI } }, -{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPC, { RA, SI } }, -{ "teqi", OPTO(3,TOEQ), OPTO_MASK, POWER, { RA, SI } }, -{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPC, { RA, SI } }, -{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, POWER, { RA, SI } }, -{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPC, { RA, SI } }, -{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, POWER, { RA, SI } }, -{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPC, { RA, SI } }, -{ "tllei", OPTO(3,TOLLE), OPTO_MASK, POWER, { RA, SI } }, -{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPC, { RA, SI } }, -{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, POWER, { RA, SI } }, -{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPC, { RA, SI } }, -{ "tgti", OPTO(3,TOGT), OPTO_MASK, POWER, { RA, SI } }, -{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPC, { RA, SI } }, -{ "tgei", OPTO(3,TOGE), OPTO_MASK, POWER, { RA, SI } }, -{ "twnli", OPTO(3,TONL), OPTO_MASK, PPC, { RA, SI } }, -{ "tnli", OPTO(3,TONL), OPTO_MASK, POWER, { RA, SI } }, -{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPC, { RA, SI } }, -{ "tlti", OPTO(3,TOLT), OPTO_MASK, POWER, { RA, SI } }, -{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPC, { RA, SI } }, -{ "tlei", OPTO(3,TOLE), OPTO_MASK, POWER, { RA, SI } }, -{ "twngi", OPTO(3,TONG), OPTO_MASK, PPC, { RA, SI } }, -{ "tngi", OPTO(3,TONG), OPTO_MASK, POWER, { RA, SI } }, -{ "twnei", OPTO(3,TONE), OPTO_MASK, PPC, { RA, SI } }, -{ "tnei", OPTO(3,TONE), OPTO_MASK, POWER, { RA, SI } }, -{ "twi", OP(3), OP_MASK, PPC, { TO, RA, SI } }, -{ "ti", OP(3), OP_MASK, POWER, { TO, RA, SI } }, - -{ "mulli", OP(7), OP_MASK, PPC, { RT, RA, SI } }, -{ "muli", OP(7), OP_MASK, POWER, { RT, RA, SI } }, - -{ "subfic", OP(8), OP_MASK, PPC, { RT, RA, SI } }, -{ "sfi", OP(8), OP_MASK, POWER, { RT, RA, SI } }, - -{ "dozi", OP(9), OP_MASK, POWER|M601, { RT, RA, SI } }, - -{ "cmplwi", OPL(10,0), OPL_MASK, PPC, { OBF, RA, UI } }, -{ "cmpldi", OPL(10,1), OPL_MASK, PPC|B64, { OBF, RA, UI } }, -{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } }, -{ "cmpli", OP(10), OP_MASK, POWER, { BF, RA, UI } }, - -{ "cmpwi", OPL(11,0), OPL_MASK, PPC, { OBF, RA, SI } }, -{ "cmpdi", OPL(11,1), OPL_MASK, PPC|B64, { OBF, RA, SI } }, -{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } }, -{ "cmpi", OP(11), OP_MASK, POWER, { BF, RA, SI } }, - -{ "addic", OP(12), OP_MASK, PPC, { RT, RA, SI } }, -{ "ai", OP(12), OP_MASK, POWER, { RT, RA, SI } }, -{ "subic", OP(12), OP_MASK, PPC, { RT, RA, NSI } }, - -{ "addic.", OP(13), OP_MASK, PPC, { RT, RA, SI } }, -{ "ai.", OP(13), OP_MASK, POWER, { RT, RA, SI } }, -{ "subic.", OP(13), OP_MASK, PPC, { RT, RA, NSI } }, - -{ "li", OP(14), DRA_MASK, PPC, { RT, SI } }, -{ "lil", OP(14), DRA_MASK, POWER, { RT, SI } }, -{ "addi", OP(14), OP_MASK, PPC, { RT, RA, SI } }, -{ "cal", OP(14), OP_MASK, POWER, { RT, D, RA } }, -{ "subi", OP(14), OP_MASK, PPC, { RT, RA, NSI } }, -{ "la", OP(14), OP_MASK, PPC, { RT, D, RA } }, - -{ "lis", OP(15), DRA_MASK, PPC, { RT, SISIGNOPT } }, -{ "liu", OP(15), DRA_MASK, POWER, { RT, SISIGNOPT } }, -{ "addis", OP(15), OP_MASK, PPC, { RT,RA,SISIGNOPT } }, -{ "cau", OP(15), OP_MASK, POWER, { RT,RA,SISIGNOPT } }, -{ "subis", OP(15), OP_MASK, PPC, { RT, RA, NSI } }, - -{ "bdnz-", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDM } }, -{ "bdnz+", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDP } }, -{ "bdnz", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BD } }, -{ "bdn", BBO(16,BODNZ,0,0), BBOYBI_MASK, POWER, { BD } }, -{ "bdnzl-", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDM } }, -{ "bdnzl+", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDP } }, -{ "bdnzl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BD } }, -{ "bdnl", BBO(16,BODNZ,0,1), BBOYBI_MASK, POWER, { BD } }, -{ "bdnza-", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDMA } }, -{ "bdnza+", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDPA } }, -{ "bdnza", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDA } }, -{ "bdna", BBO(16,BODNZ,1,0), BBOYBI_MASK, POWER, { BDA } }, -{ "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDMA } }, -{ "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDPA } }, -{ "bdnzla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDA } }, -{ "bdnla", BBO(16,BODNZ,1,1), BBOYBI_MASK, POWER, { BDA } }, -{ "bdz-", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDM } }, -{ "bdz+", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDP } }, -{ "bdz", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC|POWER, { BD } }, -{ "bdzl-", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDM } }, -{ "bdzl+", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDP } }, -{ "bdzl", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC|POWER, { BD } }, -{ "bdza-", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDMA } }, -{ "bdza+", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDPA } }, -{ "bdza", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC|POWER, { BDA } }, -{ "bdzla-", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDMA } }, -{ "bdzla+", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDPA } }, -{ "bdzla", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC|POWER, { BDA } }, -{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BD } }, -{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BD } }, -{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDA } }, -{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDA } }, -{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, -{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, -{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BD } }, -{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, -{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, -{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BD } }, -{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDA } }, -{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, -{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, -{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDA } }, -{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDM } }, -{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDP } }, -{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BD } }, -{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDM } }, -{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDP } }, -{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BD } }, -{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDA } }, -{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDA } }, -{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDM } }, -{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDP } }, -{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BD } }, -{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDM } }, -{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDP } }, -{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BD } }, -{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDA } }, -{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDA } }, -{ "bt-", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDM } }, -{ "bt+", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDP } }, -{ "bt", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BD } }, -{ "bbt", BBO(16,BOT,0,0), BBOY_MASK, POWER, { BI, BD } }, -{ "btl-", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDM } }, -{ "btl+", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDP } }, -{ "btl", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BD } }, -{ "bbtl", BBO(16,BOT,0,1), BBOY_MASK, POWER, { BI, BD } }, -{ "bta-", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bta+", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bta", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDA } }, -{ "bbta", BBO(16,BOT,1,0), BBOY_MASK, POWER, { BI, BDA } }, -{ "btla-", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDMA } }, -{ "btla+", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDPA } }, -{ "btla", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDA } }, -{ "bbtla", BBO(16,BOT,1,1), BBOY_MASK, POWER, { BI, BDA } }, -{ "bf-", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDM } }, -{ "bf+", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDP } }, -{ "bf", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BD } }, -{ "bbf", BBO(16,BOF,0,0), BBOY_MASK, POWER, { BI, BD } }, -{ "bfl-", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDM } }, -{ "bfl+", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDP } }, -{ "bfl", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BD } }, -{ "bbfl", BBO(16,BOF,0,1), BBOY_MASK, POWER, { BI, BD } }, -{ "bfa-", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bfa+", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bfa", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDA } }, -{ "bbfa", BBO(16,BOF,1,0), BBOY_MASK, POWER, { BI, BDA } }, -{ "bfla-", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bfla+", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bfla", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDA } }, -{ "bbfla", BBO(16,BOF,1,1), BBOY_MASK, POWER, { BI, BDA } }, -{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDM } }, -{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDP } }, -{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BD } }, -{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDM } }, -{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDP } }, -{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BD } }, -{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDA } }, -{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDA } }, -{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDM } }, -{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDP } }, -{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BD } }, -{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDM } }, -{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDP } }, -{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BD } }, -{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDA } }, -{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDMA } }, -{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDPA } }, -{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDA } }, -{ "bc-", B(16,0,0), B_MASK, PPC, { BOE, BI, BDM } }, -{ "bc+", B(16,0,0), B_MASK, PPC, { BOE, BI, BDP } }, -{ "bc", B(16,0,0), B_MASK, PPC|POWER, { BO, BI, BD } }, -{ "bcl-", B(16,0,1), B_MASK, PPC, { BOE, BI, BDM } }, -{ "bcl+", B(16,0,1), B_MASK, PPC, { BOE, BI, BDP } }, -{ "bcl", B(16,0,1), B_MASK, PPC|POWER, { BO, BI, BD } }, -{ "bca-", B(16,1,0), B_MASK, PPC, { BOE, BI, BDMA } }, -{ "bca+", B(16,1,0), B_MASK, PPC, { BOE, BI, BDPA } }, -{ "bca", B(16,1,0), B_MASK, PPC|POWER, { BO, BI, BDA } }, -{ "bcla-", B(16,1,1), B_MASK, PPC, { BOE, BI, BDMA } }, -{ "bcla+", B(16,1,1), B_MASK, PPC, { BOE, BI, BDPA } }, -{ "bcla", B(16,1,1), B_MASK, PPC|POWER, { BO, BI, BDA } }, - -{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } }, -{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } }, -{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } }, -{ "svca", SC(17,1,0), SC_MASK, POWER, { SV } }, -{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } }, - -{ "b", B(18,0,0), B_MASK, PPC|POWER, { LI } }, -{ "bl", B(18,0,1), B_MASK, PPC|POWER, { LI } }, -{ "ba", B(18,1,0), B_MASK, PPC|POWER, { LIA } }, -{ "bla", B(18,1,1), B_MASK, PPC|POWER, { LIA } }, - -{ "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } }, - -{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPC, { 0 } }, -{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, POWER, { 0 } }, -{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPC, { 0 } }, -{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, POWER, { 0 } }, -{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPC, { 0 } }, -{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } }, -{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } }, -{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } }, -{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } }, -{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } }, -{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } }, -{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } }, -{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } }, -{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } }, -{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } }, -{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } }, -{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } }, -{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } }, -{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } }, -{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } }, -{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } }, -{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } }, -{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } }, -{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } }, -{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } }, -{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, POWER, { BI } }, -{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, POWER, { BI } }, -{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, POWER, { BI } }, -{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, POWER, { BI } }, -{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPC, { BI } }, -{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPC, { BI } }, -{ "bclr", XLLK(19,16,0), XLYBB_MASK, PPC, { BO, BI } }, -{ "bclrl", XLLK(19,16,1), XLYBB_MASK, PPC, { BO, BI } }, -{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPC, { BOE, BI } }, -{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPC, { BOE, BI } }, -{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPC, { BOE, BI } }, -{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPC, { BOE, BI } }, -{ "bcr", XLLK(19,16,0), XLBB_MASK, POWER, { BO, BI } }, -{ "bcrl", XLLK(19,16,1), XLBB_MASK, POWER, { BO, BI } }, - -{ "crnot", XL(19,33), XL_MASK, PPC, { BT, BA, BBA } }, -{ "crnor", XL(19,33), XL_MASK, PPC|POWER, { BT, BA, BB } }, - -{ "rfi", XL(19,50), 0xffffffff, PPC|POWER, { 0 } }, - -{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } }, - -{ "crandc", XL(19,129), XL_MASK, PPC|POWER, { BT, BA, BB } }, - -{ "isync", XL(19,150), 0xffffffff, PPC, { 0 } }, -{ "ics", XL(19,150), 0xffffffff, POWER, { 0 } }, - -{ "crclr", XL(19,193), XL_MASK, PPC, { BT, BAT, BBA } }, -{ "crxor", XL(19,193), XL_MASK, PPC|POWER, { BT, BA, BB } }, - -{ "crnand", XL(19,225), XL_MASK, PPC|POWER, { BT, BA, BB } }, - -{ "crand", XL(19,257), XL_MASK, PPC|POWER, { BT, BA, BB } }, - -{ "crset", XL(19,289), XL_MASK, PPC, { BT, BAT, BBA } }, -{ "creqv", XL(19,289), XL_MASK, PPC|POWER, { BT, BA, BB } }, - -{ "crorc", XL(19,417), XL_MASK, PPC|POWER, { BT, BA, BB } }, - -{ "crmove", XL(19,449), XL_MASK, PPC, { BT, BA, BBA } }, -{ "cror", XL(19,449), XL_MASK, PPC|POWER, { BT, BA, BB } }, - -{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, PPC|POWER, { 0 } }, -{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, PPC|POWER, { 0 } }, -{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, -{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } }, -{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } }, -{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPC, { BI } }, -{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } }, -{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } }, -{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPC, { BI } }, -{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } }, -{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } }, -{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPC, { BI } }, -{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } }, -{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } }, -{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPC, { BI } }, -{ "bcctr", XLLK(19,528,0), XLYBB_MASK, PPC, { BO, BI } }, -{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPC, { BOE, BI } }, -{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPC, { BOE, BI } }, -{ "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPC, { BO, BI } }, -{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPC, { BOE, BI } }, -{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPC, { BOE, BI } }, -{ "bcc", XLLK(19,528,0), XLBB_MASK, POWER, { BO, BI } }, -{ "bccl", XLLK(19,528,1), XLBB_MASK, POWER, { BO, BI } }, - -{ "rlwimi", M(20,0), M_MASK, PPC, { RA,RS,SH,MBE,ME } }, -{ "rlimi", M(20,0), M_MASK, POWER, { RA,RS,SH,MBE,ME } }, - -{ "rlwimi.", M(20,1), M_MASK, PPC, { RA,RS,SH,MBE,ME } }, -{ "rlimi.", M(20,1), M_MASK, POWER, { RA,RS,SH,MBE,ME } }, - -{ "rotlwi", MME(21,31,0), MMBME_MASK, PPC, { RA, RS, SH } }, -{ "clrlwi", MME(21,31,0), MSHME_MASK, PPC, { RA, RS, MB } }, -{ "rlwinm", M(21,0), M_MASK, PPC, { RA,RS,SH,MBE,ME } }, -{ "rlinm", M(21,0), M_MASK, POWER, { RA,RS,SH,MBE,ME } }, -{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPC, { RA,RS,SH } }, -{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPC, { RA, RS, MB } }, -{ "rlwinm.", M(21,1), M_MASK, PPC, { RA,RS,SH,MBE,ME } }, -{ "rlinm.", M(21,1), M_MASK, POWER, { RA,RS,SH,MBE,ME } }, - -{ "rlmi", M(22,0), M_MASK, POWER|M601, { RA,RS,RB,MBE,ME } }, -{ "rlmi.", M(22,1), M_MASK, POWER|M601, { RA,RS,RB,MBE,ME } }, - -{ "rotlw", MME(23,31,0), MMBME_MASK, PPC, { RA, RS, RB } }, -{ "rlwnm", M(23,0), M_MASK, PPC, { RA,RS,RB,MBE,ME } }, -{ "rlnm", M(23,0), M_MASK, POWER, { RA,RS,RB,MBE,ME } }, -{ "rotlw.", MME(23,31,1), MMBME_MASK, PPC, { RA, RS, RB } }, -{ "rlwnm.", M(23,1), M_MASK, PPC, { RA,RS,RB,MBE,ME } }, -{ "rlnm.", M(23,1), M_MASK, POWER, { RA,RS,RB,MBE,ME } }, - -{ "nop", OP(24), 0xffffffff, PPC, { 0 } }, -{ "ori", OP(24), OP_MASK, PPC, { RA, RS, UI } }, -{ "oril", OP(24), OP_MASK, POWER, { RA, RS, UI } }, - -{ "oris", OP(25), OP_MASK, PPC, { RA, RS, UI } }, -{ "oriu", OP(25), OP_MASK, POWER, { RA, RS, UI } }, - -{ "xori", OP(26), OP_MASK, PPC, { RA, RS, UI } }, -{ "xoril", OP(26), OP_MASK, POWER, { RA, RS, UI } }, - -{ "xoris", OP(27), OP_MASK, PPC, { RA, RS, UI } }, -{ "xoriu", OP(27), OP_MASK, POWER, { RA, RS, UI } }, - -{ "andi.", OP(28), OP_MASK, PPC, { RA, RS, UI } }, -{ "andil.", OP(28), OP_MASK, POWER, { RA, RS, UI } }, - -{ "andis.", OP(29), OP_MASK, PPC, { RA, RS, UI } }, -{ "andiu.", OP(29), OP_MASK, POWER, { RA, RS, UI } }, - -{ "rotldi", MD(30,0,0), MDMB_MASK, PPC|B64, { RA, RS, SH6 } }, -{ "clrldi", MD(30,0,0), MDSH_MASK, PPC|B64, { RA, RS, MB6 } }, -{ "rldicl", MD(30,0,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } }, -{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC|B64, { RA, RS, SH6 } }, -{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC|B64, { RA, RS, MB6 } }, -{ "rldicl.", MD(30,0,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } }, - -{ "rldicr", MD(30,1,0), MD_MASK, PPC|B64, { RA, RS, SH6, ME6 } }, -{ "rldicr.", MD(30,1,1), MD_MASK, PPC|B64, { RA, RS, SH6, ME6 } }, - -{ "rldic", MD(30,2,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } }, -{ "rldic.", MD(30,2,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } }, - -{ "rldimi", MD(30,3,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } }, -{ "rldimi.", MD(30,3,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } }, - -{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC|B64, { RA, RS, RB } }, -{ "rldcl", MDS(30,8,0), MDS_MASK, PPC|B64, { RA, RS, RB, MB6 } }, -{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC|B64, { RA, RS, RB } }, -{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC|B64, { RA, RS, RB, MB6 } }, - -{ "rldcr", MDS(30,9,0), MDS_MASK, PPC|B64, { RA, RS, RB, ME6 } }, -{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC|B64, { RA, RS, RB, ME6 } }, - -{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPC, { OBF, RA, RB } }, -{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } }, -{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } }, -{ "cmp", X(31,0), XCMPL_MASK, POWER, { BF, RA, RB } }, - -{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPC, { RA, RB } }, -{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, POWER, { RA, RB } }, -{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPC, { RA, RB } }, -{ "tllt", XTO(31,4,TOLLT), XTO_MASK, POWER, { RA, RB } }, -{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPC, { RA, RB } }, -{ "teq", XTO(31,4,TOEQ), XTO_MASK, POWER, { RA, RB } }, -{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPC, { RA, RB } }, -{ "tlge", XTO(31,4,TOLGE), XTO_MASK, POWER, { RA, RB } }, -{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPC, { RA, RB } }, -{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, POWER, { RA, RB } }, -{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPC, { RA, RB } }, -{ "tlle", XTO(31,4,TOLLE), XTO_MASK, POWER, { RA, RB } }, -{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPC, { RA, RB } }, -{ "tlng", XTO(31,4,TOLNG), XTO_MASK, POWER, { RA, RB } }, -{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPC, { RA, RB } }, -{ "tgt", XTO(31,4,TOGT), XTO_MASK, POWER, { RA, RB } }, -{ "twge", XTO(31,4,TOGE), XTO_MASK, PPC, { RA, RB } }, -{ "tge", XTO(31,4,TOGE), XTO_MASK, POWER, { RA, RB } }, -{ "twnl", XTO(31,4,TONL), XTO_MASK, PPC, { RA, RB } }, -{ "tnl", XTO(31,4,TONL), XTO_MASK, POWER, { RA, RB } }, -{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPC, { RA, RB } }, -{ "tlt", XTO(31,4,TOLT), XTO_MASK, POWER, { RA, RB } }, -{ "twle", XTO(31,4,TOLE), XTO_MASK, PPC, { RA, RB } }, -{ "tle", XTO(31,4,TOLE), XTO_MASK, POWER, { RA, RB } }, -{ "twng", XTO(31,4,TONG), XTO_MASK, PPC, { RA, RB } }, -{ "tng", XTO(31,4,TONG), XTO_MASK, POWER, { RA, RB } }, -{ "twne", XTO(31,4,TONE), XTO_MASK, PPC, { RA, RB } }, -{ "tne", XTO(31,4,TONE), XTO_MASK, POWER, { RA, RB } }, -{ "trap", XTO(31,4,TOU), 0xffffffff, PPC, { 0 } }, -{ "tw", X(31,4), X_MASK, PPC, { TO, RA, RB } }, -{ "t", X(31,4), X_MASK, POWER, { TO, RA, RB } }, - -{ "subfc", XO(31,8,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "sf", XO(31,8,0,0), XO_MASK, POWER, { RT, RA, RB } }, -{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } }, -{ "subfc.", XO(31,8,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "sf.", XO(31,8,0,1), XO_MASK, POWER, { RT, RA, RB } }, -{ "subc.", XO(31,8,0,1), XO_MASK, PPC, { RT, RB, RA } }, -{ "subfco", XO(31,8,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "sfo", XO(31,8,1,0), XO_MASK, POWER, { RT, RA, RB } }, -{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } }, -{ "subfco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "sfo.", XO(31,8,1,1), XO_MASK, POWER, { RT, RA, RB } }, -{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } }, - -{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC|B64, { RT, RA, RB } }, -{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC|B64, { RT, RA, RB } }, - -{ "addc", XO(31,10,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "a", XO(31,10,0,0), XO_MASK, POWER, { RT, RA, RB } }, -{ "addc.", XO(31,10,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "a.", XO(31,10,0,1), XO_MASK, POWER, { RT, RA, RB } }, -{ "addco", XO(31,10,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "ao", XO(31,10,1,0), XO_MASK, POWER, { RT, RA, RB } }, -{ "addco.", XO(31,10,1,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "ao.", XO(31,10,1,1), XO_MASK, POWER, { RT, RA, RB } }, - -{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } }, - -{ "mfcr", X(31,19), XRARB_MASK, POWER|PPC, { RT } }, - -{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } }, - -{ "ldx", X(31,21), X_MASK, PPC|B64, { RT, RA, RB } }, - -{ "lwzx", X(31,23), X_MASK, PPC, { RT, RA, RB } }, -{ "lx", X(31,23), X_MASK, POWER, { RT, RA, RB } }, - -{ "slw", XRC(31,24,0), X_MASK, PPC, { RA, RS, RB } }, -{ "sl", XRC(31,24,0), X_MASK, POWER, { RA, RS, RB } }, -{ "slw.", XRC(31,24,1), X_MASK, PPC, { RA, RS, RB } }, -{ "sl.", XRC(31,24,1), X_MASK, POWER, { RA, RS, RB } }, - -{ "cntlzw", XRC(31,26,0), XRB_MASK, PPC, { RA, RS } }, -{ "cntlz", XRC(31,26,0), XRB_MASK, POWER, { RA, RS } }, -{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPC, { RA, RS } }, -{ "cntlz.", XRC(31,26,1), XRB_MASK, POWER, { RA, RS } }, - -{ "sld", XRC(31,27,0), X_MASK, PPC|B64, { RA, RS, RB } }, -{ "sld.", XRC(31,27,1), X_MASK, PPC|B64, { RA, RS, RB } }, - -{ "and", XRC(31,28,0), X_MASK, PPC|POWER, { RA, RS, RB } }, -{ "and.", XRC(31,28,1), X_MASK, PPC|POWER, { RA, RS, RB } }, - -{ "maskg", XRC(31,29,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "maskg.", XRC(31,29,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPC, { OBF, RA, RB } }, -{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } }, -{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } }, -{ "cmpl", X(31,32), XCMPL_MASK, POWER, { BF, RA, RB } }, - -{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } }, -{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } }, -{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } }, -{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } }, - -{ "ldux", X(31,53), X_MASK, PPC|B64, { RT, RAL, RB } }, - -{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } }, - -{ "lwzux", X(31,55), X_MASK, PPC, { RT, RAL, RB } }, -{ "lux", X(31,55), X_MASK, POWER, { RT, RA, RB } }, - -{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC|B64, { RA, RS } }, -{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC|B64, { RA, RS } }, - -{ "andc", XRC(31,60,0), X_MASK, PPC|POWER, { RA, RS, RB } }, -{ "andc.", XRC(31,60,1), X_MASK, PPC|POWER, { RA, RS, RB } }, - -{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC|B64, { RA, RB } }, -{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC|B64, { RA, RB } }, -{ "td", X(31,68), X_MASK, PPC|B64, { TO, RA, RB } }, - -{ "mulhd", XO(31,73,0,0), XO_MASK, PPC|B64, { RT, RA, RB } }, -{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC|B64, { RT, RA, RB } }, - -{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } }, - -{ "mfmsr", X(31,83), XRARB_MASK, PPC|POWER, { RT } }, - -{ "ldarx", X(31,84), X_MASK, PPC|B64, { RT, RA, RB } }, - -{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } }, - -{ "lbzx", X(31,87), X_MASK, PPC|POWER, { RT, RA, RB } }, - -{ "neg", XO(31,104,0,0), XORB_MASK, PPC|POWER, { RT, RA } }, -{ "neg.", XO(31,104,0,1), XORB_MASK, PPC|POWER, { RT, RA } }, -{ "nego", XO(31,104,1,0), XORB_MASK, PPC|POWER, { RT, RA } }, -{ "nego.", XO(31,104,1,1), XORB_MASK, PPC|POWER, { RT, RA } }, - -{ "mul", XO(31,107,0,0), XO_MASK, POWER|M601, { RT, RA, RB } }, -{ "mul.", XO(31,107,0,1), XO_MASK, POWER|M601, { RT, RA, RB } }, -{ "mulo", XO(31,107,1,0), XO_MASK, POWER|M601, { RT, RA, RB } }, -{ "mulo.", XO(31,107,1,1), XO_MASK, POWER|M601, { RT, RA, RB } }, - -{ "clf", X(31,118), XRB_MASK, POWER, { RT, RA } }, - -{ "lbzux", X(31,119), X_MASK, PPC|POWER, { RT, RAL, RB } }, - -{ "not", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RBS } }, -{ "nor", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RB } }, -{ "not.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RBS } }, -{ "nor.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RB } }, - -{ "subfe", XO(31,136,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "sfe", XO(31,136,0,0), XO_MASK, POWER, { RT, RA, RB } }, -{ "subfe.", XO(31,136,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "sfe.", XO(31,136,0,1), XO_MASK, POWER, { RT, RA, RB } }, -{ "subfeo", XO(31,136,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "sfeo", XO(31,136,1,0), XO_MASK, POWER, { RT, RA, RB } }, -{ "subfeo.", XO(31,136,1,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "sfeo.", XO(31,136,1,1), XO_MASK, POWER, { RT, RA, RB } }, - -{ "adde", XO(31,138,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "ae", XO(31,138,0,0), XO_MASK, POWER, { RT, RA, RB } }, -{ "adde.", XO(31,138,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "ae.", XO(31,138,0,1), XO_MASK, POWER, { RT, RA, RB } }, -{ "addeo", XO(31,138,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "aeo", XO(31,138,1,0), XO_MASK, POWER, { RT, RA, RB } }, -{ "addeo.", XO(31,138,1,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "aeo.", XO(31,138,1,1), XO_MASK, POWER, { RT, RA, RB } }, - -{ "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, PPC|POWER, { RS }}, -{ "mtcrf", X(31,144), XFXFXM_MASK, PPC|POWER, { FXM, RS } }, - -{ "mtmsr", X(31,146), XRARB_MASK, PPC|POWER, { RS } }, - -{ "stdx", X(31,149), X_MASK, PPC|B64, { RS, RA, RB } }, - -{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } }, - -{ "stwx", X(31,151), X_MASK, PPC, { RS, RA, RB } }, -{ "stx", X(31,151), X_MASK, POWER, { RS, RA, RB } }, - -{ "slq", XRC(31,152,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "slq.", XRC(31,152,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "sle", XRC(31,153,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "sle.", XRC(31,153,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "stdux", X(31,181), X_MASK, PPC|B64, { RS, RAS, RB } }, - -{ "stwux", X(31,183), X_MASK, PPC, { RS, RAS, RB } }, -{ "stux", X(31,183), X_MASK, POWER, { RS, RA, RB } }, - -{ "sliq", XRC(31,184,0), X_MASK, POWER|M601, { RA, RS, SH } }, -{ "sliq.", XRC(31,184,1), X_MASK, POWER|M601, { RA, RS, SH } }, - -{ "subfze", XO(31,200,0,0), XORB_MASK, PPC, { RT, RA } }, -{ "sfze", XO(31,200,0,0), XORB_MASK, POWER, { RT, RA } }, -{ "subfze.", XO(31,200,0,1), XORB_MASK, PPC, { RT, RA } }, -{ "sfze.", XO(31,200,0,1), XORB_MASK, POWER, { RT, RA } }, -{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPC, { RT, RA } }, -{ "sfzeo", XO(31,200,1,0), XORB_MASK, POWER, { RT, RA } }, -{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPC, { RT, RA } }, -{ "sfzeo.", XO(31,200,1,1), XORB_MASK, POWER, { RT, RA } }, - -{ "addze", XO(31,202,0,0), XORB_MASK, PPC, { RT, RA } }, -{ "aze", XO(31,202,0,0), XORB_MASK, POWER, { RT, RA } }, -{ "addze.", XO(31,202,0,1), XORB_MASK, PPC, { RT, RA } }, -{ "aze.", XO(31,202,0,1), XORB_MASK, POWER, { RT, RA } }, -{ "addzeo", XO(31,202,1,0), XORB_MASK, PPC, { RT, RA } }, -{ "azeo", XO(31,202,1,0), XORB_MASK, POWER, { RT, RA } }, -{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPC, { RT, RA } }, -{ "azeo.", XO(31,202,1,1), XORB_MASK, POWER, { RT, RA } }, - -{ "mtsr", X(31,210), XRB_MASK|(1<<20), PPC|POWER|B32, { SR, RS } }, - -{ "stdcx.", XRC(31,214,1), X_MASK, PPC|B64, { RS, RA, RB } }, - -{ "stbx", X(31,215), X_MASK, PPC|POWER, { RS, RA, RB } }, - -{ "sllq", XRC(31,216,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "sllq.", XRC(31,216,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "sleq", XRC(31,217,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "sleq.", XRC(31,217,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "subfme", XO(31,232,0,0), XORB_MASK, PPC, { RT, RA } }, -{ "sfme", XO(31,232,0,0), XORB_MASK, POWER, { RT, RA } }, -{ "subfme.", XO(31,232,0,1), XORB_MASK, PPC, { RT, RA } }, -{ "sfme.", XO(31,232,0,1), XORB_MASK, POWER, { RT, RA } }, -{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPC, { RT, RA } }, -{ "sfmeo", XO(31,232,1,0), XORB_MASK, POWER, { RT, RA } }, -{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPC, { RT, RA } }, -{ "sfmeo.", XO(31,232,1,1), XORB_MASK, POWER, { RT, RA } }, - -{ "mulld", XO(31,233,0,0), XO_MASK, PPC|B64, { RT, RA, RB } }, -{ "mulld.", XO(31,233,0,1), XO_MASK, PPC|B64, { RT, RA, RB } }, -{ "mulldo", XO(31,233,1,0), XO_MASK, PPC|B64, { RT, RA, RB } }, -{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC|B64, { RT, RA, RB } }, - -{ "addme", XO(31,234,0,0), XORB_MASK, PPC, { RT, RA } }, -{ "ame", XO(31,234,0,0), XORB_MASK, POWER, { RT, RA } }, -{ "addme.", XO(31,234,0,1), XORB_MASK, PPC, { RT, RA } }, -{ "ame.", XO(31,234,0,1), XORB_MASK, POWER, { RT, RA } }, -{ "addmeo", XO(31,234,1,0), XORB_MASK, PPC, { RT, RA } }, -{ "ameo", XO(31,234,1,0), XORB_MASK, POWER, { RT, RA } }, -{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPC, { RT, RA } }, -{ "ameo.", XO(31,234,1,1), XORB_MASK, POWER, { RT, RA } }, - -{ "mullw", XO(31,235,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "muls", XO(31,235,0,0), XO_MASK, POWER, { RT, RA, RB } }, -{ "mullw.", XO(31,235,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "muls.", XO(31,235,0,1), XO_MASK, POWER, { RT, RA, RB } }, -{ "mullwo", XO(31,235,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "mulso", XO(31,235,1,0), XO_MASK, POWER, { RT, RA, RB } }, -{ "mullwo.", XO(31,235,1,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "mulso.", XO(31,235,1,1), XO_MASK, POWER, { RT, RA, RB } }, - -{ "mtsrin", X(31,242), XRA_MASK, PPC|B32, { RS, RB } }, -{ "mtsri", X(31,242), XRA_MASK, POWER|B32, { RS, RB } }, - -{ "dcbtst", X(31,246), XRT_MASK, PPC, { RA, RB } }, - -{ "stbux", X(31,247), X_MASK, PPC|POWER, { RS, RAS, RB } }, - -{ "slliq", XRC(31,248,0), X_MASK, POWER|M601, { RA, RS, SH } }, -{ "slliq.", XRC(31,248,1), X_MASK, POWER|M601, { RA, RS, SH } }, - -{ "doz", XO(31,264,0,0), XO_MASK, POWER|M601, { RT, RA, RB } }, -{ "doz.", XO(31,264,0,1), XO_MASK, POWER|M601, { RT, RA, RB } }, -{ "dozo", XO(31,264,1,0), XO_MASK, POWER|M601, { RT, RA, RB } }, -{ "dozo.", XO(31,264,1,1), XO_MASK, POWER|M601, { RT, RA, RB } }, - -{ "add", XO(31,266,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "cax", XO(31,266,0,0), XO_MASK, POWER, { RT, RA, RB } }, -{ "add.", XO(31,266,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "cax.", XO(31,266,0,1), XO_MASK, POWER, { RT, RA, RB } }, -{ "addo", XO(31,266,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "caxo", XO(31,266,1,0), XO_MASK, POWER, { RT, RA, RB } }, -{ "addo.", XO(31,266,1,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "caxo.", XO(31,266,1,1), XO_MASK, POWER, { RT, RA, RB } }, - -{ "lscbx", XRC(31,277,0), X_MASK, POWER|M601, { RT, RA, RB } }, -{ "lscbx.", XRC(31,277,1), X_MASK, POWER|M601, { RT, RA, RB } }, - -{ "dcbt", X(31,278), XRT_MASK, PPC, { RA, RB } }, - -{ "lhzx", X(31,279), X_MASK, PPC|POWER, { RT, RA, RB } }, - -{ "eqv", XRC(31,284,0), X_MASK, PPC|POWER, { RA, RS, RB } }, -{ "eqv.", XRC(31,284,1), X_MASK, PPC|POWER, { RA, RS, RB } }, - -{ "tlbie", X(31,306), XRTRA_MASK, PPC, { RB } }, -{ "tlbi", X(31,306), XRTRA_MASK, POWER, { RB } }, - -{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } }, - -{ "lhzux", X(31,311), X_MASK, PPC|POWER, { RT, RAL, RB } }, - -{ "xor", XRC(31,316,0), X_MASK, PPC|POWER, { RA, RS, RB } }, -{ "xor.", XRC(31,316,1), X_MASK, PPC|POWER, { RA, RS, RB } }, - -{ "div", XO(31,331,0,0), XO_MASK, POWER|M601, { RT, RA, RB } }, -{ "div.", XO(31,331,0,1), XO_MASK, POWER|M601, { RT, RA, RB } }, -{ "divo", XO(31,331,1,0), XO_MASK, POWER|M601, { RT, RA, RB } }, -{ "divo.", XO(31,331,1,1), XO_MASK, POWER|M601, { RT, RA, RB } }, - -{ "mfmq", XSPR(31,339,0), XSPR_MASK, POWER|M601, { RT } }, -{ "mfxer", XSPR(31,339,1), XSPR_MASK, PPC|POWER, { RT } }, -{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, PPC|POWER, { RT } }, -{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, PPC|POWER, { RT } }, -{ "mfdec", XSPR(31,339,6), XSPR_MASK, POWER|M601, { RT } }, -{ "mflr", XSPR(31,339,8), XSPR_MASK, PPC|POWER, { RT } }, -{ "mfctr", XSPR(31,339,9), XSPR_MASK, PPC|POWER, { RT } }, -{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } }, -{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, PPC|POWER, { RT } }, -{ "mfdar", XSPR(31,339,19), XSPR_MASK, PPC|POWER, { RT } }, -{ "mfdec", XSPR(31,339,22), XSPR_MASK, PPC, { RT } }, -{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } }, -{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, PPC|POWER, { RT } }, -{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, PPC|POWER, { RT } }, -{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, PPC|POWER, { RT } }, -{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } }, -{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC|B64, { RT } }, -{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } }, -{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } }, -{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, -{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, -{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, -{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, -{ "mfspr", X(31,339), X_MASK, PPC|POWER, { RT, SPR } }, - -{ "lwax", X(31,341), X_MASK, PPC|B64, { RT, RA, RB } }, - -{ "lhax", X(31,343), X_MASK, PPC|POWER, { RT, RA, RB } }, - -{ "abs", XO(31,360,0,0), XORB_MASK, POWER|M601, { RT, RA } }, -{ "abs.", XO(31,360,0,1), XORB_MASK, POWER|M601, { RT, RA } }, -{ "abso", XO(31,360,1,0), XORB_MASK, POWER|M601, { RT, RA } }, -{ "abso.", XO(31,360,1,1), XORB_MASK, POWER|M601, { RT, RA } }, - -{ "divs", XO(31,363,0,0), XO_MASK, POWER|M601, { RT, RA, RB } }, -{ "divs.", XO(31,363,0,1), XO_MASK, POWER|M601, { RT, RA, RB } }, -{ "divso", XO(31,363,1,0), XO_MASK, POWER|M601, { RT, RA, RB } }, -{ "divso.", XO(31,363,1,1), XO_MASK, POWER|M601, { RT, RA, RB } }, - -{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } }, - -{ "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } }, -{ "mftb", X(31,371), X_MASK, PPC, { RT, TBR } }, - -{ "lwaux", X(31,373), X_MASK, PPC|B64, { RT, RAL, RB } }, - -{ "lhaux", X(31,375), X_MASK, PPC|POWER, { RT, RAL, RB } }, - -{ "sthx", X(31,407), X_MASK, PPC|POWER, { RS, RA, RB } }, - -{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } }, - -{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } }, - -{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } }, - -{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } }, - -{ "orc", XRC(31,412,0), X_MASK, PPC|POWER, { RA, RS, RB } }, -{ "orc.", XRC(31,412,1), X_MASK, PPC|POWER, { RA, RS, RB } }, - -{ "sradi", XS(31,413,0), XS_MASK, PPC|B64, { RA, RS, SH6 } }, -{ "sradi.", XS(31,413,1), XS_MASK, PPC|B64, { RA, RS, SH6 } }, - -{ "slbie", X(31,434), XRTRA_MASK, PPC|B64, { RB } }, - -{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } }, - -{ "sthux", X(31,439), X_MASK, PPC|POWER, { RS, RAS, RB } }, - -{ "mr", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RBS } }, -{ "or", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RB } }, -{ "mr.", XRC(31,444,1), X_MASK, PPC|POWER, { RA, RS, RBS } }, -{ "or.", XRC(31,444,1), X_MASK, PPC|POWER, { RA, RS, RB } }, - -{ "divdu", XO(31,457,0,0), XO_MASK, PPC|B64, { RT, RA, RB } }, -{ "divdu.", XO(31,457,0,1), XO_MASK, PPC|B64, { RT, RA, RB } }, -{ "divduo", XO(31,457,1,0), XO_MASK, PPC|B64, { RT, RA, RB } }, -{ "divduo.", XO(31,457,1,1), XO_MASK, PPC|B64, { RT, RA, RB } }, - -{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } }, - -{ "mtmq", XSPR(31,467,0), XSPR_MASK, POWER|M601, { RS } }, -{ "mtxer", XSPR(31,467,1), XSPR_MASK, PPC|POWER, { RS } }, -{ "mtlr", XSPR(31,467,8), XSPR_MASK, PPC|POWER, { RS } }, -{ "mtctr", XSPR(31,467,9), XSPR_MASK, PPC|POWER, { RS } }, -{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } }, -{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, PPC|POWER, { RS } }, -{ "mtdar", XSPR(31,467,19), XSPR_MASK, PPC|POWER, { RS } }, -{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, PPC|POWER, { RS } }, -{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, PPC|POWER, { RS } }, -{ "mtdec", XSPR(31,467,22), XSPR_MASK, PPC|POWER, { RS } }, -{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } }, -{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, PPC|POWER, { RS } }, -{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, PPC|POWER, { RS } }, -{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, PPC|POWER, { RS } }, -{ "mtsprg", XSPR(31,467,272), XSPRG_MASK, PPC, { SPRG, RS } }, -{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC|B64, { RS } }, -{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } }, -{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } }, -{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } }, -{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, -{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, -{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, -{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, -{ "mtspr", X(31,467), X_MASK, PPC|POWER, { SPR, RS } }, - -{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } }, - -{ "nand", XRC(31,476,0), X_MASK, PPC|POWER, { RA, RS, RB } }, -{ "nand.", XRC(31,476,1), X_MASK, PPC|POWER, { RA, RS, RB } }, - -{ "nabs", XO(31,488,0,0), XORB_MASK, POWER|M601, { RT, RA } }, -{ "nabs.", XO(31,488,0,1), XORB_MASK, POWER|M601, { RT, RA } }, -{ "nabso", XO(31,488,1,0), XORB_MASK, POWER|M601, { RT, RA } }, -{ "nabso.", XO(31,488,1,1), XORB_MASK, POWER|M601, { RT, RA } }, - -{ "divd", XO(31,489,0,0), XO_MASK, PPC|B64, { RT, RA, RB } }, -{ "divd.", XO(31,489,0,1), XO_MASK, PPC|B64, { RT, RA, RB } }, -{ "divdo", XO(31,489,1,0), XO_MASK, PPC|B64, { RT, RA, RB } }, -{ "divdo.", XO(31,489,1,1), XO_MASK, PPC|B64, { RT, RA, RB } }, - -{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } }, - -{ "slbia", X(31,498), 0xffffffff, PPC|B64, { 0 } }, - -{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } }, - -{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), PPC|POWER, { BF } }, - -{ "clcs", X(31,531), XRB_MASK, POWER|M601, { RT, RA } }, - -{ "lswx", X(31,533), X_MASK, PPC, { RT, RA, RB } }, -{ "lsx", X(31,533), X_MASK, POWER, { RT, RA, RB } }, - -{ "lwbrx", X(31,534), X_MASK, PPC, { RT, RA, RB } }, -{ "lbrx", X(31,534), X_MASK, POWER, { RT, RA, RB } }, - -{ "lfsx", X(31,535), X_MASK, PPC|POWER, { FRT, RA, RB } }, - -{ "srw", XRC(31,536,0), X_MASK, PPC, { RA, RS, RB } }, -{ "sr", XRC(31,536,0), X_MASK, POWER, { RA, RS, RB } }, -{ "srw.", XRC(31,536,1), X_MASK, PPC, { RA, RS, RB } }, -{ "sr.", XRC(31,536,1), X_MASK, POWER, { RA, RS, RB } }, - -{ "rrib", XRC(31,537,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "rrib.", XRC(31,537,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "srd", XRC(31,539,0), X_MASK, PPC|B64, { RA, RS, RB } }, -{ "srd.", XRC(31,539,1), X_MASK, PPC|B64, { RA, RS, RB } }, - -{ "maskir", XRC(31,541,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "maskir.", XRC(31,541,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } }, - -{ "lfsux", X(31,567), X_MASK, PPC|POWER, { FRT, RAS, RB } }, - -{ "mfsr", X(31,595), XRB_MASK|(1<<20), PPC|POWER|B32, { RT, SR } }, - -{ "lswi", X(31,597), X_MASK, PPC, { RT, RA, NB } }, -{ "lsi", X(31,597), X_MASK, POWER, { RT, RA, NB } }, - -{ "sync", X(31,598), 0xffffffff, PPC, { 0 } }, -{ "dcs", X(31,598), 0xffffffff, POWER, { 0 } }, - -{ "lfdx", X(31,599), X_MASK, PPC|POWER, { FRT, RA, RB } }, - -{ "mfsri", X(31,627), X_MASK, POWER, { RT, RA, RB } }, - -{ "dclst", X(31,630), XRB_MASK, POWER, { RS, RA } }, - -{ "lfdux", X(31,631), X_MASK, PPC|POWER, { FRT, RAS, RB } }, - -{ "mfsrin", X(31,659), XRA_MASK, PPC|B32, { RT, RB } }, - -{ "stswx", X(31,661), X_MASK, PPC, { RS, RA, RB } }, -{ "stsx", X(31,661), X_MASK, POWER, { RS, RA, RB } }, - -{ "stwbrx", X(31,662), X_MASK, PPC, { RS, RA, RB } }, -{ "stbrx", X(31,662), X_MASK, POWER, { RS, RA, RB } }, - -{ "stfsx", X(31,663), X_MASK, PPC|POWER, { FRS, RA, RB } }, - -{ "srq", XRC(31,664,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "srq.", XRC(31,664,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "sre", XRC(31,665,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "sre.", XRC(31,665,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "stfsux", X(31,695), X_MASK, PPC|POWER, { FRS, RAS, RB } }, - -{ "sriq", XRC(31,696,0), X_MASK, POWER|M601, { RA, RS, SH } }, -{ "sriq.", XRC(31,696,1), X_MASK, POWER|M601, { RA, RS, SH } }, - -{ "stswi", X(31,725), X_MASK, PPC, { RS, RA, NB } }, -{ "stsi", X(31,725), X_MASK, POWER, { RS, RA, NB } }, - -{ "stfdx", X(31,727), X_MASK, PPC|POWER, { FRS, RA, RB } }, - -{ "srlq", XRC(31,728,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "srlq.", XRC(31,728,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "sreq", XRC(31,729,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "sreq.", XRC(31,729,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "stfdux", X(31,759), X_MASK, PPC|POWER, { FRS, RAS, RB } }, - -{ "srliq", XRC(31,760,0), X_MASK, POWER|M601, { RA, RS, SH } }, -{ "srliq.", XRC(31,760,1), X_MASK, POWER|M601, { RA, RS, SH } }, - -{ "lhbrx", X(31,790), X_MASK, PPC|POWER, { RT, RA, RB } }, - -{ "sraw", XRC(31,792,0), X_MASK, PPC, { RA, RS, RB } }, -{ "sra", XRC(31,792,0), X_MASK, POWER, { RA, RS, RB } }, -{ "sraw.", XRC(31,792,1), X_MASK, PPC, { RA, RS, RB } }, -{ "sra.", XRC(31,792,1), X_MASK, POWER, { RA, RS, RB } }, - -{ "srad", XRC(31,794,0), X_MASK, PPC|B64, { RA, RS, RB } }, -{ "srad.", XRC(31,794,1), X_MASK, PPC|B64, { RA, RS, RB } }, - -{ "rac", X(31,818), X_MASK, POWER, { RT, RA, RB } }, - -{ "srawi", XRC(31,824,0), X_MASK, PPC, { RA, RS, SH } }, -{ "srai", XRC(31,824,0), X_MASK, POWER, { RA, RS, SH } }, -{ "srawi.", XRC(31,824,1), X_MASK, PPC, { RA, RS, SH } }, -{ "srai.", XRC(31,824,1), X_MASK, POWER, { RA, RS, SH } }, - -{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } }, - -{ "sthbrx", X(31,918), X_MASK, PPC|POWER, { RS, RA, RB } }, - -{ "sraq", XRC(31,920,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "sraq.", XRC(31,920,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "srea", XRC(31,921,0), X_MASK, POWER|M601, { RA, RS, RB } }, -{ "srea.", XRC(31,921,1), X_MASK, POWER|M601, { RA, RS, RB } }, - -{ "extsh", XRC(31,922,0), XRB_MASK, PPC, { RA, RS } }, -{ "exts", XRC(31,922,0), XRB_MASK, POWER, { RA, RS } }, -{ "extsh.", XRC(31,922,1), XRB_MASK, PPC, { RA, RS } }, -{ "exts.", XRC(31,922,1), XRB_MASK, POWER, { RA, RS } }, - -{ "sraiq", XRC(31,952,0), X_MASK, POWER|M601, { RA, RS, SH } }, -{ "sraiq.", XRC(31,952,1), X_MASK, POWER|M601, { RA, RS, SH } }, - -{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} }, -{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} }, - -{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } }, - -{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } }, - -{ "extsw", XRC(31,986,0), XRB_MASK, PPC, { RA, RS } }, -{ "extsw.", XRC(31,986,1), XRB_MASK, PPC, { RA, RS } }, - -{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, -{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, - -{ "lwz", OP(32), OP_MASK, PPC, { RT, D, RA } }, -{ "l", OP(32), OP_MASK, POWER, { RT, D, RA } }, - -{ "lwzu", OP(33), OP_MASK, PPC, { RT, D, RAL } }, -{ "lu", OP(33), OP_MASK, POWER, { RT, D, RA } }, - -{ "lbz", OP(34), OP_MASK, PPC|POWER, { RT, D, RA } }, - -{ "lbzu", OP(35), OP_MASK, PPC|POWER, { RT, D, RAL } }, - -{ "stw", OP(36), OP_MASK, PPC, { RS, D, RA } }, -{ "st", OP(36), OP_MASK, POWER, { RS, D, RA } }, - -{ "stwu", OP(37), OP_MASK, PPC, { RS, D, RAS } }, -{ "stu", OP(37), OP_MASK, POWER, { RS, D, RA } }, - -{ "stb", OP(38), OP_MASK, PPC|POWER, { RS, D, RA } }, - -{ "stbu", OP(39), OP_MASK, PPC|POWER, { RS, D, RAS } }, - -{ "lhz", OP(40), OP_MASK, PPC|POWER, { RT, D, RA } }, - -{ "lhzu", OP(41), OP_MASK, PPC|POWER, { RT, D, RAL } }, - -{ "lha", OP(42), OP_MASK, PPC|POWER, { RT, D, RA } }, - -{ "lhau", OP(43), OP_MASK, PPC|POWER, { RT, D, RAL } }, - -{ "sth", OP(44), OP_MASK, PPC|POWER, { RS, D, RA } }, - -{ "sthu", OP(45), OP_MASK, PPC|POWER, { RS, D, RAS } }, - -{ "lmw", OP(46), OP_MASK, PPC, { RT, D, RAM } }, -{ "lm", OP(46), OP_MASK, POWER, { RT, D, RA } }, - -{ "stmw", OP(47), OP_MASK, PPC, { RS, D, RA } }, -{ "stm", OP(47), OP_MASK, POWER, { RS, D, RA } }, - -{ "lfs", OP(48), OP_MASK, PPC|POWER, { FRT, D, RA } }, - -{ "lfsu", OP(49), OP_MASK, PPC|POWER, { FRT, D, RAS } }, - -{ "lfd", OP(50), OP_MASK, PPC|POWER, { FRT, D, RA } }, - -{ "lfdu", OP(51), OP_MASK, PPC|POWER, { FRT, D, RAS } }, - -{ "stfs", OP(52), OP_MASK, PPC|POWER, { FRS, D, RA } }, - -{ "stfsu", OP(53), OP_MASK, PPC|POWER, { FRS, D, RAS } }, - -{ "stfd", OP(54), OP_MASK, PPC|POWER, { FRS, D, RA } }, - -{ "stfdu", OP(55), OP_MASK, PPC|POWER, { FRS, D, RAS } }, - -{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } }, - -{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } }, - -{ "ld", DSO(58,0), DS_MASK, PPC|B64, { RT, DS, RA } }, - -{ "ldu", DSO(58,1), DS_MASK, PPC|B64, { RT, DS, RAL } }, - -{ "lwa", DSO(58,2), DS_MASK, PPC|B64, { RT, DS, RA } }, - -{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, - -{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, - -{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, - -{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, -{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, - -{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, -{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, - -{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, -{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } }, - -{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, - -{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, - -{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, - -{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, - -{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } }, - -{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } }, - -{ "std", DSO(62,0), DS_MASK, PPC|B64, { RS, DS, RA } }, - -{ "stdu", DSO(62,1), DS_MASK, PPC|B64, { RS, DS, RAS } }, - -{ "fcmpu", X(63,0), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } }, - -{ "frsp", XRC(63,12,0), XRA_MASK, PPC|POWER, { FRT, FRB } }, -{ "frsp.", XRC(63,12,1), XRA_MASK, PPC|POWER, { FRT, FRB } }, - -{ "fctiw", XRC(63,14,0), XRA_MASK, PPC, { FRT, FRB } }, -{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } }, -{ "fctiw.", XRC(63,14,1), XRA_MASK, PPC, { FRT, FRB } }, -{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } }, - -{ "fctiwz", XRC(63,15,0), XRA_MASK, PPC, { FRT, FRB } }, -{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } }, -{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPC, { FRT, FRB } }, -{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } }, - -{ "fdiv", A(63,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fd", A(63,18,0), AFRC_MASK, POWER, { FRT, FRA, FRB } }, -{ "fdiv.", A(63,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fd.", A(63,18,1), AFRC_MASK, POWER, { FRT, FRA, FRB } }, - -{ "fsub", A(63,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fs", A(63,20,0), AFRC_MASK, POWER, { FRT, FRA, FRB } }, -{ "fsub.", A(63,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fs.", A(63,20,1), AFRC_MASK, POWER, { FRT, FRA, FRB } }, - -{ "fadd", A(63,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fa", A(63,21,0), AFRC_MASK, POWER, { FRT, FRA, FRB } }, -{ "fadd.", A(63,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fa.", A(63,21,1), AFRC_MASK, POWER, { FRT, FRA, FRB } }, - -{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPC|POWER2, { FRT, FRB } }, -{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPC|POWER2, { FRT, FRB } }, - -{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, - -{ "fmul", A(63,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, -{ "fm", A(63,25,0), AFRB_MASK, POWER, { FRT, FRA, FRC } }, -{ "fmul.", A(63,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } }, -{ "fm.", A(63,25,1), AFRB_MASK, POWER, { FRT, FRA, FRC } }, - -{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, -{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, - -{ "fmsub", A(63,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fms", A(63,28,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, -{ "fmsub.", A(63,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fms.", A(63,28,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, - -{ "fmadd", A(63,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fma", A(63,29,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, -{ "fmadd.", A(63,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fma.", A(63,29,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, - -{ "fnmsub", A(63,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fnms", A(63,30,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, -{ "fnmsub.", A(63,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fnms.", A(63,30,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, - -{ "fnmadd", A(63,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fnma", A(63,31,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, -{ "fnmadd.", A(63,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fnma.", A(63,31,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, - -{ "fcmpo", X(63,30), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } }, - -{ "mtfsb1", XRC(63,38,0), XRARB_MASK, PPC|POWER, { BT } }, -{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, PPC|POWER, { BT } }, - -{ "fneg", XRC(63,40,0), XRA_MASK, PPC|POWER, { FRT, FRB } }, -{ "fneg.", XRC(63,40,1), XRA_MASK, PPC|POWER, { FRT, FRB } }, - -{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } }, - -{ "mtfsb0", XRC(63,70,0), XRARB_MASK, PPC|POWER, { BT } }, -{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, PPC|POWER, { BT } }, - -{ "fmr", XRC(63,72,0), XRA_MASK, PPC|POWER, { FRT, FRB } }, -{ "fmr.", XRC(63,72,1), XRA_MASK, PPC|POWER, { FRT, FRB } }, - -{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } }, -{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } }, - -{ "fnabs", XRC(63,136,0), XRA_MASK, PPC|POWER, { FRT, FRB } }, -{ "fnabs.", XRC(63,136,1), XRA_MASK, PPC|POWER, { FRT, FRB } }, - -{ "fabs", XRC(63,264,0), XRA_MASK, PPC|POWER, { FRT, FRB } }, -{ "fabs.", XRC(63,264,1), XRA_MASK, PPC|POWER, { FRT, FRB } }, - -{ "mffs", XRC(63,583,0), XRARB_MASK, PPC|POWER, { FRT } }, -{ "mffs.", XRC(63,583,1), XRARB_MASK, PPC|POWER, { FRT } }, - -{ "mtfsf", XFL(63,711,0), XFL_MASK, PPC|POWER, { FLM, FRB } }, -{ "mtfsf.", XFL(63,711,1), XFL_MASK, PPC|POWER, { FLM, FRB } }, - -{ "fctid", XRC(63,814,0), XRA_MASK, PPC|B64, { FRT, FRB } }, -{ "fctid.", XRC(63,814,1), XRA_MASK, PPC|B64, { FRT, FRB } }, - -{ "fctidz", XRC(63,815,0), XRA_MASK, PPC|B64, { FRT, FRB } }, -{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC|B64, { FRT, FRB } }, - -{ "fcfid", XRC(63,846,0), XRA_MASK, PPC|B64, { FRT, FRB } }, -{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC|B64, { FRT, FRB } }, - -}; - -const int powerpc_num_opcodes = - sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); - -/* The macro table. This is only used by the assembler. */ - -const struct powerpc_macro powerpc_macros[] = { -{ "extldi", 4, PPC|B64, "rldicr %0,%1,%3,(%2)-1" }, -{ "extldi.", 4, PPC|B64, "rldicr. %0,%1,%3,(%2)-1" }, -{ "extrdi", 4, PPC|B64, "rldicl %0,%1,(%2)+(%3),64-(%2)" }, -{ "extrdi.", 4, PPC|B64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" }, -{ "insrdi", 4, PPC|B64, "rldimi %0,%1,64-((%2)+(%3)),%3" }, -{ "insrdi.", 4, PPC|B64, "rldimi. %0,%1,64-((%2)+(%3)),%3" }, -{ "rotrdi", 3, PPC|B64, "rldicl %0,%1,64-(%2),0" }, -{ "rotrdi.", 3, PPC|B64, "rldicl. %0,%1,64-(%2),0" }, -{ "sldi", 3, PPC|B64, "rldicr %0,%1,%2,63-(%2)" }, -{ "sldi.", 3, PPC|B64, "rldicr. %0,%1,%2,63-(%2)" }, -{ "srdi", 3, PPC|B64, "rldicl %0,%1,64-(%2),%2" }, -{ "srdi.", 3, PPC|B64, "rldicl. %0,%1,64-(%2),%2" }, -{ "clrrdi", 3, PPC|B64, "rldicr %0,%1,0,63-(%2)" }, -{ "clrrdi.", 3, PPC|B64, "rldicr. %0,%1,0,63-(%2)" }, -{ "clrlsldi",4, PPC|B64, "rldic %0,%1,%3,(%2)-(%3)" }, -{ "clrlsldi.",4, PPC|B64, "rldic. %0,%1,%3,(%2)-(%3)" }, - -{ "extlwi", 4, PPC, "rlwinm %0,%1,%3,0,(%2)-1" }, -{ "extlwi.", 4, PPC, "rlwinm. %0,%1,%3,0,(%2)-1" }, -{ "extrwi", 4, PPC, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" }, -{ "extrwi.", 4, PPC, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" }, -{ "inslwi", 4, PPC, "rlwimi %0,%1,32-(%3),%3,(%2)+(%3)-1" }, -{ "inslwi.", 4, PPC, "rlwimi. %0,%1,32-(%3),%3,(%2)+(%3)-1" }, -{ "insrwi", 4, PPC, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" }, -{ "insrwi.", 4, PPC, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, -{ "rotrwi", 3, PPC, "rlwinm %0,%1,32-(%2),0,31" }, -{ "rotrwi.", 3, PPC, "rlwinm. %0,%1,32-(%2),0,31" }, -{ "slwi", 3, PPC, "rlwinm %0,%1,%2,0,31-(%2)" }, -{ "sli", 3, POWER, "rlinm %0,%1,%2,0,31-(%2)" }, -{ "slwi.", 3, PPC, "rlwinm. %0,%1,%2,0,31-(%2)" }, -{ "sli.", 3, POWER, "rlinm. %0,%1,%2,0,31-(%2)" }, -{ "srwi", 3, PPC, "rlwinm %0,%1,32-(%2),%2,31" }, -{ "sri", 3, POWER, "rlinm %0,%1,32-(%2),%2,31" }, -{ "srwi.", 3, PPC, "rlwinm. %0,%1,32-(%2),%2,31" }, -{ "sri.", 3, POWER, "rlinm. %0,%1,32-(%2),%2,31" }, -{ "clrrwi", 3, PPC, "rlwinm %0,%1,0,0,31-(%2)" }, -{ "clrrwi.", 3, PPC, "rlwinm. %0,%1,0,0,31-(%2)" }, -{ "clrlslwi",4, PPC, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" }, -{ "clrlslwi.",4, PPC, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" }, - -}; - -const int powerpc_num_macros = - sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); diff --git a/opcodes/sh-dis.c b/opcodes/sh-dis.c deleted file mode 100644 index 8b6efa8a87c..00000000000 --- a/opcodes/sh-dis.c +++ /dev/null @@ -1,303 +0,0 @@ -/* Disassemble SH instructions. - Copyright (C) 1993, 94, 95, 96, 1997 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include <stdio.h> -#define STATIC_TABLE -#define DEFINE_TABLE - -#include "sh-opc.h" -#include "dis-asm.h" - -#define LITTLE_BIT 2 - -static int -print_insn_shx (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - fprintf_ftype fprintf_fn = info->fprintf_func; - void *stream = info->stream; - unsigned char insn[2]; - unsigned char nibs[4]; - int status; - int relmask = ~0; - sh_opcode_info *op; - - status = info->read_memory_func (memaddr, insn, 2, info); - - if (status != 0) - { - info->memory_error_func (status, memaddr, info); - return -1; - } - - if (info->flags & LITTLE_BIT) - { - nibs[0] = (insn[1] >> 4) & 0xf; - nibs[1] = insn[1] & 0xf; - - nibs[2] = (insn[0] >> 4) & 0xf; - nibs[3] = insn[0] & 0xf; - } - else - { - nibs[0] = (insn[0] >> 4) & 0xf; - nibs[1] = insn[0] & 0xf; - - nibs[2] = (insn[1] >> 4) & 0xf; - nibs[3] = insn[1] & 0xf; - } - - for (op = sh_table; op->name; op++) - { - int n; - int imm; - int rn; - int rm; - int rb; - - for (n = 0; n < 4; n++) - { - int i = op->nibbles[n]; - - if (i < 16) - { - if (nibs[n] == i) - continue; - goto fail; - } - switch (i) - { - case BRANCH_8: - imm = (nibs[2] << 4) | (nibs[3]); - if (imm & 0x80) - imm |= ~0xff; - imm = ((char)imm) * 2 + 4 ; - goto ok; - case BRANCH_12: - imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]); - if (imm & 0x800) - imm |= ~0xfff; - imm = imm * 2 + 4; - goto ok; - case IMM_4: - imm = nibs[3]; - goto ok; - case IMM_4BY2: - imm = nibs[3] <<1; - goto ok; - case IMM_4BY4: - imm = nibs[3] <<2; - goto ok; - case IMM_8: - imm = (nibs[2] << 4) | nibs[3]; - goto ok; - case PCRELIMM_8BY2: - imm = ((nibs[2] << 4) | nibs[3]) <<1; - relmask = ~1; - goto ok; - case PCRELIMM_8BY4: - imm = ((nibs[2] << 4) | nibs[3]) <<2; - relmask = ~3; - goto ok; - case IMM_8BY2: - imm = ((nibs[2] << 4) | nibs[3]) <<1; - goto ok; - case IMM_8BY4: - imm = ((nibs[2] << 4) | nibs[3]) <<2; - goto ok; - case DISP_8: - imm = (nibs[2] << 4) | (nibs[3]); - goto ok; - case DISP_4: - imm = nibs[3]; - goto ok; - case REG_N: - rn = nibs[n]; - break; - case REG_M: - rm = nibs[n]; - break; - case REG_B: - rb = nibs[n] & 0x07; - break; - default: - abort(); - } - } - - ok: - fprintf_fn (stream,"%s\t", op->name); - for (n = 0; n < 3 && op->arg[n] != A_END; n++) - { - if (n && op->arg[1] != A_END) - fprintf_fn (stream, ","); - switch (op->arg[n]) - { - case A_IMM: - fprintf_fn (stream, "#%d", (char)(imm)); - break; - case A_R0: - fprintf_fn (stream, "r0"); - break; - case A_REG_N: - fprintf_fn (stream, "r%d", rn); - break; - case A_INC_N: - fprintf_fn (stream, "@r%d+", rn); - break; - case A_DEC_N: - fprintf_fn (stream, "@-r%d", rn); - break; - case A_IND_N: - fprintf_fn (stream, "@r%d", rn); - break; - case A_DISP_REG_N: - fprintf_fn (stream, "@(%d,r%d)", imm, rn); - break; - case A_REG_M: - fprintf_fn (stream, "r%d", rm); - break; - case A_INC_M: - fprintf_fn (stream, "@r%d+", rm); - break; - case A_DEC_M: - fprintf_fn (stream, "@-r%d", rm); - break; - case A_IND_M: - fprintf_fn (stream, "@r%d", rm); - break; - case A_DISP_REG_M: - fprintf_fn (stream, "@(%d,r%d)", imm, rm); - break; - case A_REG_B: - fprintf_fn (stream, "r%d_bank", rb); - break; - case A_DISP_PC: - fprintf_fn (stream, "0x%0x", imm + 4 + (memaddr & relmask)); - break; - case A_IND_R0_REG_N: - fprintf_fn (stream, "@(r0,r%d)", rn); - break; - case A_IND_R0_REG_M: - fprintf_fn (stream, "@(r0,r%d)", rm); - break; - case A_DISP_GBR: - fprintf_fn (stream, "@(%d,gbr)",imm); - break; - case A_R0_GBR: - fprintf_fn (stream, "@(r0,gbr)"); - break; - case A_BDISP12: - case A_BDISP8: - (*info->print_address_func) (imm + memaddr, info); - break; - case A_SR: - fprintf_fn (stream, "sr"); - break; - case A_GBR: - fprintf_fn (stream, "gbr"); - break; - case A_VBR: - fprintf_fn (stream, "vbr"); - break; - case A_SSR: - fprintf_fn (stream, "ssr"); - break; - case A_SPC: - fprintf_fn (stream, "spc"); - break; - case A_MACH: - fprintf_fn (stream, "mach"); - break; - case A_MACL: - fprintf_fn (stream ,"macl"); - break; - case A_PR: - fprintf_fn (stream, "pr"); - break; - case F_REG_N: - fprintf_fn (stream, "fr%d", rn); - break; - case F_REG_M: - fprintf_fn (stream, "fr%d", rm); - break; - case FPSCR_M: - case FPSCR_N: - fprintf_fn (stream, "fpscr"); - break; - case FPUL_M: - case FPUL_N: - fprintf_fn (stream, "fpul"); - break; - case F_FR0: - fprintf_fn (stream, "fr0"); - break; - default: - abort(); - } - - } - - if (!(info->flags & 1) - && (op->name[0] == 'j' - || (op->name[0] == 'b' - && (op->name[1] == 'r' - || op->name[1] == 's')) - || (op->name[0] == 'r' && op->name[1] == 't') - || (op->name[0] == 'b' && op->name[2] == '.'))) - { - info->flags |= 1; - fprintf_fn (stream, "\t(slot "); - print_insn_shx (memaddr + 2, info); - info->flags &= ~1; - fprintf_fn (stream, ")"); - return 4; - } - - return 2; - fail: - ; - - } - fprintf_fn (stream, ".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]); - return 2; -} - -int -print_insn_shl (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - int r; - - info->flags = LITTLE_BIT; - r = print_insn_shx (memaddr, info); - return r; -} - -int -print_insn_sh (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - int r; - - info->flags = 0; - r = print_insn_shx (memaddr, info); - return r; -} diff --git a/opcodes/sh-opc.h b/opcodes/sh-opc.h deleted file mode 100644 index e9dce857977..00000000000 --- a/opcodes/sh-opc.h +++ /dev/null @@ -1,488 +0,0 @@ -/* Definitions for SH opcodes. - Copyright (C) 1993, 1994, 1995 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -typedef enum { - HEX_0, - HEX_1, - HEX_2, - HEX_3, - HEX_4, - HEX_5, - HEX_6, - HEX_7, - HEX_8, - HEX_9, - HEX_A, - HEX_B, - HEX_C, - HEX_D, - HEX_E, - HEX_F, - REG_N, - REG_M, - BRANCH_12, - BRANCH_8, - DISP_8, - DISP_4, - IMM_4, - IMM_4BY2, - IMM_4BY4, - PCRELIMM_8BY2, - PCRELIMM_8BY4, - IMM_8, - IMM_8BY2, - IMM_8BY4 -} sh_nibble_type; - -typedef enum { - A_END, - A_BDISP12, - A_BDISP8, - A_DEC_M, - A_DEC_N, - A_DISP_GBR, - A_DISP_PC, - A_DISP_REG_M, - A_DISP_REG_N, - A_GBR, - A_IMM, - A_INC_M, - A_INC_N, - A_IND_M, - A_IND_N, - A_IND_R0_REG_M, - A_IND_R0_REG_N, - A_MACH, - A_MACL, - A_PR, - A_R0, - A_R0_GBR, - A_REG_M, - A_REG_N, - A_SR, - A_VBR, - A_SSR, - A_SPC, -/* start-sanitize-sh3e */ - F_REG_N, - F_REG_M, - F_FR0, - FPUL_N, - FPUL_M, - FPSCR_N, - FPSCR_M -/* end-sanitize-sh3e */ -} sh_arg_type; - -typedef struct { - char *name; - sh_arg_type arg[4]; - sh_nibble_type nibbles[4]; -} sh_opcode_info; - -#ifdef DEFINE_TABLE - -sh_opcode_info sh_table[] = { - -/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM_8}}, - -/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}}, - -/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}}, - -/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}}, - -/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM_8}}, - -/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}}, - -/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM_8}}, - -/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}}, - -/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}}, - -/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}}, - -/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}}, - -/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}}, - -/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}}, - -/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}}, - -/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}}, - -/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}}, - -/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM_8}}, - -/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}}, - -/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}}, - -/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}}, - -/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}}, - -/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}}, - -/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}}, - -/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}}, - -/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}}, - -/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}}, - -/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}}, - -/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}}, - -/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}}, - -/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}}, - -/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}}, - -/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}}, - -/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}}, - -/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}}, - -/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}}, - -/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}}, - -/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}}, - -/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}}, - -/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}}, - -/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}}, - -/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}}, - -/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}}, - -/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}}, - -/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}}, - -/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}}, - -/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}}, - -/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}}, - -/* start-sanitize-sh3e */ -/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}}, - -/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}}, -/* end-sanitize-sh3e - -/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}}, - -/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}}, - -/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}}, - -/* start-sanitize-sh3e */ -/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}}, - -/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}}, -/* end-sanitize-sh3e */ - -/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}}, - -/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}}, - -/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM_8}}, - -/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}}, - -/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}}, - -/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}}, - -/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}}, - -/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM_4}}, - -/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM_8}}, - -/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}}, - -/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}}, - -/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}}, - -/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM_4}}, - -/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM_8}}, - -/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM_4BY4}}, - -/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}}, - -/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}}, - -/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}}, - -/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM_4BY4}}, - -/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM_8BY4}}, - -/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}}, - -/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}}, - -/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}}, - -/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}}, - -/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM_8BY4}}, - -/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}}, - -/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}}, - -/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}}, - -/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM_4BY2}}, - -/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM_8BY2}}, - -/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}}, - -/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}}, - -/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}}, - -/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}}, - -/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM_4BY2}}, - -/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM_8BY2}}, - -/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}}, - -/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}}, - -/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}}, - -/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}}, - -/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}}, - -/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}}, - -/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}}, - -/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}}, - -/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}}, - -/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM_8}}, - -/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}}, - -/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM_8}}, - -/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}}, - -/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}}, - -/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}}, - -/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}}, - -/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}}, - -/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}}, - -/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}}, -/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}}, - -/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}}, - -/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}}, - -/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}}, - -/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}}, - -/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}}, - -/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}}, - -/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}}, - -/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}}, - -/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}}, - -/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}}, - -/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}}, - -/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}}, - -/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}}, - -/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}}, - -/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}}, - -/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}}, - -/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}}, - -/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}}, - -/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}}, - -/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}}, - -/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}}, - -/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}}, - -/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}}, - -/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}}, - -/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}}, - -/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}}, - -/* start-sanitize-sh3e */ -/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}}, - -/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}}, -/* end-sanitize-sh3e */ - -/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}}, - -/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}}, - -/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}}, - -/* start-sanitize-sh3e */ -/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}}, - -/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}}, -/* end-sanitize-sh3e */ - -/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}}, - -/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}}, - -/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}}, - -/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}}, - -/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}}, - -/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}}, - -/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM_8}}, - -/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM_8}}, - -/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}}, - -/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM_8}}, - -/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM_8}}, - -/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}}, - -/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM_8}}, - -/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}}, - -/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}}, - -/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}}, - -/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}}, - -/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}}, - -/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}}, - -/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}}, - -/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}}, - -/* start-sanitize-sh3e */ -/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}}, - -/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}}, - -/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}}, - -/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}}, - -/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}}, - -/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}}, - -/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}}, - -/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}}, - -/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}}, - -/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}}, - -/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}}, - -/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}}, - -/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}}, - -/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}}, - -/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}}, - -/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}}, - -/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}}, - -/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}}, - -/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}}, - -/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}}, - -/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}}, - -/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}}, - -/* 1111nnnn00111101 ftrc <F_REG_M>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}}, - -/* 1111nnnn01111101 ftst/nan <F_REG_N> */{"ftst/nan",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}}, -/* end-sanitize-sh3e */ -{ 0 } -}; - -#endif diff --git a/opcodes/sparc-dis.c b/opcodes/sparc-dis.c deleted file mode 100644 index ee331f3e649..00000000000 --- a/opcodes/sparc-dis.c +++ /dev/null @@ -1,913 +0,0 @@ -/* Print SPARC instructions. - Copyright (C) 1989, 91-93, 1995, 1996 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "ansidecl.h" -#include "opcode/sparc.h" -#include "dis-asm.h" -#include "libiberty.h" -#include <string.h> - -/* Bitmask of v9 architectures. */ -#define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \ - | (1 << SPARC_OPCODE_ARCH_V9A)) -/* 1 if INSN is for v9 only. */ -#define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9)) -/* 1 if INSN is for v9. */ -#define V9_P(insn) (((insn)->architecture & MASK_V9) != 0) - -/* For faster lookup, after insns are sorted they are hashed. */ -/* ??? I think there is room for even more improvement. */ - -#define HASH_SIZE 256 -/* It is important that we only look at insn code bits as that is how the - opcode table is hashed. OPCODE_BITS is a table of valid bits for each - of the main types (0,1,2,3). */ -static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 }; -#define HASH_INSN(INSN) \ - ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19)) -struct opcode_hash { - struct opcode_hash *next; - struct sparc_opcode *opcode; -}; -static struct opcode_hash *opcode_hash_table[HASH_SIZE]; -static void build_hash_table (); - -/* Sign-extend a value which is N bits long. */ -#define SEX(value, bits) \ - ((((int)(value)) << ((8 * sizeof (int)) - bits)) \ - >> ((8 * sizeof (int)) - bits) ) - -static char *reg_names[] = -{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", - "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", - "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", - "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", - "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", - "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", - "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", - "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", - "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", - "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", - "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55", - "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63", -/* psr, wim, tbr, fpsr, cpsr are v8 only. */ - "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr" -}; - -#define freg_names (®_names[4 * 8]) - -/* These are ordered according to there register number in - rdpr and wrpr insns. */ -static char *v9_priv_reg_names[] = -{ - "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl", - "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", - "wstate", "fq" - /* "ver" - special cased */ -}; - -/* Macros used to extract instruction fields. Not all fields have - macros defined here, only those which are actually used. */ - -#define X_RD(i) (((i) >> 25) & 0x1f) -#define X_RS1(i) (((i) >> 14) & 0x1f) -#define X_LDST_I(i) (((i) >> 13) & 1) -#define X_ASI(i) (((i) >> 5) & 0xff) -#define X_RS2(i) (((i) >> 0) & 0x1f) -#define X_IMM13(i) (((i) >> 0) & 0x1fff) -#define X_DISP22(i) (((i) >> 0) & 0x3fffff) -#define X_IMM22(i) X_DISP22 (i) -#define X_DISP30(i) (((i) >> 0) & 0x3fffffff) - -/* These are for v9. */ -#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff)) -#define X_DISP19(i) (((i) >> 0) & 0x7ffff) -#define X_MEMBAR(i) ((i) & 0x7f) - -/* Here is the union which was used to extract instruction fields - before the shift and mask macros were written. - - union sparc_insn - { - unsigned long int code; - struct - { - unsigned int anop:2; - #define op ldst.anop - unsigned int anrd:5; - #define rd ldst.anrd - unsigned int op3:6; - unsigned int anrs1:5; - #define rs1 ldst.anrs1 - unsigned int i:1; - unsigned int anasi:8; - #define asi ldst.anasi - unsigned int anrs2:5; - #define rs2 ldst.anrs2 - #define shcnt rs2 - } ldst; - struct - { - unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1; - unsigned int IMM13:13; - #define imm13 IMM13.IMM13 - } IMM13; - struct - { - unsigned int anop:2; - unsigned int a:1; - unsigned int cond:4; - unsigned int op2:3; - unsigned int DISP22:22; - #define disp22 branch.DISP22 - #define imm22 disp22 - } branch; - struct - { - unsigned int anop:2; - unsigned int a:1; - unsigned int z:1; - unsigned int rcond:3; - unsigned int op2:3; - unsigned int DISP16HI:2; - unsigned int p:1; - unsigned int _rs1:5; - unsigned int DISP16LO:14; - } branch16; - struct - { - unsigned int anop:2; - unsigned int adisp30:30; - #define disp30 call.adisp30 - } call; - }; - - */ - -/* Nonzero if INSN is the opcode for a delayed branch. */ -static int -is_delayed_branch (insn) - unsigned long insn; -{ - struct opcode_hash *op; - - for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) - { - CONST struct sparc_opcode *opcode = op->opcode; - if ((opcode->match & insn) == opcode->match - && (opcode->lose & insn) == 0) - return (opcode->flags & F_DELAYED); - } - return 0; -} - -/* extern void qsort (); */ -static int compare_opcodes (); - -/* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value - to compare_opcodes. */ -static unsigned int current_arch_mask; -static int compute_arch_mask (); - -/* Print one instruction from MEMADDR on INFO->STREAM. - - We suffix the instruction with a comment that gives the absolute - address involved, as well as its symbolic form, if the instruction - is preceded by a findable `sethi' and it either adds an immediate - displacement to that register, or it is an `add' or `or' instruction - on that register. */ - -int -print_insn_sparc (memaddr, info) - bfd_vma memaddr; - disassemble_info *info; -{ - FILE *stream = info->stream; - bfd_byte buffer[4]; - unsigned long insn; - register unsigned int i; - register struct opcode_hash *op; - /* Nonzero of opcode table has been initialized. */ - static int opcodes_initialized = 0; - /* bfd mach number of last call. */ - static unsigned long current_mach = 0; - - if (!opcodes_initialized - || info->mach != current_mach) - { - current_arch_mask = compute_arch_mask (info->mach); - qsort ((char *) sparc_opcodes, sparc_num_opcodes, - sizeof (sparc_opcodes[0]), compare_opcodes); - build_hash_table (sparc_opcodes, opcode_hash_table, sparc_num_opcodes); - current_mach = info->mach; - opcodes_initialized = 1; - } - - { - int status = - (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - } - - insn = bfd_getb32 (buffer); - - info->insn_info_valid = 1; /* We do return this info */ - info->insn_type = dis_nonbranch; /* Assume non branch insn */ - info->branch_delay_insns = 0; /* Assume no delay */ - info->target = 0; /* Assume no target known */ - - for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) - { - CONST struct sparc_opcode *opcode = op->opcode; - - /* If the insn isn't supported by the current architecture, skip it. */ - if (! (opcode->architecture & current_arch_mask)) - continue; - - if ((opcode->match & insn) == opcode->match - && (opcode->lose & insn) == 0) - { - /* Nonzero means that we have found an instruction which has - the effect of adding or or'ing the imm13 field to rs1. */ - int imm_added_to_rs1 = 0; - - /* Nonzero means that we have found a plus sign in the args - field of the opcode table. */ - int found_plus = 0; - - /* Nonzero means we have an annulled branch. */ - int is_annulled = 0; - - /* Do we have an `add' or `or' instruction where rs1 is the same - as rsd, and which has the i bit set? */ - if ((opcode->match == 0x80102000 || opcode->match == 0x80002000) - /* (or) (add) */ - && X_RS1 (insn) == X_RD (insn)) - imm_added_to_rs1 = 1; - - if (X_RS1 (insn) != X_RD (insn) - && strchr (opcode->args, 'r') != 0) - /* Can't do simple format if source and dest are different. */ - continue; - if (X_RS2 (insn) != X_RD (insn) - && strchr (opcode->args, 'O') != 0) - /* Can't do simple format if source and dest are different. */ - continue; - - (*info->fprintf_func) (stream, opcode->name); - - { - register CONST char *s; - - if (opcode->args[0] != ',') - (*info->fprintf_func) (stream, " "); - for (s = opcode->args; *s != '\0'; ++s) - { - while (*s == ',') - { - (*info->fprintf_func) (stream, ","); - ++s; - switch (*s) { - case 'a': - (*info->fprintf_func) (stream, "a"); - is_annulled = 1; - ++s; - continue; - case 'N': - (*info->fprintf_func) (stream, "pn"); - ++s; - continue; - - case 'T': - (*info->fprintf_func) (stream, "pt"); - ++s; - continue; - - default: - break; - } /* switch on arg */ - } /* while there are comma started args */ - - (*info->fprintf_func) (stream, " "); - - switch (*s) - { - case '+': - found_plus = 1; - - /* note fall-through */ - default: - (*info->fprintf_func) (stream, "%c", *s); - break; - - case '#': - (*info->fprintf_func) (stream, "0"); - break; - -#define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n]) - case '1': - case 'r': - reg (X_RS1 (insn)); - break; - - case '2': - case 'O': - reg (X_RS2 (insn)); - break; - - case 'd': - reg (X_RD (insn)); - break; -#undef reg - -#define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n]) -#define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)]) - case 'e': - freg (X_RS1 (insn)); - break; - case 'v': /* double/even */ - case 'V': /* quad/multiple of 4 */ - fregx (X_RS1 (insn)); - break; - - case 'f': - freg (X_RS2 (insn)); - break; - case 'B': /* double/even */ - case 'R': /* quad/multiple of 4 */ - fregx (X_RS2 (insn)); - break; - - case 'g': - freg (X_RD (insn)); - break; - case 'H': /* double/even */ - case 'J': /* quad/multiple of 4 */ - fregx (X_RD (insn)); - break; -#undef freg -#undef fregx - -#define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n)) - case 'b': - creg (X_RS1 (insn)); - break; - - case 'c': - creg (X_RS2 (insn)); - break; - - case 'D': - creg (X_RD (insn)); - break; -#undef creg - - case 'h': - (*info->fprintf_func) (stream, "%%hi(%#x)", - (0xFFFFFFFF - & ((int) X_IMM22 (insn) << 10))); - break; - - case 'i': - { - int imm = SEX (X_IMM13 (insn), 13); - - /* Check to see whether we have a 1+i, and take - note of that fact. - - Note: because of the way we sort the table, - we will be matching 1+i rather than i+1, - so it is OK to assume that i is after +, - not before it. */ - if (found_plus) - imm_added_to_rs1 = 1; - - if (imm <= 9) - (*info->fprintf_func) (stream, "%d", imm); - else - (*info->fprintf_func) (stream, "%#x", imm); - } - break; - - case 'I': /* 11 bit immediate. */ - case 'j': /* 10 bit immediate. */ - { - int imm; - - if (*s == 'I') - imm = SEX (X_IMM13 (insn), 11); - else - imm = SEX (X_IMM13 (insn), 10); - - /* Check to see whether we have a 1+i, and take - note of that fact. - - Note: because of the way we sort the table, - we will be matching 1+i rather than i+1, - so it is OK to assume that i is after +, - not before it. */ - if (found_plus) - imm_added_to_rs1 = 1; - - if (imm <= 9) - (info->fprintf_func) (stream, "%d", imm); - else - (info->fprintf_func) (stream, "%#x", (unsigned) imm); - } - break; - - case 'K': - { - int mask = X_MEMBAR (insn); - int bit = 0x40, printed_one = 0; - char *name; - - if (mask == 0) - (info->fprintf_func) (stream, "0"); - else - while (bit) - { - if (mask & bit) - { - if (printed_one) - (info->fprintf_func) (stream, "|"); - name = sparc_decode_membar (bit); - (info->fprintf_func) (stream, "%s", name); - printed_one = 1; - } - bit >>= 1; - } - break; - } - - case 'k': - info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4; - (*info->print_address_func) (info->target, info); - break; - - case 'G': - info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4; - (*info->print_address_func) (info->target, info); - break; - - case '6': - case '7': - case '8': - case '9': - (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0'); - break; - - case 'z': - (*info->fprintf_func) (stream, "%%icc"); - break; - - case 'Z': - (*info->fprintf_func) (stream, "%%xcc"); - break; - - case 'E': - (*info->fprintf_func) (stream, "%%ccr"); - break; - - case 's': - (*info->fprintf_func) (stream, "%%fprs"); - break; - - case 'o': - (*info->fprintf_func) (stream, "%%asi"); - break; - - case 'W': - (*info->fprintf_func) (stream, "%%tick"); - break; - - case 'P': - (*info->fprintf_func) (stream, "%%pc"); - break; - - case '?': - if (X_RS1 (insn) == 31) - (*info->fprintf_func) (stream, "%%ver"); - else if ((unsigned) X_RS1 (insn) < 16) - (*info->fprintf_func) (stream, "%%%s", - v9_priv_reg_names[X_RS1 (insn)]); - else - (*info->fprintf_func) (stream, "%%reserved"); - break; - - case '!': - if ((unsigned) X_RD (insn) < 15) - (*info->fprintf_func) (stream, "%%%s", - v9_priv_reg_names[X_RD (insn)]); - else - (*info->fprintf_func) (stream, "%%reserved"); - break; - - case '*': - { - char *name = sparc_decode_prefetch (X_RD (insn)); - - if (name) - (*info->fprintf_func) (stream, "%s", name); - else - (*info->fprintf_func) (stream, "%d", X_RD (insn)); - break; - } - - case 'M': - (*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn)); - break; - - case 'm': - (*info->fprintf_func) (stream, "%%asr%d", X_RD (insn)); - break; - - case 'L': - info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4; - (*info->print_address_func) (info->target, info); - break; - - case 'n': - (*info->fprintf_func) - (stream, "%#x", SEX (X_DISP22 (insn), 22)); - break; - - case 'l': - info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4; - (*info->print_address_func) (info->target, info); - break; - - case 'A': - { - char *name = sparc_decode_asi (X_ASI (insn)); - - if (name) - (*info->fprintf_func) (stream, "%s", name); - else - (*info->fprintf_func) (stream, "(%d)", X_ASI (insn)); - break; - } - - case 'C': - (*info->fprintf_func) (stream, "%%csr"); - break; - - case 'F': - (*info->fprintf_func) (stream, "%%fsr"); - break; - - case 'p': - (*info->fprintf_func) (stream, "%%psr"); - break; - - case 'q': - (*info->fprintf_func) (stream, "%%fq"); - break; - - case 'Q': - (*info->fprintf_func) (stream, "%%cq"); - break; - - case 't': - (*info->fprintf_func) (stream, "%%tbr"); - break; - - case 'w': - (*info->fprintf_func) (stream, "%%wim"); - break; - - case 'x': - (*info->fprintf_func) (stream, "%d", - ((X_LDST_I (insn) << 8) - + X_ASI (insn))); - break; - - case 'y': - (*info->fprintf_func) (stream, "%%y"); - break; - - case 'u': - case 'U': - { - int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn); - char *name = sparc_decode_sparclet_cpreg (val); - - if (name) - (*info->fprintf_func) (stream, "%s", name); - else - (*info->fprintf_func) (stream, "%%cpreg(%d)", val); - break; - } - } - } - } - - /* If we are adding or or'ing something to rs1, then - check to see whether the previous instruction was - a sethi to the same register as in the sethi. - If so, attempt to print the result of the add or - or (in this context add and or do the same thing) - and its symbolic value. */ - if (imm_added_to_rs1) - { - unsigned long prev_insn; - int errcode; - - errcode = - (*info->read_memory_func) - (memaddr - 4, buffer, sizeof (buffer), info); - prev_insn = bfd_getb32 (buffer); - - if (errcode == 0) - { - /* If it is a delayed branch, we need to look at the - instruction before the delayed branch. This handles - sequences such as - - sethi %o1, %hi(_foo), %o1 - call _printf - or %o1, %lo(_foo), %o1 - */ - - if (is_delayed_branch (prev_insn)) - { - errcode = (*info->read_memory_func) - (memaddr - 8, buffer, sizeof (buffer), info); - prev_insn = bfd_getb32 (buffer); - } - } - - /* If there was a problem reading memory, then assume - the previous instruction was not sethi. */ - if (errcode == 0) - { - /* Is it sethi to the same register? */ - if ((prev_insn & 0xc1c00000) == 0x01000000 - && X_RD (prev_insn) == X_RS1 (insn)) - { - (*info->fprintf_func) (stream, "\t! "); - info->target = - (0xFFFFFFFF & (int) X_IMM22 (prev_insn) << 10) - | SEX (X_IMM13 (insn), 13); - (*info->print_address_func) (info->target, info); - info->insn_type = dis_dref; - info->data_size = 4; /* FIXME!!! */ - } - } - } - - if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR)) - { - /* FIXME -- check is_annulled flag */ - if (opcode->flags & F_UNBR) - info->insn_type = dis_branch; - if (opcode->flags & F_CONDBR) - info->insn_type = dis_condbranch; - if (opcode->flags & F_JSR) - info->insn_type = dis_jsr; - if (opcode->flags & F_DELAYED) - info->branch_delay_insns = 1; - } - - return sizeof (buffer); - } - } - - info->insn_type = dis_noninsn; /* Mark as non-valid instruction */ - (*info->fprintf_func) (stream, "unknown"); - return sizeof (buffer); -} - -/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */ - -static int -compute_arch_mask (mach) - unsigned long mach; -{ - switch (mach) - { - case 0 : - case bfd_mach_sparc : - return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8); - case bfd_mach_sparc_sparclet : - return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET); - case bfd_mach_sparc_sparclite : - /* sparclites insns are recognized by default (because that's how - they've always been treated, for better or worse). Kludge this by - indicating generic v8 is also selected. */ - return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) - | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)); - case bfd_mach_sparc_v8plus : - case bfd_mach_sparc_v9 : - return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); - case bfd_mach_sparc_v8plusa : - case bfd_mach_sparc_v9a : - return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A); - } - abort (); -} - -/* Compare opcodes A and B. */ - -static int -compare_opcodes (a, b) - char *a, *b; -{ - struct sparc_opcode *op0 = (struct sparc_opcode *) a; - struct sparc_opcode *op1 = (struct sparc_opcode *) b; - unsigned long int match0 = op0->match, match1 = op1->match; - unsigned long int lose0 = op0->lose, lose1 = op1->lose; - register unsigned int i; - - /* If one (and only one) insn isn't supported by the current architecture, - prefer the one that is. If neither are supported, but they're both for - the same architecture, continue processing. Otherwise (both unsupported - and for different architectures), prefer lower numbered arch's (fudged - by comparing the bitmasks). */ - if (op0->architecture & current_arch_mask) - { - if (! (op1->architecture & current_arch_mask)) - return -1; - } - else - { - if (op1->architecture & current_arch_mask) - return 1; - else if (op0->architecture != op1->architecture) - return op0->architecture - op1->architecture; - } - - /* If a bit is set in both match and lose, there is something - wrong with the opcode table. */ - if (match0 & lose0) - { - fprintf (stderr, "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n", - op0->name, match0, lose0); - op0->lose &= ~op0->match; - lose0 = op0->lose; - } - - if (match1 & lose1) - { - fprintf (stderr, "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n", - op1->name, match1, lose1); - op1->lose &= ~op1->match; - lose1 = op1->lose; - } - - /* Because the bits that are variable in one opcode are constant in - another, it is important to order the opcodes in the right order. */ - for (i = 0; i < 32; ++i) - { - unsigned long int x = 1 << i; - int x0 = (match0 & x) != 0; - int x1 = (match1 & x) != 0; - - if (x0 != x1) - return x1 - x0; - } - - for (i = 0; i < 32; ++i) - { - unsigned long int x = 1 << i; - int x0 = (lose0 & x) != 0; - int x1 = (lose1 & x) != 0; - - if (x0 != x1) - return x1 - x0; - } - - /* They are functionally equal. So as long as the opcode table is - valid, we can put whichever one first we want, on aesthetic grounds. */ - - /* Our first aesthetic ground is that aliases defer to real insns. */ - { - int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS); - if (alias_diff != 0) - /* Put the one that isn't an alias first. */ - return alias_diff; - } - - /* Except for aliases, two "identical" instructions had - better have the same opcode. This is a sanity check on the table. */ - i = strcmp (op0->name, op1->name); - if (i) - { - if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */ - return i; - else - fprintf (stderr, - "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n", - op0->name, op1->name); - } - - /* Fewer arguments are preferred. */ - { - int length_diff = strlen (op0->args) - strlen (op1->args); - if (length_diff != 0) - /* Put the one with fewer arguments first. */ - return length_diff; - } - - /* Put 1+i before i+1. */ - { - char *p0 = (char *) strchr(op0->args, '+'); - char *p1 = (char *) strchr(op1->args, '+'); - - if (p0 && p1) - { - /* There is a plus in both operands. Note that a plus - sign cannot be the first character in args, - so the following [-1]'s are valid. */ - if (p0[-1] == 'i' && p1[1] == 'i') - /* op0 is i+1 and op1 is 1+i, so op1 goes first. */ - return 1; - if (p0[1] == 'i' && p1[-1] == 'i') - /* op0 is 1+i and op1 is i+1, so op0 goes first. */ - return -1; - } - } - - /* Put 1,i before i,1. */ - { - int i0 = strncmp (op0->args, "i,1", 3) == 0; - int i1 = strncmp (op1->args, "i,1", 3) == 0; - - if (i0 ^ i1) - return i0 - i1; - } - - /* They are, as far as we can tell, identical. - Since qsort may have rearranged the table partially, there is - no way to tell which one was first in the opcode table as - written, so just say there are equal. */ - return 0; -} - -/* Build a hash table from the opcode table. */ - -static void -build_hash_table (table, hash_table, num_opcodes) - struct sparc_opcode *table; - struct opcode_hash **hash_table; - int num_opcodes; -{ - register int i; - int hash_count[HASH_SIZE]; - static struct opcode_hash *hash_buf = NULL; - - /* Start at the end of the table and work backwards so that each - chain is sorted. */ - - memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0])); - memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0])); - if (hash_buf != NULL) - free (hash_buf); - hash_buf = (struct opcode_hash *) xmalloc (sizeof (struct opcode_hash) * num_opcodes); - for (i = num_opcodes - 1; i >= 0; --i) - { - register int hash = HASH_INSN (sparc_opcodes[i].match); - register struct opcode_hash *h = &hash_buf[i]; - h->next = hash_table[hash]; - h->opcode = &sparc_opcodes[i]; - hash_table[hash] = h; - ++hash_count[hash]; - } - -#if 0 /* for debugging */ - { - int min_count = num_opcodes, max_count = 0; - int total; - - for (i = 0; i < HASH_SIZE; ++i) - { - if (hash_count[i] < min_count) - min_count = hash_count[i]; - if (hash_count[i] > max_count) - max_count = hash_count[i]; - total += hash_count[i]; - } - - printf ("Opcode hash table stats: min %d, max %d, ave %f\n", - min_count, max_count, (double) total / HASH_SIZE); - } -#endif -} diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c deleted file mode 100644 index f1aa070cb96..00000000000 --- a/opcodes/sparc-opc.c +++ /dev/null @@ -1,1921 +0,0 @@ -/* Table of opcodes for the sparc. - Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 1997 - Free Software Foundation, Inc. - -This file is part of the BFD library. - -BFD is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 2, or (at your option) any later -version. - -BFD is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with this software; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* FIXME-someday: perhaps the ,a's and such should be embedded in the - instruction's name rather than the args. This would make gas faster, pinsn - slower, but would mess up some macros a bit. xoxorich. */ - -#include <stdio.h> -#include "ansidecl.h" -#include "opcode/sparc.h" - -/* Some defines to make life easy. */ -#define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6) -#define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7) -#define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8) -#define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET) -#define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) -#define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) -#define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A) - -/* Bit masks of architectures supporting the insn. */ - -#define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \ - | MASK_SPARCLITE | MASK_V9 | MASK_V9A) -/* v6 insns not supported on the sparclet */ -#define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \ - | MASK_SPARCLITE | MASK_V9 | MASK_V9A) -#define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \ - | MASK_SPARCLITE | MASK_V9 | MASK_V9A) -/* Although not all insns are implemented in hardware, sparclite is defined - to be a superset of v8. Unimplemented insns trap and are then theoretically - implemented in software. - It's not clear that the same is true for sparclet, although the docs - suggest it is. Rather than complicating things, the sparclet assembler - recognizes all v8 insns. */ -#define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE | MASK_V9 | MASK_V9A) -#define sparclet (MASK_SPARCLET) -#define sparclite (MASK_SPARCLITE) -#define v9 (MASK_V9 | MASK_V9A) -#define v9a (MASK_V9A) -/* v6 insns not supported by v9 */ -#define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \ - | MASK_SPARCLET | MASK_SPARCLITE) -/* v9a instructions which would appear to be aliases to v9's impdep's - otherwise */ -#define v9notv9a (MASK_V9) - -/* Table of opcode architectures. - The order is defined in opcode/sparc.h. - The names must match the arguments to gas' -A<arch> option in tc-sparc.c. -*/ -const struct sparc_opcode_arch sparc_opcode_archs[] = { - { "v6", MASK_V6 }, - { "v7", MASK_V6 | MASK_V7 }, - { "v8", MASK_V6 | MASK_V7 | MASK_V8 }, - { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET }, - { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE }, - /* ??? Don't some v8 priviledged insns conflict with v9? */ - { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 }, - /* v9 with ultrasparc additions */ - { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A }, - { NULL, 0 } -}; - -/* Given NAME, return it's architecture entry. */ - -enum sparc_opcode_arch_val -sparc_opcode_lookup_arch (name) - const char *name; -{ - const struct sparc_opcode_arch *p; - - for (p = &sparc_opcode_archs[0]; p->name; ++p) - { - if (strcmp (name, p->name) == 0) - return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]); - } - - return SPARC_OPCODE_ARCH_BAD; -} - -/* Branch condition field. */ -#define COND(x) (((x)&0xf)<<25) - -/* v9: Move (MOVcc and FMOVcc) condition field. */ -#define MCOND(x,i_or_f) ((((i_or_f)&1)<<18)|(((x)>>11)&(0xf<<14))) /* v9 */ - -/* v9: Move register (MOVRcc and FMOVRcc) condition field. */ -#define RCOND(x) (((x)&0x7)<<10) /* v9 */ - -#define CONDA (COND(0x8)) -#define CONDCC (COND(0xd)) -#define CONDCS (COND(0x5)) -#define CONDE (COND(0x1)) -#define CONDG (COND(0xa)) -#define CONDGE (COND(0xb)) -#define CONDGU (COND(0xc)) -#define CONDL (COND(0x3)) -#define CONDLE (COND(0x2)) -#define CONDLEU (COND(0x4)) -#define CONDN (COND(0x0)) -#define CONDNE (COND(0x9)) -#define CONDNEG (COND(0x6)) -#define CONDPOS (COND(0xe)) -#define CONDVC (COND(0xf)) -#define CONDVS (COND(0x7)) - -#define CONDNZ CONDNE -#define CONDZ CONDE -#define CONDGEU CONDCC -#define CONDLU CONDCS - -#define FCONDA (COND(0x8)) -#define FCONDE (COND(0x9)) -#define FCONDG (COND(0x6)) -#define FCONDGE (COND(0xb)) -#define FCONDL (COND(0x4)) -#define FCONDLE (COND(0xd)) -#define FCONDLG (COND(0x2)) -#define FCONDN (COND(0x0)) -#define FCONDNE (COND(0x1)) -#define FCONDO (COND(0xf)) -#define FCONDU (COND(0x7)) -#define FCONDUE (COND(0xa)) -#define FCONDUG (COND(0x5)) -#define FCONDUGE (COND(0xc)) -#define FCONDUL (COND(0x3)) -#define FCONDULE (COND(0xe)) - -#define FCONDNZ FCONDNE -#define FCONDZ FCONDE - -#define ICC (0) /* v9 */ -#define XCC (1<<12) /* v9 */ -#define FCC(x) (((x)&0x3)<<11) /* v9 */ -#define FBFCC(x) (((x)&0x3)<<20) /* v9 */ - -/* The order of the opcodes in the table is significant: - - * The assembler requires that all instances of the same mnemonic must - be consecutive. If they aren't, the assembler will bomb at runtime. - - * The disassembler should not care about the order of the opcodes. - -*/ - -/* Entries for commutative arithmetic operations. */ -/* ??? More entries can make use of this. */ -#define COMMUTEOP(opcode, op3, arch_mask) \ -{ opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, arch_mask }, \ -{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, arch_mask }, \ -{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, arch_mask } - -const struct sparc_opcode sparc_opcodes[] = { - -{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, v6 }, -{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, v6 }, /* ld [rs1+%g0],d */ -{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, v6 }, -{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, v6 }, -{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, v6 }, -{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ld [rs1+0],d */ -{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, v6 }, -{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, v6 }, /* ld [rs1+%g0],d */ -{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, v6 }, -{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0, v6 }, -{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", 0, v6 }, -{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, v6 }, /* ld [rs1+0],d */ - -{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, v6 }, -{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+%g0],d */ -{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, v6 }, -{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, v6 }, -{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, v6 }, -{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+0],d */ - -{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0, v6notv9 }, -{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", 0, v6notv9 }, /* ld [rs1+%g0],d */ -{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0, v6notv9 }, -{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0, v6notv9 }, -{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", 0, v6notv9 }, -{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ld [rs1+0],d */ -{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0, v6notv9 }, -{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", 0, v6notv9 }, /* ld [rs1+%g0],d */ -{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0, v6notv9 }, -{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0, v6notv9 }, -{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", 0, v6notv9 }, -{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, v6notv9 }, /* ld [rs1+0],d */ - -/* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the - 'ld' pseudo-op in v9. */ -{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS, v9 }, -{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", F_ALIAS, v9 }, /* ld [rs1+%g0],d */ -{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS, v9 }, -{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS, v9 }, -{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", F_ALIAS, v9 }, -{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS, v9 }, /* ld [rs1+0],d */ - -{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, v6 }, -{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldd [rs1+%g0],d */ -{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0, v6 }, -{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0, v6 }, -{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", 0, v6 }, -{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldd [rs1+0],d */ -{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", 0, v6 }, -{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H", 0, v6 }, /* ldd [rs1+%g0],d */ -{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H", 0, v6 }, -{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H", 0, v6 }, -{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0, "[i],H", 0, v6 }, -{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", 0, v6 }, /* ldd [rs1+0],d */ - -{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, v6notv9 }, -{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+%g0],d */ -{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0, v6notv9 }, -{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0, v6notv9 }, -{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i],D", 0, v6notv9 }, -{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+0],d */ - -{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, v9 }, -{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J", 0, v9 }, /* ldd [rs1+%g0],d */ -{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J", 0, v9 }, -{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J", 0, v9 }, -{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0, "[i],J", 0, v9 }, -{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, v9 }, /* ldd [rs1+0],d */ - -{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, v6 }, -{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsb [rs1+%g0],d */ -{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0, v6 }, -{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0, v6 }, -{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0, "[i],d", 0, v6 }, -{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsb [rs1+0],d */ - -{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsh [rs1+%g0],d */ -{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, v6 }, -{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0, v6 }, -{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0, v6 }, -{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0, "[i],d", 0, v6 }, -{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsh [rs1+0],d */ - -{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, v6 }, -{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldstub [rs1+%g0],d */ -{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0, v6 }, -{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0, v6 }, -{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0, "[i],d", 0, v6 }, -{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldstub [rs1+0],d */ - -{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, v9 }, -{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldsw [rs1+%g0],d */ -{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0, v9 }, -{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0, v9 }, -{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0, "[i],d", 0, v9 }, -{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldsw [rs1+0],d */ - -{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, v6 }, -{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldub [rs1+%g0],d */ -{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0, v6 }, -{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0, v6 }, -{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0, "[i],d", 0, v6 }, -{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldub [rs1+0],d */ - -{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, v6 }, -{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* lduh [rs1+%g0],d */ -{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0, v6 }, -{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0, v6 }, -{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0, "[i],d", 0, v6 }, -{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* lduh [rs1+0],d */ - -{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, v9 }, -{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldx [rs1+%g0],d */ -{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0, v9 }, -{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0, v9 }, -{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0, "[i],d", 0, v9 }, -{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldx [rs1+0],d */ - -{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, v9 }, -{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1), "[1],F", 0, v9 }, /* ld [rs1+%g0],d */ -{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, v9 }, -{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, v9 }, -{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1), "[i],F", 0, v9 }, -{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, v9 }, /* ld [rs1+0],d */ - -{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, v6 }, -{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lda [rs1+%g0],d */ -{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, v9 }, -{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", 0, v9 }, -{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ -{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g", 0, v9 }, -{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1]A,g", 0, v9 }, /* lda [rs1+%g0],d */ -{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g", 0, v9 }, -{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g", 0, v9 }, -{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i]o,g", 0, v9 }, -{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, v9 }, /* ld [rs1+0],d */ - -{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, v6 }, -{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldda [rs1+%g0],d */ -{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0, v9 }, -{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", 0, v9 }, -{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ - -{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H", 0, v9 }, -{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0, "[1]A,H", 0, v9 }, /* ldda [rs1+%g0],d */ -{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H", 0, v9 }, -{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H", 0, v9 }, -{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i]o,H", 0, v9 }, -{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, v9 }, /* ld [rs1+0],d */ - -{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J", 0, v9 }, -{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0, "[1]A,J", 0, v9 }, /* ldd [rs1+%g0],d */ -{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J", 0, v9 }, -{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J", 0, v9 }, -{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0, "[i]o,J", 0, v9 }, -{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, v9 }, /* ldd [rs1+0],d */ - -{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0, v6 }, -{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsba [rs1+%g0],d */ -{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d", 0, v9 }, -{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d", 0, v9 }, -{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ - -{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0, v6 }, -{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsha [rs1+%g0],d */ -{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d", 0, v9 }, -{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d", 0, v9 }, -{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ - -{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0, v6 }, -{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldstuba [rs1+%g0],d */ -{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d", 0, v9 }, -{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d", 0, v9 }, -{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ - -{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0, v9 }, -{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */ -{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d", 0, v9 }, -{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d", 0, v9 }, -{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ - -{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0, v6 }, -{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduba [rs1+%g0],d */ -{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d", 0, v9 }, -{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d", 0, v9 }, -{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ - -{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0, v6 }, -{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduha [rs1+%g0],d */ -{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d", 0, v9 }, -{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d", 0, v9 }, -{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ - -{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", F_ALIAS, v9 }, /* lduwa === lda */ -{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", F_ALIAS, v9 }, /* lda [rs1+%g0],d */ -{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", F_ALIAS, v9 }, -{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", F_ALIAS, v9 }, -{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", F_ALIAS, v9 }, -{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, v9 }, /* ld [rs1+0],d */ - -{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0, v9 }, /* lduwa === lda */ -{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */ -{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d", 0, v9 }, -{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d", 0, v9 }, -{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ - -{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, -{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* st d,[rs1+%g0] */ -{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", 0, v6 }, -{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", 0, v6 }, -{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", 0, v6 }, -{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* st d,[rs1+0] */ -{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, v6 }, -{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", 0, v6 }, /* st d[rs1+%g0] */ -{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", 0, v6 }, -{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", 0, v6 }, -{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]", 0, v6 }, -{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", 0, v6 }, /* st d,[rs1+0] */ - -{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 }, -{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */ -{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", 0, v6notv9 }, -{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", 0, v6notv9 }, -{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]", 0, v6notv9 }, -{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+0] */ -{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, v6notv9 }, -{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */ -{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", 0, v6notv9 }, -{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", 0, v6notv9 }, -{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]", 0, v6notv9 }, -{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+0] */ - -{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", 0, v6 }, -{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", 0, v6 }, /* st d,[rs1+%g0] */ -{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]", 0, v6 }, -{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]", 0, v6 }, -{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]", 0, v6 }, -{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0), "F,[1]", 0, v6 }, /* st d,[rs1+0] */ - -{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, -{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ -{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, -{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, -{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, -{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ - -{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0, v6 }, -{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* sta d,[rs1+%g0] */ -{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", 0, v9 }, -{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", 0, v9 }, -{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", 0, v9 }, -{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* st d,[rs1+0] */ - -{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A", 0, v9 }, -{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, v9 }, /* sta d,[rs1+%g0] */ -{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o", 0, v9 }, -{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o", 0, v9 }, -{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "g,[i]o", 0, v9 }, -{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, v9 }, /* st d,[rs1+0] */ - -{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, -{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ -{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, -{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, -{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, -{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ - -{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, -{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+%g0] */ -{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0, v6 }, -{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0, v6 }, -{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", 0, v6 }, -{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+0] */ - -{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0, v6 }, -{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stba d,[rs1+%g0] */ -{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", 0, v9 }, -{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", 0, v9 }, -{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", 0, v9 }, -{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stb d,[rs1+0] */ - -{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, -{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* std d,[rs1+%g0] */ -{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0, v6 }, -{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0, v6 }, -{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", 0, v6 }, -{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* std d,[rs1+0] */ - -{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, v6notv9 }, -{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ -{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0, v6notv9 }, -{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0, v6notv9 }, -{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "q,[i]", 0, v6notv9 }, -{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ -{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, v6 }, -{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]", 0, v6 }, /* std d,[rs1+%g0] */ -{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]", 0, v6 }, -{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]", 0, v6 }, -{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0, "H,[i]", 0, v6 }, -{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, v6 }, /* std d,[rs1+0] */ - -{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, v6notv9 }, -{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ -{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0, v6notv9 }, -{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0, v6notv9 }, -{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "Q,[i]", 0, v6notv9 }, -{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ -{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 }, -{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ -{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0, v6notv9 }, -{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0, v6notv9 }, -{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "D,[i]", 0, v6notv9 }, -{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ - -{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0, v6 }, -{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stda d,[rs1+%g0] */ -{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", 0, v9 }, -{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", 0, v9 }, -{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", 0, v9 }, -{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* std d,[rs1+0] */ -{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A", 0, v9 }, -{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, v9 }, /* stda d,[rs1+%g0] */ -{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o", 0, v9 }, -{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o", 0, v9 }, -{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "H,[i]o", 0, v9 }, -{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, v9 }, /* std d,[rs1+0] */ - -{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, -{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+%g0] */ -{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0, v6 }, -{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0, v6 }, -{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", 0, v6 }, -{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+0] */ - -{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0, v6 }, -{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stha ,[rs1+%g0] */ -{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", 0, v9 }, -{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", 0, v9 }, -{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", 0, v9 }, -{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* sth d,[rs1+0] */ - -{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, v9 }, -{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+%g0] */ -{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0, v9 }, -{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0, v9 }, -{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0, "d,[i]", 0, v9 }, -{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+0] */ - -{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, v9 }, -{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+%g0] */ -{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[1+i]", 0, v9 }, -{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[i+1]", 0, v9 }, -{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1), "F,[i]", 0, v9 }, -{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+0] */ - -{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0, v9 }, -{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, v9 }, /* stxa d,[rs1+%g0] */ -{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o", 0, v9 }, -{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o", 0, v9 }, -{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0, "d,[i]o", 0, v9 }, -{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stx d,[rs1+0] */ - -{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, v9 }, -{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]", 0, v9 }, /* stq [rs1+%g0] */ -{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]", 0, v9 }, -{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]", 0, v9 }, -{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "J,[i]", 0, v9 }, -{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, v9 }, /* stq [rs1+0] */ - -{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, v9 }, -{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A", 0, v9 }, /* stqa [rs1+%g0] */ -{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o", 0, v9 }, -{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o", 0, v9 }, -{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "J,[i]o", 0, v9 }, -{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, v9 }, /* stqa [rs1+0] */ - -{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, v7 }, -{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, v7 }, /* swap [rs1+%g0],d */ -{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, v7 }, -{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, v7 }, -{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d", 0, v7 }, -{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, v7 }, /* swap [rs1+0],d */ - -{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, v7 }, -{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, v7 }, /* swapa [rs1+%g0],d */ -{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d", 0, v9 }, -{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d", 0, v9 }, -{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* swap [rs1+0],d */ - -{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v6 }, /* restore %g0,%g0,%g0 */ -{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, v6 }, -{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0), "", 0, v6 }, /* restore %g0,0,%g0 */ - -{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* rett rs1+rs2 */ -{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1,%g0 */ -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* rett rs1+X */ -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */ -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */ -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X */ -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1+0 */ - -{ "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, v6 }, -{ "save", 0x81e00000, ~0x81e00000, "", F_ALIAS, v6 }, - -{ "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */ -{ "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %o7+8,%g0 */ - -{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR|F_DELAYED, v6 }, -{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,d */ -{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,d */ -{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,d */ -{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d", F_JSR|F_DELAYED, v6 }, -{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d", F_JSR|F_DELAYED, v6 }, - -{ "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 }, -{ "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 }, -{ "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 }, -{ "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 }, -{ "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0, "i", 0, v9 }, - -{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", 0, v8 }, -{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", 0, v8 }, /* flush rs1+%g0 */ -{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", 0, v8 }, /* flush rs1+0 */ -{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", 0, v8 }, /* flush %g0+i */ -{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", 0, v8 }, -{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", 0, v8 }, - -/* IFLUSH was renamed to FLUSH in v8. */ -{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, v6 }, -{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, v6 }, /* flush rs1+%g0 */ -{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, v6 }, /* flush rs1+0 */ -{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, v6 }, -{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, v6 }, -{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, v6 }, - -{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, v9 }, -{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1", 0, v9 }, /* return rs1+%g0 */ -{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, v9 }, /* return rs1+0 */ -{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0, "i", 0, v9 }, /* return %g0+i */ -{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i", 0, v9 }, -{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1", 0, v9 }, - -{ "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v9 }, - -{ "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, v9 }, -{ "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, v8 }, - -{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0), "[1+2],*", 0, v9 }, -{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0, "[1],*", 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */ -{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[1+i],*", 0, v9 }, -{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[i+1],*", 0, v9 }, -{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0, "[i],*", 0, v9 }, -{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*", 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */ -{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0), "[1+2]A,*", 0, v9 }, -{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0, "[1]A,*", 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */ -{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[1+i]o,*", 0, v9 }, -{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[i+1]o,*", 0, v9 }, -{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0, "[i]o,*", 0, v9 }, -{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*", 0, v9 }, /* prefetcha [rs1+0],d */ - -{ "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, -{ "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, -{ "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, -{ "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, -{ "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, -{ "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, - -{ "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, -{ "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, -{ "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, -{ "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, -{ "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, -{ "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, - -{ "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, v6 }, - -{ "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, sparclite }, -{ "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0, sparclite }, - -{ "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, sparclet|sparclite }, -{ "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d", 0, sparclet|sparclite }, - -{ "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS2_G0|ASI(~0),"2,d", 0, v9 }, -{ "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS2_G0, "i,d", 0, v9 }, - -{ "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "d", F_ALIAS, v6 }, /* or %g0,%g0,d */ -{ "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0), "d", F_ALIAS, v6 }, /* or %g0,0,d */ -{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, -{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+%g0] */ -{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, -{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, -{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, -{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+0] */ - -{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, -{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+%g0] */ -{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, -{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, -{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, -{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+0] */ - -{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, -{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+%g0] */ -{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, -{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, -{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, -{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+0] */ - -{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v9 }, -{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+%g0] */ -{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[1+i]", F_ALIAS, v9 }, -{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[i+1]", F_ALIAS, v9 }, -{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v9 }, -{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+0] */ - -{ "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, v6 }, -{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, v6 }, - -/* This is not a commutative instruction. */ -{ "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, v6 }, - -/* This is not a commutative instruction. */ -{ "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, v6 }, - -{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0), "1", 0, v6 }, /* orcc rs1, %g0, %g0 */ -{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, v6 }, /* orcc %g0, rs2, %g0 */ -{ "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1", 0, v6 }, /* orcc rs1, 0, %g0 */ - -{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, v8 }, /* wr r,r,%asrX */ -{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, v8 }, /* wr r,i,%asrX */ -{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */ -{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, v6 }, /* wr r,r,%y */ -{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", 0, v6 }, /* wr r,i,%y */ -{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */ -{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, v6notv9 }, /* wr r,r,%psr */ -{ "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", 0, v6notv9 }, /* wr r,i,%psr */ -{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */ -{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, v6notv9 }, /* wr r,r,%wim */ -{ "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", 0, v6notv9 }, /* wr r,i,%wim */ -{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */ -{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, v6notv9 }, /* wr r,r,%tbr */ -{ "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", 0, v6notv9 }, /* wr r,i,%tbr */ -{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */ - -{ "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, v9 }, /* wr r,r,%ccr */ -{ "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, v9 }, /* wr r,i,%ccr */ -{ "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, v9 }, /* wr r,r,%asi */ -{ "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, v9 }, /* wr r,i,%asi */ -{ "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, v9 }, /* wr r,r,%fprs */ -{ "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s", 0, v9 }, /* wr r,i,%fprs */ - -{ "wr", F3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pcr */ -{ "wr", F3(2, 0x30, 1)|RD(16), F3(~2, ~0x30, ~1)|RD(~16), "1,i,_", 0, v9a }, /* wr r,i,%pcr */ -{ "wr", F3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pic */ -{ "wr", F3(2, 0x30, 1)|RD(17), F3(~2, ~0x30, ~1)|RD(~17), "1,i,_", 0, v9a }, /* wr r,i,%pic */ -{ "wr", F3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%dcr */ -{ "wr", F3(2, 0x30, 1)|RD(18), F3(~2, ~0x30, ~1)|RD(~18), "1,i,_", 0, v9a }, /* wr r,i,%dcr */ -{ "wr", F3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%gsr */ -{ "wr", F3(2, 0x30, 1)|RD(19), F3(~2, ~0x30, ~1)|RD(~19), "1,i,_", 0, v9a }, /* wr r,i,%gsr */ -{ "wr", F3(2, 0x30, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%set_softint */ -{ "wr", F3(2, 0x30, 1)|RD(20), F3(~2, ~0x30, ~1)|RD(~20), "1,i,_", 0, v9a }, /* wr r,i,%set_softint */ -{ "wr", F3(2, 0x30, 0)|RD(21), F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%clear_softint */ -{ "wr", F3(2, 0x30, 1)|RD(21), F3(~2, ~0x30, ~1)|RD(~21), "1,i,_", 0, v9a }, /* wr r,i,%clear_softint */ -{ "wr", F3(2, 0x30, 0)|RD(22), F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%softint */ -{ "wr", F3(2, 0x30, 1)|RD(22), F3(~2, ~0x30, ~1)|RD(~22), "1,i,_", 0, v9a }, /* wr r,i,%softint */ -{ "wr", F3(2, 0x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%tick_cmpr */ -{ "wr", F3(2, 0x30, 1)|RD(23), F3(~2, ~0x30, ~1)|RD(~23), "1,i,_", 0, v9a }, /* wr r,i,%tick_cmpr */ - -{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, v8 }, /* rd %asrX,r */ -{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, v6 }, /* rd %y,r */ -{ "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", 0, v6notv9 }, /* rd %psr,r */ -{ "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", 0, v6notv9 }, /* rd %wim,r */ -{ "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", 0, v6notv9 }, /* rd %tbr,r */ - -{ "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, v9 }, /* rd %ccr,r */ -{ "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, v9 }, /* rd %asi,r */ -{ "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, v9 }, /* rd %tick,r */ -{ "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, v9 }, /* rd %pc,r */ -{ "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, v9 }, /* rd %fprs,r */ - -{ "rd", F3(2, 0x28, 0)|RS1(16), F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pcr,r */ -{ "rd", F3(2, 0x28, 0)|RS1(17), F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pic,r */ -{ "rd", F3(2, 0x28, 0)|RS1(18), F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0), "/,d", 0, v9a }, /* rd %dcr,r */ -{ "rd", F3(2, 0x28, 0)|RS1(19), F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0), "/,d", 0, v9a }, /* rd %gsr,r */ -{ "rd", F3(2, 0x28, 0)|RS1(22), F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0), "/,d", 0, v9a }, /* rd %softint,r */ -{ "rd", F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, v9a }, /* rd %tick_cmpr,r */ - -{ "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, v9 }, /* rdpr %priv,r */ -{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!", 0, v9 }, /* wrpr r1,r2,%priv */ -{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|SIMM13(~0), "1,!", 0, v9 }, /* wrpr r1,%priv */ -{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "1,i,!", 0, v9 }, /* wrpr r1,i,%priv */ -{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,1,!", F_ALIAS, v9 }, /* wrpr i,r1,%priv */ -{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!", 0, v9 }, /* wrpr i,%priv */ - -/* ??? This group seems wrong. A three operand move? */ -{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */ -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */ -{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", F_ALIAS, v6 }, /* wr r,r,%y */ -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", F_ALIAS, v6 }, /* wr r,i,%y */ -{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", F_ALIAS, v6notv9 }, /* wr r,r,%psr */ -{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", F_ALIAS, v6notv9 }, /* wr r,i,%psr */ -{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", F_ALIAS, v6notv9 }, /* wr r,r,%wim */ -{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", F_ALIAS, v6notv9 }, /* wr r,i,%wim */ -{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", F_ALIAS, v6notv9 }, /* wr r,r,%tbr */ -{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", F_ALIAS, v6notv9 }, /* wr r,i,%tbr */ - -{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS, v8 }, /* rd %asr1,r */ -{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", F_ALIAS, v6 }, /* rd %y,r */ -{ "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", F_ALIAS, v6notv9 }, /* rd %psr,r */ -{ "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", F_ALIAS, v6notv9 }, /* rd %wim,r */ -{ "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", F_ALIAS, v6notv9 }, /* rd %tbr,r */ - -{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */ -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "i,m", F_ALIAS, v8 }, /* wr %g0,i,%asrX */ -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,0,%asrX */ -{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */ -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "i,y", F_ALIAS, v6 }, /* wr %g0,i,%y */ -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,0,%y */ -{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */ -{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "i,p", F_ALIAS, v6notv9 }, /* wr %g0,i,%psr */ -{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,0,%psr */ -{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */ -{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "i,w", F_ALIAS, v6notv9 }, /* wr %g0,i,%wim */ -{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,0,%wim */ -{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */ -{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "i,t", F_ALIAS, v6notv9 }, /* wr %g0,i,%tbr */ -{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,0,%tbr */ - -{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d", 0, v6 }, /* or %g0,rs2,d */ -{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0, "i,d", 0, v6 }, /* or %g0,i,d */ -{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d", 0, v6 }, /* or rs1,%g0,d */ -{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d", 0, v6 }, /* or rs1,0,d */ - -{ "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, v6 }, -{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, v6 }, - -{ "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* or rd,rs2,rd */ -{ "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS, v6 }, /* or rd,i,rd */ - -/* This is not a commutative instruction. */ -{ "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, v6 }, - -/* This is not a commutative instruction. */ -{ "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, v6 }, - -{ "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* andn rd,rs2,rd */ -{ "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS, v6 }, /* andn rd,i,rd */ - -{ "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0), "1,2", 0, v6 }, /* subcc rs1,rs2,%g0 */ -{ "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0, "1,i", 0, v6 }, /* subcc rs1,i,%g0 */ - -{ "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, v6 }, - -{ "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, v6 }, - -{ "subx", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, -{ "subx", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v6notv9 }, -{ "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v9 }, -{ "subc", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v9 }, - -{ "subxcc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, -{ "subxcc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v6notv9 }, -{ "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v9 }, -{ "subccc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v9 }, - -{ "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, v6 }, -{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, v6 }, - -{ "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, v6 }, -{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, v6 }, - -{ "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* sub rd,1,rd */ -{ "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r", F_ALIAS, v8 }, /* sub rd,imm,rd */ -{ "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* subcc rd,1,rd */ -{ "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r", F_ALIAS, v8 }, /* subcc rd,imm,rd */ -{ "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* add rd,1,rd */ -{ "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r", F_ALIAS, v8 }, /* add rd,imm,rd */ -{ "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* addcc rd,1,rd */ -{ "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r", F_ALIAS, v8 }, /* addcc rd,imm,rd */ - -{ "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, v6 }, /* andcc rs1,rs2,%g0 */ -{ "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, v6 }, /* andcc rs1,i,%g0 */ - -{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, v6 }, /* sub %g0,rs2,rd */ -{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, v6 }, /* sub %g0,rd,rd */ - -{ "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, v6 }, -{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, v6 }, -{ "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, v6 }, -{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, v6 }, - -{ "addx", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, -{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v6notv9 }, -{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v6notv9 }, -{ "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v9 }, -{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v9 }, -{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v9 }, - -{ "addxcc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, -{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v6notv9 }, -{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v6notv9 }, -{ "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v9 }, -{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v9 }, -{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v9 }, - -{ "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, v8 }, -{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, v8 }, -{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, v8 }, -{ "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, v8 }, -{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, v8 }, -{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, v8 }, -{ "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, v8 }, -{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, v8 }, -{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, v8 }, -{ "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, v8 }, -{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, v8 }, -{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, v8 }, -{ "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, v8 }, -{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, v8 }, -{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, v8 }, -{ "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, v8 }, -{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, v8 }, -{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, v8 }, -{ "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, v8 }, -{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, v8 }, -{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, v8 }, -{ "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, v8 }, -{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, v8 }, -{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, v8 }, - -{ "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, v9 }, -{ "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, v9 }, -{ "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, v9 }, -{ "sdivx", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, v9 }, -{ "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, v9 }, -{ "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, v9 }, - -{ "call", F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, v6 }, -{ "call", F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, v6 }, - -{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%o7 */ -{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#", F_JSR|F_DELAYED, v6 }, -{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%o7 */ -{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR|F_DELAYED, v6 }, -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+i,%o7 */ -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i,#", F_JSR|F_DELAYED, v6 }, -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1", F_JSR|F_DELAYED, v6 }, /* jmpl i+rs1,%o7 */ -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1,#", F_JSR|F_DELAYED, v6 }, -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,%o7 */ -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i,#", F_JSR|F_DELAYED, v6 }, -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,%o7 */ -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR|F_DELAYED, v6 }, - - -/* Conditional instructions. - - Because this part of the table was such a mess earlier, I have - macrofied it so that all the branches and traps are generated from - a single-line description of each condition value. John Gilmore. */ - -/* Define branches -- one annulled, one without, etc. */ -#define br(opcode, mask, lose, flags) \ - { opcode, (mask)|ANNUL, (lose), ",a l", (flags), v6 }, \ - { opcode, (mask) , (lose)|ANNUL, "l", (flags), v6 } - -#define brx(opcode, mask, lose, flags) /* v9 */ \ - { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G", (flags), v9 }, \ - { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G", (flags), v9 }, \ - { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G", (flags), v9 }, \ - { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), v9 }, \ - { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G", (flags), v9 }, \ - { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), v9 }, \ - { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G", (flags), v9 }, \ - { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G", (flags), v9 }, \ - { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G", (flags), v9 }, \ - { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), v9 }, \ - { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G", (flags), v9 }, \ - { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), v9 } - -/* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */ -#define tr(opcode, mask, lose, flags) \ - { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), v9 }, /* %g0 + imm */ \ - { opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), v9 }, /* rs1 + imm */ \ - { opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), v9 }, /* rs1 + rs2 */ \ - { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), v9 }, /* rs1 + %g0 */ \ - { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, v9 }, /* %g0 + imm */ \ - { opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, v9 }, /* rs1 + imm */ \ - { opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, v9 }, /* rs1 + rs2 */ \ - { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, v9 }, /* rs1 + %g0 */ \ - { opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), v6 }, /* %g0 + imm */ \ - { opcode, (mask)|IMMED, (lose), "1+i", (flags), v6 }, /* rs1 + imm */ \ - { opcode, (mask), IMMED|(lose), "1+2", (flags), v6 }, /* rs1 + rs2 */ \ - { opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), v6 } /* rs1 + %g0 */ - -/* v9: We must put `brx' before `br', to ensure that we never match something - v9: against an expression unless it is an expression. Otherwise, we end - v9: up with undefined symbol tables entries, because they get added, but - v9: are not deleted if the pattern fails to match. */ - -/* Define both branches and traps based on condition mask */ -#define cond(bop, top, mask, flags) \ - brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \ - br(bop, F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \ - tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR))) - -/* Define all the conditions, all the branches, all the traps. */ - -/* Standard branch, trap mnemonics */ -cond ("b", "ta", CONDA, F_UNBR), -/* Alternative form (just for assembly, not for disassembly) */ -cond ("ba", "t", CONDA, F_UNBR|F_ALIAS), - -cond ("bcc", "tcc", CONDCC, F_CONDBR), -cond ("bcs", "tcs", CONDCS, F_CONDBR), -cond ("be", "te", CONDE, F_CONDBR), -cond ("beq", "teq", CONDE, F_CONDBR|F_ALIAS), -cond ("bg", "tg", CONDG, F_CONDBR), -cond ("bgt", "tgt", CONDG, F_CONDBR|F_ALIAS), -cond ("bge", "tge", CONDGE, F_CONDBR), -cond ("bgeu", "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */ -cond ("bgu", "tgu", CONDGU, F_CONDBR), -cond ("bl", "tl", CONDL, F_CONDBR), -cond ("blt", "tlt", CONDL, F_CONDBR|F_ALIAS), -cond ("ble", "tle", CONDLE, F_CONDBR), -cond ("bleu", "tleu", CONDLEU, F_CONDBR), -cond ("blu", "tlu", CONDLU, F_CONDBR|F_ALIAS), /* for cs */ -cond ("bn", "tn", CONDN, F_CONDBR), -cond ("bne", "tne", CONDNE, F_CONDBR), -cond ("bneg", "tneg", CONDNEG, F_CONDBR), -cond ("bnz", "tnz", CONDNZ, F_CONDBR|F_ALIAS), /* for ne */ -cond ("bpos", "tpos", CONDPOS, F_CONDBR), -cond ("bvc", "tvc", CONDVC, F_CONDBR), -cond ("bvs", "tvs", CONDVS, F_CONDBR), -cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */ - -#undef cond -#undef br -#undef brr /* v9 */ -#undef tr - -#define brr(opcode, mask, lose, flags) /* v9 */ \ - { opcode, (mask)|BPRED, ANNUL|(lose), "1,k", F_DELAYED|(flags), v9 }, \ - { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k", F_DELAYED|(flags), v9 }, \ - { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k", F_DELAYED|(flags), v9 }, \ - { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), v9 }, \ - { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k", F_DELAYED|(flags), v9 }, \ - { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), v9 } - -#define condr(bop, mask, flags) /* v9 */ \ - brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */ - -/* v9 */ condr("brnz", 0x5, F_CONDBR), -/* v9 */ condr("brz", 0x1, F_CONDBR), -/* v9 */ condr("brgez", 0x7, F_CONDBR), -/* v9 */ condr("brlz", 0x3, F_CONDBR), -/* v9 */ condr("brlez", 0x2, F_CONDBR), -/* v9 */ condr("brgz", 0x6, F_CONDBR), - -#undef condr /* v9 */ -#undef brr /* v9 */ - -#define movr(opcode, mask, flags) /* v9 */ \ - { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), v9 }, \ - { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), v9 } - -#define fmrrs(opcode, mask, lose, flags) /* v9 */ \ - { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, v9 } -#define fmrrd(opcode, mask, lose, flags) /* v9 */ \ - { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, v9 } -#define fmrrq(opcode, mask, lose, flags) /* v9 */ \ - { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, v9 } - -#define fmovrs(mop, mask, flags) /* v9 */ \ - fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */ -#define fmovrd(mop, mask, flags) /* v9 */ \ - fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */ -#define fmovrq(mop, mask, flags) /* v9 */ \ - fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */ - -/* v9 */ movr("movrne", 0x5, 0), -/* v9 */ movr("movre", 0x1, 0), -/* v9 */ movr("movrgez", 0x7, 0), -/* v9 */ movr("movrlz", 0x3, 0), -/* v9 */ movr("movrlez", 0x2, 0), -/* v9 */ movr("movrgz", 0x6, 0), -/* v9 */ movr("movrnz", 0x5, F_ALIAS), -/* v9 */ movr("movrz", 0x1, F_ALIAS), - -/* v9 */ fmovrs("fmovrsne", 0x5, 0), -/* v9 */ fmovrs("fmovrse", 0x1, 0), -/* v9 */ fmovrs("fmovrsgez", 0x7, 0), -/* v9 */ fmovrs("fmovrslz", 0x3, 0), -/* v9 */ fmovrs("fmovrslez", 0x2, 0), -/* v9 */ fmovrs("fmovrsgz", 0x6, 0), -/* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS), -/* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS), - -/* v9 */ fmovrd("fmovrdne", 0x5, 0), -/* v9 */ fmovrd("fmovrde", 0x1, 0), -/* v9 */ fmovrd("fmovrdgez", 0x7, 0), -/* v9 */ fmovrd("fmovrdlz", 0x3, 0), -/* v9 */ fmovrd("fmovrdlez", 0x2, 0), -/* v9 */ fmovrd("fmovrdgz", 0x6, 0), -/* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS), -/* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS), - -/* v9 */ fmovrq("fmovrqne", 0x5, 0), -/* v9 */ fmovrq("fmovrqe", 0x1, 0), -/* v9 */ fmovrq("fmovrqgez", 0x7, 0), -/* v9 */ fmovrq("fmovrqlz", 0x3, 0), -/* v9 */ fmovrq("fmovrqlez", 0x2, 0), -/* v9 */ fmovrq("fmovrqgz", 0x6, 0), -/* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS), -/* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS), - -#undef movr /* v9 */ -#undef fmovr /* v9 */ -#undef fmrr /* v9 */ - -#define movicc(opcode, cond, flags) /* v9 */ \ - { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11), "Z,2,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11), "Z,I,d", flags, v9 } - -#define movfcc(opcode, fcond, flags) /* v9 */ \ - { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, v9 } - -#define movcc(opcode, cond, fcond, flags) /* v9 */ \ - movfcc (opcode, fcond, flags), /* v9 */ \ - movicc (opcode, cond, flags) /* v9 */ - -/* v9 */ movcc ("mova", CONDA, FCONDA, 0), -/* v9 */ movicc ("movcc", CONDCC, 0), -/* v9 */ movicc ("movgeu", CONDGEU, F_ALIAS), -/* v9 */ movicc ("movcs", CONDCS, 0), -/* v9 */ movicc ("movlu", CONDLU, F_ALIAS), -/* v9 */ movcc ("move", CONDE, FCONDE, 0), -/* v9 */ movcc ("movg", CONDG, FCONDG, 0), -/* v9 */ movcc ("movge", CONDGE, FCONDGE, 0), -/* v9 */ movicc ("movgu", CONDGU, 0), -/* v9 */ movcc ("movl", CONDL, FCONDL, 0), -/* v9 */ movcc ("movle", CONDLE, FCONDLE, 0), -/* v9 */ movicc ("movleu", CONDLEU, 0), -/* v9 */ movfcc ("movlg", FCONDLG, 0), -/* v9 */ movcc ("movn", CONDN, FCONDN, 0), -/* v9 */ movcc ("movne", CONDNE, FCONDNE, 0), -/* v9 */ movicc ("movneg", CONDNEG, 0), -/* v9 */ movcc ("movnz", CONDNZ, FCONDNZ, F_ALIAS), -/* v9 */ movfcc ("movo", FCONDO, 0), -/* v9 */ movicc ("movpos", CONDPOS, 0), -/* v9 */ movfcc ("movu", FCONDU, 0), -/* v9 */ movfcc ("movue", FCONDUE, 0), -/* v9 */ movfcc ("movug", FCONDUG, 0), -/* v9 */ movfcc ("movuge", FCONDUGE, 0), -/* v9 */ movfcc ("movul", FCONDUL, 0), -/* v9 */ movfcc ("movule", FCONDULE, 0), -/* v9 */ movicc ("movvc", CONDVC, 0), -/* v9 */ movicc ("movvs", CONDVS, 0), -/* v9 */ movcc ("movz", CONDZ, FCONDZ, F_ALIAS), - -#undef movicc /* v9 */ -#undef movfcc /* v9 */ -#undef movcc /* v9 */ - -#define FM_SF 1 /* v9 - values for fpsize */ -#define FM_DF 2 /* v9 */ -#define FM_QF 3 /* v9 */ - -#define fmovicc(opcode, fpsize, cond, flags) /* v9 */ \ -{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z,f,g", flags, v9 }, \ -{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z,f,g", flags, v9 } - -#define fmovfcc(opcode, fpsize, fcond, flags) /* v9 */ \ -{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6,f,g", flags, v9 }, \ -{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7,f,g", flags, v9 }, \ -{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8,f,g", flags, v9 }, \ -{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9,f,g", flags, v9 } - -/* FIXME: use fmovicc/fmovfcc? */ /* v9 */ -#define fmovcc(opcode, fpsize, cond, fcond, flags) /* v9 */ \ -{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z,f,g", flags | F_FLOAT, v9 }, \ -{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6,f,g", flags | F_FLOAT, v9 }, \ -{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z,f,g", flags | F_FLOAT, v9 }, \ -{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7,f,g", flags | F_FLOAT, v9 }, \ -{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8,f,g", flags | F_FLOAT, v9 }, \ -{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9,f,g", flags | F_FLOAT, v9 } - -/* v9 */ fmovcc ("fmovda", FM_DF, CONDA, FCONDA, 0), -/* v9 */ fmovcc ("fmovqa", FM_QF, CONDA, FCONDA, 0), -/* v9 */ fmovcc ("fmovsa", FM_SF, CONDA, FCONDA, 0), -/* v9 */ fmovicc ("fmovdcc", FM_DF, CONDCC, 0), -/* v9 */ fmovicc ("fmovqcc", FM_QF, CONDCC, 0), -/* v9 */ fmovicc ("fmovscc", FM_SF, CONDCC, 0), -/* v9 */ fmovicc ("fmovdcs", FM_DF, CONDCS, 0), -/* v9 */ fmovicc ("fmovqcs", FM_QF, CONDCS, 0), -/* v9 */ fmovicc ("fmovscs", FM_SF, CONDCS, 0), -/* v9 */ fmovcc ("fmovde", FM_DF, CONDE, FCONDE, 0), -/* v9 */ fmovcc ("fmovqe", FM_QF, CONDE, FCONDE, 0), -/* v9 */ fmovcc ("fmovse", FM_SF, CONDE, FCONDE, 0), -/* v9 */ fmovcc ("fmovdg", FM_DF, CONDG, FCONDG, 0), -/* v9 */ fmovcc ("fmovqg", FM_QF, CONDG, FCONDG, 0), -/* v9 */ fmovcc ("fmovsg", FM_SF, CONDG, FCONDG, 0), -/* v9 */ fmovcc ("fmovdge", FM_DF, CONDGE, FCONDGE, 0), -/* v9 */ fmovcc ("fmovqge", FM_QF, CONDGE, FCONDGE, 0), -/* v9 */ fmovcc ("fmovsge", FM_SF, CONDGE, FCONDGE, 0), -/* v9 */ fmovicc ("fmovdgeu", FM_DF, CONDGEU, F_ALIAS), -/* v9 */ fmovicc ("fmovqgeu", FM_QF, CONDGEU, F_ALIAS), -/* v9 */ fmovicc ("fmovsgeu", FM_SF, CONDGEU, F_ALIAS), -/* v9 */ fmovicc ("fmovdgu", FM_DF, CONDGU, 0), -/* v9 */ fmovicc ("fmovqgu", FM_QF, CONDGU, 0), -/* v9 */ fmovicc ("fmovsgu", FM_SF, CONDGU, 0), -/* v9 */ fmovcc ("fmovdl", FM_DF, CONDL, FCONDL, 0), -/* v9 */ fmovcc ("fmovql", FM_QF, CONDL, FCONDL, 0), -/* v9 */ fmovcc ("fmovsl", FM_SF, CONDL, FCONDL, 0), -/* v9 */ fmovcc ("fmovdle", FM_DF, CONDLE, FCONDLE, 0), -/* v9 */ fmovcc ("fmovqle", FM_QF, CONDLE, FCONDLE, 0), -/* v9 */ fmovcc ("fmovsle", FM_SF, CONDLE, FCONDLE, 0), -/* v9 */ fmovicc ("fmovdleu", FM_DF, CONDLEU, 0), -/* v9 */ fmovicc ("fmovqleu", FM_QF, CONDLEU, 0), -/* v9 */ fmovicc ("fmovsleu", FM_SF, CONDLEU, 0), -/* v9 */ fmovfcc ("fmovdlg", FM_DF, FCONDLG, 0), -/* v9 */ fmovfcc ("fmovqlg", FM_QF, FCONDLG, 0), -/* v9 */ fmovfcc ("fmovslg", FM_SF, FCONDLG, 0), -/* v9 */ fmovicc ("fmovdlu", FM_DF, CONDLU, F_ALIAS), -/* v9 */ fmovicc ("fmovqlu", FM_QF, CONDLU, F_ALIAS), -/* v9 */ fmovicc ("fmovslu", FM_SF, CONDLU, F_ALIAS), -/* v9 */ fmovcc ("fmovdn", FM_DF, CONDN, FCONDN, 0), -/* v9 */ fmovcc ("fmovqn", FM_QF, CONDN, FCONDN, 0), -/* v9 */ fmovcc ("fmovsn", FM_SF, CONDN, FCONDN, 0), -/* v9 */ fmovcc ("fmovdne", FM_DF, CONDNE, FCONDNE, 0), -/* v9 */ fmovcc ("fmovqne", FM_QF, CONDNE, FCONDNE, 0), -/* v9 */ fmovcc ("fmovsne", FM_SF, CONDNE, FCONDNE, 0), -/* v9 */ fmovicc ("fmovdneg", FM_DF, CONDNEG, 0), -/* v9 */ fmovicc ("fmovqneg", FM_QF, CONDNEG, 0), -/* v9 */ fmovicc ("fmovsneg", FM_SF, CONDNEG, 0), -/* v9 */ fmovcc ("fmovdnz", FM_DF, CONDNZ, FCONDNZ, F_ALIAS), -/* v9 */ fmovcc ("fmovqnz", FM_QF, CONDNZ, FCONDNZ, F_ALIAS), -/* v9 */ fmovcc ("fmovsnz", FM_SF, CONDNZ, FCONDNZ, F_ALIAS), -/* v9 */ fmovfcc ("fmovdo", FM_DF, FCONDO, 0), -/* v9 */ fmovfcc ("fmovqo", FM_QF, FCONDO, 0), -/* v9 */ fmovfcc ("fmovso", FM_SF, FCONDO, 0), -/* v9 */ fmovicc ("fmovdpos", FM_DF, CONDPOS, 0), -/* v9 */ fmovicc ("fmovqpos", FM_QF, CONDPOS, 0), -/* v9 */ fmovicc ("fmovspos", FM_SF, CONDPOS, 0), -/* v9 */ fmovfcc ("fmovdu", FM_DF, FCONDU, 0), -/* v9 */ fmovfcc ("fmovqu", FM_QF, FCONDU, 0), -/* v9 */ fmovfcc ("fmovsu", FM_SF, FCONDU, 0), -/* v9 */ fmovfcc ("fmovdue", FM_DF, FCONDUE, 0), -/* v9 */ fmovfcc ("fmovque", FM_QF, FCONDUE, 0), -/* v9 */ fmovfcc ("fmovsue", FM_SF, FCONDUE, 0), -/* v9 */ fmovfcc ("fmovdug", FM_DF, FCONDUG, 0), -/* v9 */ fmovfcc ("fmovqug", FM_QF, FCONDUG, 0), -/* v9 */ fmovfcc ("fmovsug", FM_SF, FCONDUG, 0), -/* v9 */ fmovfcc ("fmovduge", FM_DF, FCONDUGE, 0), -/* v9 */ fmovfcc ("fmovquge", FM_QF, FCONDUGE, 0), -/* v9 */ fmovfcc ("fmovsuge", FM_SF, FCONDUGE, 0), -/* v9 */ fmovfcc ("fmovdul", FM_DF, FCONDUL, 0), -/* v9 */ fmovfcc ("fmovqul", FM_QF, FCONDUL, 0), -/* v9 */ fmovfcc ("fmovsul", FM_SF, FCONDUL, 0), -/* v9 */ fmovfcc ("fmovdule", FM_DF, FCONDULE, 0), -/* v9 */ fmovfcc ("fmovqule", FM_QF, FCONDULE, 0), -/* v9 */ fmovfcc ("fmovsule", FM_SF, FCONDULE, 0), -/* v9 */ fmovicc ("fmovdvc", FM_DF, CONDVC, 0), -/* v9 */ fmovicc ("fmovqvc", FM_QF, CONDVC, 0), -/* v9 */ fmovicc ("fmovsvc", FM_SF, CONDVC, 0), -/* v9 */ fmovicc ("fmovdvs", FM_DF, CONDVS, 0), -/* v9 */ fmovicc ("fmovqvs", FM_QF, CONDVS, 0), -/* v9 */ fmovicc ("fmovsvs", FM_SF, CONDVS, 0), -/* v9 */ fmovcc ("fmovdz", FM_DF, CONDZ, FCONDZ, F_ALIAS), -/* v9 */ fmovcc ("fmovqz", FM_QF, CONDZ, FCONDZ, F_ALIAS), -/* v9 */ fmovcc ("fmovsz", FM_SF, CONDZ, FCONDZ, F_ALIAS), - -#undef fmovicc /* v9 */ -#undef fmovfcc /* v9 */ -#undef fmovcc /* v9 */ -#undef FM_DF /* v9 */ -#undef FM_QF /* v9 */ -#undef FM_SF /* v9 */ - -/* Coprocessor branches. */ -#define CBR(opcode, mask, lose, flags, arch) \ - { opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED, arch }, \ - { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED, arch } - -/* Floating point branches. */ -#define FBR(opcode, mask, lose, flags) \ - { opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED|F_FBR, v6 }, \ - { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED|F_FBR, v6 } - -/* V9 extended floating point branches. */ -#define FBRX(opcode, mask, lose, flags) /* v9 */ \ - { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, v9 } - -/* v9: We must put `FBRX' before `FBR', to ensure that we never match - v9: something against an expression unless it is an expression. Otherwise, - v9: we end up with undefined symbol tables entries, because they get added, - v9: but are not deleted if the pattern fails to match. */ - -#define CONDFC(fop, cop, mask, flags) \ - FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ - FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \ - CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet) - -#define CONDFCL(fop, cop, mask, flags) \ - FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ - FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \ - CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6) - -#define CONDF(fop, mask, flags) \ - FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ - FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags) - -CONDFC ("fb", "cb", 0x8, 0), -CONDFCL ("fba", "cba", 0x8, F_ALIAS), -CONDFC ("fbe", "cb0", 0x9, 0), -CONDF ("fbz", 0x9, F_ALIAS), -CONDFC ("fbg", "cb2", 0x6, 0), -CONDFC ("fbge", "cb02", 0xb, 0), -CONDFC ("fbl", "cb1", 0x4, 0), -CONDFC ("fble", "cb01", 0xd, 0), -CONDFC ("fblg", "cb12", 0x2, 0), -CONDFCL ("fbn", "cbn", 0x0, 0), -CONDFC ("fbne", "cb123", 0x1, 0), -CONDF ("fbnz", 0x1, F_ALIAS), -CONDFC ("fbo", "cb012", 0xf, 0), -CONDFC ("fbu", "cb3", 0x7, 0), -CONDFC ("fbue", "cb03", 0xa, 0), -CONDFC ("fbug", "cb23", 0x5, 0), -CONDFC ("fbuge", "cb023", 0xc, 0), -CONDFC ("fbul", "cb13", 0x3, 0), -CONDFC ("fbule", "cb013", 0xe, 0), - -#undef CONDFC -#undef CONDFCL -#undef CONDF -#undef CBR -#undef FBR -#undef FBRX /* v9 */ - -{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%g0 */ -{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%g0 */ -{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+i,%g0 */ -{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* jmpl i+rs1,%g0 */ -{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* jmpl %g0+i,%g0 */ -{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+0,%g0 */ - -{ "nop", F2(0, 4), 0xfeffffff, "", 0, v6 }, /* sethi 0, %g0 */ - -{ "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "Sh,d", F_ALIAS, v6 }, -{ "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "Sh,d", F_ALIAS, v9 }, -{ "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "Sh,d", F_ALIAS, v9 }, -{ "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, v9 }, - -{ "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 }, - -{ "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, v6 }, -{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, v6 }, -{ "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d", 0, v6 }, -{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d", 0, v6 }, - -{ "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, v6 }, -{ "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "tsubcctv", F3(2, 0x23, 1), F3(~2, ~0x23, ~1), "1,i,d", 0, v6 }, - -{ "unimp", F2(0x0, 0x0), 0xffc00000, "n", 0, v6notv9 }, -{ "illtrap", F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, v9 }, - -/* This *is* a commutative instruction. */ -{ "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, v6 }, -{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, v6 }, -/* This *is* a commutative instruction. */ -{ "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, v6 }, -{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, v6 }, -{ "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, v6 }, -{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, v6 }, -{ "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, v6 }, -{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, v6 }, - -{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, v6 }, /* xnor rs1,%0,rd */ -{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, v6 }, /* xnor rd,%0,rd */ - -{ "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* xor rd,rs2,rd */ -{ "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS, v6 }, /* xor rd,i,rd */ - -/* FPop1 and FPop2 are not instructions. Don't accept them. */ - -{ "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, v6 }, -{ "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, v6 }, -{ "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, v8 }, - -{ "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,g", F_FLOAT, v9 }, -{ "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,g", F_FLOAT, v9 }, -{ "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,g", F_FLOAT, v9 }, - -{ "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, v6 }, -{ "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, v6 }, -{ "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, v8 }, - -{ "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "f,H", F_FLOAT, v9 }, -{ "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "f,g", F_FLOAT, v9 }, -{ "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "f,J", F_FLOAT, v9 }, - -{ "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, v8 }, -{ "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, v6 }, -{ "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, v8 }, -{ "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, v8 }, -{ "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, v6 }, -{ "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, v8 }, - -{ "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, v6 }, -{ "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, v8 }, -{ "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, v6 }, -{ "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, v6 }, -{ "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, v8 }, -{ "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, v6 }, - -{ "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, v8 }, -{ "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, v8 }, - -{ "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, v7 }, -{ "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, v8 }, -{ "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, v7 }, - -{ "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, v9 }, -{ "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, v9 }, -{ "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, v6 }, -{ "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, v9 }, -{ "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, v9 }, -{ "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, v6 }, -{ "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, v9 }, -{ "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, v9 }, -{ "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, v6 }, - -{ "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, v6 }, -{ "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, v8 }, -{ "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, v6 }, -{ "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, v6 }, -{ "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, v8 }, -{ "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, v6 }, - -#define CMPFCC(x) (((x)&0x3)<<25) - -{ "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RD_G0, "v,B", F_FLOAT, v6 }, -{ "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B", F_FLOAT, v9 }, -{ "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B", F_FLOAT, v9 }, -{ "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B", F_FLOAT, v9 }, -{ "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B", F_FLOAT, v9 }, -{ "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RD_G0, "v,B", F_FLOAT, v6 }, -{ "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B", F_FLOAT, v9 }, -{ "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B", F_FLOAT, v9 }, -{ "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B", F_FLOAT, v9 }, -{ "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B", F_FLOAT, v9 }, -{ "fcmpq", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT, v8 }, -{ "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT, v9 }, -{ "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT, v9 }, -{ "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT, v9 }, -{ "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT, v9 }, -{ "fcmpeq", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT, v8 }, -{ "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT, v9 }, -{ "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT, v9 }, -{ "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT, v9 }, -{ "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT, v9 }, -{ "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f", F_FLOAT, v6 }, -{ "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f", F_FLOAT, v9 }, -{ "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f", F_FLOAT, v9 }, -{ "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f", F_FLOAT, v9 }, -{ "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f", F_FLOAT, v9 }, -{ "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f", F_FLOAT, v6 }, -{ "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f", F_FLOAT, v9 }, -{ "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f", F_FLOAT, v9 }, -{ "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f", F_FLOAT, v9 }, -{ "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f", F_FLOAT, v9 }, - -/* These Extended FPop (FIFO) instructions are new in the Fujitsu - MB86934, replacing the CPop instructions from v6 and later - processors. */ - -#define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, sparclite } -#define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op), args, 0, sparclite } -#define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0, args, 0, sparclite } - -EFPOP1_2 ("efitod", 0x0c8, "f,H"), -EFPOP1_2 ("efitos", 0x0c4, "f,g"), -EFPOP1_2 ("efdtoi", 0x0d2, "B,g"), -EFPOP1_2 ("efstoi", 0x0d1, "f,g"), -EFPOP1_2 ("efstod", 0x0c9, "f,H"), -EFPOP1_2 ("efdtos", 0x0c6, "B,g"), -EFPOP1_2 ("efmovs", 0x001, "f,g"), -EFPOP1_2 ("efnegs", 0x005, "f,g"), -EFPOP1_2 ("efabss", 0x009, "f,g"), -EFPOP1_2 ("efsqrtd", 0x02a, "B,H"), -EFPOP1_2 ("efsqrts", 0x029, "f,g"), -EFPOP1_3 ("efaddd", 0x042, "v,B,H"), -EFPOP1_3 ("efadds", 0x041, "e,f,g"), -EFPOP1_3 ("efsubd", 0x046, "v,B,H"), -EFPOP1_3 ("efsubs", 0x045, "e,f,g"), -EFPOP1_3 ("efdivd", 0x04e, "v,B,H"), -EFPOP1_3 ("efdivs", 0x04d, "e,f,g"), -EFPOP1_3 ("efmuld", 0x04a, "v,B,H"), -EFPOP1_3 ("efmuls", 0x049, "e,f,g"), -EFPOP1_3 ("efsmuld", 0x069, "e,f,H"), -EFPOP2_2 ("efcmpd", 0x052, "v,B"), -EFPOP2_2 ("efcmped", 0x056, "v,B"), -EFPOP2_2 ("efcmps", 0x051, "e,f"), -EFPOP2_2 ("efcmpes", 0x055, "e,f"), - -#undef EFPOP1_2 -#undef EFPOP1_3 -#undef EFPOP2_2 - -/* These are marked F_ALIAS, so that they won't conflict with sparclite insns - present. Otherwise, the F_ALIAS flag is ignored. */ -{ "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, v6notv9 }, -{ "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, v6notv9 }, - -/* sparclet specific insns */ - -COMMUTEOP ("umac", 0x3e, sparclet), -COMMUTEOP ("smac", 0x3f, sparclet), -COMMUTEOP ("umacd", 0x2e, sparclet), -COMMUTEOP ("smacd", 0x2f, sparclet), -COMMUTEOP ("umuld", 0x09, sparclet), -COMMUTEOP ("smuld", 0x0d, sparclet), - -{ "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, sparclet }, -{ "shuffle", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, sparclet }, - -/* The manual isn't completely accurate on these insns. The `rs2' field is - treated as being 6 bits to account for 6 bit immediates to cpush. It is - assumed that it is intended that bit 5 is 0 when rs2 contains a reg. */ -#define BIT5 (1<<5) -{ "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, sparclet }, -{ "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, sparclet }, -{ "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, sparclet }, -{ "cpush", F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0), "1,Y", 0, sparclet }, -{ "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, sparclet }, -{ "cpusha", F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0), "1,Y", 0, sparclet }, -{ "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, sparclet }, -#undef BIT5 - -/* sparclet coprocessor branch insns */ -#define SLCBCC2(opcode, mask, lose) \ - { opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR, sparclet }, \ - { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, sparclet } -#define SLCBCC(opcode, mask) \ - SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask))) - -/* cbn,cba can't be defined here because they're defined elsewhere and GAS - requires all mnemonics of the same name to be consecutive. */ -/*SLCBCC("cbn", 0), - already defined */ -SLCBCC("cbe", 1), -SLCBCC("cbf", 2), -SLCBCC("cbef", 3), -SLCBCC("cbr", 4), -SLCBCC("cber", 5), -SLCBCC("cbfr", 6), -SLCBCC("cbefr", 7), -/*SLCBCC("cba", 8), - already defined */ -SLCBCC("cbne", 9), -SLCBCC("cbnf", 10), -SLCBCC("cbnef", 11), -SLCBCC("cbnr", 12), -SLCBCC("cbner", 13), -SLCBCC("cbnfr", 14), -SLCBCC("cbnefr", 15), - -#undef SLCBCC2 -#undef SLCBCC - -{ "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, v9 }, -{ "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, v9 }, -{ "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, v9 }, -{ "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, v9 }, - -/* v9 synthetic insns */ -/* FIXME: still missing "signx d", and "clruw d". Can't be done here. */ -{ "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, v9 }, /* bn,a,pt %xcc,label */ -{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* sra rs1,%g0,rd */ -{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* srl rs1,%g0,rd */ -{ "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P,rs2,rd */ -{ "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */ -{ "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */ -{ "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */ - -/* Ultrasparc extensions */ -{ "shutdown", F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, v9a }, - -/* FIXME: Do we want to mark these as F_FLOAT, or something similar? */ -{ "fpadd16", F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, v9a }, -{ "fpadd16s", F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, v9a }, -{ "fpadd32", F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, v9a }, -{ "fpadd32s", F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, v9a }, -{ "fpsub16", F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, v9a }, -{ "fpsub16s", F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, v9a }, -{ "fpsub32", F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, v9a }, -{ "fpsub32s", F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, v9a }, - -{ "fpack32", F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, v9a }, -{ "fpack16", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, v9a }, -{ "fpackfix", F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, v9a }, -{ "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, v9a }, -{ "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, v9a }, - -/* Note that the mixing of 32/64 bit regs is intentional. */ -{ "fmul8x16", F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, v9a }, -{ "fmul8x16au", F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, v9a }, -{ "fmul8x16al", F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, v9a }, -{ "fmul8sux16", F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, v9a }, -{ "fmul8ulx16", F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, v9a }, -{ "fmuld8sux16", F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, v9a }, -{ "fmuld8ulx16", F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, v9a }, - -{ "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, v9a }, -{ "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, v9a }, -{ "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, v9a }, - -{ "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, v9a }, -{ "fzeros", F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, v9a }, -{ "fone", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, v9a }, -{ "fones", F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, v9a }, -{ "fsrc1", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, v9a }, -{ "fsrc1s", F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, v9a }, -{ "fsrc2", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, v9a }, -{ "fsrc2s", F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, v9a }, -{ "fnot1", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, v9a }, -{ "fnot1s", F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, v9a }, -{ "fnot2", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, v9a }, -{ "fnot2s", F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, v9a }, -{ "for", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, v9a }, -{ "fors", F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, v9a }, -{ "fnor", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, v9a }, -{ "fnors", F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, v9a }, -{ "fand", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, v9a }, -{ "fands", F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, v9a }, -{ "fnand", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, v9a }, -{ "fnands", F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, v9a }, -{ "fxor", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, v9a }, -{ "fxors", F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, v9a }, -{ "fxnor", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, v9a }, -{ "fxnors", F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, v9a }, -{ "fornot1", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, v9a }, -{ "fornot1s", F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, v9a }, -{ "fornot2", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, v9a }, -{ "fornot2s", F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, v9a }, -{ "fandnot1", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, v9a }, -{ "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, v9a }, -{ "fandnot2", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, v9a }, -{ "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, v9a }, - -{ "fcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, v9a }, -{ "fcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, v9a }, -{ "fcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, v9a }, -{ "fcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, v9a }, -{ "fcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, v9a }, -{ "fcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, v9a }, -{ "fcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, v9a }, -{ "fcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, v9a }, - -{ "edge8", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, v9a }, -{ "edge8l", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, v9a }, -{ "edge16", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, v9a }, -{ "edge16l", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, v9a }, -{ "edge32", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, v9a }, -{ "edge32l", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, v9a }, - -{ "pdist", F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, v9a }, - -{ "array8", F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, v9a }, -{ "array16", F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, v9a }, -{ "array32", F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, v9a }, - -/* More v9 specific insns, these need to come last so they do not clash - with v9a instructions such as "edge8" which looks like impdep1. */ - -#define IMPDEP(name, code) \ -{ name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, v9notv9a }, \ -{ name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, v9notv9a }, \ -{ name, F3(2, code, 0), F3(~2, ~code, ~0), "x,1,2,d", 0, v9notv9a }, \ -{ name, F3(2, code, 0), F3(~2, ~code, ~0), "x,e,f,g", 0, v9notv9a } - -IMPDEP ("impdep1", 0x36), -IMPDEP ("impdep2", 0x37), - -#undef IMPDEP - -}; - -const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0])); - -/* Utilities for argument parsing. */ - -typedef struct -{ - int value; - const char *name; -} arg; - -/* Look up NAME in TABLE. */ - -static int lookup_name PARAMS ((const arg *, const char *)); -static const char *lookup_value PARAMS ((const arg *, int)); - -static int -lookup_name (table, name) - const arg *table; - const char *name; -{ - const arg *p; - - for (p = table; p->name; ++p) - if (strcmp (name, p->name) == 0) - return p->value; - - return -1; -} - -/* Look up VALUE in TABLE. */ - -static const char * -lookup_value (table, value) - const arg *table; - int value; -{ - const arg *p; - - for (p = table; p->name; ++p) - if (value == p->value) - return p->name; - - return (char *) 0; -} - -/* Handle ASI's. */ - -static arg asi_table[] = -{ - /* These are in the v9 architecture manual. */ - /* The shorter versions appear first, they're here because Sun's as has them. - Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the - UltraSPARC architecture manual). */ - { 0x04, "#ASI_N" }, - { 0x0c, "#ASI_N_L" }, - { 0x10, "#ASI_AIUP" }, - { 0x11, "#ASI_AIUS" }, - { 0x18, "#ASI_AIUP_L" }, - { 0x19, "#ASI_AIUS_L" }, - { 0x80, "#ASI_P" }, - { 0x81, "#ASI_S" }, - { 0x82, "#ASI_PNF" }, - { 0x83, "#ASI_SNF" }, - { 0x88, "#ASI_P_L" }, - { 0x89, "#ASI_S_L" }, - { 0x8a, "#ASI_PNF_L" }, - { 0x8b, "#ASI_SNF_L" }, - { 0x04, "#ASI_NUCLEUS" }, - { 0x0c, "#ASI_NUCLEUS_LITTLE" }, - { 0x10, "#ASI_AS_IF_USER_PRIMARY" }, - { 0x11, "#ASI_AS_IF_USER_SECONDARY" }, - { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" }, - { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" }, - { 0x80, "#ASI_PRIMARY" }, - { 0x81, "#ASI_SECONDARY" }, - { 0x82, "#ASI_PRIMARY_NOFAULT" }, - { 0x83, "#ASI_SECONDARY_NOFAULT" }, - { 0x88, "#ASI_PRIMARY_LITTLE" }, - { 0x89, "#ASI_SECONDARY_LITTLE" }, - { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" }, - { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" }, - /* These are UltraSPARC extensions. */ - /* FIXME: There are dozens of them. Not sure we want them all. - Most are for kernel building but some are for vis type stuff. */ - { 0, 0 } -}; - -/* Return the value for ASI NAME, or -1 if not found. */ - -int -sparc_encode_asi (name) - const char *name; -{ - return lookup_name (asi_table, name); -} - -/* Return the name for ASI value VALUE or NULL if not found. */ - -const char * -sparc_decode_asi (value) - int value; -{ - return lookup_value (asi_table, value); -} - -/* Handle membar masks. */ - -static arg membar_table[] = -{ - { 0x40, "#Sync" }, - { 0x20, "#MemIssue" }, - { 0x10, "#Lookaside" }, - { 0x08, "#StoreStore" }, - { 0x04, "#LoadStore" }, - { 0x02, "#StoreLoad" }, - { 0x01, "#LoadLoad" }, - { 0, 0 } -}; - -/* Return the value for membar arg NAME, or -1 if not found. */ - -int -sparc_encode_membar (name) - const char *name; -{ - return lookup_name (membar_table, name); -} - -/* Return the name for membar value VALUE or NULL if not found. */ - -const char * -sparc_decode_membar (value) - int value; -{ - return lookup_value (membar_table, value); -} - -/* Handle prefetch args. */ - -static arg prefetch_table[] = -{ - { 0, "#n_reads" }, - { 1, "#one_read" }, - { 2, "#n_writes" }, - { 3, "#one_write" }, - { 4, "#page" }, - { 0, 0 } -}; - -/* Return the value for prefetch arg NAME, or -1 if not found. */ - -int -sparc_encode_prefetch (name) - const char *name; -{ - return lookup_name (prefetch_table, name); -} - -/* Return the name for prefetch value VALUE or NULL if not found. */ - -const char * -sparc_decode_prefetch (value) - int value; -{ - return lookup_value (prefetch_table, value); -} - -/* Handle sparclet coprocessor registers. */ - -static arg sparclet_cpreg_table[] = -{ - { 0, "%ccsr" }, - { 1, "%ccfr" }, - { 2, "%cccrcr" }, - { 3, "%ccpr" }, - { 4, "%ccsr2" }, - { 5, "%cccrr" }, - { 6, "%ccrstr" }, - { 0, 0 } -}; - -/* Return the value for sparclet cpreg arg NAME, or -1 if not found. */ - -int -sparc_encode_sparclet_cpreg (name) - const char *name; -{ - return lookup_name (sparclet_cpreg_table, name); -} - -/* Return the name for sparclet cpreg value VALUE or NULL if not found. */ - -const char * -sparc_decode_sparclet_cpreg (value) - int value; -{ - return lookup_value (sparclet_cpreg_table, value); -} diff --git a/opcodes/stamp-h.in b/opcodes/stamp-h.in deleted file mode 100644 index 9788f70238c..00000000000 --- a/opcodes/stamp-h.in +++ /dev/null @@ -1 +0,0 @@ -timestamp diff --git a/opcodes/sysdep.h b/opcodes/sysdep.h deleted file mode 100644 index f1556da1f2e..00000000000 --- a/opcodes/sysdep.h +++ /dev/null @@ -1,38 +0,0 @@ -/* Random host-dependent support code. - Copyright (C) 1995 Free Software Foundation, Inc. - Written by Ken Raeburn. - -This file is part of libopcodes, the opcodes library. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -/* Do system-dependent stuff, mainly driven by autoconf-detected info. - - Well, some generic common stuff is done here too, like including - ansidecl.h. That's because the .h files in bfd/hosts files I'm - trying to replace often did that. If it can be dropped from this - file (check in a non-ANSI environment!), it should be. */ - -#include "config.h" - -#include <ansidecl.h> - -#ifdef HAVE_STRING_H -#include <string.h> -#else -#ifdef HAVE_STRINGS_H -#include <strings.h> -#endif -#endif diff --git a/opcodes/tic30-dis.c b/opcodes/tic30-dis.c deleted file mode 100644 index 3a7cafe0131..00000000000 --- a/opcodes/tic30-dis.c +++ /dev/null @@ -1,704 +0,0 @@ -/* Disassembly routines for TMS320C30 architecture - Copyright (C) 1998 Free Software Foundation, Inc. - Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au) - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -#include <errno.h> -#include <math.h> -#include <stdlib.h> -#include <string.h> -#include "dis-asm.h" -#include "opcode/tic30.h" - -#define NORMAL_INSN 1 -#define PARALLEL_INSN 2 - -/* Gets the type of instruction based on the top 2 or 3 bits of the - instruction word. */ -#define GET_TYPE(insn) (insn & 0x80000000 ? insn & 0xC0000000 : insn & 0xE0000000) - -/* Instruction types. */ -#define TWO_OPERAND_1 0x00000000 -#define TWO_OPERAND_2 0x40000000 -#define THREE_OPERAND 0x20000000 -#define PAR_STORE 0xC0000000 -#define MUL_ADDS 0x80000000 -#define BRANCHES 0x60000000 - -/* Specific instruction id bits. */ -#define NORMAL_IDEN 0x1F800000 -#define PAR_STORE_IDEN 0x3E000000 -#define MUL_ADD_IDEN 0x2C000000 -#define BR_IMM_IDEN 0x1F000000 -#define BR_COND_IDEN 0x1C3F0000 - -/* Addressing modes. */ -#define AM_REGISTER 0x00000000 -#define AM_DIRECT 0x00200000 -#define AM_INDIRECT 0x00400000 -#define AM_IMM 0x00600000 - -#define P_FIELD 0x03000000 - -#define REG_AR0 0x08 -#define LDP_INSN 0x08700000 - -/* TMS320C30 program counter for current instruction. */ -static unsigned int _pc; - -struct instruction - { - int type; - template *tm; - partemplate *ptm; - }; - -int get_tic30_instruction PARAMS ((unsigned long, struct instruction *)); -int print_two_operand - PARAMS ((disassemble_info *, unsigned long, struct instruction *)); -int print_three_operand - PARAMS ((disassemble_info *, unsigned long, struct instruction *)); -int print_par_insn - PARAMS ((disassemble_info *, unsigned long, struct instruction *)); -int print_branch - PARAMS ((disassemble_info *, unsigned long, struct instruction *)); -int get_indirect_operand PARAMS ((unsigned short, int, char *)); -int get_register_operand PARAMS ((unsigned char, char *)); -int cnvt_tmsfloat_ieee PARAMS ((unsigned long, int, float *)); - -int -print_insn_tic30 (pc, info) - bfd_vma pc; - disassemble_info *info; -{ - unsigned long insn_word; - struct instruction insn = - {0, NULL, NULL}; - bfd_vma bufaddr = pc - info->buffer_vma; - /* Obtain the current instruction word from the buffer. */ - insn_word = (*(info->buffer + bufaddr) << 24) | (*(info->buffer + bufaddr + 1) << 16) | - (*(info->buffer + bufaddr + 2) << 8) | *(info->buffer + bufaddr + 3); - _pc = pc / 4; - /* Get the instruction refered to by the current instruction word - and print it out based on its type. */ - if (!get_tic30_instruction (insn_word, &insn)) - return -1; - switch (GET_TYPE (insn_word)) - { - case TWO_OPERAND_1: - case TWO_OPERAND_2: - if (!print_two_operand (info, insn_word, &insn)) - return -1; - break; - case THREE_OPERAND: - if (!print_three_operand (info, insn_word, &insn)) - return -1; - break; - case PAR_STORE: - case MUL_ADDS: - if (!print_par_insn (info, insn_word, &insn)) - return -1; - break; - case BRANCHES: - if (!print_branch (info, insn_word, &insn)) - return -1; - break; - } - return 4; -} - -int -get_tic30_instruction (insn_word, insn) - unsigned long insn_word; - struct instruction *insn; -{ - switch (GET_TYPE (insn_word)) - { - case TWO_OPERAND_1: - case TWO_OPERAND_2: - case THREE_OPERAND: - insn->type = NORMAL_INSN; - { - template *current_optab = (template *) tic30_optab; - for (; current_optab < tic30_optab_end; current_optab++) - { - if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) - { - if (current_optab->operands == 0) - { - if (current_optab->base_opcode == insn_word) - { - insn->tm = current_optab; - break; - } - } - else if ((current_optab->base_opcode & NORMAL_IDEN) == (insn_word & NORMAL_IDEN)) - { - insn->tm = current_optab; - break; - } - } - } - } - break; - case PAR_STORE: - insn->type = PARALLEL_INSN; - { - partemplate *current_optab = (partemplate *) tic30_paroptab; - for (; current_optab < tic30_paroptab_end; current_optab++) - { - if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) - { - if ((current_optab->base_opcode & PAR_STORE_IDEN) == (insn_word & PAR_STORE_IDEN)) - { - insn->ptm = current_optab; - break; - } - } - } - } - break; - case MUL_ADDS: - insn->type = PARALLEL_INSN; - { - partemplate *current_optab = (partemplate *) tic30_paroptab; - for (; current_optab < tic30_paroptab_end; current_optab++) - { - if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) - { - if ((current_optab->base_opcode & MUL_ADD_IDEN) == (insn_word & MUL_ADD_IDEN)) - { - insn->ptm = current_optab; - break; - } - } - } - } - break; - case BRANCHES: - insn->type = NORMAL_INSN; - { - template *current_optab = (template *) tic30_optab; - for (; current_optab < tic30_optab_end; current_optab++) - { - if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) - { - if (current_optab->operand_types[0] & Imm24) - { - if ((current_optab->base_opcode & BR_IMM_IDEN) == (insn_word & BR_IMM_IDEN)) - { - insn->tm = current_optab; - break; - } - } - else if (current_optab->operands > 0) - { - if ((current_optab->base_opcode & BR_COND_IDEN) == (insn_word & BR_COND_IDEN)) - { - insn->tm = current_optab; - break; - } - } - else - { - if ((current_optab->base_opcode & (BR_COND_IDEN | 0x00800000)) == (insn_word & (BR_COND_IDEN | 0x00800000))) - { - insn->tm = current_optab; - break; - } - } - } - } - } - break; - default: - return 0; - } - return 1; -} - -int -print_two_operand (info, insn_word, insn) - disassemble_info *info; - unsigned long insn_word; - struct instruction *insn; -{ - char name[12]; - char operand[2][13] = - { - {0}, - {0}}; - float f_number; - - if (insn->tm == NULL) - return 0; - strcpy (name, insn->tm->name); - if (insn->tm->opcode_modifier == AddressMode) - { - int src_op, dest_op; - /* Determine whether instruction is a store or a normal instruction. */ - if ((insn->tm->operand_types[1] & (Direct | Indirect)) == (Direct | Indirect)) - { - src_op = 1; - dest_op = 0; - } - else - { - src_op = 0; - dest_op = 1; - } - /* Get the destination register. */ - if (insn->tm->operands == 2) - get_register_operand ((insn_word & 0x001F0000) >> 16, operand[dest_op]); - /* Get the source operand based on addressing mode. */ - switch (insn_word & AddressMode) - { - case AM_REGISTER: - /* Check for the NOP instruction before getting the operand. */ - if ((insn->tm->operand_types[0] & NotReq) == 0) - get_register_operand ((insn_word & 0x0000001F), operand[src_op]); - break; - case AM_DIRECT: - sprintf (operand[src_op], "@0x%lX", (insn_word & 0x0000FFFF)); - break; - case AM_INDIRECT: - get_indirect_operand ((insn_word & 0x0000FFFF), 2, operand[src_op]); - break; - case AM_IMM: - /* Get the value of the immediate operand based on variable type. */ - switch (insn->tm->imm_arg_type) - { - case Imm_Float: - cnvt_tmsfloat_ieee ((insn_word & 0x0000FFFF), 2, &f_number); - sprintf (operand[src_op], "%2.2f", f_number); - break; - case Imm_SInt: - sprintf (operand[src_op], "%d", (short) (insn_word & 0x0000FFFF)); - break; - case Imm_UInt: - sprintf (operand[src_op], "%lu", (insn_word & 0x0000FFFF)); - break; - default: - return 0; - } - /* Handle special case for LDP instruction. */ - if ((insn_word & 0xFFFFFF00) == LDP_INSN) - { - strcpy (name, "ldp"); - sprintf (operand[0], "0x%06lX", (insn_word & 0x000000FF) << 16); - operand[1][0] = '\0'; - } - } - } - /* Handle case for stack and rotate instructions. */ - else if (insn->tm->operands == 1) - { - if (insn->tm->opcode_modifier == StackOp) - { - get_register_operand ((insn_word & 0x001F0000) >> 16, operand[0]); - } - } - /* Output instruction to stream. */ - info->fprintf_func (info->stream, " %s %s%c%s", name, - operand[0][0] ? operand[0] : "", - operand[1][0] ? ',' : ' ', - operand[1][0] ? operand[1] : ""); - return 1; -} - -int -print_three_operand (info, insn_word, insn) - disassemble_info *info; - unsigned long insn_word; - struct instruction *insn; -{ - char operand[3][13] = - { - {0}, - {0}, - {0}}; - - if (insn->tm == NULL) - return 0; - switch (insn_word & AddressMode) - { - case AM_REGISTER: - get_register_operand ((insn_word & 0x000000FF), operand[0]); - get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]); - break; - case AM_DIRECT: - get_register_operand ((insn_word & 0x000000FF), operand[0]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]); - break; - case AM_INDIRECT: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]); - get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]); - break; - case AM_IMM: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]); - break; - default: - return 0; - } - if (insn->tm->operands == 3) - get_register_operand ((insn_word & 0x001F0000) >> 16, operand[2]); - info->fprintf_func (info->stream, " %s %s,%s%c%s", insn->tm->name, - operand[0], operand[1], - operand[2][0] ? ',' : ' ', - operand[2][0] ? operand[2] : ""); - return 1; -} - -int -print_par_insn (info, insn_word, insn) - disassemble_info *info; - unsigned long insn_word; - struct instruction *insn; -{ - int i; - char *name1, *name2; - char operand[2][3][13] = - { - { - {0}, - {0}, - {0}}, - { - {0}, - {0}, - {0}}}; - - if (insn->ptm == NULL) - return 0; - /* Parse out the names of each of the parallel instructions from the - q_insn1_insn2 format. */ - name1 = (char *) strdup (insn->ptm->name + 2); - for (i = 0; i < strlen (name1); i++) - { - if (name1[i] == '_') - { - name2 = &name1[i + 1]; - name1[i] = '\0'; - break; - } - } - /* Get the operands of the instruction based on the operand order. */ - switch (insn->ptm->oporder) - { - case OO_4op1: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); - get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); - get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]); - break; - case OO_4op2: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]); - get_register_operand ((insn_word >> 19) & 0x07, operand[1][1]); - get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]); - break; - case OO_4op3: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); - get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); - get_register_operand ((insn_word >> 22) & 0x07, operand[0][0]); - break; - case OO_5op1: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); - get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); - get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]); - get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]); - break; - case OO_5op2: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); - get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); - get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]); - get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]); - break; - case OO_PField: - if (insn_word & 0x00800000) - get_register_operand (0x01, operand[0][2]); - else - get_register_operand (0x00, operand[0][2]); - if (insn_word & 0x00400000) - get_register_operand (0x03, operand[1][2]); - else - get_register_operand (0x02, operand[1][2]); - switch (insn_word & P_FIELD) - { - case 0x00000000: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]); - get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]); - get_register_operand ((insn_word >> 19) & 0x07, operand[1][0]); - break; - case 0x01000000: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][0]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]); - get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]); - get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]); - break; - case 0x02000000: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]); - get_register_operand ((insn_word >> 16) & 0x07, operand[0][1]); - get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]); - break; - case 0x03000000: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]); - get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); - get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]); - break; - } - break; - default: - return 0; - } - info->fprintf_func (info->stream, " %s %s,%s%c%s", name1, - operand[0][0], operand[0][1], - operand[0][2][0] ? ',' : ' ', - operand[0][2][0] ? operand[0][2] : ""); - info->fprintf_func (info->stream, "\n\t\t\t|| %s %s,%s%c%s", name2, - operand[1][0], operand[1][1], - operand[1][2][0] ? ',' : ' ', - operand[1][2][0] ? operand[1][2] : ""); - free (name1); - return 1; -} - -int -print_branch (info, insn_word, insn) - disassemble_info *info; - unsigned long insn_word; - struct instruction *insn; -{ - char operand[2][13] = - { - {0}, - {0}}; - unsigned long address; - int print_label = 0; - - if (insn->tm == NULL) - return 0; - /* Get the operands for 24-bit immediate jumps. */ - if (insn->tm->operand_types[0] & Imm24) - { - address = insn_word & 0x00FFFFFF; - sprintf (operand[0], "0x%lX", address); - print_label = 1; - } - /* Get the operand for the trap instruction. */ - else if (insn->tm->operand_types[0] & IVector) - { - address = insn_word & 0x0000001F; - sprintf (operand[0], "0x%lX", address); - } - else - { - address = insn_word & 0x0000FFFF; - /* Get the operands for the DB instructions. */ - if (insn->tm->operands == 2) - { - get_register_operand (((insn_word & 0x01C00000) >> 22) + REG_AR0, operand[0]); - if (insn_word & PCRel) - { - sprintf (operand[1], "%d", (short) address); - print_label = 1; - } - else - get_register_operand (insn_word & 0x0000001F, operand[1]); - } - /* Get the operands for the standard branches. */ - else if (insn->tm->operands == 1) - { - if (insn_word & PCRel) - { - address = (short) address; - sprintf (operand[0], "%ld", address); - print_label = 1; - } - else - get_register_operand (insn_word & 0x0000001F, operand[0]); - } - } - info->fprintf_func (info->stream, " %s %s%c%s", insn->tm->name, - operand[0][0] ? operand[0] : "", - operand[1][0] ? ',' : ' ', - operand[1][0] ? operand[1] : ""); - /* Print destination of branch in relation to current symbol. */ - if (print_label && info->symbol) - { - if ((insn->tm->opcode_modifier == PCRel) && (insn_word & PCRel)) - { - address = (_pc + 1 + (short) address) - ((info->symbol->section->vma + info->symbol->value) / 4); - /* Check for delayed instruction, if so adjust destination. */ - if (insn_word & 0x00200000) - address += 2; - } - else - { - address -= ((info->symbol->section->vma + info->symbol->value) / 4); - } - if (address == 0) - info->fprintf_func (info->stream, " <%s>", info->symbol->name); - else - info->fprintf_func (info->stream, " <%s %c %d>", info->symbol->name, - ((short) address < 0) ? '-' : '+', - abs (address)); - } - return 1; -} - -int -get_indirect_operand (fragment, size, buffer) - unsigned short fragment; - int size; - char *buffer; -{ - unsigned char mod; - unsigned arnum; - unsigned char disp; - - if (buffer == NULL) - return 0; - /* Determine which bits identify the sections of the indirect operand based on the - size in bytes. */ - switch (size) - { - case 1: - mod = (fragment & 0x00F8) >> 3; - arnum = (fragment & 0x0007); - disp = 0; - break; - case 2: - mod = (fragment & 0xF800) >> 11; - arnum = (fragment & 0x0700) >> 8; - disp = (fragment & 0x00FF); - break; - default: - return 0; - } - { - const ind_addr_type *current_ind = tic30_indaddr_tab; - for (; current_ind < tic30_indaddrtab_end; current_ind++) - { - if (current_ind->modfield == mod) - { - if (current_ind->displacement == IMPLIED_DISP && size == 2) - { - continue; - } - else - { - int i, bufcnt; - for (i = 0, bufcnt = 0; i < strlen (current_ind->syntax); i++, bufcnt++) - { - buffer[bufcnt] = current_ind->syntax[i]; - if (buffer[bufcnt - 1] == 'a' && buffer[bufcnt] == 'r') - buffer[++bufcnt] = arnum + '0'; - if (buffer[bufcnt] == '(' && current_ind->displacement == DISP_REQUIRED) - { - sprintf (&buffer[bufcnt + 1], "%u", disp); - bufcnt += strlen (&buffer[bufcnt + 1]); - } - } - buffer[bufcnt + 1] = '\0'; - break; - } - } - } - } - return 1; -} - -int -get_register_operand (fragment, buffer) - unsigned char fragment; - char *buffer; -{ - const reg *current_reg = tic30_regtab; - - if (buffer == NULL) - return 0; - for (; current_reg < tic30_regtab_end; current_reg++) - { - if ((fragment & 0x1F) == current_reg->opcode) - { - strcpy (buffer, current_reg->name); - return 1; - } - } - return 0; -} - -int -cnvt_tmsfloat_ieee (tmsfloat, size, ieeefloat) - unsigned long tmsfloat; - int size; - float *ieeefloat; -{ - unsigned long exp, sign, mant; - - if (size == 2) - { - if ((tmsfloat & 0x0000F000) == 0x00008000) - tmsfloat = 0x80000000; - else - { - tmsfloat <<= 16; - tmsfloat = (long) tmsfloat >> 4; - } - } - exp = tmsfloat & 0xFF000000; - if (exp == 0x80000000) - { - *ieeefloat = 0.0; - return 1; - } - exp += 0x7F000000; - sign = (tmsfloat & 0x00800000) << 8; - mant = tmsfloat & 0x007FFFFF; - if (exp == 0xFF000000) - { - if (mant == 0) - *ieeefloat = ERANGE; - if (sign == 0) - *ieeefloat = 1.0 / 0.0; - else - *ieeefloat = -1.0 / 0.0; - return 1; - } - exp >>= 1; - if (sign) - { - mant = (~mant) & 0x007FFFFF; - mant += 1; - exp += mant & 0x00800000; - exp &= 0x7F800000; - mant &= 0x007FFFFF; - } - if (tmsfloat == 0x80000000) - sign = mant = exp = 0; - tmsfloat = sign | exp | mant; - *ieeefloat = *((float *) &tmsfloat); - return 1; -} diff --git a/opcodes/tic80-dis.c b/opcodes/tic80-dis.c deleted file mode 100644 index 24fb9309eb2..00000000000 --- a/opcodes/tic80-dis.c +++ /dev/null @@ -1,397 +0,0 @@ -/* Print TI TMS320C80 (MVP) instructions - Copyright 1996, 1997 Free Software Foundation, Inc. - -This file is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include <stdio.h> - -#include "ansidecl.h" -#include "opcode/tic80.h" -#include "dis-asm.h" - -static int length; - -static void print_operand_bitnum PARAMS ((struct disassemble_info *, long)); -static void print_operand_condition_code PARAMS ((struct disassemble_info *, long)); -static void print_operand_control_register PARAMS ((struct disassemble_info *, long)); -static void print_operand_float PARAMS ((struct disassemble_info *, long)); -static void print_operand_integer PARAMS ((struct disassemble_info *, long)); -static void print_operand PARAMS ((struct disassemble_info *, long, unsigned long, - const struct tic80_operand *, bfd_vma)); -static int print_one_instruction PARAMS ((struct disassemble_info *, bfd_vma, - unsigned long, const struct tic80_opcode *)); -static int print_instruction PARAMS ((struct disassemble_info *, bfd_vma, unsigned long, - const struct tic80_opcode *)); -static int fill_instruction PARAMS ((struct disassemble_info *, bfd_vma, - unsigned long *)); - - -/* Print an integer operand. Try to be somewhat smart about the - format by assuming that small positive or negative integers are - probably loop increment values, structure offsets, or similar - values that are more meaningful printed as signed decimal values. - Larger numbers are probably better printed as hex values. */ - -static void -print_operand_integer (info, value) - struct disassemble_info *info; - long value; -{ - if ((value > 9999 || value < -9999)) - { - (*info -> fprintf_func) (info -> stream, "%#lx", value); - } - else - { - (*info -> fprintf_func) (info -> stream, "%ld", value); - } -} - - -/* FIXME: depends upon sizeof (long) == sizeof (float) and - also upon host floating point format matching target - floating point format. */ - -static void -print_operand_float (info, value) - struct disassemble_info *info; - long value; -{ - union { float f; long l; } fval; - - fval.l = value; - (*info -> fprintf_func) (info -> stream, "%g", fval.f); -} - - -static void -print_operand_control_register (info, value) - struct disassemble_info *info; - long value; -{ - const char *tmp; - - tmp = tic80_value_to_symbol (value, TIC80_OPERAND_CR); - if (tmp != NULL) - { - (*info -> fprintf_func) (info -> stream, "%s", tmp); - } - else - { - (*info -> fprintf_func) (info -> stream, "%#lx", value); - } -} - - -static void -print_operand_condition_code (info, value) - struct disassemble_info *info; - long value; -{ - const char *tmp; - - tmp = tic80_value_to_symbol (value, TIC80_OPERAND_CC); - if (tmp != NULL) - { - (*info -> fprintf_func) (info -> stream, "%s", tmp); - } - else - { - (*info -> fprintf_func) (info -> stream, "%ld", value); - } -} - - -static void -print_operand_bitnum (info, value) - struct disassemble_info *info; - long value; -{ - int bitnum; - const char *tmp; - - bitnum = ~value & 0x1F; - tmp = tic80_value_to_symbol (bitnum, TIC80_OPERAND_BITNUM); - if (tmp != NULL) - { - (*info -> fprintf_func) (info -> stream, "%s", tmp); - } - else - { - (*info -> fprintf_func) (info -> stream, "%ld", bitnum); - } -} - - -/* Print the operand as directed by the flags. */ - -#define M_SI(insn,op) ((((op) -> flags & TIC80_OPERAND_M_SI) != 0) && ((insn) & (1 << 17))) -#define M_LI(insn,op) ((((op) -> flags & TIC80_OPERAND_M_LI) != 0) && ((insn) & (1 << 15))) -#define R_SCALED(insn,op) ((((op) -> flags & TIC80_OPERAND_SCALED) != 0) && ((insn) & (1 << 11))) - -static void -print_operand (info, value, insn, operand, memaddr) - struct disassemble_info *info; - long value; - unsigned long insn; - const struct tic80_operand *operand; - bfd_vma memaddr; -{ - if ((operand -> flags & TIC80_OPERAND_GPR) != 0) - { - (*info -> fprintf_func) (info -> stream, "r%ld", value); - if (M_SI (insn, operand) || M_LI (insn, operand)) - { - (*info -> fprintf_func) (info -> stream, ":m"); - } - } - else if ((operand -> flags & TIC80_OPERAND_FPA) != 0) - { - (*info -> fprintf_func) (info -> stream, "a%ld", value); - } - else if ((operand -> flags & TIC80_OPERAND_PCREL) != 0) - { - (*info -> print_address_func) (memaddr + 4 * value, info); - } - else if ((operand -> flags & TIC80_OPERAND_BASEREL) != 0) - { - (*info -> print_address_func) (value, info); - } - else if ((operand -> flags & TIC80_OPERAND_BITNUM) != 0) - { - print_operand_bitnum (info, value); - } - else if ((operand -> flags & TIC80_OPERAND_CC) != 0) - { - print_operand_condition_code (info, value); - } - else if ((operand -> flags & TIC80_OPERAND_CR) != 0) - { - print_operand_control_register (info, value); - } - else if ((operand -> flags & TIC80_OPERAND_FLOAT) != 0) - { - print_operand_float (info, value); - } - else if ((operand -> flags & TIC80_OPERAND_BITFIELD)) - { - (*info -> fprintf_func) (info -> stream, "%#lx", value); - } - else - { - print_operand_integer (info, value); - } - - /* If this is a scaled operand, then print the modifier */ - - if (R_SCALED (insn, operand)) - { - (*info -> fprintf_func) (info -> stream, ":s"); - } -} - - -/* We have chosen an opcode table entry */ - -static int -print_one_instruction (info, memaddr, insn, opcode) - struct disassemble_info *info; - bfd_vma memaddr; - unsigned long insn; - const struct tic80_opcode *opcode; -{ - const struct tic80_operand *operand; - long value; - int status; - const unsigned char *opindex; - bfd_byte buffer[4]; - int close_paren; - - (*info -> fprintf_func) (info -> stream, "%-10s", opcode -> name); - - for (opindex = opcode -> operands; *opindex != 0; opindex++) - { - operand = tic80_operands + *opindex; - - /* Extract the value from the instruction. */ - if (operand -> extract) - { - value = (*operand -> extract) (insn, (int *) NULL); - } - else if (operand -> bits == 32) - { - status = fill_instruction (info, memaddr, (unsigned long *) &value); - if (status == -1) - { - return (status); - } - } - else - { - value = (insn >> operand -> shift) & ((1 << operand -> bits) - 1); - if ((operand -> flags & TIC80_OPERAND_SIGNED) != 0 - && (value & (1 << (operand -> bits - 1))) != 0) - { - value -= 1 << operand -> bits; - } - } - - /* If this operand is enclosed in parenthesis, then print - the open paren, otherwise just print the regular comma - separator, except for the first operand. */ - - if ((operand -> flags & TIC80_OPERAND_PARENS) == 0) - { - close_paren = 0; - if (opindex != opcode -> operands) - { - (*info -> fprintf_func) (info -> stream, ","); - } - } - else - { - close_paren = 1; - (*info -> fprintf_func) (info -> stream, "("); - } - - print_operand (info, value, insn, operand, memaddr); - - /* If we printed an open paren before printing this operand, close - it now. The flag gets reset on each loop. */ - - if (close_paren) - { - (*info -> fprintf_func) (info -> stream, ")"); - } - } - return (length); -} - - - -/* There are no specific bits that tell us for certain whether a vector - instruction opcode contains one or two instructions. However since - a destination register of r0 is illegal, we can check for nonzero - values in both destination register fields. Only opcodes that have - two valid instructions will have non-zero in both */ - -#define TWO_INSN(insn) ((((insn) & (0x1F << 27)) != 0) && (((insn) & (0x1F << 22)) != 0)) - -static int -print_instruction (info, memaddr, insn, vec_opcode) - struct disassemble_info *info; - bfd_vma memaddr; - unsigned long insn; - const struct tic80_opcode *vec_opcode; -{ - const struct tic80_opcode *opcode; - const struct tic80_opcode *opcode_end; - - /* Find the first opcode match in the opcodes table. For vector - opcodes (vec_opcode != NULL) find the first match that is not the - previously found match. FIXME: there should be faster ways to - search (hash table or binary search), but don't worry too much - about it until other TIc80 support is finished. */ - - opcode_end = tic80_opcodes + tic80_num_opcodes; - for (opcode = tic80_opcodes; opcode < opcode_end; opcode++) - { - if ((insn & opcode -> mask) == opcode -> opcode && - opcode != vec_opcode) - { - break; - } - } - - if (opcode == opcode_end) - { - /* No match found, just print the bits as a .word directive */ - (*info -> fprintf_func) (info -> stream, ".word %#08lx", insn); - } - else - { - /* Match found, decode the instruction. */ - length = print_one_instruction (info, memaddr, insn, opcode); - if (opcode -> flags & TIC80_VECTOR && vec_opcode == NULL && TWO_INSN (insn)) - { - /* There is another instruction to print from the same opcode. - Print the separator and then find and print the other - instruction. */ - (*info -> fprintf_func) (info -> stream, " || "); - length = print_instruction (info, memaddr, insn, opcode); - } - } - return (length); -} - -/* Get the next 32 bit word from the instruction stream and convert it - into internal format in the unsigned long INSN, for which we are - passed the address. Return 0 on success, -1 on error. */ - -static int -fill_instruction (info, memaddr, insnp) - struct disassemble_info *info; - bfd_vma memaddr; - unsigned long *insnp; -{ - bfd_byte buffer[4]; - int status; - - /* Get the bits for the next 32 bit word and put in buffer */ - - status = (*info -> read_memory_func) (memaddr + length, buffer, 4, info); - if (status != 0) - { - (*info -> memory_error_func) (status, memaddr, info); - return (-1); - } - - /* Read was successful, so increment count of bytes read and convert - the bits into internal format. */ - - length += 4; - if (info -> endian == BFD_ENDIAN_LITTLE) - { - *insnp = bfd_getl32 (buffer); - } - else if (info -> endian == BFD_ENDIAN_BIG) - { - *insnp = bfd_getb32 (buffer); - } - else - { - /* FIXME: Should probably just default to one or the other */ - abort (); - } - return (0); -} - - -int -print_insn_tic80 (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - unsigned long insn; - int status; - - length = 0; - status = fill_instruction (info, memaddr, &insn); - if (status != -1) - { - status = print_instruction (info, memaddr, insn, NULL); - } - return (status); -} diff --git a/opcodes/tic80-opc.c b/opcodes/tic80-opc.c deleted file mode 100644 index 061b63761c4..00000000000 --- a/opcodes/tic80-opc.c +++ /dev/null @@ -1,1215 +0,0 @@ -/* Opcode table for TI TMS320C80 (MVP). - Copyright 1996 Free Software Foundation, Inc. - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include <stdio.h> -#include "ansidecl.h" -#include "opcode/tic80.h" - -/* This file holds various tables for the TMS320C80 (MVP). - - The opcode table is strictly constant data, so the compiler should - be able to put it in the .text section. - - This file also holds the operand table. All knowledge about - inserting operands into instructions and vice-versa is kept in this - file. - - The predefined register table maps from register names to register - values. */ - - -/* Table of predefined symbol names, such as general purpose registers, - floating point registers, condition codes, control registers, and bit - numbers. - - The table is sorted case independently by name so that it is suitable for - searching via a binary search using a case independent comparison - function. - - Note that the type of the symbol is stored in the upper bits of the value - field, which allows the value and type to be passed around as a unit in a - single int. The types have to be masked off before using the numeric - value as a number. -*/ - -const struct predefined_symbol tic80_predefined_symbols[] = -{ - { "a0", TIC80_OPERAND_FPA | 0 }, - { "a1", TIC80_OPERAND_FPA | 1 }, - { "alw.b", TIC80_OPERAND_CC | 7 }, - { "alw.h", TIC80_OPERAND_CC | 15 }, - { "alw.w", TIC80_OPERAND_CC | 23 }, - { "ANASTAT", TIC80_OPERAND_CR | 0x34 }, - { "BRK1", TIC80_OPERAND_CR | 0x39 }, - { "BRK2", TIC80_OPERAND_CR | 0x3A }, - { "CONFIG", TIC80_OPERAND_CR | 2 }, - { "DLRU", TIC80_OPERAND_CR | 0x500 }, - { "DTAG0", TIC80_OPERAND_CR | 0x400 }, - { "DTAG1", TIC80_OPERAND_CR | 0x401 }, - { "DTAG10", TIC80_OPERAND_CR | 0x40A }, - { "DTAG11", TIC80_OPERAND_CR | 0x40B }, - { "DTAG12", TIC80_OPERAND_CR | 0x40C }, - { "DTAG13", TIC80_OPERAND_CR | 0x40D }, - { "DTAG14", TIC80_OPERAND_CR | 0x40E }, - { "DTAG15", TIC80_OPERAND_CR | 0x40F }, - { "DTAG2", TIC80_OPERAND_CR | 0x402 }, - { "DTAG3", TIC80_OPERAND_CR | 0x403 }, - { "DTAG4", TIC80_OPERAND_CR | 0x404 }, - { "DTAG5", TIC80_OPERAND_CR | 0x405 }, - { "DTAG6", TIC80_OPERAND_CR | 0x406 }, - { "DTAG7", TIC80_OPERAND_CR | 0x407 }, - { "DTAG8", TIC80_OPERAND_CR | 0x408 }, - { "DTAG9", TIC80_OPERAND_CR | 0x409 }, - { "ECOMCNTL", TIC80_OPERAND_CR | 0x33 }, - { "EIP", TIC80_OPERAND_CR | 1 }, - { "EPC", TIC80_OPERAND_CR | 0 }, - { "eq.b", TIC80_OPERAND_BITNUM | 0 }, - { "eq.f", TIC80_OPERAND_BITNUM | 20 }, - { "eq.h", TIC80_OPERAND_BITNUM | 10 }, - { "eq.w", TIC80_OPERAND_BITNUM | 20 }, - { "eq0.b", TIC80_OPERAND_CC | 2 }, - { "eq0.h", TIC80_OPERAND_CC | 10 }, - { "eq0.w", TIC80_OPERAND_CC | 18 }, - { "FLTADR", TIC80_OPERAND_CR | 0x11 }, - { "FLTDTH", TIC80_OPERAND_CR | 0x14 }, - { "FLTDTL", TIC80_OPERAND_CR | 0x13 }, - { "FLTOP", TIC80_OPERAND_CR | 0x10 }, - { "FLTTAG", TIC80_OPERAND_CR | 0x12 }, - { "FPST", TIC80_OPERAND_CR | 8 }, - { "ge.b", TIC80_OPERAND_BITNUM | 5 }, - { "ge.f", TIC80_OPERAND_BITNUM | 25 }, - { "ge.h", TIC80_OPERAND_BITNUM | 15 }, - { "ge.w", TIC80_OPERAND_BITNUM | 25 }, - { "ge0.b", TIC80_OPERAND_CC | 3 }, - { "ge0.h", TIC80_OPERAND_CC | 11 }, - { "ge0.w", TIC80_OPERAND_CC | 19 }, - { "gt.b", TIC80_OPERAND_BITNUM | 2 }, - { "gt.f", TIC80_OPERAND_BITNUM | 22 }, - { "gt.h", TIC80_OPERAND_BITNUM | 12 }, - { "gt.w", TIC80_OPERAND_BITNUM | 22 }, - { "gt0.b", TIC80_OPERAND_CC | 1 }, - { "gt0.h", TIC80_OPERAND_CC | 9 }, - { "gt0.w", TIC80_OPERAND_CC | 17 }, - { "hi.b", TIC80_OPERAND_BITNUM | 6 }, - { "hi.h", TIC80_OPERAND_BITNUM | 16 }, - { "hi.w", TIC80_OPERAND_BITNUM | 26 }, - { "hs.b", TIC80_OPERAND_BITNUM | 9 }, - { "hs.h", TIC80_OPERAND_BITNUM | 19 }, - { "hs.w", TIC80_OPERAND_BITNUM | 29 }, - { "ib.f", TIC80_OPERAND_BITNUM | 28 }, - { "IE", TIC80_OPERAND_CR | 6 }, - { "ILRU", TIC80_OPERAND_CR | 0x300 }, - { "in.f", TIC80_OPERAND_BITNUM | 27 }, - { "IN0P", TIC80_OPERAND_CR | 0x4000 }, - { "IN1P", TIC80_OPERAND_CR | 0x4001 }, - { "INTPEN", TIC80_OPERAND_CR | 4 }, - { "ITAG0", TIC80_OPERAND_CR | 0x200 }, - { "ITAG1", TIC80_OPERAND_CR | 0x201 }, - { "ITAG10", TIC80_OPERAND_CR | 0x20A }, - { "ITAG11", TIC80_OPERAND_CR | 0x20B }, - { "ITAG12", TIC80_OPERAND_CR | 0x20C }, - { "ITAG13", TIC80_OPERAND_CR | 0x20D }, - { "ITAG14", TIC80_OPERAND_CR | 0x20E }, - { "ITAG15", TIC80_OPERAND_CR | 0x20F }, - { "ITAG2", TIC80_OPERAND_CR | 0x202 }, - { "ITAG3", TIC80_OPERAND_CR | 0x203 }, - { "ITAG4", TIC80_OPERAND_CR | 0x204 }, - { "ITAG5", TIC80_OPERAND_CR | 0x205 }, - { "ITAG6", TIC80_OPERAND_CR | 0x206 }, - { "ITAG7", TIC80_OPERAND_CR | 0x207 }, - { "ITAG8", TIC80_OPERAND_CR | 0x208 }, - { "ITAG9", TIC80_OPERAND_CR | 0x209 }, - { "le.b", TIC80_OPERAND_BITNUM | 3 }, - { "le.f", TIC80_OPERAND_BITNUM | 23 }, - { "le.h", TIC80_OPERAND_BITNUM | 13 }, - { "le.w", TIC80_OPERAND_BITNUM | 23 }, - { "le0.b", TIC80_OPERAND_CC | 6 }, - { "le0.h", TIC80_OPERAND_CC | 14 }, - { "le0.w", TIC80_OPERAND_CC | 22 }, - { "lo.b", TIC80_OPERAND_BITNUM | 8 }, - { "lo.h", TIC80_OPERAND_BITNUM | 18 }, - { "lo.w", TIC80_OPERAND_BITNUM | 28 }, - { "ls.b", TIC80_OPERAND_BITNUM | 7 }, - { "ls.h", TIC80_OPERAND_BITNUM | 17 }, - { "ls.w", TIC80_OPERAND_BITNUM | 27 }, - { "lt.b", TIC80_OPERAND_BITNUM | 4 }, - { "lt.f", TIC80_OPERAND_BITNUM | 24 }, - { "lt.h", TIC80_OPERAND_BITNUM | 14 }, - { "lt.w", TIC80_OPERAND_BITNUM | 24 }, - { "lt0.b", TIC80_OPERAND_CC | 4 }, - { "lt0.h", TIC80_OPERAND_CC | 12 }, - { "lt0.w", TIC80_OPERAND_CC | 20 }, - { "MIP", TIC80_OPERAND_CR | 0x31 }, - { "MPC", TIC80_OPERAND_CR | 0x30 }, - { "ne.b", TIC80_OPERAND_BITNUM | 1 }, - { "ne.f", TIC80_OPERAND_BITNUM | 21 }, - { "ne.h", TIC80_OPERAND_BITNUM | 11 }, - { "ne.w", TIC80_OPERAND_BITNUM | 21 }, - { "ne0.b", TIC80_OPERAND_CC | 5 }, - { "ne0.h", TIC80_OPERAND_CC | 13 }, - { "ne0.w", TIC80_OPERAND_CC | 21 }, - { "nev.b", TIC80_OPERAND_CC | 0 }, - { "nev.h", TIC80_OPERAND_CC | 8 }, - { "nev.w", TIC80_OPERAND_CC | 16 }, - { "ob.f", TIC80_OPERAND_BITNUM | 29 }, - { "or.f", TIC80_OPERAND_BITNUM | 31 }, - { "ou.f", TIC80_OPERAND_BITNUM | 26 }, - { "OUTP", TIC80_OPERAND_CR | 0x4002 }, - { "PKTREQ", TIC80_OPERAND_CR | 0xD }, - { "PPERROR", TIC80_OPERAND_CR | 0xA }, - { "r0", TIC80_OPERAND_GPR | 0 }, - { "r1", TIC80_OPERAND_GPR | 1 }, - { "r10", TIC80_OPERAND_GPR | 10 }, - { "r11", TIC80_OPERAND_GPR | 11 }, - { "r12", TIC80_OPERAND_GPR | 12 }, - { "r13", TIC80_OPERAND_GPR | 13 }, - { "r14", TIC80_OPERAND_GPR | 14 }, - { "r15", TIC80_OPERAND_GPR | 15 }, - { "r16", TIC80_OPERAND_GPR | 16 }, - { "r17", TIC80_OPERAND_GPR | 17 }, - { "r18", TIC80_OPERAND_GPR | 18 }, - { "r19", TIC80_OPERAND_GPR | 19 }, - { "r2", TIC80_OPERAND_GPR | 2 }, - { "r20", TIC80_OPERAND_GPR | 20 }, - { "r21", TIC80_OPERAND_GPR | 21 }, - { "r22", TIC80_OPERAND_GPR | 22 }, - { "r23", TIC80_OPERAND_GPR | 23 }, - { "r24", TIC80_OPERAND_GPR | 24 }, - { "r25", TIC80_OPERAND_GPR | 25 }, - { "r26", TIC80_OPERAND_GPR | 26 }, - { "r27", TIC80_OPERAND_GPR | 27 }, - { "r28", TIC80_OPERAND_GPR | 28 }, - { "r29", TIC80_OPERAND_GPR | 29 }, - { "r3", TIC80_OPERAND_GPR | 3 }, - { "r30", TIC80_OPERAND_GPR | 30 }, - { "r31", TIC80_OPERAND_GPR | 31 }, - { "r4", TIC80_OPERAND_GPR | 4 }, - { "r5", TIC80_OPERAND_GPR | 5 }, - { "r6", TIC80_OPERAND_GPR | 6 }, - { "r7", TIC80_OPERAND_GPR | 7 }, - { "r8", TIC80_OPERAND_GPR | 8 }, - { "r9", TIC80_OPERAND_GPR | 9 }, - { "SYSSTK", TIC80_OPERAND_CR | 0x20 }, - { "SYSTMP", TIC80_OPERAND_CR | 0x21 }, - { "TCOUNT", TIC80_OPERAND_CR | 0xE }, - { "TSCALE", TIC80_OPERAND_CR | 0xF }, - { "uo.f", TIC80_OPERAND_BITNUM | 30 }, -}; - -const int tic80_num_predefined_symbols = sizeof (tic80_predefined_symbols) / sizeof (struct predefined_symbol); - -/* This function takes a predefined symbol name in NAME, symbol class - in CLASS, and translates it to a numeric value, which it returns. - - If CLASS is zero, any symbol that matches NAME is translated. If - CLASS is non-zero, then only a symbol that has class CLASS is - matched. - - If no translation is possible, it returns -1, a value not used by - any predefined symbol. Note that the predefined symbol array is - presorted case independently by name. - - This function is implemented with the assumption that there are no - duplicate names in the predefined symbol array, which happens to be - true at the moment. - - */ - -int -tic80_symbol_to_value (name, class) - char *name; - int class; -{ - const struct predefined_symbol *pdsp; - int low = 0; - int middle; - int high = tic80_num_predefined_symbols - 1; - int cmp; - int rtnval = -1; - - while (low <= high) - { - middle = (low + high) / 2; - cmp = strcasecmp (name, tic80_predefined_symbols[middle].name); - if (cmp < 0) - { - high = middle - 1; - } - else if (cmp > 0) - { - low = middle + 1; - } - else - { - pdsp = &tic80_predefined_symbols[middle]; - if ((class == 0) || (class & PDS_VALUE (pdsp))) - { - rtnval = PDS_VALUE (pdsp); - } - /* For now we assume that there are no duplicate names */ - break; - } - } - return (rtnval); -} - -/* This function takes a value VAL and finds a matching predefined - symbol that is in the operand class specified by CLASS. If CLASS - is zero, the first matching symbol is returned. */ - -const char * -tic80_value_to_symbol (val, class) - int val; - int class; -{ - const struct predefined_symbol *pdsp; - int ival; - char *name; - - name = NULL; - for (pdsp = tic80_predefined_symbols; - pdsp < tic80_predefined_symbols + tic80_num_predefined_symbols; - pdsp++) - { - ival = PDS_VALUE (pdsp) & ~TIC80_OPERAND_MASK; - if (ival == val) - { - if ((class == 0) || (class & PDS_VALUE (pdsp))) - { - /* Found the desired match */ - name = PDS_NAME (pdsp); - break; - } - } - } - return (name); -} - -/* This function returns a pointer to the next symbol in the predefined - symbol table after PDSP, or NULL if PDSP points to the last symbol. If - PDSP is NULL, it returns the first symbol in the table. Thus it can be - used to walk through the table by first calling it with NULL and then - calling it with each value it returned on the previous call, until it - returns NULL. */ - -const struct predefined_symbol * -tic80_next_predefined_symbol (pdsp) - const struct predefined_symbol *pdsp; -{ - if (pdsp == NULL) - { - pdsp = tic80_predefined_symbols; - } - else if (pdsp >= tic80_predefined_symbols && - pdsp < tic80_predefined_symbols + tic80_num_predefined_symbols - 1) - { - pdsp++; - } - else - { - pdsp = NULL; - } - return (pdsp); -} - - - -/* The operands table. The fields are: - - bits, shift, insertion function, extraction function, flags - */ - -const struct tic80_operand tic80_operands[] = -{ - - /* The zero index is used to indicate the end of the list of operands. */ - -#define UNUSED (0) - { 0, 0, 0, 0, 0 }, - - /* Short signed immediate value in bits 14-0. */ - -#define SSI (UNUSED + 1) - { 15, 0, NULL, NULL, TIC80_OPERAND_SIGNED }, - - /* Short unsigned immediate value in bits 14-0 */ - -#define SUI (SSI + 1) - { 15, 0, NULL, NULL, 0 }, - - /* Short unsigned bitfield in bits 14-0. We distinguish this - from a regular unsigned immediate value only for the convenience - of the disassembler and the user. */ - -#define SUBF (SUI + 1) - { 15, 0, NULL, NULL, TIC80_OPERAND_BITFIELD }, - - /* Long signed immediate in following 32 bit word */ - -#define LSI (SUBF + 1) - { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED }, - - /* Long unsigned immediate in following 32 bit word */ - -#define LUI (LSI + 1) - { 32, 0, NULL, NULL, 0 }, - - /* Long unsigned bitfield in following 32 bit word. We distinguish - this from a regular unsigned immediate value only for the - convenience of the disassembler and the user. */ - -#define LUBF (LUI + 1) - { 32, 0, NULL, NULL, TIC80_OPERAND_BITFIELD }, - - /* Single precision floating point immediate in following 32 bit - word. */ - -#define SPFI (LUBF + 1) - { 32, 0, NULL, NULL, TIC80_OPERAND_FLOAT }, - - /* Register in bits 4-0 */ - -#define REG_0 (SPFI + 1) - { 5, 0, NULL, NULL, TIC80_OPERAND_GPR }, - - /* Even register in bits 4-0 */ - -#define REG_0_E (REG_0 + 1) - { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN }, - - /* Register in bits 26-22 */ - -#define REG_22 (REG_0_E + 1) - { 5, 22, NULL, NULL, TIC80_OPERAND_GPR }, - - /* Even register in bits 26-22 */ - -#define REG_22_E (REG_22 + 1) - { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN }, - - /* Register in bits 31-27 */ - -#define REG_DEST (REG_22_E + 1) - { 5, 27, NULL, NULL, TIC80_OPERAND_GPR }, - - /* Even register in bits 31-27 */ - -#define REG_DEST_E (REG_DEST + 1) - { 5, 27, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN }, - - /* Floating point accumulator register (a0-a3) specified by bit 16 (MSB) - and bit 11 (LSB) */ - /* FIXME! Needs to use functions to insert and extract the register - number in bits 16 and 11. */ - -#define REG_FPA (REG_DEST_E + 1) - { 0, 0, NULL, NULL, TIC80_OPERAND_FPA }, - - /* Short signed PC word offset in bits 14-0 */ - -#define OFF_SS_PC (REG_FPA + 1) - { 15, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED }, - - /* Long signed PC word offset in following 32 bit word */ - -#define OFF_SL_PC (OFF_SS_PC + 1) - { 32, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED }, - - /* Short signed base relative byte offset in bits 14-0 */ - -#define OFF_SS_BR (OFF_SL_PC + 1) - { 15, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED }, - - /* Long signed base relative byte offset in following 32 bit word */ - -#define OFF_SL_BR (OFF_SS_BR + 1) - { 32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED }, - - /* Long signed base relative byte offset in following 32 bit word - with optional ":s" modifier flag in bit 11 */ - -#define OFF_SL_BR_SCALED (OFF_SL_BR + 1) - { 32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED | TIC80_OPERAND_SCALED }, - - /* BITNUM in bits 31-27 */ - -#define BITNUM (OFF_SL_BR_SCALED + 1) - { 5, 27, NULL, NULL, TIC80_OPERAND_BITNUM }, - - /* Condition code in bits 31-27 */ - -#define CC (BITNUM + 1) - { 5, 27, NULL, NULL, TIC80_OPERAND_CC }, - - /* Control register number in bits 14-0 */ - -#define CR_SI (CC + 1) - { 15, 0, NULL, NULL, TIC80_OPERAND_CR }, - - /* Control register number in next 32 bit word */ - -#define CR_LI (CR_SI + 1) - { 32, 0, NULL, NULL, TIC80_OPERAND_CR }, - - /* A base register in bits 26-22, enclosed in parens */ - -#define REG_BASE (CR_LI + 1) - { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS }, - - /* A base register in bits 26-22, enclosed in parens, with optional ":m" - flag in bit 17 (short immediate instructions only) */ - -#define REG_BASE_M_SI (REG_BASE + 1) - { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_SI }, - - /* A base register in bits 26-22, enclosed in parens, with optional ":m" - flag in bit 15 (long immediate and register instructions only) */ - -#define REG_BASE_M_LI (REG_BASE_M_SI + 1) - { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_LI }, - - /* Scaled register in bits 4-0, with optional ":s" modifier flag in bit 11 */ - -#define REG_SCALED (REG_BASE_M_LI + 1) - { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_SCALED }, - - /* Unsigned immediate in bits 4-0, used only for shift instructions */ - -#define ROTATE (REG_SCALED + 1) - { 5, 0, NULL, NULL, 0 }, - - /* Unsigned immediate in bits 9-5, used only for shift instructions */ -#define ENDMASK (ROTATE + 1) - { 5, 5, NULL, NULL, TIC80_OPERAND_ENDMASK }, - -}; - -const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands); - - -/* Macros used to generate entries for the opcodes table. */ - -#define FIXME 0 - -/* Short-Immediate Format Instructions - basic opcode */ -#define OP_SI(x) (((x) & 0x7F) << 15) -#define MASK_SI OP_SI(0x7F) - -/* Long-Immediate Format Instructions - basic opcode */ -#define OP_LI(x) (((x) & 0x3FF) << 12) -#define MASK_LI OP_LI(0x3FF) - -/* Register Format Instructions - basic opcode */ -#define OP_REG(x) OP_LI(x) /* For readability */ -#define MASK_REG MASK_LI /* For readability */ - -/* The 'n' bit at bit 10 */ -#define n(x) ((x) << 10) - -/* The 'i' bit at bit 11 */ -#define i(x) ((x) << 11) - -/* The 'F' bit at bit 27 */ -#define F(x) ((x) << 27) - -/* The 'E' bit at bit 27 */ -#define E(x) ((x) << 27) - -/* The 'M' bit at bit 15 in register and long immediate opcodes */ -#define M_REG(x) ((x) << 15) -#define M_LI(x) ((x) << 15) - -/* The 'M' bit at bit 17 in short immediate opcodes */ -#define M_SI(x) ((x) << 17) - -/* The 'SZ' field at bits 14-13 in register and long immediate opcodes */ -#define SZ_REG(x) ((x) << 13) -#define SZ_LI(x) ((x) << 13) - -/* The 'SZ' field at bits 16-15 in short immediate opcodes */ -#define SZ_SI(x) ((x) << 15) - -/* The 'D' (direct external memory access) bit at bit 10 in long immediate - and register opcodes. */ -#define D(x) ((x) << 10) - -/* The 'S' (scale offset by data size) bit at bit 11 in long immediate - and register opcodes. */ -#define S(x) ((x) << 11) - -/* The 'PD' field at bits 10-9 in floating point instructions */ -#define PD(x) ((x) << 9) - -/* The 'P2' field at bits 8-7 in floating point instructions */ -#define P2(x) ((x) << 7) - -/* The 'P1' field at bits 6-5 in floating point instructions */ -#define P1(x) ((x) << 5) - -/* The 'a' field at bit 16 in vector instructions */ -#define V_a1(x) ((x) << 16) - -/* The 'a' field at bit 11 in vector instructions */ -#define V_a0(x) ((x) << 11) - -/* The 'm' field at bit 10 in vector instructions */ -#define V_m(x) ((x) << 10) - -/* The 'S' field at bit 9 in vector instructions */ -#define V_S(x) ((x) << 9) - -/* The 'Z' field at bit 8 in vector instructions */ -#define V_Z(x) ((x) << 8) - -/* The 'p' field at bit 6 in vector instructions */ -#define V_p(x) ((x) << 6) - -/* The opcode field at bits 21-17 for vector instructions */ -#define OP_V(x) ((x) << 17) -#define MASK_V OP_V(0x1F) - - -/* The opcode table. Formatted for better readability on a wide screen. Also, all - entries with the same mnemonic are sorted so that they are adjacent in the table, - allowing the use of a hash table to locate the first of a sequence of opcodes that have - a particular name. The short immediate forms also come before the long immediate forms - so that the assembler will pick the "best fit" for the size of the operand, except for - the case of the PC relative forms, where the long forms come first and are the default - forms. */ - -const struct tic80_opcode tic80_opcodes[] = { - - /* The "nop" instruction is really "rdcr 0,r0". We put it first so that this - specific bit pattern will get disassembled as a nop rather than an rdcr. The - mask of all ones ensures that this will happen. */ - - {"nop", OP_SI(0x4), ~0, 0, {0} }, - - /* The "br" instruction is really "bbz target,r0,31". We put it first so that - this specific bit pattern will get disassembled as a br rather than bbz. */ - - {"br", OP_LI(0x391), 0xFFFFF000, 0, {OFF_SL_PC} }, - {"br", OP_SI(0x48), 0xFFFF8000, 0, {OFF_SS_PC} }, - {"br", OP_REG(0x390), 0xFFFFF000, 0, {REG_0} }, - {"br.a", OP_LI(0x393), 0xFFFFF000, 0, {OFF_SL_PC} }, - {"br.a", OP_SI(0x49), 0xFFFF8000, 0, {OFF_SS_PC} }, - {"br.a", OP_REG(0x392), 0xFFFFF000, 0, {REG_0} }, - - /* Signed integer ADD */ - - {"add", OP_SI(0x58), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, - {"add", OP_LI(0x3B1), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, - {"add", OP_REG(0x3B0), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - - /* Unsigned integer ADD */ - - {"addu", OP_SI(0x59), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, - {"addu", OP_LI(0x3B3), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, - {"addu", OP_REG(0x3B2), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - - /* Bitwise AND */ - - {"and", OP_SI(0x11), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, - {"and", OP_LI(0x323), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, - {"and", OP_REG(0x322), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"and.tt", OP_SI(0x11), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, - {"and.tt", OP_LI(0x323), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, - {"and.tt", OP_REG(0x322), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - - /* Bitwise AND with ones complement of both sources */ - - {"and.ff", OP_SI(0x18), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, - {"and.ff", OP_LI(0x331), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, - {"and.ff", OP_REG(0x330), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - - /* Bitwise AND with ones complement of source 1 */ - - {"and.ft", OP_SI(0x14), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, - {"and.ft", OP_LI(0x329), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, - {"and.ft", OP_REG(0x328), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - - /* Bitwise AND with ones complement of source 2 */ - - {"and.tf", OP_SI(0x12), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, - {"and.tf", OP_LI(0x325), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, - {"and.tf", OP_REG(0x324), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - - /* Branch Bit One - nonannulled */ - - {"bbo", OP_LI(0x395), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, - {"bbo", OP_SI(0x4A), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, - {"bbo", OP_REG(0x394), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, - - /* Branch Bit One - annulled */ - - {"bbo.a", OP_LI(0x397), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, - {"bbo.a", OP_SI(0x4B), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, - {"bbo.a", OP_REG(0x396), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, - - /* Branch Bit Zero - nonannulled */ - - {"bbz", OP_LI(0x391), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, - {"bbz", OP_SI(0x48), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, - {"bbz", OP_REG(0x390), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, - - /* Branch Bit Zero - annulled */ - - {"bbz.a", OP_LI(0x393), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, - {"bbz.a", OP_SI(0x49), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, - {"bbz.a", OP_REG(0x392), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, - - /* Branch Conditional - nonannulled */ - - {"bcnd", OP_LI(0x399), MASK_LI, 0, {OFF_SL_PC, REG_22, CC} }, - {"bcnd", OP_SI(0x4C), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} }, - {"bcnd", OP_REG(0x398), MASK_REG, 0, {REG_0, REG_22, CC} }, - - /* Branch Conditional - annulled */ - - {"bcnd.a", OP_LI(0x39B), MASK_LI, 0, {OFF_SL_PC, REG_22, CC} }, - {"bcnd.a", OP_SI(0x4D), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} }, - {"bcnd.a", OP_REG(0x39A), MASK_REG, 0, {REG_0, REG_22, CC} }, - - /* Branch Control Register */ - - {"brcr", OP_SI(0x6), MASK_SI, 0, {CR_SI} }, - {"brcr", OP_LI(0x30D), MASK_LI, 0, {CR_LI} }, - {"brcr", OP_REG(0x30C), MASK_REG, 0, {REG_0} }, - - /* Branch and save return - nonannulled */ - - {"bsr", OP_LI(0x381), MASK_LI, 0, {OFF_SL_PC, REG_DEST} }, - {"bsr", OP_SI(0x40), MASK_SI, 0, {OFF_SS_PC, REG_DEST} }, - {"bsr", OP_REG(0x380), MASK_REG, 0, {REG_0, REG_DEST} }, - - /* Branch and save return - annulled */ - - {"bsr.a", OP_LI(0x383), MASK_LI, 0, {OFF_SL_PC, REG_DEST} }, - {"bsr.a", OP_SI(0x41), MASK_SI, 0, {OFF_SS_PC, REG_DEST} }, - {"bsr.a", OP_REG(0x382), MASK_REG, 0, {REG_0, REG_DEST} }, - - /* Send command */ - - {"cmnd", OP_SI(0x2), MASK_SI, 0, {SUI} }, - {"cmnd", OP_LI(0x305), MASK_LI, 0, {LUI} }, - {"cmnd", OP_REG(0x304), MASK_REG, 0, {REG_0} }, - - /* Integer compare */ - - {"cmp", OP_SI(0x50), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, - {"cmp", OP_LI(0x3A1), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, - {"cmp", OP_REG(0x3A0), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - - /* Flush data cache subblock - don't clear subblock preset flag */ - - {"dcachec", OP_SI(0x38), F(1) | (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI} }, - {"dcachec", OP_LI(0x371), F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1), 0, {LSI, REG_BASE_M_LI} }, - {"dcachec", OP_REG(0x370), F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1), 0, {REG_0, REG_BASE_M_LI} }, - - /* Flush data cache subblock - clear subblock preset flag */ - - {"dcachef", OP_SI(0x38) | F(1), F(1) | (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI} }, - {"dcachef", OP_LI(0x371) | F(1), F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1), 0, {LSI, REG_BASE_M_LI} }, - {"dcachef", OP_REG(0x370) | F(1), F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1), 0, {REG_0, REG_BASE_M_LI} }, - - /* Direct load signed data into register */ - - {"dld", OP_LI(0x345) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dld", OP_REG(0x344) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dld.b", OP_LI(0x341) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dld.b", OP_REG(0x340) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dld.d", OP_LI(0x347) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} }, - {"dld.d", OP_REG(0x346) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} }, - {"dld.h", OP_LI(0x343) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dld.h", OP_REG(0x342) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - - /* Direct load unsigned data into register */ - - {"dld.ub", OP_LI(0x351) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dld.ub", OP_REG(0x350) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dld.uh", OP_LI(0x353) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dld.uh", OP_REG(0x352) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - - /* Direct store data into memory */ - - {"dst", OP_LI(0x365) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dst", OP_REG(0x364) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dst.b", OP_LI(0x361) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dst.b", OP_REG(0x360) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dst.d", OP_LI(0x367) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} }, - {"dst.d", OP_REG(0x366) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} }, - {"dst.h", OP_LI(0x363) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dst.h", OP_REG(0x362) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - - /* Emulation stop */ - - {"estop", OP_LI(0x3FC), MASK_LI, 0, {0} }, - - /* Emulation trap */ - - {"etrap", OP_SI(0x1) | E(1), MASK_SI | E(1), 0, {SUI} }, - {"etrap", OP_LI(0x303) | E(1), MASK_LI | E(1), 0, {LUI} }, - {"etrap", OP_REG(0x302) | E(1), MASK_REG | E(1), 0, {REG_0} }, - - /* Floating-point addition */ - - {"fadd.ddd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} }, - {"fadd.dsd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} }, - {"fadd.sdd", OP_LI(0x3E1) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} }, - {"fadd.sdd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} }, - {"fadd.ssd", OP_LI(0x3E1) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} }, - {"fadd.ssd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} }, - {"fadd.sss", OP_LI(0x3E1) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, - {"fadd.sss", OP_REG(0x3E0) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, - - /* Floating point compare */ - - {"fcmp.dd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST} }, - {"fcmp.ds", OP_REG(0x3EA) | PD(0) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST} }, - {"fcmp.sd", OP_LI(0x3EB) | PD(0) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST} }, - {"fcmp.sd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST} }, - {"fcmp.ss", OP_LI(0x3EB) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, - {"fcmp.ss", OP_REG(0x3EA) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, - - /* Floating point divide */ - - {"fdiv.ddd", OP_REG(0x3E6) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} }, - {"fdiv.dsd", OP_REG(0x3E6) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} }, - {"fdiv.sdd", OP_LI(0x3E7) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} }, - {"fdiv.sdd", OP_REG(0x3E6) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} }, - {"fdiv.ssd", OP_LI(0x3E7) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} }, - {"fdiv.ssd", OP_REG(0x3E6) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} }, - {"fdiv.sss", OP_LI(0x3E7) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, - {"fdiv.sss", OP_REG(0x3E6) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, - - /* Floating point multiply */ - - {"fmpy.ddd", OP_REG(0x3E4) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} }, - {"fmpy.dsd", OP_REG(0x3E4) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} }, - {"fmpy.iii", OP_LI(0x3E5) | PD(2) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_22, REG_DEST} }, - {"fmpy.iii", OP_REG(0x3E4) | PD(2) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, - {"fmpy.sdd", OP_LI(0x3E5) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} }, - {"fmpy.sdd", OP_REG(0x3E4) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} }, - {"fmpy.ssd", OP_LI(0x3E5) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} }, - {"fmpy.ssd", OP_REG(0x3E4) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} }, - {"fmpy.sss", OP_LI(0x3E5) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, - {"fmpy.sss", OP_REG(0x3E4) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, - {"fmpy.uuu", OP_LI(0x3E5) | PD(3) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LUI, REG_22, REG_DEST} }, - {"fmpy.uuu", OP_REG(0x3E4) | PD(3) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, - - /* Convert/Round to Minus Infinity */ - - {"frndm.dd", OP_REG(0x3E8) | PD(1) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} }, - {"frndm.di", OP_REG(0x3E8) | PD(2) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, - {"frndm.ds", OP_REG(0x3E8) | PD(0) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, - {"frndm.du", OP_REG(0x3E8) | PD(3) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, - {"frndm.id", OP_LI(0x3E9) | PD(1) | P2(3) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, - {"frndm.id", OP_REG(0x3E8) | PD(1) | P2(3) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"frndm.is", OP_LI(0x3E9) | PD(0) | P2(3) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, - {"frndm.is", OP_REG(0x3E8) | PD(0) | P2(3) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndm.sd", OP_LI(0x3E9) | PD(1) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} }, - {"frndm.sd", OP_REG(0x3E8) | PD(1) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"frndm.si", OP_LI(0x3E9) | PD(2) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"frndm.si", OP_REG(0x3E8) | PD(2) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndm.ss", OP_LI(0x3E9) | PD(0) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"frndm.ss", OP_REG(0x3E8) | PD(0) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndm.su", OP_LI(0x3E9) | PD(3) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"frndm.su", OP_REG(0x3E8) | PD(3) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndm.ud", OP_LI(0x3E9) | PD(1) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, - {"frndm.ud", OP_REG(0x3E8) | PD(1) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"frndm.us", OP_LI(0x3E9) | PD(0) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, - {"frndm.us", OP_REG(0x3E8) | PD(0) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - - /* Convert/Round to Nearest */ - - {"frndn.dd", OP_REG(0x3E8) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} }, - {"frndn.di", OP_REG(0x3E8) | PD(2) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, - {"frndn.ds", OP_REG(0x3E8) | PD(0) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, - {"frndn.du", OP_REG(0x3E8) | PD(3) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, - {"frndn.id", OP_LI(0x3E9) | PD(1) | P2(0) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, - {"frndn.id", OP_REG(0x3E8) | PD(1) | P2(0) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"frndn.is", OP_LI(0x3E9) | PD(0) | P2(0) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, - {"frndn.is", OP_REG(0x3E8) | PD(0) | P2(0) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndn.sd", OP_LI(0x3E9) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} }, - {"frndn.sd", OP_REG(0x3E8) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"frndn.si", OP_LI(0x3E9) | PD(2) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"frndn.si", OP_REG(0x3E8) | PD(2) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndn.ss", OP_LI(0x3E9) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"frndn.ss", OP_REG(0x3E8) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndn.su", OP_LI(0x3E9) | PD(3) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"frndn.su", OP_REG(0x3E8) | PD(3) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndn.ud", OP_LI(0x3E9) | PD(1) | P2(0) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, - {"frndn.ud", OP_REG(0x3E8) | PD(1) | P2(0) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"frndn.us", OP_LI(0x3E9) | PD(0) | P2(0) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, - {"frndn.us", OP_REG(0x3E8) | PD(0) | P2(0) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - - /* Convert/Round to Positive Infinity */ - - {"frndp.dd", OP_REG(0x3E8) | PD(1) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} }, - {"frndp.di", OP_REG(0x3E8) | PD(2) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, - {"frndp.ds", OP_REG(0x3E8) | PD(0) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, - {"frndp.du", OP_REG(0x3E8) | PD(3) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, - {"frndp.id", OP_LI(0x3E9) | PD(1) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, - {"frndp.id", OP_REG(0x3E8) | PD(1) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"frndp.is", OP_LI(0x3E9) | PD(0) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, - {"frndp.is", OP_REG(0x3E8) | PD(0) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndp.sd", OP_LI(0x3E9) | PD(1) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} }, - {"frndp.sd", OP_REG(0x3E8) | PD(1) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"frndp.si", OP_LI(0x3E9) | PD(2) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"frndp.si", OP_REG(0x3E8) | PD(2) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndp.ss", OP_LI(0x3E9) | PD(0) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"frndp.ss", OP_REG(0x3E8) | PD(0) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndp.su", OP_LI(0x3E9) | PD(3) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"frndp.su", OP_REG(0x3E8) | PD(3) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndp.ud", OP_LI(0x3E9) | PD(1) | P2(2) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, - {"frndp.ud", OP_REG(0x3E8) | PD(1) | P2(2) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"frndp.us", OP_LI(0x3E9) | PD(0) | P2(2) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, - {"frndp.us", OP_REG(0x3E8) | PD(0) | P2(2) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - - /* Convert/Round to Zero */ - - {"frndz.dd", OP_REG(0x3E8) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} }, - {"frndz.di", OP_REG(0x3E8) | PD(2) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, - {"frndz.ds", OP_REG(0x3E8) | PD(0) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, - {"frndz.du", OP_REG(0x3E8) | PD(3) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, - {"frndz.id", OP_LI(0x3E9) | PD(1) | P2(1) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, - {"frndz.id", OP_REG(0x3E8) | PD(1) | P2(1) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"frndz.is", OP_LI(0x3E9) | PD(0) | P2(1) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, - {"frndz.is", OP_REG(0x3E8) | PD(0) | P2(1) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndz.sd", OP_LI(0x3E9) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} }, - {"frndz.sd", OP_REG(0x3E8) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"frndz.si", OP_LI(0x3E9) | PD(2) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"frndz.si", OP_REG(0x3E8) | PD(2) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndz.ss", OP_LI(0x3E9) | PD(0) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"frndz.ss", OP_REG(0x3E8) | PD(0) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndz.su", OP_LI(0x3E9) | PD(3) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"frndz.su", OP_REG(0x3E8) | PD(3) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndz.ud", OP_LI(0x3E9) | PD(1) | P2(1) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, - {"frndz.ud", OP_REG(0x3E8) | PD(1) | P2(1) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"frndz.us", OP_LI(0x3E9) | PD(0) | P2(1) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, - {"frndz.us", OP_REG(0x3E8) | PD(0) | P2(1) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - - /* Floating point square root */ - - {"fsqrt.dd", OP_REG(0x3EE) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} }, - {"fsqrt.sd", OP_LI(0x3EF) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} }, - {"fsqrt.sd", OP_REG(0x3EE) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"fsqrt.ss", OP_LI(0x3EF) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"fsqrt.ss", OP_REG(0x3EE) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - - /* Floating point subtraction */ - - { "fsub.ddd", OP_REG(0x3E2) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} }, - { "fsub.dsd", OP_REG(0x3E2) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} }, - { "fsub.sdd", OP_LI(0x3E3) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} }, - { "fsub.sdd", OP_REG(0x3E2) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} }, - { "fsub.ssd", OP_LI(0x3E3) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} }, - { "fsub.ssd", OP_REG(0x3E2) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} }, - { "fsub.sss", OP_LI(0x3E3) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, - { "fsub.sss", OP_REG(0x3E2) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, - - /* Illegal instructions */ - - {"illop0", OP_SI(0x0), MASK_SI, 0, {0} }, - {"illopF", 0x1FF << 13, 0x1FF << 13, 0, {0} }, - - /* Jump and save return */ - - {"jsr", OP_SI(0x44), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} }, - {"jsr", OP_LI(0x389), MASK_LI, 0, {OFF_SL_BR, REG_BASE, REG_DEST} }, - {"jsr", OP_REG(0x388), MASK_REG, 0, {REG_0, REG_BASE, REG_DEST} }, - {"jsr.a", OP_SI(0x45), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} }, - {"jsr.a", OP_LI(0x38B), MASK_LI, 0, {OFF_SL_BR, REG_BASE, REG_DEST} }, - {"jsr.a", OP_REG(0x38A), MASK_REG, 0, {REG_0, REG_BASE, REG_DEST} }, - - /* Load Signed Data Into Register */ - - {"ld", OP_SI(0x22), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, - {"ld", OP_LI(0x345) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld", OP_REG(0x344) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld.b", OP_SI(0x20), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, - {"ld.b", OP_LI(0x341) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld.b", OP_REG(0x340) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld.d", OP_SI(0x23), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST_E} }, - {"ld.d", OP_LI(0x347) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} }, - {"ld.d", OP_REG(0x346) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} }, - {"ld.h", OP_SI(0x21), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, - {"ld.h", OP_LI(0x343) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld.h", OP_REG(0x342) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - - /* Load Unsigned Data Into Register */ - - {"ld.ub", OP_SI(0x28), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, - {"ld.ub", OP_LI(0x351) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld.ub", OP_REG(0x350) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld.uh", OP_SI(0x29), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, - {"ld.uh", OP_LI(0x353) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld.uh", OP_REG(0x352) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - - /* Leftmost one */ - - {"lmo", OP_LI(0x3F0), MASK_LI, 0, {REG_22, REG_DEST} }, - - /* Bitwise logical OR. Note that "or.tt" and "or" are the same instructions. */ - - {"or.ff", OP_SI(0x1E), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, - {"or.ff", OP_LI(0x33D), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, - {"or.ff", OP_REG(0x33C), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"or.ft", OP_SI(0x1D), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, - {"or.ft", OP_LI(0x33B), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, - {"or.ft", OP_REG(0x33A), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"or.tf", OP_SI(0x1B), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, - {"or.tf", OP_LI(0x337), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, - {"or.tf", OP_REG(0x336), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"or.tt", OP_SI(0x17), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, - {"or.tt", OP_LI(0x32F), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, - {"or.tt", OP_REG(0x32E), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"or", OP_SI(0x17), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, - {"or", OP_LI(0x32F), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, - {"or", OP_REG(0x32E), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - - /* Read Control Register */ - - {"rdcr", OP_SI(0x4), MASK_SI | (0x1F << 22), 0, {CR_SI, REG_DEST} }, - {"rdcr", OP_LI(0x309), MASK_LI | (0x1F << 22), 0, {CR_LI, REG_DEST} }, - {"rdcr", OP_REG(0x308), MASK_REG | (0x1F << 22), 0, {REG_0, REG_DEST} }, - - /* Rightmost one */ - - {"rmo", OP_LI(0x3F2), MASK_LI, 0, {REG_22, REG_DEST} }, - - /* Shift Register Left - note that rotl, shl, and ins are all alternate names for one of the shift instructions. - They appear prior to their sl equivalent so that they will be diassembled as the alternate name. */ - - - {"ins", OP_REG(0x31E) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"ins", OP_SI(0xF) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"rotl", OP_REG(0x310) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"rotl", OP_SI(0x8) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"shl", OP_REG(0x31C) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"shl", OP_SI(0xE) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sl.dm", OP_REG(0x312) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sl.dm", OP_SI(0x9) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sl.ds", OP_REG(0x314) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sl.ds", OP_SI(0xA) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sl.dz", OP_REG(0x310) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sl.dz", OP_SI(0x8) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sl.em", OP_REG(0x318) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sl.em", OP_SI(0xC) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sl.es", OP_REG(0x31A) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sl.es", OP_SI(0xD) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sl.ez", OP_REG(0x316) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sl.ez", OP_SI(0xB) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sl.im", OP_REG(0x31E) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sl.im", OP_SI(0xF) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sl.iz", OP_REG(0x31C) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sl.iz", OP_SI(0xE) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - - /* Shift Register Left With Inverted Endmask */ - - {"sli.dm", OP_REG(0x312) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sli.dm", OP_SI(0x9) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sli.ds", OP_REG(0x314) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sli.ds", OP_SI(0xA) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sli.dz", OP_REG(0x310) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sli.dz", OP_SI(0x8) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sli.em", OP_REG(0x318) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sli.em", OP_SI(0xC) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sli.es", OP_REG(0x31A) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sli.es", OP_SI(0xD) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sli.ez", OP_REG(0x316) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sli.ez", OP_SI(0xB) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sli.im", OP_REG(0x31E) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sli.im", OP_SI(0xF) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sli.iz", OP_REG(0x31C) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sli.iz", OP_SI(0xE) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - - /* Shift Register Right - note that exts, extu, rotr, sra, and srl are all alternate names for one of the shift instructions. - They appear prior to their sr equivalent so that they will be diassembled as the alternate name. */ - - {"exts", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"exts", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"extu", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"extu", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"rotr", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"rotr", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sra", OP_REG(0x31A) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sra", OP_SI(0xD) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"srl", OP_REG(0x316) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"srl", OP_SI(0xB) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sr.dm", OP_REG(0x312) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sr.dm", OP_SI(0x9) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sr.ds", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sr.ds", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sr.dz", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sr.dz", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sr.em", OP_REG(0x318) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sr.em", OP_SI(0xC) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sr.es", OP_REG(0x31A) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sr.es", OP_SI(0xD) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sr.ez", OP_REG(0x316) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sr.ez", OP_SI(0xB) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sr.im", OP_REG(0x31E) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sr.im", OP_SI(0xF) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sr.iz", OP_REG(0x31C) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sr.iz", OP_SI(0xE) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - - /* Shift Register Right With Inverted Endmask */ - - {"sri.dm", OP_REG(0x312) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sri.dm", OP_SI(0x9) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sri.ds", OP_REG(0x314) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sri.ds", OP_SI(0xA) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sri.dz", OP_REG(0x310) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sri.dz", OP_SI(0x8) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sri.em", OP_REG(0x318) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sri.em", OP_SI(0xC) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sri.es", OP_REG(0x31A) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sri.es", OP_SI(0xD) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sri.ez", OP_REG(0x316) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sri.ez", OP_SI(0xB) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sri.im", OP_REG(0x31E) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sri.im", OP_SI(0xF) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sri.iz", OP_REG(0x31C) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sri.iz", OP_SI(0xE) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - - /* Store Data into Memory */ - - {"st", OP_SI(0x32), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, - {"st", OP_LI(0x365) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"st", OP_REG(0x364) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"st.b", OP_SI(0x30), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, - {"st.b", OP_LI(0x361) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"st.b", OP_REG(0x360) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"st.d", OP_SI(0x33), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST_E} }, - {"st.d", OP_LI(0x367) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} }, - {"st.d", OP_REG(0x366) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} }, - {"st.h", OP_SI(0x31), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, - {"st.h", OP_LI(0x363) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"st.h", OP_REG(0x362) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - - /* Signed Integer Subtract */ - - {"sub", OP_SI(0x5A), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, - {"sub", OP_LI(0x3B5), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, - {"sub", OP_REG(0x3B4), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - - /* Unsigned Integer Subtract */ - - {"subu", OP_SI(0x5B), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, - {"subu", OP_LI(0x3B7), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, - {"subu", OP_REG(0x3B6), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - - /* Write Control Register - Is a special form of the "swcr" instruction so comes before it in the table. */ - - {"wrcr", OP_SI(0x5), MASK_SI | (0x1F << 27), 0, {CR_SI, REG_22} }, - {"wrcr", OP_LI(0x30B), MASK_LI | (0x1F << 27), 0, {CR_LI, REG_22} }, - {"wrcr", OP_REG(0x30A), MASK_REG | (0x1F << 27), 0, {REG_0, REG_22} }, - - /* Swap Control Register */ - - {"swcr", OP_SI(0x5), MASK_SI, 0, {CR_SI, REG_22, REG_DEST} }, - {"swcr", OP_LI(0x30B), MASK_LI, 0, {CR_LI, REG_22, REG_DEST} }, - {"swcr", OP_REG(0x30A), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - - /* Trap */ - - {"trap", OP_SI(0x1) | E(0), MASK_SI | E(1), 0, {SUI} }, - {"trap", OP_LI(0x303) | E(0), MASK_LI | E(1), 0, {LUI} }, - {"trap", OP_REG(0x302) | E(0), MASK_REG | E(1), 0, {REG_0} }, - - /* Vector Floating-Point Add */ - - {"vadd.dd", OP_REG(0x3C0) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0_E, REG_22_E, REG_22_E} }, - {"vadd.sd", OP_LI(0x3C1) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22_E, REG_22_E} }, - {"vadd.sd", OP_REG(0x3C0) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E, REG_22_E} }, - {"vadd.ss", OP_LI(0x3C1) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, - {"vadd.ss", OP_REG(0x3C0) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} }, - - /* Vector Floating-Point Multiply and Add to Accumulator FIXME! This is not yet fully implemented. - From the documentation there appears to be no way to tell the difference between the opcodes for - instructions that have register destinations and instructions that have accumulator destinations. - Further investigation is necessary. Since this isn't critical to getting a TIC80 toolchain up - and running, it is defered until later. */ - - /* Vector Floating-Point Multiply - Note: If r0 is in the destination reg, then this is a "vector nop" instruction. */ - - {"vmpy.dd", OP_REG(0x3C4) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0_E, REG_22_E, REG_22_E} }, - {"vmpy.sd", OP_LI(0x3C5) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22_E, REG_22_E} }, - {"vmpy.sd", OP_REG(0x3C4) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22_E, REG_22_E} }, - {"vmpy.ss", OP_LI(0x3C5) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22, REG_22} }, - {"vmpy.ss", OP_REG(0x3C4) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} }, - - /* Vector Floating-Point Multiply and Subtract from Accumulator - FIXME: See note above for vmac instruction */ - - /* Vector Floating-Point Subtract Accumulator From Source - FIXME: See note above for vmac instruction */ - - /* Vector Round With Floating-Point Input - FIXME: See note above for vmac instruction */ - - /* Vector Round with Integer Input */ - - {"vrnd.id", OP_LI (0x3CB) | P2(1) | P1(0), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LSI, REG_22_E}}, - {"vrnd.id", OP_REG (0x3CA) | P2(1) | P1(0), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E}}, - {"vrnd.is", OP_LI (0x3CB) | P2(0) | P1(0), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LSI, REG_22}}, - {"vrnd.is", OP_REG (0x3CA) | P2(0) | P1(0), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22}}, - {"vrnd.ud", OP_LI (0x3CB) | P2(1) | P1(1), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LUI, REG_22_E}}, - {"vrnd.ud", OP_REG (0x3CA) | P2(1) | P1(1), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E}}, - {"vrnd.us", OP_LI (0x3CB) | P2(0) | P1(1), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LUI, REG_22}}, - {"vrnd.us", OP_REG (0x3CA) | P2(0) | P1(1), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22}}, - - /* Vector Floating-Point Subtract */ - - {"vsub.dd", OP_REG(0x3C2) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0_E, REG_22_E, REG_22_E} }, - {"vsub.sd", OP_LI(0x3C3) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22_E, REG_22_E} }, - {"vsub.sd", OP_REG(0x3C2) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E, REG_22_E} }, - {"vsub.ss", OP_LI(0x3C3) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, - {"vsub.ss", OP_REG(0x3C2) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} }, - - /* Vector Load Data Into Register - Note that the vector load/store instructions come after the other - vector instructions so that the disassembler will always print the load/store instruction second for - vector instructions that have two instructions in the same opcode. */ - - {"vld0.d", OP_V(0x1E) | V_m(1) | V_S(1) | V_p(0), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} }, - {"vld0.s", OP_V(0x1E) | V_m(1) | V_S(0) | V_p(0), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} }, - {"vld1.d", OP_V(0x1E) | V_m(1) | V_S(1) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} }, - {"vld1.s", OP_V(0x1E) | V_m(1) | V_S(0) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} }, - - /* Vector Store Data Into Memory - Note that the vector load/store instructions come after the other - vector instructions so that the disassembler will always print the load/store instruction second for - vector instructions that have two instructions in the same opcode. */ - - {"vst.d", OP_V(0x1E) | V_m(0) | V_S(1) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} }, - {"vst.s", OP_V(0x1E) | V_m(0) | V_S(0) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} }, - - {"xnor", OP_SI(0x19), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, - {"xnor", OP_LI(0x333), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, - {"xnor", OP_REG(0x332), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - - {"xor", OP_SI(0x16), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, - {"xor", OP_LI(0x32D), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, - {"xor", OP_REG(0x32C), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - -}; - -const int tic80_num_opcodes = sizeof (tic80_opcodes) / sizeof (tic80_opcodes[0]); diff --git a/opcodes/v850-dis.c b/opcodes/v850-dis.c deleted file mode 100644 index c43f6dbea70..00000000000 --- a/opcodes/v850-dis.c +++ /dev/null @@ -1,386 +0,0 @@ -/* Disassemble V850 instructions. - Copyright (C) 1996 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - - -#include <stdio.h> - -#include "ansidecl.h" -#include "opcode/v850.h" -#include "dis-asm.h" - -static const char *const v850_reg_names[] = -{ "r0", "r1", "r2", "sp", "gp", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", - "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", - "r24", "r25", "r26", "r27", "r28", "r29", "ep", "lp" }; - -static const char *const v850_sreg_names[] = -{ "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7", - "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15", -/* start-sanitize-v850e */ - "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "sr21", "sr22", "sr23", - "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31", -/* end-sanitize-v850e */ - "sr16", "sr17", "sr18", "sr19", "sr20", "sr21", "sr22", "sr23", - "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31" }; - -static const char *const v850_cc_names[] = -{ "v", "c/l", "z", "nh", "s/n", "t", "lt", "le", - "nv", "nc/nl", "nz", "h", "ns/p", "sa", "ge", "gt" }; - -static int -disassemble (memaddr, info, insn) - bfd_vma memaddr; - struct disassemble_info *info; - unsigned long insn; -{ - struct v850_opcode * op = (struct v850_opcode *)v850_opcodes; - const struct v850_operand * operand; - int match = 0; - int short_op = ((insn & 0x0600) != 0x0600); - int bytes_read; - int target_processor; - -/* start-sanitize-v850e */ - /* Special case: 32 bit MOV */ - if ((insn & 0xffe0) == 0x0620) - short_op = true; -/* end-sanitize-v850e */ - - bytes_read = short_op ? 2 : 4; - - /* If this is a two byte insn, then mask off the high bits. */ - if (short_op) - insn &= 0xffff; - - switch (info->mach) - { - case 0: - default: - target_processor = PROCESSOR_V850; - break; - -/* start-sanitize-v850e */ - case bfd_mach_v850e: - target_processor = PROCESSOR_V850E; - break; - - case bfd_mach_v850eq: - target_processor = PROCESSOR_V850EQ; - break; -/* end-sanitize-v850e */ - } - - /* Find the opcode. */ - while (op->name) - { - if ((op->mask & insn) == op->opcode - && (op->processors & target_processor)) - { - const unsigned char * opindex_ptr; - unsigned int opnum; - unsigned int memop; - - match = 1; - (*info->fprintf_func) (info->stream, "%s\t", op->name); -//fprintf (stderr, "match: mask: %x insn: %x, opcode: %x, name: %s\n", op->mask, insn, op->opcode, op->name ); - - memop = op->memop; - /* Now print the operands. - - MEMOP is the operand number at which a memory - address specification starts, or zero if this - instruction has no memory addresses. - - A memory address is always two arguments. - - This information allows us to determine when to - insert commas into the output stream as well as - when to insert disp[reg] expressions onto the - output stream. */ - - for (opindex_ptr = op->operands, opnum = 1; - *opindex_ptr != 0; - opindex_ptr++, opnum++) - { - long value; - int flag; - int status; - bfd_byte buffer[ 4 ]; - - operand = &v850_operands[*opindex_ptr]; - - if (operand->extract) - value = (operand->extract) (insn, 0); - else - { - if (operand->bits == -1) - value = (insn & operand->shift); - else - value = (insn >> operand->shift) & ((1 << operand->bits) - 1); - - if (operand->flags & V850_OPERAND_SIGNED) - value = ((long)(value << (32 - operand->bits)) - >> (32 - operand->bits)); - } - - /* The first operand is always output without any - special handling. - - For the following arguments: - - If memop && opnum == memop + 1, then we need '[' since - we're about to output the register used in a memory - reference. - - If memop && opnum == memop + 2, then we need ']' since - we just finished the register in a memory reference. We - also need a ',' before this operand. - - Else we just need a comma. - - We may need to output a trailing ']' if the last operand - in an instruction is the register for a memory address. - - The exception (and there's always an exception) is the - "jmp" insn which needs square brackets around it's only - register argument. */ - - if (memop && opnum == memop + 1) info->fprintf_func (info->stream, "["); - else if (memop && opnum == memop + 2) info->fprintf_func (info->stream, "],"); - else if (memop == 1 && opnum == 1 - && (operand->flags & V850_OPERAND_REG)) - info->fprintf_func (info->stream, "["); - else if (opnum > 1) info->fprintf_func (info->stream, ", "); - - /* extract the flags, ignorng ones which do not effect disassembly output. */ - flag = operand->flags; - flag &= ~ V850_OPERAND_SIGNED; - flag &= ~ V850_OPERAND_RELAX; - flag &= - flag; - - switch (flag) - { - case V850_OPERAND_REG: info->fprintf_func (info->stream, "%s", v850_reg_names[value]); break; - case V850_OPERAND_SRG: info->fprintf_func (info->stream, "%s", v850_sreg_names[value]); break; - case V850_OPERAND_CC: info->fprintf_func (info->stream, "%s", v850_cc_names[value]); break; - case V850_OPERAND_EP: info->fprintf_func (info->stream, "ep"); break; - default: info->fprintf_func (info->stream, "%d", value); break; - case V850_OPERAND_DISP: - { - bfd_vma addr = value + memaddr; - - /* On the v850 the top 8 bits of an address are used by an overlay manager. - Thus it may happen that when we are looking for a symbol to match - against an address with some of its top bits set, the search fails to - turn up an exact match. In this case we try to find an exact match - against a symbol in the lower address space, and if we find one, we - use that address. We only do this for JARL instructions however, as - we do not want to misinterpret branch instructions. */ - if (operand->bits == 22) - { - if ( ! info->symbol_at_address_func (addr, info) - && ((addr & 0xFF000000) != 0) - && info->symbol_at_address_func (addr & 0x00FFFFFF, info)) - { - addr &= 0x00FFFFFF; - } - } - info->print_address_func (addr, info); - break; - } - -/* start-sanitize-v850e */ - case V850E_PUSH_POP: - { - static int list12_regs[32] = { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 }; - static int list18_h_regs[32] = { 19, 18, 17, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, 30, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 }; - static int list18_l_regs[32] = { 3, 2, 1, -2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, 14, 15, 13, 12, 7, 6, 5, 4, 11, 10, 9, 8 }; - int * regs; - int i; - unsigned long int mask = 0; - int pc = false; - int sr = false; - - - switch (operand->shift) - { - case 0xffe00001: regs = list12_regs; break; - case 0xfff8000f: regs = list18_h_regs; break; - case 0xfff8001f: regs = list18_l_regs; value &= ~0x10; break; /* Do not include magic bit */ - default: - fprintf (stderr, "unknown operand shift: %x\n", operand->shift ); - abort(); - } - - for (i = 0; i < 32; i++) - { - if (value & (1 << i)) - { - switch (regs[ i ]) - { - default: mask |= (1 << regs[ i ]); break; - case 0: fprintf (stderr, "unknown pop reg: %d\n", i ); abort(); - case -1: pc = true; break; - case -2: sr = true; break; - } - } - } - - info->fprintf_func (info->stream, "{"); - - if (mask || pc || sr) - { - if (mask) - { - unsigned int bit; - int shown_one = false; - - for (bit = 0; bit < 32; bit++) - if (mask & (1 << bit)) - { - unsigned long int first = bit; - unsigned long int last; - - if (shown_one) - info->fprintf_func (info->stream, ", "); - else - shown_one = true; - - info->fprintf_func (info->stream, v850_reg_names[first]); - - for (bit++; bit < 32; bit++) - if ((mask & (1 << bit)) == 0) - break; - - last = bit; - - if (last > first + 1) - { - info->fprintf_func (info->stream, " - %s", v850_reg_names[ last - 1 ]); - } - } - } - - if (pc) - info->fprintf_func (info->stream, "%sPC", mask ? ", " : ""); - if (sr) - info->fprintf_func (info->stream, "%sSR", (mask || pc) ? ", " : ""); - } - - info->fprintf_func (info->stream, "}"); - } - break; - - case V850E_IMMEDIATE16: - status = info->read_memory_func (memaddr + bytes_read, buffer, 2, info); - if (status == 0) - { - bytes_read += 2; - value = bfd_getl16 (buffer); - - /* If this is a DISPOSE instruction with ff set to 0x10, then shift value up by 16. */ - if ((insn & 0x001fffc0) == 0x00130780) - value <<= 16; - - info->fprintf_func (info->stream, "0x%x", value); - } - else - { - info->memory_error_func (status, memaddr + bytes_read, info); - } - break; - - case V850E_IMMEDIATE32: - status = info->read_memory_func (memaddr + bytes_read, buffer, 4, info); - if (status == 0) - { - bytes_read += 4; - value = bfd_getl32 (buffer); - info->fprintf_func (info->stream, "0x%lx", value); - } - else - { - info->memory_error_func (status, memaddr + bytes_read, info); - } - break; -/* end-sanitize-v850e */ - } - - /* Handle jmp correctly. */ - if (memop == 1 && opnum == 1 - && ((operand->flags & V850_OPERAND_REG) != 0)) - (*info->fprintf_func) (info->stream, "]"); - } - - /* Close any square bracket we left open. */ - if (memop && opnum == memop + 2) - (*info->fprintf_func) (info->stream, "]"); - - /* All done. */ - break; - } - op++; - } - - if (!match) - { - if (short_op) - info->fprintf_func (info->stream, ".short\t0x%04x", insn); - else - info->fprintf_func (info->stream, ".long\t0x%08x", insn); - } - - return bytes_read; -} - -int -print_insn_v850 (memaddr, info) - bfd_vma memaddr; - struct disassemble_info * info; -{ - int status; - bfd_byte buffer[ 4 ]; - unsigned long insn; - - /* First figure out how big the opcode is. */ - - status = info->read_memory_func (memaddr, buffer, 2, info); - if (status == 0) - { - insn = bfd_getl16 (buffer); - - if ( (insn & 0x0600) == 0x0600 - && (insn & 0xffe0) != 0x0620) - { - /* If this is a 4 byte insn, read 4 bytes of stuff. */ - status = info->read_memory_func (memaddr, buffer, 4, info); - - if (status == 0) - insn = bfd_getl32 (buffer); - } - } - - if (status != 0) - { - info->memory_error_func (status, memaddr, info); - return -1; - } - - /* Make sure we tell our caller how many bytes we consumed. */ - return disassemble (memaddr, info, insn); -} diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c deleted file mode 100644 index 5376bdc09ad..00000000000 --- a/opcodes/v850-opc.c +++ /dev/null @@ -1,803 +0,0 @@ -/* Assemble V850 instructions. - Copyright (C) 1996 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "ansidecl.h" -#include "opcode/v850.h" -#include <stdio.h> - -/* regular opcode */ -#define OP(x) ((x & 0x3f) << 5) -#define OP_MASK OP (0x3f) - -/* conditional branch opcode */ -#define BOP(x) ((0x0b << 7) | (x & 0x0f)) -#define BOP_MASK ((0x0f << 7) | 0x0f) - -/* one-word opcodes */ -#define one(x) ((unsigned int) (x)) - -/* two-word opcodes */ -#define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16)) - - - -/* The functions used to insert and extract complicated operands. */ - -static unsigned long -insert_d9 (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - if (value > 0xff || value < -0x100) - *errmsg = "branch value out of range"; - - if ((value % 2) != 0) - *errmsg = "branch to odd offset"; - - return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3)); -} - -static unsigned long -extract_d9 (insn, invalid) - unsigned long insn; - int *invalid; -{ - unsigned long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3); - - if ((insn & 0x8000) != 0) - ret -= 0x0200; - - return ret; -} - -static unsigned long -insert_d22 (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - if (value > 0x1fffff || value < -0x200000) - *errmsg = "branch value out of range"; - - if ((value % 2) != 0) - *errmsg = "branch to odd offset"; - - return (insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16)); -} - -static unsigned long -extract_d22 (insn, invalid) - unsigned long insn; - int *invalid; -{ - unsigned long ret = ((insn & 0xfffe0000) >> 16) | ((insn & 0x3f) << 16); - - return ((ret << 10) >> 10); -} - -static unsigned long -insert_d16_15 (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - if (value > 0x7fff || value < -0x8000) - *errmsg = "value out of range"; - - if ((value % 2) != 0) - *errmsg = "load/store half/word at odd offset"; - - return insn | ((value & 0xfffe) << 16); -} - -static unsigned long -extract_d16_15 (insn, invalid) - unsigned long insn; - int * invalid; -{ - signed long ret = (insn & 0xfffe0000); - - return ret >> 16; -} - -static unsigned long -insert_d8_7 (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - if (value > 0xff || value < 0) - *errmsg = "short load/store half value out of range"; - - if ((value % 2) != 0) - *errmsg = "short load/store half at odd offset"; - - value >>= 1; - - return (insn | (value & 0x7f)); -} - -static unsigned long -extract_d8_7 (insn, invalid) - unsigned long insn; - int *invalid; -{ - unsigned long ret = (insn & 0x7f); - - return ret << 1; -} - -static unsigned long -insert_d8_6 (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; -{ - if (value > 0xff || value < 0) - *errmsg = "short load/store word value out of range"; - - if ((value % 4) != 0) - *errmsg = "short load/store word at odd offset"; - - value >>= 1; - - return (insn | (value & 0x7e)); -} - -static unsigned long -extract_d8_6 (insn, invalid) - unsigned long insn; - int *invalid; -{ - unsigned long ret = (insn & 0x7e); - - return ret << 1; -} - -/* start-sanitize-v850e */ - -static unsigned long -insert_d5_4 (insn, value, errmsg) - unsigned long insn; - long value; - const char ** errmsg; -{ - if (value > 0x1f || value < 0) - *errmsg = "unsigned short load half value out of range"; - - if (value & 1) - *errmsg = "unsigned short load half at odd offset"; - - value >>= 1; - - return (insn | (value & 0x0f)); -} - -static unsigned long -extract_d5_4 (insn, invalid) - unsigned long insn; - int * invalid; -{ - unsigned long ret = (insn & 0x0f); - - return ret << 1; -} - -static unsigned long -insert_d16_16 (insn, value, errmsg) - unsigned long insn; - signed long value; - const char ** errmsg; -{ - if (value > 0x7fff || value < -0x8000) - *errmsg = "value out of range"; - - return (insn | ((value & 0xfffe) << 16) | ((value & 1) << 5)); -} - -static unsigned long -extract_d16_16 (insn, invalid) - unsigned long insn; - int * invalid; -{ - signed long ret = insn & 0xfffe0000; - - ret >>= 16; - - ret |= ((insn & 0x20) >> 5); - - return ret; -} - -static unsigned long -insert_i9 (insn, value, errmsg) - unsigned long insn; - signed long value; - const char ** errmsg; -{ - if (value > 0xff || value < -0x100) - *errmsg = "value out of range"; - - return insn | ((value & 0x1e0) << 13) | (value & 0x1f); -} - -static unsigned long -extract_i9 (insn, invalid) - unsigned long insn; - int * invalid; -{ - signed long ret = insn & 0x003c0000; - - ret <<= 10; - ret >>= 23; - - ret |= (insn & 0x1f); - - return ret; -} - -static unsigned long -insert_u9 (insn, value, errmsg) - unsigned long insn; - unsigned long value; - const char ** errmsg; -{ - if (value > 0x1ff) - *errmsg = "value out of range"; - - return insn | ((value & 0x1e0) << 13) | (value & 0x1f); -} - -static unsigned long -extract_u9 (insn, invalid) - unsigned long insn; - int * invalid; -{ - unsigned long ret = insn & 0x003c0000; - - ret >>= 13; - - ret |= (insn & 0x1f); - - return ret; -} - -static unsigned long -insert_spe (insn, value, errmsg) - unsigned long insn; - unsigned long value; - const char ** errmsg; -{ - if (value != 3) - *errmsg = "invalid register for stack adjustment"; - - return insn & (~ 0x180000); -} - -static unsigned long -extract_spe (insn, invalid) - unsigned long insn; - int * invalid; -{ - return 3; -} - -/* end-sanitize-v850e */ -/* start-sanitize-v850eq */ - -static unsigned long -insert_i5div (insn, value, errmsg) - unsigned long insn; - unsigned long value; - const char ** errmsg; -{ - if (value > 0x1ff) - *errmsg = "value out of range"; - - if (value & 1) - *errmsg = "value must be even"; - - value = 32 - value; - - return insn | ((value & 0x1e) << 17); -} - -static unsigned long -extract_i5div (insn, invalid) - unsigned long insn; - int * invalid; -{ - unsigned long ret = insn & 0x3c0000; - - ret >>= 17; - - ret = 32 - ret; - - return ret; -} - -/* end-sanitize-v850eq */ - - -/* Warning: code in gas/config/tc-v850.c examines the contents of this array. - If you change any of the values here, be sure to look for side effects in - that code. */ -const struct v850_operand v850_operands[] = -{ -#define UNUSED 0 - { 0, 0, NULL, NULL, 0 }, - -/* The R1 field in a format 1, 6, 7, or 9 insn. */ -#define R1 (UNUSED + 1) - { 5, 0, NULL, NULL, V850_OPERAND_REG }, - -/* As above, but register 0 is not allowed. */ -#define R1_NOTR0 (R1 + 1) - { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, - -/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */ -#define R2 (R1_NOTR0 + 1) - { 5, 11, NULL, NULL, V850_OPERAND_REG }, - -/* As above, but register 0 is not allowed. */ -#define R2_NOTR0 (R2 + 1) - { 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, - -/* The imm5 field in a format 2 insn. */ -#define I5 (R2_NOTR0 + 1) - { 5, 0, NULL, NULL, V850_OPERAND_SIGNED }, - -/* The unsigned imm5 field in a format 2 insn. */ -#define I5U (I5 + 1) - { 5, 0, NULL, NULL, 0 }, - -/* The imm16 field in a format 6 insn. */ -#define I16 (I5U + 1) - { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, - -/* The signed disp7 field in a format 4 insn. */ -#define D7 (I16 + 1) - { 7, 0, NULL, NULL, 0}, - -/* The disp16 field in a format 6 insn. */ -#define D16_15 (D7 + 1) - { 15, 17, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED }, - -/* The 3 bit immediate field in format 8 insn. */ -#define B3 (D16_15 + 1) - { 3, 11, NULL, NULL, 0 }, - -/* The 4 bit condition code in a setf instruction */ -#define CCCC (B3 + 1) - { 4, 0, NULL, NULL, V850_OPERAND_CC }, - -/* The unsigned DISP8 field in a format 4 insn. */ -#define D8_7 (CCCC + 1) - { 7, 0, insert_d8_7, extract_d8_7, 0 }, - -/* The unsigned DISP8 field in a format 4 insn. */ -#define D8_6 (D8_7 + 1) - { 6, 1, insert_d8_6, extract_d8_6, 0 }, - -/* System register operands. */ -#define SR1 (D8_6 + 1) - { 5, 0, NULL, NULL, V850_OPERAND_SRG }, - -/* EP Register. */ -#define EP (SR1 + 1) - { 0, 0, NULL, NULL, V850_OPERAND_EP }, - -/* The imm16 field (unsigned) in a format 6 insn. */ -#define I16U (EP + 1) - { 16, 16, NULL, NULL, 0}, - -/* The R2 field as a system register. */ -#define SR2 (I16U + 1) - { 5, 11, NULL, NULL, V850_OPERAND_SRG }, - -/* The disp16 field in a format 8 insn. */ -#define D16 (SR2 + 1) - { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, - -/* The DISP22 field in a format 4 insn, relaxable. */ -#define D9_RELAX (D16 + 1) - { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP }, - -/* The DISP22 field in a format 4 insn. - - This _must_ follow D9_RELAX; the assembler assumes that the longer - version immediately follows the shorter version for relaxing. */ -#define D22 (D9_RELAX + 1) - { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP }, - -/* start-sanitize-v850e */ - -/* The signed disp4 field in a format 4 insn. */ -#define D4 (D22 + 1) - { 4, 0, NULL, NULL, 0}, - -/* The unsigned disp5 field in a format 4 insn. */ -#define D5_4 (D4 + 1) - { 4, 0, insert_d5_4, extract_d5_4, 0 }, - -/* The disp16 field in an format 7 unsigned byte load insn. */ -#define D16_16 (D5_4 + 1) - { -1, 0xfffe0020, insert_d16_16, extract_d16_16, 0 }, - -/* Third register in conditional moves. */ -#define R3 (D16_16 + 1) - { 5, 27, NULL, NULL, V850_OPERAND_REG }, - -/* Condition code in conditional moves. */ -#define MOVCC (R3 + 1) - { 4, 17, NULL, NULL, V850_OPERAND_CC }, - -/* The imm9 field in a multiply word. */ -#define I9 (MOVCC + 1) - { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED }, - -/* The unsigned imm9 field in a multiply word. */ -#define U9 (I9 + 1) - { 9, 0, insert_u9, extract_u9, 0 }, - -/* A list of registers in a prepare/dispose instruction. */ -#define LIST12 (U9 + 1) - { -1, 0xffe00001, NULL, NULL, V850E_PUSH_POP }, - -/* The IMM6 field in a call instruction. */ -#define I6 (LIST12 + 1) - { 6, 0, NULL, NULL, 0 }, - -/* The 16 bit immediate following a 32 bit instruction. */ -#define IMM16 (I6 + 1) - { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850E_IMMEDIATE16 }, - -/* The 32 bit immediate following a 32 bit instruction. */ -#define IMM32 (IMM16 + 1) - { 0, 0, NULL, NULL, V850E_IMMEDIATE32 }, - -/* The imm5 field in a push/pop instruction. */ -#define IMM5 (IMM32 + 1) - { 5, 1, NULL, NULL, 0 }, - -/* Reg2 in dispose instruction. */ -#define R2DISPOSE (IMM5 + 1) - { 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, - -/* Stack pointer in prepare instruction. */ -#define SP (R2DISPOSE + 1) - { 2, 19, insert_spe, extract_spe, V850_OPERAND_REG }, - -/* end-sanitize-v850e */ -/* start-sanitize-v850eq */ - -/* The IMM5 field in a divide N step instruction. */ -#define I5DIV (SP + 1) - { 9, 0, insert_i5div, extract_i5div, V850_OPERAND_SIGNED }, - - /* The list of registers in a PUSHMH/POPMH instruction. */ -#define LIST18_H (I5DIV + 1) - { -1, 0xfff8000f, NULL, NULL, V850E_PUSH_POP }, - - /* The list of registers in a PUSHML/POPML instruction. */ -#define LIST18_L (LIST18_H + 1) - { -1, 0xfff8001f, NULL, NULL, V850E_PUSH_POP }, /* The setting of the 4th bit is a flag to disassmble() in v850-dis.c */ - -/* end-sanitize-v850eq */ -} ; - - -/* reg-reg instruction format (Format I) */ -#define IF1 {R1, R2} - -/* imm-reg instruction format (Format II) */ -#define IF2 {I5, R2} - -/* conditional branch instruction format (Format III) */ -#define IF3 {D9_RELAX} - -/* 3 operand instruction (Format VI) */ -#define IF6 {I16, R1, R2} - -/* 3 operand instruction (Format VI) */ -#define IF6U {I16U, R1, R2} - - - -/* The opcode table. - - The format of the opcode table is: - - NAME OPCODE MASK { OPERANDS } MEMOP PROCESSOR - - NAME is the name of the instruction. - OPCODE is the instruction opcode. - MASK is the opcode mask; this is used to tell the disassembler - which bits in the actual opcode must match OPCODE. - OPERANDS is the list of operands. - MEMOP specifies which operand (if any) is a memory operand. - PROCESSOR specifies which CPUs support the opcode. - - The disassembler reads the table in order and prints the first - instruction which matches, so this table is sorted to put more - specific instructions before more general instructions. It is also - sorted by major opcode. - - The table is also sorted by name. This is used by the assembler. - When parsing an instruction the assembler finds the first occurance - of the name of the instruciton in this table and then attempts to - match the instruction's arguments with description of the operands - associated with the entry it has just found in this table. If the - match fails the assembler looks at the next entry in this table. - If that entry has the same name as the previous entry, then it - tries to match the instruction against that entry and so on. This - is how the assembler copes with multiple, different formats of the - same instruction. */ - -const struct v850_opcode v850_opcodes[] = -{ -{ "breakpoint", 0xffff, 0xffff, {UNUSED}, 0, PROCESSOR_ALL }, - -{ "jmp", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL }, - -/* load/store instructions */ -/* start-sanitize-v850eq */ -{ "sld.bu", one (0x0300), one (0x0780), {D7, EP, R2_NOTR0}, 1, PROCESSOR_V850EQ }, -/* end-sanitize-v850eq */ -/* start-sanitize-v850e */ -{ "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2_NOTR0}, 1, PROCESSOR_V850E }, -/* end-sanitize-v850e */ - -/* start-sanitize-v850eq */ -{ "sld.hu", one (0x0400), one (0x0780), {D8_7, EP, R2_NOTR0}, 1, PROCESSOR_V850EQ }, -/* end-sanitize-v850eq */ -/* start-sanitize-v850e */ -{ "sld.hu", one (0x0070), one (0x07f0), {D5_4, EP, R2_NOTR0}, 1, PROCESSOR_V850E }, -/* end-sanitize-v850e */ - -/* start-sanitize-v850eq */ -{ "sld.b", one (0x0060), one (0x07f0), {D4, EP, R2}, 1, PROCESSOR_V850EQ }, -/* end-sanitize-v850eq */ -/* start-sanitize-v850e */ -{ "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850E }, -/* end-sanitize-v850e */ -{ "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850 }, - -/* start-sanitize-v850eq */ -{ "sld.h", one (0x0070), one (0x07f0), {D5_4, EP, R2}, 1, PROCESSOR_V850EQ }, -/* end-sanitize-v850eq */ -/* start-sanitize-v850e */ -{ "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850E }, -/* end-sanitize-v850e */ - -{ "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850 }, -{ "sld.w", one (0x0500), one (0x0781), {D8_6, EP, R2}, 1, PROCESSOR_ALL }, -{ "sst.b", one (0x0380), one (0x0780), {R2, D7, EP}, 2, PROCESSOR_ALL }, -{ "sst.h", one (0x0480), one (0x0780), {R2, D8_7, EP}, 2, PROCESSOR_ALL }, -{ "sst.w", one (0x0501), one (0x0781), {R2, D8_6, EP}, 2, PROCESSOR_ALL }, - -/* start-sanitize-v850eq */ -{ "pushml", two (0x07e0, 0x0001), two (0xfff0, 0x0007), {LIST18_L}, 0, PROCESSOR_V850EQ }, -{ "pushmh", two (0x07e0, 0x0003), two (0xfff0, 0x0007), {LIST18_H}, 0, PROCESSOR_V850EQ }, -{ "popml", two (0x07f0, 0x0001), two (0xfff0, 0x0007), {LIST18_L}, 0, PROCESSOR_V850EQ }, -{ "popmh", two (0x07f0, 0x0003), two (0xfff0, 0x0007), {LIST18_H}, 0, PROCESSOR_V850EQ }, -/* end-sanitize-v850eq */ - -/* start-sanitize-v850e */ -{ "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0, PROCESSOR_NOT_V850 }, -{ "prepare", two (0x0780, 0x000b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16}, 0, PROCESSOR_NOT_V850 }, -{ "prepare", two (0x0780, 0x0013), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16}, 0, PROCESSOR_NOT_V850 }, -{ "prepare", two (0x0780, 0x001b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM32}, 0, PROCESSOR_NOT_V850 }, -{ "prepare", two (0x0780, 0x0001), two (0xffc0, 0x001f), {LIST12, IMM5}, 0, PROCESSOR_NOT_V850 }, -{ "dispose", one (0x0640), one (0xffc0), {IMM5, LIST12, R2DISPOSE},0, PROCESSOR_NOT_V850 }, -{ "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0, PROCESSOR_NOT_V850 }, -/* end-sanitize-v850e */ - -{ "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 1, PROCESSOR_ALL }, -{ "ld.h", two (0x0720, 0x0000), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1, PROCESSOR_ALL }, -{ "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1, PROCESSOR_ALL }, -/* start-sanitize-v850e */ -{ "ld.bu", two (0x0780, 0x0001), two (0x07c0, 0x0001), {D16_16, R1, R2_NOTR0}, 1, PROCESSOR_NOT_V850 }, -{ "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2_NOTR0}, 1, PROCESSOR_NOT_V850 }, -/* end-sanitize-v850e */ -{ "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 2, PROCESSOR_ALL }, -{ "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL }, -{ "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL }, - -/* start-sanitize-v850e */ -/* byte swap/extend instructions */ -{ "zxb", one (0x0080), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, -{ "zxh", one (0x00c0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, -{ "sxb", one (0x00a0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, -{ "sxh", one (0x00e0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, -{ "bsh", two (0x07e0, 0x0342), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, - -/* jump table instructions */ -{ "switch", one (0x0040), one (0xffe0), {R1}, 1, PROCESSOR_NOT_V850 }, -{ "callt", one (0x0200), one (0xffc0), {I6}, 0, PROCESSOR_NOT_V850 }, -{ "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 }, -/* end-sanitize-v850e */ - -/* arithmetic operation instructions */ -{ "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_ALL }, -/* start-sanitize-v850e */ -{ "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 }, - -{ "mul", two (0x07e0, 0x0220), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "mul", two (0x07e0, 0x0240), two (0x07e0, 0x07c3), {I9, R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "mulu", two (0x07e0, 0x0222), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "mulu", two (0x07e0, 0x0242), two (0x07e0, 0x07c3), {U9, R2, R3}, 0, PROCESSOR_NOT_V850 }, - -{ "div", two (0x07e0, 0x02c0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "divu", two (0x07e0, 0x02c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, -/* end-sanitize-v850e */ -{ "divh", OP (0x02), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, - -/* start-sanitize-v850eq */ -{ "divhn", two (0x07e0, 0x0280), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EQ }, -{ "divhun", two (0x07e0, 0x0282), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EQ }, -{ "divn", two (0x07e0, 0x02c0), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EQ }, -{ "divun", two (0x07e0, 0x02c2), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EQ }, -{ "sdivhn", two (0x07e0, 0x0180), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EQ }, -{ "sdivhun", two (0x07e0, 0x0182), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EQ }, -{ "sdivn", two (0x07e0, 0x01c0), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EQ }, -{ "sdivun", two (0x07e0, 0x01c2), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EQ }, -/* end-sanitize-v850eq */ - -{ "nop", one (0x00), one (0xffff), {0}, 0, PROCESSOR_ALL }, -{ "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, -/* start-sanitize-v850e */ -{ "mov", one (0x0620), one (0xffe0), {IMM32, R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, -/* end-sanitize-v850e */ -{ "mov", OP (0x00), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "movea", OP (0x31), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "movhi", OP (0x32), OP_MASK, {I16U, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "add", OP (0x0e), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "add", OP (0x12), OP_MASK, IF2, 0, PROCESSOR_ALL }, -{ "addi", OP (0x30), OP_MASK, IF6, 0, PROCESSOR_ALL }, -{ "sub", OP (0x0d), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "subr", OP (0x0c), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "mulh", OP (0x07), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "mulhi", OP (0x37), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "cmp", OP (0x0f), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "cmp", OP (0x13), OP_MASK, IF2, 0, PROCESSOR_ALL }, - -/* saturated operation instructions */ -{ "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, - -/* logical operation instructions */ -{ "tst", OP (0x0b), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "or", OP (0x08), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "ori", OP (0x34), OP_MASK, IF6U, 0, PROCESSOR_ALL }, -{ "and", OP (0x0a), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "andi", OP (0x36), OP_MASK, IF6U, 0, PROCESSOR_ALL }, -{ "xor", OP (0x09), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "xori", OP (0x35), OP_MASK, IF6U, 0, PROCESSOR_ALL }, -{ "not", OP (0x01), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "sar", OP (0x15), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, -{ "sar", two (0x07e0, 0x00a0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, -{ "shl", OP (0x16), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, -{ "shl", two (0x07e0, 0x00c0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, -{ "shr", OP (0x14), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, -{ "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, -/* start-sanitize-v850e */ -{ "sasf", two (0x07e0, 0x0200), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_NOT_V850 }, -/* end-sanitize-v850e */ - -/* branch instructions */ - /* signed integer */ -{ "bgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "blt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "ble", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* unsigned integer */ -{ "bh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* common */ -{ "be", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* others */ -{ "bv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "br", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - -/* Branch macros. - - We use the short form in the opcode/mask fields. The assembler - will twiddle bits as necessary if the long form is needed. */ - - /* signed integer */ -{ "jgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jlt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jle", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* unsigned integer */ -{ "jh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* common */ -{ "je", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* others */ -{ "jv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jbr", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - -{ "jr", one (0x0780), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL }, -{ "jarl", one (0x0780), two (0x07c0, 0x0001), {D22, R2}, 0, PROCESSOR_ALL}, - -/* bit manipulation instructions */ -{ "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, -/* start-sanitize-v850e */ -{ "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, -/* end-sanitize-v850e */ -{ "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, -/* start-sanitize-v850e */ -{ "not1", two (0x07e0, 0x00e2), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, -/* end-sanitize-v850e */ -{ "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, -/* start-sanitize-v850e */ -{ "clr1", two (0x07e0, 0x00e4), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, -/* end-sanitize-v850e */ -{ "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, -/* start-sanitize-v850e */ -{ "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, -/* end-sanitize-v850e */ - -/* special instructions */ -{ "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, -{ "ei", two (0x87e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, -{ "halt", two (0x07e0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, -{ "reti", two (0x07e0, 0x0140), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, -{ "trap", two (0x07e0, 0x0100), two (0xffe0, 0xffff), {I5U}, 0, PROCESSOR_ALL }, -{ "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0xffff), {R1, SR2}, 0, PROCESSOR_ALL }, -{ "stsr", two (0x07e0, 0x0040), two (0x07e0, 0xffff), {SR1, R2}, 0, PROCESSOR_ALL }, -{ 0, 0, 0, {0}, 0, 0 }, - -} ; - -const int v850_num_opcodes = - sizeof (v850_opcodes) / sizeof (v850_opcodes[0]); - diff --git a/opcodes/vax-dis.c b/opcodes/vax-dis.c deleted file mode 100644 index 54b59f30d40..00000000000 --- a/opcodes/vax-dis.c +++ /dev/null @@ -1,299 +0,0 @@ -/* Print VAX instructions. - Copyright (C) 1995, 1998 Free Software Foundation, Inc. - Contributed by Pauline Middelink <middelin@polyware.iaf.nl> - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "opcode/vax.h" -#include "dis-asm.h" - -/* Local function prototypes */ -static int -print_insn_arg PARAMS ((const char *, unsigned char *, bfd_vma, - disassemble_info *)); - -static int -print_insn_mode PARAMS ((int, unsigned char *, bfd_vma, disassemble_info *)); - -static char *reg_names[] = -{ - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", "ap", "fp", "sp", "pc" -}; - -/* Sign-extend an (unsigned char). */ -#if __STDC__ == 1 -#define COERCE_SIGNED_CHAR(ch) ((signed char)(ch)) -#else -#define COERCE_SIGNED_CHAR(ch) ((int)(((ch) ^ 0x80) & 0xFF) - 128) -#endif - -/* Get a 1 byte signed integer. */ -#define NEXTBYTE(p) \ - (p += 1, FETCH_DATA (info, p), \ - COERCE_SIGNED_CHAR(p[-1])) - -/* Get a 2 byte signed integer. */ -#define COERCE16(x) ((int) (((x) ^ 0x8000) - 0x8000)) -#define NEXTWORD(p) \ - (p += 2, FETCH_DATA (info, p), \ - COERCE16 ((p[-1] << 8) + p[-2])) - -/* Get a 4 byte signed integer. */ -#define COERCE32(x) ((int) (((x) ^ 0x80000000) - 0x80000000)) -#define NEXTLONG(p) \ - (p += 4, FETCH_DATA (info, p), \ - (COERCE32 ((((((p[-1] << 8) + p[-2]) << 8) + p[-3]) << 8) + p[-4]))) - -/* Maximum length of an instruction. */ -#define MAXLEN 25 - -#include <setjmp.h> - -struct private -{ - /* Points to first byte not fetched. */ - bfd_byte *max_fetched; - bfd_byte the_buffer[MAXLEN]; - bfd_vma insn_start; - jmp_buf bailout; -}; - -/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) - to ADDR (exclusive) are valid. Returns 1 for success, longjmps - on error. */ -#define FETCH_DATA(info, addr) \ - ((addr) <= ((struct private *)(info->private_data))->max_fetched \ - ? 1 : fetch_data ((info), (addr))) - -static int -fetch_data (info, addr) - struct disassemble_info *info; - bfd_byte *addr; -{ - int status; - struct private *priv = (struct private *) info->private_data; - bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); - - status = (*info->read_memory_func) (start, - priv->max_fetched, - addr - priv->max_fetched, - info); - if (status != 0) - { - (*info->memory_error_func) (status, start, info); - longjmp (priv->bailout, 1); - } - else - priv->max_fetched = addr; - - return 1; -} - -/* Print the vax instruction at address MEMADDR in debugged memory, - on INFO->STREAM. Returns length of the instruction, in bytes. */ - -int -print_insn_vax (memaddr, info) - bfd_vma memaddr; - disassemble_info *info; -{ - const struct vot *votp; - const char *argp = NULL; - unsigned char *arg; - struct private priv; - bfd_byte *buffer = priv.the_buffer; - - info->private_data = (PTR) &priv; - priv.max_fetched = priv.the_buffer; - priv.insn_start = memaddr; - if (setjmp (priv.bailout) != 0) - { - /* Error return. */ - return -1; - } - - FETCH_DATA (info, buffer + 2); - for (votp = &votstrs[0]; votp->name[0]; votp++) - { - register vax_opcodeT opcode = votp->detail.code; - - /* 2 byte codes match 2 buffer pos. */ - if ((bfd_byte) opcode == buffer[0] - && (opcode >> 8 == 0 || opcode >> 8 == buffer[1])) - { - argp = votp->detail.args; - break; - } - } - if (argp == NULL) - { - /* Handle undefined instructions. */ - (*info->fprintf_func) (info->stream, ".word 0x%x", - (buffer[0] << 8) + buffer[1]); - return 2; - } - - /* Point at first byte of argument data, and at descriptor for first - argument. */ - arg = buffer + ((votp->detail.code >> 8) ? 2 : 1); - - /* Make sure we have it in mem */ - FETCH_DATA (info, arg); - - (*info->fprintf_func) (info->stream, "%s", votp->name); - if (*argp) - (*info->fprintf_func) (info->stream, " "); - - while (*argp) - { - arg += print_insn_arg (argp, arg, memaddr + arg - buffer, info); - argp += 2; - if (*argp) - (*info->fprintf_func) (info->stream, ","); - } - - return arg - buffer; -} - -/* Returns number of bytes "eaten" by the operand, or return -1 if an - invalid operand was found, or -2 if an opcode tabel error was - found. */ - -static int -print_insn_arg (d, p0, addr, info) - const char *d; - unsigned char *p0; - bfd_vma addr; /* PC for this arg to be relative to */ - disassemble_info *info; -{ - int arg_len; - - /* check validity of addressing length */ - switch (d[1]) - { - case 'b' : arg_len = 1; break; - case 'd' : arg_len = 8; break; - case 'f' : arg_len = 4; break; - case 'g' : arg_len = 8; break; - case 'h' : arg_len = 16; break; - case 'l' : arg_len = 4; break; - case 'o' : arg_len = 16; break; - case 'w' : arg_len = 2; break; - case 'q' : arg_len = 8; break; - default : abort(); - } - - /* branches have no mode byte */ - if (d[0] == 'b') - { - unsigned char *p = p0; - - if (arg_len == 1) - (*info->print_address_func) (addr + 1 + NEXTBYTE (p), info); - else - (*info->print_address_func) (addr + 2 + NEXTWORD (p), info); - - return p - p0; - } - - return print_insn_mode (arg_len, p0, addr, info); -} - -static int -print_insn_mode (size, p0, addr, info) - int size; - unsigned char *p0; - bfd_vma addr; /* PC for this arg to be relative to */ - disassemble_info *info; -{ - unsigned char *p = p0; - unsigned char mode, reg; - - /* fetch and interpret mode byte */ - mode = (unsigned char) NEXTBYTE (p); - reg = mode & 0xF; - switch (mode & 0xF0) - { - case 0x00: - case 0x10: - case 0x20: - case 0x30: /* literal mode $number */ - (*info->fprintf_func) (info->stream, "$0x%x", mode); - break; - case 0x40: /* index: base-addr[Rn] */ - p += print_insn_mode (size, p0 + 1, addr + 1, info); - (*info->fprintf_func) (info->stream, "[%s]", reg_names[reg]); - break; - case 0x50: /* register: Rn */ - (*info->fprintf_func) (info->stream, "%s", reg_names[reg]); - break; - case 0x60: /* register deferred: (Rn) */ - (*info->fprintf_func) (info->stream, "(%s)", reg_names[reg]); - break; - case 0x70: /* autodecrement: -(Rn) */ - (*info->fprintf_func) (info->stream, "-(%s)", reg_names[reg]); - break; - case 0x80: /* autoincrement: (Rn)+ */ - if (reg == 0xF) - { /* immediate? */ - int i; - - FETCH_DATA (info, p + size); - (*info->fprintf_func) (info->stream, "$0x"); - for (i = 0; i < size; i++) - (*info->fprintf_func) (info->stream, "%02x", p[size - i - 1]); - p += size; - } - else - (*info->fprintf_func) (info->stream, "(%s)+", reg_names[reg]); - break; - case 0x90: /* autoincrement deferred: @(Rn)+ */ - if (reg == 0xF) - (*info->fprintf_func) (info->stream, "*0x%x", NEXTLONG (p)); - else - (*info->fprintf_func) (info->stream, "@(%s)+", reg_names[reg]); - break; - case 0xB0: /* displacement byte deferred: *displ(Rn) */ - (*info->fprintf_func) (info->stream, "*"); - case 0xA0: /* displacement byte: displ(Rn) */ - if (reg == 0xF) - (*info->print_address_func) (addr + 2 + NEXTBYTE (p), info); - else - (*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTBYTE (p), - reg_names[reg]); - break; - case 0xD0: /* displacement word deferred: *displ(Rn) */ - (*info->fprintf_func) (info->stream, "*"); - case 0xC0: /* displacement word: displ(Rn) */ - if (reg == 0xF) - (*info->print_address_func) (addr + 3 + NEXTWORD (p), info); - else - (*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTWORD (p), - reg_names[reg]); - break; - case 0xF0: /* displacement long deferred: *displ(Rn) */ - (*info->fprintf_func) (info->stream, "*"); - case 0xE0: /* displacement long: displ(Rn) */ - if (reg == 0xF) - (*info->print_address_func) (addr + 5 + NEXTLONG (p), info); - else - (*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTLONG (p), - reg_names[reg]); - break; - } - - return p - p0; -} diff --git a/opcodes/w65-dis.c b/opcodes/w65-dis.c deleted file mode 100644 index 02c6d195b9a..00000000000 --- a/opcodes/w65-dis.c +++ /dev/null @@ -1,118 +0,0 @@ -/* Disassemble WDC 65816 instructions. - Copyright (C) 1995 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ - -#include <stdio.h> -#define STATIC_TABLE -#define DEFINE_TABLE - -#include "w65-opc.h" -#include "dis-asm.h" - -static fprintf_ftype fpr; -static void *stream; -static struct disassemble_info *local_info; -#if 0 -static char *lname[] = {"r0","r1","r2","r3","r4","r5","r6","r7","s0"}; - -static char *findname (val) - unsigned int val; -{ - if (val >= 0x10 && val <= 0x20) - return lname[(val - 0x10) / 2]; - return 0; -} -#endif -static void -print_operand (lookup, format, args) - int lookup; - char *format; - unsigned int *args; -{ - int val; - int c; - char *name; - while (*format) - { - switch ( c = *format++) - { - case '$': - val = args[(*format++) - '0']; - if (lookup) - { -#if 0 - name = findname(val); - if (name) - fpr(stream, "%s", name); - else -#endif - local_info->print_address_func (val, local_info); - } - else - fpr (stream, "0x%x", val); - - break; - default: - fpr(stream,"%c", c); - break; - } - } -} -int -print_insn_w65(memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - - - int status = 0; - unsigned char insn[4]; - register struct opinfo *op; - int i; - int X =0; - int M = 0; - int args[2]; -stream = info->stream; - fpr = info->fprintf_func; -local_info = info; - for (i = 0; i <4 && status == 0; i++) - { - status = info->read_memory_func(memaddr+i, insn + i, 1, info); - } - - - for (op = optable; op->val != insn[0]; op++) - ; - - fpr(stream,"%s", op->name); - - /* Prepare all the posible operand values */ - { - int size = 1; - int asR_W65_ABS8 = insn[1]; - int asR_W65_ABS16 = (insn[2] << 8) + asR_W65_ABS8; - int asR_W65_ABS24 = (insn[3] << 16) + asR_W65_ABS16; - int asR_W65_PCR8 = ((char)(asR_W65_ABS8)) + memaddr + 2; - int asR_W65_PCR16 = ((short)(asR_W65_ABS16)) + memaddr + 3; - - switch (op->amode) { - DISASM(); - } - - return size; - } - -} diff --git a/opcodes/w65-opc.h b/opcodes/w65-opc.h deleted file mode 100644 index 91bfabb114d..00000000000 --- a/opcodes/w65-opc.h +++ /dev/null @@ -1,547 +0,0 @@ - /* WDC 65816 Assembler opcode table */ - /* (generated by the program sim/w65/gencode -a) */ -#define ADDR_IMMTOA 1 /* #a */ -#define ADDR_IMMCOP 2 /* #c */ -#define ADDR_IMMTOI 3 /* #i */ -#define ADDR_ACC 4 /* A */ -#define ADDR_PC_REL 5 /* r */ -#define ADDR_PC_REL_LONG 6 /* rl */ -#define ADDR_IMPLIED 7 /* i */ -#define ADDR_STACK 8 /* s */ -#define ADDR_DIR 9 /* d */ -#define ADDR_DIR_IDX_X 10 /* d,x */ -#define ADDR_DIR_IDX_Y 11 /* d,y */ -#define ADDR_DIR_IND 12 /* (d) */ -#define ADDR_DIR_IDX_IND_X 13 /* (d,x) */ -#define ADDR_DIR_IND_IDX_Y 14 /* (d),y */ -#define ADDR_DIR_IND_LONG 15 /* [d] */ -#define ADDR_DIR_IND_IDX_Y_LONG 16 /* [d],y */ -#define ADDR_ABS 17 /* a */ -#define ADDR_ABS_IDX_X 18 /* a,x */ -#define ADDR_ABS_IDX_Y 19 /* a,y */ -#define ADDR_ABS_LONG 20 /* al */ -#define ADDR_ABS_IND_LONG 21 /* [a] */ -#define ADDR_ABS_LONG_IDX_X 22 /* al,x */ -#define ADDR_STACK_REL 23 /* d,s */ -#define ADDR_STACK_REL_INDX_IDX 24 /* (d,s),y */ -#define ADDR_ABS_IND 25 /* (a) */ -#define ADDR_ABS_IND_IDX 26 /* (a,x) */ -#define ADDR_BLOCK_MOVE 27 /* xyz */ -struct opinfo { - int val; - int code; - char *name; - int amode; -}; -struct opinfo optable[257]={ -#define O_adc 1 -#define O_and 2 -#define O_asl 3 -#define O_bcc 4 -#define O_bcs 5 -#define O_beq 6 -#define O_bit 7 -#define O_bmi 8 -#define O_bne 9 -#define O_bpl 10 -#define O_bra 11 -#define O_brk 12 -#define O_brl 13 -#define O_bvc 14 -#define O_bvs 15 -#define O_clc 16 -#define O_cld 17 -#define O_cli 18 -#define O_clv 19 -#define O_cmp 20 -#define O_cop 21 -#define O_cpx 22 -#define O_cpy 23 -#define O_dec 24 -#define O_dex 25 -#define O_dey 26 -#define O_eor 27 -#define O_inc 28 -#define O_inx 29 -#define O_iny 30 -#define O_jmp 31 -#define O_jsr 32 -#define O_lda 33 -#define O_ldx 34 -#define O_ldy 35 -#define O_lsr 36 -#define O_mvn 37 -#define O_mvp 38 -#define O_nop 39 -#define O_ora 40 -#define O_pea 41 -#define O_pei 42 -#define O_per 43 -#define O_pha 44 -#define O_phb 45 -#define O_phd 46 -#define O_phk 47 -#define O_php 48 -#define O_phx 49 -#define O_phy 50 -#define O_pla 51 -#define O_plb 52 -#define O_pld 53 -#define O_plp 54 -#define O_plx 55 -#define O_ply 56 -#define O_rep 57 -#define O_rol 58 -#define O_ror 59 -#define O_rti 60 -#define O_rtl 61 -#define O_rts 62 -#define O_sbc 63 -#define O_sec 64 -#define O_sed 65 -#define O_sei 66 -#define O_sep 67 -#define O_sta 68 -#define O_stp 69 -#define O_stx 70 -#define O_sty 71 -#define O_stz 72 -#define O_tax 73 -#define O_tay 74 -#define O_tcd 75 -#define O_tcs 76 -#define O_tdc 77 -#define O_trb 78 -#define O_tsb 79 -#define O_tsc 80 -#define O_tsx 81 -#define O_txa 82 -#define O_txs 83 -#define O_txy 84 -#define O_tya 85 -#define O_tyx 86 -#define O_wai 87 -#define O_wdm 88 -#define O_xba 89 -#define O_xce 90 -#ifdef DEFINE_TABLE - {0x69, O_adc, "adc", ADDR_IMMTOA}, - {0x72, O_adc, "adc", ADDR_DIR_IND}, - {0x71, O_adc, "adc", ADDR_DIR_IND_IDX_Y}, - {0x73, O_adc, "adc", ADDR_STACK_REL_INDX_IDX}, - {0x61, O_adc, "adc", ADDR_DIR_IDX_IND_X}, - {0x67, O_adc, "adc", ADDR_DIR_IND_LONG}, - {0x77, O_adc, "adc", ADDR_DIR_IND_IDX_Y_LONG}, - {0x6D, O_adc, "adc", ADDR_ABS}, - {0x7D, O_adc, "adc", ADDR_ABS_IDX_X}, - {0x79, O_adc, "adc", ADDR_ABS_IDX_Y}, - {0x6F, O_adc, "adc", ADDR_ABS_LONG}, - {0x7F, O_adc, "adc", ADDR_ABS_LONG_IDX_X}, - {0x65, O_adc, "adc", ADDR_DIR}, - {0x63, O_adc, "adc", ADDR_STACK_REL}, - {0x75, O_adc, "adc", ADDR_DIR_IDX_X}, - {0x29, O_and, "and", ADDR_IMMTOA}, - {0x32, O_and, "and", ADDR_DIR_IND}, - {0x31, O_and, "and", ADDR_DIR_IND_IDX_Y}, - {0x33, O_and, "and", ADDR_STACK_REL_INDX_IDX}, - {0x21, O_and, "and", ADDR_DIR_IDX_IND_X}, - {0x27, O_and, "and", ADDR_DIR_IND_LONG}, - {0x37, O_and, "and", ADDR_DIR_IND_IDX_Y_LONG}, - {0x2D, O_and, "and", ADDR_ABS}, - {0x3D, O_and, "and", ADDR_ABS_IDX_X}, - {0x39, O_and, "and", ADDR_ABS_IDX_Y}, - {0x2F, O_and, "and", ADDR_ABS_LONG}, - {0x3F, O_and, "and", ADDR_ABS_LONG_IDX_X}, - {0x25, O_and, "and", ADDR_DIR}, - {0x23, O_and, "and", ADDR_STACK_REL}, - {0x35, O_and, "and", ADDR_DIR_IDX_X}, - {0x0A, O_asl, "asl", ADDR_ACC}, - {0x0E, O_asl, "asl", ADDR_ABS}, - {0x1E, O_asl, "asl", ADDR_ABS_IDX_X}, - {0x06, O_asl, "asl", ADDR_DIR}, - {0x16, O_asl, "asl", ADDR_DIR_IDX_X}, - {0x90, O_bcc, "bcc", ADDR_PC_REL}, - {0xB0, O_bcs, "bcs", ADDR_PC_REL}, - {0xF0, O_beq, "beq", ADDR_PC_REL}, - {0x89, O_bit, "bit", ADDR_IMMTOA}, - {0x24, O_bit, "bit", ADDR_DIR_IND}, - {0x34, O_bit, "bit", ADDR_DIR_IDX_IND_X}, - {0x2C, O_bit, "bit", ADDR_ABS}, - {0x3C, O_bit, "bit", ADDR_ABS_IDX_X}, - {0x30, O_bmi, "bmi", ADDR_PC_REL}, - {0xD0, O_bne, "bne", ADDR_PC_REL}, - {0x10, O_bpl, "bpl", ADDR_PC_REL}, - {0x80, O_bra, "bra", ADDR_PC_REL}, - {0x00, O_brk, "brk", ADDR_STACK}, - {0x82, O_brl, "brl", ADDR_PC_REL_LONG}, - {0x50, O_bvc, "bvc", ADDR_PC_REL}, - {0x70, O_bvs, "bvs", ADDR_PC_REL}, - {0x18, O_clc, "clc", ADDR_IMPLIED}, - {0xD8, O_cld, "cld", ADDR_IMPLIED}, - {0x58, O_cli, "cli", ADDR_IMPLIED}, - {0xB8, O_clv, "clv", ADDR_IMPLIED}, - {0xC9, O_cmp, "cmp", ADDR_IMMTOA}, - {0xD2, O_cmp, "cmp", ADDR_DIR_IND}, - {0xD1, O_cmp, "cmp", ADDR_DIR_IND_IDX_Y}, - {0xD3, O_cmp, "cmp", ADDR_STACK_REL_INDX_IDX}, - {0xC1, O_cmp, "cmp", ADDR_DIR_IDX_IND_X}, - {0xC7, O_cmp, "cmp", ADDR_DIR_IND_LONG}, - {0xD7, O_cmp, "cmp", ADDR_DIR_IND_IDX_Y_LONG}, - {0xCD, O_cmp, "cmp", ADDR_ABS}, - {0xDD, O_cmp, "cmp", ADDR_ABS_IDX_X}, - {0xD9, O_cmp, "cmp", ADDR_ABS_IDX_Y}, - {0xCF, O_cmp, "cmp", ADDR_ABS_LONG}, - {0xDF, O_cmp, "cmp", ADDR_ABS_LONG_IDX_X}, - {0xC5, O_cmp, "cmp", ADDR_DIR}, - {0xC3, O_cmp, "cmp", ADDR_STACK_REL}, - {0xD5, O_cmp, "cmp", ADDR_DIR_IDX_X}, - {0x02, O_cop, "cop", ADDR_IMMCOP}, - {0xE0, O_cpx, "cpx", ADDR_IMMTOI}, - {0xEC, O_cpx, "cpx", ADDR_ABS}, - {0xE4, O_cpx, "cpx", ADDR_DIR}, - {0xC0, O_cpy, "cpy", ADDR_IMMTOI}, - {0xCC, O_cpy, "cpy", ADDR_ABS}, - {0xC4, O_cpy, "cpy", ADDR_DIR}, - {0x3A, O_dec, "dec", ADDR_ACC}, - {0xCE, O_dec, "dec", ADDR_ABS}, - {0xDE, O_dec, "dec", ADDR_ABS_IDX_X}, - {0xC6, O_dec, "dec", ADDR_DIR}, - {0xD6, O_dec, "dec", ADDR_DIR_IDX_X}, - {0xCA, O_dex, "dex", ADDR_IMPLIED}, - {0x88, O_dey, "dey", ADDR_IMPLIED}, - {0x49, O_eor, "eor", ADDR_IMMTOA}, - {0x52, O_eor, "eor", ADDR_DIR_IND}, - {0x51, O_eor, "eor", ADDR_DIR_IND_IDX_Y}, - {0x53, O_eor, "eor", ADDR_STACK_REL_INDX_IDX}, - {0x41, O_eor, "eor", ADDR_DIR_IDX_IND_X}, - {0x47, O_eor, "eor", ADDR_DIR_IND_LONG}, - {0x57, O_eor, "eor", ADDR_DIR_IND_IDX_Y_LONG}, - {0x4D, O_eor, "eor", ADDR_ABS}, - {0x5D, O_eor, "eor", ADDR_ABS_IDX_X}, - {0x59, O_eor, "eor", ADDR_ABS_IDX_Y}, - {0x4F, O_eor, "eor", ADDR_ABS_LONG}, - {0x5F, O_eor, "eor", ADDR_ABS_LONG_IDX_X}, - {0x45, O_eor, "eor", ADDR_DIR}, - {0x43, O_eor, "eor", ADDR_STACK_REL}, - {0x55, O_eor, "eor", ADDR_DIR_IDX_X}, - {0x1A, O_inc, "inc", ADDR_ACC}, - {0xEE, O_inc, "inc", ADDR_ABS}, - {0xFE, O_inc, "inc", ADDR_ABS_IDX_X}, - {0xE6, O_inc, "inc", ADDR_DIR}, - {0xF6, O_inc, "inc", ADDR_DIR_IDX_X}, - {0xE8, O_inx, "inx", ADDR_IMPLIED}, - {0xC8, O_iny, "iny", ADDR_IMPLIED}, - {0x6C, O_jmp, "jmp", ADDR_ABS_IND}, - {0x7C, O_jmp, "jmp", ADDR_ABS_IND_IDX}, - {0xDC, O_jmp, "jmp", ADDR_ABS_IND_LONG}, - {0x4C, O_jmp, "jmp", ADDR_ABS}, - {0x5C, O_jmp, "jmp", ADDR_ABS_LONG}, - {0xFC, O_jsr, "jsr", ADDR_ABS_IND_IDX}, - {0x20, O_jsr, "jsr", ADDR_ABS}, - {0x22, O_jsr, "jsr", ADDR_ABS_LONG}, - {0xA9, O_lda, "lda", ADDR_IMMTOA}, - {0xB2, O_lda, "lda", ADDR_DIR_IND}, - {0xB1, O_lda, "lda", ADDR_DIR_IND_IDX_Y}, - {0xB3, O_lda, "lda", ADDR_STACK_REL_INDX_IDX}, - {0xA1, O_lda, "lda", ADDR_DIR_IDX_IND_X}, - {0xA7, O_lda, "lda", ADDR_DIR_IND_LONG}, - {0xB7, O_lda, "lda", ADDR_DIR_IND_IDX_Y_LONG}, - {0xAD, O_lda, "lda", ADDR_ABS}, - {0xBD, O_lda, "lda", ADDR_ABS_IDX_X}, - {0xB9, O_lda, "lda", ADDR_ABS_IDX_Y}, - {0xAF, O_lda, "lda", ADDR_ABS_LONG}, - {0xBF, O_lda, "lda", ADDR_ABS_LONG_IDX_X}, - {0xA5, O_lda, "lda", ADDR_DIR}, - {0xA3, O_lda, "lda", ADDR_STACK_REL}, - {0xB5, O_lda, "lda", ADDR_DIR_IDX_X}, - {0xA2, O_ldx, "ldx", ADDR_IMMTOI}, - {0xAE, O_ldx, "ldx", ADDR_ABS}, - {0xBE, O_ldx, "ldx", ADDR_ABS_IDX_Y}, - {0xA6, O_ldx, "ldx", ADDR_DIR}, - {0xB6, O_ldx, "ldx", ADDR_DIR_IDX_Y}, - {0xA0, O_ldy, "ldy", ADDR_IMMTOI}, - {0xAC, O_ldy, "ldy", ADDR_ABS}, - {0xBC, O_ldy, "ldy", ADDR_ABS_IDX_X}, - {0xA4, O_ldy, "ldy", ADDR_DIR}, - {0xB4, O_ldy, "ldy", ADDR_DIR_IDX_X}, - {0x4A, O_lsr, "lsr", ADDR_ACC}, - {0x4E, O_lsr, "lsr", ADDR_ABS}, - {0x5E, O_lsr, "lsr", ADDR_ABS_IDX_X}, - {0x46, O_lsr, "lsr", ADDR_DIR}, - {0x56, O_lsr, "lsr", ADDR_DIR_IDX_X}, - {0x54, O_mvn, "mvn", ADDR_BLOCK_MOVE}, - {0x44, O_mvp, "mvp", ADDR_BLOCK_MOVE}, - {0xEA, O_nop, "nop", ADDR_IMPLIED}, - {0x09, O_ora, "ora", ADDR_IMMTOA}, - {0x12, O_ora, "ora", ADDR_DIR_IND}, - {0x11, O_ora, "ora", ADDR_DIR_IND_IDX_Y}, - {0x13, O_ora, "ora", ADDR_STACK_REL_INDX_IDX}, - {0x01, O_ora, "ora", ADDR_DIR_IDX_IND_X}, - {0x07, O_ora, "ora", ADDR_DIR_IND_LONG}, - {0x17, O_ora, "ora", ADDR_DIR_IND_IDX_Y_LONG}, - {0x0D, O_ora, "ora", ADDR_ABS}, - {0x1D, O_ora, "ora", ADDR_ABS_IDX_X}, - {0x19, O_ora, "ora", ADDR_ABS_IDX_Y}, - {0x0F, O_ora, "ora", ADDR_ABS_LONG}, - {0x1F, O_ora, "ora", ADDR_ABS_LONG_IDX_X}, - {0x05, O_ora, "ora", ADDR_DIR}, - {0x03, O_ora, "ora", ADDR_STACK_REL}, - {0x15, O_ora, "ora", ADDR_DIR_IDX_X}, - {0xF4, O_pea, "pea", ADDR_ABS}, - {0xD4, O_pei, "pei", ADDR_DIR}, - {0x62, O_per, "per", ADDR_PC_REL_LONG}, - {0x48, O_pha, "pha", ADDR_STACK}, - {0x8B, O_phb, "phb", ADDR_STACK}, - {0x0B, O_phd, "phd", ADDR_STACK}, - {0x4B, O_phk, "phk", ADDR_STACK}, - {0x08, O_php, "php", ADDR_STACK}, - {0xDA, O_phx, "phx", ADDR_STACK}, - {0x5A, O_phy, "phy", ADDR_STACK}, - {0x68, O_pla, "pla", ADDR_STACK}, - {0xAB, O_plb, "plb", ADDR_STACK}, - {0x2B, O_pld, "pld", ADDR_STACK}, - {0x28, O_plp, "plp", ADDR_STACK}, - {0xFA, O_plx, "plx", ADDR_STACK}, - {0x7A, O_ply, "ply", ADDR_STACK}, - {0xC2, O_rep, "rep", ADDR_IMMCOP}, - {0x2A, O_rol, "rol", ADDR_ACC}, - {0x2E, O_rol, "rol", ADDR_ABS}, - {0x3E, O_rol, "rol", ADDR_ABS_IDX_X}, - {0x26, O_rol, "rol", ADDR_DIR}, - {0x36, O_rol, "rol", ADDR_DIR_IDX_X}, - {0x6A, O_ror, "ror", ADDR_ACC}, - {0x6E, O_ror, "ror", ADDR_ABS}, - {0x7E, O_ror, "ror", ADDR_ABS_IDX_X}, - {0x66, O_ror, "ror", ADDR_DIR}, - {0x76, O_ror, "ror", ADDR_DIR_IDX_X}, - {0x40, O_rti, "rti", ADDR_STACK}, - {0x6B, O_rtl, "rtl", ADDR_STACK}, - {0x60, O_rts, "rts", ADDR_STACK}, - {0xE9, O_sbc, "sbc", ADDR_IMMTOA}, - {0xF2, O_sbc, "sbc", ADDR_DIR_IND}, - {0xF1, O_sbc, "sbc", ADDR_DIR_IND_IDX_Y}, - {0xF3, O_sbc, "sbc", ADDR_STACK_REL_INDX_IDX}, - {0xE1, O_sbc, "sbc", ADDR_DIR_IDX_IND_X}, - {0xE7, O_sbc, "sbc", ADDR_DIR_IND_LONG}, - {0xF7, O_sbc, "sbc", ADDR_DIR_IND_IDX_Y_LONG}, - {0xED, O_sbc, "sbc", ADDR_ABS}, - {0xFD, O_sbc, "sbc", ADDR_ABS_IDX_X}, - {0xF9, O_sbc, "sbc", ADDR_ABS_IDX_Y}, - {0xEF, O_sbc, "sbc", ADDR_ABS_LONG}, - {0xFF, O_sbc, "sbc", ADDR_ABS_LONG_IDX_X}, - {0xE5, O_sbc, "sbc", ADDR_DIR}, - {0xE3, O_sbc, "sbc", ADDR_STACK_REL}, - {0xF5, O_sbc, "sbc", ADDR_DIR_IDX_X}, - {0x38, O_sec, "sec", ADDR_IMPLIED}, - {0xF8, O_sed, "sed", ADDR_IMPLIED}, - {0x78, O_sei, "sei", ADDR_IMPLIED}, - {0xE2, O_sep, "sep", ADDR_IMMCOP}, - {0x92, O_sta, "sta", ADDR_DIR_IND}, - {0x91, O_sta, "sta", ADDR_DIR_IND_IDX_Y}, - {0x93, O_sta, "sta", ADDR_STACK_REL_INDX_IDX}, - {0x81, O_sta, "sta", ADDR_DIR_IDX_IND_X}, - {0x87, O_sta, "sta", ADDR_DIR_IND_LONG}, - {0x97, O_sta, "sta", ADDR_DIR_IND_IDX_Y_LONG}, - {0x8D, O_sta, "sta", ADDR_ABS}, - {0x9D, O_sta, "sta", ADDR_ABS_IDX_X}, - {0x99, O_sta, "sta", ADDR_ABS_IDX_Y}, - {0x8F, O_sta, "sta", ADDR_ABS_LONG}, - {0x9F, O_sta, "sta", ADDR_ABS_LONG_IDX_X}, - {0x85, O_sta, "sta", ADDR_DIR}, - {0x83, O_sta, "sta", ADDR_STACK_REL}, - {0x95, O_sta, "sta", ADDR_DIR_IDX_X}, - {0xDB, O_stp, "stp", ADDR_IMPLIED}, - {0x8E, O_stx, "stx", ADDR_ABS}, - {0x86, O_stx, "stx", ADDR_DIR}, - {0x96, O_stx, "stx", ADDR_DIR_IDX_X}, - {0x8C, O_sty, "sty", ADDR_ABS}, - {0x84, O_sty, "sty", ADDR_DIR}, - {0x94, O_sty, "sty", ADDR_DIR_IDX_X}, - {0x9C, O_stz, "stz", ADDR_ABS}, - {0x9E, O_stz, "stz", ADDR_ABS_IDX_X}, - {0x64, O_stz, "stz", ADDR_DIR}, - {0x74, O_stz, "stz", ADDR_DIR_IDX_X}, - {0xAA, O_tax, "tax", ADDR_IMPLIED}, - {0xA8, O_tay, "tay", ADDR_IMPLIED}, - {0x5B, O_tcd, "tcd", ADDR_IMPLIED}, - {0x1B, O_tcs, "tcs", ADDR_IMPLIED}, - {0x7B, O_tdc, "tdc", ADDR_IMPLIED}, - {0x1C, O_trb, "trb", ADDR_ABS}, - {0x14, O_trb, "trb", ADDR_DIR}, - {0x0C, O_tsb, "tsb", ADDR_ABS}, - {0x04, O_tsb, "tsb", ADDR_DIR}, - {0x3B, O_tsc, "tsc", ADDR_IMPLIED}, - {0xBA, O_tsx, "tsx", ADDR_IMPLIED}, - {0x8A, O_txa, "txa", ADDR_IMPLIED}, - {0x9A, O_txs, "txs", ADDR_IMPLIED}, - {0x9B, O_txy, "txy", ADDR_IMPLIED}, - {0x98, O_tya, "tya", ADDR_IMPLIED}, - {0xBB, O_tyx, "tyx", ADDR_IMPLIED}, - {0xCB, O_wai, "wai", ADDR_IMPLIED}, - {0x42, O_wdm, "wdm", ADDR_IMPLIED}, - {0xEB, O_xba, "xba", ADDR_IMPLIED}, - {0xFB, O_xce, "xce", ADDR_IMPLIED}, -0}; -#endif -#define DISASM()\ - case ADDR_IMMTOA:\ - args[0] = M==0 ? asR_W65_ABS16 : asR_W65_ABS8;\ - print_operand (0, " #$0", args);\ - size += M==0 ? 2:1;\ - break;\ - case ADDR_IMMCOP:\ - args[0] = asR_W65_ABS8;\ - print_operand (0, " #$0", args);\ - size += 1;\ - break;\ - case ADDR_IMMTOI:\ - args[0] = X==0 ? asR_W65_ABS16 : asR_W65_ABS8;\ - print_operand (0, " #$0", args);\ - size += X==0 ? 2:1;\ - break;\ - case ADDR_ACC:\ - print_operand (0, " a", 0);\ - size += 0;\ - break;\ - case ADDR_PC_REL:\ - args[0] = asR_W65_PCR8;\ - print_operand (0, " $0", args);\ - size += 1;\ - break;\ - case ADDR_PC_REL_LONG:\ - args[0] = asR_W65_PCR16;\ - print_operand (0, " $0", args);\ - size += 2;\ - break;\ - case ADDR_IMPLIED:\ - size += 0;\ - break;\ - case ADDR_STACK:\ - size += 0;\ - break;\ - case ADDR_DIR:\ - args[0] = asR_W65_ABS8;\ - print_operand (1, " <$0", args);\ - size += 1;\ - break;\ - case ADDR_DIR_IDX_X:\ - args[0] = asR_W65_ABS8;\ - print_operand (1, " <$0,x", args);\ - size += 1;\ - break;\ - case ADDR_DIR_IDX_Y:\ - args[0] = asR_W65_ABS8;\ - print_operand (1, " <$0,y", args);\ - size += 1;\ - break;\ - case ADDR_DIR_IND:\ - args[0] = asR_W65_ABS8;\ - print_operand (1, " (<$0)", args);\ - size += 1;\ - break;\ - case ADDR_DIR_IDX_IND_X:\ - args[0] = asR_W65_ABS8;\ - print_operand (1, " (<$0,x)", args);\ - size += 1;\ - break;\ - case ADDR_DIR_IND_IDX_Y:\ - args[0] = asR_W65_ABS8;\ - print_operand (1, " (<$0),y", args);\ - size += 1;\ - break;\ - case ADDR_DIR_IND_LONG:\ - args[0] = asR_W65_ABS8;\ - print_operand (1, " [$0]", args);\ - size += 1;\ - break;\ - case ADDR_DIR_IND_IDX_Y_LONG:\ - args[0] = asR_W65_ABS8;\ - print_operand (1, " [$0],y", args);\ - size += 1;\ - break;\ - case ADDR_ABS:\ - args[0] = asR_W65_ABS16;\ - print_operand (1, " !$0", args);\ - size += 2;\ - break;\ - case ADDR_ABS_IDX_X:\ - args[0] = asR_W65_ABS16;\ - print_operand (1, " !$0,x", args);\ - size += 2;\ - break;\ - case ADDR_ABS_IDX_Y:\ - args[0] = asR_W65_ABS16;\ - print_operand (1, " !$0,y", args);\ - size += 2;\ - break;\ - case ADDR_ABS_LONG:\ - args[0] = asR_W65_ABS24;\ - print_operand (1, " >$0", args);\ - size += 3;\ - break;\ - case ADDR_ABS_IND_LONG:\ - args[0] = asR_W65_ABS16;\ - print_operand (1, " [>$0]", args);\ - size += 2;\ - break;\ - case ADDR_ABS_LONG_IDX_X:\ - args[0] = asR_W65_ABS24;\ - print_operand (1, " >$0,x", args);\ - size += 3;\ - break;\ - case ADDR_STACK_REL:\ - args[0] = asR_W65_ABS8;\ - print_operand (0, " $0,s", args);\ - size += 1;\ - break;\ - case ADDR_STACK_REL_INDX_IDX:\ - args[0] = asR_W65_ABS8;\ - print_operand (0, " ($0,s),y", args);\ - size += 1;\ - break;\ - case ADDR_ABS_IND:\ - args[0] = asR_W65_ABS16;\ - print_operand (1, " ($0)", args);\ - size += 2;\ - break;\ - case ADDR_ABS_IND_IDX:\ - args[0] = asR_W65_ABS16;\ - print_operand (1, " ($0,x)", args);\ - size += 2;\ - break;\ - case ADDR_BLOCK_MOVE:\ - args[0] = (asR_W65_ABS16 >>8) &0xff;\ - args[1] = ( asR_W65_ABS16 & 0xff);\ - print_operand (0," $0,$1",args);\ - size += 2;\ - break;\ - -#define GETINFO(size,type,pcrel)\ - case ADDR_IMMTOA: size = M==0 ? 2:1;type=M==0 ? R_W65_ABS16 : R_W65_ABS8;pcrel=0;break;\ - case ADDR_IMMCOP: size = 1;type=R_W65_ABS8;pcrel=0;break;\ - case ADDR_IMMTOI: size = X==0 ? 2:1;type=X==0 ? R_W65_ABS16 : R_W65_ABS8;pcrel=0;break;\ - case ADDR_ACC: size = 0;type=-1;pcrel=0;break;\ - case ADDR_PC_REL: size = 1;type=R_W65_PCR8;pcrel=0;break;\ - case ADDR_PC_REL_LONG: size = 2;type=R_W65_PCR16;pcrel=0;break;\ - case ADDR_IMPLIED: size = 0;type=-1;pcrel=0;break;\ - case ADDR_STACK: size = 0;type=-1;pcrel=0;break;\ - case ADDR_DIR: size = 1;type=R_W65_ABS8;pcrel=0;break;\ - case ADDR_DIR_IDX_X: size = 1;type=R_W65_ABS8;pcrel=0;break;\ - case ADDR_DIR_IDX_Y: size = 1;type=R_W65_ABS8;pcrel=0;break;\ - case ADDR_DIR_IND: size = 1;type=R_W65_ABS8;pcrel=0;break;\ - case ADDR_DIR_IDX_IND_X: size = 1;type=R_W65_ABS8;pcrel=0;break;\ - case ADDR_DIR_IND_IDX_Y: size = 1;type=R_W65_ABS8;pcrel=0;break;\ - case ADDR_DIR_IND_LONG: size = 1;type=R_W65_ABS8;pcrel=0;break;\ - case ADDR_DIR_IND_IDX_Y_LONG: size = 1;type=R_W65_ABS8;pcrel=0;break;\ - case ADDR_ABS: size = 2;type=R_W65_ABS16;pcrel=0;break;\ - case ADDR_ABS_IDX_X: size = 2;type=R_W65_ABS16;pcrel=0;break;\ - case ADDR_ABS_IDX_Y: size = 2;type=R_W65_ABS16;pcrel=0;break;\ - case ADDR_ABS_LONG: size = 3;type=R_W65_ABS24;pcrel=0;break;\ - case ADDR_ABS_IND_LONG: size = 2;type=R_W65_ABS16;pcrel=0;break;\ - case ADDR_ABS_LONG_IDX_X: size = 3;type=R_W65_ABS24;pcrel=0;break;\ - case ADDR_STACK_REL: size = 1;type=R_W65_ABS8;pcrel=0;break;\ - case ADDR_STACK_REL_INDX_IDX: size = 1;type=R_W65_ABS8;pcrel=0;break;\ - case ADDR_ABS_IND: size = 2;type=R_W65_ABS16;pcrel=0;break;\ - case ADDR_ABS_IND_IDX: size = 2;type=R_W65_ABS16;pcrel=0;break;\ - case ADDR_BLOCK_MOVE: size = 2;type=-1;pcrel=0;break;\ - diff --git a/opcodes/z8k-dis.c b/opcodes/z8k-dis.c deleted file mode 100644 index 858d5a2102e..00000000000 --- a/opcodes/z8k-dis.c +++ /dev/null @@ -1,569 +0,0 @@ -/* -This file is part of GNU Binutils. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ - -#include <ansidecl.h> -#include "sysdep.h" -#include "dis-asm.h" - -#define DEFINE_TABLE -#include "z8k-opc.h" - - -#include <setjmp.h> - - -typedef struct -{ - /* These are all indexed by nibble number (i.e only every other entry - of bytes is used, and every 4th entry of words). */ - unsigned char nibbles[24]; - unsigned char bytes[24]; - unsigned short words[24]; - - /* Nibble number of first word not yet fetched. */ - int max_fetched; - bfd_vma insn_start; - jmp_buf bailout; - - long tabl_index; - char instr_asmsrc[80]; - unsigned long arg_reg[0x0f]; - unsigned long immediate; - unsigned long displacement; - unsigned long address; - unsigned long cond_code; - unsigned long ctrl_code; - unsigned long flags; - unsigned long interrupts; -} -instr_data_s; - -/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) - to ADDR (exclusive) are valid. Returns 1 for success, longjmps - on error. */ -#define FETCH_DATA(info, nibble) \ - ((nibble) <= ((instr_data_s *)(info->private_data))->max_fetched \ - ? 1 : fetch_data ((info), (nibble))) - -static int -fetch_data (info, nibble) - struct disassemble_info *info; - int nibble; -{ - unsigned char mybuf[20]; - int status; - instr_data_s *priv = (instr_data_s *)info->private_data; - bfd_vma start = priv->insn_start + priv->max_fetched / 2; - - if ((nibble % 4) != 0) - abort (); - status = (*info->read_memory_func) (start, - (bfd_byte *) mybuf, - (nibble - priv->max_fetched) / 2, - info); - if (status != 0) - { - (*info->memory_error_func) (status, start, info); - longjmp (priv->bailout, 1); - } - - { - int i; - char *p = mybuf + priv->max_fetched / 2; - - for (i = priv->max_fetched; i < nibble;) - { - priv->words[i] = (p[0] << 8) | p[1]; - - priv->bytes[i] = *p; - priv->nibbles[i++] = *p >> 4; - priv->nibbles[i++] = *p &0xf; - - ++p; - priv->bytes[i] = *p; - priv->nibbles[i++] = *p >> 4; - priv->nibbles[i++] = *p & 0xf; - - ++p; - } - } - priv->max_fetched = nibble; - return 1; -} - -static char *codes[16] = -{ - "f", - "lt", - "le", - "ule", - "ov/pe", - "mi", - "eq", - "c/ult", - "t", - "ge", - "gt", - "ugt", - "nov/po", - "pl", - "ne", - "nc/uge" -}; - -int z8k_lookup_instr PARAMS ((unsigned char*, disassemble_info *)); -static void output_instr - PARAMS ((instr_data_s *, unsigned long, disassemble_info *)); -static void unpack_instr PARAMS ((instr_data_s *, int, disassemble_info *)); -static void unparse_instr PARAMS ((instr_data_s *)); - -static int -print_insn_z8k (addr, info, is_segmented) - unsigned long addr; - disassemble_info *info; - int is_segmented; -{ - instr_data_s instr_data; - - info->private_data = (PTR) &instr_data; - instr_data.max_fetched = 0; - instr_data.insn_start = addr; - if (setjmp (instr_data.bailout) != 0) - /* Error return. */ - return -1; - - instr_data.tabl_index = z8k_lookup_instr (instr_data.nibbles, info); - if (instr_data.tabl_index > 0) - { - unpack_instr (&instr_data, is_segmented, info); - unparse_instr (&instr_data); - output_instr (&instr_data, addr, info); - return z8k_table[instr_data.tabl_index].length; - } - else - { - FETCH_DATA (info, 4); - (*info->fprintf_func) (info->stream, ".word %02x%02x", - instr_data.bytes[0], instr_data.bytes[2]); - return 2; - } -} - -print_insn_z8001 (addr, info) - unsigned long addr; - disassemble_info *info; -{ - return print_insn_z8k (addr, info, 1); -} - -print_insn_z8002 (addr, info) - unsigned long addr; - disassemble_info *info; -{ - return print_insn_z8k (addr, info, 0); -} - -int -z8k_lookup_instr (nibbles, info) - unsigned char *nibbles; - disassemble_info *info; -{ - - int nibl_index, tabl_index; - int nibl_matched; - unsigned short instr_nibl; - unsigned short tabl_datum, datum_class, datum_value; - - nibl_matched = 0; - tabl_index = 0; - while (!nibl_matched && z8k_table[tabl_index].name) - { - nibl_matched = 1; - for (nibl_index = 0; nibl_index < z8k_table[tabl_index].length * 2 && nibl_matched; nibl_index++) - { - if ((nibl_index % 4) == 0) - /* Fetch one word at a time. */ - FETCH_DATA (info, nibl_index + 4); - instr_nibl = nibbles[nibl_index]; - - tabl_datum = z8k_table[tabl_index].byte_info[nibl_index]; - datum_class = tabl_datum & CLASS_MASK; - datum_value = ~CLASS_MASK & tabl_datum; - - switch (datum_class) - { - case CLASS_BIT: - if (datum_value != instr_nibl) - nibl_matched = 0; - break; - case CLASS_00II: - if (!((~instr_nibl) & 0x4)) - nibl_matched = 0; - break; - case CLASS_01II: - if (!(instr_nibl & 0x4)) - nibl_matched = 0; - break; - case CLASS_0CCC: - if (!((~instr_nibl) & 0x8)) - nibl_matched = 0; - break; - case CLASS_1CCC: - if (!(instr_nibl & 0x8)) - nibl_matched = 0; - break; - case CLASS_0DISP7: - if (!((~instr_nibl) & 0x8)) - nibl_matched = 0; - nibl_index += 1; - break; - case CLASS_1DISP7: - if (!(instr_nibl & 0x8)) - nibl_matched = 0; - nibl_index += 1; - break; - case CLASS_REGN0: - if (instr_nibl == 0) - nibl_matched = 0; - break; - case CLASS_BIT_1OR2: - if ((instr_nibl | 0x2) != (datum_value | 0x2)) - nibl_matched = 0; - break; - default: - break; - } - } - if (nibl_matched) - { - return tabl_index; - } - - tabl_index++; - } - return -1; - -} - -static void -output_instr (instr_data, addr, info) - instr_data_s *instr_data; - unsigned long addr; - disassemble_info *info; -{ - int loop, loop_limit; - char tmp_str[20]; - char out_str[100]; - - strcpy (out_str, "\t"); - - loop_limit = z8k_table[instr_data->tabl_index].length * 2; - FETCH_DATA (info, loop_limit); - for (loop = 0; loop < loop_limit; loop++) - { - sprintf (tmp_str, "%x", instr_data->nibbles[loop]); - strcat (out_str, tmp_str); - } - - while (loop++ < 8) - { - strcat (out_str, " "); - } - - strcat (out_str, instr_data->instr_asmsrc); - - (*info->fprintf_func) (info->stream, "%s", out_str); -} - -static void -unpack_instr (instr_data, is_segmented, info) - instr_data_s *instr_data; - int is_segmented; - disassemble_info *info; -{ - int nibl_count, loop; - unsigned short instr_nibl, instr_byte, instr_word; - long instr_long; - unsigned short tabl_datum, datum_class, datum_value; - - nibl_count = 0; - loop = 0; - while (z8k_table[instr_data->tabl_index].byte_info[loop] != 0) - { - FETCH_DATA (info, nibl_count + 4 - (nibl_count % 4)); - instr_nibl = instr_data->nibbles[nibl_count]; - instr_byte = instr_data->bytes[nibl_count]; - instr_word = instr_data->words[nibl_count]; - - tabl_datum = z8k_table[instr_data->tabl_index].byte_info[loop]; - datum_class = tabl_datum & CLASS_MASK; - datum_value = tabl_datum & ~CLASS_MASK; - - switch (datum_class) - { - case CLASS_X: - instr_data->address = instr_nibl; - break; - case CLASS_BA: - instr_data->displacement = instr_nibl; - break; - case CLASS_BX: - instr_data->arg_reg[datum_value] = instr_nibl; - break; - case CLASS_DISP: - switch (datum_value) - { - case ARG_DISP16: - instr_data->displacement = instr_word; - nibl_count += 3; - break; - case ARG_DISP12: - instr_data->displacement = instr_word & 0x0fff; - nibl_count += 2; - break; - default: - break; - } - break; - case CLASS_IMM: - switch (datum_value) - { - case ARG_IMM4: - instr_data->immediate = instr_nibl; - break; - case ARG_NIM8: - instr_data->immediate = (-instr_byte); - nibl_count += 1; - break; - case ARG_IMM8: - instr_data->immediate = instr_byte; - nibl_count += 1; - break; - case ARG_IMM16: - instr_data->immediate = instr_word; - nibl_count += 3; - break; - case ARG_IMM32: - FETCH_DATA (info, nibl_count + 8); - instr_long = (instr_data->words[nibl_count] << 16) - | (instr_data->words[nibl_count + 4]); - instr_data->immediate = instr_long; - nibl_count += 7; - break; - case ARG_IMMN: - instr_data->immediate = instr_nibl - 1; - break; - /* ????? */ - /* missing ARG_IMMNMINUS1 */ - case ARG_IMM_1: - instr_data->immediate = 1; - break; - case ARG_IMM_2: - instr_data->immediate = 2; - break; - case ARG_IMM2: - instr_data->immediate = instr_nibl & 0x3; - break; - default: - break; - } - break; - case CLASS_CC: - instr_data->cond_code = instr_nibl; - break; - case CLASS_CTRL: - instr_data->ctrl_code = instr_nibl; - break; - case CLASS_DA: - case CLASS_ADDRESS: - if (is_segmented) - { - if (instr_nibl & 0x8) - { - FETCH_DATA (info, nibl_count + 8); - instr_long = (instr_data->words[nibl_count] << 16) - | (instr_data->words[nibl_count + 4]); - instr_data->address = ((instr_word & 0x7f00) << 8) + - (instr_long & 0xffff); - nibl_count += 7; - } - else - { - instr_data->address = ((instr_word & 0x7f00) << 8) + - (instr_word & 0x00ff); - nibl_count += 3; - } - } - else - { - instr_data->address = instr_word; - nibl_count += 3; - } - break; - case CLASS_0CCC: - instr_data->cond_code = instr_nibl & 0x7; - break; - case CLASS_1CCC: - instr_data->cond_code = instr_nibl & 0x7; - break; - case CLASS_0DISP7: - instr_data->displacement = instr_byte & 0x7f; - nibl_count += 1; - break; - case CLASS_1DISP7: - instr_data->displacement = instr_byte & 0x7f; - nibl_count += 1; - break; - case CLASS_01II: - instr_data->interrupts = instr_nibl & 0x3; - break; - case CLASS_00II: - instr_data->interrupts = instr_nibl & 0x3; - break; - case CLASS_BIT: - /* do nothing */ - break; - case CLASS_IR: - instr_data->arg_reg[datum_value] = instr_nibl; - break; - case CLASS_FLAGS: - instr_data->flags = instr_nibl; - break; - case CLASS_REG: - instr_data->arg_reg[datum_value] = instr_nibl; - break; - case CLASS_REG_BYTE: - instr_data->arg_reg[datum_value] = instr_nibl; - break; - case CLASS_REG_WORD: - instr_data->arg_reg[datum_value] = instr_nibl; - break; - case CLASS_REG_QUAD: - instr_data->arg_reg[datum_value] = instr_nibl; - break; - case CLASS_REG_LONG: - instr_data->arg_reg[datum_value] = instr_nibl; - break; - case CLASS_REGN0: - instr_data->arg_reg[datum_value] = instr_nibl; - break; - default: - break; - } - - loop += 1; - nibl_count += 1; - } -} - -static void -unparse_instr (instr_data) - instr_data_s *instr_data; -{ - unsigned short tabl_datum, datum_class, datum_value; - int loop, loop_limit; - char out_str[80], tmp_str[25]; - - sprintf (out_str, "\t%s\t", z8k_table[instr_data->tabl_index].name); - - loop_limit = z8k_table[instr_data->tabl_index].noperands; - for (loop = 0; loop < loop_limit; loop++) - { - if (loop) - strcat (out_str, ","); - - tabl_datum = z8k_table[instr_data->tabl_index].arg_info[loop]; - datum_class = tabl_datum & CLASS_MASK; - datum_value = tabl_datum & ~CLASS_MASK; - - switch (datum_class) - { - case CLASS_X: - sprintf (tmp_str, "0x%0x(R%d)", instr_data->address, - instr_data->arg_reg[datum_value]); - strcat (out_str, tmp_str); - break; - case CLASS_BA: - sprintf (tmp_str, "r%d(#%x)", instr_data->arg_reg[datum_value], - instr_data->immediate); - strcat (out_str, tmp_str); - break; - case CLASS_BX: - sprintf (tmp_str, "r%d(R%d)", instr_data->arg_reg[datum_value], - instr_data->arg_reg[ARG_RX]); - strcat (out_str, tmp_str); - break; - case CLASS_DISP: - sprintf (tmp_str, "#0x%0x", instr_data->displacement); - strcat (out_str, tmp_str); - break; - case CLASS_IMM: - sprintf (tmp_str, "#0x%0x", instr_data->immediate); - strcat (out_str, tmp_str); - break; - case CLASS_CC: - sprintf (tmp_str, "%s", codes[instr_data->cond_code]); - strcat (out_str, tmp_str); - break; - case CLASS_CTRL: - sprintf (tmp_str, "0x%0x", instr_data->ctrl_code); - strcat (out_str, tmp_str); - break; - case CLASS_DA: - case CLASS_ADDRESS: - sprintf (tmp_str, "#0x%0x", instr_data->address); - strcat (out_str, tmp_str); - break; - case CLASS_IR: - sprintf (tmp_str, "@R%d", instr_data->arg_reg[datum_value]); - strcat (out_str, tmp_str); - break; - case CLASS_FLAGS: - sprintf (tmp_str, "0x%0x", instr_data->flags); - strcat (out_str, tmp_str); - break; - case CLASS_REG_BYTE: - if (instr_data->arg_reg[datum_value] >= 0x8) - { - sprintf (tmp_str, "rl%d", - instr_data->arg_reg[datum_value] - 0x8); - } - else - { - sprintf (tmp_str, "rh%d", instr_data->arg_reg[datum_value]); - } - strcat (out_str, tmp_str); - break; - case CLASS_REG_WORD: - sprintf (tmp_str, "r%d", instr_data->arg_reg[datum_value]); - strcat (out_str, tmp_str); - break; - case CLASS_REG_QUAD: - sprintf (tmp_str, "rq%d", instr_data->arg_reg[datum_value]); - strcat (out_str, tmp_str); - break; - case CLASS_REG_LONG: - sprintf (tmp_str, "rr%d", instr_data->arg_reg[datum_value]); - strcat (out_str, tmp_str); - break; - default: - break; - } - } - - strcpy (instr_data->instr_asmsrc, out_str); -} diff --git a/opcodes/z8k-opc.h b/opcodes/z8k-opc.h deleted file mode 100644 index 62eec3522a2..00000000000 --- a/opcodes/z8k-opc.h +++ /dev/null @@ -1,867 +0,0 @@ - /* THIS FILE IS AUTOMAGICALLY GENERATED, DON'T EDIT IT */ -#define ARG_MASK 0x0f -#define ARG_RS 0x01 -#define ARG_RD 0x02 -#define ARG_RA 0x03 -#define ARG_RB 0x04 -#define ARG_RR 0x05 -#define ARG_RX 0x06 -#define ARG_IMM4 0x01 -#define ARG_IMM8 0x02 -#define ARG_IMM16 0x03 -#define ARG_IMM32 0x04 -#define ARG_IMMN 0x05 -#define ARG_IMMNMINUS1 0x05 -#define ARG_IMM_1 0x06 -#define ARG_IMM_2 0x07 -#define ARG_DISP16 0x08 -#define ARG_NIM16 0x09 -#define ARG_IMM2 0x0a -#define ARG_DISP12 0x0b -#define ARG_DISP8 0x0c -#define CLASS_MASK 0xfff0 -#define CLASS_X 0x10 -#define CLASS_BA 0x20 -#define CLASS_DA 0x30 -#define CLASS_BX 0x40 -#define CLASS_DISP 0x50 -#define CLASS_IMM 0x60 -#define CLASS_CC 0x70 -#define CLASS_CTRL 0x80 -#define CLASS_ADDRESS 0xd0 -#define CLASS_0CCC 0xe0 -#define CLASS_1CCC 0xf0 -#define CLASS_0DISP7 0x100 -#define CLASS_1DISP7 0x200 -#define CLASS_01II 0x300 -#define CLASS_00II 0x400 -#define CLASS_BIT 0x500 -#define CLASS_FLAGS 0x600 -#define CLASS_IR 0x700 -#define CLASS_DISP8 0x800 -#define CLASS_REG 0x7000 -#define CLASS_REG_BYTE 0x2000 -#define CLASS_REG_WORD 0x3000 -#define CLASS_REG_QUAD 0x4000 -#define CLASS_REG_LONG 0x5000 -#define CLASS_REGN0 0x8000 -typedef struct { -char *name; -unsigned short arg_info[4]; -unsigned short byte_info[10]; -int noperands; -int length; -int idx; -} opcode_entry_type; -#ifdef DEFINE_TABLE -opcode_entry_type z8k_table[] = { -{"adc",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+11,CLASS_BIT+5,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,0}, -{"adcb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+11,CLASS_BIT+4,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,1}, -{"add",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,2}, -{"add",{CLASS_REG_WORD+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+4,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,3}, -{"add",{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,4}, -{"add",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,5}, -{"add",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+1,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,6}, -{"addb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,7}, -{"addb",{CLASS_REG_BYTE+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+4,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,8}, -{"addb",{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,9}, -{"addb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,10}, -{"addb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,11}, -{"addl",{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,12}, -{"addl",{CLASS_REG_LONG+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+5,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,13}, -{"addl",{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,14}, -{"addl",{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, - {CLASS_BIT+1,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,15}, -{"addl",{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+6,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,16}, -{"and",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,17}, -{"and",{CLASS_REG_WORD+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+4,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,18}, -{"and",{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,19}, -{"and",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,20}, -{"and",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+7,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,21}, -{"andb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,22}, -{"andb",{CLASS_REG_BYTE+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+4,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,23}, -{"andb",{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,24}, -{"andb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,25}, -{"andb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+6,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,26}, -{"bit",{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,27}, -{"bit",{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,28}, -{"bit",{CLASS_DA,CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+7,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,29}, -{"bit",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+10,CLASS_BIT+7,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,30}, -{"bit",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,31}, -{"bitb",{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+6,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,32}, -{"bitb",{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+6,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,33}, -{"bitb",{CLASS_DA,CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+6,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,34}, -{"bitb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+10,CLASS_BIT+6,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,35}, -{"bitb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,36}, -{"call",{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+1,CLASS_BIT+15,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,37}, -{"call",{CLASS_DA,}, - {CLASS_BIT+5,CLASS_BIT+15,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS,0,0,0,0,},1,4,38}, -{"call",{CLASS_X+(ARG_RD),}, - {CLASS_BIT+5,CLASS_BIT+15,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS,0,0,0,0,},1,4,39}, -{"calr",{CLASS_DISP,}, - {CLASS_BIT+13,CLASS_DISP+(ARG_DISP12),0,0,0,0,0,0,0,},1,2,40}, -{"clr",{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,41}, -{"clr",{CLASS_DA,}, - {CLASS_BIT+4,CLASS_BIT+13,CLASS_BIT+0,CLASS_BIT+8,0,0,0,0,0,},1,2,42}, -{"clr",{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,43}, -{"clr",{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+13,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,44}, -{"clrb",{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,45}, -{"clrb",{CLASS_DA,}, - {CLASS_BIT+4,CLASS_BIT+12,CLASS_BIT+0,CLASS_BIT+8,0,0,0,0,0,},1,2,46}, -{"clrb",{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,47}, -{"clrb",{CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+12,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,48}, -{"com",{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,49}, -{"com",{CLASS_DA,}, - {CLASS_BIT+4,CLASS_BIT+13,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},1,2,50}, -{"com",{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,51}, -{"com",{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+13,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,52}, -{"comb",{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,53}, -{"comb",{CLASS_DA,}, - {CLASS_BIT+4,CLASS_BIT+12,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},1,2,54}, -{"comb",{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,55}, -{"comb",{CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+12,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,56}, -{"comflg",{CLASS_FLAGS,}, - {CLASS_BIT+8,CLASS_BIT+13,CLASS_IMM+(ARG_IMM4),CLASS_BIT+5,0,0,0,0,0,},1,2,57}, -{"cp",{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,58}, -{"cp",{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+4,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_ADDRESS,CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,59}, -{"cp",{CLASS_DA,CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+4,CLASS_BIT+13,CLASS_BIT+0,CLASS_BIT+1,CLASS_ADDRESS,CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,60}, -{"cp",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,61}, -{"cp",{CLASS_REG_WORD+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+4,CLASS_BIT+11,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,62}, -{"cp",{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,63}, -{"cp",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+11,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,64}, -{"cp",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+11,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,65}, -{"cpb",{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,66}, -{"cpb",{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+4,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_ADDRESS,CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,67}, -{"cpb",{CLASS_DA,CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+4,CLASS_BIT+12,CLASS_BIT+0,CLASS_BIT+1,CLASS_ADDRESS,CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,68}, -{"cpb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,69}, -{"cpb",{CLASS_REG_BYTE+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+4,CLASS_BIT+10,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,70}, -{"cpb",{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,71}, -{"cpb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+10,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,72}, -{"cpb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+10,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,73}, -{"cpd",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+11,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,74}, -{"cpdb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+11,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,75}, -{"cpdr",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+11,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+12,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,76}, -{"cpdrb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+11,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+12,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,77}, -{"cpi",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+11,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,78}, -{"cpib",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+11,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,79}, -{"cpir",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+11,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,80}, -{"cpirb",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+11,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,81}, -{"cpl",{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,82}, -{"cpl",{CLASS_REG_LONG+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+5,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,83}, -{"cpl",{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,84}, -{"cpl",{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, - {CLASS_BIT+1,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,85}, -{"cpl",{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,86}, -{"cpsd",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+11,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+10,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,87}, -{"cpsdb",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+11,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+10,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,88}, -{"cpsdr",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+11,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+14,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,89}, -{"cpsdrb",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+11,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+14,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,90}, -{"cpsi",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+11,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,91}, -{"cpsib",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+11,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,92}, -{"cpsir",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+11,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,93}, -{"cpsirb",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+11,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,94}, -{"dab",{CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+11,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,95}, -{"dbjnz",{CLASS_REG_BYTE+(ARG_RD),CLASS_DISP,}, - {CLASS_BIT+15,CLASS_REG+(ARG_RD),CLASS_1DISP7,0,0,0,0,0,0,},2,2,96}, -{"dec",{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+11,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,97}, -{"dec",{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+11,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,98}, -{"dec",{CLASS_DA,CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+11,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,99}, -{"dec",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+10,CLASS_BIT+11,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,100}, -{"decb",{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+10,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,101}, -{"decb",{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+10,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,102}, -{"decb",{CLASS_DA,CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+10,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,103}, -{"decb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+10,CLASS_BIT+10,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,104}, -{"di",{CLASS_IMM+(ARG_IMM2),}, - {CLASS_BIT+7,CLASS_BIT+12,CLASS_BIT+0,CLASS_00II,0,0,0,0,0,},1,2,105}, -{"div",{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,106}, -{"div",{CLASS_REG_LONG+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+5,CLASS_BIT+11,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,107}, -{"div",{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,108}, -{"div",{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+1,CLASS_BIT+11,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,109}, -{"div",{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+11,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,110}, -{"divl",{CLASS_REG_QUAD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,111}, -{"divl",{CLASS_REG_QUAD+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+5,CLASS_BIT+10,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,112}, -{"divl",{CLASS_REG_QUAD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,113}, -{"divl",{CLASS_REG_QUAD+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, - {CLASS_BIT+1,CLASS_BIT+10,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,114}, -{"divl",{CLASS_REG_QUAD+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+10,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,115}, -{"djnz",{CLASS_REG_WORD+(ARG_RD),CLASS_DISP,}, - {CLASS_BIT+15,CLASS_REG+(ARG_RD),CLASS_0DISP7,0,0,0,0,0,0,},2,2,116}, -{"ei",{CLASS_IMM+(ARG_IMM2),}, - {CLASS_BIT+7,CLASS_BIT+12,CLASS_BIT+0,CLASS_01II,0,0,0,0,0,},1,2,117}, -{"ex",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+10,CLASS_BIT+13,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,118}, -{"ex",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+13,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,119}, -{"ex",{CLASS_REG_WORD+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+6,CLASS_BIT+13,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,120}, -{"ex",{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+13,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,121}, -{"exb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,122}, -{"exb",{CLASS_REG_BYTE+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+6,CLASS_BIT+12,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,123}, -{"exb",{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,124}, -{"exb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+10,CLASS_BIT+12,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,125}, -{"exts",{CLASS_REG_LONG+(ARG_RD),}, - {CLASS_BIT+11,CLASS_BIT+1,CLASS_REG+(ARG_RD),CLASS_BIT+10,0,0,0,0,0,},1,2,126}, -{"extsb",{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+11,CLASS_BIT+1,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,127}, -{"extsl",{CLASS_REG_QUAD+(ARG_RD),}, - {CLASS_BIT+11,CLASS_BIT+1,CLASS_REG+(ARG_RD),CLASS_BIT+7,0,0,0,0,0,},1,2,128}, -{"halt",{0}, - {CLASS_BIT+7,CLASS_BIT+10,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},0,2,129}, -{"in",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+13,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,130}, -{"in",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+3,CLASS_BIT+13,CLASS_REG+(ARG_RD),CLASS_BIT+4,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,131}, -{"inb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,132}, -{"inb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+3,CLASS_BIT+12,CLASS_REG+(ARG_RD),CLASS_BIT+4,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,133}, -{"inc",{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+9,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,134}, -{"inc",{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+9,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,135}, -{"inc",{CLASS_DA,CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+9,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,136}, -{"inc",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+10,CLASS_BIT+9,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,137}, -{"incb",{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,138}, -{"incb",{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,139}, -{"incb",{CLASS_DA,CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+8,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,140}, -{"incb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+10,CLASS_BIT+8,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,141}, -{"ind",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,142}, -{"indb",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,143}, -{"inib",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,144}, -{"inibr",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,145}, -{"iret",{0}, - {CLASS_BIT+7,CLASS_BIT+11,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},0,2,146}, -{"jp",{CLASS_CC,CLASS_IR+(ARG_RD),}, - {CLASS_BIT+1,CLASS_BIT+14,CLASS_REGN0+(ARG_RD),CLASS_CC,0,0,0,0,0,},2,2,147}, -{"jp",{CLASS_CC,CLASS_DA,}, - {CLASS_BIT+5,CLASS_BIT+14,CLASS_BIT+0,CLASS_CC,CLASS_ADDRESS,0,0,0,0,},2,4,148}, -{"jp",{CLASS_CC,CLASS_X+(ARG_RD),}, - {CLASS_BIT+5,CLASS_BIT+14,CLASS_REGN0+(ARG_RD),CLASS_CC,CLASS_ADDRESS,0,0,0,0,},2,4,149}, -{"jr",{CLASS_CC,CLASS_DISP,}, - {CLASS_BIT+14,CLASS_CC,CLASS_DISP8,0,0,0,0,0,0,},2,2,150}, -{"ld",{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,151}, -{"ld",{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+15,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,152}, -{"ld",{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+4,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_ADDRESS,CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,153}, -{"ld",{CLASS_X+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+15,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_ADDRESS,0,0,0,0,},2,4,154}, -{"ld",{CLASS_DA,CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+4,CLASS_BIT+13,CLASS_BIT+0,CLASS_BIT+5,CLASS_ADDRESS,CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,155}, -{"ld",{CLASS_DA,CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+15,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_ADDRESS,0,0,0,0,},2,4,156}, -{"ld",{CLASS_BA+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,157}, -{"ld",{CLASS_BX+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REGN0+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,158}, -{"ld",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,159}, -{"ld",{CLASS_REG_WORD+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+6,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,160}, -{"ld",{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,161}, -{"ld",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+2,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,162}, -{"ld",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+10,CLASS_BIT+1,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,163}, -{"ld",{CLASS_REG_WORD+(ARG_RD),CLASS_BA+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,164}, -{"ld",{CLASS_REG_WORD+(ARG_RD),CLASS_BX+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REGN0+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,165}, -{"lda",{CLASS_REG_WORD+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+7,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,166}, -{"lda",{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,167}, -{"lda",{CLASS_REG_WORD+(ARG_RD),CLASS_BA+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,168}, -{"lda",{CLASS_REG_WORD+(ARG_RD),CLASS_BX+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REGN0+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,169}, -{"ldar",{CLASS_REG_WORD+(ARG_RD),CLASS_DISP,}, - {CLASS_BIT+3,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,170}, -{"ldb",{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,171}, -{"ldb",{CLASS_IR+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+14,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,172}, -{"ldb",{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+4,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_ADDRESS,CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,173}, -{"ldb",{CLASS_X+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+14,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_ADDRESS,0,0,0,0,},2,4,174}, -{"ldb",{CLASS_DA,CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+4,CLASS_BIT+12,CLASS_BIT+0,CLASS_BIT+5,CLASS_ADDRESS,CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,175}, -{"ldb",{CLASS_DA,CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+14,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_ADDRESS,0,0,0,0,},2,4,176}, -{"ldb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,177}, -{"ldb",{CLASS_REG_BYTE+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+6,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,178}, -{"ldb",{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,179}, -{"ldb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+12,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},2,2,180}, -{"ldb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+2,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,181}, -{"ldb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+10,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,181}, -{"ldb",{CLASS_REG_BYTE+(ARG_RD),CLASS_BA+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,182}, -{"ldb",{CLASS_REG_BYTE+(ARG_RD),CLASS_BX+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REGN0+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,183}, -{"ldb",{CLASS_BA+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,184}, -{"ldb",{CLASS_BX+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REGN0+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,185}, -{"ldctl",{CLASS_CTRL,CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+13,CLASS_REG+(ARG_RS),CLASS_1CCC,0,0,0,0,0,},2,2,186}, -{"ldctl",{CLASS_REG_WORD+(ARG_RD),CLASS_CTRL,}, - {CLASS_BIT+7,CLASS_BIT+13,CLASS_REG+(ARG_RD),CLASS_0CCC,0,0,0,0,0,},2,2,187}, -{"ldir",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+11,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,188}, -{"ldirb",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+11,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,189}, -{"ldk",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+11,CLASS_BIT+13,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,190}, -{"ldl",{CLASS_IR+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,191}, -{"ldl",{CLASS_X+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_ADDRESS,0,0,0,0,},2,4,192}, -{"ldl",{CLASS_DA,CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+13,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_ADDRESS,0,0,0,0,},2,4,193}, -{"ldl",{CLASS_BA+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,194}, -{"ldl",{CLASS_BX+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REGN0+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,195}, -{"ldl",{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,196}, -{"ldl",{CLASS_REG_LONG+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+5,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,197}, -{"ldl",{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,198}, -{"ldl",{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, - {CLASS_BIT+1,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,199}, -{"ldl",{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+4,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,200}, -{"ldl",{CLASS_REG_LONG+(ARG_RD),CLASS_BA+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,201}, -{"ldl",{CLASS_REG_LONG+(ARG_RD),CLASS_BX+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REGN0+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,202}, -{"ldm",{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMMN),}, - {CLASS_BIT+1,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),0,},3,4,203}, -{"ldm",{CLASS_X+(ARG_RD),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMMN),}, - {CLASS_BIT+5,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),CLASS_ADDRESS,},3,6,204}, -{"ldm",{CLASS_DA,CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMMN),}, - {CLASS_BIT+5,CLASS_BIT+12,CLASS_BIT+0,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),CLASS_ADDRESS,},3,6,205}, -{"ldm",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_IMM + (ARG_IMMN),}, - {CLASS_BIT+1,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),0,},3,4,206}, -{"ldm",{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),CLASS_IMM + (ARG_IMMN),}, - {CLASS_BIT+5,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),CLASS_ADDRESS,},3,6,207}, -{"ldm",{CLASS_REG_WORD+(ARG_RD),CLASS_DA,CLASS_IMM + (ARG_IMMN),}, - {CLASS_BIT+5,CLASS_BIT+12,CLASS_BIT+0,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),CLASS_ADDRESS,},3,6,208}, -{"ldps",{CLASS_IR+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,0,0,0,0,},1,2,209}, -{"ldps",{CLASS_DA,}, - {CLASS_BIT+7,CLASS_BIT+9,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS,0,0,0,0,},1,4,210}, -{"ldps",{CLASS_X+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_ADDRESS,0,0,0,0,},1,4,211}, -{"ldr",{CLASS_DISP,CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,212}, -{"ldr",{CLASS_REG_WORD+(ARG_RD),CLASS_DISP,}, - {CLASS_BIT+3,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,213}, -{"ldrb",{CLASS_DISP,CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,214}, -{"ldrb",{CLASS_REG_BYTE+(ARG_RD),CLASS_DISP,}, - {CLASS_BIT+3,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,215}, -{"ldrl",{CLASS_DISP,CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,216}, -{"ldrl",{CLASS_REG_LONG+(ARG_RD),CLASS_DISP,}, - {CLASS_BIT+3,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,217}, -{"mbit",{0}, - {CLASS_BIT+7,CLASS_BIT+11,CLASS_BIT+0,CLASS_BIT+10,0,0,0,0,0,},0,2,218}, -{"mreq",{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+7,CLASS_BIT+11,CLASS_REG+(ARG_RD),CLASS_BIT+13,0,0,0,0,0,},1,2,219}, -{"mres",{0}, - {CLASS_BIT+7,CLASS_BIT+11,CLASS_BIT+0,CLASS_BIT+9,0,0,0,0,0,},0,2,220}, -{"mset",{0}, - {CLASS_BIT+7,CLASS_BIT+11,CLASS_BIT+0,CLASS_BIT+8,0,0,0,0,0,},0,2,221}, -{"mult",{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,222}, -{"mult",{CLASS_REG_LONG+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+5,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,223}, -{"mult",{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,224}, -{"mult",{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+1,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,225}, -{"mult",{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+9,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,226}, -{"multl",{CLASS_REG_QUAD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,227}, -{"multl",{CLASS_REG_QUAD+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+5,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,228}, -{"multl",{CLASS_REG_QUAD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,229}, -{"multl",{CLASS_REG_QUAD+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, - {CLASS_BIT+1,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,230}, -{"multl",{CLASS_REG_QUAD+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+8,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,231}, -{"neg",{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,232}, -{"neg",{CLASS_DA,}, - {CLASS_BIT+4,CLASS_BIT+13,CLASS_BIT+0,CLASS_BIT+2,0,0,0,0,0,},1,2,233}, -{"neg",{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,234}, -{"neg",{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+13,CLASS_REG+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,235}, -{"negb",{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,236}, -{"negb",{CLASS_DA,}, - {CLASS_BIT+4,CLASS_BIT+12,CLASS_BIT+0,CLASS_BIT+2,0,0,0,0,0,},1,2,237}, -{"negb",{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,238}, -{"negb",{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+12,CLASS_REG+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,239}, -{"nop",{0}, - {CLASS_BIT+8,CLASS_BIT+13,CLASS_BIT+0,CLASS_BIT+7,0,0,0,0,0,},0,2,240}, -{"or",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,241}, -{"or",{CLASS_REG_WORD+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+4,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,242}, -{"or",{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,243}, -{"or",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,244}, -{"or",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+5,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,245}, -{"orb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,246}, -{"orb",{CLASS_REG_BYTE+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+4,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,247}, -{"orb",{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,248}, -{"orb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,249}, -{"orb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+4,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,250}, -{"out",{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+15,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,251}, -{"out",{CLASS_IMM+(ARG_IMM16),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+11,CLASS_REG+(ARG_RS),CLASS_BIT+6,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,252}, -{"outb",{CLASS_IR+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+14,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,253}, -{"outb",{CLASS_IMM+(ARG_IMM16),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+10,CLASS_REG+(ARG_RS),CLASS_BIT+6,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,254}, -{"outd",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+10,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,255}, -{"outdb",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+10,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,256}, -{"outib",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,257}, -{"outibr",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,258}, -{"pop",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),0,0,0,0,0,},2,2,259}, -{"pop",{CLASS_X+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,260}, -{"pop",{CLASS_DA,CLASS_IR+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_ADDRESS,0,0,0,0,},2,4,261}, -{"pop",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,262}, -{"popl",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),0,0,0,0,0,},2,2,263}, -{"popl",{CLASS_X+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,264}, -{"popl",{CLASS_DA,CLASS_IR+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_ADDRESS,0,0,0,0,},2,4,265}, -{"popl",{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,266}, -{"push",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),0,0,0,0,0,},2,2,267}, -{"push",{CLASS_IR+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+5,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS,0,0,0,0,},2,4,268}, -{"push",{CLASS_IR+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+5,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS,0,0,0,0,},2,4,269}, -{"push",{CLASS_IR+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),CLASS_ADDRESS,0,0,0,0,},2,4,269}, -{"push",{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,270}, -{"push",{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,271}, -{"pushl",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),0,0,0,0,0,},2,2,272}, -{"pushl",{CLASS_IR+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),CLASS_ADDRESS,0,0,0,0,},2,4,273}, -{"pushl",{CLASS_IR+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,274}, -{"res",{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,275}, -{"res",{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,276}, -{"res",{CLASS_DA,CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+3,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,277}, -{"res",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+10,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,278}, -{"res",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,279}, -{"resb",{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,280}, -{"resb",{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,281}, -{"resb",{CLASS_DA,CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+2,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,282}, -{"resb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+10,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,283}, -{"resb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,284}, -{"resflg",{CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+8,CLASS_BIT+13,CLASS_IMM+(ARG_IMM4),CLASS_BIT+3,0,0,0,0,0,},1,2,285}, -{"ret",{CLASS_CC,}, - {CLASS_BIT+9,CLASS_BIT+14,CLASS_BIT+0,CLASS_CC,0,0,0,0,0,},1,2,286}, -{"rl",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM_1),}, - {CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},2,2,287}, -{"rl",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM_2),}, - {CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},2,2,288}, -{"rlb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM_1),}, - {CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},2,2,289}, -{"rlb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM_2),}, - {CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},2,2,290}, -{"rlc",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM_1),}, - {CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},2,2,291}, -{"rlc",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM_2),}, - {CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+10,0,0,0,0,0,},2,2,292}, -{"rlcb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM_1),}, - {CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},2,2,293}, -{"rlcb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM_2),}, - {CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+10,0,0,0,0,0,},2,2,294}, -{"rldb",{CLASS_REG_BYTE+(ARG_RB),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+11,CLASS_BIT+14,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RB),0,0,0,0,0,},2,2,295}, -{"rr",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM_1),}, - {CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},2,2,296}, -{"rr",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM_2),}, - {CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},2,2,297}, -{"rrb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM_1),}, - {CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},2,2,298}, -{"rrb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM_2),}, - {CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},2,2,299}, -{"rrc",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM_1),}, - {CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+12,0,0,0,0,0,},2,2,300}, -{"rrc",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM_2),}, - {CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+14,0,0,0,0,0,},2,2,301}, -{"rrcb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM_1),}, - {CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+12,0,0,0,0,0,},2,2,302}, -{"rrcb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM_2),}, - {CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+14,0,0,0,0,0,},2,2,303}, -{"rrdb",{CLASS_REG_BYTE+(ARG_RB),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+11,CLASS_BIT+12,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RB),0,0,0,0,0,},2,2,304}, -{"sbc",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+11,CLASS_BIT+7,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,305}, -{"sbcb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+11,CLASS_BIT+6,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,306}, -{"sda",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+11,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,307}, -{"sdab",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+11,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,308}, -{"sdal",{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+15,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,309}, -{"sdl",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,310}, -{"sdlb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,311}, -{"sdll",{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,312}, -{"set",{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+5,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,313}, -{"set",{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+5,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,314}, -{"set",{CLASS_DA,CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+5,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,315}, -{"set",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+10,CLASS_BIT+5,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,316}, -{"set",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,317}, -{"setb",{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+4,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,318}, -{"setb",{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+4,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,319}, -{"setb",{CLASS_DA,CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+4,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS,0,0,0,0,},2,4,320}, -{"setb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+10,CLASS_BIT+4,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,321}, -{"setb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,322}, -{"setflg",{CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+8,CLASS_BIT+13,CLASS_IMM+(ARG_IMM4),CLASS_BIT+1,0,0,0,0,0,},1,2,323}, -{"sinb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+3,CLASS_BIT+12,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,324}, -{"sinb",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+3,CLASS_BIT+13,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,325}, -{"sind",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+1,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,326}, -{"sindb",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+1,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,327}, -{"sinib",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,328}, -{"sinibr",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,329}, -{"sla",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,330}, -{"slab",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,331}, -{"slal",{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+13,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,332}, -{"sll",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,333}, -{"sllb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,334}, -{"slll",{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,335}, -{"sout",{CLASS_IMM+(ARG_IMM16),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+11,CLASS_REG+(ARG_RS),CLASS_BIT+7,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,336}, -{"soutb",{CLASS_IMM+(ARG_IMM16),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+10,CLASS_REG+(ARG_RS),CLASS_BIT+7,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,337}, -{"soutd",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+11,CLASS_REGN0+(ARG_RS),CLASS_BIT+11,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,338}, -{"soutdb",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+10,CLASS_REGN0+(ARG_RS),CLASS_BIT+11,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,339}, -{"soutib",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,340}, -{"soutibr",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+12,CLASS_REGN0+(ARG_RS),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,341}, -{"sra",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_IMM+(ARG_NIM16),0,0,0,0,},2,4,342}, -{"srab",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_IMM+(ARG_NIM16),0,0,0,0,},2,4,343}, -{"sral",{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+13,CLASS_IMM+(ARG_NIM16),0,0,0,0,},2,4,344}, -{"srl",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_IMM+(ARG_NIM16),0,0,0,0,},2,4,345}, -{"srlb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+11,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_IMM+(ARG_NIM16),0,0,0,0,},2,4,346}, -{"srll",{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+11,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_NIM16),0,0,0,0,},2,4,347}, -{"sub",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+3,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,348}, -{"sub",{CLASS_REG_WORD+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+4,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,349}, -{"sub",{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+3,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,350}, -{"sub",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,351}, -{"sub",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+3,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,352}, -{"subb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,353}, -{"subb",{CLASS_REG_BYTE+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+4,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,354}, -{"subb",{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,355}, -{"subb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,356}, -{"subb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+2,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,357}, -{"subl",{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,358}, -{"subl",{CLASS_REG_LONG+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+5,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,359}, -{"subl",{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,360}, -{"subl",{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, - {CLASS_BIT+1,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,361}, -{"subl",{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+2,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,362}, -{"tcc",{CLASS_CC,CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+10,CLASS_BIT+15,CLASS_REG+(ARG_RD),CLASS_CC,0,0,0,0,0,},2,2,363}, -{"tccb",{CLASS_CC,CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+10,CLASS_BIT+14,CLASS_REG+(ARG_RD),CLASS_CC,0,0,0,0,0,},2,2,364}, -{"test",{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,365}, -{"test",{CLASS_DA,}, - {CLASS_BIT+4,CLASS_BIT+13,CLASS_BIT+0,CLASS_BIT+4,0,0,0,0,0,},1,2,366}, -{"test",{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,367}, -{"test",{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+13,CLASS_REG+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,368}, -{"testb",{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,369}, -{"testb",{CLASS_DA,}, - {CLASS_BIT+4,CLASS_BIT+12,CLASS_BIT+0,CLASS_BIT+4,0,0,0,0,0,},1,2,370}, -{"testb",{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,371}, -{"testb",{CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+12,CLASS_REG+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,372}, -{"testl",{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+1,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,373}, -{"testl",{CLASS_DA,}, - {CLASS_BIT+5,CLASS_BIT+12,CLASS_BIT+0,CLASS_BIT+8,0,0,0,0,0,},1,2,374}, -{"testl",{CLASS_REG_LONG+(ARG_RD),}, - {CLASS_BIT+9,CLASS_BIT+12,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,375}, -{"trdb",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+11,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,376}, -{"trdrb",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+11,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+12,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,377}, -{"trib",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+11,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,378}, -{"trirb",{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+11,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,379}, -{"trtdrb",{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+11,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+14,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+14,0,},3,4,380}, -{"trtib",{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+11,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0,0,},3,4,381}, -{"trtirb",{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+11,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+14,0,},3,4,382}, -{"trtrb",{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+11,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+10,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0,0,},3,4,383}, -{"tset",{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,384}, -{"tset",{CLASS_DA,}, - {CLASS_BIT+4,CLASS_BIT+13,CLASS_BIT+0,CLASS_BIT+6,0,0,0,0,0,},1,2,385}, -{"tset",{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+13,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,386}, -{"tset",{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+13,CLASS_REG+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,387}, -{"tsetb",{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,388}, -{"tsetb",{CLASS_DA,}, - {CLASS_BIT+4,CLASS_BIT+12,CLASS_BIT+0,CLASS_BIT+6,0,0,0,0,0,},1,2,389}, -{"tsetb",{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+12,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,390}, -{"tsetb",{CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+12,CLASS_REG+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,391}, -{"xor",{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,392}, -{"xor",{CLASS_REG_WORD+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+4,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,393}, -{"xor",{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,394}, -{"xor",{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,395}, -{"xor",{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+9,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,396}, -{"xorb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,397}, -{"xorb",{CLASS_REG_BYTE+(ARG_RD),CLASS_DA,}, - {CLASS_BIT+4,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,398}, -{"xorb",{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS,0,0,0,0,},2,4,399}, -{"xorb",{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,400}, -{"xorb",{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+8,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,401}, -0,0}; -#endif diff --git a/opcodes/z8kgen.c b/opcodes/z8kgen.c deleted file mode 100644 index 9549425b63c..00000000000 --- a/opcodes/z8kgen.c +++ /dev/null @@ -1,879 +0,0 @@ -#include <stdio.h> -#define BYTE_INFO_LEN 10 -/*#include "z8opcode.h"*/ -struct op { -char *bits; -char *name; -} ; -#define iswhite(x) ((x) == ' ' || (x) == '\t') -struct op opt[] = -{ -"1011 0101 ssss dddd","adc rd,rs", -"1011 0100 ssss dddd","adcb rbd,rbs", -"0000 0001 ssN0 dddd","add rd,@rs", -"0100 0001 0000 dddd address","add rd,address", -"0100 0001 ssN0 dddd address","add rd,address(rs)", -"0000 0001 0000 dddd imm16","add rd,imm16", -"1000 0001 ssss dddd","add rd,rs", -"0000 0000 ssN0 dddd","addb rbd,@rs", -"0100 0000 0000 dddd address","addb rbd,address", -"0100 0000 ssN0 dddd address","addb rbd,address(rs)", -"0000 0000 0000 dddd imm8 imm8","addb rbd,imm8", -"1000 0000 ssss dddd","addb rbd,rbs", -"0001 0110 ssN0 dddd","addl rrd,@rs", -"0101 0110 0000 dddd address","addl rrd,address", -"0101 0110 ssN0 dddd address","addl rrd,address(rs)", -"0001 0110 0000 dddd imm32","addl rrd,imm32", -"1001 0110 ssss dddd","addl rrd,rrs", -"0000 0111 ssN0 dddd","and rd,@rs", -"0100 0111 0000 dddd address","and rd,address", -"0100 0111 ssN0 dddd address","and rd,address(rs)", -"0000 0111 0000 dddd imm16","and rd,imm16", -"1000 0111 ssss dddd","and rd,rs", -"0000 0110 ssN0 dddd","andb rbd,@rs", -"0100 0110 0000 dddd address","andb rbd,address", -"0100 0110 ssN0 dddd address","andb rbd,address(rs)", -"0000 0110 0000 dddd imm8 imm8","andb rbd,imm8", -"1000 0110 ssss dddd","andb rbd,rbs", -"0010 0111 ddN0 imm4","bit @rd,imm4", -"0110 0111 ddN0 imm4 address","bit address(rd),imm4", -"0110 0111 0000 imm4 address","bit address,imm4", -"1010 0111 dddd imm4","bit rd,imm4", -"0010 0111 0000 ssss 0000 dddd 0000 0000","bit rd,rs", -"0010 0110 ddN0 imm4","bitb @rd,imm4", -"0110 0110 ddN0 imm4 address","bitb address(rd),imm4", -"0110 0110 0000 imm4 address","bitb address,imm4", -"1010 0110 dddd imm4","bitb rbd,imm4", -"0010 0110 0000 ssss 0000 dddd 0000 0000","bitb rbd,rs", -"0001 1111 ddN0 0000","call @rd", -"0101 1111 0000 0000 address","call address", -"0101 1111 ddN0 0000 address","call address(rd)", -"1101 disp12","calr disp12", -"0000 1101 ddN0 1000","clr @rd", -"0100 1101 0000 1000 address","clr address", -"0100 1101 ddN0 1000 address","clr address(rd)", -"1000 1101 dddd 1000","clr rd", -"0000 1100 ddN0 1000","clrb @rd", -"0100 1100 0000 1000 address","clrb address", -"0100 1100 ddN0 1000 address","clrb address(rd)", -"1000 1100 dddd 1000","clrb rbd", -"1011 1011 ssN0 1010 0000 rrrr ddN0 cccc","cpsd @rd,@rs,rr,cc", -"1011 1010 ssN0 1010 0000 rrrr ddN0 cccc","cpsdb @rd,@rs,rr,cc", -"1011 1011 ssN0 1110 0000 rrrr ddN0 cccc","cpsdr @rd,@rs,rr,cc", -"1011 1010 ssN0 1110 0000 rrrr ddN0 cccc","cpsdrb @rd,@rs,rr,cc", -"1011 1011 ssN0 0010 0000 rrrr ddN0 cccc","cpsi @rd,@rs,rr,cc", -"1011 1010 ssN0 0010 0000 rrrr ddN0 cccc","cpsib @rd,@rs,rr,cc", -"1011 1011 ssN0 0110 0000 rrrr ddN0 cccc","cpsir @rd,@rs,rr,cc", -"1011 1010 ssN0 0110 0000 rrrr ddN0 cccc","cpsirb @rd,@rs,rr,cc", -"0000 1101 ddN0 0000","com @rd", -"0100 1101 0000 0000 address","com address", -"0100 1101 ddN0 0000 address","com address(rd)", -"1000 1101 dddd 0000","com rd", -"0000 1100 ddN0 0000","comb @rd", -"0100 1100 0000 0000 address","comb address", -"0100 1100 ddN0 0000 address","comb address(rd)", -"1000 1100 dddd 0000","comb rbd", -"1000 1101 imm4 0101","comflg flags", -"0000 1101 ddN0 0001 imm16","cp @rd,imm16", -"0100 1101 ddN0 0001 address imm16","cp address(rd),imm16", -"0100 1101 0000 0001 address imm16","cp address,imm16", -"0000 1011 ssN0 dddd","cp rd,@rs", -"0100 1011 0000 dddd address","cp rd,address", -"0100 1011 ssN0 dddd address","cp rd,address(rs)", -"0000 1011 0000 dddd imm16","cp rd,imm16", -"1000 1011 ssss dddd","cp rd,rs", -"0000 1100 ddN0 0001 imm8 imm8","cpb @rd,imm8", -"0100 1100 ddN0 0001 address imm8 imm8","cpb address(rd),imm8", -"0100 1100 0000 0001 address imm8 imm8","cpb address,imm8", -"0000 1010 ssN0 dddd","cpb rbd,@rs", -"0100 1010 0000 dddd address","cpb rbd,address", -"0100 1010 ssN0 dddd address","cpb rbd,address(rs)", -"0000 1010 0000 dddd imm8 imm8","cpb rbd,imm8", -"1000 1010 ssss dddd","cpb rbd,rbs", -"1011 1011 ssN0 1000 0000 rrrr dddd cccc","cpd rd,@rs,rr,cc", -"1011 1010 ssN0 1000 0000 rrrr dddd cccc","cpdb rbd,@rs,rr,cc", -"1011 1011 ssN0 1100 0000 rrrr dddd cccc","cpdr rd,@rs,rr,cc", -"1011 1010 ssN0 1100 0000 rrrr dddd cccc","cpdrb rbd,@rs,rr,cc", -"1011 1011 ssN0 0000 0000 rrrr dddd cccc","cpi rbd,@rs,rr,cc", -"1011 1010 ssN0 0000 0000 rrrr dddd cccc","cpib rd,@rs,rr,cc", -"1011 1011 ssN0 0100 0000 rrrr dddd cccc","cpir rbd,@rs,rr,cc", -"1011 1010 ssN0 0100 0000 rrrr dddd cccc","cpirb rd,@rs,rr,cc", -"0001 0000 ssN0 dddd","cpl rrd,@rs", -"0101 0000 0000 dddd address","cpl rrd,address", -"0101 0000 ssN0 dddd address","cpl rrd,address(rs)", -"0001 0000 0000 dddd imm32","cpl rrd,imm32", -"1001 0000 ssss dddd","cpl rrd,rrs", -"1011 0000 dddd 0000","dab rbd", -"1111 dddd 1disp7","dbjnz rbd,disp7", -"0010 1011 ddN0 imm4","dec @rd,imm4", -"0110 1011 ddN0 imm4 address","dec address(rd),imm4", -"0110 1011 0000 imm4 address","dec address,imm4", -"1010 1011 dddd imm4","dec rd,imm4", -"0010 1010 ddN0 imm4","decb @rd,imm4", -"0110 1010 ddN0 imm4 address","decb address(rd),imm4", -"0110 1010 0000 imm4 address","decb address,imm4", -"1010 1010 dddd imm4","decb rbd,imm4", -"0111 1100 0000 00ii","di i2", -"0001 1011 ssN0 dddd","div rrd,@rs", -"0101 1011 0000 dddd address","div rrd,address", -"0101 1011 ssN0 dddd address","div rrd,address(rs)", -"0001 1011 0000 dddd imm16","div rrd,imm16", -"1001 1011 ssss dddd","div rrd,rs", -"0001 1010 ssN0 dddd","divl rqd,@rs", -"0101 1010 0000 dddd address","divl rqd,address", -"0101 1010 ssN0 dddd address","divl rqd,address(rs)", -"0001 1010 0000 dddd imm32","divl rqd,imm32", -"1001 1010 ssss dddd","divl rqd,rrs", -"1111 dddd 0disp7","djnz rd,disp7", -"0111 1100 0000 01ii","ei i2", -"1010 1101 ssss dddd","ex rbd,rbs", -"0010 1101 ssN0 dddd","ex rd,@rs", -"0110 1101 0000 dddd address","ex rd,address", -"0110 1101 ssN0 dddd address","ex rd,address(rs)", -"0010 1100 ssN0 dddd","exb rbd,@rs", -"0110 1100 0000 dddd address","exb rbd,address", -"0110 1100 ssN0 dddd address","exb rbd,address(rs)", -"1010 1100 ssss dddd","exb rbd,rbs", -"1011 0001 dddd 1010","exts rrd", -"1011 0001 dddd 0000","extsb rd", -"1011 0001 dddd 0111","extsl rqd", -"0111 1010 0000 0000","halt", -"0011 1101 ssN0 dddd","in rd,@rs", -"0011 1101 dddd 0100 imm16","in rd,imm16", -"0011 1100 ssN0 dddd","inb rbd,@rs", -"0011 1100 dddd 0100 imm16","inb rbd,imm16", -"0010 1001 ddN0 imm4","inc @rd,imm4", -"0110 1001 ddN0 imm4 address","inc address(rd),imm4", -"0110 1001 0000 imm4 address","inc address,imm4", -"1010 1001 dddd imm4","inc rd,imm4", -"0010 1000 ddN0 imm4","incb @rd,imm4", -"0110 1000 ddN0 imm4 address","incb address(rd),imm4", -"0110 1000 0000 imm4 address","incb address,imm4", -"1010 1000 dddd imm4","incb rbd,imm4", -"0011 1011 ssN0 1000 0000 aaaa ddN0 1000","ind @rd,@rs,ra", -"0011 1010 ssN0 1000 0000 aaaa ddN0 1000","indb @rd,@rs,rba", -"0011 1100 ssN0 0000 0000 aaaa ddN0 1000","inib @rd,@rs,ra", -"0011 1100 ssN0 0000 0000 aaaa ddN0 0000","inibr @rd,@rs,ra", -"0111 1011 0000 0000","iret", -"0001 1110 ddN0 cccc","jp cc,@rd", -"0101 1110 0000 cccc address","jp cc,address", -"0101 1110 ddN0 cccc address","jp cc,address(rd)", -"1110 cccc disp8","jr cc,disp8", -"0000 1101 ddN0 0101 imm16","ld @rd,imm16", -"0010 1111 ddN0 ssss","ld @rd,rs", -"0100 1101 ddN0 0101 address imm16","ld address(rd),imm16", -"0110 1111 ddN0 ssss address","ld address(rd),rs", -"0100 1101 0000 0101 address imm16","ld address,imm16", -"0110 1111 0000 ssss address","ld address,rs", -"0011 0011 ddN0 ssss disp16","ld rd(disp16),rs", -"0111 0011 ddN0 ssss 0000 xxxx 0000 0000","ld rd(rx),rs", -"0010 0001 ssN0 dddd","ld rd,@rs", -"0110 0001 0000 dddd address","ld rd,address", -"0110 0001 ssN0 dddd address","ld rd,address(rs)", -"0010 0001 0000 dddd imm16","ld rd,imm16", -"1010 0001 ssss dddd","ld rd,rs", -"0011 0001 ssN0 dddd disp16","ld rd,rs(disp16)", -"0111 0001 ssN0 dddd 0000 xxxx 0000 0000","ld rd,rs(rx)", -"0111 0110 0000 dddd address","lda rd,address", -"0111 0110 ssN0 dddd address","lda rd,address(rs)", -"0011 0100 ssN0 dddd disp16","lda rd,rs(disp16)", -"0111 0100 ssN0 dddd 0000 xxxx 0000 0000","lda rd,rs(rx)", -"0011 0100 0000 dddd disp16","ldar rd,disp16", -"0000 1100 ddN0 0101 imm8 imm8","ldb @rd,imm8", -"0010 1110 ddN0 ssss","ldb @rd,rbs", -"0100 1100 ddN0 0101 address imm8 imm8","ldb address(rd),imm8", -"0100 1110 ddN0 ssss address","ldb address(rd),rbs", -"0100 1100 0000 0101 address imm8 imm8","ldb address,imm8", -"0110 1110 0000 ssss address","ldb address,rbs", -"0010 0000 ssN0 dddd","ldb rbd,@rs", -"0110 0000 0000 dddd address","ldb rbd,address", -"0110 0000 ssN0 dddd address","ldb rbd,address(rs)", -"1100 dddd imm8","ldb rbd,imm8", -"0010 0000 0000 dddd imm8 imm8","ldb rbd,imm8", -"1010 0000 ssss dddd","ldb rbd,rbs", -"0011 0000 ssN0 dddd disp16","ldb rbd,rs(disp16)", -"0111 0000 ssN0 dddd 0000 xxxx 0000 0000","ldb rbd,rs(rx)", -"0011 0010 ddN0 ssss disp16","ldb rd(disp16),rbs", -"0111 0010 ddN0 ssss 0000 xxxx 0000 0000","ldb rd(rx),rbs", -"0111 1101 ssss 1ccc","ldctl ctrl,rs", -"0111 1101 dddd 0ccc","ldctl rd,ctrl", -"0001 1101 ddN0 ssss","ldl @rd,rrs", -"0101 1101 ddN0 ssss address","ldl address(rd),rrs", -"0101 1101 0000 ssss address","ldl address,rrs", -"0011 0111 ddN0 ssss disp16","ldl rd(disp16),rrs", -"0111 0111 ddN0 ssss 0000 xxxx 0000 0000","ldl rd(rx),rrs", -"0001 0100 ssN0 dddd","ldl rrd,@rs", -"0101 0100 0000 dddd address","ldl rrd,address", -"0101 0100 ssN0 dddd address","ldl rrd,address(rs)", -"0001 0100 0000 dddd imm32","ldl rrd,imm32", -"1001 0100 ssss dddd","ldl rrd,rrs", -"0011 0101 ssN0 dddd disp16","ldl rrd,rs(disp16)", -"0111 0101 ssN0 dddd 0000 xxxx 0000 0000","ldl rrd,rs(rx)", -"0001 1100 ddN0 1001 0000 ssss 0000 nminus1","ldm @rd,rs,n", -"0101 1100 ddN0 1001 0000 ssN0 0000 nminus1 address","ldm address(rd),rs,n", -"0101 1100 0000 1001 0000 ssss 0000 nminus1 address","ldm address,rs,n", -"0001 1100 ssN0 0001 0000 dddd 0000 nminus1","ldm rd,@rs,n", -"0101 1100 ssN0 0001 0000 dddd 0000 nminus1 address","ldm rd,address(rs),n", -"0101 1100 0000 0001 0000 dddd 0000 nminus1 address","ldm rd,address,n", -"0011 1001 ssN0 0000","ldps @rs", -"1011 1101 dddd imm4","ldk rd,imm4", -"1011 1010 ssN0 0001 0000 rrrr ddN0 0000","ldirb @rd,@rs,rr", -"1011 1011 ssN0 0001 0000 rrrr ddN0 0000","ldir @rd,@rs,rr", - -"0111 1001 0000 0000 address","ldps address", -"0111 1001 ssN0 0000 address","ldps address(rs)", -"0011 0011 0000 ssss disp16","ldr disp16,rs", -"0011 0001 0000 dddd disp16","ldr rd,disp16", -"0011 0010 0000 ssss disp16","ldrb disp16,rbs", -"0011 0000 0000 dddd disp16","ldrb rbd,disp16", -"0011 0111 0000 ssss disp16","ldrl disp16,rrs", -"0011 0101 0000 dddd disp16","ldrl rrd,disp16", -"0111 1011 0000 1010","mbit", -"0111 1011 dddd 1101","mreq rd", -"0111 1011 0000 1001","mres", -"0111 1011 0000 1000","mset", -"0001 1001 ssN0 dddd","mult rrd,@rs", -"0101 1001 0000 dddd address","mult rrd,address", -"0101 1001 ssN0 dddd address","mult rrd,address(rs)", -"0001 1001 0000 dddd imm16","mult rrd,imm16", -"1001 1001 ssss dddd","mult rrd,rs", -"0001 1000 ssN0 dddd","multl rqd,@rs", -"0101 1000 0000 dddd address","multl rqd,address", -"0101 1000 ssN0 dddd address","multl rqd,address(rs)", -"0001 1000 0000 dddd imm32","multl rqd,imm32", -"1001 1000 ssss dddd","multl rqd,rrs", -"0000 1101 ddN0 0010","neg @rd", -"0100 1101 0000 0010 address","neg address", -"0100 1101 ddN0 0010 address","neg address(rd)", -"1000 1101 dddd 0010","neg rd", -"0000 1100 ddN0 0010","negb @rd", -"0100 1100 0000 0010 address","negb address", -"0100 1100 ddN0 0010 address","negb address(rd)", -"1000 1100 dddd 0010","negb rbd", -"1000 1101 0000 0111","nop", -"0000 0101 ssN0 dddd","or rd,@rs", -"0100 0101 0000 dddd address","or rd,address", -"0100 0101 ssN0 dddd address","or rd,address(rs)", -"0000 0101 0000 dddd imm16","or rd,imm16", -"1000 0101 ssss dddd","or rd,rs", -"0000 0100 ssN0 dddd","orb rbd,@rs", -"0100 0100 0000 dddd address","orb rbd,address", -"0100 0100 ssN0 dddd address","orb rbd,address(rs)", -"0000 0100 0000 dddd imm8 imm8","orb rbd,imm8", -"1000 0100 ssss dddd","orb rbd,rbs", -"0011 1111 ddN0 ssss","out @rd,rs", -"0011 1011 ssss 0110 imm16","out imm16,rs", -"0011 1110 ddN0 ssss","outb @rd,rbs", -"0011 1010 ssss 0110 imm16","outb imm16,rbs", -"0011 1011 ssN0 1010 0000 aaaa ddN0 1000","outd @rd,@rs,ra", -"0011 1010 ssN0 1010 0000 aaaa ddN0 1000","outdb @rd,@rs,rba", -"0011 1100 ssN0 0010 0000 aaaa ddN0 1000","outib @rd,@rs,ra", -"0011 1100 ssN0 0010 0000 aaaa ddN0 0000","outibr @rd,@rs,ra", -"0001 0111 ssN0 ddN0","pop @rd,@rs", -"0101 0111 ssN0 ddN0 address","pop address(rd),@rs", -"0101 0111 ssN0 0000 address","pop address,@rs", -"1001 0111 ssN0 dddd","pop rd,@rs", -"0001 0101 ssN0 ddN0","popl @rd,@rs", -"0101 0101 ssN0 ddN0 address","popl address(rd),@rs", -"0101 0101 ssN0 0000 address","popl address,@rs", -"1001 0101 ssN0 dddd","popl rrd,@rs", -"0001 0011 ddN0 ssN0","push @rd,@rs", -"0101 0011 ddN0 0000 address","push @rd,address", -"0000 1101 ddN0 1001 imm16","push @rd,imm16", -"1001 0011 ddN0 ssss","push @rd,rs", -"0101 0011 ddN0 ssN0 address","push @rd,address(rs)", -"0001 0001 ddN0 ssN0","pushl @rd,@rs", -"0101 0001 ddN0 0000 address","push @rd,address", -"1001 0001 ddN0 ssss","pushl @rd,rrs", -"0101 0001 ddN0 ssN0 address","pushl @rd,address(rs)", -"0010 0011 ddN0 imm4","res @rd,imm4", -"0110 0011 ddN0 imm4 address","res address(rd),imm4", -"0110 0011 0000 imm4 address","res address,imm4", -"1010 0011 dddd imm4","res rd,imm4", -"0010 0011 0000 ssss 0000 dddd 0000 0000","res rd,rs", -"0010 0010 ddN0 imm4","resb @rd,imm4", -"0110 0010 ddN0 imm4 address","resb address(rd),imm4", -"0110 0010 0000 imm4 address","resb address,imm4", -"1010 0010 dddd imm4","resb rbd,imm4", -"0010 0010 0000 ssss 0000 dddd 0000 0000","resb rbd,rs", -"1000 1101 imm4 0011","resflg imm4", -"1001 1110 0000 cccc","ret cc", -"1011 0011 dddd 0000","rl rd,1", -"1011 0011 dddd 0010","rl rd,2", -"1011 0010 dddd 0000","rlb rbd,1", -"1011 0010 dddd 0010","rlb rbd,2", -"1011 0011 dddd 1000","rlc rd,1", -"1011 0011 dddd 1010","rlc rd,2", -"1011 0010 dddd 1000","rlcb rbd,1", -"1011 0010 dddd 1010","rlcb rbd,2", -"1011 1110 aaaa bbbb","rldb rbb,rba", -"1011 0011 dddd 0100","rr rd,1", -"1011 0011 dddd 0110","rr rd,2", -"1011 0010 dddd 0100","rrb rbd,1", -"1011 0010 dddd 0110","rrb rbd,2", -"1011 0011 dddd 1100","rrc rd,1", -"1011 0011 dddd 1110","rrc rd,2", -"1011 0010 dddd 1100","rrcb rbd,1", -"1011 0010 dddd 1110","rrcb rbd,2", -"1011 1100 aaaa bbbb","rrdb rbb,rba", -"1011 0111 ssss dddd","sbc rd,rs", -"1011 0110 ssss dddd","sbcb rbd,rbs", -"1011 0011 dddd 1011 0000 ssss 0000 0000","sda rd,rs", -"1011 0010 dddd 1011 0000 ssss 0000 0000","sdab rbd,rs", -"1011 0011 dddd 1111 0000 ssss 0000 0000","sdal rrd,rs", -"1011 0011 dddd 0011 0000 ssss 0000 0000","sdl rd,rs", -"1011 0010 dddd 0011 0000 ssss 0000 0000","sdlb rbd,rs", -"1011 0011 dddd 0111 0000 ssss 0000 0000","sdll rrd,rs", -"0010 0101 ddN0 imm4","set @rd,imm4", -"0110 0101 ddN0 imm4 address","set address(rd),imm4", -"0110 0101 0000 imm4 address","set address,imm4", -"1010 0101 dddd imm4","set rd,imm4", -"0010 0101 0000 ssss 0000 dddd 0000 0000","set rd,rs", -"0010 0100 ddN0 imm4","setb @rd,imm4", -"0110 0100 ddN0 imm4 address","setb address(rd),imm4", -"0110 0100 0000 imm4 address","setb address,imm4", -"1010 0100 dddd imm4","setb rbd,imm4", -"0010 0100 0000 ssss 0000 dddd 0000 0000","setb rbd,rs", -"1000 1101 imm4 0001","setflg imm4", -"0011 1100 dddd 0101 imm16","sinb rbd,imm16", -"0011 1101 dddd 0101 imm16","sinb rd,imm16", -"0011 1011 ssN0 1000 0001 aaaa ddN0 1000","sind @rd,@rs,ra", -"0011 1010 ssN0 1000 0001 aaaa ddN0 1000","sindb @rd,@rs,rba", -"0011 1100 ssN0 0001 0000 aaaa ddN0 1000","sinib @rd,@rs,ra", -"0011 1100 ssN0 0001 0000 aaaa ddN0 0000","sinibr @rd,@rs,ra", -"1011 0011 dddd 1001 imm16","sla rd,imm16", -"1011 0010 dddd 1001 imm16","slab rbd,imm16", -"1011 0011 dddd 1101 imm16","slal rrd,imm16", -"1011 0011 dddd 0001 imm16","sll rd,imm16", -"1011 0010 dddd 0001 imm16","sllb rbd,imm16", -"1011 0011 dddd 0101 imm16","slll rrd,imm16", -"0011 1011 ssss 0111 imm16","sout imm16,rs", -"0011 1010 ssss 0111 imm16","soutb imm16,rbs", -"0011 1011 ssN0 1011 0000 aaaa ddN0 1000","soutd @rd,@rs,ra", -"0011 1010 ssN0 1011 0000 aaaa ddN0 1000","soutdb @rd,@rs,rba", -"0011 1100 ssN0 0011 0000 aaaa ddN0 1000","soutib @rd,@rs,ra", -"0011 1100 ssN0 0011 0000 aaaa ddN0 0000","soutibr @rd,@rs,ra", -"1011 0011 dddd 1001 nim16","sra rd,imm16", -"1011 0010 dddd 1001 nim16","srab rbd,imm16", -"1011 0011 dddd 1101 nim16","sral rrd,imm16", -"1011 0011 dddd 0001 nim16","srl rd,imm16", -"1011 0010 dddd 0001 nim16","srlb rbd,imm16", -"1011 0011 dddd 0101 nim16","srll rrd,imm16", -"0000 0011 ssN0 dddd","sub rd,@rs", -"0100 0011 0000 dddd address","sub rd,address", -"0100 0011 ssN0 dddd address","sub rd,address(rs)", -"0000 0010 0000 dddd imm16","sub rd,imm16", -"1000 0011 ssss dddd","sub rd,rs", -"0000 0010 ssN0 dddd","subb rbd,@rs", -"0100 0010 0000 dddd address","subb rbd,address", -"0100 0010 ssN0 dddd address","subb rbd,address(rs)", -"0000 0010 0000 dddd imm8 imm8","subb rbd,imm8", -"1000 0010 ssss dddd","subb rbd,rbs", -"0001 0010 ssN0 dddd","subl rrd,@rs", -"0101 0010 0000 dddd address","subl rrd,address", -"0101 0010 ssN0 dddd address","subl rrd,address(rs)", -"0001 0010 0000 dddd imm32","subl rrd,imm32", -"1001 0010 ssss dddd","subl rrd,rrs", -"1010 1111 dddd cccc","tcc cc,rd", -"1010 1110 dddd cccc","tccb cc,rbd", -"0000 1101 ddN0 0100","test @rd", -"0100 1101 0000 0100 address","test address", -"0100 1101 ddN0 0100 address","test address(rd)", -"1000 1101 dddd 0100","test rd", -"0000 1100 ddN0 0100","testb @rd", -"0100 1100 0000 0100 address","testb address", -"0100 1100 ddN0 0100 address","testb address(rd)", -"1000 1100 dddd 0100","testb rbd", -"0001 1100 ddN0 1000","testl @rd", -"0101 1100 0000 1000 address","testl address", -"1001 1100 dddd 1000","testl rrd", -"1011 1000 ddN0 1000 0000 aaaa ssN0 0000","trdb @rd,@rs,rba", -"1011 1000 ddN0 1100 0000 aaaa ssN0 0000","trdrb @rd,@rs,rba", -"1011 1000 ddN0 0000 0000 rrrr ssN0 0000","trib @rd,@rs,rbr", -"1011 1000 ddN0 0100 0000 rrrr ssN0 0000","trirb @rd,@rs,rbr", -"1011 1000 aaN0 1110 0000 rrrr bbN0 1110","trtdrb @ra,@rb,rbr", -"1011 1000 aaN0 0010 0000 rrrr bbN0 0000","trtib @ra,@rb,rr", -"1011 1000 aaN0 0110 0000 rrrr bbN0 1110","trtirb @ra,@rb,rbr", -"1011 1000 aaN0 1010 0000 rrrr bbN0 0000","trtrb @ra,@rb,rbr", -"0000 1101 ddN0 0110","tset @rd", -"0100 1101 0000 0110 address","tset address", -"0100 1101 ddN0 0110 address","tset address(rd)", -"1000 1101 dddd 0110","tset rd", -"0000 1100 ddN0 0110","tsetb @rd", -"0100 1100 0000 0110 address","tsetb address", -"0100 1100 ddN0 0110 address","tsetb address(rd)", -"1000 1100 dddd 0110","tsetb rbd", -"0000 1001 ssN0 dddd","xor rd,@rs", -"0100 1001 0000 dddd address","xor rd,address", -"0100 1001 ssN0 dddd address","xor rd,address(rs)", -"0000 1001 0000 dddd imm16","xor rd,imm16", -"1000 1001 ssss dddd","xor rd,rs", -"0000 1000 ssN0 dddd","xorb rbd,@rs", -"0100 1000 0000 dddd address","xorb rbd,address", -"0100 1000 ssN0 dddd address","xorb rbd,address(rs)", -"0000 1000 0000 dddd imm8 imm8","xorb rbd,imm8", -"1000 1000 ssss dddd","xorb rbd,rbs", - - -0,0 -} -; - -int count() -{ - struct op *p = opt; - int r = 0; - while (p->name) - { - r++; - p++; - } - return r; - -} -func(a,b) -struct op *a; -struct op *b; -{ -return strcmp((a)->name, (b)->name); - - -} - -func1(a,b) -struct op *a; -struct op *b; -{ -return strcmp((a)->bits, (b)->bits); - - -} - -/* opcode - - literal 0000 nnnn insert nnn into stream - operand 0001 nnnn insert operand reg nnn into stream -*/ - -typedef struct tok_struct -{ - -char *match; -char *token; -int length; -}; - - - -struct tok_struct args[] = -{ - -{ "address(rs)", "CLASS_X+(ARG_RS)",}, -{ "address(rd)", "CLASS_X+(ARG_RD)",}, - -{ "rs(disp16)","CLASS_BA+(ARG_RS)",}, -{ "rd(disp16)","CLASS_BA+(ARG_RD)",}, - -{ "address", "CLASS_DA",}, -{ "rd(rx)", "CLASS_BX+(ARG_RD)",}, -{ "rs(rx)","CLASS_BX+(ARG_RS)",}, -{ "disp16", "CLASS_DISP",}, -{ "disp12", "CLASS_DISP",}, -{ "disp7", "CLASS_DISP",}, -{ "disp8", "CLASS_DISP",}, -{ "flags","CLASS_FLAGS",}, -{ "imm16", "CLASS_IMM+(ARG_IMM16)",}, -{ "imm32", "CLASS_IMM+(ARG_IMM32)",}, -{ "imm4", "CLASS_IMM +(ARG_IMM4)",}, -{ "n", "CLASS_IMM + (ARG_IMMN)",}, -{ "ctrl", "CLASS_CTRL",}, -{ "rba", "CLASS_REG_BYTE+(ARG_RA)",}, -{ "rbb", "CLASS_REG_BYTE+(ARG_RB)",}, -{ "rbd", "CLASS_REG_BYTE+(ARG_RD)",}, -{ "rbs", "CLASS_REG_BYTE+(ARG_RS)",}, -{ "rbr", "CLASS_REG_BYTE+(ARG_RR)",}, - -{ "rrd","CLASS_REG_LONG+(ARG_RD)",}, -{ "rrs","CLASS_REG_LONG+(ARG_RS)",}, - -{ "rqd", "CLASS_REG_QUAD+(ARG_RD)",}, - -{ "rd", "CLASS_REG_WORD+(ARG_RD)",}, -{ "rs", "CLASS_REG_WORD+(ARG_RS)",}, - -{ "@rd", "CLASS_IR+(ARG_RD)",}, -{ "@ra", "CLASS_IR+(ARG_RA)",}, -{ "@rb", "CLASS_IR+(ARG_RB)",}, -{ "@rs", "CLASS_IR+(ARG_RS)",}, - -{ "imm8", "CLASS_IMM+(ARG_IMM8)",}, -{ "i2", "CLASS_IMM+(ARG_IMM2)",}, -{ "cc", "CLASS_CC",}, - -{ "rr", "CLASS_REG_WORD+(ARG_RR)",}, -{ "ra", "CLASS_REG_WORD+(ARG_RA)",}, -{ "rs", "CLASS_REG_WORD+(ARG_RS)",}, - -{ "1", "CLASS_IMM+(ARG_IMM_1)",}, -{ "2", "CLASS_IMM+(ARG_IMM_2)",}, - - 0,0 - }; - -struct tok_struct toks[] = -{ - "0000", "CLASS_BIT+0",1, - "0001", "CLASS_BIT+1",1, - "0010", "CLASS_BIT+2",1, - "0011", "CLASS_BIT+3",1, - "0100", "CLASS_BIT+4",1, - "0101", "CLASS_BIT+5",1, - "0110", "CLASS_BIT+6",1, - "0111", "CLASS_BIT+7",1, - "1000", "CLASS_BIT+8",1, - "1001", "CLASS_BIT+9",1, - "1010", "CLASS_BIT+10",1, - "1011", "CLASS_BIT+11",1, - "1100", "CLASS_BIT+12",1, - "1101", "CLASS_BIT+13",1, - "1110", "CLASS_BIT+14",1, - "1111", "CLASS_BIT+15",1, - - "ssss", "CLASS_REG+(ARG_RS)",1, - "dddd", "CLASS_REG+(ARG_RD)",1, - "aaaa", "CLASS_REG+(ARG_RA)",1, - "bbbb", "CLASS_REG+(ARG_RB)",1, - "rrrr", "CLASS_REG+(ARG_RR)",1, - - "ssN0", "CLASS_REGN0+(ARG_RS)",1, - "ddN0", "CLASS_REGN0+(ARG_RD)",1, - "aaN0", "CLASS_REGN0+(ARG_RA)",1, - "bbN0", "CLASS_REGN0+(ARG_RB)",1, - "rrN0", "CLASS_REGN0+(ARG_RR)",1, - - "cccc", "CLASS_CC",1, - "nnnn", "CLASS_IMM+(ARG_IMMN)",1, - "xxxx", "CLASS_REG+(ARG_RX)",1, - "xxN0", "CLASS_REGN0+(ARG_RX)",1, - "nminus1", "CLASS_IMM+(ARG_IMMNMINUS1)",1, - - "disp16", "CLASS_DISP+(ARG_DISP16)",4, - "disp12", "CLASS_DISP+(ARG_DISP12)",3, - "flags", "CLASS_FLAGS",1, - "address", "CLASS_ADDRESS",4, - "imm4", "CLASS_IMM+(ARG_IMM4)",1, - "imm8", "CLASS_IMM+(ARG_IMM8)",2, - "imm16", "CLASS_IMM+(ARG_IMM16)",4, - "imm32", "CLASS_IMM+(ARG_IMM32)",8, - "nim16", "CLASS_IMM+(ARG_NIM16)",4, - "0ccc", "CLASS_0CCC",1, - "1ccc", "CLASS_1CCC",1, - "disp8", "CLASS_DISP8",2, - "0disp7", "CLASS_0DISP7",2, - "1disp7", "CLASS_1DISP7",2, - "01ii", "CLASS_01II",1, - "00ii", "CLASS_00II",1, - 0,0 - - }; - - -char *translate(table, x, length) -struct tok_struct *table; -char *x; -int *length; -{ - - int found; - found = 0; - while (table->match) - { - int l = strlen(table->match); - if (strncmp(table->match, x, l) == 0) - { - /* Got a hit */ - printf("%s", table->token); - *length += table->length; - return x + l; - } - - table++; - } - fprintf(stderr,"Can't find %s\n", x); - while (*x) - x++; - return x; -} - - -void - chewbits(bits, length) -char *bits; -int *length; -{ - int i; - int found; - - int n = 0; - *length = 0; - printf("{"); - while (*bits) - { - while (*bits == ' ') - { - bits++; - } - bits = translate(toks, bits, length); - n++; - printf(","); - - } - while (n < BYTE_INFO_LEN-1) { - printf("0,"); - n++; - } - printf("}"); -} - -doreg(x) -char *x; -{ -printf("REGH %c ", x[0]); - -} -int chewname(name) -char *name; -{ - char *n; - int nargs = 0; - int nbytes= 0; - n = name; - printf("\""); - while (*n && !iswhite(*n)) { - printf("%c", *n ); - n++; - } - printf("\",{"); - /* Scan the operands and make entires for them -remember indirect things */ - while (*n) { - int d; - while (*n == ',' || iswhite(*n)) - n++; - nargs++; - n= translate(args, n, &d); - printf(","); - } - if (nargs == 0) { - printf("0"); - } - printf("},"); - return nargs; -} -sub(x,c) -char *x; -char c; -{ - while (*x) - { - if (x[0] == c - && x[1] == c - && x[2] == c - && x[3] == c) { - x[2] = 'N'; - x[3] = '0'; - } - x++; - } -} -internal() -{ - int c = count(); - struct op *new = malloc(sizeof(struct op) * c); - struct op *p = opt; - memcpy(new, p, c * sizeof(struct op)); - - /* sort all names in table alphabetically */ - qsort(new, c, sizeof(struct op), func); - p = new; - while (p->name) { - /* If there are any @rs, sub the ssss into a ssn0, - (rs), (ssn0) - */ - int loop = 1; - while (loop) { - char *s = p->name; - loop = 0; - while (*s) { - if(s[0] == '@') { - char c ; - /* skip the r and sub the string */ - s++; - c = s[1]; - sub(p->bits,c); - } - if (s[0] == '(' && s[3] == ')') - { - sub(p->bits, s[2]); - } - if (s[0] == '(') - { - sub(p->bits, s[-1]); - } - - s++; - } - - } - printf("\"%s\",\"%s\",\n", p->bits, p->name); - p++; - } -} -gas() -{ - - int c = count(); - int i; - struct op *p = opt; - int idx = 0; - char *oldname = ""; - struct op *new = malloc(sizeof(struct op) * c); - - memcpy(new, p, c * sizeof(struct op)); - - /* sort all names in table alphabetically */ - qsort(new, c, sizeof(struct op), func); - - printf(" /* THIS FILE IS AUTOMAGICALLY GENERATED, DON'T EDIT IT */\n"); - - printf("#define ARG_MASK 0x0f\n"); - printf("#define ARG_RS 0x01\n"); - printf("#define ARG_RD 0x02\n"); - printf("#define ARG_RA 0x03\n"); - printf("#define ARG_RB 0x04\n"); - printf("#define ARG_RR 0x05\n"); - printf("#define ARG_RX 0x06\n"); - printf("#define ARG_IMM4 0x01\n"); - printf("#define ARG_IMM8 0x02\n"); - printf("#define ARG_IMM16 0x03\n"); - printf("#define ARG_IMM32 0x04\n"); - printf("#define ARG_IMMN 0x05\n"); - printf("#define ARG_IMMNMINUS1 0x05\n"); - printf("#define ARG_IMM_1 0x06\n"); - printf("#define ARG_IMM_2 0x07\n"); - printf("#define ARG_DISP16 0x08\n"); - printf("#define ARG_NIM16 0x09\n"); - printf("#define ARG_IMM2 0x0a\n"); - printf("#define ARG_DISP12 0x0b\n"); - printf("#define ARG_DISP8 0x0c\n"); - - printf("#define CLASS_MASK 0xfff0\n"); - printf("#define CLASS_X 0x10\n"); - printf("#define CLASS_BA 0x20\n"); - printf("#define CLASS_DA 0x30\n"); - printf("#define CLASS_BX 0x40\n"); - printf("#define CLASS_DISP 0x50\n"); - printf("#define CLASS_IMM 0x60\n"); - printf("#define CLASS_CC 0x70\n"); - printf("#define CLASS_CTRL 0x80\n"); - printf("#define CLASS_ADDRESS 0xd0\n"); - printf("#define CLASS_0CCC 0xe0\n"); - printf("#define CLASS_1CCC 0xf0\n"); - printf("#define CLASS_0DISP7 0x100\n"); - printf("#define CLASS_1DISP7 0x200\n"); - printf("#define CLASS_01II 0x300\n"); - printf("#define CLASS_00II 0x400\n"); - printf("#define CLASS_BIT 0x500\n"); - printf("#define CLASS_FLAGS 0x600\n"); - printf("#define CLASS_IR 0x700\n"); - printf("#define CLASS_DISP8 0x800\n"); - - - printf("#define CLASS_REG 0x7000\n"); - printf("#define CLASS_REG_BYTE 0x2000\n"); - printf("#define CLASS_REG_WORD 0x3000\n"); - printf("#define CLASS_REG_QUAD 0x4000\n"); - printf("#define CLASS_REG_LONG 0x5000\n"); - printf("#define CLASS_REGN0 0x8000\n"); - - - -#if 0 - for (i = 0; toks[i].token; i++) - printf("#define %s\t0x%x\n",toks[i].token,i*16); -#endif - printf("typedef struct {\n"); - printf("char *name;\n"); - printf("unsigned short arg_info[4];\n"); - printf("unsigned short byte_info[%d];\n", BYTE_INFO_LEN); - printf("int noperands;\n"); - printf("int length;\n"); - printf("int idx;\n"); - printf("} opcode_entry_type;\n"); - printf("#ifdef DEFINE_TABLE\n"); - printf("opcode_entry_type z8k_table[] = {\n"); - - while (new->name) { - int nargs; - int length; - printf("{"); - nargs = chewname(new->name); - -printf("\n\t"); - chewbits(new->bits, &length); - length /=2; - if (length &1) fail(); - - printf(",%d,%d,%d", nargs, length, idx); - if(strcmp(oldname, new->name)) - { - idx++; - oldname = new->name; - } - printf("},\n"); - new++; - } - printf("0,0};\n"); - printf("#endif\n"); -} -main(ac,av) -int ac; -char **av; -{ - struct op *p = opt; - - if (ac == 2 && strcmp(av[1],"-t")==0) - { - internal(); - } -else if (ac == 2 && strcmp(av[1],"-h")==0) - { - while (p->name) { - printf("%-25s\t%s\n", p->name, p->bits); - p++; - } - } - - else if (ac== 2 && strcmp(av[1], "-a") == 0) - { - gas(); - } - else if (ac== 2 && strcmp(av[1], "-d") == 0) - { - /*dis();*/ - } - else { - printf("Usage: %s -t\n", av[0]); - printf("-t : generate new z8.c internal table\n"); - printf("-a : generate new table for gas\n"); - printf("-d : generate new table for disassemble\n"); - printf("-h : generate new table for humans\n"); - } - - -} - -fail() -{ -} - - |