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| author | Richard Henderson <rth@redhat.com> | 1999-06-07 12:44:48 +0000 |
|---|---|---|
| committer | Richard Henderson <rth@redhat.com> | 1999-06-07 12:44:48 +0000 |
| commit | 440034c99f17db548089e694de8330911152c767 (patch) | |
| tree | 8641b586de6e3937cd50acc5a7537ceab9fb5d9f /opcodes/sparc-opc.c | |
| parent | cf9a13018b99097694b31dd4b2df642cd7907ccf (diff) | |
| download | binutils-gdb-440034c99f17db548089e694de8330911152c767.tar.gz | |
Jakub Jelinek <jj@ultra.linux.cz>
* sparc-opc.c: Fix up set, setsw, setuw operand kinds.
Support signx %reg, clruw %reg.
Diffstat (limited to 'opcodes/sparc-opc.c')
| -rw-r--r-- | opcodes/sparc-opc.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c index 8d825288883..7ad9d183878 100644 --- a/opcodes/sparc-opc.c +++ b/opcodes/sparc-opc.c @@ -1464,9 +1464,9 @@ CONDFC ("fbule", "cb013", 0xe, 0), { "nop", F2(0, 4), 0xfeffffff, "", 0, v6 }, /* sethi 0, %g0 */ -{ "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "Sh,d", F_ALIAS, v6 }, -{ "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "Sh,d", F_ALIAS, v9 }, -{ "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "Sh,d", F_ALIAS, v9 }, +{ "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v6 }, +{ "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 }, +{ "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 }, { "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, v9 }, { "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 }, @@ -1717,10 +1717,11 @@ SLCBCC("cbnefr", 15), { "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, v9 }, /* v9 synthetic insns */ -/* FIXME: still missing "signx d", and "clruw d". Can't be done here. */ { "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, v9 }, /* bn,a,pt %xcc,label */ { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* sra rs1,%g0,rd */ +{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* sra rd,%g0,rd */ { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* srl rs1,%g0,rd */ +{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* srl rd,%g0,rd */ { "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P,rs2,rd */ { "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */ { "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */ |