diff options
| author | Richard Henderson <rth@redhat.com> | 2018-10-05 11:41:41 +0900 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2018-10-05 11:41:42 +0900 |
| commit | 07f5f4c683879e844d20d0d4963bbaf1b7cd47b9 (patch) | |
| tree | 872d6d64ac1dd790d76b214c2f7ae0150d51bdbb /opcodes/or1k-desc.h | |
| parent | c8e98e3692cec125b92c995d8f881d9bdf1fac00 (diff) | |
| download | binutils-gdb-07f5f4c683879e844d20d0d4963bbaf1b7cd47b9.tar.gz | |
or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns
Also fix the incorrect definitions of multiply and divide carry and
overflow float.
Changes to the instructions are made in the .cpu file, then we
regenerate the binutils and sim files.
The changes also required a few fixups for tests and additional sim helpers.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
(insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
(l-mul): Fix overflow support and indentation.
(l-mulu): Fix overflow support and indentation.
(l-muld, l-muldu, l-msbu, l-macu): New instructions.
(l-div); Remove incorrect carry behavior.
(l-divu): Fix carry and overflow behavior.
(l-mac): Add overflow support.
(l-msb, l-msbu): Add carry and overflow support.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1k-desc.c: Regenerate.
* or1k-desc.h: Regenerate.
* or1k-opc.c: Regenerate.
* or1k-opc.h: Regenerate.
* or1k-opinst.c: Regenerate.
sim/common/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* cgen-ops.h (ADDCFDI): New function, add carry flag DI variant.
(ADDOFDI): New function, add overflow flag DI variant.
(SUBCFDI): New function, subtract carry flag DI variant.
(SUBOFDI): New function, subtract overflow flag DI variant.
sim/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1k/cpu.h: Regenerate.
* or1k/decode.c: Regenerate.
* or1k/decode.h: Regenerate.
* or1k/model.c: Regenerate.
* or1k/sem-switch.c: Regenerate.
* or1k/sem.c: Regenerate:
sim/testsuite/sim/or1k/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* div.S: Fix tests to match correct overflow/carry semantics.
* mul.S: Likewise.
gas/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* testsuite/gas/or1k/allinsn.s: Add instruction tests for
l.muld, l.muldu, l.macu, l.msb, l.msbu.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
Diffstat (limited to 'opcodes/or1k-desc.h')
| -rw-r--r-- | opcodes/or1k-desc.h | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/opcodes/or1k-desc.h b/opcodes/or1k-desc.h index d84f0fa52a9..040bd926c59 100644 --- a/opcodes/or1k-desc.h +++ b/opcodes/or1k-desc.h @@ -306,7 +306,7 @@ typedef enum insn_opcode_movehimacrc { /* Enum declaration for multiply/accumulate insn opcode enums. */ typedef enum insn_opcode_mac { - OPC_MAC_MAC = 1, OPC_MAC_MSB = 2 + OPC_MAC_MAC = 1, OPC_MAC_MSB = 2, OPC_MAC_MACU = 3, OPC_MAC_MSBU = 4 } INSN_OPCODE_MAC; /* Enum declaration for shift/rotate insn opcode enums. */ @@ -327,9 +327,10 @@ typedef enum insn_opcode_extws { /* Enum declaration for alu reg/reg insn opcode enums. */ typedef enum insn_opcode_alu_regreg { OPC_ALU_REGREG_ADD = 0, OPC_ALU_REGREG_ADDC = 1, OPC_ALU_REGREG_SUB = 2, OPC_ALU_REGREG_AND = 3 - , OPC_ALU_REGREG_OR = 4, OPC_ALU_REGREG_XOR = 5, OPC_ALU_REGREG_MUL = 6, OPC_ALU_REGREG_SHROT = 8 - , OPC_ALU_REGREG_DIV = 9, OPC_ALU_REGREG_DIVU = 10, OPC_ALU_REGREG_MULU = 11, OPC_ALU_REGREG_EXTBH = 12 - , OPC_ALU_REGREG_EXTW = 13, OPC_ALU_REGREG_CMOV = 14, OPC_ALU_REGREG_FFL1 = 15 + , OPC_ALU_REGREG_OR = 4, OPC_ALU_REGREG_XOR = 5, OPC_ALU_REGREG_MUL = 6, OPC_ALU_REGREG_MULD = 7 + , OPC_ALU_REGREG_SHROT = 8, OPC_ALU_REGREG_DIV = 9, OPC_ALU_REGREG_DIVU = 10, OPC_ALU_REGREG_MULU = 11 + , OPC_ALU_REGREG_EXTBH = 12, OPC_ALU_REGREG_EXTW = 13, OPC_ALU_REGREG_MULDU = 13, OPC_ALU_REGREG_CMOV = 14 + , OPC_ALU_REGREG_FFL1 = 15 } INSN_OPCODE_ALU_REGREG; /* Enum declaration for setflag insn opcode enums. */ @@ -632,7 +633,7 @@ typedef enum cgen_operand_type { #define MAX_OPERANDS 32 /* Maximum number of operands referenced by any insn. */ -#define MAX_OPERAND_INSTANCES 9 +#define MAX_OPERAND_INSTANCES 10 /* Insn attribute indices. */ |