opcodes/or1k: Regenerate opcodes

This picks up changes for:
  - new orfpx64a32 spec additions
  - new unordered instructions
  - symbol and documentation updates

opcodes/ChangeLog:

	* or1k-asm.c: Regenerated.
	* or1k-desc.c: Regenerated.
	* or1k-desc.h: Regenerated.
	* or1k-dis.c: Regenerated.
	* or1k-ibld.c: Regenerated.
	* or1k-opc.c: Regenerated.
	* or1k-opc.h: Regenerated.
	* or1k-opinst.c: Regenerated.

1 files changed, 272 insertions, 37 deletions

diff --git a/opcodes/or1k-desc.c b/opcodes/or1k-desc.c
index 486b0f26260..3357849a272 100644
--- a/opcodes/or1k-desc.c
+++ b/opcodes/or1k-desc.c
@@ -134,7 +134,7 @@ static const CGEN_MACH or1k_cgen_mach_table[] = {
   { 0, 0, 0, 0 }
 };
 
-static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fsr_entries[] =
+static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_gpr_entries[] =
 {
   { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
   { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
@@ -173,14 +173,14 @@ static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fsr_entries[] =
   { "fp", 2, {0, {{{0, 0}}}}, 0, 0 }
 };
 
-CGEN_KEYWORD or1k_cgen_opval_h_fsr =
+CGEN_KEYWORD or1k_cgen_opval_h_gpr =
 {
-  & or1k_cgen_opval_h_fsr_entries[0],
+  & or1k_cgen_opval_h_gpr_entries[0],
   35,
   0, 0, 0, 0, ""
 };
 
-static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fdr_entries[] =
+static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fsr_entries[] =
 {
   { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
   { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
@@ -219,14 +219,14 @@ static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fdr_entries[] =
   { "fp", 2, {0, {{{0, 0}}}}, 0, 0 }
 };
 
-CGEN_KEYWORD or1k_cgen_opval_h_fdr =
+CGEN_KEYWORD or1k_cgen_opval_h_fsr =
 {
-  & or1k_cgen_opval_h_fdr_entries[0],
+  & or1k_cgen_opval_h_fsr_entries[0],
   35,
   0, 0, 0, 0, ""
 };
 
-static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_gpr_entries[] =
+static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fdr_entries[] =
 {
   { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
   { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
@@ -265,9 +265,9 @@ static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_gpr_entries[] =
   { "fp", 2, {0, {{{0, 0}}}}, 0, 0 }
 };
 
-CGEN_KEYWORD or1k_cgen_opval_h_gpr =
+CGEN_KEYWORD or1k_cgen_opval_h_fdr =
 {
-  & or1k_cgen_opval_h_gpr_entries[0],
+  & or1k_cgen_opval_h_fdr_entries[0],
   35,
   0, 0, 0, 0, ""
 };
@@ -285,10 +285,12 @@ const CGEN_HW_ENTRY or1k_cgen_hw_table[] =
   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
-  { "h-fsr", HW_H_FSR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_fsr, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
-  { "h-fdr", HW_H_FDR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_fdr, { 0|A(VIRTUAL), { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
   { "h-spr", HW_H_SPR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
   { "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_gpr, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+  { "h-fsr", HW_H_FSR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_fsr, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+  { "h-fdr", HW_H_FDR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_fdr, { 0|A(VIRTUAL), { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+  { "h-fd32r", HW_H_FD32R, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
+  { "h-i64r", HW_H_I64R, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
   { "h-sys-vr", HW_H_SYS_VR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
   { "h-sys-upr", HW_H_SYS_UPR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
   { "h-sys-cpucfgr", HW_H_SYS_CPUCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
@@ -922,6 +924,7 @@ const CGEN_HW_ENTRY or1k_cgen_hw_table[] =
   { "h-uimm6", HW_H_UIMM6, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
   { "h-atomic-reserve", HW_H_ATOMIC_RESERVE, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
   { "h-atomic-address", HW_H_ATOMIC_ADDRESS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-roff1", HW_H_ROFF1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 };
 
@@ -962,6 +965,7 @@ const CGEN_IFLD or1k_cgen_ifld_table[] =
   { OR1K_F_RESV_10_7, "f-resv-10-7", 0, 32, 10, 7, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
   { OR1K_F_RESV_10_3, "f-resv-10-3", 0, 32, 10, 3, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
   { OR1K_F_RESV_10_1, "f-resv-10-1", 0, 32, 10, 1, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
+  { OR1K_F_RESV_8_1, "f-resv-8-1", 0, 32, 8, 1, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
   { OR1K_F_RESV_7_4, "f-resv-7-4", 0, 32, 7, 4, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
   { OR1K_F_RESV_5_2, "f-resv-5-2", 0, 32, 5, 2, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
   { OR1K_F_IMM16_25_5, "f-imm16-25-5", 0, 32, 25, 5, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
@@ -973,6 +977,12 @@ const CGEN_IFLD or1k_cgen_ifld_table[] =
   { OR1K_F_UIMM6, "f-uimm6", 0, 32, 5, 6, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
   { OR1K_F_UIMM16_SPLIT, "f-uimm16-split", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
   { OR1K_F_SIMM16_SPLIT, "f-simm16-split", 0, 0, 0, 0,{ 0|A(SIGN_OPT)|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
+  { OR1K_F_RDOFF_10_1, "f-rdoff-10-1", 0, 32, 10, 1, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
+  { OR1K_F_RAOFF_9_1, "f-raoff-9-1", 0, 32, 9, 1, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
+  { OR1K_F_RBOFF_8_1, "f-rboff-8-1", 0, 32, 8, 1, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
+  { OR1K_F_RDD32, "f-rdd32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
+  { OR1K_F_RAD32, "f-rad32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
+  { OR1K_F_RBD32, "f-rbd32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 };
 
@@ -984,6 +994,9 @@ const CGEN_IFLD or1k_cgen_ifld_table[] =
 
 const CGEN_MAYBE_MULTI_IFLD OR1K_F_UIMM16_SPLIT_MULTI_IFIELD [];
 const CGEN_MAYBE_MULTI_IFLD OR1K_F_SIMM16_SPLIT_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD OR1K_F_RDD32_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD OR1K_F_RAD32_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD OR1K_F_RBD32_MULTI_IFIELD [];
 
 
 /* multi ifield definitions */
@@ -1000,6 +1013,24 @@ const CGEN_MAYBE_MULTI_IFLD OR1K_F_SIMM16_SPLIT_MULTI_IFIELD [] =
     { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_IMM16_10_11] } },
     { 0, { (const PTR) 0 } }
 };
+const CGEN_MAYBE_MULTI_IFLD OR1K_F_RDD32_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+    { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_RDOFF_10_1] } },
+    { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD OR1K_F_RAD32_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } },
+    { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_RAOFF_9_1] } },
+    { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD OR1K_F_RBD32_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
+    { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_RBOFF_8_1] } },
+    { 0, { (const PTR) 0 } }
+};
 
 /* The operand table.  */
 
@@ -1124,18 +1155,42 @@ const CGEN_OPERAND or1k_cgen_operand_table[] =
   { "rBSF", OR1K_OPERAND_RBSF, HW_H_FSR, 15, 5,
     { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
-/* rDDF: destination register (double floating point mode) */
+/* rDDF: or64 destination register (double floating point mode) */
   { "rDDF", OR1K_OPERAND_RDDF, HW_H_FDR, 25, 5,
     { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
-/* rADF: source register A (double floating point mode) */
-  { "rADF", OR1K_OPERAND_RADF, HW_H_FDR, 25, 5,
-    { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+/* rADF: or64 source register A (double floating point mode) */
+  { "rADF", OR1K_OPERAND_RADF, HW_H_FDR, 20, 5,
+    { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } },
     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
-/* rBDF: source register B (double floating point mode) */
-  { "rBDF", OR1K_OPERAND_RBDF, HW_H_FDR, 25, 5,
-    { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+/* rBDF: or64 source register B (double floating point mode) */
+  { "rBDF", OR1K_OPERAND_RBDF, HW_H_FDR, 15, 5,
+    { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
+/* rDD32F: destination register (double floating point pair) */
+  { "rDD32F", OR1K_OPERAND_RDD32F, HW_H_FD32R, 10, 6,
+    { 2, { (const PTR) &OR1K_F_RDD32_MULTI_IFIELD[0] } },
+    { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
+/* rDDI: destination register (double integer pair) */
+  { "rDDI", OR1K_OPERAND_RDDI, HW_H_I64R, 10, 6,
+    { 2, { (const PTR) &OR1K_F_RDD32_MULTI_IFIELD[0] } },
+    { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
+/* rAD32F: source register A (double floating point pair) */
+  { "rAD32F", OR1K_OPERAND_RAD32F, HW_H_FD32R, 9, 6,
+    { 2, { (const PTR) &OR1K_F_RAD32_MULTI_IFIELD[0] } },
+    { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
+/* rADI: source register A (double integer pair) */
+  { "rADI", OR1K_OPERAND_RADI, HW_H_I64R, 9, 6,
+    { 2, { (const PTR) &OR1K_F_RAD32_MULTI_IFIELD[0] } },
+    { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
+/* rBD32F: source register B (double floating point pair) */
+  { "rBD32F", OR1K_OPERAND_RBD32F, HW_H_FD32R, 8, 6,
+    { 2, { (const PTR) &OR1K_F_RBD32_MULTI_IFIELD[0] } },
+    { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
+/* rBDI: source register B (double integer pair) */
+  { "rBDI", OR1K_OPERAND_RBDI, HW_H_I64R, 8, 6,
+    { 2, { (const PTR) &OR1K_F_RBD32_MULTI_IFIELD[0] } },
+    { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }  },
 /* sentinel */
   { 0, 0, 0, 0, 0,
     { 0, { (const PTR) 0 } },
@@ -1656,6 +1711,11 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
     OR1K_INSN_LF_ADD_D, "lf-add-d", "lf.add.d", 32,
     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
   },
+/* lf.add.d $rDD32F,$rAD32F,$rBD32F */
+  {
+    OR1K_INSN_LF_ADD_D32, "lf-add-d32", "lf.add.d", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+  },
 /* lf.sub.s $rDSF,$rASF,$rBSF */
   {
     OR1K_INSN_LF_SUB_S, "lf-sub-s", "lf.sub.s", 32,
@@ -1666,6 +1726,11 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
     OR1K_INSN_LF_SUB_D, "lf-sub-d", "lf.sub.d", 32,
     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
   },
+/* lf.sub.d $rDD32F,$rAD32F,$rBD32F */
+  {
+    OR1K_INSN_LF_SUB_D32, "lf-sub-d32", "lf.sub.d", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+  },
 /* lf.mul.s $rDSF,$rASF,$rBSF */
   {
     OR1K_INSN_LF_MUL_S, "lf-mul-s", "lf.mul.s", 32,
@@ -1676,6 +1741,11 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
     OR1K_INSN_LF_MUL_D, "lf-mul-d", "lf.mul.d", 32,
     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
   },
+/* lf.mul.d $rDD32F,$rAD32F,$rBD32F */
+  {
+    OR1K_INSN_LF_MUL_D32, "lf-mul-d32", "lf.mul.d", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+  },
 /* lf.div.s $rDSF,$rASF,$rBSF */
   {
     OR1K_INSN_LF_DIV_S, "lf-div-s", "lf.div.s", 32,
@@ -1686,6 +1756,11 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
     OR1K_INSN_LF_DIV_D, "lf-div-d", "lf.div.d", 32,
     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
   },
+/* lf.div.d $rDD32F,$rAD32F,$rBD32F */
+  {
+    OR1K_INSN_LF_DIV_D32, "lf-div-d32", "lf.div.d", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+  },
 /* lf.rem.s $rDSF,$rASF,$rBSF */
   {
     OR1K_INSN_LF_REM_S, "lf-rem-s", "lf.rem.s", 32,
@@ -1696,16 +1771,26 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
     OR1K_INSN_LF_REM_D, "lf-rem-d", "lf.rem.d", 32,
     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
   },
+/* lf.rem.d $rDD32F,$rAD32F,$rBD32F */
+  {
+    OR1K_INSN_LF_REM_D32, "lf-rem-d32", "lf.rem.d", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+  },
 /* lf.itof.s $rDSF,$rA */
   {
     OR1K_INSN_LF_ITOF_S, "lf-itof-s", "lf.itof.s", 32,
     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
   },
-/* lf.itof.d $rDSF,$rA */
+/* lf.itof.d $rDDF,$rA */
   {
     OR1K_INSN_LF_ITOF_D, "lf-itof-d", "lf.itof.d", 32,
     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
   },
+/* lf.itof.d $rDD32F,$rADI */
+  {
+    OR1K_INSN_LF_ITOF_D32, "lf-itof-d32", "lf.itof.d", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+  },
 /* lf.ftoi.s $rD,$rASF */
   {
     OR1K_INSN_LF_FTOI_S, "lf-ftoi-s", "lf.ftoi.s", 32,
@@ -1716,66 +1801,206 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
     OR1K_INSN_LF_FTOI_D, "lf-ftoi-d", "lf.ftoi.d", 32,
     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
   },
+/* lf.ftoi.d $rDDI,$rAD32F */
+  {
+    OR1K_INSN_LF_FTOI_D32, "lf-ftoi-d32", "lf.ftoi.d", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+  },
 /* lf.sfeq.s $rASF,$rBSF */
   {
-    OR1K_INSN_LF_EQ_S, "lf-eq-s", "lf.sfeq.s", 32,
+    OR1K_INSN_LF_SFEQ_S, "lf-sfeq-s", "lf.sfeq.s", 32,
     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
   },
-/* lf.sfeq.d $rASF,$rBSF */
+/* lf.sfeq.d $rADF,$rBDF */
   {
-    OR1K_INSN_LF_EQ_D, "lf-eq-d", "lf.sfeq.d", 32,
+    OR1K_INSN_LF_SFEQ_D, "lf-sfeq-d", "lf.sfeq.d", 32,
     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
   },
+/* lf.sfeq.d $rAD32F,$rBD32F */
+  {
+    OR1K_INSN_LF_SFEQ_D32, "lf-sfeq-d32", "lf.sfeq.d", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+  },
 /* lf.sfne.s $rASF,$rBSF */
   {
-    OR1K_INSN_LF_NE_S, "lf-ne-s", "lf.sfne.s", 32,
+    OR1K_INSN_LF_SFNE_S, "lf-sfne-s", "lf.sfne.s", 32,
     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
   },
-/* lf.sfne.d $rASF,$rBSF */
+/* lf.sfne.d $rADF,$rBDF */
   {
-    OR1K_INSN_LF_NE_D, "lf-ne-d", "lf.sfne.d", 32,
+    OR1K_INSN_LF_SFNE_D, "lf-sfne-d", "lf.sfne.d", 32,
     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
   },
+/* lf.sfne.d $rAD32F,$rBD32F */
+  {
+    OR1K_INSN_LF_SFNE_D32, "lf-sfne-d32", "lf.sfne.d", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+  },
 /* lf.sfge.s $rASF,$rBSF */
   {
-    OR1K_INSN_LF_GE_S, "lf-ge-s", "lf.sfge.s", 32,
+    OR1K_INSN_LF_SFGE_S, "lf-sfge-s", "lf.sfge.s", 32,
     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
   },
-/* lf.sfge.d $rASF,$rBSF */
+/* lf.sfge.d $rADF,$rBDF */
   {
-    OR1K_INSN_LF_GE_D, "lf-ge-d", "lf.sfge.d", 32,
+    OR1K_INSN_LF_SFGE_D, "lf-sfge-d", "lf.sfge.d", 32,
     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
   },
+/* lf.sfge.d $rAD32F,$rBD32F */
+  {
+    OR1K_INSN_LF_SFGE_D32, "lf-sfge-d32", "lf.sfge.d", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+  },
 /* lf.sfgt.s $rASF,$rBSF */
   {
-    OR1K_INSN_LF_GT_S, "lf-gt-s", "lf.sfgt.s", 32,
+    OR1K_INSN_LF_SFGT_S, "lf-sfgt-s", "lf.sfgt.s", 32,
     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
   },
-/* lf.sfgt.d $rASF,$rBSF */
+/* lf.sfgt.d $rADF,$rBDF */
   {
-    OR1K_INSN_LF_GT_D, "lf-gt-d", "lf.sfgt.d", 32,
+    OR1K_INSN_LF_SFGT_D, "lf-sfgt-d", "lf.sfgt.d", 32,
     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
   },
+/* lf.sfgt.d $rAD32F,$rBD32F */
+  {
+    OR1K_INSN_LF_SFGT_D32, "lf-sfgt-d32", "lf.sfgt.d", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+  },
 /* lf.sflt.s $rASF,$rBSF */
   {
-    OR1K_INSN_LF_LT_S, "lf-lt-s", "lf.sflt.s", 32,
+    OR1K_INSN_LF_SFLT_S, "lf-sflt-s", "lf.sflt.s", 32,
     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
   },
-/* lf.sflt.d $rASF,$rBSF */
+/* lf.sflt.d $rADF,$rBDF */
   {
-    OR1K_INSN_LF_LT_D, "lf-lt-d", "lf.sflt.d", 32,
+    OR1K_INSN_LF_SFLT_D, "lf-sflt-d", "lf.sflt.d", 32,
     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
   },
+/* lf.sflt.d $rAD32F,$rBD32F */
+  {
+    OR1K_INSN_LF_SFLT_D32, "lf-sflt-d32", "lf.sflt.d", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+  },
 /* lf.sfle.s $rASF,$rBSF */
   {
-    OR1K_INSN_LF_LE_S, "lf-le-s", "lf.sfle.s", 32,
+    OR1K_INSN_LF_SFLE_S, "lf-sfle-s", "lf.sfle.s", 32,
     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
   },
-/* lf.sfle.d $rASF,$rBSF */
+/* lf.sfle.d $rADF,$rBDF */
   {
-    OR1K_INSN_LF_LE_D, "lf-le-d", "lf.sfle.d", 32,
+    OR1K_INSN_LF_SFLE_D, "lf-sfle-d", "lf.sfle.d", 32,
     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
   },
+/* lf.sfle.d $rAD32F,$rBD32F */
+  {
+    OR1K_INSN_LF_SFLE_D32, "lf-sfle-d32", "lf.sfle.d", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+  },
+/* lf.sfueq.s $rASF,$rBSF */
+  {
+    OR1K_INSN_LF_SFUEQ_S, "lf-sfueq-s", "lf.sfueq.s", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+  },
+/* lf.sfueq.d $rADF,$rBDF */
+  {
+    OR1K_INSN_LF_SFUEQ_D, "lf-sfueq-d", "lf.sfueq.d", 32,
+    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+  },
+/* lf.sfueq.d $rAD32F,$rBD32F */
+  {
+    OR1K_INSN_LF_SFUEQ_D32, "lf-sfueq-d32", "lf.sfueq.d", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+  },
+/* lf.sfune.s $rASF,$rBSF */
+  {
+    OR1K_INSN_LF_SFUNE_S, "lf-sfune-s", "lf.sfune.s", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+  },
+/* lf.sfune.d $rADF,$rBDF */
+  {
+    OR1K_INSN_LF_SFUNE_D, "lf-sfune-d", "lf.sfune.d", 32,
+    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+  },
+/* lf.sfune.d $rAD32F,$rBD32F */
+  {
+    OR1K_INSN_LF_SFUNE_D32, "lf-sfune-d32", "lf.sfune.d", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+  },
+/* lf.sfugt.s $rASF,$rBSF */
+  {
+    OR1K_INSN_LF_SFUGT_S, "lf-sfugt-s", "lf.sfugt.s", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+  },
+/* lf.sfugt.d $rADF,$rBDF */
+  {
+    OR1K_INSN_LF_SFUGT_D, "lf-sfugt-d", "lf.sfugt.d", 32,
+    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+  },
+/* lf.sfugt.d $rAD32F,$rBD32F */
+  {
+    OR1K_INSN_LF_SFUGT_D32, "lf-sfugt-d32", "lf.sfugt.d", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+  },
+/* lf.sfuge.s $rASF,$rBSF */
+  {
+    OR1K_INSN_LF_SFUGE_S, "lf-sfuge-s", "lf.sfuge.s", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+  },
+/* lf.sfuge.d $rADF,$rBDF */
+  {
+    OR1K_INSN_LF_SFUGE_D, "lf-sfuge-d", "lf.sfuge.d", 32,
+    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+  },
+/* lf.sfuge.d $rAD32F,$rBD32F */
+  {
+    OR1K_INSN_LF_SFUGE_D32, "lf-sfuge-d32", "lf.sfuge.d", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+  },
+/* lf.sfult.s $rASF,$rBSF */
+  {
+    OR1K_INSN_LF_SFULT_S, "lf-sfult-s", "lf.sfult.s", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+  },
+/* lf.sfult.d $rADF,$rBDF */
+  {
+    OR1K_INSN_LF_SFULT_D, "lf-sfult-d", "lf.sfult.d", 32,
+    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+  },
+/* lf.sfult.d $rAD32F,$rBD32F */
+  {
+    OR1K_INSN_LF_SFULT_D32, "lf-sfult-d32", "lf.sfult.d", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+  },
+/* lf.sfule.s $rASF,$rBSF */
+  {
+    OR1K_INSN_LF_SFULE_S, "lf-sfule-s", "lf.sfule.s", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+  },
+/* lf.sfule.d $rADF,$rBDF */
+  {
+    OR1K_INSN_LF_SFULE_D, "lf-sfule-d", "lf.sfule.d", 32,
+    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+  },
+/* lf.sfule.d $rAD32F,$rBD32F */
+  {
+    OR1K_INSN_LF_SFULE_D32, "lf-sfule-d32", "lf.sfule.d", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+  },
+/* lf.sfun.s $rASF,$rBSF */
+  {
+    OR1K_INSN_LF_SFUN_S, "lf-sfun-s", "lf.sfun.s", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+  },
+/* lf.sfun.d $rADF,$rBDF */
+  {
+    OR1K_INSN_LF_SFUN_D, "lf-sfun-d", "lf.sfun.d", 32,
+    { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
+  },
+/* lf.sfun.d $rAD32F,$rBD32F */
+  {
+    OR1K_INSN_LF_SFUN_D32, "lf-sfun-d32", "lf.sfun.d", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+  },
 /* lf.madd.s $rDSF,$rASF,$rBSF */
   {
     OR1K_INSN_LF_MADD_S, "lf-madd-s", "lf.madd.s", 32,
@@ -1786,6 +2011,11 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
     OR1K_INSN_LF_MADD_D, "lf-madd-d", "lf.madd.d", 32,
     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
   },
+/* lf.madd.d $rDD32F,$rAD32F,$rBD32F */
+  {
+    OR1K_INSN_LF_MADD_D32, "lf-madd-d32", "lf.madd.d", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+  },
 /* lf.cust1.s $rASF,$rBSF */
   {
     OR1K_INSN_LF_CUST1_S, "lf-cust1-s", "lf.cust1.s", 32,
@@ -1796,6 +2026,11 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
     OR1K_INSN_LF_CUST1_D, "lf-cust1-d", "lf.cust1.d", 32,
     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
   },
+/* lf.cust1.d */
+  {
+    OR1K_INSN_LF_CUST1_D32, "lf-cust1-d32", "lf.cust1.d", 32,
+    { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+  },
 };
 
 #undef OP