MIPS16: Switch to 32-bit opcode table interpretation

Switch to 32-bit MIPS16 opcode table entry interpretation, similar to
how the microMIPS opcode table is handled, for both the `match' and
`mask' fields, removing special casing for JAL and JALX instructions and
their `a' and `i' operand codes throughout, while retaining automatic
processing of extendable opcodes in assembly and disassembly.

In assembly disallow size enforcement suffixes as appropriate: `.t' for
both 32-bit instructions and macros and `.e' for macros only, making
macro handling consistent with the microMIPS instruction set.

In disassembly fully decode EXTEND prefixes prepended to unsupported
instruction encodings (according to the ISA selection) rather than
dumping them as hexadecimal data along with the following instruction,
removing all special casing for the EXTEND prefix and making its
handling rely on its opcode table entry, except where it is considered a
part of an extendable instruction.

	include/
	* opcode/mips.h (mips_opcode_32bit_p): New inline function.

	gas/
	* config/tc-mips.c (micromips_insn_length): Use
	`mips_opcode_32bit_p'.
	(is_size_valid): Adjust description.
	(is_size_valid_16): New function.
	(validate_mips_insn): Use `mips_opcode_32bit_p' in MIPS16
	operand decoding.
	(validate_mips16_insn): Remove `a' and `i' operand code special
	casing, use `mips_opcode_32bit_p' to determine instruction
	width.
	(append_insn): Adjust forced MIPS16 instruction size
	determination.
	(match_mips16_insn): Likewise.  Don't shift the instruction's
	opcode with the `a' and `i' operand codes.  Use
	`mips_opcode_32bit_p' in operand decoding.
	(match_mips16_insns): Check for forced instruction size's
	validity.
	(mips16_ip): Don't force instruction size in the `noautoextend'
	mode.
	* testsuite/gas/mips/mips16-jal-e.d: New test.
	* testsuite/gas/mips/mips16-jal-t.d: New test.
	* testsuite/gas/mips/mips16-macro-e.d: New test.
	* testsuite/gas/mips/mips16-macro-t.d: New test.
	* testsuite/gas/mips/mips16-jal-t.l: New stderr output.
	* testsuite/gas/mips/mips16-macro-e.l: New stderr output.
	* testsuite/gas/mips/mips16-macro-t.l: New stderr output.
	* testsuite/gas/mips/mips16-jal-e.s: New test source.
	* testsuite/gas/mips/mips16-jal-t.s: New test source.
	* testsuite/gas/mips/mips16-macro-e.s: New test source.
	* testsuite/gas/mips/mips16-macro-t.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	opcodes/
	* mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
	`insn' together, with `extend' as the high-order 16 bits.
	(match_kind): New enum.
	(print_insn_mips16): Rework for 32-bit instruction matching.
	Do not dump EXTEND prefixes here.
	* mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
	Recode `match' and `mask' fields as 32-bit in absolute "jal" and
	"jalx" entries.

	binutils/
	* testsuite/binutils-all/mips/mips16-extend-noinsn.d: Adjust
	test for separate EXTEND prefix disassembly.

1 files changed, 5 insertions, 3 deletions

diff --git a/opcodes/mips16-opc.c b/opcodes/mips16-opc.c
index 0c4bb7f53d2..758b78fba62 100644
--- a/opcodes/mips16-opc.c
+++ b/opcodes/mips16-opc.c
@@ -273,13 +273,12 @@ const struct mips_opcode mips16_opcodes[] =
 {"exit",    "L",	0xef09, 0xff1f,		TRAP,			0,		I1,	0,	0 },
 {"entry",   "",		0xe809, 0xffff,		TRAP,			0,		I1,	0,	0 },
 {"entry",   "l",	0xe809, 0xf81f,		TRAP,			0,		I1,	0,	0 },
-{"extend",  "e",	0xf000, 0xf800,		0,			0,		I1,	0,	0 },
 {"jalr",    "x",	0xe840, 0xf8ff,		RD_1|WR_31|UBD,		0,		I1,	0,	0 },
 {"jalr",    "R,x",	0xe840, 0xf8ff,		RD_2|WR_31|UBD,		0,		I1,	0,	0 },
 {"jal",     "x",	0xe840, 0xf8ff,		RD_1|WR_31|UBD,		0,		I1,	0,	0 },
 {"jal",     "R,x",	0xe840, 0xf8ff,		RD_2|WR_31|UBD,		0,		I1,	0,	0 },
-{"jal",	    "a",	0x1800, 0xfc00,		WR_31|UBD,		0,		I1,	0,	0 },
-{"jalx",    "i",	0x1c00, 0xfc00,		WR_31|UBD,		0,		I1,	0,	0 },
+{"jal",	    "a",	0x18000000, 0xfc000000,	WR_31|UBD,		0,		I1,	0,	0 },
+{"jalx",    "i",	0x1c000000, 0xfc000000,	WR_31|UBD,		0,		I1,	0,	0 },
 {"jr",	    "x",	0xe800, 0xf8ff,		RD_1|UBD,		0,		I1,	0,	0 },
 {"jr",	    "R",	0xe820, 0xffff,		UBD,			RD_31,		I1,	0,	0 },
 {"j",	    "x",	0xe800, 0xf8ff,		RD_1|UBD,		0,		I1,	0,	0 },
@@ -356,6 +355,9 @@ const struct mips_opcode mips16_opcodes[] =
 {"zeb",	    "x",	0xe811, 0xf8ff,		MOD_1,			0,		I32,	0,	0 },
 {"zeh",	    "x",	0xe831, 0xf8ff,		MOD_1,			0,		I32,	0,	0 },
 {"zew",	    "x",	0xe851, 0xf8ff,		MOD_1,			0,		I64,	0,	0 },
+  /* Place EXTEND last so that it catches any prefix that didn't match
+     anything.  */
+{"extend",  "e",	0xf000, 0xf800,		0,			0,		I1,	0,	0 },
 };
 
 const int bfd_mips16_num_opcodes =