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authorDJ Delorie <dj@redhat.com>2009-05-22 17:37:45 +0000
committerDJ Delorie <dj@redhat.com>2009-05-22 17:37:45 +0000
commit1d74713bc6983fddbae51aed5337c0b88b0a672f (patch)
tree04746389866a2bc40caf9dfd7e5efd3ed24251a2 /opcodes/mep-ibld.c
parentc1e679ec0a47d39a315c7adb5e28106fcb27beac (diff)
downloadbinutils-gdb-1d74713bc6983fddbae51aed5337c0b88b0a672f.tar.gz
[cgen]
* cpu/mep.opc (mep_examine_ivc2_insns): Fix bug in ivc2 decoder. (mep_config_map): Regenerate. * cpu/mep-ivc2.cpu (h-ccr-ivc2): Add generic names as well as ivc2-specific names. (simm8p20): New. (cmovc): move to after field definitions, use ivc2-specific register names. (cpmovi_b_P0S_P1): New. [utils/mep] * mepcfgtool.c (do_cgen_config_opc): Propagate endianness and VLIW size to default configuration. [sid/component/cgen-cpu/mep] * mep-cop1-16-decode.cxx: Regenerate. * mep-cop1-16-decode.h: Regenerate. * mep-cop1-16-model.cxx: Regenerate. * mep-cop1-16-model.h: Regenerate. * mep-cop1-16-sem.cxx: Regenerate. * mep-cop1-64-decode.cxx: Regenerate. * mep-cop1-64-decode.h: Regenerate. * mep-cop1-64-model.cxx: Regenerate. * mep-cop1-64-model.h: Regenerate. * mep-cop1-64-sem.cxx: Regenerate. [opcodes] * mep-asm.c: Regenerate. * mep-desc.c: Regenerate. * mep-desc.h: Regenerate. * mep-dis.c: Regenerate. * mep-ibld.c: Regenerate. * mep-opc.c: Regenerate. * mep-opc.h: Regenerate.
Diffstat (limited to 'opcodes/mep-ibld.c')
-rw-r--r--opcodes/mep-ibld.c53
1 files changed, 53 insertions, 0 deletions
diff --git a/opcodes/mep-ibld.c b/opcodes/mep-ibld.c
index 69fedea5c81..bca40056771 100644
--- a/opcodes/mep-ibld.c
+++ b/opcodes/mep-ibld.c
@@ -878,6 +878,20 @@ mep_cgen_insert_operand (CGEN_CPU_DESC cd,
case MEP_OPERAND_IVC_X_6_3 :
errmsg = insert_normal (cd, fields->f_ivc2_3u6, 0, 0, 6, 3, 32, total_length, buffer);
break;
+ case MEP_OPERAND_IVC2C3CCRN :
+ {
+{
+ FLD (f_ccrn_hi) = ((((unsigned int) (FLD (f_ccrn)) >> (4))) & (3));
+ FLD (f_ccrn_lo) = ((FLD (f_ccrn)) & (15));
+}
+ errmsg = insert_normal (cd, fields->f_ccrn_hi, 0, 0, 28, 2, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_ccrn_lo, 0, 0, 4, 4, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
case MEP_OPERAND_IVC2CCRN :
{
{
@@ -1066,6 +1080,9 @@ mep_cgen_insert_operand (CGEN_CPU_DESC cd,
case MEP_OPERAND_SIMM8P0 :
errmsg = insert_normal (cd, fields->f_ivc2_8s0, 0|(1<<CGEN_IFLD_SIGNED), 0, 0, 8, 32, total_length, buffer);
break;
+ case MEP_OPERAND_SIMM8P20 :
+ errmsg = insert_normal (cd, fields->f_ivc2_8s20, 0|(1<<CGEN_IFLD_SIGNED), 0, 20, 8, 32, total_length, buffer);
+ break;
case MEP_OPERAND_SIMM8P4 :
errmsg = insert_normal (cd, fields->f_ivc2_8s4, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 32, total_length, buffer);
break;
@@ -1442,6 +1459,15 @@ mep_cgen_extract_operand (CGEN_CPU_DESC cd,
case MEP_OPERAND_IVC_X_6_3 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 3, 32, total_length, pc, & fields->f_ivc2_3u6);
break;
+ case MEP_OPERAND_IVC2C3CCRN :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 2, 32, total_length, pc, & fields->f_ccrn_hi);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_ccrn_lo);
+ if (length <= 0) break;
+ FLD (f_ccrn) = ((((FLD (f_ccrn_hi)) << (4))) | (FLD (f_ccrn_lo)));
+ }
+ break;
case MEP_OPERAND_IVC2CCRN :
{
length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 2, 32, total_length, pc, & fields->f_ivc2_ccrn_h2);
@@ -1609,6 +1635,9 @@ mep_cgen_extract_operand (CGEN_CPU_DESC cd,
case MEP_OPERAND_SIMM8P0 :
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 0, 8, 32, total_length, pc, & fields->f_ivc2_8s0);
break;
+ case MEP_OPERAND_SIMM8P20 :
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 20, 8, 32, total_length, pc, & fields->f_ivc2_8s20);
+ break;
case MEP_OPERAND_SIMM8P4 :
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 32, total_length, pc, & fields->f_ivc2_8s4);
break;
@@ -1888,6 +1917,9 @@ mep_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MEP_OPERAND_IVC_X_6_3 :
value = fields->f_ivc2_3u6;
break;
+ case MEP_OPERAND_IVC2C3CCRN :
+ value = fields->f_ccrn;
+ break;
case MEP_OPERAND_IVC2CCRN :
value = fields->f_ivc2_ccrn;
break;
@@ -2020,6 +2052,9 @@ mep_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MEP_OPERAND_SIMM8P0 :
value = fields->f_ivc2_8s0;
break;
+ case MEP_OPERAND_SIMM8P20 :
+ value = fields->f_ivc2_8s20;
+ break;
case MEP_OPERAND_SIMM8P4 :
value = fields->f_ivc2_8s4;
break;
@@ -2265,6 +2300,9 @@ mep_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MEP_OPERAND_IVC_X_6_3 :
value = fields->f_ivc2_3u6;
break;
+ case MEP_OPERAND_IVC2C3CCRN :
+ value = fields->f_ccrn;
+ break;
case MEP_OPERAND_IVC2CCRN :
value = fields->f_ivc2_ccrn;
break;
@@ -2397,6 +2435,9 @@ mep_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MEP_OPERAND_SIMM8P0 :
value = fields->f_ivc2_8s0;
break;
+ case MEP_OPERAND_SIMM8P20 :
+ value = fields->f_ivc2_8s20;
+ break;
case MEP_OPERAND_SIMM8P4 :
value = fields->f_ivc2_8s4;
break;
@@ -2643,6 +2684,9 @@ mep_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MEP_OPERAND_IVC_X_6_3 :
fields->f_ivc2_3u6 = value;
break;
+ case MEP_OPERAND_IVC2C3CCRN :
+ fields->f_ccrn = value;
+ break;
case MEP_OPERAND_IVC2CCRN :
fields->f_ivc2_ccrn = value;
break;
@@ -2763,6 +2807,9 @@ mep_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MEP_OPERAND_SIMM8P0 :
fields->f_ivc2_8s0 = value;
break;
+ case MEP_OPERAND_SIMM8P20 :
+ fields->f_ivc2_8s20 = value;
+ break;
case MEP_OPERAND_SIMM8P4 :
fields->f_ivc2_8s4 = value;
break;
@@ -2994,6 +3041,9 @@ mep_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MEP_OPERAND_IVC_X_6_3 :
fields->f_ivc2_3u6 = value;
break;
+ case MEP_OPERAND_IVC2C3CCRN :
+ fields->f_ccrn = value;
+ break;
case MEP_OPERAND_IVC2CCRN :
fields->f_ivc2_ccrn = value;
break;
@@ -3114,6 +3164,9 @@ mep_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MEP_OPERAND_SIMM8P0 :
fields->f_ivc2_8s0 = value;
break;
+ case MEP_OPERAND_SIMM8P20 :
+ fields->f_ivc2_8s20 = value;
+ break;
case MEP_OPERAND_SIMM8P4 :
fields->f_ivc2_8s4 = value;
break;