Add support for M340 part.

1 files changed, 30 insertions, 1 deletions

diff --git a/opcodes/mcore-dis.c b/opcodes/mcore-dis.c
index 518ef5b6930..096cec9aec0 100644
--- a/opcodes/mcore-dis.c
+++ b/opcodes/mcore-dis.c
@@ -1,5 +1,5 @@
 /* Disassemble Motorola M*Core instructions.
-   Copyright (C) 1993, 1999 Free Software Foundation, Inc.
+   Copyright (C) 1993, 1999, 2000 Free Software Foundation, Inc.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -57,6 +57,9 @@ static const unsigned short imsk[] =
     /* OMc */ 0xFF00,
     /* SIa */ 0xFE00,
 
+  /* MULSH */ 0xFF00,    
+  /* OPSR  */ 0xFFF8,   /* psrset/psrclr */
+		 
     /* JC  */ 0,		/* JC,JU,JL don't appear in object */
     /* JU  */ 0,
     /* JL  */ 0,
@@ -105,7 +108,12 @@ print_insn_mcore (memaddr, info)
       return -1;
     }
 
+  if (info->endian == BFD_ENDIAN_BIG)
     inst = (ibytes[0] << 8) | ibytes[1];
+  else if (info->endian == BFD_ENDIAN_LITTLE)
+    inst = (ibytes[1] << 8) | ibytes[0];
+  else
+    abort ();
 
   /* Just a linear search of the table.  */
   for (op = mcore_table; op->name != 0; op ++)
@@ -129,6 +137,7 @@ print_insn_mcore (memaddr, info)
 	case JSR: fprintf (stream, "\t%s", name); break;
 	case OC:  fprintf (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]); break;
 	case O1R1: fprintf (stream, "\t%s, r1", name); break;
+	case MULSH:
 	case O2: fprintf (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]); break;
 	case X1: fprintf (stream, "\tr1, %s", name); break;
 	case OI: fprintf (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1); break;
@@ -193,6 +202,10 @@ print_insn_mcore (memaddr, info)
 		break;
 	      }
 	    
+	    if (info->endian == BFD_ENDIAN_LITTLE)
+	      val = (ibytes[3] << 24) | (ibytes[2] << 16)
+		| (ibytes[1] << 8) | (ibytes[0]);
+	    else
 	      val = (ibytes[0] << 24) | (ibytes[1] << 16)
 		| (ibytes[2] << 8) | (ibytes[3]);
 	    
@@ -218,6 +231,10 @@ print_insn_mcore (memaddr, info)
 		break;
 	      }
 
+	    if (info->endian == BFD_ENDIAN_LITTLE)
+	      val = (ibytes[3] << 24) | (ibytes[2] << 16)
+		| (ibytes[1] << 8) | (ibytes[0]);
+	    else
 	      val = (ibytes[0] << 24) | (ibytes[1] << 16)
 		| (ibytes[2] << 8) | (ibytes[3]);
 	    
@@ -237,6 +254,18 @@ print_insn_mcore (memaddr, info)
 	  }
 	  break;
 	  
+	case OPSR:
+	  {
+	    static char * fields[] = 
+	    {
+	      "af", "ie",    "fe",    "fe,ie", 
+	      "ee", "ee,ie", "ee,fe", "ee,fe,ie"
+	    };
+	    
+	    fprintf (stream, "\t%s", fields[inst & 0x7]);
+	  }
+	  break;
+	  
 	default:
 	  /* if the disassembler lags the instruction set */
 	  fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst);