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authorDoug Evans <dje@google.com>1999-10-05 00:05:52 +0000
committerDoug Evans <dje@google.com>1999-10-05 00:05:52 +0000
commit1fa60b5dde8d6e82e4c8589c1b76b4b8a8730f22 (patch)
tree471599c575886f9e3aa0f8a62b0b23473f4fcb13 /opcodes/m32r-opc.h
parent103f02d372fd3f4960fb51cc3b83bbb98dc64ec1 (diff)
downloadbinutils-gdb-1fa60b5dde8d6e82e4c8589c1b76b4b8a8730f22.tar.gz
* fr30-asm.c,fr30-desc.h: Rebuild.
* m32r-asm.c,m32r-desc.c,m32r-desc.h: Rebuild. Add m32rx support. * m32r-dis.c,m32r-ibld.c,m32r-opc.c,m32r-opc.h,m32r-opinst.c: Ditto.
Diffstat (limited to 'opcodes/m32r-opc.h')
-rw-r--r--opcodes/m32r-opc.h53
1 files changed, 29 insertions, 24 deletions
diff --git a/opcodes/m32r-opc.h b/opcodes/m32r-opc.h
index 6c57daa8f9c..f92a33278d6 100644
--- a/opcodes/m32r-opc.h
+++ b/opcodes/m32r-opc.h
@@ -47,37 +47,34 @@ typedef enum cgen_insn_type {
, M32R_INSN_ADDX, M32R_INSN_BC8, M32R_INSN_BC24, M32R_INSN_BEQ
, M32R_INSN_BEQZ, M32R_INSN_BGEZ, M32R_INSN_BGTZ, M32R_INSN_BLEZ
, M32R_INSN_BLTZ, M32R_INSN_BNEZ, M32R_INSN_BL8, M32R_INSN_BL24
- , M32R_INSN_BNC8, M32R_INSN_BNC24, M32R_INSN_BNE, M32R_INSN_BRA8
- , M32R_INSN_BRA24
- , M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU, M32R_INSN_CMPUI
- , M32R_INSN_DIV, M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU
- , M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD, M32R_INSN_LD_D
- , M32R_INSN_LDB, M32R_INSN_LDB_D, M32R_INSN_LDH, M32R_INSN_LDH_D
- , M32R_INSN_LDUB, M32R_INSN_LDUB_D, M32R_INSN_LDUH, M32R_INSN_LDUH_D
- , M32R_INSN_LD_PLUS, M32R_INSN_LD24, M32R_INSN_LDI8, M32R_INSN_LDI16
- , M32R_INSN_LOCK, M32R_INSN_MACHI
- , M32R_INSN_MACLO
- , M32R_INSN_MACWHI
- , M32R_INSN_MACWLO
- , M32R_INSN_MUL, M32R_INSN_MULHI
- , M32R_INSN_MULLO
- , M32R_INSN_MULWHI
- , M32R_INSN_MULWLO
- , M32R_INSN_MV, M32R_INSN_MVFACHI
- , M32R_INSN_MVFACLO
- , M32R_INSN_MVFACMI
- , M32R_INSN_MVFC, M32R_INSN_MVTACHI
- , M32R_INSN_MVTACLO
+ , M32R_INSN_BCL8, M32R_INSN_BCL24, M32R_INSN_BNC8, M32R_INSN_BNC24
+ , M32R_INSN_BNE, M32R_INSN_BRA8, M32R_INSN_BRA24, M32R_INSN_BNCL8
+ , M32R_INSN_BNCL24, M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU
+ , M32R_INSN_CMPUI, M32R_INSN_CMPEQ, M32R_INSN_CMPZ, M32R_INSN_DIV
+ , M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU, M32R_INSN_DIVH
+ , M32R_INSN_JC, M32R_INSN_JNC, M32R_INSN_JL, M32R_INSN_JMP
+ , M32R_INSN_LD, M32R_INSN_LD_D, M32R_INSN_LDB, M32R_INSN_LDB_D
+ , M32R_INSN_LDH, M32R_INSN_LDH_D, M32R_INSN_LDUB, M32R_INSN_LDUB_D
+ , M32R_INSN_LDUH, M32R_INSN_LDUH_D, M32R_INSN_LD_PLUS, M32R_INSN_LD24
+ , M32R_INSN_LDI8, M32R_INSN_LDI16, M32R_INSN_LOCK, M32R_INSN_MACHI
+ , M32R_INSN_MACHI_A, M32R_INSN_MACLO, M32R_INSN_MACLO_A, M32R_INSN_MACWHI
+ , M32R_INSN_MACWHI_A, M32R_INSN_MACWLO, M32R_INSN_MACWLO_A, M32R_INSN_MUL
+ , M32R_INSN_MULHI, M32R_INSN_MULHI_A, M32R_INSN_MULLO, M32R_INSN_MULLO_A
+ , M32R_INSN_MULWHI, M32R_INSN_MULWHI_A, M32R_INSN_MULWLO, M32R_INSN_MULWLO_A
+ , M32R_INSN_MV, M32R_INSN_MVFACHI, M32R_INSN_MVFACHI_A, M32R_INSN_MVFACLO
+ , M32R_INSN_MVFACLO_A, M32R_INSN_MVFACMI, M32R_INSN_MVFACMI_A, M32R_INSN_MVFC
+ , M32R_INSN_MVTACHI, M32R_INSN_MVTACHI_A, M32R_INSN_MVTACLO, M32R_INSN_MVTACLO_A
, M32R_INSN_MVTC, M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT
- , M32R_INSN_RAC
- , M32R_INSN_RACH
+ , M32R_INSN_RAC, M32R_INSN_RAC_DSI, M32R_INSN_RACH, M32R_INSN_RACH_DSI
, M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3
, M32R_INSN_SLLI, M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI
, M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST
, M32R_INSN_ST_D, M32R_INSN_STB, M32R_INSN_STB_D, M32R_INSN_STH
, M32R_INSN_STH_D, M32R_INSN_ST_PLUS, M32R_INSN_ST_MINUS, M32R_INSN_SUB
, M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP, M32R_INSN_UNLOCK
- , M32R_INSN_MAX
+ , M32R_INSN_SATB, M32R_INSN_SATH, M32R_INSN_SAT, M32R_INSN_PCMPBZ
+ , M32R_INSN_SADD, M32R_INSN_MACWU1, M32R_INSN_MSBLO, M32R_INSN_MULWU1
+ , M32R_INSN_MACLH1, M32R_INSN_SC, M32R_INSN_SNC, M32R_INSN_MAX
} CGEN_INSN_TYPE;
/* Index of `invalid' insn place holder. */
@@ -107,6 +104,14 @@ struct cgen_fields
long f_disp8;
long f_disp16;
long f_disp24;
+ long f_op23;
+ long f_op3;
+ long f_acc;
+ long f_accs;
+ long f_accd;
+ long f_bits67;
+ long f_bit14;
+ long f_imm1;
};
#define CGEN_INIT_PARSE(od) \