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| author | Jan Beulich <jbeulich@suse.com> | 2020-07-14 10:28:12 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2020-07-14 10:28:12 +0200 |
| commit | b24d668c078f65c8f092557ef4fca63a18df8280 (patch) | |
| tree | 5885d23e44c59309d173eba737324ec3ae3ee75d /opcodes/i386-dis-evex-w.h | |
| parent | c4de76066e9c6fa42d6f02c6519d2c6bbe0cc983 (diff) | |
| download | binutils-gdb-b24d668c078f65c8f092557ef4fca63a18df8280.tar.gz | |
x86-64: fix {,V}PCMPESTR{I,M} disassembly in Intel mode
The operands don't allow disambiguating the insn in 64-bit mode, and
hence suffixes need to be emitted not just in AT&T mode. Achieve this
by re-using %LQ while dropping PCMPESTR_Fixup().
Diffstat (limited to 'opcodes/i386-dis-evex-w.h')
| -rw-r--r-- | opcodes/i386-dis-evex-w.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h index f7460efccd4..2d92290b885 100644 --- a/opcodes/i386-dis-evex-w.h +++ b/opcodes/i386-dis-evex-w.h @@ -39,8 +39,8 @@ }, /* EVEX_W_0F2A_P_3 */ { - { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ed }, 0 }, - { "vcvtsi2sd%LQ", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 }, + { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, Ed }, 0 }, + { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 }, }, /* EVEX_W_0F51_P_1 */ { @@ -245,8 +245,8 @@ }, /* EVEX_W_0F7B_P_3 */ { - { "vcvtusi2sd%LQ", { XMScalar, VexScalar, Ed }, 0 }, - { "vcvtusi2sd%LQ", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 }, + { "vcvtusi2sd{%LQ|}", { XMScalar, VexScalar, Ed }, 0 }, + { "vcvtusi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 }, }, /* EVEX_W_0F7E_P_1 */ { |