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| author | Jan Beulich <jbeulich@suse.com> | 2020-07-14 10:33:40 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2020-07-14 10:33:40 +0200 |
| commit | 7531c61332dbd9061b09312e44b62523547e8225 (patch) | |
| tree | b6263d54a1222a908ece3bd2612cd1fbf5dea945 /opcodes/i386-dis-evex-reg.h | |
| parent | 17d3c7eccd41c5053c0b567eb67fe59808cc748a (diff) | |
| download | binutils-gdb-7531c61332dbd9061b09312e44b62523547e8225.tar.gz | |
x86: simplify decode of opcodes valid with (embedded) 66 prefix only
The only valid (embedded or explicit) prefix being the data size one
(which is a fairly common pattern), avoid going through prefix_table[].
Instead extend the "required prefix" logic to also handle PREFIX_DATA
alone in a table entry, now used to identify this case. This requires
moving the (adjusted) ->prefix_requirement logic ahead of the printing
of stray prefixes, as the latter needs to observe the new setting of
PREFIX_DATA in used_prefixes.
Also add PREFIX_OPCODE on related entries when previously there was
mistakenly no decode step through prefix_table[].
Diffstat (limited to 'opcodes/i386-dis-evex-reg.h')
| -rw-r--r-- | opcodes/i386-dis-evex-reg.h | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/opcodes/i386-dis-evex-reg.h b/opcodes/i386-dis-evex-reg.h index 9647e30db39..1ed79264ebb 100644 --- a/opcodes/i386-dis-evex-reg.h +++ b/opcodes/i386-dis-evex-reg.h @@ -2,32 +2,32 @@ { { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_EVEX_0F71_REG_2) }, + { "vpsrlw", { Vex, EXx, Ib }, PREFIX_DATA }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_EVEX_0F71_REG_4) }, + { "vpsraw", { Vex, EXx, Ib }, PREFIX_DATA }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_EVEX_0F71_REG_6) }, + { "vpsllw", { Vex, EXx, Ib }, PREFIX_DATA }, }, /* REG_EVEX_0F72 */ { - { PREFIX_TABLE (PREFIX_EVEX_0F72_REG_0) }, - { PREFIX_TABLE (PREFIX_EVEX_0F72_REG_1) }, - { PREFIX_TABLE (PREFIX_EVEX_0F72_REG_2) }, + { "vpror%DQ", { Vex, EXx, Ib }, PREFIX_DATA }, + { "vprol%DQ", { Vex, EXx, Ib }, PREFIX_DATA }, + { VEX_W_TABLE (EVEX_W_0F72_R_2) }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_EVEX_0F72_REG_4) }, + { "vpsra%DQ", { Vex, EXx, Ib }, PREFIX_DATA }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_EVEX_0F72_REG_6) }, + { VEX_W_TABLE (EVEX_W_0F72_R_6) }, }, /* REG_EVEX_0F73 */ { { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_EVEX_0F73_REG_2) }, - { PREFIX_TABLE (PREFIX_EVEX_0F73_REG_3) }, + { VEX_W_TABLE (EVEX_W_0F73_R_2) }, + { "vpsrldq", { Vex, EXx, Ib }, PREFIX_DATA }, { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_EVEX_0F73_REG_6) }, - { PREFIX_TABLE (PREFIX_EVEX_0F73_REG_7) }, + { VEX_W_TABLE (EVEX_W_0F73_R_6) }, + { "vpslldq", { Vex, EXx, Ib }, PREFIX_DATA }, }, /* REG_EVEX_0F38C6 */ { |