Use bool in opcodes

cpu/
	* frv.opc: Replace bfd_boolean with bool, FALSE with false, and
	TRUE with true throughout.
opcodes/
	* sysdep.h (POISON_BFD_BOOLEAN): Define.
	* aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
	* aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
	* aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
	* arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
	* cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
	* disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
	* i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
	* microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
	* mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
	* msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
	* ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
	* tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
	* xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
	and TRUE with true throughout.

1 files changed, 330 insertions, 330 deletions

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 2f3f19ba1cb..797998722cf 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -5252,7 +5252,7 @@ enum vpt_pred_state
 struct vpt_block
 {
   /* Are we in a vpt block.  */
-  bfd_boolean in_vpt_block;
+  bool in_vpt_block;
 
   /* Next predicate state if in vpt block.  */
   enum vpt_pred_state next_pred_state;
@@ -5269,7 +5269,7 @@ struct vpt_block
 
 static struct vpt_block vpt_block_state =
 {
-  FALSE,
+  false,
   PRED_NONE,
   0,
   0,
@@ -5282,7 +5282,7 @@ static unsigned int regname_selected = 1;
 #define NUM_ARM_OPTIONS   ARRAY_SIZE (regnames)
 #define arm_regnames      regnames[regname_selected].reg_names
 
-static bfd_boolean force_thumb = FALSE;
+static bool force_thumb = false;
 static uint16_t cde_coprocs = 0;
 
 /* Current IT instruction state.  This contains the same state as the IT
@@ -5334,7 +5334,7 @@ num_instructions_vpt_block (long given)
 static void
 mark_outside_vpt_block (void)
 {
-  vpt_block_state.in_vpt_block = FALSE;
+  vpt_block_state.in_vpt_block = false;
   vpt_block_state.next_pred_state = PRED_NONE;
   vpt_block_state.predicate_mask = 0;
   vpt_block_state.current_insn_num = 0;
@@ -5344,7 +5344,7 @@ mark_outside_vpt_block (void)
 static void
 mark_inside_vpt_block (long given)
 {
-  vpt_block_state.in_vpt_block = TRUE;
+  vpt_block_state.in_vpt_block = true;
   vpt_block_state.next_pred_state = PRED_THEN;
   vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
   vpt_block_state.current_insn_num = 0;
@@ -5448,7 +5448,7 @@ arm_decode_bitfield (const char *ptr,
 
 static void
 arm_decode_shift (long given, fprintf_ftype func, void *stream,
-		  bfd_boolean print_shift)
+		  bool print_shift)
 {
   func (stream, "%s", arm_regnames[given & 0xf]);
 
@@ -5487,7 +5487,7 @@ arm_decode_shift (long given, fprintf_ftype func, void *stream,
 
 /* Return TRUE if the MATCHED_INSN can be inside an IT block.  */
 
-static bfd_boolean
+static bool
 is_mve_okay_in_it (enum mve_instructions matched_insn)
 {
   switch (matched_insn)
@@ -5513,13 +5513,13 @@ is_mve_okay_in_it (enum mve_instructions matched_insn)
     case MVE_SRSHR:
     case MVE_SQSHLL:
     case MVE_SQSHL:
-      return TRUE;
+      return true;
     default:
-      return FALSE;
+      return false;
     }
 }
 
-static bfd_boolean
+static bool
 is_mve_architecture (struct disassemble_info *info)
 {
   struct arm_private_data *private_data = info->private_data;
@@ -5530,18 +5530,18 @@ is_mve_architecture (struct disassemble_info *info)
 
   if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
       && !ARM_CPU_IS_ANY (allowed_arches))
-    return TRUE;
+    return true;
   else
-    return FALSE;
+    return false;
 }
 
-static bfd_boolean
+static bool
 is_vpt_instruction (long given)
 {
 
   /* If mkh:mkl is '0000' then its not a vpt/vpst instruction.  */
   if ((given & 0x0040e000) == 0)
-    return FALSE;
+    return false;
 
   /* VPT floating point T1 variant.  */
   if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
@@ -5562,9 +5562,9 @@ is_vpt_instruction (long given)
       || ((given & 0xff811f50) == 0xfe011f40)
   /* VPST vector T variant.  */
       || ((given & 0xffbf1fff) == 0xfe310f4d))
-    return TRUE;
+    return true;
   else
-    return FALSE;
+    return false;
 }
 
 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
@@ -5609,7 +5609,7 @@ arm_decode_field_multiple (unsigned long given, unsigned int start,
    This helps us decode instructions that change mnemonic depending on specific
    operand values/encodings.  */
 
-static bfd_boolean
+static bool
 is_mve_encoding_conflict (unsigned long given,
 			  enum mve_instructions matched_insn)
 {
@@ -5617,24 +5617,24 @@ is_mve_encoding_conflict (unsigned long given,
     {
     case MVE_VPST:
       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
-	return TRUE;
+	return true;
       else
-	return FALSE;
+	return false;
 
     case MVE_VPT_FP_T1:
       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
-	return TRUE;
+	return true;
       if ((arm_decode_field (given, 12, 12) == 0)
 	  && (arm_decode_field (given, 0, 0) == 1))
-	return TRUE;
-      return FALSE;
+	return true;
+      return false;
 
     case MVE_VPT_FP_T2:
       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
-	return TRUE;
+	return true;
       if (arm_decode_field (given, 0, 3) == 0xd)
-	return TRUE;
-      return FALSE;
+	return true;
+      return false;
 
     case MVE_VPT_VEC_T1:
     case MVE_VPT_VEC_T2:
@@ -5643,23 +5643,23 @@ is_mve_encoding_conflict (unsigned long given,
     case MVE_VPT_VEC_T5:
     case MVE_VPT_VEC_T6:
       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
-	return TRUE;
+	return true;
       if (arm_decode_field (given, 20, 21) == 3)
-	return TRUE;
-      return FALSE;
+	return true;
+      return false;
 
     case MVE_VCMP_FP_T1:
       if ((arm_decode_field (given, 12, 12) == 0)
 	  && (arm_decode_field (given, 0, 0) == 1))
-	return TRUE;
+	return true;
       else
-	return FALSE;
+	return false;
 
     case MVE_VCMP_FP_T2:
       if (arm_decode_field (given, 0, 3) == 0xd)
-	return TRUE;
+	return true;
       else
-	return FALSE;
+	return false;
 
     case MVE_VQADD_T2:
     case MVE_VQSUB_T2:
@@ -5702,30 +5702,30 @@ is_mve_encoding_conflict (unsigned long given,
     case MVE_VCMP_VEC_T5:
     case MVE_VCMP_VEC_T6:
       if (arm_decode_field (given, 20, 21) == 3)
-	return TRUE;
+	return true;
       else
-	return FALSE;
+	return false;
 
     case MVE_VLD2:
     case MVE_VLD4:
     case MVE_VST2:
     case MVE_VST4:
       if (arm_decode_field (given, 7, 8) == 3)
-	return TRUE;
+	return true;
       else
-	return FALSE;
+	return false;
 
     case MVE_VSTRB_T1:
     case MVE_VSTRH_T2:
       if ((arm_decode_field (given, 24, 24) == 0)
 	  && (arm_decode_field (given, 21, 21) == 0))
 	{
-	    return TRUE;
+	    return true;
 	}
       else if ((arm_decode_field (given, 7, 8) == 3))
-	return TRUE;
+	return true;
       else
-	return FALSE;
+	return false;
 
     case MVE_VSTRB_T5:
     case MVE_VSTRH_T6:
@@ -5733,10 +5733,10 @@ is_mve_encoding_conflict (unsigned long given,
       if ((arm_decode_field (given, 24, 24) == 0)
 	  && (arm_decode_field (given, 21, 21) == 0))
 	{
-	    return TRUE;
+	    return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VCVT_FP_FIX_VEC:
       return (arm_decode_field (given, 16, 21) & 0x38) == 0;
@@ -5747,11 +5747,11 @@ is_mve_encoding_conflict (unsigned long given,
 	unsigned long cmode = arm_decode_field (given, 8, 11);
 
 	if ((cmode & 1) == 0)
-	  return TRUE;
+	  return true;
 	else if ((cmode & 0xc) == 0xc)
-	  return TRUE;
+	  return true;
 	else
-	  return FALSE;
+	  return false;
       }
 
     case MVE_VMVN_IMM:
@@ -5759,29 +5759,29 @@ is_mve_encoding_conflict (unsigned long given,
 	unsigned long cmode = arm_decode_field (given, 8, 11);
 
 	if (cmode == 0xe)
-	  return TRUE;
+	  return true;
 	else if ((cmode & 0x9) == 1)
-	  return TRUE;
+	  return true;
 	else if ((cmode & 0xd) == 9)
-	  return TRUE;
+	  return true;
 	else
-	  return FALSE;
+	  return false;
       }
 
     case MVE_VMOV_IMM_TO_VEC:
       if ((arm_decode_field (given, 5, 5) == 1)
 	  && (arm_decode_field (given, 8, 11) != 0xe))
-	return TRUE;
+	return true;
       else
-	return FALSE;
+	return false;
 
     case MVE_VMOVL:
       {
 	unsigned long size = arm_decode_field (given, 19, 20);
 	if ((size == 0) || (size == 3))
-	  return TRUE;
+	  return true;
 	else
-	  return FALSE;
+	  return false;
       }
 
     case MVE_VMAXA:
@@ -5800,32 +5800,32 @@ is_mve_encoding_conflict (unsigned long given,
     case MVE_VQMOVUN:
     case MVE_VQMOVN:
       if (arm_decode_field (given, 18, 19) == 3)
-	return TRUE;
+	return true;
       else
-	return FALSE;
+	return false;
 
     case MVE_VMLSLDAV:
     case MVE_VRMLSLDAVH:
     case MVE_VMLALDAV:
     case MVE_VADDLV:
       if (arm_decode_field (given, 20, 22) == 7)
-	return TRUE;
+	return true;
       else
-	return FALSE;
+	return false;
 
     case MVE_VRMLALDAVH:
       if ((arm_decode_field (given, 20, 22) & 6) == 6)
-	return TRUE;
+	return true;
       else
-	return FALSE;
+	return false;
 
     case MVE_VDWDUP:
     case MVE_VIWDUP:
       if ((arm_decode_field (given, 20, 21) == 3)
 	  || (arm_decode_field (given, 1, 3) == 7))
-	return TRUE;
+	return true;
       else
-	return FALSE;
+	return false;
 
 
     case MVE_VSHLL_T1:
@@ -5834,12 +5834,12 @@ is_mve_encoding_conflict (unsigned long given,
 	  unsigned long sz = arm_decode_field (given, 19, 20);
 
 	  if ((sz == 1) || (sz == 2))
-	    return TRUE;
+	    return true;
 	  else
-	    return FALSE;
+	    return false;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VQSHL_T2:
     case MVE_VQSHLU_T3:
@@ -5849,15 +5849,15 @@ is_mve_encoding_conflict (unsigned long given,
     case MVE_VSLI:
     case MVE_VSRI:
       if (arm_decode_field (given, 19, 21) == 0)
-	return TRUE;
+	return true;
       else
-	return FALSE;
+	return false;
 
     case MVE_VCTP:
     if (arm_decode_field (given, 16, 19) == 0xf)
-      return TRUE;
+      return true;
     else
-      return FALSE;
+      return false;
 
     case MVE_ASRLI:
     case MVE_ASRL:
@@ -5871,9 +5871,9 @@ is_mve_encoding_conflict (unsigned long given,
     case MVE_UQSHLL:
     case MVE_URSHRL:
       if (arm_decode_field (given, 9, 11) == 0x7)
-	return TRUE;
+	return true;
       else
-	return FALSE;
+	return false;
 
     case MVE_CSINC:
     case MVE_CSINV:
@@ -5883,27 +5883,27 @@ is_mve_encoding_conflict (unsigned long given,
 	rn = arm_decode_field (given, 16, 19);
 	/* CSET/CSETM.  */
 	if (rm == 0xf && rn == 0xf)
-	  return TRUE;
+	  return true;
 	/* CINC/CINV.  */
 	else if (rn == rm && rn != 0xf)
-	  return TRUE;
+	  return true;
       }
     /* Fall through.  */
     case MVE_CSEL:
     case MVE_CSNEG:
       if (arm_decode_field (given, 0, 3) == 0xd)
-	return TRUE;
+	return true;
       /* CNEG.  */
       else if (matched_insn == MVE_CSNEG)
 	if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
-	  return TRUE;
-      return FALSE;
+	  return true;
+      return false;
 
     default:
     case MVE_VADD_FP_T1:
     case MVE_VADD_FP_T2:
     case MVE_VADD_VEC_T1:
-      return FALSE;
+      return false;
 
     }
 }
@@ -5986,7 +5986,7 @@ print_mve_vld_str_addr (struct disassemble_info *info,
    Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
    this encoding is undefined.  */
 
-static bfd_boolean
+static bool
 is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
 		  enum mve_undefined *undefined_code)
 {
@@ -5998,10 +5998,10 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
       if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
 	{
 	  *undefined_code = UNDEF_SIZE_3;
-	  return TRUE;
+	  return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VQADD_T1:
     case MVE_VQSUB_T1:
@@ -6017,118 +6017,118 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
       if (arm_decode_field (given, 20, 21) == 3)
 	{
 	  *undefined_code = UNDEF_SIZE_3;
-	  return TRUE;
+	  return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VLDRB_T1:
       if (arm_decode_field (given, 7, 8) == 3)
 	{
 	  *undefined_code = UNDEF_SIZE_3;
-	  return TRUE;
+	  return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VLDRH_T2:
       if (arm_decode_field (given, 7, 8) <= 1)
 	{
 	  *undefined_code = UNDEF_SIZE_LE_1;
-	  return TRUE;
+	  return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VSTRB_T1:
       if ((arm_decode_field (given, 7, 8) == 0))
 	{
 	  *undefined_code = UNDEF_SIZE_0;
-	  return TRUE;
+	  return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VSTRH_T2:
       if ((arm_decode_field (given, 7, 8) <= 1))
 	{
 	  *undefined_code = UNDEF_SIZE_LE_1;
-	  return TRUE;
+	  return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VLDRB_GATHER_T1:
       if (arm_decode_field (given, 7, 8) == 3)
 	{
 	  *undefined_code = UNDEF_SIZE_3;
-	  return TRUE;
+	  return true;
 	}
       else if ((arm_decode_field (given, 28, 28) == 0)
 	       && (arm_decode_field (given, 7, 8) == 0))
 	{
 	  *undefined_code = UNDEF_NOT_UNS_SIZE_0;
-	  return TRUE;
+	  return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VLDRH_GATHER_T2:
       if (arm_decode_field (given, 7, 8) == 3)
 	{
 	  *undefined_code = UNDEF_SIZE_3;
-	  return TRUE;
+	  return true;
 	}
       else if ((arm_decode_field (given, 28, 28) == 0)
 	       && (arm_decode_field (given, 7, 8) == 1))
 	{
 	  *undefined_code = UNDEF_NOT_UNS_SIZE_1;
-	  return TRUE;
+	  return true;
 	}
       else if (arm_decode_field (given, 7, 8) == 0)
 	{
 	  *undefined_code = UNDEF_SIZE_0;
-	  return TRUE;
+	  return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VLDRW_GATHER_T3:
       if (arm_decode_field (given, 7, 8) != 2)
 	{
 	  *undefined_code = UNDEF_SIZE_NOT_2;
-	  return TRUE;
+	  return true;
 	}
       else if (arm_decode_field (given, 28, 28) == 0)
 	{
 	  *undefined_code = UNDEF_NOT_UNSIGNED;
-	  return TRUE;
+	  return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VLDRD_GATHER_T4:
       if (arm_decode_field (given, 7, 8) != 3)
 	{
 	  *undefined_code = UNDEF_SIZE_NOT_3;
-	  return TRUE;
+	  return true;
 	}
       else if (arm_decode_field (given, 28, 28) == 0)
 	{
 	  *undefined_code = UNDEF_NOT_UNSIGNED;
-	  return TRUE;
+	  return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VSTRB_SCATTER_T1:
       if (arm_decode_field (given, 7, 8) == 3)
 	{
 	  *undefined_code = UNDEF_SIZE_3;
-	  return TRUE;
+	  return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VSTRH_SCATTER_T2:
       {
@@ -6136,34 +6136,34 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
 	if (size == 3)
 	  {
 	    *undefined_code = UNDEF_SIZE_3;
-	    return TRUE;
+	    return true;
 	  }
 	else if (size == 0)
 	  {
 	    *undefined_code = UNDEF_SIZE_0;
-	    return TRUE;
+	    return true;
 	  }
 	else
-	  return FALSE;
+	  return false;
       }
 
     case MVE_VSTRW_SCATTER_T3:
       if (arm_decode_field (given, 7, 8) != 2)
 	{
 	  *undefined_code = UNDEF_SIZE_NOT_2;
-	  return TRUE;
+	  return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VSTRD_SCATTER_T4:
       if (arm_decode_field (given, 7, 8) != 3)
 	{
 	  *undefined_code = UNDEF_SIZE_NOT_3;
-	  return TRUE;
+	  return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VCVT_FP_FIX_VEC:
       {
@@ -6171,17 +6171,17 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
 	if ((imm6 & 0x20) == 0)
 	  {
 	    *undefined_code = UNDEF_VCVT_IMM6;
-	    return TRUE;
+	    return true;
 	  }
 
 	if ((arm_decode_field (given, 9, 9) == 0)
 	    && ((imm6 & 0x30) == 0x20))
 	  {
 	    *undefined_code = UNDEF_VCVT_FSI_IMM6;
-	    return TRUE;
+	    return true;
 	  }
 
-	return FALSE;
+	return false;
       }
 
     case MVE_VNEG_FP:
@@ -6193,15 +6193,15 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
 	if (size == 0)
 	  {
 	    *undefined_code = UNDEF_SIZE_0;
-	    return TRUE;
+	    return true;
 	  }
 	else if (size == 3)
 	  {
 	    *undefined_code = UNDEF_SIZE_3;
-	    return TRUE;
+	    return true;
 	  }
 	else
-	  return FALSE;
+	  return false;
       }
 
     case MVE_VMOV_VEC_LANE_TO_GP:
@@ -6215,23 +6215,23 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
 	    if ((op1 == 0) || (op1 == 1))
 	      {
 		*undefined_code = UNDEF_BAD_U_OP1_OP2;
-		return TRUE;
+		return true;
 	      }
 	    else
-	      return FALSE;
+	      return false;
 	  }
 	else if (op2 == 2)
 	  {
 	    if ((op1 == 0) || (op1 == 1))
 	      {
 		*undefined_code = UNDEF_BAD_OP1_OP2;
-		return TRUE;
+		return true;
 	      }
 	    else
-	      return FALSE;
+	      return false;
 	  }
 
-	return FALSE;
+	return false;
       }
 
     case MVE_VMOV_GP_TO_VEC_LANE:
@@ -6241,19 +6241,19 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
 	  if ((op1 == 0) || (op1 == 1))
 	    {
 	      *undefined_code = UNDEF_BAD_OP1_OP2;
-	      return TRUE;
+	      return true;
 	    }
 	  else
-	    return FALSE;
+	    return false;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VMOV_VEC_TO_VEC:
       if ((arm_decode_field (given, 5, 5) == 1)
 	  || (arm_decode_field (given, 22, 22) == 1))
-	  return TRUE;
-      return FALSE;
+	  return true;
+      return false;
 
     case MVE_VMOV_IMM_TO_VEC:
       if (arm_decode_field (given, 5, 5) == 0)
@@ -6263,23 +6263,23 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
 	if (((cmode & 9) == 1) || ((cmode & 5) == 1))
 	  {
 	    *undefined_code = UNDEF_OP_0_BAD_CMODE;
-	    return TRUE;
+	    return true;
 	  }
 	else
-	  return FALSE;
+	  return false;
       }
       else
-	return FALSE;
+	return false;
 
     case MVE_VSHLL_T2:
     case MVE_VMOVN:
       if (arm_decode_field (given, 18, 19) == 2)
 	{
 	  *undefined_code = UNDEF_SIZE_2;
-	  return TRUE;
+	  return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VRMLALDAVH:
     case MVE_VMLADAV_T1:
@@ -6289,10 +6289,10 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
 	  && (arm_decode_field (given, 12, 12) == 1))
 	{
 	  *undefined_code = UNDEF_XCHG_UNS;
-	  return TRUE;
+	  return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VQSHRN:
     case MVE_VQSHRUN:
@@ -6301,13 +6301,13 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
       {
 	unsigned long sz = arm_decode_field (given, 19, 20);
 	if (sz == 1)
-	  return FALSE;
+	  return false;
 	else if ((sz & 2) == 2)
-	  return FALSE;
+	  return false;
 	else
 	  {
 	    *undefined_code = UNDEF_SIZE;
-	    return TRUE;
+	    return true;
 	  }
       }
       break;
@@ -6322,15 +6322,15 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
       {
 	unsigned long sz = arm_decode_field (given, 19, 21);
 	if ((sz & 7) == 1)
-	  return FALSE;
+	  return false;
 	else if ((sz & 6) == 2)
-	  return FALSE;
+	  return false;
 	else if ((sz & 4) == 4)
-	  return FALSE;
+	  return false;
 	else
 	  {
 	    *undefined_code = UNDEF_SIZE;
-	    return TRUE;
+	    return true;
 	  }
       }
 
@@ -6339,19 +6339,19 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
       if (arm_decode_field (given, 19, 20) == 0)
 	{
 	  *undefined_code = UNDEF_SIZE_0;
-	  return TRUE;
+	  return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VABS_VEC:
 	if (arm_decode_field (given, 18, 19) == 3)
 	{
 	  *undefined_code = UNDEF_SIZE_3;
-	  return TRUE;
+	  return true;
 	}
 	else
-	  return FALSE;
+	  return false;
 
     case MVE_VQNEG:
     case MVE_VQABS:
@@ -6361,18 +6361,18 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
       if (arm_decode_field (given, 18, 19) == 3)
 	{
 	  *undefined_code = UNDEF_SIZE_3;
-	  return TRUE;
+	  return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VREV16:
       if (arm_decode_field (given, 18, 19) == 0)
-	return FALSE;
+	return false;
       else
 	{
 	  *undefined_code = UNDEF_SIZE_NOT_0;
-	  return TRUE;
+	  return true;
 	}
 
     case MVE_VREV32:
@@ -6381,23 +6381,23 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
 	if ((size & 2) == 2)
 	  {
 	    *undefined_code = UNDEF_SIZE_2;
-	    return TRUE;
+	    return true;
 	  }
 	else
-	  return FALSE;
+	  return false;
       }
 
     case MVE_VREV64:
       if (arm_decode_field (given, 18, 19) != 3)
-	return FALSE;
+	return false;
       else
 	{
 	  *undefined_code = UNDEF_SIZE_3;
-	  return TRUE;
+	  return true;
 	}
 
     default:
-      return FALSE;
+      return false;
     }
 }
 
@@ -6405,7 +6405,7 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
    Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
    why this encoding is unpredictable.  */
 
-static bfd_boolean
+static bool
 is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
 		      enum mve_unpredictable *unpredictable_code)
 {
@@ -6419,10 +6419,10 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
 	  && (arm_decode_field (given, 5, 5) == 1))
 	{
 	  *unpredictable_code = UNPRED_FCA_0_FCB_1;
-	  return TRUE;
+	  return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VPT_VEC_T4:
     case MVE_VPT_VEC_T5:
@@ -6433,10 +6433,10 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
       if (arm_decode_field (given, 0, 3) == 0xd)
 	{
 	  *unpredictable_code = UNPRED_R13;
-	  return TRUE;
+	  return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VDUP:
       {
@@ -6444,15 +6444,15 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
 	if (gpr == 0xd)
 	  {
 	    *unpredictable_code = UNPRED_R13;
-	    return TRUE;
+	    return true;
 	  }
 	else if (gpr == 0xf)
 	  {
 	    *unpredictable_code = UNPRED_R15;
-	    return TRUE;
+	    return true;
 	  }
 
-	return FALSE;
+	return false;
       }
 
     case MVE_VQADD_T2:
@@ -6486,15 +6486,15 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
 	if (gpr == 0xd)
 	  {
 	    *unpredictable_code = UNPRED_R13;
-	    return TRUE;
+	    return true;
 	  }
 	else if (gpr == 0xf)
 	  {
 	    *unpredictable_code = UNPRED_R15;
-	    return TRUE;
+	    return true;
 	  }
 
-	return FALSE;
+	return false;
       }
 
     case MVE_VLD2:
@@ -6505,22 +6505,22 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
 	if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
 	  {
 	    *unpredictable_code = UNPRED_R13_AND_WB;
-	    return TRUE;
+	    return true;
 	  }
 
 	if (rn == 0xf)
 	  {
 	    *unpredictable_code = UNPRED_R15;
-	    return TRUE;
+	    return true;
 	  }
 
 	if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
 	  {
 	    *unpredictable_code = UNPRED_Q_GT_6;
-	    return TRUE;
+	    return true;
 	  }
 	else
-	  return FALSE;
+	  return false;
       }
 
     case MVE_VLD4:
@@ -6531,22 +6531,22 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
 	if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
 	  {
 	    *unpredictable_code = UNPRED_R13_AND_WB;
-	    return TRUE;
+	    return true;
 	  }
 
 	if (rn == 0xf)
 	  {
 	    *unpredictable_code = UNPRED_R15;
-	    return TRUE;
+	    return true;
 	  }
 
 	if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
 	  {
 	    *unpredictable_code = UNPRED_Q_GT_4;
-	    return TRUE;
+	    return true;
 	  }
 	else
-	  return FALSE;
+	  return false;
       }
 
     case MVE_VLDRB_T5:
@@ -6561,22 +6561,22 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
 	if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
 	  {
 	    *unpredictable_code = UNPRED_R13_AND_WB;
-	    return TRUE;
+	    return true;
 	  }
 	else if (rn == 0xf)
 	  {
 	    *unpredictable_code = UNPRED_R15;
-	    return TRUE;
+	    return true;
 	  }
 	else
-	  return FALSE;
+	  return false;
       }
 
     case MVE_VLDRB_GATHER_T1:
       if (arm_decode_field (given, 0, 0) == 1)
 	{
 	  *unpredictable_code = UNPRED_OS;
-	  return TRUE;
+	  return true;
 	}
 
       /*  fall through.  */
@@ -6591,16 +6591,16 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
 	if (qd == qm)
 	  {
 	    *unpredictable_code = UNPRED_Q_REGS_EQUAL;
-	    return TRUE;
+	    return true;
 	  }
 
 	if (arm_decode_field (given, 16, 19) == 0xf)
 	  {
 	    *unpredictable_code = UNPRED_R15;
-	    return TRUE;
+	    return true;
 	  }
 
-	return FALSE;
+	return false;
       }
 
     case MVE_VLDRW_GATHER_T5:
@@ -6612,25 +6612,25 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
 	if (qd == qm)
 	  {
 	    *unpredictable_code = UNPRED_Q_REGS_EQUAL;
-	    return TRUE;
+	    return true;
 	  }
 	else
-	  return FALSE;
+	  return false;
       }
 
     case MVE_VSTRB_SCATTER_T1:
       if (arm_decode_field (given, 16, 19) == 0xf)
 	{
 	  *unpredictable_code = UNPRED_R15;
-	  return TRUE;
+	  return true;
 	}
       else if (arm_decode_field (given, 0, 0) == 1)
 	{
 	  *unpredictable_code = UNPRED_OS;
-	  return TRUE;
+	  return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VSTRH_SCATTER_T2:
     case MVE_VSTRW_SCATTER_T3:
@@ -6638,10 +6638,10 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
       if (arm_decode_field (given, 16, 19) == 0xf)
 	{
 	  *unpredictable_code = UNPRED_R15;
-	  return TRUE;
+	  return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VMOV2_VEC_LANE_TO_GP:
     case MVE_VMOV2_GP_TO_VEC_LANE:
@@ -6654,20 +6654,20 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
 	if ((rt == 0xd) || (rt2 == 0xd))
 	  {
 	    *unpredictable_code = UNPRED_R13;
-	    return TRUE;
+	    return true;
 	  }
 	else if ((rt == 0xf) || (rt2 == 0xf))
 	  {
 	    *unpredictable_code = UNPRED_R15;
-	    return TRUE;
+	    return true;
 	  }
 	else if (rt == rt2)
 	  {
 	    *unpredictable_code = UNPRED_GP_REGS_EQUAL;
-	    return TRUE;
+	    return true;
 	  }
 
-	return FALSE;
+	return false;
       }
 
     case MVE_VMAXV:
@@ -6687,15 +6687,15 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
 	if (rda == 0xd)
 	  {
 	    *unpredictable_code = UNPRED_R13;
-	    return TRUE;
+	    return true;
 	  }
 	else if (rda == 0xf)
 	  {
 	    *unpredictable_code = UNPRED_R15;
-	    return TRUE;
+	    return true;
 	  }
 
-	return FALSE;
+	return false;
       }
 
     case MVE_VMULL_INT:
@@ -6713,13 +6713,13 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
 	    if ((Qd == Qn) || (Qd == Qm))
 	      {
 		*unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
-		return TRUE;
+		return true;
 	      }
 	    else
-	      return FALSE;
+	      return false;
 	  }
 	else
-	  return FALSE;
+	  return false;
       }
 
     case MVE_VCMUL_FP:
@@ -6738,13 +6738,13 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
 	    if ((Qd == Qn) || (Qd == Qm))
 	      {
 		*unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
-		return TRUE;
+		return true;
 	      }
 	    else
-	      return FALSE;
+	      return false;
 	  }
 	else
-	  return FALSE;
+	  return false;
       }
 
     case MVE_VQDMULL_T2:
@@ -6753,12 +6753,12 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
 	if (gpr == 0xd)
 	  {
 	    *unpredictable_code = UNPRED_R13;
-	    return TRUE;
+	    return true;
 	  }
 	else if (gpr == 0xf)
 	  {
 	    *unpredictable_code = UNPRED_R15;
-	    return TRUE;
+	    return true;
 	  }
 
 	if (arm_decode_field (given, 28, 28) == 1)
@@ -6770,13 +6770,13 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
 	    if (Qd == Qn)
 	      {
 		*unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
-		return TRUE;
+		return true;
 	      }
 	    else
-	      return FALSE;
+	      return false;
 	  }
 
-	return FALSE;
+	return false;
       }
 
     case MVE_VMLSLDAV:
@@ -6786,20 +6786,20 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
       if (arm_decode_field (given, 20, 22) == 6)
 	{
 	  *unpredictable_code = UNPRED_R13;
-	  return TRUE;
+	  return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VDWDUP:
     case MVE_VIWDUP:
       if (arm_decode_field (given, 1, 3) == 6)
 	{
 	  *unpredictable_code = UNPRED_R13;
-	  return TRUE;
+	  return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VCADD_VEC:
     case MVE_VHCADD:
@@ -6809,10 +6809,10 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
 	if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
 	  {
 	    *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
-	    return TRUE;
+	    return true;
 	  }
 	else
-	  return FALSE;
+	  return false;
       }
 
     case MVE_VCADD_FP:
@@ -6822,10 +6822,10 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
 	if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
 	  {
 	    *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
-	    return TRUE;
+	    return true;
 	  }
 	else
-	  return FALSE;
+	  return false;
       }
 
     case MVE_VCMLA_FP:
@@ -6843,13 +6843,13 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
 	    if ((Qda == Qn) || (Qda == Qm))
 	      {
 		*unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
-		return TRUE;
+		return true;
 	      }
 	    else
-	      return FALSE;
+	      return false;
 	  }
 	else
-	  return FALSE;
+	  return false;
 
       }
 
@@ -6857,10 +6857,10 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
       if (arm_decode_field (given, 16, 19) == 0xd)
 	{
 	  *unpredictable_code = UNPRED_R13;
-	  return TRUE;
+	  return true;
 	}
       else
-	return FALSE;
+	return false;
 
     case MVE_VREV64:
       {
@@ -6870,10 +6870,10 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
 	if (qd == qm)
 	  {
 	    *unpredictable_code = UNPRED_Q_REGS_EQUAL;
-	    return TRUE;
+	    return true;
 	  }
 	else
-	  return FALSE;
+	  return false;
       }
 
     case MVE_LSLL:
@@ -6893,19 +6893,19 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
 	if (gpr == 0xd)
 	  {
 	    *unpredictable_code = UNPRED_R13;
-	    return TRUE;
+	    return true;
 	  }
 	else if (gpr == 0xf)
 	  {
 	    *unpredictable_code = UNPRED_R15;
-	    return TRUE;
+	    return true;
 	  }
 
-	return FALSE;
+	return false;
       }
 
     default:
-      return FALSE;
+      return false;
     }
 }
 
@@ -8021,12 +8021,12 @@ print_vec_condition (struct disassemble_info *info, long given,
    Return TRUE if the instuction matched, FALSE if this is not a
    recognised coprocessor instruction.  */
 
-static bfd_boolean
+static bool
 print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
 			  bfd_vma pc,
 			  struct disassemble_info *info,
 			  long given,
-			  bfd_boolean thumb)
+			  bool thumb)
 {
   const struct sopcode32 *insn;
   void *stream = info->stream;
@@ -8045,7 +8045,7 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
   for (insn = opcodes; insn->assembler; insn++)
     {
       unsigned long u_reg = 16;
-      bfd_boolean is_unpredictable = FALSE;
+      bool is_unpredictable = false;
       signed long value_in_comment = 0;
       const char *c;
 
@@ -8122,7 +8122,7 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
 	  || insn->value == 0xfc000000) /* stc2  */
 	{
 	  if (cp_num == 9 || cp_num == 10 || cp_num == 11)
-	    is_unpredictable = TRUE;
+	    is_unpredictable = true;
 
 	  /* Armv8.1-M Mainline FP & MVE instructions.  */
 	  if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
@@ -8254,7 +8254,7 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
 
 		case 'C':
 		  {
-		    bfd_boolean single = ((given >> 8) & 1) == 0;
+		    bool single = ((given >> 8) & 1) == 0;
 		    char reg_prefix = single ? 's' : 'd';
 		    int Dreg = (given >> 22) & 0x1;
 		    int Vdreg = (given >> 12) & 0xf;
@@ -8279,12 +8279,12 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
 
 		case 'u':
 		  if (cond != COND_UNCOND)
-		    is_unpredictable = TRUE;
+		    is_unpredictable = true;
 
 		  /* Fall through.  */
 		case 'c':
 		  if (cond != COND_UNCOND && cp_num == 9)
-		    is_unpredictable = TRUE;
+		    is_unpredictable = true;
 
 		  /* Fall through.  */
 		case 'b':
@@ -8423,7 +8423,7 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
 		      {
 		      case 'R':
 			if (value == 15)
-			  is_unpredictable = TRUE;
+			  is_unpredictable = true;
 			/* Fall through.  */
 		      case 'r':
 			if (c[1] == 'u')
@@ -8432,7 +8432,7 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
 			    ++ c;
 
 			    if (u_reg == value)
-			      is_unpredictable = TRUE;
+			      is_unpredictable = true;
 			    u_reg = value;
 			  }
 			func (stream, "%s", arm_regnames[value]);
@@ -8755,26 +8755,26 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
       if (is_unpredictable)
 	func (stream, UNPREDICTABLE_INSTRUCTION);
 
-      return TRUE;
+      return true;
     }
-  return FALSE;
+  return false;
 }
 
-static bfd_boolean
+static bool
 print_insn_coprocessor (bfd_vma pc,
 			struct disassemble_info *info,
 			long given,
-			bfd_boolean thumb)
+			bool thumb)
 {
   return print_insn_coprocessor_1 (coprocessor_opcodes,
 				   pc, info, given, thumb);
 }
 
-static bfd_boolean
+static bool
 print_insn_generic_coprocessor (bfd_vma pc,
 				struct disassemble_info *info,
 				long given,
-				bfd_boolean thumb)
+				bool thumb)
 {
   return print_insn_coprocessor_1 (generic_coprocessor_opcodes,
 				   pc, info, given, thumb);
@@ -8846,7 +8846,7 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
 	  else
 	    {
 	      func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
-	      arm_decode_shift (given, func, stream, TRUE);
+	      arm_decode_shift (given, func, stream, true);
 	    }
 
 	  func (stream, "]%s",
@@ -8865,7 +8865,7 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
 	    {
 	      func (stream, "], %s",
 		    NEGATIVE_BIT_SET ? "-" : "");
-	      arm_decode_shift (given, func, stream, TRUE);
+	      arm_decode_shift (given, func, stream, true);
 	    }
 	}
       if (NEGATIVE_BIT_SET)
@@ -8879,8 +8879,8 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
 /* Print one cde instruction on INFO->STREAM.
    Return TRUE if the instuction matched, FALSE if this is not a
    recognised cde instruction.  */
-static bfd_boolean
-print_insn_cde (struct disassemble_info *info, long given, bfd_boolean thumb)
+static bool
+print_insn_cde (struct disassemble_info *info, long given, bool thumb)
 {
   const struct cdeopcode32 *insn;
   void *stream = info->stream;
@@ -8899,7 +8899,7 @@ print_insn_cde (struct disassemble_info *info, long given, bfd_boolean thumb)
 
       if ((given & insn->mask) == insn->value)
       {
-	bfd_boolean is_unpredictable = FALSE;
+	bool is_unpredictable = false;
 	const char *c;
 
 	for (c = insn->assembler; *c; c++)
@@ -8924,11 +8924,11 @@ print_insn_cde (struct disassemble_info *info, long given, bfd_boolean thumb)
 		{
 		  case 'S':
 		    if (value > 10)
-		      is_unpredictable = TRUE;
+		      is_unpredictable = true;
 		    /* Fall through.  */
 		  case 'R':
 		    if (value == 13)
-		      is_unpredictable = TRUE;
+		      is_unpredictable = true;
 		    /* Fall through.  */
 		  case 'r':
 		    func (stream, "%s", arm_regnames[value]);
@@ -8999,13 +8999,13 @@ print_insn_cde (struct disassemble_info *info, long given, bfd_boolean thumb)
       if (is_unpredictable)
 	func (stream, UNPREDICTABLE_INSTRUCTION);
 
-      return TRUE;
+      return true;
       }
     }
-    return FALSE;
+    return false;
   }
   else
-    return FALSE;
+    return false;
 }
 
 
@@ -9013,8 +9013,8 @@ print_insn_cde (struct disassemble_info *info, long given, bfd_boolean thumb)
    Return TRUE if the instuction matched, FALSE if this is not a
    recognised neon instruction.  */
 
-static bfd_boolean
-print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
+static bool
+print_insn_neon (struct disassemble_info *info, long given, bool thumb)
 {
   const struct opcode32 *insn;
   void *stream = info->stream;
@@ -9041,7 +9041,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
 	;
       /* vdup is also a valid neon instruction.  */
       else if ((given & 0xff900f5f) != 0xee800b10)
-	return FALSE;
+	return false;
     }
 
   for (insn = neon_opcodes; insn->assembler; insn++)
@@ -9087,7 +9087,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
       if ((given & cond_mask) == cond_value)
 	{
 	  signed long value_in_comment = 0;
-	  bfd_boolean is_unpredictable = FALSE;
+	  bool is_unpredictable = false;
 	  const char *c;
 
 	  for (c = insn->assembler; *c; c++)
@@ -9102,7 +9102,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
 
 		    case 'u':
 		      if (thumb && ifthen_state)
-			is_unpredictable = TRUE;
+			is_unpredictable = true;
 
 		      /* Fall through.  */
 		    case 'c':
@@ -9175,34 +9175,34 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
                             {
                               int amask = (1 << size) - 1;
                               if ((idx_align & (1 << size)) != 0)
-                                return FALSE;
+                                return false;
                               if (size > 0)
                                 {
                                   if ((idx_align & amask) == amask)
                                     align = 8 << size;
                                   else if ((idx_align & amask) != 0)
-                                    return FALSE;
+                                    return false;
                                 }
                               }
                             break;
 
                           case 2:
                             if (size == 2 && (idx_align & 2) != 0)
-                              return FALSE;
+                              return false;
                             align = (idx_align & 1) ? 16 << size : 0;
                             break;
 
                           case 3:
                             if ((size == 2 && (idx_align & 3) != 0)
                                 || (idx_align & 1) != 0)
-                              return FALSE;
+                              return false;
                             break;
 
                           case 4:
                             if (size == 2)
                               {
                                 if ((idx_align & 3) == 3)
-                                  return FALSE;
+                                  return false;
                                 align = (idx_align & 3) * 64;
                               }
                             else
@@ -9520,17 +9520,17 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
 	  if (is_unpredictable)
 	    func (stream, UNPREDICTABLE_INSTRUCTION);
 
-	  return TRUE;
+	  return true;
 	}
     }
-  return FALSE;
+  return false;
 }
 
 /* Print one mve instruction on INFO->STREAM.
    Return TRUE if the instuction matched, FALSE if this is not a
    recognised mve instruction.  */
 
-static bfd_boolean
+static bool
 print_insn_mve (struct disassemble_info *info, long given)
 {
   const struct mopcode32 *insn;
@@ -9543,8 +9543,8 @@ print_insn_mve (struct disassemble_info *info, long given)
 	  && !is_mve_encoding_conflict (given, insn->mve_op))
 	{
 	  signed long value_in_comment = 0;
-	  bfd_boolean is_unpredictable = FALSE;
-	  bfd_boolean is_undefined = FALSE;
+	  bool is_unpredictable = false;
+	  bool is_undefined = false;
 	  const char *c;
 	  enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
 	  enum mve_undefined undefined_cond = UNDEF_NONE;
@@ -9553,15 +9553,15 @@ print_insn_mve (struct disassemble_info *info, long given)
 	     There are a few exceptions; check for them.  */
 	  if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
 	    {
-	      is_unpredictable = TRUE;
+	      is_unpredictable = true;
 	      unpredictable_cond = UNPRED_IT_BLOCK;
 	    }
 	  else if (is_mve_unpredictable (given, insn->mve_op,
 					 &unpredictable_cond))
-	    is_unpredictable = TRUE;
+	    is_unpredictable = true;
 
 	  if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
-	    is_undefined = TRUE;
+	    is_undefined = true;
 
 	  /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
 	     i.e "VMOV Qd, Qm".  */
@@ -9715,7 +9715,7 @@ print_insn_mve (struct disassemble_info *info, long given)
 			  {
 			  case 'Z':
 			    if (value == 13)
-			      is_unpredictable = TRUE;
+			      is_unpredictable = true;
 			    else if (value == 15)
 			      func (stream, "zr");
 			    else
@@ -9733,7 +9733,7 @@ print_insn_mve (struct disassemble_info *info, long given)
 
 			  case 'S':
 			    if (value == 13 || value == 15)
-			      is_unpredictable = TRUE;
+			      is_unpredictable = true;
 			    else
 			      func (stream, "%s", arm_regnames[value]);
 			    break;
@@ -9894,10 +9894,10 @@ print_insn_mve (struct disassemble_info *info, long given)
 	  else if (vpt_block_state.in_vpt_block)
 	    update_vpt_block_state ();
 
-	  return TRUE;
+	  return true;
 	}
     }
-  return FALSE;
+  return false;
 }
 
 
@@ -9979,13 +9979,13 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
   fprintf_ftype func = info->fprintf_func;
   struct arm_private_data *private_data = info->private_data;
 
-  if (print_insn_coprocessor (pc, info, given, FALSE))
+  if (print_insn_coprocessor (pc, info, given, false))
     return;
 
-  if (print_insn_neon (info, given, FALSE))
+  if (print_insn_neon (info, given, false))
     return;
 
-  if (print_insn_generic_coprocessor (pc, info, given, FALSE))
+  if (print_insn_generic_coprocessor (pc, info, given, false))
     return;
 
   for (insn = arm_opcodes; insn->assembler; insn++)
@@ -10005,7 +10005,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 	{
 	  unsigned long u_reg = 16;
 	  unsigned long U_reg = 16;
-	  bfd_boolean is_unpredictable = FALSE;
+	  bool is_unpredictable = false;
 	  signed long value_in_comment = 0;
 	  const char *c;
 
@@ -10013,7 +10013,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 	    {
 	      if (*c == '%')
 		{
-		  bfd_boolean allow_unpredictable = FALSE;
+		  bool allow_unpredictable = false;
 
 		  switch (*++c)
 		    {
@@ -10032,7 +10032,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 		      break;
 
 		    case 'S':
-		      allow_unpredictable = TRUE;
+		      allow_unpredictable = true;
 		      /* Fall through.  */
 		    case 's':
                       if ((given & 0x004f0000) == 0x004f0000)
@@ -10058,7 +10058,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 			      func (stream, "[pc], #%s%d",
 				    NEGATIVE_BIT_SET ? "-" : "", (int) offset);
 			      if (! allow_unpredictable)
-				is_unpredictable = TRUE;
+				is_unpredictable = true;
 			    }
 			}
 		      else
@@ -10096,7 +10096,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 				  if (! allow_unpredictable
 				      && WRITEBACK_BIT_SET
 				      && ((given & 0xf) == ((given >> 12) & 0xf)))
-				    is_unpredictable = TRUE;
+				    is_unpredictable = true;
 				}
 
 			      func (stream, "]%s",
@@ -10125,7 +10125,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 				     destination of the load/store is unpredictable.  */
 				  if (! allow_unpredictable
 				      && (given & 0xf) == ((given >> 12) & 0xf))
-				    is_unpredictable = TRUE;
+				    is_unpredictable = true;
 				}
 
 			      if (! allow_unpredictable)
@@ -10137,7 +10137,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 				      /* Specifying the PC register as the post-indexed
 					 registers is also unpredictable.  */
 				      || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
-				    is_unpredictable = TRUE;
+				    is_unpredictable = true;
 				}
 			    }
 			}
@@ -10178,12 +10178,12 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 			    }
 			func (stream, "}");
 			if (! started)
-			  is_unpredictable = TRUE;
+			  is_unpredictable = true;
 		      }
 		      break;
 
 		    case 'q':
-		      arm_decode_shift (given, func, stream, FALSE);
+		      arm_decode_shift (given, func, stream, false);
 		      break;
 
 		    case 'o':
@@ -10208,7 +10208,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 			  value_in_comment = a;
 			}
 		      else
-			arm_decode_shift (given, func, stream, TRUE);
+			arm_decode_shift (given, func, stream, true);
 		      break;
 
 		    case 'p':
@@ -10224,7 +10224,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 						     arm_ext_v6))
 			    func (stream, "p");
 			  else
-			    is_unpredictable = TRUE;
+			    is_unpredictable = true;
 			}
 		      break;
 
@@ -10360,7 +10360,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 			  {
 			  case 'R':
 			    if (value == 15)
-			      is_unpredictable = TRUE;
+			      is_unpredictable = true;
 			    /* Fall through.  */
 			  case 'r':
 			  case 'T':
@@ -10374,7 +10374,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 				++ c;
 
 				if (u_reg == value)
-				  is_unpredictable = TRUE;
+				  is_unpredictable = true;
 				u_reg = value;
 			      }
 			    if (c[1] == 'U')
@@ -10383,7 +10383,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 				++ c;
 
 				if (U_reg == value)
-				  is_unpredictable = TRUE;
+				  is_unpredictable = true;
 				U_reg = value;
 			      }
 			    func (stream, "%s", arm_regnames[value]);
@@ -10836,28 +10836,28 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
   const struct opcode32 *insn;
   void *stream = info->stream;
   fprintf_ftype func = info->fprintf_func;
-  bfd_boolean is_mve = is_mve_architecture (info);
+  bool is_mve = is_mve_architecture (info);
 
-  if (print_insn_coprocessor (pc, info, given, TRUE))
+  if (print_insn_coprocessor (pc, info, given, true))
     return;
 
-  if (!is_mve && print_insn_neon (info, given, TRUE))
+  if (!is_mve && print_insn_neon (info, given, true))
     return;
 
   if (is_mve && print_insn_mve (info, given))
     return;
 
-  if (print_insn_cde (info, given, TRUE))
+  if (print_insn_cde (info, given, true))
     return;
 
-  if (print_insn_generic_coprocessor (pc, info, given, TRUE))
+  if (print_insn_generic_coprocessor (pc, info, given, true))
     return;
 
   for (insn = thumb32_opcodes; insn->assembler; insn++)
     if ((given & insn->mask) == insn->value)
       {
-	bfd_boolean is_clrm = FALSE;
-	bfd_boolean is_unpredictable = FALSE;
+	bool is_clrm = false;
+	bool is_unpredictable = false;
 	signed long value_in_comment = 0;
 	const char *c = insn->assembler;
 
@@ -11019,7 +11019,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
 		  unsigned int op  = (given & 0x00000f00) >> 8;
 		  unsigned int i12 = (given & 0x00000fff);
 		  unsigned int i8  = (given & 0x000000ff);
-		  bfd_boolean writeback = FALSE, postind = FALSE;
+		  bool writeback = false, postind = false;
 		  bfd_vma offset = 0;
 
 		  func (stream, "[%s", arm_regnames[Rn]);
@@ -11054,22 +11054,22 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
 
 		    case 0xF:  /* 8-bit + preindex with wb.  */
 		      offset = i8;
-		      writeback = TRUE;
+		      writeback = true;
 		      break;
 
 		    case 0xD:  /* 8-bit - preindex with wb.  */
 		      offset = -i8;
-		      writeback = TRUE;
+		      writeback = true;
 		      break;
 
 		    case 0xB:  /* 8-bit + postindex.  */
 		      offset = i8;
-		      postind = TRUE;
+		      postind = true;
 		      break;
 
 		    case 0x9:  /* 8-bit - postindex.  */
 		      offset = -i8;
-		      postind = TRUE;
+		      postind = true;
 		      break;
 
 		    default:
@@ -11153,7 +11153,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
 		break;
 
 	      case 'n':
-		is_clrm = TRUE;
+		is_clrm = true;
 		/* Fall through.  */
 	      case 'm':
 		{
@@ -11473,11 +11473,11 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
 
 		    case 'S':
 		      if (val == 13)
-			is_unpredictable = TRUE;
+			is_unpredictable = true;
 		      /* Fall through.  */
 		    case 'R':
 		      if (val == 15)
-			is_unpredictable = TRUE;
+			is_unpredictable = true;
 		      /* Fall through.  */
 		    case 'r':
 		      func (stream, "%s", arm_regnames[val]);
@@ -11577,14 +11577,14 @@ print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
    Also disallow private symbol, with __tagsym$$ prefix,
    from ARM RVCT toolchain being displayed.  */
 
-bfd_boolean
+bool
 arm_symbol_is_valid (asymbol * sym,
 		     struct disassemble_info * info ATTRIBUTE_UNUSED)
 {
   const char * name;
 
   if (sym == NULL)
-    return FALSE;
+    return false;
 
   name = bfd_asymbol_name (sym);
 
@@ -11657,7 +11657,7 @@ parse_arm_disassembler_options (const char *options)
   return;
 }
 
-static bfd_boolean
+static bool
 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
 			 enum map_type *map_symbol);
 
@@ -11667,7 +11667,7 @@ mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
 static void
 find_ifthen_state (bfd_vma pc,
 		   struct disassemble_info *info,
-		   bfd_boolean little)
+		   bool little)
 {
   unsigned char b[2];
   unsigned int insn;
@@ -11724,7 +11724,7 @@ find_ifthen_state (bfd_vma pc,
       if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
 	{
 	  enum map_type type = MAP_ARM;
-	  bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
+	  bool found = mapping_symbol_for_insn (addr, info, &type);
 
 	  if (!found || (found && type == MAP_THUMB))
 	    {
@@ -11763,10 +11763,10 @@ is_mapping_symbol (struct disassemble_info *info, int n,
       *map_type = ((name[1] == 'a') ? MAP_ARM
 		   : (name[1] == 't') ? MAP_THUMB
 		   : MAP_DATA);
-      return TRUE;
+      return true;
     }
 
-  return FALSE;
+  return false;
 }
 
 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
@@ -11779,7 +11779,7 @@ get_map_sym_type (struct disassemble_info *info,
 {
   /* If the symbol is in a different section, ignore it.  */
   if (info->section != NULL && info->section != info->symtab[n]->section)
-    return FALSE;
+    return false;
 
   return is_mapping_symbol (info, n, map_type);
 }
@@ -11797,7 +11797,7 @@ get_sym_code_type (struct disassemble_info *info,
 
   /* If the symbol is in a different section, ignore it.  */
   if (info->section != NULL && info->section != info->symtab[n]->section)
-    return FALSE;
+    return false;
 
   es = *(elf_symbol_type **)(info->symtab + n);
   type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
@@ -11810,10 +11810,10 @@ get_sym_code_type (struct disassemble_info *info,
 	*map_type = MAP_THUMB;
       else
 	*map_type = MAP_ARM;
-      return TRUE;
+      return true;
     }
 
-  return FALSE;
+  return false;
 }
 
 /* Search the mapping symbol state for instruction at pc.  This is only
@@ -11826,14 +11826,14 @@ get_sym_code_type (struct disassemble_info *info,
    Return TRUE if the mapping state can be determined, and map_symbol
    will be updated accordingly.  Otherwise, return FALSE.  */
 
-static bfd_boolean
+static bool
 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
 			 enum map_type *map_symbol)
 {
   bfd_vma addr, section_vma = 0;
   int n, last_sym = -1;
-  bfd_boolean found = FALSE;
-  bfd_boolean can_use_search_opt_p = FALSE;
+  bool found = false;
+  bool can_use_search_opt_p = false;
 
   /* Default to DATA.  A text section is required by the ABI to contain an
      INSN mapping symbol at the start.  A data section has no such
@@ -11850,7 +11850,7 @@ mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
 
   if (info->private_data == NULL
       || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
-    return FALSE;
+    return false;
 
   private_data = info->private_data;
 
@@ -11886,7 +11886,7 @@ mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
 	if (get_map_sym_type (info, n, &type))
 	  {
 	    last_sym = n;
-	    found = TRUE;
+	    found = true;
 	  }
       }
 
@@ -11914,7 +11914,7 @@ mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
 	    if (get_map_sym_type (info, n, &type))
 	      {
 		last_sym = n;
-		found = TRUE;
+		found = true;
 		break;
 	      }
 	  }
@@ -11931,7 +11931,7 @@ mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
       if (n >= 0 && get_sym_code_type (info, n, &type))
 	{
 	  last_sym = n;
-	  found = TRUE;
+	  found = true;
 	}
     }
 
@@ -12035,17 +12035,17 @@ select_arm_features (unsigned long mach,
    the relevant number of data bytes exist.  */
 
 static int
-print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
+print_insn (bfd_vma pc, struct disassemble_info *info, bool little)
 {
   unsigned char b[4];
   unsigned long given;
-  int           status;
-  int           is_thumb = FALSE;
-  int           is_data = FALSE;
-  int           little_code;
+  int status;
+  int is_thumb = false;
+  int is_data = false;
+  int little_code;
   unsigned int	size = 4;
-  void	 	(*printer) (bfd_vma, struct disassemble_info *, long);
-  bfd_boolean   found = FALSE;
+  void (*printer) (bfd_vma, struct disassemble_info *, long);
+  bool found = false;
   struct arm_private_data *private_data;
 
   /* Clear instruction information field.  */
@@ -12189,7 +12189,7 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
     }
 
   if (force_thumb)
-    is_thumb = TRUE;
+    is_thumb = true;
 
   if (is_data)
     info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
@@ -12310,13 +12310,13 @@ print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
       && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
     info->endian_code = BFD_ENDIAN_LITTLE;
 
-  return print_insn (pc, info, FALSE);
+  return print_insn (pc, info, false);
 }
 
 int
 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
 {
-  return print_insn (pc, info, TRUE);
+  return print_insn (pc, info, true);
 }
 
 const disasm_options_and_args_t *