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authorBarnaby Wilks <barnaby.wilks@arm.com>2019-08-05 12:43:38 +0100
committerNick Clifton <nickc@redhat.com>2019-08-05 12:43:38 +0100
commit23d188c74e7481bb0af3c42b84fc9cb0c94267e5 (patch)
tree4d88f17e87bc76e01a6924381ac4d1bfb9db37c0 /opcodes/arm-dis.c
parenta80cf5d88e028fa6a72b37fe50795e70bb6e3559 (diff)
downloadbinutils-gdb-23d188c74e7481bb0af3c42b84fc9cb0c94267e5.tar.gz
Removes support in the ARM assembler for the unsigned variants of the VQ(R)DMLAH and VQ(R)DMLASH MVE instructions.
Previously GAS would accept .u32, .u16 and .u8 suffixes to the VQ(R)DMLAH and VQ(R)DMLASH instructions, however the Armv8.1-M Mainline specification states that these functions only have signed variations (.s32, .s16 and .s8 suffixes). This is documented here: https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf?_ga=2.143079093.1892401233.1563295591-999473562.1560847439#page=1183 gas * config/tc-arm.c (do_mve_vqdmlah): Use N_S_32 macro. (do_neon_qrdmlah): Use N_S_32 macro. * testsuite/gas/arm/mve-vqdmlah-bad.d: New test. * testsuite/gas/arm/mve-vqdmlah-bad.l: New test. * testsuite/gas/arm/mve-vqdmlah-bad.s: New test. * testsuite/gas/arm/mve-vqdmlah.d: Remove unsigned instruction tests. * testsuite/gas/arm/mve-vqdmlah.s: Remove unsigned instruction tests. * testsuite/gas/arm/mve-vqdmlash-bad.d: New test. * testsuite/gas/arm/mve-vqdmlash-bad.l: New test. * testsuite/gas/arm/mve-vqdmlash-bad.s: New test. * testsuite/gas/arm/mve-vqdmlash.d: Remove unsigned instruction tests. * testsuite/gas/arm/mve-vqdmlash.s: Remove unsigned instruction tests. opcodes * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH instructions.
Diffstat (limited to 'opcodes/arm-dis.c')
-rw-r--r--opcodes/arm-dis.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index d1e6f03756d..033725dbad9 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -3019,25 +3019,25 @@ static const struct mopcode32 mve_opcodes[] =
/* Vector VQDMLAH. */
{ARM_FEATURE_COPROC (FPU_MVE),
MVE_VQDMLAH,
- 0xee000e60, 0xef811f70,
+ 0xee000e60, 0xff811f70,
"vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VQRDMLAH. */
{ARM_FEATURE_COPROC (FPU_MVE),
MVE_VQRDMLAH,
- 0xee000e40, 0xef811f70,
+ 0xee000e40, 0xff811f70,
"vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VQDMLASH. */
{ARM_FEATURE_COPROC (FPU_MVE),
MVE_VQDMLASH,
- 0xee001e60, 0xef811f70,
+ 0xee001e60, 0xff811f70,
"vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VQRDMLASH. */
{ARM_FEATURE_COPROC (FPU_MVE),
MVE_VQRDMLASH,
- 0xee001e40, 0xef811f70,
+ 0xee001e40, 0xff811f70,
"vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VQDMLSDH. */