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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2019-08-12 17:17:18 +0100 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2019-08-12 17:17:18 +0100 |
| commit | 08132bdd876fa1825810f90ecc25390dd4ded457 (patch) | |
| tree | 2a803c56103c18a109093c5be9176efb05eee657 /opcodes/arm-dis.c | |
| parent | 5312fe52e9ae6fd108f161a271315eb2821246eb (diff) | |
| download | binutils-gdb-08132bdd876fa1825810f90ecc25390dd4ded457.tar.gz | |
Modify the ARM encoding and decoding of SQRSHRL and UQRSHLL MVE instructions.
This is a change to the first published specifications [1][a] but since there is no hardware
out there that uses the old instructions we do not want to support the old variant.
This changes are done based on the latest published specifications [1][b].
[1] https://developer.arm.com/architectures/cpu-architecture/m-profile/docs/ddi0553/latest/armv81-m-architecture-reference-manual
[a] version bf
[b] version bh
gas * config/tc-arm.c (enum operand_parse_code): Add the entry OP_I48_I64.
(po_imm1_or_imm2_or_fail): Marco to check the immediate is either of
48 or 64.
(parse_operands): Add case OP_I48_I64.
(do_mve_scalar_shift1): Add function to encode the MVE shift
instructions with 4 arguments.
* testsuite/gas/arm/mve-shift-bad.l: Modify.
* testsuite/gas/arm/mve-shift-bad.s: Likewise.
* testsuite/gas/arm/mve-shift.d: Likewise.
* testsuite/gas/arm/mve-shift.s: Likewise.
opcodes * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
cases MVE_SQRSHRL and MVE_UQRSHLL.
(print_insn_mve): Add case for specifier 'k' to check
specific bit of the instruction.
Diffstat (limited to 'opcodes/arm-dis.c')
| -rw-r--r-- | opcodes/arm-dis.c | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 033725dbad9..50d1306c19d 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -2073,6 +2073,7 @@ static const struct opcode32 neon_opcodes[] = %u print 'U' (unsigned) or 'S' for various mve instructions %i print MVE predicate(s) for vpt and vpst %j print a 5-bit immediate from hw2[14:12,7:6] + %k print 48 if the 7th position bit is set else print 64. %m print rounding mode for vcvt and vrint %n print vector comparison code for predicated instruction %s print size for various vcvt instructions @@ -3373,8 +3374,8 @@ static const struct mopcode32 mve_opcodes[] = {ARM_FEATURE_COPROC (FPU_MVE), MVE_SQRSHRL, - 0xea51012d, 0xfff101ff, - "sqrshrl%c\t%17-19l, %9-11h, %12-15S"}, + 0xea51012d, 0xfff1017f, + "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"}, {ARM_FEATURE_COPROC (FPU_MVE), MVE_SQRSHR, @@ -3403,8 +3404,8 @@ static const struct mopcode32 mve_opcodes[] = {ARM_FEATURE_COPROC (FPU_MVE), MVE_UQRSHLL, - 0xea51010d, 0xfff101ff, - "uqrshll%c\t%17-19l, %9-11h, %12-15S"}, + 0xea51010d, 0xfff1017f, + "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"}, {ARM_FEATURE_COPROC (FPU_MVE), MVE_UQRSHL, @@ -9254,6 +9255,11 @@ print_insn_mve (struct disassemble_info *info, long given) } break; + case 'k': + func (stream, "#%u", + (arm_decode_field (given, 7, 7) == 0) ? 64 : 48); + break; + case 'n': print_vec_condition (info, given, insn->mve_op); break; |