diff options
| author | Sudakshina Das <sudi.das@arm.com> | 2018-11-12 12:52:55 +0000 |
|---|---|---|
| committer | Sudakshina Das <sudi.das@arm.com> | 2018-11-12 12:59:22 +0000 |
| commit | 193614f2b908c2b55c188cb14c3ef78993ff85b0 (patch) | |
| tree | 4a762f9576281e236a28853ba62089abdd1b43e8 /opcodes/aarch64-opc.h | |
| parent | 73b605ec3f546ff5a1c343ae02e6322aaa451bcf (diff) | |
| download | binutils-gdb-193614f2b908c2b55c188cb14c3ef78993ff85b0.tar.gz | |
[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Tag generation instructions from
MTE. These are the following instructions added in this patch:
- IRG <Xd|SP>, <Xn|SP>{, Xm}
- ADDG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2>
- SUBG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2>
- GMI <Xd>, <Xn|SP>, <Xm>
where
<Xd|SP> : Is the 64-bit destination GPR or Stack pointer.
<Xn|SP> : Is the 64-bit source GPR or Stack pointer.
<uimm6> : Is the unsigned immediate, a multiple of 16
in the range 0 to 1008.
<uimm4> : Is the unsigned immediate, in the range 0 to 15.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
(OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
* aarch64-opc.c (fields): Add entry for imm4_3.
(operand_general_constraint_met_p): Add cases for
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
(aarch64_print_operand): Likewise.
* aarch64-tbl.h (QL_ADDG): New.
(aarch64_opcode_table): Add addg, subg, irg and gmi.
(AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
* aarch64-asm.c (aarch64_ins_imm): Add case for
operand_need_shift_by_four.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add switch case for
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: New.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.d: Likewise.
Diffstat (limited to 'opcodes/aarch64-opc.h')
| -rw-r--r-- | opcodes/aarch64-opc.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index 79227883d80..3d1765ba95b 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -70,6 +70,7 @@ enum aarch64_field_kind FLD_imm6_2, FLD_imm4, FLD_imm4_2, + FLD_imm4_3, FLD_imm5, FLD_imm7, FLD_imm8, @@ -199,6 +200,10 @@ verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma, #define OPD_F_OD_MASK 0x000000e0 /* Operand-dependent data. */ #define OPD_F_OD_LSB 5 #define OPD_F_NO_ZR 0x00000100 /* ZR index not allowed. */ +#define OPD_F_SHIFT_BY_4 0x00000200 /* Need to left shift the field + value by 4 to get the value + of an immediate operand. */ + /* Register flags. */ @@ -253,6 +258,12 @@ operand_need_shift_by_two (const aarch64_operand *operand) } static inline bfd_boolean +operand_need_shift_by_four (const aarch64_operand *operand) +{ + return (operand->flags & OPD_F_SHIFT_BY_4) ? TRUE : FALSE; +} + +static inline bfd_boolean operand_maybe_stack_pointer (const aarch64_operand *operand) { return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE; |